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authorNick Kossifidis <mick@madwifi.org>2008-04-16 11:49:02 -0400
committerJohn W. Linville <linville@tuxdriver.com>2008-04-16 16:00:03 -0400
commit194828a292db3cf421ae7f82232f2fc655fbbc3c (patch)
tree1525b49d4db5b979d8cc4058207b855a4386fc28 /drivers/net
parent136bfc798fe5378c7c1b5f5294abcfd1428438b3 (diff)
ath5k: Misc fixes/cleanups
*Handle MIB interrupts and pass low level stats to mac80211 *Add Power On Self Test function *Update to match recent dumps *Let RF2425 attach so we can further test it *Remove unused files regdom.c and regdom.h base.c Changes-licensed-under: 3-clause-BSD rest Changes-licensed-under: ISC Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/wireless/ath5k/ath5k.h10
-rw-r--r--drivers/net/wireless/ath5k/base.c13
-rw-r--r--drivers/net/wireless/ath5k/hw.c138
-rw-r--r--drivers/net/wireless/ath5k/regdom.c121
-rw-r--r--drivers/net/wireless/ath5k/regdom.h500
5 files changed, 139 insertions, 643 deletions
diff --git a/drivers/net/wireless/ath5k/ath5k.h b/drivers/net/wireless/ath5k/ath5k.h
index d0d70b32e78b..ba35c30d203c 100644
--- a/drivers/net/wireless/ath5k/ath5k.h
+++ b/drivers/net/wireless/ath5k/ath5k.h
@@ -450,14 +450,6 @@ struct ath5k_rx_status {
450#define AR5K_RXKEYIX_INVALID ((u8) - 1) 450#define AR5K_RXKEYIX_INVALID ((u8) - 1)
451#define AR5K_TXKEYIX_INVALID ((u32) - 1) 451#define AR5K_TXKEYIX_INVALID ((u32) - 1)
452 452
453struct ath5k_mib_stats {
454 u32 ackrcv_bad;
455 u32 rts_bad;
456 u32 rts_good;
457 u32 fcs_bad;
458 u32 beacons;
459};
460
461 453
462/**************************\ 454/**************************\
463 BEACON TIMERS DEFINITIONS 455 BEACON TIMERS DEFINITIONS
@@ -1070,6 +1062,7 @@ extern int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
1070extern bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah); 1062extern bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1071extern int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask); 1063extern int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
1072extern enum ath5k_int ath5k_hw_set_intr(struct ath5k_hw *ah, enum ath5k_int new_mask); 1064extern enum ath5k_int ath5k_hw_set_intr(struct ath5k_hw *ah, enum ath5k_int new_mask);
1065extern void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, struct ieee80211_low_level_stats *stats);
1073/* EEPROM access functions */ 1066/* EEPROM access functions */
1074extern int ath5k_hw_set_regdomain(struct ath5k_hw *ah, u16 regdomain); 1067extern int ath5k_hw_set_regdomain(struct ath5k_hw *ah, u16 regdomain);
1075/* Protocol Control Unit Functions */ 1068/* Protocol Control Unit Functions */
@@ -1098,7 +1091,6 @@ extern int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah, const struct ath5k_be
1098extern void ath5k_hw_reset_beacon(struct ath5k_hw *ah); 1091extern void ath5k_hw_reset_beacon(struct ath5k_hw *ah);
1099extern int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr); 1092extern int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr);
1100#endif 1093#endif
1101extern void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, struct ath5k_mib_stats *statistics);
1102/* ACK bit rate */ 1094/* ACK bit rate */
1103void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high); 1095void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high);
1104/* ACK/CTS Timeouts */ 1096/* ACK/CTS Timeouts */
diff --git a/drivers/net/wireless/ath5k/base.c b/drivers/net/wireless/ath5k/base.c
index dfd202ddcff3..e18305b781c9 100644
--- a/drivers/net/wireless/ath5k/base.c
+++ b/drivers/net/wireless/ath5k/base.c
@@ -2342,7 +2342,8 @@ ath5k_init(struct ath5k_softc *sc)
2342 * Enable interrupts. 2342 * Enable interrupts.
2343 */ 2343 */
2344 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL | 2344 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
2345 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL; 2345 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL |
2346 AR5K_INT_MIB;
2346 2347
2347 ath5k_hw_set_intr(sc->ah, sc->imask); 2348 ath5k_hw_set_intr(sc->ah, sc->imask);
2348 /* Set ack to be sent at low bit-rates */ 2349 /* Set ack to be sent at low bit-rates */
@@ -2522,7 +2523,11 @@ ath5k_intr(int irq, void *dev_id)
2522 if (status & AR5K_INT_BMISS) { 2523 if (status & AR5K_INT_BMISS) {
2523 } 2524 }
2524 if (status & AR5K_INT_MIB) { 2525 if (status & AR5K_INT_MIB) {
2525 /* TODO */ 2526 /*
2527 * These stats are also used for ANI i think
2528 * so how about updating them more often ?
2529 */
2530 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2526 } 2531 }
2527 } 2532 }
2528 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0); 2533 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
@@ -3015,6 +3020,10 @@ ath5k_get_stats(struct ieee80211_hw *hw,
3015 struct ieee80211_low_level_stats *stats) 3020 struct ieee80211_low_level_stats *stats)
3016{ 3021{
3017 struct ath5k_softc *sc = hw->priv; 3022 struct ath5k_softc *sc = hw->priv;
3023 struct ath5k_hw *ah = sc->ah;
3024
3025 /* Force update */
3026 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3018 3027
3019 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats)); 3028 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3020 3029
diff --git a/drivers/net/wireless/ath5k/hw.c b/drivers/net/wireless/ath5k/hw.c
index 9e16bc09f1fd..87e782291a01 100644
--- a/drivers/net/wireless/ath5k/hw.c
+++ b/drivers/net/wireless/ath5k/hw.c
@@ -120,11 +120,69 @@ int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
120\***************************************/ 120\***************************************/
121 121
122/* 122/*
123 * Power On Self Test helper function
124 */
125static int ath5k_hw_post(struct ath5k_hw *ah)
126{
127
128 int i, c;
129 u16 cur_reg;
130 u16 regs[2] = {AR5K_STA_ID0, AR5K_PHY(8)};
131 u32 var_pattern;
132 u32 static_pattern[4] = {
133 0x55555555, 0xaaaaaaaa,
134 0x66666666, 0x99999999
135 };
136 u32 init_val;
137 u32 cur_val;
138
139 for (c = 0; c < 2; c++) {
140
141 cur_reg = regs[c];
142 init_val = ath5k_hw_reg_read(ah, cur_reg);
143
144 for (i = 0; i < 256; i++) {
145 var_pattern = i << 16 | i;
146 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
147 cur_val = ath5k_hw_reg_read(ah, cur_reg);
148
149 if (cur_val != var_pattern) {
150 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
151 return -EAGAIN;
152 }
153
154 /* Found on ndiswrapper dumps */
155 var_pattern = 0x0039080f;
156 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
157 }
158
159 for (i = 0; i < 4; i++) {
160 var_pattern = static_pattern[i];
161 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
162 cur_val = ath5k_hw_reg_read(ah, cur_reg);
163
164 if (cur_val != var_pattern) {
165 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
166 return -EAGAIN;
167 }
168
169 /* Found on ndiswrapper dumps */
170 var_pattern = 0x003b080f;
171 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
172 }
173 }
174
175 return 0;
176
177}
178
179/*
123 * Check if the device is supported and initialize the needed structs 180 * Check if the device is supported and initialize the needed structs
124 */ 181 */
125struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version) 182struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
126{ 183{
127 struct ath5k_hw *ah; 184 struct ath5k_hw *ah;
185 struct pci_dev *pdev = sc->pdev;
128 u8 mac[ETH_ALEN]; 186 u8 mac[ETH_ALEN];
129 int ret; 187 int ret;
130 u32 srev; 188 u32 srev;
@@ -204,10 +262,13 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
204 CHANNEL_2GHZ); 262 CHANNEL_2GHZ);
205 263
206 /* Return on unsuported chips (unsupported eeprom etc) */ 264 /* Return on unsuported chips (unsupported eeprom etc) */
207 if (srev >= AR5K_SREV_VER_AR5416) { 265 if ((srev >= AR5K_SREV_VER_AR5416) &&
266 (srev < AR5K_SREV_VER_AR2425)) {
208 ATH5K_ERR(sc, "Device not yet supported.\n"); 267 ATH5K_ERR(sc, "Device not yet supported.\n");
209 ret = -ENODEV; 268 ret = -ENODEV;
210 goto err_free; 269 goto err_free;
270 } else if (srev == AR5K_SREV_VER_AR2425) {
271 ATH5K_WARN(sc, "Support for RF2425 is under development.\n");
211 } 272 }
212 273
213 /* Identify single chip solutions */ 274 /* Identify single chip solutions */
@@ -251,8 +312,13 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
251 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5424; 312 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5424;
252 else 313 else
253 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112A; 314 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112A;
254 315 /*
255 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5133) { 316 * Register returns 0x4 for radio revision
317 * so ath5k_hw_radio_revision doesn't parse the value
318 * correctly. For now we are based on mac's srev to
319 * identify RF2425 radio.
320 */
321 } else if (srev == AR5K_SREV_VER_AR2425) {
256 ah->ah_radio = AR5K_RF2425; 322 ah->ah_radio = AR5K_RF2425;
257 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112; 323 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112;
258 } 324 }
@@ -260,6 +326,44 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
260 ah->ah_phy = AR5K_PHY(0); 326 ah->ah_phy = AR5K_PHY(0);
261 327
262 /* 328 /*
329 * Identify AR5212-based PCI-E cards
330 * And write some initial settings.
331 *
332 * (doing a "strings" on ndis driver
333 * -ar5211.sys- reveals the following
334 * pci-e related functions:
335 *
336 * pcieClockReq
337 * pcieRxErrNotify
338 * pcieL1SKPEnable
339 * pcieAspm
340 * pcieDisableAspmOnRfWake
341 * pciePowerSaveEnable
342 *
343 * I guess these point to ClockReq but
344 * i'm not sure.)
345 */
346 if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) {
347 ath5k_hw_reg_write(ah, 0x9248fc00, 0x4080);
348 ath5k_hw_reg_write(ah, 0x24924924, 0x4080);
349 ath5k_hw_reg_write(ah, 0x28000039, 0x4080);
350 ath5k_hw_reg_write(ah, 0x53160824, 0x4080);
351 ath5k_hw_reg_write(ah, 0xe5980579, 0x4080);
352 ath5k_hw_reg_write(ah, 0x001defff, 0x4080);
353 ath5k_hw_reg_write(ah, 0x1aaabe40, 0x4080);
354 ath5k_hw_reg_write(ah, 0xbe105554, 0x4080);
355 ath5k_hw_reg_write(ah, 0x000e3007, 0x4080);
356 ath5k_hw_reg_write(ah, 0x00000000, 0x4084);
357 }
358
359 /*
360 * POST
361 */
362 ret = ath5k_hw_post(ah);
363 if (ret)
364 goto err_free;
365
366 /*
263 * Get card capabilities, values, ... 367 * Get card capabilities, values, ...
264 */ 368 */
265 369
@@ -2851,15 +2955,19 @@ int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr)
2851 * Update mib counters (statistics) 2955 * Update mib counters (statistics)
2852 */ 2956 */
2853void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, 2957void ath5k_hw_update_mib_counters(struct ath5k_hw *ah,
2854 struct ath5k_mib_stats *statistics) 2958 struct ieee80211_low_level_stats *stats)
2855{ 2959{
2856 ATH5K_TRACE(ah->ah_sc); 2960 ATH5K_TRACE(ah->ah_sc);
2961
2857 /* Read-And-Clear */ 2962 /* Read-And-Clear */
2858 statistics->ackrcv_bad += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL); 2963 stats->dot11ACKFailureCount += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
2859 statistics->rts_bad += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL); 2964 stats->dot11RTSFailureCount += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
2860 statistics->rts_good += ath5k_hw_reg_read(ah, AR5K_RTS_OK); 2965 stats->dot11RTSSuccessCount += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
2861 statistics->fcs_bad += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL); 2966 stats->dot11FCSErrorCount += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
2862 statistics->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT); 2967
2968 /* XXX: Should we use this to track beacon count ?
2969 * -we read it anyway to clear the register */
2970 ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
2863 2971
2864 /* Reset profile count registers on 5212*/ 2972 /* Reset profile count registers on 5212*/
2865 if (ah->ah_version == AR5K_AR5212) { 2973 if (ah->ah_version == AR5K_AR5212) {
@@ -2960,8 +3068,16 @@ int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry)
2960 for (i = 0; i < AR5K_KEYCACHE_SIZE; i++) 3068 for (i = 0; i < AR5K_KEYCACHE_SIZE; i++)
2961 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i)); 3069 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i));
2962 3070
2963 /* Set NULL encryption on non-5210*/ 3071 /*
2964 if (ah->ah_version != AR5K_AR5210) 3072 * Set NULL encryption on AR5212+
3073 *
3074 * Note: AR5K_KEYTABLE_TYPE -> AR5K_KEYTABLE_OFF(entry, 5)
3075 * AR5K_KEYTABLE_TYPE_NULL -> 0x00000007
3076 *
3077 * Note2: Windows driver (ndiswrapper) sets this to
3078 * 0x00000714 instead of 0x00000007
3079 */
3080 if (ah->ah_version > AR5K_AR5211)
2965 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL, 3081 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
2966 AR5K_KEYTABLE_TYPE(entry)); 3082 AR5K_KEYTABLE_TYPE(entry));
2967 3083
diff --git a/drivers/net/wireless/ath5k/regdom.c b/drivers/net/wireless/ath5k/regdom.c
deleted file mode 100644
index e851957dacfd..000000000000
--- a/drivers/net/wireless/ath5k/regdom.c
+++ /dev/null
@@ -1,121 +0,0 @@
1/*
2 * Copyright (c) 2004, 2005 Reyk Floeter <reyk@vantronix.net>
3 *
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17/*
18 * Basic regulation domain extensions for the IEEE 802.11 stack
19 */
20
21#include <linux/kernel.h>
22#include <linux/string.h>
23
24#include "regdom.h"
25
26static const struct ath5k_regdommap {
27 enum ath5k_regdom dmn;
28 enum ath5k_regdom dmn5;
29 enum ath5k_regdom dmn2;
30} r_map[] = {
31 { DMN_DEFAULT, DMN_DEBUG, DMN_DEBUG },
32 { DMN_NULL_WORLD, DMN_NULL, DMN_WORLD },
33 { DMN_NULL_ETSIB, DMN_NULL, DMN_ETSIB },
34 { DMN_NULL_ETSIC, DMN_NULL, DMN_ETSIC },
35 { DMN_FCC1_FCCA, DMN_FCC1, DMN_FCCA },
36 { DMN_FCC1_WORLD, DMN_FCC1, DMN_WORLD },
37 { DMN_FCC2_FCCA, DMN_FCC2, DMN_FCCA },
38 { DMN_FCC2_WORLD, DMN_FCC2, DMN_WORLD },
39 { DMN_FCC2_ETSIC, DMN_FCC2, DMN_ETSIC },
40 { DMN_FRANCE_NULL, DMN_ETSI3, DMN_ETSI3 },
41 { DMN_FCC3_FCCA, DMN_FCC3, DMN_WORLD },
42 { DMN_ETSI1_WORLD, DMN_ETSI1, DMN_WORLD },
43 { DMN_ETSI3_ETSIA, DMN_ETSI3, DMN_WORLD },
44 { DMN_ETSI2_WORLD, DMN_ETSI2, DMN_WORLD },
45 { DMN_ETSI3_WORLD, DMN_ETSI3, DMN_WORLD },
46 { DMN_ETSI4_WORLD, DMN_ETSI4, DMN_WORLD },
47 { DMN_ETSI4_ETSIC, DMN_ETSI4, DMN_ETSIC },
48 { DMN_ETSI5_WORLD, DMN_ETSI5, DMN_WORLD },
49 { DMN_ETSI6_WORLD, DMN_ETSI6, DMN_WORLD },
50 { DMN_ETSI_NULL, DMN_ETSI1, DMN_ETSI1 },
51 { DMN_MKK1_MKKA, DMN_MKK1, DMN_MKKA },
52 { DMN_MKK1_MKKB, DMN_MKK1, DMN_MKKA },
53 { DMN_APL4_WORLD, DMN_APL4, DMN_WORLD },
54 { DMN_MKK2_MKKA, DMN_MKK2, DMN_MKKA },
55 { DMN_APL_NULL, DMN_APL1, DMN_NULL },
56 { DMN_APL2_WORLD, DMN_APL2, DMN_WORLD },
57 { DMN_APL2_APLC, DMN_APL2, DMN_WORLD },
58 { DMN_APL3_WORLD, DMN_APL3, DMN_WORLD },
59 { DMN_MKK1_FCCA, DMN_MKK1, DMN_FCCA },
60 { DMN_APL2_APLD, DMN_APL2, DMN_APLD },
61 { DMN_MKK1_MKKA1, DMN_MKK1, DMN_MKKA },
62 { DMN_MKK1_MKKA2, DMN_MKK1, DMN_MKKA },
63 { DMN_APL1_WORLD, DMN_APL1, DMN_WORLD },
64 { DMN_APL1_FCCA, DMN_APL1, DMN_FCCA },
65 { DMN_APL1_APLA, DMN_APL1, DMN_WORLD },
66 { DMN_APL1_ETSIC, DMN_APL1, DMN_ETSIC },
67 { DMN_APL2_ETSIC, DMN_APL2, DMN_ETSIC },
68 { DMN_APL5_WORLD, DMN_APL5, DMN_WORLD },
69 { DMN_WOR0_WORLD, DMN_WORLD, DMN_WORLD },
70 { DMN_WOR1_WORLD, DMN_WORLD, DMN_WORLD },
71 { DMN_WOR2_WORLD, DMN_WORLD, DMN_WORLD },
72 { DMN_WOR3_WORLD, DMN_WORLD, DMN_WORLD },
73 { DMN_WOR4_WORLD, DMN_WORLD, DMN_WORLD },
74 { DMN_WOR5_ETSIC, DMN_WORLD, DMN_WORLD },
75 { DMN_WOR01_WORLD, DMN_WORLD, DMN_WORLD },
76 { DMN_WOR02_WORLD, DMN_WORLD, DMN_WORLD },
77 { DMN_EU1_WORLD, DMN_ETSI1, DMN_WORLD },
78 { DMN_WOR9_WORLD, DMN_WORLD, DMN_WORLD },
79 { DMN_WORA_WORLD, DMN_WORLD, DMN_WORLD },
80};
81
82enum ath5k_regdom ath5k_regdom2flag(enum ath5k_regdom dmn, u16 mhz)
83{
84 unsigned int i;
85
86 for (i = 0; i < ARRAY_SIZE(r_map); i++) {
87 if (r_map[i].dmn == dmn) {
88 if (mhz >= 2000 && mhz <= 3000)
89 return r_map[i].dmn2;
90 if (mhz >= IEEE80211_CHANNELS_5GHZ_MIN &&
91 mhz <= IEEE80211_CHANNELS_5GHZ_MAX)
92 return r_map[i].dmn5;
93 }
94 }
95
96 return DMN_DEBUG;
97}
98
99u16 ath5k_regdom_from_ieee(enum ath5k_regdom ieee)
100{
101 u32 regdomain = (u32)ieee;
102
103 /*
104 * Use the default regulation domain if the value is empty
105 * or not supported by the net80211 regulation code.
106 */
107 if (ath5k_regdom2flag(regdomain, IEEE80211_CHANNELS_5GHZ_MIN) ==
108 DMN_DEBUG)
109 return (u16)AR5K_TUNE_REGDOMAIN;
110
111 /* It is supported, just return the value */
112 return regdomain;
113}
114
115enum ath5k_regdom ath5k_regdom_to_ieee(u16 regdomain)
116{
117 enum ath5k_regdom ieee = (enum ath5k_regdom)regdomain;
118
119 return ieee;
120}
121
diff --git a/drivers/net/wireless/ath5k/regdom.h b/drivers/net/wireless/ath5k/regdom.h
deleted file mode 100644
index f7d3c66e594e..000000000000
--- a/drivers/net/wireless/ath5k/regdom.h
+++ /dev/null
@@ -1,500 +0,0 @@
1/*
2 * Copyright (c) 2004, 2005 Reyk Floeter <reyk@openbsd.org>
3 *
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _IEEE80211_REGDOMAIN_H_
18#define _IEEE80211_REGDOMAIN_H_
19
20#include <linux/types.h>
21
22/* Default regulation domain if stored value EEPROM value is invalid */
23#define AR5K_TUNE_REGDOMAIN DMN_FCC2_FCCA /* Canada */
24#define AR5K_TUNE_CTRY CTRY_DEFAULT
25
26
27enum ath5k_regdom {
28 DMN_DEFAULT = 0x00,
29 DMN_NULL_WORLD = 0x03,
30 DMN_NULL_ETSIB = 0x07,
31 DMN_NULL_ETSIC = 0x08,
32 DMN_FCC1_FCCA = 0x10,
33 DMN_FCC1_WORLD = 0x11,
34 DMN_FCC2_FCCA = 0x20,
35 DMN_FCC2_WORLD = 0x21,
36 DMN_FCC2_ETSIC = 0x22,
37 DMN_FRANCE_NULL = 0x31,
38 DMN_FCC3_FCCA = 0x3A,
39 DMN_ETSI1_WORLD = 0x37,
40 DMN_ETSI3_ETSIA = 0x32,
41 DMN_ETSI2_WORLD = 0x35,
42 DMN_ETSI3_WORLD = 0x36,
43 DMN_ETSI4_WORLD = 0x30,
44 DMN_ETSI4_ETSIC = 0x38,
45 DMN_ETSI5_WORLD = 0x39,
46 DMN_ETSI6_WORLD = 0x34,
47 DMN_ETSI_NULL = 0x33,
48 DMN_MKK1_MKKA = 0x40,
49 DMN_MKK1_MKKB = 0x41,
50 DMN_APL4_WORLD = 0x42,
51 DMN_MKK2_MKKA = 0x43,
52 DMN_APL_NULL = 0x44,
53 DMN_APL2_WORLD = 0x45,
54 DMN_APL2_APLC = 0x46,
55 DMN_APL3_WORLD = 0x47,
56 DMN_MKK1_FCCA = 0x48,
57 DMN_APL2_APLD = 0x49,
58 DMN_MKK1_MKKA1 = 0x4A,
59 DMN_MKK1_MKKA2 = 0x4B,
60 DMN_APL1_WORLD = 0x52,
61 DMN_APL1_FCCA = 0x53,
62 DMN_APL1_APLA = 0x54,
63 DMN_APL1_ETSIC = 0x55,
64 DMN_APL2_ETSIC = 0x56,
65 DMN_APL5_WORLD = 0x58,
66 DMN_WOR0_WORLD = 0x60,
67 DMN_WOR1_WORLD = 0x61,
68 DMN_WOR2_WORLD = 0x62,
69 DMN_WOR3_WORLD = 0x63,
70 DMN_WOR4_WORLD = 0x64,
71 DMN_WOR5_ETSIC = 0x65,
72 DMN_WOR01_WORLD = 0x66,
73 DMN_WOR02_WORLD = 0x67,
74 DMN_EU1_WORLD = 0x68,
75 DMN_WOR9_WORLD = 0x69,
76 DMN_WORA_WORLD = 0x6A,
77
78 DMN_APL1 = 0xf0000001,
79 DMN_APL2 = 0xf0000002,
80 DMN_APL3 = 0xf0000004,
81 DMN_APL4 = 0xf0000008,
82 DMN_APL5 = 0xf0000010,
83 DMN_ETSI1 = 0xf0000020,
84 DMN_ETSI2 = 0xf0000040,
85 DMN_ETSI3 = 0xf0000080,
86 DMN_ETSI4 = 0xf0000100,
87 DMN_ETSI5 = 0xf0000200,
88 DMN_ETSI6 = 0xf0000400,
89 DMN_ETSIA = 0xf0000800,
90 DMN_ETSIB = 0xf0001000,
91 DMN_ETSIC = 0xf0002000,
92 DMN_FCC1 = 0xf0004000,
93 DMN_FCC2 = 0xf0008000,
94 DMN_FCC3 = 0xf0010000,
95 DMN_FCCA = 0xf0020000,
96 DMN_APLD = 0xf0040000,
97 DMN_MKK1 = 0xf0080000,
98 DMN_MKK2 = 0xf0100000,
99 DMN_MKKA = 0xf0200000,
100 DMN_NULL = 0xf0400000,
101 DMN_WORLD = 0xf0800000,
102 DMN_DEBUG = 0xf1000000 /* used for debugging */
103};
104
105#define IEEE80211_DMN(_d) ((_d) & ~0xf0000000)
106
107enum ath5k_countrycode {
108 CTRY_DEFAULT = 0, /* Default domain (NA) */
109 CTRY_ALBANIA = 8, /* Albania */
110 CTRY_ALGERIA = 12, /* Algeria */
111 CTRY_ARGENTINA = 32, /* Argentina */
112 CTRY_ARMENIA = 51, /* Armenia */
113 CTRY_AUSTRALIA = 36, /* Australia */
114 CTRY_AUSTRIA = 40, /* Austria */
115 CTRY_AZERBAIJAN = 31, /* Azerbaijan */
116 CTRY_BAHRAIN = 48, /* Bahrain */
117 CTRY_BELARUS = 112, /* Belarus */
118 CTRY_BELGIUM = 56, /* Belgium */
119 CTRY_BELIZE = 84, /* Belize */
120 CTRY_BOLIVIA = 68, /* Bolivia */
121 CTRY_BRAZIL = 76, /* Brazil */
122 CTRY_BRUNEI_DARUSSALAM = 96, /* Brunei Darussalam */
123 CTRY_BULGARIA = 100, /* Bulgaria */
124 CTRY_CANADA = 124, /* Canada */
125 CTRY_CHILE = 152, /* Chile */
126 CTRY_CHINA = 156, /* People's Republic of China */
127 CTRY_COLOMBIA = 170, /* Colombia */
128 CTRY_COSTA_RICA = 188, /* Costa Rica */
129 CTRY_CROATIA = 191, /* Croatia */
130 CTRY_CYPRUS = 196, /* Cyprus */
131 CTRY_CZECH = 203, /* Czech Republic */
132 CTRY_DENMARK = 208, /* Denmark */
133 CTRY_DOMINICAN_REPUBLIC = 214, /* Dominican Republic */
134 CTRY_ECUADOR = 218, /* Ecuador */
135 CTRY_EGYPT = 818, /* Egypt */
136 CTRY_EL_SALVADOR = 222, /* El Salvador */
137 CTRY_ESTONIA = 233, /* Estonia */
138 CTRY_FAEROE_ISLANDS = 234, /* Faeroe Islands */
139 CTRY_FINLAND = 246, /* Finland */
140 CTRY_FRANCE = 250, /* France */
141 CTRY_FRANCE2 = 255, /* France2 */
142 CTRY_GEORGIA = 268, /* Georgia */
143 CTRY_GERMANY = 276, /* Germany */
144 CTRY_GREECE = 300, /* Greece */
145 CTRY_GUATEMALA = 320, /* Guatemala */
146 CTRY_HONDURAS = 340, /* Honduras */
147 CTRY_HONG_KONG = 344, /* Hong Kong S.A.R., P.R.C. */
148 CTRY_HUNGARY = 348, /* Hungary */
149 CTRY_ICELAND = 352, /* Iceland */
150 CTRY_INDIA = 356, /* India */
151 CTRY_INDONESIA = 360, /* Indonesia */
152 CTRY_IRAN = 364, /* Iran */
153 CTRY_IRAQ = 368, /* Iraq */
154 CTRY_IRELAND = 372, /* Ireland */
155 CTRY_ISRAEL = 376, /* Israel */
156 CTRY_ITALY = 380, /* Italy */
157 CTRY_JAMAICA = 388, /* Jamaica */
158 CTRY_JAPAN = 392, /* Japan */
159 CTRY_JAPAN1 = 393, /* Japan (JP1) */
160 CTRY_JAPAN2 = 394, /* Japan (JP0) */
161 CTRY_JAPAN3 = 395, /* Japan (JP1-1) */
162 CTRY_JAPAN4 = 396, /* Japan (JE1) */
163 CTRY_JAPAN5 = 397, /* Japan (JE2) */
164 CTRY_JORDAN = 400, /* Jordan */
165 CTRY_KAZAKHSTAN = 398, /* Kazakhstan */
166 CTRY_KENYA = 404, /* Kenya */
167 CTRY_KOREA_NORTH = 408, /* North Korea */
168 CTRY_KOREA_ROC = 410, /* South Korea */
169 CTRY_KOREA_ROC2 = 411, /* South Korea */
170 CTRY_KUWAIT = 414, /* Kuwait */
171 CTRY_LATVIA = 428, /* Latvia */
172 CTRY_LEBANON = 422, /* Lebanon */
173 CTRY_LIBYA = 434, /* Libya */
174 CTRY_LIECHTENSTEIN = 438, /* Liechtenstein */
175 CTRY_LITHUANIA = 440, /* Lithuania */
176 CTRY_LUXEMBOURG = 442, /* Luxembourg */
177 CTRY_MACAU = 446, /* Macau */
178 CTRY_MACEDONIA = 807, /* Republic of Macedonia */
179 CTRY_MALAYSIA = 458, /* Malaysia */
180 CTRY_MEXICO = 484, /* Mexico */
181 CTRY_MONACO = 492, /* Principality of Monaco */
182 CTRY_MOROCCO = 504, /* Morocco */
183 CTRY_NETHERLANDS = 528, /* Netherlands */
184 CTRY_NEW_ZEALAND = 554, /* New Zealand */
185 CTRY_NICARAGUA = 558, /* Nicaragua */
186 CTRY_NORWAY = 578, /* Norway */
187 CTRY_OMAN = 512, /* Oman */
188 CTRY_PAKISTAN = 586, /* Islamic Republic of Pakistan */
189 CTRY_PANAMA = 591, /* Panama */
190 CTRY_PARAGUAY = 600, /* Paraguay */
191 CTRY_PERU = 604, /* Peru */
192 CTRY_PHILIPPINES = 608, /* Republic of the Philippines */
193 CTRY_POLAND = 616, /* Poland */
194 CTRY_PORTUGAL = 620, /* Portugal */
195 CTRY_PUERTO_RICO = 630, /* Puerto Rico */
196 CTRY_QATAR = 634, /* Qatar */
197 CTRY_ROMANIA = 642, /* Romania */
198 CTRY_RUSSIA = 643, /* Russia */
199 CTRY_SAUDI_ARABIA = 682, /* Saudi Arabia */
200 CTRY_SINGAPORE = 702, /* Singapore */
201 CTRY_SLOVAKIA = 703, /* Slovak Republic */
202 CTRY_SLOVENIA = 705, /* Slovenia */
203 CTRY_SOUTH_AFRICA = 710, /* South Africa */
204 CTRY_SPAIN = 724, /* Spain */
205 CTRY_SRI_LANKA = 728, /* Sri Lanka */
206 CTRY_SWEDEN = 752, /* Sweden */
207 CTRY_SWITZERLAND = 756, /* Switzerland */
208 CTRY_SYRIA = 760, /* Syria */
209 CTRY_TAIWAN = 158, /* Taiwan */
210 CTRY_THAILAND = 764, /* Thailand */
211 CTRY_TRINIDAD_Y_TOBAGO = 780, /* Trinidad y Tobago */
212 CTRY_TUNISIA = 788, /* Tunisia */
213 CTRY_TURKEY = 792, /* Turkey */
214 CTRY_UAE = 784, /* U.A.E. */
215 CTRY_UKRAINE = 804, /* Ukraine */
216 CTRY_UNITED_KINGDOM = 826, /* United Kingdom */
217 CTRY_UNITED_STATES = 840, /* United States */
218 CTRY_URUGUAY = 858, /* Uruguay */
219 CTRY_UZBEKISTAN = 860, /* Uzbekistan */
220 CTRY_VENEZUELA = 862, /* Venezuela */
221 CTRY_VIET_NAM = 704, /* Viet Nam */
222 CTRY_YEMEN = 887, /* Yemen */
223 CTRY_ZIMBABWE = 716, /* Zimbabwe */
224};
225
226#define IEEE80211_CHANNELS_2GHZ_MIN 2412 /* 2GHz channel 1 */
227#define IEEE80211_CHANNELS_2GHZ_MAX 2732 /* 2GHz channel 26 */
228#define IEEE80211_CHANNELS_5GHZ_MIN 5005 /* 5GHz channel 1 */
229#define IEEE80211_CHANNELS_5GHZ_MAX 6100 /* 5GHz channel 220 */
230
231struct ath5k_regchannel {
232 u16 chan;
233 enum ath5k_regdom domain;
234 u32 mode;
235};
236
237#define IEEE80211_CHANNELS_2GHZ { \
238/*2412*/ { 1, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
239/*2417*/ { 2, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
240/*2422*/ { 3, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
241/*2427*/ { 4, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
242/*2432*/ { 5, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
243/*2437*/ { 6, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
244/*2442*/ { 7, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
245/*2447*/ { 8, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
246/*2452*/ { 9, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
247/*2457*/ { 10, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
248/*2462*/ { 11, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
249/*2467*/ { 12, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
250/*2472*/ { 13, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
251 \
252/*2432*/ { 5, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM }, \
253/*2437*/ { 6, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \
254/*2442*/ { 7, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM }, \
255 \
256/*2412*/ { 1, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
257/*2417*/ { 2, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
258/*2422*/ { 3, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
259/*2427*/ { 4, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
260/*2432*/ { 5, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
261/*2437*/ { 6, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \
262/*2442*/ { 7, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
263/*2447*/ { 8, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
264/*2452*/ { 9, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
265/*2457*/ { 10, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
266/*2462*/ { 11, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
267/*2467*/ { 12, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
268/*2472*/ { 13, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
269 \
270/*2412*/ { 1, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
271/*2417*/ { 2, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
272/*2422*/ { 3, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
273/*2427*/ { 4, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
274/*2432*/ { 5, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
275/*2437*/ { 6, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \
276/*2442*/ { 7, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
277/*2447*/ { 8, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
278/*2452*/ { 9, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
279/*2457*/ { 10, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
280/*2462*/ { 11, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
281 \
282/*2412*/ { 1, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
283/*2417*/ { 2, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
284/*2422*/ { 3, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
285/*2427*/ { 4, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
286/*2432*/ { 5, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
287/*2437*/ { 6, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
288/*2442*/ { 7, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
289/*2447*/ { 8, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
290/*2452*/ { 9, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
291/*2457*/ { 10, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
292/*2462*/ { 11, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
293/*2467*/ { 12, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
294/*2472*/ { 13, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
295/*2484*/ { 14, DMN_MKKA, CHANNEL_CCK }, \
296 \
297/*2412*/ { 1, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
298/*2417*/ { 2, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
299/*2422*/ { 3, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
300/*2427*/ { 4, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
301/*2432*/ { 5, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
302/*2437*/ { 6, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \
303/*2442*/ { 7, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
304/*2447*/ { 8, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
305/*2452*/ { 9, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
306/*2457*/ { 10, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
307/*2462*/ { 11, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
308/*2467*/ { 12, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
309/*2472*/ { 13, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
310}
311
312#define IEEE80211_CHANNELS_5GHZ { \
313/*5745*/ { 149, DMN_APL1, CHANNEL_OFDM }, \
314/*5765*/ { 153, DMN_APL1, CHANNEL_OFDM }, \
315/*5785*/ { 157, DMN_APL1, CHANNEL_OFDM }, \
316/*5805*/ { 161, DMN_APL1, CHANNEL_OFDM }, \
317/*5825*/ { 165, DMN_APL1, CHANNEL_OFDM }, \
318 \
319/*5745*/ { 149, DMN_APL2, CHANNEL_OFDM }, \
320/*5765*/ { 153, DMN_APL2, CHANNEL_OFDM }, \
321/*5785*/ { 157, DMN_APL2, CHANNEL_OFDM }, \
322/*5805*/ { 161, DMN_APL2, CHANNEL_OFDM }, \
323 \
324/*5280*/ { 56, DMN_APL3, CHANNEL_OFDM }, \
325/*5300*/ { 60, DMN_APL3, CHANNEL_OFDM }, \
326/*5320*/ { 64, DMN_APL3, CHANNEL_OFDM }, \
327/*5745*/ { 149, DMN_APL3, CHANNEL_OFDM }, \
328/*5765*/ { 153, DMN_APL3, CHANNEL_OFDM }, \
329/*5785*/ { 157, DMN_APL3, CHANNEL_OFDM }, \
330/*5805*/ { 161, DMN_APL3, CHANNEL_OFDM }, \
331 \
332/*5180*/ { 36, DMN_APL4, CHANNEL_OFDM }, \
333/*5200*/ { 40, DMN_APL4, CHANNEL_OFDM }, \
334/*5220*/ { 44, DMN_APL4, CHANNEL_OFDM }, \
335/*5240*/ { 48, DMN_APL4, CHANNEL_OFDM }, \
336/*5745*/ { 149, DMN_APL4, CHANNEL_OFDM }, \
337/*5765*/ { 153, DMN_APL4, CHANNEL_OFDM }, \
338/*5785*/ { 157, DMN_APL4, CHANNEL_OFDM }, \
339/*5805*/ { 161, DMN_APL4, CHANNEL_OFDM }, \
340/*5825*/ { 165, DMN_APL4, CHANNEL_OFDM }, \
341 \
342/*5745*/ { 149, DMN_APL5, CHANNEL_OFDM }, \
343/*5765*/ { 153, DMN_APL5, CHANNEL_OFDM }, \
344/*5785*/ { 157, DMN_APL5, CHANNEL_OFDM }, \
345/*5805*/ { 161, DMN_APL5, CHANNEL_OFDM }, \
346/*5825*/ { 165, DMN_APL5, CHANNEL_OFDM }, \
347 \
348/*5180*/ { 36, DMN_ETSI1, CHANNEL_OFDM }, \
349/*5200*/ { 40, DMN_ETSI1, CHANNEL_OFDM }, \
350/*5220*/ { 44, DMN_ETSI1, CHANNEL_OFDM }, \
351/*5240*/ { 48, DMN_ETSI1, CHANNEL_OFDM }, \
352/*5260*/ { 52, DMN_ETSI1, CHANNEL_OFDM }, \
353/*5280*/ { 56, DMN_ETSI1, CHANNEL_OFDM }, \
354/*5300*/ { 60, DMN_ETSI1, CHANNEL_OFDM }, \
355/*5320*/ { 64, DMN_ETSI1, CHANNEL_OFDM }, \
356/*5500*/ { 100, DMN_ETSI1, CHANNEL_OFDM }, \
357/*5520*/ { 104, DMN_ETSI1, CHANNEL_OFDM }, \
358/*5540*/ { 108, DMN_ETSI1, CHANNEL_OFDM }, \
359/*5560*/ { 112, DMN_ETSI1, CHANNEL_OFDM }, \
360/*5580*/ { 116, DMN_ETSI1, CHANNEL_OFDM }, \
361/*5600*/ { 120, DMN_ETSI1, CHANNEL_OFDM }, \
362/*5620*/ { 124, DMN_ETSI1, CHANNEL_OFDM }, \
363/*5640*/ { 128, DMN_ETSI1, CHANNEL_OFDM }, \
364/*5660*/ { 132, DMN_ETSI1, CHANNEL_OFDM }, \
365/*5680*/ { 136, DMN_ETSI1, CHANNEL_OFDM }, \
366/*5700*/ { 140, DMN_ETSI1, CHANNEL_OFDM }, \
367 \
368/*5180*/ { 36, DMN_ETSI2, CHANNEL_OFDM }, \
369/*5200*/ { 40, DMN_ETSI2, CHANNEL_OFDM }, \
370/*5220*/ { 44, DMN_ETSI2, CHANNEL_OFDM }, \
371/*5240*/ { 48, DMN_ETSI2, CHANNEL_OFDM }, \
372 \
373/*5180*/ { 36, DMN_ETSI3, CHANNEL_OFDM }, \
374/*5200*/ { 40, DMN_ETSI3, CHANNEL_OFDM }, \
375/*5220*/ { 44, DMN_ETSI3, CHANNEL_OFDM }, \
376/*5240*/ { 48, DMN_ETSI3, CHANNEL_OFDM }, \
377/*5260*/ { 52, DMN_ETSI3, CHANNEL_OFDM }, \
378/*5280*/ { 56, DMN_ETSI3, CHANNEL_OFDM }, \
379/*5300*/ { 60, DMN_ETSI3, CHANNEL_OFDM }, \
380/*5320*/ { 64, DMN_ETSI3, CHANNEL_OFDM }, \
381 \
382/*5180*/ { 36, DMN_ETSI4, CHANNEL_OFDM }, \
383/*5200*/ { 40, DMN_ETSI4, CHANNEL_OFDM }, \
384/*5220*/ { 44, DMN_ETSI4, CHANNEL_OFDM }, \
385/*5240*/ { 48, DMN_ETSI4, CHANNEL_OFDM }, \
386/*5260*/ { 52, DMN_ETSI4, CHANNEL_OFDM }, \
387/*5280*/ { 56, DMN_ETSI4, CHANNEL_OFDM }, \
388/*5300*/ { 60, DMN_ETSI4, CHANNEL_OFDM }, \
389/*5320*/ { 64, DMN_ETSI4, CHANNEL_OFDM }, \
390 \
391/*5180*/ { 36, DMN_ETSI5, CHANNEL_OFDM }, \
392/*5200*/ { 40, DMN_ETSI5, CHANNEL_OFDM }, \
393/*5220*/ { 44, DMN_ETSI5, CHANNEL_OFDM }, \
394/*5240*/ { 48, DMN_ETSI5, CHANNEL_OFDM }, \
395 \
396/*5180*/ { 36, DMN_ETSI6, CHANNEL_OFDM }, \
397/*5200*/ { 40, DMN_ETSI6, CHANNEL_OFDM }, \
398/*5220*/ { 44, DMN_ETSI6, CHANNEL_OFDM }, \
399/*5240*/ { 48, DMN_ETSI6, CHANNEL_OFDM }, \
400/*5260*/ { 52, DMN_ETSI6, CHANNEL_OFDM }, \
401/*5280*/ { 56, DMN_ETSI6, CHANNEL_OFDM }, \
402/*5500*/ { 100, DMN_ETSI6, CHANNEL_OFDM }, \
403/*5520*/ { 104, DMN_ETSI6, CHANNEL_OFDM }, \
404/*5540*/ { 108, DMN_ETSI6, CHANNEL_OFDM }, \
405/*5560*/ { 112, DMN_ETSI6, CHANNEL_OFDM }, \
406/*5580*/ { 116, DMN_ETSI6, CHANNEL_OFDM }, \
407/*5600*/ { 120, DMN_ETSI6, CHANNEL_OFDM }, \
408/*5620*/ { 124, DMN_ETSI6, CHANNEL_OFDM }, \
409/*5640*/ { 128, DMN_ETSI6, CHANNEL_OFDM }, \
410/*5660*/ { 132, DMN_ETSI6, CHANNEL_OFDM }, \
411/*5680*/ { 136, DMN_ETSI6, CHANNEL_OFDM }, \
412/*5700*/ { 140, DMN_ETSI6, CHANNEL_OFDM }, \
413 \
414/*5180*/ { 36, DMN_FCC1, CHANNEL_OFDM }, \
415/*5200*/ { 40, DMN_FCC1, CHANNEL_OFDM }, \
416/*5210*/ { 42, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \
417/*5220*/ { 44, DMN_FCC1, CHANNEL_OFDM }, \
418/*5240*/ { 48, DMN_FCC1, CHANNEL_OFDM }, \
419/*5250*/ { 50, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \
420/*5260*/ { 52, DMN_FCC1, CHANNEL_OFDM }, \
421/*5280*/ { 56, DMN_FCC1, CHANNEL_OFDM }, \
422/*5290*/ { 58, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \
423/*5300*/ { 60, DMN_FCC1, CHANNEL_OFDM }, \
424/*5320*/ { 64, DMN_FCC1, CHANNEL_OFDM }, \
425/*5745*/ { 149, DMN_FCC1, CHANNEL_OFDM }, \
426/*5760*/ { 152, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \
427/*5765*/ { 153, DMN_FCC1, CHANNEL_OFDM }, \
428/*5785*/ { 157, DMN_FCC1, CHANNEL_OFDM }, \
429/*5800*/ { 160, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \
430/*5805*/ { 161, DMN_FCC1, CHANNEL_OFDM }, \
431/*5825*/ { 165, DMN_FCC1, CHANNEL_OFDM }, \
432 \
433/*5180*/ { 36, DMN_FCC2, CHANNEL_OFDM }, \
434/*5200*/ { 40, DMN_FCC2, CHANNEL_OFDM }, \
435/*5220*/ { 44, DMN_FCC2, CHANNEL_OFDM }, \
436/*5240*/ { 48, DMN_FCC2, CHANNEL_OFDM }, \
437/*5260*/ { 52, DMN_FCC2, CHANNEL_OFDM }, \
438/*5280*/ { 56, DMN_FCC2, CHANNEL_OFDM }, \
439/*5300*/ { 60, DMN_FCC2, CHANNEL_OFDM }, \
440/*5320*/ { 64, DMN_FCC2, CHANNEL_OFDM }, \
441/*5745*/ { 149, DMN_FCC2, CHANNEL_OFDM }, \
442/*5765*/ { 153, DMN_FCC2, CHANNEL_OFDM }, \
443/*5785*/ { 157, DMN_FCC2, CHANNEL_OFDM }, \
444/*5805*/ { 161, DMN_FCC2, CHANNEL_OFDM }, \
445/*5825*/ { 165, DMN_FCC2, CHANNEL_OFDM }, \
446 \
447/*5180*/ { 36, DMN_FCC3, CHANNEL_OFDM }, \
448/*5200*/ { 40, DMN_FCC3, CHANNEL_OFDM }, \
449/*5210*/ { 42, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \
450/*5220*/ { 44, DMN_FCC3, CHANNEL_OFDM }, \
451/*5240*/ { 48, DMN_FCC3, CHANNEL_OFDM }, \
452/*5250*/ { 50, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \
453/*5260*/ { 52, DMN_FCC3, CHANNEL_OFDM }, \
454/*5280*/ { 56, DMN_FCC3, CHANNEL_OFDM }, \
455/*5290*/ { 58, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \
456/*5300*/ { 60, DMN_FCC3, CHANNEL_OFDM }, \
457/*5320*/ { 64, DMN_FCC3, CHANNEL_OFDM }, \
458/*5500*/ { 100, DMN_FCC3, CHANNEL_OFDM }, \
459/*5520*/ { 104, DMN_FCC3, CHANNEL_OFDM }, \
460/*5540*/ { 108, DMN_FCC3, CHANNEL_OFDM }, \
461/*5560*/ { 112, DMN_FCC3, CHANNEL_OFDM }, \
462/*5580*/ { 116, DMN_FCC3, CHANNEL_OFDM }, \
463/*5600*/ { 120, DMN_FCC3, CHANNEL_OFDM }, \
464/*5620*/ { 124, DMN_FCC3, CHANNEL_OFDM }, \
465/*5640*/ { 128, DMN_FCC3, CHANNEL_OFDM }, \
466/*5660*/ { 132, DMN_FCC3, CHANNEL_OFDM }, \
467/*5680*/ { 136, DMN_FCC3, CHANNEL_OFDM }, \
468/*5700*/ { 140, DMN_FCC3, CHANNEL_OFDM }, \
469/*5745*/ { 149, DMN_FCC3, CHANNEL_OFDM }, \
470/*5760*/ { 152, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \
471/*5765*/ { 153, DMN_FCC3, CHANNEL_OFDM }, \
472/*5785*/ { 157, DMN_FCC3, CHANNEL_OFDM }, \
473/*5800*/ { 160, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \
474/*5805*/ { 161, DMN_FCC3, CHANNEL_OFDM }, \
475/*5825*/ { 165, DMN_FCC3, CHANNEL_OFDM }, \
476 \
477/*5170*/ { 34, DMN_MKK1, CHANNEL_OFDM }, \
478/*5190*/ { 38, DMN_MKK1, CHANNEL_OFDM }, \
479/*5210*/ { 42, DMN_MKK1, CHANNEL_OFDM }, \
480/*5230*/ { 46, DMN_MKK1, CHANNEL_OFDM }, \
481 \
482/*5040*/ { 8, DMN_MKK2, CHANNEL_OFDM }, \
483/*5060*/ { 12, DMN_MKK2, CHANNEL_OFDM }, \
484/*5080*/ { 16, DMN_MKK2, CHANNEL_OFDM }, \
485/*5170*/ { 34, DMN_MKK2, CHANNEL_OFDM }, \
486/*5190*/ { 38, DMN_MKK2, CHANNEL_OFDM }, \
487/*5210*/ { 42, DMN_MKK2, CHANNEL_OFDM }, \
488/*5230*/ { 46, DMN_MKK2, CHANNEL_OFDM }, \
489 \
490/*5180*/ { 36, DMN_WORLD, CHANNEL_OFDM }, \
491/*5200*/ { 40, DMN_WORLD, CHANNEL_OFDM }, \
492/*5220*/ { 44, DMN_WORLD, CHANNEL_OFDM }, \
493/*5240*/ { 48, DMN_WORLD, CHANNEL_OFDM }, \
494}
495
496enum ath5k_regdom ath5k_regdom2flag(enum ath5k_regdom, u16);
497u16 ath5k_regdom_from_ieee(enum ath5k_regdom ieee);
498enum ath5k_regdom ath5k_regdom_to_ieee(u16 regdomain);
499
500#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 09:39:50 -0500