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authorMatt Carlson <mcarlson@broadcom.com>2010-04-12 02:58:24 -0400
committerDavid S. Miller <davem@davemloft.net>2010-04-13 05:25:42 -0400
commitcea46462681d61a65a208d17206d38739c1ea1b1 (patch)
treeaf5b17960d6871e9dc2b6d104eaadf87730220f5 /drivers/net
parentb6c6712a42ca3f9fa7f4a3d7c40e3a9dd1fd9e03 (diff)
tg3: Disable CLKREQ in L2
This patch disables CLKREQ in L2 to workaround a chipset bug. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/tg3.c14
-rw-r--r--drivers/net/tg3.h2
2 files changed, 16 insertions, 0 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 460a0c22b318..4ae01b3799f4 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -7642,6 +7642,20 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7642 tw32(GRC_MODE, grc_mode); 7642 tw32(GRC_MODE, grc_mode);
7643 } 7643 }
7644 7644
7645 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7646 u32 grc_mode = tr32(GRC_MODE);
7647
7648 /* Access the lower 1K of PL PCIE block registers. */
7649 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7650 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7651
7652 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7653 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7654 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7655
7656 tw32(GRC_MODE, grc_mode);
7657 }
7658
7645 /* This works around an issue with Athlon chipsets on 7659 /* This works around an issue with Athlon chipsets on
7646 * B3 tigon3 silicon. This bit has no effect on any 7660 * B3 tigon3 silicon. This bit has no effect on any
7647 * other revision. But do not set this on PCI Express 7661 * other revision. But do not set this on PCI Express
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 5d7f72a2ea01..8a6012ab23ff 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1854,6 +1854,8 @@
1854#define TG3_PCIE_TLDLPL_PORT 0x00007c00 1854#define TG3_PCIE_TLDLPL_PORT 0x00007c00
1855#define TG3_PCIE_PL_LO_PHYCTL1 0x00000004 1855#define TG3_PCIE_PL_LO_PHYCTL1 0x00000004
1856#define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN 0x00001000 1856#define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN 0x00001000
1857#define TG3_PCIE_PL_LO_PHYCTL5 0x00000014
1858#define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ 0x80000000
1857 1859
1858/* OTP bit definitions */ 1860/* OTP bit definitions */
1859#define TG3_OTP_AGCTGT_MASK 0x000000e0 1861#define TG3_OTP_AGCTGT_MASK 0x000000e0