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authorVladislav Zolotarov <vladz@broadcom.com>2010-12-13 00:44:18 -0500
committerDavid S. Miller <davem@davemloft.net>2010-12-16 16:15:55 -0500
commite4901dde12d92b70dd13fa8b3bbc9df7a6129aab (patch)
treeda436a7a43cf5f212485cc9691592d90e01478db /drivers/net
parent8307fa3e86a83924dd7f8310ce1e051f34986fe8 (diff)
bnx2x: add DCB support
Adding DCB initialization and handling on 57712 FW/HW Signed-off-by: Dmitry Kravkov <dmitry@broadcom.com> Signed-off-by: Shmulik Ravid-Rabinovitz <shmulikr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/bnx2x/Makefile2
-rw-r--r--drivers/net/bnx2x/bnx2x.h15
-rw-r--r--drivers/net/bnx2x/bnx2x_cmn.c2
-rw-r--r--drivers/net/bnx2x/bnx2x_cmn.h7
-rw-r--r--drivers/net/bnx2x/bnx2x_dcb.c1491
-rw-r--r--drivers/net/bnx2x/bnx2x_dcb.h193
-rw-r--r--drivers/net/bnx2x/bnx2x_hsi.h281
-rw-r--r--drivers/net/bnx2x/bnx2x_link.h40
-rw-r--r--drivers/net/bnx2x/bnx2x_main.c24
9 files changed, 2050 insertions, 5 deletions
diff --git a/drivers/net/bnx2x/Makefile b/drivers/net/bnx2x/Makefile
index 084afce89ae9..bb83a2961273 100644
--- a/drivers/net/bnx2x/Makefile
+++ b/drivers/net/bnx2x/Makefile
@@ -4,4 +4,4 @@
4 4
5obj-$(CONFIG_BNX2X) += bnx2x.o 5obj-$(CONFIG_BNX2X) += bnx2x.o
6 6
7bnx2x-objs := bnx2x_main.o bnx2x_link.o bnx2x_cmn.o bnx2x_ethtool.o bnx2x_stats.o 7bnx2x-objs := bnx2x_main.o bnx2x_link.o bnx2x_cmn.o bnx2x_ethtool.o bnx2x_stats.o bnx2x_dcb.o
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index 475725c566d7..66b3b6055cef 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -50,6 +50,7 @@
50#include "bnx2x_fw_defs.h" 50#include "bnx2x_fw_defs.h"
51#include "bnx2x_hsi.h" 51#include "bnx2x_hsi.h"
52#include "bnx2x_link.h" 52#include "bnx2x_link.h"
53#include "bnx2x_dcb.h"
53#include "bnx2x_stats.h" 54#include "bnx2x_stats.h"
54 55
55/* error/debug prints */ 56/* error/debug prints */
@@ -820,6 +821,8 @@ struct bnx2x_slowpath {
820 821
821 u32 wb_comp; 822 u32 wb_comp;
822 u32 wb_data[4]; 823 u32 wb_data[4];
824 /* pfc configuration for DCBX ramrod */
825 struct flow_control_configuration pfc_config;
823}; 826};
824 827
825#define bnx2x_sp(bp, var) (&bp->slowpath->var) 828#define bnx2x_sp(bp, var) (&bp->slowpath->var)
@@ -1180,6 +1183,18 @@ struct bnx2x {
1180 1183
1181 char fw_ver[32]; 1184 char fw_ver[32];
1182 const struct firmware *firmware; 1185 const struct firmware *firmware;
1186 /* LLDP params */
1187 struct bnx2x_config_lldp_params lldp_config_params;
1188
1189 /* DCBX params */
1190 struct bnx2x_config_dcbx_params dcbx_config_params;
1191
1192 struct bnx2x_dcbx_port_params dcbx_port_params;
1193 int dcb_version;
1194
1195 /* DCBX Negotation results */
1196 struct dcbx_features dcbx_local_feat;
1197 u32 dcbx_error;
1183}; 1198};
1184 1199
1185/** 1200/**
diff --git a/drivers/net/bnx2x/bnx2x_cmn.c b/drivers/net/bnx2x/bnx2x_cmn.c
index 10eef5434386..710ce5d04c53 100644
--- a/drivers/net/bnx2x/bnx2x_cmn.c
+++ b/drivers/net/bnx2x/bnx2x_cmn.c
@@ -1371,6 +1371,8 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
1371 } 1371 }
1372 } 1372 }
1373 1373
1374 bnx2x_dcbx_init(bp);
1375
1374 bp->state = BNX2X_STATE_OPENING_WAIT4_PORT; 1376 bp->state = BNX2X_STATE_OPENING_WAIT4_PORT;
1375 1377
1376 rc = bnx2x_func_start(bp); 1378 rc = bnx2x_func_start(bp);
diff --git a/drivers/net/bnx2x/bnx2x_cmn.h b/drivers/net/bnx2x/bnx2x_cmn.h
index 258f0c04716b..03eb4d68e6bb 100644
--- a/drivers/net/bnx2x/bnx2x_cmn.h
+++ b/drivers/net/bnx2x/bnx2x_cmn.h
@@ -324,6 +324,13 @@ int bnx2x_func_start(struct bnx2x *bp);
324void bnx2x_ilt_set_info(struct bnx2x *bp); 324void bnx2x_ilt_set_info(struct bnx2x *bp);
325 325
326/** 326/**
327 * Inintialize dcbx protocol
328 *
329 * @param bp
330 */
331void bnx2x_dcbx_init(struct bnx2x *bp);
332
333/**
327 * Set power state to the requested value. Currently only D0 and 334 * Set power state to the requested value. Currently only D0 and
328 * D3hot are supported. 335 * D3hot are supported.
329 * 336 *
diff --git a/drivers/net/bnx2x/bnx2x_dcb.c b/drivers/net/bnx2x/bnx2x_dcb.c
new file mode 100644
index 000000000000..0b86480379ff
--- /dev/null
+++ b/drivers/net/bnx2x/bnx2x_dcb.c
@@ -0,0 +1,1491 @@
1/* bnx2x_dcb.c: Broadcom Everest network driver.
2 *
3 * Copyright 2009-2010 Broadcom Corporation
4 *
5 * Unless you and Broadcom execute a separate written software license
6 * agreement governing use of this software, this software is licensed to you
7 * under the terms of the GNU General Public License version 2, available
8 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
9 *
10 * Notwithstanding the above, under no circumstances may you combine this
11 * software in any way with any other Broadcom software provided under a
12 * license other than the GPL, without Broadcom's express prior written
13 * consent.
14 *
15 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
16 * Written by: Dmitry Kravkov
17 *
18 */
19#include <linux/netdevice.h>
20#include <linux/types.h>
21#include <linux/errno.h>
22
23#include "bnx2x.h"
24#include "bnx2x_cmn.h"
25#include "bnx2x_dcb.h"
26
27
28/* forward declarations of dcbx related functions */
29static void bnx2x_dcbx_stop_hw_tx(struct bnx2x *bp);
30static void bnx2x_pfc_set_pfc(struct bnx2x *bp);
31static void bnx2x_dcbx_update_ets_params(struct bnx2x *bp);
32static void bnx2x_dcbx_resume_hw_tx(struct bnx2x *bp);
33static void bnx2x_dcbx_get_ets_pri_pg_tbl(struct bnx2x *bp,
34 u32 *set_configuration_ets_pg,
35 u32 *pri_pg_tbl);
36static void bnx2x_dcbx_get_num_pg_traf_type(struct bnx2x *bp,
37 u32 *pg_pri_orginal_spread,
38 struct pg_help_data *help_data);
39static void bnx2x_dcbx_fill_cos_params(struct bnx2x *bp,
40 struct pg_help_data *help_data,
41 struct dcbx_ets_feature *ets,
42 u32 *pg_pri_orginal_spread);
43static void bnx2x_dcbx_separate_pauseable_from_non(struct bnx2x *bp,
44 struct cos_help_data *cos_data,
45 u32 *pg_pri_orginal_spread,
46 struct dcbx_ets_feature *ets);
47static void bnx2x_pfc_fw_struct_e2(struct bnx2x *bp);
48
49
50static void bnx2x_pfc_set(struct bnx2x *bp)
51{
52 struct bnx2x_nig_brb_pfc_port_params pfc_params = {0};
53 u32 pri_bit, val = 0;
54 u8 pri;
55
56 /* Tx COS configuration */
57 if (bp->dcbx_port_params.ets.cos_params[0].pauseable)
58 pfc_params.rx_cos0_priority_mask =
59 bp->dcbx_port_params.ets.cos_params[0].pri_bitmask;
60 if (bp->dcbx_port_params.ets.cos_params[1].pauseable)
61 pfc_params.rx_cos1_priority_mask =
62 bp->dcbx_port_params.ets.cos_params[1].pri_bitmask;
63
64
65 /**
66 * Rx COS configuration
67 * Changing PFC RX configuration .
68 * In RX COS0 will always be configured to lossy and COS1 to lossless
69 */
70 for (pri = 0 ; pri < MAX_PFC_PRIORITIES ; pri++) {
71 pri_bit = 1 << pri;
72
73 if (pri_bit & DCBX_PFC_PRI_PAUSE_MASK(bp))
74 val |= 1 << (pri * 4);
75 }
76
77 pfc_params.pkt_priority_to_cos = val;
78
79 /* RX COS0 */
80 pfc_params.llfc_low_priority_classes = 0;
81 /* RX COS1 */
82 pfc_params.llfc_high_priority_classes = DCBX_PFC_PRI_PAUSE_MASK(bp);
83
84 /* BRB configuration */
85 pfc_params.cos0_pauseable = false;
86 pfc_params.cos1_pauseable = true;
87
88 bnx2x_acquire_phy_lock(bp);
89 bp->link_params.feature_config_flags |= FEATURE_CONFIG_PFC_ENABLED;
90 bnx2x_update_pfc(&bp->link_params, &bp->link_vars, &pfc_params);
91 bnx2x_release_phy_lock(bp);
92}
93
94static void bnx2x_pfc_clear(struct bnx2x *bp)
95{
96 struct bnx2x_nig_brb_pfc_port_params nig_params = {0};
97 nig_params.pause_enable = 1;
98#ifdef BNX2X_SAFC
99 if (bp->flags & SAFC_TX_FLAG) {
100 u32 high = 0, low = 0;
101 int i;
102
103 for (i = 0; i < BNX2X_MAX_PRIORITY; i++) {
104 if (bp->pri_map[i] == 1)
105 high |= (1 << i);
106 if (bp->pri_map[i] == 0)
107 low |= (1 << i);
108 }
109
110 nig_params.llfc_low_priority_classes = high;
111 nig_params.llfc_low_priority_classes = low;
112
113 nig_params.pause_enable = 0;
114 nig_params.llfc_enable = 1;
115 nig_params.llfc_out_en = 1;
116 }
117#endif /* BNX2X_SAFC */
118 bnx2x_acquire_phy_lock(bp);
119 bp->link_params.feature_config_flags &= ~FEATURE_CONFIG_PFC_ENABLED;
120 bnx2x_update_pfc(&bp->link_params, &bp->link_vars, &nig_params);
121 bnx2x_release_phy_lock(bp);
122}
123
124static void bnx2x_dump_dcbx_drv_param(struct bnx2x *bp,
125 struct dcbx_features *features,
126 u32 error)
127{
128 u8 i = 0;
129 DP(NETIF_MSG_LINK, "local_mib.error %x\n", error);
130
131 /* PG */
132 DP(NETIF_MSG_LINK,
133 "local_mib.features.ets.enabled %x\n", features->ets.enabled);
134 for (i = 0; i < DCBX_MAX_NUM_PG_BW_ENTRIES; i++)
135 DP(NETIF_MSG_LINK,
136 "local_mib.features.ets.pg_bw_tbl[%d] %d\n", i,
137 DCBX_PG_BW_GET(features->ets.pg_bw_tbl, i));
138 for (i = 0; i < DCBX_MAX_NUM_PRI_PG_ENTRIES; i++)
139 DP(NETIF_MSG_LINK,
140 "local_mib.features.ets.pri_pg_tbl[%d] %d\n", i,
141 DCBX_PRI_PG_GET(features->ets.pri_pg_tbl, i));
142
143 /* pfc */
144 DP(NETIF_MSG_LINK, "dcbx_features.pfc.pri_en_bitmap %x\n",
145 features->pfc.pri_en_bitmap);
146 DP(NETIF_MSG_LINK, "dcbx_features.pfc.pfc_caps %x\n",
147 features->pfc.pfc_caps);
148 DP(NETIF_MSG_LINK, "dcbx_features.pfc.enabled %x\n",
149 features->pfc.enabled);
150
151 DP(NETIF_MSG_LINK, "dcbx_features.app.default_pri %x\n",
152 features->app.default_pri);
153 DP(NETIF_MSG_LINK, "dcbx_features.app.tc_supported %x\n",
154 features->app.tc_supported);
155 DP(NETIF_MSG_LINK, "dcbx_features.app.enabled %x\n",
156 features->app.enabled);
157 for (i = 0; i < DCBX_MAX_APP_PROTOCOL; i++) {
158 DP(NETIF_MSG_LINK,
159 "dcbx_features.app.app_pri_tbl[%x].app_id %x\n",
160 i, features->app.app_pri_tbl[i].app_id);
161 DP(NETIF_MSG_LINK,
162 "dcbx_features.app.app_pri_tbl[%x].pri_bitmap %x\n",
163 i, features->app.app_pri_tbl[i].pri_bitmap);
164 DP(NETIF_MSG_LINK,
165 "dcbx_features.app.app_pri_tbl[%x].appBitfield %x\n",
166 i, features->app.app_pri_tbl[i].appBitfield);
167 }
168}
169
170static void bnx2x_dcbx_get_ap_priority(struct bnx2x *bp,
171 u8 pri_bitmap,
172 u8 llfc_traf_type)
173{
174 u32 pri = MAX_PFC_PRIORITIES;
175 u32 index = MAX_PFC_PRIORITIES - 1;
176 u32 pri_mask;
177 u32 *ttp = bp->dcbx_port_params.app.traffic_type_priority;
178
179 /* Choose the highest priority */
180 while ((MAX_PFC_PRIORITIES == pri) && (0 != index)) {
181 pri_mask = 1 << index;
182 if (GET_FLAGS(pri_bitmap, pri_mask))
183 pri = index ;
184 index--;
185 }
186
187 if (pri < MAX_PFC_PRIORITIES)
188 ttp[llfc_traf_type] = max_t(u32, ttp[llfc_traf_type], pri);
189}
190
191static void bnx2x_dcbx_get_ap_feature(struct bnx2x *bp,
192 struct dcbx_app_priority_feature *app,
193 u32 error) {
194 u8 index;
195 u32 *ttp = bp->dcbx_port_params.app.traffic_type_priority;
196
197 if (GET_FLAGS(error, DCBX_LOCAL_APP_ERROR))
198 DP(NETIF_MSG_LINK, "DCBX_LOCAL_APP_ERROR\n");
199
200 if (app->enabled && !GET_FLAGS(error, DCBX_LOCAL_APP_ERROR)) {
201
202 bp->dcbx_port_params.app.enabled = true;
203
204 for (index = 0 ; index < LLFC_DRIVER_TRAFFIC_TYPE_MAX; index++)
205 ttp[index] = 0;
206
207 if (app->default_pri < MAX_PFC_PRIORITIES)
208 ttp[LLFC_TRAFFIC_TYPE_NW] = app->default_pri;
209
210 for (index = 0 ; index < DCBX_MAX_APP_PROTOCOL; index++) {
211 struct dcbx_app_priority_entry *entry =
212 app->app_pri_tbl;
213
214 if (GET_FLAGS(entry[index].appBitfield,
215 DCBX_APP_SF_ETH_TYPE) &&
216 ETH_TYPE_FCOE == entry[index].app_id)
217 bnx2x_dcbx_get_ap_priority(bp,
218 entry[index].pri_bitmap,
219 LLFC_TRAFFIC_TYPE_FCOE);
220
221 if (GET_FLAGS(entry[index].appBitfield,
222 DCBX_APP_SF_PORT) &&
223 TCP_PORT_ISCSI == entry[index].app_id)
224 bnx2x_dcbx_get_ap_priority(bp,
225 entry[index].pri_bitmap,
226 LLFC_TRAFFIC_TYPE_ISCSI);
227 }
228 } else {
229 DP(NETIF_MSG_LINK, "DCBX_LOCAL_APP_DISABLED\n");
230 bp->dcbx_port_params.app.enabled = false;
231 for (index = 0 ; index < LLFC_DRIVER_TRAFFIC_TYPE_MAX; index++)
232 ttp[index] = INVALID_TRAFFIC_TYPE_PRIORITY;
233 }
234}
235
236static void bnx2x_dcbx_get_ets_feature(struct bnx2x *bp,
237 struct dcbx_ets_feature *ets,
238 u32 error) {
239 int i = 0;
240 u32 pg_pri_orginal_spread[DCBX_MAX_NUM_PG_BW_ENTRIES] = {0};
241 struct pg_help_data pg_help_data;
242 struct bnx2x_dcbx_cos_params *cos_params =
243 bp->dcbx_port_params.ets.cos_params;
244
245 memset(&pg_help_data, 0, sizeof(struct pg_help_data));
246
247
248 if (GET_FLAGS(error, DCBX_LOCAL_ETS_ERROR))
249 DP(NETIF_MSG_LINK, "DCBX_LOCAL_ETS_ERROR\n");
250
251
252 /* Clean up old settings of ets on COS */
253 for (i = 0; i < E2_NUM_OF_COS ; i++) {
254
255 cos_params[i].pauseable = false;
256 cos_params[i].strict = BNX2X_DCBX_COS_NOT_STRICT;
257 cos_params[i].bw_tbl = DCBX_INVALID_COS_BW;
258 cos_params[i].pri_bitmask = DCBX_PFC_PRI_GET_NON_PAUSE(bp, 0);
259 }
260
261 if (bp->dcbx_port_params.app.enabled &&
262 !GET_FLAGS(error, DCBX_LOCAL_ETS_ERROR) &&
263 ets->enabled) {
264 DP(NETIF_MSG_LINK, "DCBX_LOCAL_ETS_ENABLE\n");
265 bp->dcbx_port_params.ets.enabled = true;
266
267 bnx2x_dcbx_get_ets_pri_pg_tbl(bp,
268 pg_pri_orginal_spread,
269 ets->pri_pg_tbl);
270
271 bnx2x_dcbx_get_num_pg_traf_type(bp,
272 pg_pri_orginal_spread,
273 &pg_help_data);
274
275 bnx2x_dcbx_fill_cos_params(bp, &pg_help_data,
276 ets, pg_pri_orginal_spread);
277
278 } else {
279 DP(NETIF_MSG_LINK, "DCBX_LOCAL_ETS_DISABLED\n");
280 bp->dcbx_port_params.ets.enabled = false;
281 ets->pri_pg_tbl[0] = 0;
282
283 for (i = 0; i < DCBX_MAX_NUM_PRI_PG_ENTRIES ; i++)
284 DCBX_PG_BW_SET(ets->pg_bw_tbl, i, 1);
285 }
286}
287
288static void bnx2x_dcbx_get_pfc_feature(struct bnx2x *bp,
289 struct dcbx_pfc_feature *pfc, u32 error)
290{
291
292 if (GET_FLAGS(error, DCBX_LOCAL_PFC_ERROR))
293 DP(NETIF_MSG_LINK, "DCBX_LOCAL_PFC_ERROR\n");
294
295 if (bp->dcbx_port_params.app.enabled &&
296 !GET_FLAGS(error, DCBX_LOCAL_PFC_ERROR) &&
297 pfc->enabled) {
298 bp->dcbx_port_params.pfc.enabled = true;
299 bp->dcbx_port_params.pfc.priority_non_pauseable_mask =
300 ~(pfc->pri_en_bitmap);
301 } else {
302 DP(NETIF_MSG_LINK, "DCBX_LOCAL_PFC_DISABLED\n");
303 bp->dcbx_port_params.pfc.enabled = false;
304 bp->dcbx_port_params.pfc.priority_non_pauseable_mask = 0;
305 }
306}
307
308static void bnx2x_get_dcbx_drv_param(struct bnx2x *bp,
309 struct dcbx_features *features,
310 u32 error)
311{
312 bnx2x_dcbx_get_ap_feature(bp, &features->app, error);
313
314 bnx2x_dcbx_get_pfc_feature(bp, &features->pfc, error);
315
316 bnx2x_dcbx_get_ets_feature(bp, &features->ets, error);
317}
318
319#define DCBX_LOCAL_MIB_MAX_TRY_READ (100)
320static int bnx2x_dcbx_read_mib(struct bnx2x *bp,
321 u32 *base_mib_addr,
322 u32 offset,
323 int read_mib_type)
324{
325 int max_try_read = 0, i;
326 u32 *buff, mib_size, prefix_seq_num, suffix_seq_num;
327 struct lldp_remote_mib *remote_mib ;
328 struct lldp_local_mib *local_mib;
329
330
331 switch (read_mib_type) {
332 case DCBX_READ_LOCAL_MIB:
333 mib_size = sizeof(struct lldp_local_mib);
334 break;
335 case DCBX_READ_REMOTE_MIB:
336 mib_size = sizeof(struct lldp_remote_mib);
337 break;
338 default:
339 return 1; /*error*/
340 }
341
342 offset += BP_PORT(bp) * mib_size;
343
344 do {
345 buff = base_mib_addr;
346 for (i = 0; i < mib_size; i += 4, buff++)
347 *buff = REG_RD(bp, offset + i);
348
349 max_try_read++;
350
351 switch (read_mib_type) {
352 case DCBX_READ_LOCAL_MIB:
353 local_mib = (struct lldp_local_mib *) base_mib_addr;
354 prefix_seq_num = local_mib->prefix_seq_num;
355 suffix_seq_num = local_mib->suffix_seq_num;
356 break;
357 case DCBX_READ_REMOTE_MIB:
358 remote_mib = (struct lldp_remote_mib *) base_mib_addr;
359 prefix_seq_num = remote_mib->prefix_seq_num;
360 suffix_seq_num = remote_mib->suffix_seq_num;
361 break;
362 default:
363 return 1; /*error*/
364 }
365 } while ((prefix_seq_num != suffix_seq_num) &&
366 (max_try_read < DCBX_LOCAL_MIB_MAX_TRY_READ));
367
368 if (max_try_read >= DCBX_LOCAL_MIB_MAX_TRY_READ) {
369 BNX2X_ERR("MIB could not be read\n");
370 return 1;
371 }
372
373 return 0;
374}
375
376static void bnx2x_pfc_set_pfc(struct bnx2x *bp)
377{
378 if (CHIP_IS_E2(bp)) {
379 if (BP_PORT(bp)) {
380 BNX2X_ERR("4 port mode is not supported");
381 return;
382 }
383
384 if (bp->dcbx_port_params.pfc.enabled)
385
386 /* 1. Fills up common PFC structures if required.*/
387 /* 2. Configure NIG, MAC and BRB via the elink:
388 * elink must first check if BMAC is not in reset
389 * and only then configures the BMAC
390 * Or, configure EMAC.
391 */
392 bnx2x_pfc_set(bp);
393
394 else
395 bnx2x_pfc_clear(bp);
396 }
397}
398
399static void bnx2x_dcbx_stop_hw_tx(struct bnx2x *bp)
400{
401 DP(NETIF_MSG_LINK, "sending STOP TRAFFIC\n");
402 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_STOP_TRAFFIC,
403 0 /* connectionless */,
404 0 /* dataHi is zero */,
405 0 /* dataLo is zero */,
406 1 /* common */);
407}
408
409static void bnx2x_dcbx_resume_hw_tx(struct bnx2x *bp)
410{
411 bnx2x_pfc_fw_struct_e2(bp);
412 DP(NETIF_MSG_LINK, "sending START TRAFFIC\n");
413 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_START_TRAFFIC,
414 0, /* connectionless */
415 U64_HI(bnx2x_sp_mapping(bp, pfc_config)),
416 U64_LO(bnx2x_sp_mapping(bp, pfc_config)),
417 1 /* commmon */);
418}
419
420static void bnx2x_dcbx_update_ets_params(struct bnx2x *bp)
421{
422 struct bnx2x_dcbx_pg_params *ets = &(bp->dcbx_port_params.ets);
423 u8 status = 0;
424
425 bnx2x_ets_disabled(&bp->link_params);
426
427 if (!ets->enabled)
428 return;
429
430 if ((ets->num_of_cos == 0) || (ets->num_of_cos > E2_NUM_OF_COS)) {
431 BNX2X_ERR("illegal num of cos= %x", ets->num_of_cos);
432 return;
433 }
434
435 /* valid COS entries */
436 if (ets->num_of_cos == 1) /* no ETS */
437 return;
438
439 /* sanity */
440 if (((BNX2X_DCBX_COS_NOT_STRICT == ets->cos_params[0].strict) &&
441 (DCBX_INVALID_COS_BW == ets->cos_params[0].bw_tbl)) ||
442 ((BNX2X_DCBX_COS_NOT_STRICT == ets->cos_params[1].strict) &&
443 (DCBX_INVALID_COS_BW == ets->cos_params[1].bw_tbl))) {
444 BNX2X_ERR("all COS should have at least bw_limit or strict"
445 "ets->cos_params[0].strict= %x"
446 "ets->cos_params[0].bw_tbl= %x"
447 "ets->cos_params[1].strict= %x"
448 "ets->cos_params[1].bw_tbl= %x",
449 ets->cos_params[0].strict,
450 ets->cos_params[0].bw_tbl,
451 ets->cos_params[1].strict,
452 ets->cos_params[1].bw_tbl);
453 return;
454 }
455 /* If we join a group and there is bw_tbl and strict then bw rules */
456 if ((DCBX_INVALID_COS_BW != ets->cos_params[0].bw_tbl) &&
457 (DCBX_INVALID_COS_BW != ets->cos_params[1].bw_tbl)) {
458 u32 bw_tbl_0 = ets->cos_params[0].bw_tbl;
459 u32 bw_tbl_1 = ets->cos_params[1].bw_tbl;
460 /* Do not allow 0-100 configuration
461 * since PBF does not support it
462 * force 1-99 instead
463 */
464 if (bw_tbl_0 == 0) {
465 bw_tbl_0 = 1;
466 bw_tbl_1 = 99;
467 } else if (bw_tbl_1 == 0) {
468 bw_tbl_1 = 1;
469 bw_tbl_0 = 99;
470 }
471
472 bnx2x_ets_bw_limit(&bp->link_params, bw_tbl_0, bw_tbl_1);
473 } else {
474 if (ets->cos_params[0].strict == BNX2X_DCBX_COS_HIGH_STRICT)
475 status = bnx2x_ets_strict(&bp->link_params, 0);
476 else if (ets->cos_params[1].strict
477 == BNX2X_DCBX_COS_HIGH_STRICT)
478 status = bnx2x_ets_strict(&bp->link_params, 1);
479
480 if (status)
481 BNX2X_ERR("update_ets_params failed\n");
482 }
483}
484
485static int bnx2x_dcbx_read_shmem_neg_results(struct bnx2x *bp)
486{
487 struct lldp_local_mib local_mib = {0};
488 u32 dcbx_neg_res_offset = SHMEM2_RD(bp, dcbx_neg_res_offset);
489 int rc;
490
491 DP(NETIF_MSG_LINK, "dcbx_neg_res_offset 0x%x\n", dcbx_neg_res_offset);
492
493 if (SHMEM_DCBX_NEG_RES_NONE == dcbx_neg_res_offset) {
494 BNX2X_ERR("FW doesn't support dcbx_neg_res_offset\n");
495 return -EINVAL;
496 }
497 rc = bnx2x_dcbx_read_mib(bp, (u32 *)&local_mib, dcbx_neg_res_offset,
498 DCBX_READ_LOCAL_MIB);
499
500 if (rc) {
501 BNX2X_ERR("Faild to read local mib from FW\n");
502 return rc;
503 }
504
505 /* save features and error */
506 bp->dcbx_local_feat = local_mib.features;
507 bp->dcbx_error = local_mib.error;
508 return 0;
509}
510
511void bnx2x_dcbx_set_params(struct bnx2x *bp, u32 state)
512{
513 switch (state) {
514 case BNX2X_DCBX_STATE_NEG_RECEIVED:
515 {
516 DP(NETIF_MSG_LINK, "BNX2X_DCBX_STATE_NEG_RECEIVED\n");
517
518 /* Read neg results if dcbx is in the FW */
519 if (bnx2x_dcbx_read_shmem_neg_results(bp))
520 return;
521
522 bnx2x_dump_dcbx_drv_param(bp, &bp->dcbx_local_feat,
523 bp->dcbx_error);
524
525 bnx2x_get_dcbx_drv_param(bp, &bp->dcbx_local_feat,
526 bp->dcbx_error);
527
528 if (bp->state != BNX2X_STATE_OPENING_WAIT4_LOAD) {
529 bnx2x_dcbx_stop_hw_tx(bp);
530 return;
531 }
532 /* fall through */
533 }
534 case BNX2X_DCBX_STATE_TX_PAUSED:
535 DP(NETIF_MSG_LINK, "BNX2X_DCBX_STATE_TX_PAUSED\n");
536 bnx2x_pfc_set_pfc(bp);
537
538 bnx2x_dcbx_update_ets_params(bp);
539 if (bp->state != BNX2X_STATE_OPENING_WAIT4_LOAD) {
540 bnx2x_dcbx_resume_hw_tx(bp);
541 return;
542 }
543 /* fall through */
544 case BNX2X_DCBX_STATE_TX_RELEASED:
545 DP(NETIF_MSG_LINK, "BNX2X_DCBX_STATE_TX_RELEASED\n");
546 if (bp->state != BNX2X_STATE_OPENING_WAIT4_LOAD)
547 bnx2x_fw_command(bp, DRV_MSG_CODE_DCBX_PMF_DRV_OK, 0);
548
549 return;
550 default:
551 BNX2X_ERR("Unknown DCBX_STATE\n");
552 }
553}
554
555
556#define LLDP_STATS_OFFSET(bp) (BP_PORT(bp)*\
557 sizeof(struct lldp_dcbx_stat))
558
559/* calculate struct offset in array according to chip information */
560#define LLDP_PARAMS_OFFSET(bp) (BP_PORT(bp)*sizeof(struct lldp_params))
561
562#define LLDP_ADMIN_MIB_OFFSET(bp) (PORT_MAX*sizeof(struct lldp_params) + \
563 BP_PORT(bp)*sizeof(struct lldp_admin_mib))
564
565static void bnx2x_dcbx_lldp_updated_params(struct bnx2x *bp,
566 u32 dcbx_lldp_params_offset)
567{
568 struct lldp_params lldp_params = {0};
569 u32 i = 0, *buff = NULL;
570 u32 offset = dcbx_lldp_params_offset + LLDP_PARAMS_OFFSET(bp);
571
572 DP(NETIF_MSG_LINK, "lldp_offset 0x%x\n", offset);
573
574 if ((bp->lldp_config_params.overwrite_settings ==
575 BNX2X_DCBX_OVERWRITE_SETTINGS_ENABLE)) {
576 /* Read the data first */
577 buff = (u32 *)&lldp_params;
578 for (i = 0; i < sizeof(struct lldp_params); i += 4, buff++)
579 *buff = REG_RD(bp, (offset + i));
580
581 lldp_params.msg_tx_hold =
582 (u8)bp->lldp_config_params.msg_tx_hold;
583 lldp_params.msg_fast_tx_interval =
584 (u8)bp->lldp_config_params.msg_fast_tx;
585 lldp_params.tx_crd_max =
586 (u8)bp->lldp_config_params.tx_credit_max;
587 lldp_params.msg_tx_interval =
588 (u8)bp->lldp_config_params.msg_tx_interval;
589 lldp_params.tx_fast =
590 (u8)bp->lldp_config_params.tx_fast;
591
592 /* Write the data.*/
593 buff = (u32 *)&lldp_params;
594 for (i = 0; i < sizeof(struct lldp_params); i += 4, buff++)
595 REG_WR(bp, (offset + i) , *buff);
596
597
598 } else if (BNX2X_DCBX_OVERWRITE_SETTINGS_ENABLE ==
599 bp->lldp_config_params.overwrite_settings)
600 bp->lldp_config_params.overwrite_settings =
601 BNX2X_DCBX_OVERWRITE_SETTINGS_INVALID;
602}
603
604static void bnx2x_dcbx_admin_mib_updated_params(struct bnx2x *bp,
605 u32 dcbx_lldp_params_offset)
606{
607 struct lldp_admin_mib admin_mib;
608 u32 i, other_traf_type = PREDEFINED_APP_IDX_MAX, traf_type = 0;
609 u32 *buff;
610 u32 offset = dcbx_lldp_params_offset + LLDP_ADMIN_MIB_OFFSET(bp);
611
612 /*shortcuts*/
613 struct dcbx_features *af = &admin_mib.features;
614 struct bnx2x_config_dcbx_params *dp = &bp->dcbx_config_params;
615
616 memset(&admin_mib, 0, sizeof(struct lldp_admin_mib));
617 buff = (u32 *)&admin_mib;
618 /* Read the data first */
619 for (i = 0; i < sizeof(struct lldp_admin_mib); i += 4, buff++)
620 *buff = REG_RD(bp, (offset + i));
621
622
623 if (BNX2X_DCBX_CONFIG_INV_VALUE != dp->admin_dcbx_enable) {
624 if (dp->admin_dcbx_enable)
625 SET_FLAGS(admin_mib.ver_cfg_flags, DCBX_DCBX_ENABLED);
626 else
627 RESET_FLAGS(admin_mib.ver_cfg_flags, DCBX_DCBX_ENABLED);
628 }
629
630 if ((BNX2X_DCBX_OVERWRITE_SETTINGS_ENABLE ==
631 dp->overwrite_settings)) {
632 RESET_FLAGS(admin_mib.ver_cfg_flags, DCBX_CEE_VERSION_MASK);
633 admin_mib.ver_cfg_flags |=
634 (dp->admin_dcbx_version << DCBX_CEE_VERSION_SHIFT) &
635 DCBX_CEE_VERSION_MASK;
636
637 af->ets.enabled = (u8)dp->admin_ets_enable;
638
639 af->pfc.enabled = (u8)dp->admin_pfc_enable;
640
641 /* FOR IEEE dp->admin_tc_supported_tx_enable */
642 if (dp->admin_ets_configuration_tx_enable)
643 SET_FLAGS(admin_mib.ver_cfg_flags,
644 DCBX_ETS_CONFIG_TX_ENABLED);
645 else
646 RESET_FLAGS(admin_mib.ver_cfg_flags,
647 DCBX_ETS_CONFIG_TX_ENABLED);
648 /* For IEEE admin_ets_recommendation_tx_enable */
649 if (dp->admin_pfc_tx_enable)
650 SET_FLAGS(admin_mib.ver_cfg_flags,
651 DCBX_PFC_CONFIG_TX_ENABLED);
652 else
653 RESET_FLAGS(admin_mib.ver_cfg_flags,
654 DCBX_PFC_CONFIG_TX_ENABLED);
655
656 if (dp->admin_application_priority_tx_enable)
657 SET_FLAGS(admin_mib.ver_cfg_flags,
658 DCBX_APP_CONFIG_TX_ENABLED);
659 else
660 RESET_FLAGS(admin_mib.ver_cfg_flags,
661 DCBX_APP_CONFIG_TX_ENABLED);
662
663 if (dp->admin_ets_willing)
664 SET_FLAGS(admin_mib.ver_cfg_flags, DCBX_ETS_WILLING);
665 else
666 RESET_FLAGS(admin_mib.ver_cfg_flags, DCBX_ETS_WILLING);
667 /* For IEEE admin_ets_reco_valid */
668 if (dp->admin_pfc_willing)
669 SET_FLAGS(admin_mib.ver_cfg_flags, DCBX_PFC_WILLING);
670 else
671 RESET_FLAGS(admin_mib.ver_cfg_flags, DCBX_PFC_WILLING);
672
673 if (dp->admin_app_priority_willing)
674 SET_FLAGS(admin_mib.ver_cfg_flags, DCBX_APP_WILLING);
675 else
676 RESET_FLAGS(admin_mib.ver_cfg_flags, DCBX_APP_WILLING);
677
678 for (i = 0 ; i < DCBX_MAX_NUM_PG_BW_ENTRIES; i++) {
679 DCBX_PG_BW_SET(af->ets.pg_bw_tbl, i,
680 (u8)dp->admin_configuration_bw_precentage[i]);
681
682 DP(NETIF_MSG_LINK, "pg_bw_tbl[%d] = %02x\n",
683 i, DCBX_PG_BW_GET(af->ets.pg_bw_tbl, i));
684 }
685
686 for (i = 0; i < DCBX_MAX_NUM_PRI_PG_ENTRIES; i++) {
687 DCBX_PRI_PG_SET(af->ets.pri_pg_tbl, i,
688 (u8)dp->admin_configuration_ets_pg[i]);
689
690 DP(NETIF_MSG_LINK, "pri_pg_tbl[%d] = %02x\n",
691 i, DCBX_PRI_PG_GET(af->ets.pri_pg_tbl, i));
692 }
693
694 /*For IEEE admin_recommendation_bw_precentage
695 *For IEEE admin_recommendation_ets_pg */
696 af->pfc.pri_en_bitmap = (u8)dp->admin_pfc_bitmap;
697 for (i = 0; i < 4; i++) {
698 if (dp->admin_priority_app_table[i].valid) {
699 struct bnx2x_admin_priority_app_table *table =
700 dp->admin_priority_app_table;
701 if ((ETH_TYPE_FCOE == table[i].app_id) &&
702 (TRAFFIC_TYPE_ETH == table[i].traffic_type))
703 traf_type = FCOE_APP_IDX;
704 else if ((TCP_PORT_ISCSI == table[i].app_id) &&
705 (TRAFFIC_TYPE_PORT == table[i].traffic_type))
706 traf_type = ISCSI_APP_IDX;
707 else
708 traf_type = other_traf_type++;
709
710 af->app.app_pri_tbl[traf_type].app_id =
711 table[i].app_id;
712
713 af->app.app_pri_tbl[traf_type].pri_bitmap =
714 (u8)(1 << table[i].priority);
715
716 af->app.app_pri_tbl[traf_type].appBitfield =
717 (DCBX_APP_ENTRY_VALID);
718
719 af->app.app_pri_tbl[traf_type].appBitfield |=
720 (TRAFFIC_TYPE_ETH == table[i].traffic_type) ?
721 DCBX_APP_SF_ETH_TYPE : DCBX_APP_SF_PORT;
722 }
723 }
724
725 af->app.default_pri = (u8)dp->admin_default_priority;
726
727 } else if (BNX2X_DCBX_OVERWRITE_SETTINGS_ENABLE ==
728 dp->overwrite_settings)
729 dp->overwrite_settings = BNX2X_DCBX_OVERWRITE_SETTINGS_INVALID;
730
731 /* Write the data. */
732 buff = (u32 *)&admin_mib;
733 for (i = 0; i < sizeof(struct lldp_admin_mib); i += 4, buff++)
734 REG_WR(bp, (offset + i), *buff);
735}
736
737/* default */
738void bnx2x_dcbx_init_params(struct bnx2x *bp)
739{
740 bp->dcbx_config_params.admin_dcbx_version = 0x0; /* 0 - CEE; 1 - IEEE */
741 bp->dcbx_config_params.dcb_enable = 1;
742 bp->dcbx_config_params.admin_dcbx_enable = 1;
743 bp->dcbx_config_params.admin_ets_willing = 1;
744 bp->dcbx_config_params.admin_pfc_willing = 1;
745 bp->dcbx_config_params.overwrite_settings = 1;
746 bp->dcbx_config_params.admin_ets_enable = 1;
747 bp->dcbx_config_params.admin_pfc_enable = 1;
748 bp->dcbx_config_params.admin_tc_supported_tx_enable = 1;
749 bp->dcbx_config_params.admin_ets_configuration_tx_enable = 1;
750 bp->dcbx_config_params.admin_pfc_tx_enable = 1;
751 bp->dcbx_config_params.admin_application_priority_tx_enable = 1;
752 bp->dcbx_config_params.admin_ets_reco_valid = 1;
753 bp->dcbx_config_params.admin_app_priority_willing = 1;
754 bp->dcbx_config_params.admin_configuration_bw_precentage[0] = 00;
755 bp->dcbx_config_params.admin_configuration_bw_precentage[1] = 50;
756 bp->dcbx_config_params.admin_configuration_bw_precentage[2] = 50;
757 bp->dcbx_config_params.admin_configuration_bw_precentage[3] = 0;
758 bp->dcbx_config_params.admin_configuration_bw_precentage[4] = 0;
759 bp->dcbx_config_params.admin_configuration_bw_precentage[5] = 0;
760 bp->dcbx_config_params.admin_configuration_bw_precentage[6] = 0;
761 bp->dcbx_config_params.admin_configuration_bw_precentage[7] = 0;
762 bp->dcbx_config_params.admin_configuration_ets_pg[0] = 1;
763 bp->dcbx_config_params.admin_configuration_ets_pg[1] = 0;
764 bp->dcbx_config_params.admin_configuration_ets_pg[2] = 0;
765 bp->dcbx_config_params.admin_configuration_ets_pg[3] = 2;
766 bp->dcbx_config_params.admin_configuration_ets_pg[4] = 0;
767 bp->dcbx_config_params.admin_configuration_ets_pg[5] = 0;
768 bp->dcbx_config_params.admin_configuration_ets_pg[6] = 0;
769 bp->dcbx_config_params.admin_configuration_ets_pg[7] = 0;
770 bp->dcbx_config_params.admin_recommendation_bw_precentage[0] = 0;
771 bp->dcbx_config_params.admin_recommendation_bw_precentage[1] = 1;
772 bp->dcbx_config_params.admin_recommendation_bw_precentage[2] = 2;
773 bp->dcbx_config_params.admin_recommendation_bw_precentage[3] = 0;
774 bp->dcbx_config_params.admin_recommendation_bw_precentage[4] = 7;
775 bp->dcbx_config_params.admin_recommendation_bw_precentage[5] = 5;
776 bp->dcbx_config_params.admin_recommendation_bw_precentage[6] = 6;
777 bp->dcbx_config_params.admin_recommendation_bw_precentage[7] = 7;
778 bp->dcbx_config_params.admin_recommendation_ets_pg[0] = 0;
779 bp->dcbx_config_params.admin_recommendation_ets_pg[1] = 1;
780 bp->dcbx_config_params.admin_recommendation_ets_pg[2] = 2;
781 bp->dcbx_config_params.admin_recommendation_ets_pg[3] = 3;
782 bp->dcbx_config_params.admin_recommendation_ets_pg[4] = 4;
783 bp->dcbx_config_params.admin_recommendation_ets_pg[5] = 5;
784 bp->dcbx_config_params.admin_recommendation_ets_pg[6] = 6;
785 bp->dcbx_config_params.admin_recommendation_ets_pg[7] = 7;
786 bp->dcbx_config_params.admin_pfc_bitmap = 0x8; /* FCoE(3) enable */
787 bp->dcbx_config_params.admin_priority_app_table[0].valid = 1;
788 bp->dcbx_config_params.admin_priority_app_table[1].valid = 1;
789 bp->dcbx_config_params.admin_priority_app_table[2].valid = 0;
790 bp->dcbx_config_params.admin_priority_app_table[3].valid = 0;
791 bp->dcbx_config_params.admin_priority_app_table[0].priority = 3;
792 bp->dcbx_config_params.admin_priority_app_table[1].priority = 0;
793 bp->dcbx_config_params.admin_priority_app_table[2].priority = 0;
794 bp->dcbx_config_params.admin_priority_app_table[3].priority = 0;
795 bp->dcbx_config_params.admin_priority_app_table[0].traffic_type = 0;
796 bp->dcbx_config_params.admin_priority_app_table[1].traffic_type = 1;
797 bp->dcbx_config_params.admin_priority_app_table[2].traffic_type = 0;
798 bp->dcbx_config_params.admin_priority_app_table[3].traffic_type = 0;
799 bp->dcbx_config_params.admin_priority_app_table[0].app_id = 0x8906;
800 bp->dcbx_config_params.admin_priority_app_table[1].app_id = 3260;
801 bp->dcbx_config_params.admin_priority_app_table[2].app_id = 0;
802 bp->dcbx_config_params.admin_priority_app_table[3].app_id = 0;
803 bp->dcbx_config_params.admin_default_priority =
804 bp->dcbx_config_params.admin_priority_app_table[1].priority;
805}
806
807void bnx2x_dcbx_init(struct bnx2x *bp)
808{
809 u32 dcbx_lldp_params_offset = SHMEM_LLDP_DCBX_PARAMS_NONE;
810 /* validate:
811 * chip of good for dcbx version,
812 * dcb is wanted
813 * the function is pmf
814 * shmem2 contains DCBX support fields
815 */
816 DP(NETIF_MSG_LINK, "dcb_enable %d bp->port.pmf %d\n",
817 bp->dcbx_config_params.dcb_enable, bp->port.pmf);
818
819 if (CHIP_IS_E2(bp) && !CHIP_MODE_IS_4_PORT(bp) &&
820 bp->dcbx_config_params.dcb_enable &&
821 bp->port.pmf &&
822 SHMEM2_HAS(bp, dcbx_lldp_params_offset)) {
823 dcbx_lldp_params_offset = SHMEM2_RD(bp,
824 dcbx_lldp_params_offset);
825 DP(NETIF_MSG_LINK, "dcbx_lldp_params_offset 0x%x\n",
826 dcbx_lldp_params_offset);
827 if (SHMEM_LLDP_DCBX_PARAMS_NONE != dcbx_lldp_params_offset) {
828 bnx2x_dcbx_lldp_updated_params(bp,
829 dcbx_lldp_params_offset);
830
831 bnx2x_dcbx_admin_mib_updated_params(bp,
832 dcbx_lldp_params_offset);
833
834 /* set default configuration BC has */
835 bnx2x_dcbx_set_params(bp,
836 BNX2X_DCBX_STATE_NEG_RECEIVED);
837
838 bnx2x_fw_command(bp,
839 DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG, 0);
840 }
841 }
842}
843
844void bnx2x_dcb_init_intmem_pfc(struct bnx2x *bp)
845{
846 struct priority_cos pricos[MAX_PFC_TRAFFIC_TYPES];
847 u32 i = 0, addr;
848 memset(pricos, 0, sizeof(pricos));
849 /* Default initialization */
850 for (i = 0; i < MAX_PFC_TRAFFIC_TYPES; i++)
851 pricos[i].priority = LLFC_TRAFFIC_TYPE_TO_PRIORITY_UNMAPPED;
852
853 /* Store per port struct to internal memory */
854 addr = BAR_XSTRORM_INTMEM +
855 XSTORM_CMNG_PER_PORT_VARS_OFFSET(BP_PORT(bp)) +
856 offsetof(struct cmng_struct_per_port,
857 traffic_type_to_priority_cos);
858 __storm_memset_struct(bp, addr, sizeof(pricos), (u32 *)pricos);
859
860
861 /* LLFC disabled.*/
862 REG_WR8(bp , BAR_XSTRORM_INTMEM +
863 XSTORM_CMNG_PER_PORT_VARS_OFFSET(BP_PORT(bp)) +
864 offsetof(struct cmng_struct_per_port, llfc_mode),
865 LLFC_MODE_NONE);
866
867 /* DCBX disabled.*/
868 REG_WR8(bp , BAR_XSTRORM_INTMEM +
869 XSTORM_CMNG_PER_PORT_VARS_OFFSET(BP_PORT(bp)) +
870 offsetof(struct cmng_struct_per_port, dcb_enabled),
871 DCB_DISABLED);
872}
873
874static void
875bnx2x_dcbx_print_cos_params(struct bnx2x *bp,
876 struct flow_control_configuration *pfc_fw_cfg)
877{
878 u8 pri = 0;
879 u8 cos = 0;
880
881 DP(NETIF_MSG_LINK,
882 "pfc_fw_cfg->dcb_version %x\n", pfc_fw_cfg->dcb_version);
883 DP(NETIF_MSG_LINK,
884 "pdev->params.dcbx_port_params.pfc."
885 "priority_non_pauseable_mask %x\n",
886 bp->dcbx_port_params.pfc.priority_non_pauseable_mask);
887
888 for (cos = 0 ; cos < bp->dcbx_port_params.ets.num_of_cos ; cos++) {
889 DP(NETIF_MSG_LINK, "pdev->params.dcbx_port_params.ets."
890 "cos_params[%d].pri_bitmask %x\n", cos,
891 bp->dcbx_port_params.ets.cos_params[cos].pri_bitmask);
892
893 DP(NETIF_MSG_LINK, "pdev->params.dcbx_port_params.ets."
894 "cos_params[%d].bw_tbl %x\n", cos,
895 bp->dcbx_port_params.ets.cos_params[cos].bw_tbl);
896
897 DP(NETIF_MSG_LINK, "pdev->params.dcbx_port_params.ets."
898 "cos_params[%d].strict %x\n", cos,
899 bp->dcbx_port_params.ets.cos_params[cos].strict);
900
901 DP(NETIF_MSG_LINK, "pdev->params.dcbx_port_params.ets."
902 "cos_params[%d].pauseable %x\n", cos,
903 bp->dcbx_port_params.ets.cos_params[cos].pauseable);
904 }
905
906 for (pri = 0; pri < LLFC_DRIVER_TRAFFIC_TYPE_MAX; pri++) {
907 DP(NETIF_MSG_LINK,
908 "pfc_fw_cfg->traffic_type_to_priority_cos[%d]."
909 "priority %x\n", pri,
910 pfc_fw_cfg->traffic_type_to_priority_cos[pri].priority);
911
912 DP(NETIF_MSG_LINK,
913 "pfc_fw_cfg->traffic_type_to_priority_cos[%d].cos %x\n",
914 pri, pfc_fw_cfg->traffic_type_to_priority_cos[pri].cos);
915 }
916}
917
918/* fills help_data according to pg_info */
919static void bnx2x_dcbx_get_num_pg_traf_type(struct bnx2x *bp,
920 u32 *pg_pri_orginal_spread,
921 struct pg_help_data *help_data)
922{
923 bool pg_found = false;
924 u32 i, traf_type, add_traf_type, add_pg;
925 u32 *ttp = bp->dcbx_port_params.app.traffic_type_priority;
926 struct pg_entry_help_data *data = help_data->data; /*shotcut*/
927
928 /* Set to invalid */
929 for (i = 0; i < LLFC_DRIVER_TRAFFIC_TYPE_MAX; i++)
930 data[i].pg = DCBX_ILLEGAL_PG;
931
932 for (add_traf_type = 0;
933 add_traf_type < LLFC_DRIVER_TRAFFIC_TYPE_MAX; add_traf_type++) {
934 pg_found = false;
935 if (ttp[add_traf_type] < MAX_PFC_PRIORITIES) {
936 add_pg = (u8)pg_pri_orginal_spread[ttp[add_traf_type]];
937 for (traf_type = 0;
938 traf_type < LLFC_DRIVER_TRAFFIC_TYPE_MAX;
939 traf_type++) {
940 if (data[traf_type].pg == add_pg) {
941 if (!(data[traf_type].pg_priority &
942 (1 << ttp[add_traf_type])))
943 data[traf_type].
944 num_of_dif_pri++;
945 data[traf_type].pg_priority |=
946 (1 << ttp[add_traf_type]);
947 pg_found = true;
948 break;
949 }
950 }
951 if (false == pg_found) {
952 data[help_data->num_of_pg].pg = add_pg;
953 data[help_data->num_of_pg].pg_priority =
954 (1 << ttp[add_traf_type]);
955 data[help_data->num_of_pg].num_of_dif_pri = 1;
956 help_data->num_of_pg++;
957 }
958 }
959 DP(NETIF_MSG_LINK,
960 "add_traf_type %d pg_found %s num_of_pg %d\n",
961 add_traf_type, (false == pg_found) ? "NO" : "YES",
962 help_data->num_of_pg);
963 }
964}
965
966
967/*******************************************************************************
968 * Description: single priority group
969 *
970 * Return:
971 ******************************************************************************/
972static void bnx2x_dcbx_ets_disabled_entry_data(struct bnx2x *bp,
973 struct cos_help_data *cos_data,
974 u32 pri_join_mask)
975{
976 /* Only one priority than only one COS */
977 cos_data->data[0].pausable =
978 IS_DCBX_PFC_PRI_ONLY_PAUSE(bp, pri_join_mask);
979 cos_data->data[0].pri_join_mask = pri_join_mask;
980 cos_data->data[0].cos_bw = 100;
981 cos_data->num_of_cos = 1;
982}
983
984/*******************************************************************************
985 * Description: updating the cos bw
986 *
987 * Return:
988 ******************************************************************************/
989static inline void bnx2x_dcbx_add_to_cos_bw(struct bnx2x *bp,
990 struct cos_entry_help_data *data,
991 u8 pg_bw)
992{
993 if (data->cos_bw == DCBX_INVALID_COS_BW)
994 data->cos_bw = pg_bw;
995 else
996 data->cos_bw += pg_bw;
997}
998
999/*******************************************************************************
1000 * Description: single priority group
1001 *
1002 * Return:
1003 ******************************************************************************/
1004static void bnx2x_dcbx_separate_pauseable_from_non(struct bnx2x *bp,
1005 struct cos_help_data *cos_data,
1006 u32 *pg_pri_orginal_spread,
1007 struct dcbx_ets_feature *ets)
1008{
1009 u32 pri_tested = 0;
1010 u8 i = 0;
1011 u8 entry = 0;
1012 u8 pg_entry = 0;
1013 u8 num_of_pri = LLFC_DRIVER_TRAFFIC_TYPE_MAX;
1014
1015 cos_data->data[0].pausable = true;
1016 cos_data->data[1].pausable = false;
1017 cos_data->data[0].pri_join_mask = cos_data->data[1].pri_join_mask = 0;
1018
1019 for (i = 0 ; i < num_of_pri ; i++) {
1020 pri_tested = 1 << bp->dcbx_port_params.
1021 app.traffic_type_priority[i];
1022
1023 if (pri_tested & DCBX_PFC_PRI_NON_PAUSE_MASK(bp)) {
1024 cos_data->data[1].pri_join_mask |= pri_tested;
1025 entry = 1;
1026 } else {
1027 cos_data->data[0].pri_join_mask |= pri_tested;
1028 entry = 0;
1029 }
1030 pg_entry = (u8)pg_pri_orginal_spread[bp->dcbx_port_params.
1031 app.traffic_type_priority[i]];
1032 /* There can be only one strict pg */
1033 if (pg_entry < DCBX_MAX_NUM_PG_BW_ENTRIES)
1034 bnx2x_dcbx_add_to_cos_bw(bp, &cos_data->data[entry],
1035 DCBX_PG_BW_GET(ets->pg_bw_tbl, pg_entry));
1036 else
1037 /* If we join a group and one is strict
1038 * than the bw rulls */
1039 cos_data->data[entry].strict =
1040 BNX2X_DCBX_COS_HIGH_STRICT;
1041 }
1042 if ((0 == cos_data->data[0].pri_join_mask) &&
1043 (0 == cos_data->data[1].pri_join_mask))
1044 BNX2X_ERR("dcbx error: Both groups must have priorities\n");
1045}
1046
1047
1048#ifndef POWER_OF_2
1049#define POWER_OF_2(x) ((0 != x) && (0 == (x & (x-1))))
1050#endif
1051
1052static void bxn2x_dcbx_single_pg_to_cos_params(struct bnx2x *bp,
1053 struct pg_help_data *pg_help_data,
1054 struct cos_help_data *cos_data,
1055 u32 pri_join_mask,
1056 u8 num_of_dif_pri)
1057{
1058 u8 i = 0;
1059 u32 pri_tested = 0;
1060 u32 pri_mask_without_pri = 0;
1061 u32 *ttp = bp->dcbx_port_params.app.traffic_type_priority;
1062 /*debug*/
1063 if (num_of_dif_pri == 1) {
1064 bnx2x_dcbx_ets_disabled_entry_data(bp, cos_data, pri_join_mask);
1065 return;
1066 }
1067 /* single priority group */
1068 if (pg_help_data->data[0].pg < DCBX_MAX_NUM_PG_BW_ENTRIES) {
1069 /* If there are both pauseable and non-pauseable priorities,
1070 * the pauseable priorities go to the first queue and
1071 * the non-pauseable priorities go to the second queue.
1072 */
1073 if (IS_DCBX_PFC_PRI_MIX_PAUSE(bp, pri_join_mask)) {
1074 /* Pauseable */
1075 cos_data->data[0].pausable = true;
1076 /* Non pauseable.*/
1077 cos_data->data[1].pausable = false;
1078
1079 if (2 == num_of_dif_pri) {
1080 cos_data->data[0].cos_bw = 50;
1081 cos_data->data[1].cos_bw = 50;
1082 }
1083
1084 if (3 == num_of_dif_pri) {
1085 if (POWER_OF_2(DCBX_PFC_PRI_GET_PAUSE(bp,
1086 pri_join_mask))) {
1087 cos_data->data[0].cos_bw = 33;
1088 cos_data->data[1].cos_bw = 67;
1089 } else {
1090 cos_data->data[0].cos_bw = 67;
1091 cos_data->data[1].cos_bw = 33;
1092 }
1093 }
1094
1095 } else if (IS_DCBX_PFC_PRI_ONLY_PAUSE(bp, pri_join_mask)) {
1096 /* If there are only pauseable priorities,
1097 * then one/two priorities go to the first queue
1098 * and one priority goes to the second queue.
1099 */
1100 if (2 == num_of_dif_pri) {
1101 cos_data->data[0].cos_bw = 50;
1102 cos_data->data[1].cos_bw = 50;
1103 } else {
1104 cos_data->data[0].cos_bw = 67;
1105 cos_data->data[1].cos_bw = 33;
1106 }
1107 cos_data->data[1].pausable = true;
1108 cos_data->data[0].pausable = true;
1109 /* All priorities except FCOE */
1110 cos_data->data[0].pri_join_mask = (pri_join_mask &
1111 ((u8)~(1 << ttp[LLFC_TRAFFIC_TYPE_FCOE])));
1112 /* Only FCOE priority.*/
1113 cos_data->data[1].pri_join_mask =
1114 (1 << ttp[LLFC_TRAFFIC_TYPE_FCOE]);
1115 } else
1116 /* If there are only non-pauseable priorities,
1117 * they will all go to the same queue.
1118 */
1119 bnx2x_dcbx_ets_disabled_entry_data(bp,
1120 cos_data, pri_join_mask);
1121 } else {
1122 /* priority group which is not BW limited (PG#15):*/
1123 if (IS_DCBX_PFC_PRI_MIX_PAUSE(bp, pri_join_mask)) {
1124 /* If there are both pauseable and non-pauseable
1125 * priorities, the pauseable priorities go to the first
1126 * queue and the non-pauseable priorities
1127 * go to the second queue.
1128 */
1129 if (DCBX_PFC_PRI_GET_PAUSE(bp, pri_join_mask) >
1130 DCBX_PFC_PRI_GET_NON_PAUSE(bp, pri_join_mask)) {
1131 cos_data->data[0].strict =
1132 BNX2X_DCBX_COS_HIGH_STRICT;
1133 cos_data->data[1].strict =
1134 BNX2X_DCBX_COS_LOW_STRICT;
1135 } else {
1136 cos_data->data[0].strict =
1137 BNX2X_DCBX_COS_LOW_STRICT;
1138 cos_data->data[1].strict =
1139 BNX2X_DCBX_COS_HIGH_STRICT;
1140 }
1141 /* Pauseable */
1142 cos_data->data[0].pausable = true;
1143 /* Non pause-able.*/
1144 cos_data->data[1].pausable = false;
1145 } else {
1146 /* If there are only pauseable priorities or
1147 * only non-pauseable,* the lower priorities go
1148 * to the first queue and the higherpriorities go
1149 * to the second queue.
1150 */
1151 cos_data->data[0].pausable =
1152 cos_data->data[1].pausable =
1153 IS_DCBX_PFC_PRI_ONLY_PAUSE(bp, pri_join_mask);
1154
1155 for (i = 0 ; i < LLFC_DRIVER_TRAFFIC_TYPE_MAX; i++) {
1156 pri_tested = 1 << bp->dcbx_port_params.
1157 app.traffic_type_priority[i];
1158 /* Remove priority tested */
1159 pri_mask_without_pri =
1160 (pri_join_mask & ((u8)(~pri_tested)));
1161 if (pri_mask_without_pri < pri_tested)
1162 break;
1163 }
1164
1165 if (i == LLFC_DRIVER_TRAFFIC_TYPE_MAX)
1166 BNX2X_ERR("Invalid value for pri_join_mask -"
1167 " could not find a priority\n");
1168
1169 cos_data->data[0].pri_join_mask = pri_mask_without_pri;
1170 cos_data->data[1].pri_join_mask = pri_tested;
1171 /* Both queues are strict priority,
1172 * and that with the highest priority
1173 * gets the highest strict priority in the arbiter.
1174 */
1175 cos_data->data[0].strict = BNX2X_DCBX_COS_LOW_STRICT;
1176 cos_data->data[1].strict = BNX2X_DCBX_COS_HIGH_STRICT;
1177 }
1178 }
1179}
1180
1181static void bnx2x_dcbx_two_pg_to_cos_params(
1182 struct bnx2x *bp,
1183 struct pg_help_data *pg_help_data,
1184 struct dcbx_ets_feature *ets,
1185 struct cos_help_data *cos_data,
1186 u32 *pg_pri_orginal_spread,
1187 u32 pri_join_mask,
1188 u8 num_of_dif_pri)
1189{
1190 u8 i = 0;
1191 u8 pg[E2_NUM_OF_COS] = {0};
1192
1193 /* If there are both pauseable and non-pauseable priorities,
1194 * the pauseable priorities go to the first queue and
1195 * the non-pauseable priorities go to the second queue.
1196 */
1197 if (IS_DCBX_PFC_PRI_MIX_PAUSE(bp, pri_join_mask)) {
1198 if (IS_DCBX_PFC_PRI_MIX_PAUSE(bp,
1199 pg_help_data->data[0].pg_priority) ||
1200 IS_DCBX_PFC_PRI_MIX_PAUSE(bp,
1201 pg_help_data->data[1].pg_priority)) {
1202 /* If one PG contains both pauseable and
1203 * non-pauseable priorities then ETS is disabled.
1204 */
1205 bnx2x_dcbx_separate_pauseable_from_non(bp, cos_data,
1206 pg_pri_orginal_spread, ets);
1207 bp->dcbx_port_params.ets.enabled = false;
1208 return;
1209 }
1210
1211 /* Pauseable */
1212 cos_data->data[0].pausable = true;
1213 /* Non pauseable. */
1214 cos_data->data[1].pausable = false;
1215 if (IS_DCBX_PFC_PRI_ONLY_PAUSE(bp,
1216 pg_help_data->data[0].pg_priority)) {
1217 /* 0 is pauseable */
1218 cos_data->data[0].pri_join_mask =
1219 pg_help_data->data[0].pg_priority;
1220 pg[0] = pg_help_data->data[0].pg;
1221 cos_data->data[1].pri_join_mask =
1222 pg_help_data->data[1].pg_priority;
1223 pg[1] = pg_help_data->data[1].pg;
1224 } else {/* 1 is pauseable */
1225 cos_data->data[0].pri_join_mask =
1226 pg_help_data->data[1].pg_priority;
1227 pg[0] = pg_help_data->data[1].pg;
1228 cos_data->data[1].pri_join_mask =
1229 pg_help_data->data[0].pg_priority;
1230 pg[1] = pg_help_data->data[0].pg;
1231 }
1232 } else {
1233 /* If there are only pauseable priorities or
1234 * only non-pauseable, each PG goes to a queue.
1235 */
1236 cos_data->data[0].pausable = cos_data->data[1].pausable =
1237 IS_DCBX_PFC_PRI_ONLY_PAUSE(bp, pri_join_mask);
1238 cos_data->data[0].pri_join_mask =
1239 pg_help_data->data[0].pg_priority;
1240 pg[0] = pg_help_data->data[0].pg;
1241 cos_data->data[1].pri_join_mask =
1242 pg_help_data->data[1].pg_priority;
1243 pg[1] = pg_help_data->data[1].pg;
1244 }
1245
1246 /* There can be only one strict pg */
1247 for (i = 0 ; i < E2_NUM_OF_COS; i++) {
1248 if (pg[i] < DCBX_MAX_NUM_PG_BW_ENTRIES)
1249 cos_data->data[i].cos_bw =
1250 DCBX_PG_BW_GET(ets->pg_bw_tbl, pg[i]);
1251 else
1252 cos_data->data[i].strict = BNX2X_DCBX_COS_HIGH_STRICT;
1253 }
1254}
1255
1256/*******************************************************************************
1257 * Description: Still
1258 *
1259 * Return:
1260 ******************************************************************************/
1261static void bnx2x_dcbx_three_pg_to_cos_params(
1262 struct bnx2x *bp,
1263 struct pg_help_data *pg_help_data,
1264 struct dcbx_ets_feature *ets,
1265 struct cos_help_data *cos_data,
1266 u32 *pg_pri_orginal_spread,
1267 u32 pri_join_mask,
1268 u8 num_of_dif_pri)
1269{
1270 u8 i = 0;
1271 u32 pri_tested = 0;
1272 u8 entry = 0;
1273 u8 pg_entry = 0;
1274 bool b_found_strict = false;
1275 u8 num_of_pri = LLFC_DRIVER_TRAFFIC_TYPE_MAX;
1276
1277 cos_data->data[0].pri_join_mask = cos_data->data[1].pri_join_mask = 0;
1278 /* If there are both pauseable and non-pauseable priorities,
1279 * the pauseable priorities go to the first queue and the
1280 * non-pauseable priorities go to the second queue.
1281 */
1282 if (IS_DCBX_PFC_PRI_MIX_PAUSE(bp, pri_join_mask))
1283 bnx2x_dcbx_separate_pauseable_from_non(bp,
1284 cos_data, pg_pri_orginal_spread, ets);
1285 else {
1286 /* If two BW-limited PG-s were combined to one queue,
1287 * the BW is their sum.
1288 *
1289 * If there are only pauseable priorities or only non-pauseable,
1290 * and there are both BW-limited and non-BW-limited PG-s,
1291 * the BW-limited PG/s go to one queue and the non-BW-limited
1292 * PG/s go to the second queue.
1293 *
1294 * If there are only pauseable priorities or only non-pauseable
1295 * and all are BW limited, then two priorities go to the first
1296 * queue and one priority goes to the second queue.
1297 *
1298 * We will join this two cases:
1299 * if one is BW limited it will go to the secoend queue
1300 * otherwise the last priority will get it
1301 */
1302
1303 cos_data->data[0].pausable = cos_data->data[1].pausable =
1304 IS_DCBX_PFC_PRI_ONLY_PAUSE(bp, pri_join_mask);
1305
1306 for (i = 0 ; i < num_of_pri; i++) {
1307 pri_tested = 1 << bp->dcbx_port_params.
1308 app.traffic_type_priority[i];
1309 pg_entry = (u8)pg_pri_orginal_spread[bp->
1310 dcbx_port_params.app.traffic_type_priority[i]];
1311
1312 if (pg_entry < DCBX_MAX_NUM_PG_BW_ENTRIES) {
1313 entry = 0;
1314
1315 if (i == (num_of_pri-1) &&
1316 false == b_found_strict)
1317 /* last entry will be handled separately
1318 * If no priority is strict than last
1319 * enty goes to last queue.*/
1320 entry = 1;
1321 cos_data->data[entry].pri_join_mask |=
1322 pri_tested;
1323 bnx2x_dcbx_add_to_cos_bw(bp,
1324 &cos_data->data[entry],
1325 DCBX_PG_BW_GET(ets->pg_bw_tbl,
1326 pg_entry));
1327 } else {
1328 b_found_strict = true;
1329 cos_data->data[1].pri_join_mask |= pri_tested;
1330 /* If we join a group and one is strict
1331 * than the bw rulls */
1332 cos_data->data[1].strict =
1333 BNX2X_DCBX_COS_HIGH_STRICT;
1334 }
1335 }
1336 }
1337}
1338
1339
1340static void bnx2x_dcbx_fill_cos_params(struct bnx2x *bp,
1341 struct pg_help_data *help_data,
1342 struct dcbx_ets_feature *ets,
1343 u32 *pg_pri_orginal_spread)
1344{
1345 struct cos_help_data cos_data ;
1346 u8 i = 0;
1347 u32 pri_join_mask = 0;
1348 u8 num_of_dif_pri = 0;
1349
1350 memset(&cos_data, 0, sizeof(cos_data));
1351 /* Validate the pg value */
1352 for (i = 0; i < help_data->num_of_pg ; i++) {
1353 if (DCBX_STRICT_PRIORITY != help_data->data[i].pg &&
1354 DCBX_MAX_NUM_PG_BW_ENTRIES <= help_data->data[i].pg)
1355 BNX2X_ERR("Invalid pg[%d] data %x\n", i,
1356 help_data->data[i].pg);
1357 pri_join_mask |= help_data->data[i].pg_priority;
1358 num_of_dif_pri += help_data->data[i].num_of_dif_pri;
1359 }
1360
1361 /* default settings */
1362 cos_data.num_of_cos = 2;
1363 for (i = 0; i < E2_NUM_OF_COS ; i++) {
1364 cos_data.data[i].pri_join_mask = pri_join_mask;
1365 cos_data.data[i].pausable = false;
1366 cos_data.data[i].strict = BNX2X_DCBX_COS_NOT_STRICT;
1367 cos_data.data[i].cos_bw = DCBX_INVALID_COS_BW;
1368 }
1369
1370 switch (help_data->num_of_pg) {
1371 case 1:
1372
1373 bxn2x_dcbx_single_pg_to_cos_params(
1374 bp,
1375 help_data,
1376 &cos_data,
1377 pri_join_mask,
1378 num_of_dif_pri);
1379 break;
1380 case 2:
1381 bnx2x_dcbx_two_pg_to_cos_params(
1382 bp,
1383 help_data,
1384 ets,
1385 &cos_data,
1386 pg_pri_orginal_spread,
1387 pri_join_mask,
1388 num_of_dif_pri);
1389 break;
1390
1391 case 3:
1392 bnx2x_dcbx_three_pg_to_cos_params(
1393 bp,
1394 help_data,
1395 ets,
1396 &cos_data,
1397 pg_pri_orginal_spread,
1398 pri_join_mask,
1399 num_of_dif_pri);
1400
1401 break;
1402 default:
1403 BNX2X_ERR("Wrong pg_help_data.num_of_pg\n");
1404 bnx2x_dcbx_ets_disabled_entry_data(bp,
1405 &cos_data, pri_join_mask);
1406 }
1407
1408 for (i = 0; i < cos_data.num_of_cos ; i++) {
1409 struct bnx2x_dcbx_cos_params *params =
1410 &bp->dcbx_port_params.ets.cos_params[i];
1411
1412 params->pauseable = cos_data.data[i].pausable;
1413 params->strict = cos_data.data[i].strict;
1414 params->bw_tbl = cos_data.data[i].cos_bw;
1415 if (params->pauseable) {
1416 params->pri_bitmask =
1417 DCBX_PFC_PRI_GET_PAUSE(bp,
1418 cos_data.data[i].pri_join_mask);
1419 DP(NETIF_MSG_LINK, "COS %d PAUSABLE prijoinmask 0x%x\n",
1420 i, cos_data.data[i].pri_join_mask);
1421 } else {
1422 params->pri_bitmask =
1423 DCBX_PFC_PRI_GET_NON_PAUSE(bp,
1424 cos_data.data[i].pri_join_mask);
1425 DP(NETIF_MSG_LINK, "COS %d NONPAUSABLE prijoinmask "
1426 "0x%x\n",
1427 i, cos_data.data[i].pri_join_mask);
1428 }
1429 }
1430
1431 bp->dcbx_port_params.ets.num_of_cos = cos_data.num_of_cos ;
1432}
1433
1434static void bnx2x_dcbx_get_ets_pri_pg_tbl(struct bnx2x *bp,
1435 u32 *set_configuration_ets_pg,
1436 u32 *pri_pg_tbl)
1437{
1438 int i;
1439
1440 for (i = 0; i < DCBX_MAX_NUM_PRI_PG_ENTRIES; i++) {
1441 set_configuration_ets_pg[i] = DCBX_PRI_PG_GET(pri_pg_tbl, i);
1442
1443 DP(NETIF_MSG_LINK, "set_configuration_ets_pg[%d] = 0x%x\n",
1444 i, set_configuration_ets_pg[i]);
1445 }
1446}
1447
1448/*******************************************************************************
1449 * Description: Fill pfc_config struct that will be sent in DCBX start ramrod
1450 *
1451 * Return:
1452 ******************************************************************************/
1453static void bnx2x_pfc_fw_struct_e2(struct bnx2x *bp)
1454{
1455 struct flow_control_configuration *pfc_fw_cfg = 0;
1456 u16 pri_bit = 0;
1457 u8 cos = 0, pri = 0;
1458 struct priority_cos *tt2cos;
1459 u32 *ttp = bp->dcbx_port_params.app.traffic_type_priority;
1460
1461 pfc_fw_cfg = (struct flow_control_configuration *)
1462 bnx2x_sp(bp, pfc_config);
1463 memset(pfc_fw_cfg, 0, sizeof(struct flow_control_configuration));
1464
1465 /*shortcut*/
1466 tt2cos = pfc_fw_cfg->traffic_type_to_priority_cos;
1467
1468 /* Fw version should be incremented each update */
1469 pfc_fw_cfg->dcb_version = ++bp->dcb_version;
1470 pfc_fw_cfg->dcb_enabled = DCB_ENABLED;
1471
1472 /* Default initialization */
1473 for (pri = 0; pri < MAX_PFC_TRAFFIC_TYPES ; pri++) {
1474 tt2cos[pri].priority = LLFC_TRAFFIC_TYPE_TO_PRIORITY_UNMAPPED;
1475 tt2cos[pri].cos = 0;
1476 }
1477
1478 /* Fill priority parameters */
1479 for (pri = 0; pri < LLFC_DRIVER_TRAFFIC_TYPE_MAX; pri++) {
1480 tt2cos[pri].priority = ttp[pri];
1481 pri_bit = 1 << tt2cos[pri].priority;
1482
1483 /* Fill COS parameters based on COS calculated to
1484 * make it more generally for future use */
1485 for (cos = 0; cos < bp->dcbx_port_params.ets.num_of_cos; cos++)
1486 if (bp->dcbx_port_params.ets.cos_params[cos].
1487 pri_bitmask & pri_bit)
1488 tt2cos[pri].cos = cos;
1489 }
1490 bnx2x_dcbx_print_cos_params(bp, pfc_fw_cfg);
1491}
diff --git a/drivers/net/bnx2x/bnx2x_dcb.h b/drivers/net/bnx2x/bnx2x_dcb.h
new file mode 100644
index 000000000000..8dea56b511f5
--- /dev/null
+++ b/drivers/net/bnx2x/bnx2x_dcb.h
@@ -0,0 +1,193 @@
1/* bnx2x_dcb.h: Broadcom Everest network driver.
2 *
3 * Copyright 2009-2010 Broadcom Corporation
4 *
5 * Unless you and Broadcom execute a separate written software license
6 * agreement governing use of this software, this software is licensed to you
7 * under the terms of the GNU General Public License version 2, available
8 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
9 *
10 * Notwithstanding the above, under no circumstances may you combine this
11 * software in any way with any other Broadcom software provided under a
12 * license other than the GPL, without Broadcom's express prior written
13 * consent.
14 *
15 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
16 * Written by: Dmitry Kravkov
17 *
18 */
19#ifndef BNX2X_DCB_H
20#define BNX2X_DCB_H
21
22#include "bnx2x_hsi.h"
23
24#define LLFC_DRIVER_TRAFFIC_TYPE_MAX 3 /* NW, iSCSI, FCoE */
25struct bnx2x_dcbx_app_params {
26 u32 enabled;
27 u32 traffic_type_priority[LLFC_DRIVER_TRAFFIC_TYPE_MAX];
28};
29
30#define E2_NUM_OF_COS 2
31#define BNX2X_DCBX_COS_NOT_STRICT 0
32#define BNX2X_DCBX_COS_LOW_STRICT 1
33#define BNX2X_DCBX_COS_HIGH_STRICT 2
34
35struct bnx2x_dcbx_cos_params {
36 u32 bw_tbl;
37 u32 pri_bitmask;
38 u8 strict;
39 u8 pauseable;
40};
41
42struct bnx2x_dcbx_pg_params {
43 u32 enabled;
44 u8 num_of_cos; /* valid COS entries */
45 struct bnx2x_dcbx_cos_params cos_params[E2_NUM_OF_COS];
46};
47
48struct bnx2x_dcbx_pfc_params {
49 u32 enabled;
50 u32 priority_non_pauseable_mask;
51};
52
53struct bnx2x_dcbx_port_params {
54 u32 dcbx_enabled;
55 struct bnx2x_dcbx_pfc_params pfc;
56 struct bnx2x_dcbx_pg_params ets;
57 struct bnx2x_dcbx_app_params app;
58};
59
60#define BNX2X_DCBX_CONFIG_INV_VALUE (0xFFFFFFFF)
61#define BNX2X_DCBX_OVERWRITE_SETTINGS_DISABLE 0
62#define BNX2X_DCBX_OVERWRITE_SETTINGS_ENABLE 1
63#define BNX2X_DCBX_OVERWRITE_SETTINGS_INVALID (BNX2X_DCBX_CONFIG_INV_VALUE)
64
65/*******************************************************************************
66 * LLDP protocol configuration parameters.
67 ******************************************************************************/
68struct bnx2x_config_lldp_params {
69 u32 overwrite_settings;
70 u32 msg_tx_hold;
71 u32 msg_fast_tx;
72 u32 tx_credit_max;
73 u32 msg_tx_interval;
74 u32 tx_fast;
75};
76
77struct bnx2x_admin_priority_app_table {
78 u32 valid;
79 u32 priority;
80#define INVALID_TRAFFIC_TYPE_PRIORITY (0xFFFFFFFF)
81 u32 traffic_type;
82#define TRAFFIC_TYPE_ETH 0
83#define TRAFFIC_TYPE_PORT 1
84 u32 app_id;
85};
86
87/*******************************************************************************
88 * DCBX protocol configuration parameters.
89 ******************************************************************************/
90struct bnx2x_config_dcbx_params {
91 u32 dcb_enable;
92 u32 admin_dcbx_enable;
93 u32 overwrite_settings;
94 u32 admin_dcbx_version;
95 u32 admin_ets_enable;
96 u32 admin_pfc_enable;
97 u32 admin_tc_supported_tx_enable;
98 u32 admin_ets_configuration_tx_enable;
99 u32 admin_ets_recommendation_tx_enable;
100 u32 admin_pfc_tx_enable;
101 u32 admin_application_priority_tx_enable;
102 u32 admin_ets_willing;
103 u32 admin_ets_reco_valid;
104 u32 admin_pfc_willing;
105 u32 admin_app_priority_willing;
106 u32 admin_configuration_bw_precentage[8];
107 u32 admin_configuration_ets_pg[8];
108 u32 admin_recommendation_bw_precentage[8];
109 u32 admin_recommendation_ets_pg[8];
110 u32 admin_pfc_bitmap;
111 struct bnx2x_admin_priority_app_table admin_priority_app_table[4];
112 u32 admin_default_priority;
113};
114
115#define GET_FLAGS(flags, bits) ((flags) & (bits))
116#define SET_FLAGS(flags, bits) ((flags) |= (bits))
117#define RESET_FLAGS(flags, bits) ((flags) &= ~(bits))
118
119enum {
120 DCBX_READ_LOCAL_MIB,
121 DCBX_READ_REMOTE_MIB
122};
123
124#define ETH_TYPE_FCOE (0x8906)
125#define TCP_PORT_ISCSI (0xCBC)
126
127#define PFC_VALUE_FRAME_SIZE (512)
128#define PFC_QUANTA_IN_NANOSEC_FROM_SPEED_MEGA(mega_speed) \
129 ((1000 * PFC_VALUE_FRAME_SIZE)/(mega_speed))
130
131#define PFC_BRB1_REG_HIGH_LLFC_LOW_THRESHOLD 130
132#define PFC_BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD 170
133
134
135
136struct cos_entry_help_data {
137 u32 pri_join_mask;
138 u32 cos_bw;
139 u8 strict;
140 bool pausable;
141};
142
143struct cos_help_data {
144 struct cos_entry_help_data data[E2_NUM_OF_COS];
145 u8 num_of_cos;
146};
147
148#define DCBX_ILLEGAL_PG (0xFF)
149#define DCBX_PFC_PRI_MASK (0xFF)
150#define DCBX_STRICT_PRIORITY (15)
151#define DCBX_INVALID_COS_BW (0xFFFFFFFF)
152#define DCBX_PFC_PRI_NON_PAUSE_MASK(bp) \
153 ((bp)->dcbx_port_params.pfc.priority_non_pauseable_mask)
154#define DCBX_PFC_PRI_PAUSE_MASK(bp) \
155 ((u8)~DCBX_PFC_PRI_NON_PAUSE_MASK(bp))
156#define DCBX_PFC_PRI_GET_PAUSE(bp, pg_pri) \
157 ((pg_pri) & (DCBX_PFC_PRI_PAUSE_MASK(bp)))
158#define DCBX_PFC_PRI_GET_NON_PAUSE(bp, pg_pri) \
159 (DCBX_PFC_PRI_NON_PAUSE_MASK(bp) & (pg_pri))
160#define IS_DCBX_PFC_PRI_ONLY_PAUSE(bp, pg_pri) \
161 (pg_pri == DCBX_PFC_PRI_GET_PAUSE((bp), (pg_pri)))
162#define IS_DCBX_PFC_PRI_ONLY_NON_PAUSE(bp, pg_pri)\
163 ((pg_pri) == DCBX_PFC_PRI_GET_NON_PAUSE((bp), (pg_pri)))
164#define IS_DCBX_PFC_PRI_MIX_PAUSE(bp, pg_pri) \
165 (!(IS_DCBX_PFC_PRI_ONLY_NON_PAUSE((bp), (pg_pri)) || \
166 IS_DCBX_PFC_PRI_ONLY_PAUSE((bp), (pg_pri))))
167
168
169struct pg_entry_help_data {
170 u8 num_of_dif_pri;
171 u8 pg;
172 u32 pg_priority;
173};
174
175struct pg_help_data {
176 struct pg_entry_help_data data[LLFC_DRIVER_TRAFFIC_TYPE_MAX];
177 u8 num_of_pg;
178};
179
180/* forward DCB/PFC related declarations */
181struct bnx2x;
182void bnx2x_dcb_init_intmem_pfc(struct bnx2x *bp);
183void bnx2x_dcbx_update(struct work_struct *work);
184void bnx2x_dcbx_init_params(struct bnx2x *bp);
185
186enum {
187 BNX2X_DCBX_STATE_NEG_RECEIVED = 0x1,
188 BNX2X_DCBX_STATE_TX_PAUSED = 0x2,
189 BNX2X_DCBX_STATE_TX_RELEASED = 0x4
190};
191void bnx2x_dcbx_set_params(struct bnx2x *bp, u32 state);
192
193#endif /* BNX2X_DCB_H */
diff --git a/drivers/net/bnx2x/bnx2x_hsi.h b/drivers/net/bnx2x/bnx2x_hsi.h
index 6555c477f893..ed90ec831fe0 100644
--- a/drivers/net/bnx2x/bnx2x_hsi.h
+++ b/drivers/net/bnx2x/bnx2x_hsi.h
@@ -684,7 +684,7 @@ struct shm_dev_info { /* size */
684#define E1VN_MAX 1 684#define E1VN_MAX 1
685#define E1HVN_MAX 4 685#define E1HVN_MAX 4
686 686
687 687#define E2_VF_MAX 64
688/* This value (in milliseconds) determines the frequency of the driver 688/* This value (in milliseconds) determines the frequency of the driver
689 * issuing the PULSE message code. The firmware monitors this periodic 689 * issuing the PULSE message code. The firmware monitors this periodic
690 * pulse to determine when to switch to an OS-absent mode. */ 690 * pulse to determine when to switch to an OS-absent mode. */
@@ -820,6 +820,8 @@ struct drv_func_mb {
820#define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000 820#define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000
821#define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234 821#define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234
822 822
823#define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000
824#define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000
823#define DRV_MSG_CODE_SET_MF_BW 0xe0000000 825#define DRV_MSG_CODE_SET_MF_BW 0xe0000000
824#define REQ_BC_VER_4_SET_MF_BW 0x00060202 826#define REQ_BC_VER_4_SET_MF_BW 0x00060202
825#define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000 827#define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000
@@ -905,6 +907,8 @@ struct drv_func_mb {
905#define DRV_STATUS_DCC_RESERVED1 0x00000800 907#define DRV_STATUS_DCC_RESERVED1 0x00000800
906#define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000 908#define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
907#define DRV_STATUS_DCC_SET_PRIORITY 0x00002000 909#define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
910#define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000
911#define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000
908 912
909 u32 virt_mac_upper; 913 u32 virt_mac_upper;
910#define VIRT_MAC_SIGN_MASK 0xffff0000 914#define VIRT_MAC_SIGN_MASK 0xffff0000
@@ -1089,6 +1093,251 @@ struct fw_flr_mb {
1089 struct fw_flr_ack ack; 1093 struct fw_flr_ack ack;
1090}; 1094};
1091 1095
1096/**** SUPPORT FOR SHMEM ARRRAYS ***
1097 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to
1098 * define arrays with storage types smaller then unsigned dwords.
1099 * The macros below add generic support for SHMEM arrays with numeric elements
1100 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword
1101 * array with individual bit-filed elements accessed using shifts and masks.
1102 *
1103 */
1104
1105/* eb is the bitwidth of a single element */
1106#define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1)
1107#define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb)))
1108
1109/* the bit-position macro allows the used to flip the order of the arrays
1110 * elements on a per byte or word boundary.
1111 *
1112 * example: an array with 8 entries each 4 bit wide. This array will fit into
1113 * a single dword. The diagrmas below show the array order of the nibbles.
1114 *
1115 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:
1116 *
1117 * | | | |
1118 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1119 * | | | |
1120 *
1121 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:
1122 *
1123 * | | | |
1124 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 |
1125 * | | | |
1126 *
1127 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:
1128 *
1129 * | | | |
1130 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 |
1131 * | | | |
1132 */
1133#define SHMEM_ARRAY_BITPOS(i, eb, fb) \
1134 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
1135 (((i)%((fb)/(eb))) * (eb)))
1136
1137#define SHMEM_ARRAY_GET(a, i, eb, fb) \
1138 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \
1139 SHMEM_ARRAY_MASK(eb))
1140
1141#define SHMEM_ARRAY_SET(a, i, eb, fb, val) \
1142do { \
1143 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \
1144 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1145 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \
1146 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1147} while (0)
1148
1149
1150/****START OF DCBX STRUCTURES DECLARATIONS****/
1151#define DCBX_MAX_NUM_PRI_PG_ENTRIES 8
1152#define DCBX_PRI_PG_BITWIDTH 4
1153#define DCBX_PRI_PG_FBITS 8
1154#define DCBX_PRI_PG_GET(a, i) \
1155 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
1156#define DCBX_PRI_PG_SET(a, i, val) \
1157 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
1158#define DCBX_MAX_NUM_PG_BW_ENTRIES 8
1159#define DCBX_BW_PG_BITWIDTH 8
1160#define DCBX_PG_BW_GET(a, i) \
1161 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
1162#define DCBX_PG_BW_SET(a, i, val) \
1163 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
1164#define DCBX_STRICT_PRI_PG 15
1165#define DCBX_MAX_APP_PROTOCOL 16
1166#define FCOE_APP_IDX 0
1167#define ISCSI_APP_IDX 1
1168#define PREDEFINED_APP_IDX_MAX 2
1169
1170struct dcbx_ets_feature {
1171 u32 enabled;
1172 u32 pg_bw_tbl[2];
1173 u32 pri_pg_tbl[1];
1174};
1175
1176struct dcbx_pfc_feature {
1177#ifdef __BIG_ENDIAN
1178 u8 pri_en_bitmap;
1179#define DCBX_PFC_PRI_0 0x01
1180#define DCBX_PFC_PRI_1 0x02
1181#define DCBX_PFC_PRI_2 0x04
1182#define DCBX_PFC_PRI_3 0x08
1183#define DCBX_PFC_PRI_4 0x10
1184#define DCBX_PFC_PRI_5 0x20
1185#define DCBX_PFC_PRI_6 0x40
1186#define DCBX_PFC_PRI_7 0x80
1187 u8 pfc_caps;
1188 u8 reserved;
1189 u8 enabled;
1190#elif defined(__LITTLE_ENDIAN)
1191 u8 enabled;
1192 u8 reserved;
1193 u8 pfc_caps;
1194 u8 pri_en_bitmap;
1195#define DCBX_PFC_PRI_0 0x01
1196#define DCBX_PFC_PRI_1 0x02
1197#define DCBX_PFC_PRI_2 0x04
1198#define DCBX_PFC_PRI_3 0x08
1199#define DCBX_PFC_PRI_4 0x10
1200#define DCBX_PFC_PRI_5 0x20
1201#define DCBX_PFC_PRI_6 0x40
1202#define DCBX_PFC_PRI_7 0x80
1203#endif
1204};
1205
1206struct dcbx_app_priority_entry {
1207#ifdef __BIG_ENDIAN
1208 u16 app_id;
1209 u8 pri_bitmap;
1210 u8 appBitfield;
1211#define DCBX_APP_ENTRY_VALID 0x01
1212#define DCBX_APP_ENTRY_SF_MASK 0x30
1213#define DCBX_APP_ENTRY_SF_SHIFT 4
1214#define DCBX_APP_SF_ETH_TYPE 0x10
1215#define DCBX_APP_SF_PORT 0x20
1216#elif defined(__LITTLE_ENDIAN)
1217 u8 appBitfield;
1218#define DCBX_APP_ENTRY_VALID 0x01
1219#define DCBX_APP_ENTRY_SF_MASK 0x30
1220#define DCBX_APP_ENTRY_SF_SHIFT 4
1221#define DCBX_APP_SF_ETH_TYPE 0x10
1222#define DCBX_APP_SF_PORT 0x20
1223 u8 pri_bitmap;
1224 u16 app_id;
1225#endif
1226};
1227
1228struct dcbx_app_priority_feature {
1229#ifdef __BIG_ENDIAN
1230 u8 reserved;
1231 u8 default_pri;
1232 u8 tc_supported;
1233 u8 enabled;
1234#elif defined(__LITTLE_ENDIAN)
1235 u8 enabled;
1236 u8 tc_supported;
1237 u8 default_pri;
1238 u8 reserved;
1239#endif
1240 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
1241};
1242
1243struct dcbx_features {
1244 struct dcbx_ets_feature ets;
1245 struct dcbx_pfc_feature pfc;
1246 struct dcbx_app_priority_feature app;
1247};
1248
1249struct lldp_params {
1250#ifdef __BIG_ENDIAN
1251 u8 msg_fast_tx_interval;
1252 u8 msg_tx_hold;
1253 u8 msg_tx_interval;
1254 u8 admin_status;
1255#define LLDP_TX_ONLY 0x01
1256#define LLDP_RX_ONLY 0x02
1257#define LLDP_TX_RX 0x03
1258#define LLDP_DISABLED 0x04
1259 u8 reserved1;
1260 u8 tx_fast;
1261 u8 tx_crd_max;
1262 u8 tx_crd;
1263#elif defined(__LITTLE_ENDIAN)
1264 u8 admin_status;
1265#define LLDP_TX_ONLY 0x01
1266#define LLDP_RX_ONLY 0x02
1267#define LLDP_TX_RX 0x03
1268#define LLDP_DISABLED 0x04
1269 u8 msg_tx_interval;
1270 u8 msg_tx_hold;
1271 u8 msg_fast_tx_interval;
1272 u8 tx_crd;
1273 u8 tx_crd_max;
1274 u8 tx_fast;
1275 u8 reserved1;
1276#endif
1277#define REM_CHASSIS_ID_STAT_LEN 4
1278#define REM_PORT_ID_STAT_LEN 4
1279 u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
1280 u32 peer_port_id[REM_PORT_ID_STAT_LEN];
1281};
1282
1283struct lldp_dcbx_stat {
1284#define LOCAL_CHASSIS_ID_STAT_LEN 2
1285#define LOCAL_PORT_ID_STAT_LEN 2
1286 u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
1287 u32 local_port_id[LOCAL_PORT_ID_STAT_LEN];
1288 u32 num_tx_dcbx_pkts;
1289 u32 num_rx_dcbx_pkts;
1290};
1291
1292struct lldp_admin_mib {
1293 u32 ver_cfg_flags;
1294#define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001
1295#define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002
1296#define DCBX_APP_CONFIG_TX_ENABLED 0x00000004
1297#define DCBX_ETS_RECO_TX_ENABLED 0x00000008
1298#define DCBX_ETS_RECO_VALID 0x00000010
1299#define DCBX_ETS_WILLING 0x00000020
1300#define DCBX_PFC_WILLING 0x00000040
1301#define DCBX_APP_WILLING 0x00000080
1302#define DCBX_VERSION_CEE 0x00000100
1303#define DCBX_VERSION_IEEE 0x00000200
1304#define DCBX_DCBX_ENABLED 0x00000400
1305#define DCBX_CEE_VERSION_MASK 0x0000f000
1306#define DCBX_CEE_VERSION_SHIFT 12
1307#define DCBX_CEE_MAX_VERSION_MASK 0x000f0000
1308#define DCBX_CEE_MAX_VERSION_SHIFT 16
1309 struct dcbx_features features;
1310};
1311
1312struct lldp_remote_mib {
1313 u32 prefix_seq_num;
1314 u32 flags;
1315#define DCBX_ETS_TLV_RX 0x00000001
1316#define DCBX_PFC_TLV_RX 0x00000002
1317#define DCBX_APP_TLV_RX 0x00000004
1318#define DCBX_ETS_RX_ERROR 0x00000010
1319#define DCBX_PFC_RX_ERROR 0x00000020
1320#define DCBX_APP_RX_ERROR 0x00000040
1321#define DCBX_ETS_REM_WILLING 0x00000100
1322#define DCBX_PFC_REM_WILLING 0x00000200
1323#define DCBX_APP_REM_WILLING 0x00000400
1324#define DCBX_REMOTE_ETS_RECO_VALID 0x00001000
1325 struct dcbx_features features;
1326 u32 suffix_seq_num;
1327};
1328
1329struct lldp_local_mib {
1330 u32 prefix_seq_num;
1331 u32 error;
1332#define DCBX_LOCAL_ETS_ERROR 0x00000001
1333#define DCBX_LOCAL_PFC_ERROR 0x00000002
1334#define DCBX_LOCAL_APP_ERROR 0x00000004
1335#define DCBX_LOCAL_PFC_MISMATCH 0x00000010
1336#define DCBX_LOCAL_APP_MISMATCH 0x00000020
1337 struct dcbx_features features;
1338 u32 suffix_seq_num;
1339};
1340/***END OF DCBX STRUCTURES DECLARATIONS***/
1092 1341
1093struct shmem2_region { 1342struct shmem2_region {
1094 1343
@@ -1112,7 +1361,12 @@ struct shmem2_region {
1112#define SHMEM_MF_CFG_ADDR_NONE 0x00000000 1361#define SHMEM_MF_CFG_ADDR_NONE 0x00000000
1113 1362
1114 struct fw_flr_mb flr_mb; 1363 struct fw_flr_mb flr_mb;
1115 u32 reserved[3]; 1364 u32 dcbx_lldp_params_offset;
1365#define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000
1366 u32 dcbx_neg_res_offset;
1367#define SHMEM_DCBX_NEG_RES_NONE 0x00000000
1368 u32 dcbx_remote_mib_offset;
1369#define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000
1116 /* 1370 /*
1117 * The other shmemX_base_addr holds the other path's shmem address 1371 * The other shmemX_base_addr holds the other path's shmem address
1118 * required for example in case of common phy init, or for path1 to know 1372 * required for example in case of common phy init, or for path1 to know
@@ -1121,6 +1375,10 @@ struct shmem2_region {
1121 */ 1375 */
1122 u32 other_shmem_base_addr; 1376 u32 other_shmem_base_addr;
1123 u32 other_shmem2_base_addr; 1377 u32 other_shmem2_base_addr;
1378 u32 reserved1[E2_VF_MAX / 32];
1379 u32 reserved2[E2_FUNC_MAX][E2_VF_MAX / 32];
1380 u32 dcbx_lldp_dcbx_stat_offset;
1381#define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000
1124}; 1382};
1125 1383
1126 1384
@@ -3023,6 +3281,25 @@ struct fairness_vars_per_vn {
3023 3281
3024 3282
3025/* 3283/*
3284 * The data for flow control configuration
3285 */
3286struct flow_control_configuration {
3287 struct priority_cos
3288 traffic_type_to_priority_cos[MAX_PFC_TRAFFIC_TYPES];
3289#if defined(__BIG_ENDIAN)
3290 u16 reserved1;
3291 u8 dcb_version;
3292 u8 dcb_enabled;
3293#elif defined(__LITTLE_ENDIAN)
3294 u8 dcb_enabled;
3295 u8 dcb_version;
3296 u16 reserved1;
3297#endif
3298 u32 reserved2;
3299};
3300
3301
3302/*
3026 * FW version stored in the Xstorm RAM 3303 * FW version stored in the Xstorm RAM
3027 */ 3304 */
3028struct fw_version { 3305struct fw_version {
diff --git a/drivers/net/bnx2x/bnx2x_link.h b/drivers/net/bnx2x/bnx2x_link.h
index 171abf8097ee..149f84258d8b 100644
--- a/drivers/net/bnx2x/bnx2x_link.h
+++ b/drivers/net/bnx2x/bnx2x_link.h
@@ -216,6 +216,7 @@ struct link_params {
216 216
217 u32 feature_config_flags; 217 u32 feature_config_flags;
218#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0) 218#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
219#define FEATURE_CONFIG_PFC_ENABLED (1<<1)
219#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2) 220#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
220#define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3) 221#define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3)
221 /* Will be populated during common init */ 222 /* Will be populated during common init */
@@ -332,4 +333,43 @@ u8 bnx2x_phy_probe(struct link_params *params);
332u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base, 333u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base,
333 u32 shmem2_base, u8 port); 334 u32 shmem2_base, u8 port);
334 335
336/* PFC port configuration params */
337struct bnx2x_nig_brb_pfc_port_params {
338 /* NIG */
339 u32 pause_enable;
340 u32 llfc_out_en;
341 u32 llfc_enable;
342 u32 pkt_priority_to_cos;
343 u32 rx_cos0_priority_mask;
344 u32 rx_cos1_priority_mask;
345 u32 llfc_high_priority_classes;
346 u32 llfc_low_priority_classes;
347 /* BRB */
348 u32 cos0_pauseable;
349 u32 cos1_pauseable;
350};
351
352/**
353 * Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
354 * when link is already up
355 */
356void bnx2x_update_pfc(struct link_params *params,
357 struct link_vars *vars,
358 struct bnx2x_nig_brb_pfc_port_params *pfc_params);
359
360
361/* Used to configure the ETS to disable */
362void bnx2x_ets_disabled(struct link_params *params);
363
364/* Used to configure the ETS to BW limited */
365void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
366 const u32 cos1_bw);
367
368/* Used to configure the ETS to strict */
369u8 bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos);
370
371/* Read pfc statistic*/
372void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
373 u32 pfc_frames_sent[2],
374 u32 pfc_frames_received[2]);
335#endif /* BNX2X_LINK_H */ 375#endif /* BNX2X_LINK_H */
diff --git a/drivers/net/bnx2x/bnx2x_main.c b/drivers/net/bnx2x/bnx2x_main.c
index 563b2cb8e544..bdc3fc26b31a 100644
--- a/drivers/net/bnx2x/bnx2x_main.c
+++ b/drivers/net/bnx2x/bnx2x_main.c
@@ -55,6 +55,7 @@
55#include "bnx2x_init.h" 55#include "bnx2x_init.h"
56#include "bnx2x_init_ops.h" 56#include "bnx2x_init_ops.h"
57#include "bnx2x_cmn.h" 57#include "bnx2x_cmn.h"
58#include "bnx2x_dcb.h"
58 59
59#include <linux/firmware.h> 60#include <linux/firmware.h>
60#include "bnx2x_fw_file_hdr.h" 61#include "bnx2x_fw_file_hdr.h"
@@ -3105,6 +3106,11 @@ static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3105 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) 3106 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3106 bnx2x_pmf_update(bp); 3107 bnx2x_pmf_update(bp);
3107 3108
3109 if (bp->port.pmf &&
3110 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS))
3111 /* start dcbx state machine */
3112 bnx2x_dcbx_set_params(bp,
3113 BNX2X_DCBX_STATE_NEG_RECEIVED);
3108 } else if (attn & BNX2X_MC_ASSERT_BITS) { 3114 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3109 3115
3110 BNX2X_ERR("MC assert!\n"); 3116 BNX2X_ERR("MC assert!\n");
@@ -3724,6 +3730,15 @@ static void bnx2x_eq_int(struct bnx2x *bp)
3724 BNX2X_FP_STATE_CLOSED; 3730 BNX2X_FP_STATE_CLOSED;
3725 3731
3726 goto next_spqe; 3732 goto next_spqe;
3733
3734 case EVENT_RING_OPCODE_STOP_TRAFFIC:
3735 DP(NETIF_MSG_IFUP, "got STOP TRAFFIC\n");
3736 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
3737 goto next_spqe;
3738 case EVENT_RING_OPCODE_START_TRAFFIC:
3739 DP(NETIF_MSG_IFUP, "got START TRAFFIC\n");
3740 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
3741 goto next_spqe;
3727 } 3742 }
3728 3743
3729 switch (opcode | bp->state) { 3744 switch (opcode | bp->state) {
@@ -4363,6 +4378,7 @@ static void bnx2x_init_internal_common(struct bnx2x *bp)
4363static void bnx2x_init_internal_port(struct bnx2x *bp) 4378static void bnx2x_init_internal_port(struct bnx2x *bp)
4364{ 4379{
4365 /* port */ 4380 /* port */
4381 bnx2x_dcb_init_intmem_pfc(bp);
4366} 4382}
4367 4383
4368static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) 4384static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
@@ -5488,8 +5504,10 @@ static int bnx2x_init_hw_port(struct bnx2x *bp)
5488 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use 5504 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
5489 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF 5505 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
5490 * bits 4-7 are used for "per vn group attention" */ 5506 * bits 4-7 are used for "per vn group attention" */
5491 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 5507 val = IS_MF(bp) ? 0xF7 : 0x7;
5492 (IS_MF(bp) ? 0xF7 : 0x7)); 5508 /* Enable DCBX attention for all but E1 */
5509 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
5510 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
5493 5511
5494 bnx2x_init_block(bp, PXPCS_BLOCK, init_stage); 5512 bnx2x_init_block(bp, PXPCS_BLOCK, init_stage);
5495 bnx2x_init_block(bp, EMAC0_BLOCK, init_stage); 5513 bnx2x_init_block(bp, EMAC0_BLOCK, init_stage);
@@ -8775,6 +8793,8 @@ static int __devinit bnx2x_init_bp(struct bnx2x *bp)
8775 bp->timer.data = (unsigned long) bp; 8793 bp->timer.data = (unsigned long) bp;
8776 bp->timer.function = bnx2x_timer; 8794 bp->timer.function = bnx2x_timer;
8777 8795
8796 bnx2x_dcbx_init_params(bp);
8797
8778 return rc; 8798 return rc;
8779} 8799}
8780 8800
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-06 20:43:51 -0500