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authorJeff Garzik <jgarzik@pobox.com>2006-01-03 10:49:18 -0500
committerJeff Garzik <jgarzik@pobox.com>2006-01-03 10:49:18 -0500
commitac67c6247361b3b8644b34e5301a46d5069c1373 (patch)
treedd83147e304181e889eefa39e5056451031f4b5d /drivers/net
parentc4c48d83e9ffb1c25cccd59d5ea9dda6ded01faf (diff)
parent88026842b0a760145aa71d69e74fbc9ec118ca44 (diff)
Merge branch 'master'
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/forcedeth.c15
-rw-r--r--drivers/net/phy/phy_device.c4
-rw-r--r--drivers/net/ppp_generic.c3
-rw-r--r--drivers/net/sungem.c4
-rw-r--r--drivers/net/tg3.c195
-rw-r--r--drivers/net/tg3.h7
-rw-r--r--drivers/net/wireless/orinoco_nortel.c6
7 files changed, 134 insertions, 100 deletions
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index 525624fc03b4..c39344adecce 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -10,7 +10,7 @@
10 * trademarks of NVIDIA Corporation in the United States and other 10 * trademarks of NVIDIA Corporation in the United States and other
11 * countries. 11 * countries.
12 * 12 *
13 * Copyright (C) 2003,4 Manfred Spraul 13 * Copyright (C) 2003,4,5 Manfred Spraul
14 * Copyright (C) 2004 Andrew de Quincey (wol support) 14 * Copyright (C) 2004 Andrew de Quincey (wol support)
15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane 15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
16 * IRQ rate fixes, bigendian fixes, cleanups, verification) 16 * IRQ rate fixes, bigendian fixes, cleanups, verification)
@@ -100,6 +100,7 @@
100 * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check 100 * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
101 * 0.46: 20 Oct 2005: Add irq optimization modes. 101 * 0.46: 20 Oct 2005: Add irq optimization modes.
102 * 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan. 102 * 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
103 * 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
103 * 104 *
104 * Known bugs: 105 * Known bugs:
105 * We suspect that on some hardware no TX done interrupts are generated. 106 * We suspect that on some hardware no TX done interrupts are generated.
@@ -111,7 +112,7 @@
111 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few 112 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
112 * superfluous timer interrupts from the nic. 113 * superfluous timer interrupts from the nic.
113 */ 114 */
114#define FORCEDETH_VERSION "0.47" 115#define FORCEDETH_VERSION "0.48"
115#define DRV_NAME "forcedeth" 116#define DRV_NAME "forcedeth"
116 117
117#include <linux/module.h> 118#include <linux/module.h>
@@ -871,8 +872,8 @@ static int nv_alloc_rx(struct net_device *dev)
871 } else { 872 } else {
872 skb = np->rx_skbuff[nr]; 873 skb = np->rx_skbuff[nr];
873 } 874 }
874 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len, 875 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data,
875 PCI_DMA_FROMDEVICE); 876 skb->end-skb->data, PCI_DMA_FROMDEVICE);
876 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) { 877 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
877 np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]); 878 np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
878 wmb(); 879 wmb();
@@ -999,7 +1000,7 @@ static void nv_drain_rx(struct net_device *dev)
999 wmb(); 1000 wmb();
1000 if (np->rx_skbuff[i]) { 1001 if (np->rx_skbuff[i]) {
1001 pci_unmap_single(np->pci_dev, np->rx_dma[i], 1002 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1002 np->rx_skbuff[i]->len, 1003 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1003 PCI_DMA_FROMDEVICE); 1004 PCI_DMA_FROMDEVICE);
1004 dev_kfree_skb(np->rx_skbuff[i]); 1005 dev_kfree_skb(np->rx_skbuff[i]);
1005 np->rx_skbuff[i] = NULL; 1006 np->rx_skbuff[i] = NULL;
@@ -1334,7 +1335,7 @@ static void nv_rx_process(struct net_device *dev)
1334 * the performance. 1335 * the performance.
1335 */ 1336 */
1336 pci_unmap_single(np->pci_dev, np->rx_dma[i], 1337 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1337 np->rx_skbuff[i]->len, 1338 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1338 PCI_DMA_FROMDEVICE); 1339 PCI_DMA_FROMDEVICE);
1339 1340
1340 { 1341 {
@@ -2455,7 +2456,7 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
2455 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; 2456 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
2456 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG; 2457 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
2457#ifdef NETIF_F_TSO 2458#ifdef NETIF_F_TSO
2458 dev->features |= NETIF_F_TSO; 2459 /* disabled dev->features |= NETIF_F_TSO; */
2459#endif 2460#endif
2460 } 2461 }
2461 2462
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index 16bebe7a7ce1..7da0e3dd5fe3 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -38,6 +38,10 @@
38#include <asm/irq.h> 38#include <asm/irq.h>
39#include <asm/uaccess.h> 39#include <asm/uaccess.h>
40 40
41MODULE_DESCRIPTION("PHY library");
42MODULE_AUTHOR("Andy Fleming");
43MODULE_LICENSE("GPL");
44
41static struct phy_driver genphy_driver; 45static struct phy_driver genphy_driver;
42extern int mdio_bus_init(void); 46extern int mdio_bus_init(void);
43extern void mdio_bus_exit(void); 47extern void mdio_bus_exit(void);
diff --git a/drivers/net/ppp_generic.c b/drivers/net/ppp_generic.c
index 50430f79f8cf..1c6d328165bb 100644
--- a/drivers/net/ppp_generic.c
+++ b/drivers/net/ppp_generic.c
@@ -524,9 +524,6 @@ static int get_filter(void __user *arg, struct sock_filter **p)
524 if (copy_from_user(&uprog, arg, sizeof(uprog))) 524 if (copy_from_user(&uprog, arg, sizeof(uprog)))
525 return -EFAULT; 525 return -EFAULT;
526 526
527 if (uprog.len > BPF_MAXINSNS)
528 return -EINVAL;
529
530 if (!uprog.len) { 527 if (!uprog.len) {
531 *p = NULL; 528 *p = NULL;
532 return 0; 529 return 0;
diff --git a/drivers/net/sungem.c b/drivers/net/sungem.c
index 081717d01374..28ce47a02408 100644
--- a/drivers/net/sungem.c
+++ b/drivers/net/sungem.c
@@ -2907,7 +2907,7 @@ static int __devinit gem_get_device_address(struct gem *gp)
2907 return 0; 2907 return 0;
2908} 2908}
2909 2909
2910static void __devexit gem_remove_one(struct pci_dev *pdev) 2910static void gem_remove_one(struct pci_dev *pdev)
2911{ 2911{
2912 struct net_device *dev = pci_get_drvdata(pdev); 2912 struct net_device *dev = pci_get_drvdata(pdev);
2913 2913
@@ -3181,7 +3181,7 @@ static struct pci_driver gem_driver = {
3181 .name = GEM_MODULE_NAME, 3181 .name = GEM_MODULE_NAME,
3182 .id_table = gem_pci_tbl, 3182 .id_table = gem_pci_tbl,
3183 .probe = gem_init_one, 3183 .probe = gem_init_one,
3184 .remove = __devexit_p(gem_remove_one), 3184 .remove = gem_remove_one,
3185#ifdef CONFIG_PM 3185#ifdef CONFIG_PM
3186 .suspend = gem_suspend, 3186 .suspend = gem_suspend,
3187 .resume = gem_resume, 3187 .resume = gem_resume,
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index a23ed28a72b8..2fc9893d69e1 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -68,8 +68,8 @@
68 68
69#define DRV_MODULE_NAME "tg3" 69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": " 70#define PFX DRV_MODULE_NAME ": "
71#define DRV_MODULE_VERSION "3.45" 71#define DRV_MODULE_VERSION "3.47"
72#define DRV_MODULE_RELDATE "Dec 13, 2005" 72#define DRV_MODULE_RELDATE "Dec 28, 2005"
73 73
74#define TG3_DEF_MAC_MODE 0 74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0 75#define TG3_DEF_RX_MODE 0
@@ -341,6 +341,16 @@ static struct {
341 { "interrupt test (offline)" }, 341 { "interrupt test (offline)" },
342}; 342};
343 343
344static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
345{
346 writel(val, tp->regs + off);
347}
348
349static u32 tg3_read32(struct tg3 *tp, u32 off)
350{
351 return (readl(tp->regs + off));
352}
353
344static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) 354static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
345{ 355{
346 unsigned long flags; 356 unsigned long flags;
@@ -411,13 +421,29 @@ static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
411 return val; 421 return val;
412} 422}
413 423
414static void _tw32_flush(struct tg3 *tp, u32 off, u32 val) 424/* usec_wait specifies the wait time in usec when writing to certain registers
425 * where it is unsafe to read back the register without some delay.
426 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
427 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
428 */
429static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
415{ 430{
416 tp->write32(tp, off, val); 431 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
417 if (!(tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) && 432 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
418 !(tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG) && 433 /* Non-posted methods */
419 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)) 434 tp->write32(tp, off, val);
420 tp->read32(tp, off); /* flush */ 435 else {
436 /* Posted method */
437 tg3_write32(tp, off, val);
438 if (usec_wait)
439 udelay(usec_wait);
440 tp->read32(tp, off);
441 }
442 /* Wait again after the read for the posted method to guarantee that
443 * the wait time is met.
444 */
445 if (usec_wait)
446 udelay(usec_wait);
421} 447}
422 448
423static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) 449static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
@@ -438,16 +464,6 @@ static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
438 readl(mbox); 464 readl(mbox);
439} 465}
440 466
441static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
442{
443 writel(val, tp->regs + off);
444}
445
446static u32 tg3_read32(struct tg3 *tp, u32 off)
447{
448 return (readl(tp->regs + off));
449}
450
451#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) 467#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
452#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val)) 468#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
453#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) 469#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
@@ -455,7 +471,8 @@ static u32 tg3_read32(struct tg3 *tp, u32 off)
455#define tr32_mailbox(reg) tp->read32_mbox(tp, reg) 471#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
456 472
457#define tw32(reg,val) tp->write32(tp, reg, val) 473#define tw32(reg,val) tp->write32(tp, reg, val)
458#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val)) 474#define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
475#define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
459#define tr32(reg) tp->read32(tp, reg) 476#define tr32(reg) tp->read32(tp, reg)
460 477
461static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) 478static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
@@ -595,21 +612,19 @@ static void tg3_switch_clocks(struct tg3 *tp)
595 612
596 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { 613 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
597 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) { 614 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
598 tw32_f(TG3PCI_CLOCK_CTRL, 615 tw32_wait_f(TG3PCI_CLOCK_CTRL,
599 clock_ctrl | CLOCK_CTRL_625_CORE); 616 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
600 udelay(40);
601 } 617 }
602 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) { 618 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
603 tw32_f(TG3PCI_CLOCK_CTRL, 619 tw32_wait_f(TG3PCI_CLOCK_CTRL,
604 clock_ctrl | 620 clock_ctrl |
605 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK)); 621 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
606 udelay(40); 622 40);
607 tw32_f(TG3PCI_CLOCK_CTRL, 623 tw32_wait_f(TG3PCI_CLOCK_CTRL,
608 clock_ctrl | (CLOCK_CTRL_ALTCLK)); 624 clock_ctrl | (CLOCK_CTRL_ALTCLK),
609 udelay(40); 625 40);
610 } 626 }
611 tw32_f(TG3PCI_CLOCK_CTRL, clock_ctrl); 627 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
612 udelay(40);
613} 628}
614 629
615#define PHY_BUSY_LOOPS 5000 630#define PHY_BUSY_LOOPS 5000
@@ -1017,39 +1032,50 @@ static void tg3_frob_aux_power(struct tg3 *tp)
1017 if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0) 1032 if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
1018 return; 1033 return;
1019 1034
1020 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { 1035 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1021 tp_peer = pci_get_drvdata(tp->pdev_peer); 1036 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1022 if (!tp_peer) 1037 struct net_device *dev_peer;
1038
1039 dev_peer = pci_get_drvdata(tp->pdev_peer);
1040 if (!dev_peer)
1023 BUG(); 1041 BUG();
1042 tp_peer = netdev_priv(dev_peer);
1024 } 1043 }
1025 1044
1026
1027 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 || 1045 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1028 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 || 1046 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1029 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 || 1047 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1030 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) { 1048 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1031 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || 1049 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1032 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { 1050 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1033 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | 1051 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1034 (GRC_LCLCTRL_GPIO_OE0 | 1052 (GRC_LCLCTRL_GPIO_OE0 |
1035 GRC_LCLCTRL_GPIO_OE1 | 1053 GRC_LCLCTRL_GPIO_OE1 |
1036 GRC_LCLCTRL_GPIO_OE2 | 1054 GRC_LCLCTRL_GPIO_OE2 |
1037 GRC_LCLCTRL_GPIO_OUTPUT0 | 1055 GRC_LCLCTRL_GPIO_OUTPUT0 |
1038 GRC_LCLCTRL_GPIO_OUTPUT1)); 1056 GRC_LCLCTRL_GPIO_OUTPUT1),
1039 udelay(100); 1057 100);
1040 } else { 1058 } else {
1041 u32 no_gpio2; 1059 u32 no_gpio2;
1042 u32 grc_local_ctrl; 1060 u32 grc_local_ctrl = 0;
1043 1061
1044 if (tp_peer != tp && 1062 if (tp_peer != tp &&
1045 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0) 1063 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1046 return; 1064 return;
1047 1065
1066 /* Workaround to prevent overdrawing Amps. */
1067 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1068 ASIC_REV_5714) {
1069 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1070 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1071 grc_local_ctrl, 100);
1072 }
1073
1048 /* On 5753 and variants, GPIO2 cannot be used. */ 1074 /* On 5753 and variants, GPIO2 cannot be used. */
1049 no_gpio2 = tp->nic_sram_data_cfg & 1075 no_gpio2 = tp->nic_sram_data_cfg &
1050 NIC_SRAM_DATA_CFG_NO_GPIO2; 1076 NIC_SRAM_DATA_CFG_NO_GPIO2;
1051 1077
1052 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 | 1078 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1053 GRC_LCLCTRL_GPIO_OE1 | 1079 GRC_LCLCTRL_GPIO_OE1 |
1054 GRC_LCLCTRL_GPIO_OE2 | 1080 GRC_LCLCTRL_GPIO_OE2 |
1055 GRC_LCLCTRL_GPIO_OUTPUT1 | 1081 GRC_LCLCTRL_GPIO_OUTPUT1 |
@@ -1058,21 +1084,18 @@ static void tg3_frob_aux_power(struct tg3 *tp)
1058 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 | 1084 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1059 GRC_LCLCTRL_GPIO_OUTPUT2); 1085 GRC_LCLCTRL_GPIO_OUTPUT2);
1060 } 1086 }
1061 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | 1087 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1062 grc_local_ctrl); 1088 grc_local_ctrl, 100);
1063 udelay(100);
1064 1089
1065 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0; 1090 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1066 1091
1067 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | 1092 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1068 grc_local_ctrl); 1093 grc_local_ctrl, 100);
1069 udelay(100);
1070 1094
1071 if (!no_gpio2) { 1095 if (!no_gpio2) {
1072 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2; 1096 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1073 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | 1097 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1074 grc_local_ctrl); 1098 grc_local_ctrl, 100);
1075 udelay(100);
1076 } 1099 }
1077 } 1100 }
1078 } else { 1101 } else {
@@ -1082,19 +1105,16 @@ static void tg3_frob_aux_power(struct tg3 *tp)
1082 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0) 1105 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1083 return; 1106 return;
1084 1107
1085 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | 1108 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1086 (GRC_LCLCTRL_GPIO_OE1 | 1109 (GRC_LCLCTRL_GPIO_OE1 |
1087 GRC_LCLCTRL_GPIO_OUTPUT1)); 1110 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1088 udelay(100);
1089 1111
1090 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | 1112 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1091 (GRC_LCLCTRL_GPIO_OE1)); 1113 GRC_LCLCTRL_GPIO_OE1, 100);
1092 udelay(100);
1093 1114
1094 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | 1115 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1095 (GRC_LCLCTRL_GPIO_OE1 | 1116 (GRC_LCLCTRL_GPIO_OE1 |
1096 GRC_LCLCTRL_GPIO_OUTPUT1)); 1117 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1097 udelay(100);
1098 } 1118 }
1099 } 1119 }
1100} 1120}
@@ -1137,10 +1157,8 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
1137 udelay(100); /* Delay after power state change */ 1157 udelay(100); /* Delay after power state change */
1138 1158
1139 /* Switch out of Vaux if it is not a LOM */ 1159 /* Switch out of Vaux if it is not a LOM */
1140 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) { 1160 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
1141 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); 1161 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1142 udelay(100);
1143 }
1144 1162
1145 return 0; 1163 return 0;
1146 1164
@@ -1239,10 +1257,8 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
1239 base_val |= (CLOCK_CTRL_RXCLK_DISABLE | 1257 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1240 CLOCK_CTRL_TXCLK_DISABLE); 1258 CLOCK_CTRL_TXCLK_DISABLE);
1241 1259
1242 tw32_f(TG3PCI_CLOCK_CTRL, base_val | 1260 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1243 CLOCK_CTRL_ALTCLK | 1261 CLOCK_CTRL_PWRDOWN_PLL133, 40);
1244 CLOCK_CTRL_PWRDOWN_PLL133);
1245 udelay(40);
1246 } else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { 1262 } else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
1247 /* do nothing */ 1263 /* do nothing */
1248 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && 1264 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
@@ -1263,11 +1279,11 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
1263 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; 1279 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1264 } 1280 }
1265 1281
1266 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1); 1282 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1267 udelay(40); 1283 40);
1268 1284
1269 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2); 1285 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1270 udelay(40); 1286 40);
1271 1287
1272 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { 1288 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1273 u32 newbits3; 1289 u32 newbits3;
@@ -1281,9 +1297,8 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
1281 newbits3 = CLOCK_CTRL_44MHZ_CORE; 1297 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1282 } 1298 }
1283 1299
1284 tw32_f(TG3PCI_CLOCK_CTRL, 1300 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1285 tp->pci_clock_ctrl | newbits3); 1301 tp->pci_clock_ctrl | newbits3, 40);
1286 udelay(40);
1287 } 1302 }
1288 } 1303 }
1289 1304
@@ -1294,7 +1309,8 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
1294 tg3_writephy(tp, MII_TG3_EXT_CTRL, 1309 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1295 MII_TG3_EXT_CTRL_FORCE_LED_OFF); 1310 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1296 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2); 1311 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1297 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); 1312 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
1313 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1298 } 1314 }
1299 } 1315 }
1300 1316
@@ -7135,8 +7151,13 @@ do { p = (u32 *)(orig_p + (reg)); \
7135 GET_REG32_LOOP(BUFMGR_MODE, 0x58); 7151 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7136 GET_REG32_LOOP(RDMAC_MODE, 0x08); 7152 GET_REG32_LOOP(RDMAC_MODE, 0x08);
7137 GET_REG32_LOOP(WDMAC_MODE, 0x08); 7153 GET_REG32_LOOP(WDMAC_MODE, 0x08);
7138 GET_REG32_LOOP(RX_CPU_BASE, 0x280); 7154 GET_REG32_1(RX_CPU_MODE);
7139 GET_REG32_LOOP(TX_CPU_BASE, 0x280); 7155 GET_REG32_1(RX_CPU_STATE);
7156 GET_REG32_1(RX_CPU_PGMCTR);
7157 GET_REG32_1(RX_CPU_HWBKPT);
7158 GET_REG32_1(TX_CPU_MODE);
7159 GET_REG32_1(TX_CPU_STATE);
7160 GET_REG32_1(TX_CPU_PGMCTR);
7140 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110); 7161 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7141 GET_REG32_LOOP(FTQ_RESET, 0x120); 7162 GET_REG32_LOOP(FTQ_RESET, 0x120);
7142 GET_REG32_LOOP(MSGINT_MODE, 0x0c); 7163 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
@@ -7959,13 +7980,12 @@ static int tg3_test_memory(struct tg3 *tp)
7959 u32 offset; 7980 u32 offset;
7960 u32 len; 7981 u32 len;
7961 } mem_tbl_570x[] = { 7982 } mem_tbl_570x[] = {
7962 { 0x00000000, 0x01000}, 7983 { 0x00000000, 0x00b50},
7963 { 0x00002000, 0x1c000}, 7984 { 0x00002000, 0x1c000},
7964 { 0xffffffff, 0x00000} 7985 { 0xffffffff, 0x00000}
7965 }, mem_tbl_5705[] = { 7986 }, mem_tbl_5705[] = {
7966 { 0x00000100, 0x0000c}, 7987 { 0x00000100, 0x0000c},
7967 { 0x00000200, 0x00008}, 7988 { 0x00000200, 0x00008},
7968 { 0x00000b50, 0x00400},
7969 { 0x00004000, 0x00800}, 7989 { 0x00004000, 0x00800},
7970 { 0x00006000, 0x01000}, 7990 { 0x00006000, 0x01000},
7971 { 0x00008000, 0x02000}, 7991 { 0x00008000, 0x02000},
@@ -10466,7 +10486,7 @@ static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
10466 return str; 10486 return str;
10467} 10487}
10468 10488
10469static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp) 10489static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
10470{ 10490{
10471 struct pci_dev *peer; 10491 struct pci_dev *peer;
10472 unsigned int func, devnr = tp->pdev->devfn & ~7; 10492 unsigned int func, devnr = tp->pdev->devfn & ~7;
@@ -10719,8 +10739,9 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
10719 tp->rx_pending = 63; 10739 tp->rx_pending = 63;
10720 } 10740 }
10721 10741
10722 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) 10742 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
10723 tp->pdev_peer = tg3_find_5704_peer(tp); 10743 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
10744 tp->pdev_peer = tg3_find_peer(tp);
10724 10745
10725 err = tg3_get_device_address(tp); 10746 err = tg3_get_device_address(tp);
10726 if (err) { 10747 if (err) {
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 94dbcf3537ec..890e1635996b 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1124,7 +1124,14 @@
1124/* 0x280 --> 0x400 unused */ 1124/* 0x280 --> 0x400 unused */
1125 1125
1126#define RX_CPU_BASE 0x00005000 1126#define RX_CPU_BASE 0x00005000
1127#define RX_CPU_MODE 0x00005000
1128#define RX_CPU_STATE 0x00005004
1129#define RX_CPU_PGMCTR 0x0000501c
1130#define RX_CPU_HWBKPT 0x00005034
1127#define TX_CPU_BASE 0x00005400 1131#define TX_CPU_BASE 0x00005400
1132#define TX_CPU_MODE 0x00005400
1133#define TX_CPU_STATE 0x00005404
1134#define TX_CPU_PGMCTR 0x0000541c
1128 1135
1129/* Mailboxes */ 1136/* Mailboxes */
1130#define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */ 1137#define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */
diff --git a/drivers/net/wireless/orinoco_nortel.c b/drivers/net/wireless/orinoco_nortel.c
index d8afd51ff8a5..d1a670b35338 100644
--- a/drivers/net/wireless/orinoco_nortel.c
+++ b/drivers/net/wireless/orinoco_nortel.c
@@ -1,6 +1,8 @@
1/* orinoco_nortel.c 1/* orinoco_nortel.c
2 * 2 *
3 * Driver for Prism II devices which would usually be driven by orinoco_cs, 3 * Driver for Prism II devices which would usually be driven by orinoco_cs,
4 * but are connected to the PCI bus by a PCI-to-PCMCIA adapter used in
5 * Nortel emobility, Symbol LA-4113 and Symbol LA-4123.
4 * but are connected to the PCI bus by a Nortel PCI-PCMCIA-Adapter. 6 * but are connected to the PCI bus by a Nortel PCI-PCMCIA-Adapter.
5 * 7 *
6 * Copyright (C) 2002 Tobias Hoffmann 8 * Copyright (C) 2002 Tobias Hoffmann
@@ -165,7 +167,7 @@ static int nortel_pci_init_one(struct pci_dev *pdev,
165 goto fail_resources; 167 goto fail_resources;
166 } 168 }
167 169
168 iomem = pci_iomap(pdev, 3, 0); 170 iomem = pci_iomap(pdev, 2, 0);
169 if (!iomem) { 171 if (!iomem) {
170 err = -ENOMEM; 172 err = -ENOMEM;
171 goto fail_map_io; 173 goto fail_map_io;
@@ -265,6 +267,8 @@ static void __devexit nortel_pci_remove_one(struct pci_dev *pdev)
265static struct pci_device_id nortel_pci_id_table[] = { 267static struct pci_device_id nortel_pci_id_table[] = {
266 /* Nortel emobility PCI */ 268 /* Nortel emobility PCI */
267 {0x126c, 0x8030, PCI_ANY_ID, PCI_ANY_ID,}, 269 {0x126c, 0x8030, PCI_ANY_ID, PCI_ANY_ID,},
270 /* Symbol LA-4123 PCI */
271 {0x1562, 0x0001, PCI_ANY_ID, PCI_ANY_ID,},
268 {0,}, 272 {0,},
269}; 273};
270 274