aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net
diff options
context:
space:
mode:
authorDavid S. Miller <davem@davemloft.net>2008-07-30 18:44:30 -0400
committerDavid S. Miller <davem@davemloft.net>2008-07-30 18:44:30 -0400
commite62112c53acfefc67ccfbdc1895eebccf866bc1b (patch)
tree46c99ef13fc1764016ca8d2bb749f252f70cfab9 /drivers/net
parent031cf19e6f63941506c9baf76ac7adac06edcf08 (diff)
parent68905eb4dc9c691ba09df767ac0641395025cef6 (diff)
Merge branch 'upstream-davem' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/netdev-2.6
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/Kconfig4
-rw-r--r--drivers/net/bfin_mac.c111
-rw-r--r--drivers/net/cxgb3/t3_hw.c2
-rw-r--r--drivers/net/ehea/ehea_main.c4
-rw-r--r--drivers/net/enc28j60.c6
-rw-r--r--drivers/net/forcedeth.c64
-rw-r--r--drivers/net/mv643xx_eth.c358
-rw-r--r--drivers/net/ne.c6
-rw-r--r--drivers/net/s2io.c29
-rw-r--r--drivers/net/sh_eth.c202
-rw-r--r--drivers/net/sh_eth.h426
-rw-r--r--drivers/net/usb/dm9601.c52
-rw-r--r--drivers/net/wd.c2
13 files changed, 933 insertions, 333 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index fa533c27052a..8a03875ec877 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -510,14 +510,14 @@ config STNIC
510config SH_ETH 510config SH_ETH
511 tristate "Renesas SuperH Ethernet support" 511 tristate "Renesas SuperH Ethernet support"
512 depends on SUPERH && \ 512 depends on SUPERH && \
513 (CPU_SUBTYPE_SH7710 || CPU_SUBTYPE_SH7712) 513 (CPU_SUBTYPE_SH7710 || CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7763)
514 select CRC32 514 select CRC32
515 select MII 515 select MII
516 select MDIO_BITBANG 516 select MDIO_BITBANG
517 select PHYLIB 517 select PHYLIB
518 help 518 help
519 Renesas SuperH Ethernet device driver. 519 Renesas SuperH Ethernet device driver.
520 This driver support SH7710 and SH7712. 520 This driver support SH7710, SH7712 and SH7763.
521 521
522config SUNLANCE 522config SUNLANCE
523 tristate "Sun LANCE support" 523 tristate "Sun LANCE support"
diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c
index a8ec60e1ed75..3db7db1828e7 100644
--- a/drivers/net/bfin_mac.c
+++ b/drivers/net/bfin_mac.c
@@ -605,36 +605,87 @@ adjust_head:
605static int bfin_mac_hard_start_xmit(struct sk_buff *skb, 605static int bfin_mac_hard_start_xmit(struct sk_buff *skb,
606 struct net_device *dev) 606 struct net_device *dev)
607{ 607{
608 unsigned int data; 608 u16 *data;
609 609
610 current_tx_ptr->skb = skb; 610 current_tx_ptr->skb = skb;
611 611
612 /* 612 if (ANOMALY_05000285) {
613 * Is skb->data always 16-bit aligned? 613 /*
614 * Do we need to memcpy((char *)(tail->packet + 2), skb->data, len)? 614 * TXDWA feature is not avaible to older revision < 0.3 silicon
615 */ 615 * of BF537
616 if ((((unsigned int)(skb->data)) & 0x02) == 2) { 616 *
617 /* move skb->data to current_tx_ptr payload */ 617 * Only if data buffer is ODD WORD alignment, we do not
618 data = (unsigned int)(skb->data) - 2; 618 * need to memcpy
619 *((unsigned short *)data) = (unsigned short)(skb->len); 619 */
620 current_tx_ptr->desc_a.start_addr = (unsigned long)data; 620 u32 data_align = (u32)(skb->data) & 0x3;
621 /* this is important! */ 621 if (data_align == 0x2) {
622 blackfin_dcache_flush_range(data, (data + (skb->len)) + 2); 622 /* move skb->data to current_tx_ptr payload */
623 623 data = (u16 *)(skb->data) - 1;
624 *data = (u16)(skb->len);
625 current_tx_ptr->desc_a.start_addr = (u32)data;
626 /* this is important! */
627 blackfin_dcache_flush_range((u32)data,
628 (u32)((u8 *)data + skb->len + 4));
629 } else {
630 *((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len);
631 memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data,
632 skb->len);
633 current_tx_ptr->desc_a.start_addr =
634 (u32)current_tx_ptr->packet;
635 if (current_tx_ptr->status.status_word != 0)
636 current_tx_ptr->status.status_word = 0;
637 blackfin_dcache_flush_range(
638 (u32)current_tx_ptr->packet,
639 (u32)(current_tx_ptr->packet + skb->len + 2));
640 }
624 } else { 641 } else {
625 *((unsigned short *)(current_tx_ptr->packet)) = 642 /*
626 (unsigned short)(skb->len); 643 * TXDWA feature is avaible to revision < 0.3 silicon of
627 memcpy((char *)(current_tx_ptr->packet + 2), skb->data, 644 * BF537 and always avaible to BF52x
628 (skb->len)); 645 */
629 current_tx_ptr->desc_a.start_addr = 646 u32 data_align = (u32)(skb->data) & 0x3;
630 (unsigned long)current_tx_ptr->packet; 647 if (data_align == 0x0) {
631 if (current_tx_ptr->status.status_word != 0) 648 u16 sysctl = bfin_read_EMAC_SYSCTL();
632 current_tx_ptr->status.status_word = 0; 649 sysctl |= TXDWA;
633 blackfin_dcache_flush_range((unsigned int)current_tx_ptr-> 650 bfin_write_EMAC_SYSCTL(sysctl);
634 packet, 651
635 (unsigned int)(current_tx_ptr-> 652 /* move skb->data to current_tx_ptr payload */
636 packet + skb->len) + 653 data = (u16 *)(skb->data) - 2;
637 2); 654 *data = (u16)(skb->len);
655 current_tx_ptr->desc_a.start_addr = (u32)data;
656 /* this is important! */
657 blackfin_dcache_flush_range(
658 (u32)data,
659 (u32)((u8 *)data + skb->len + 4));
660 } else if (data_align == 0x2) {
661 u16 sysctl = bfin_read_EMAC_SYSCTL();
662 sysctl &= ~TXDWA;
663 bfin_write_EMAC_SYSCTL(sysctl);
664
665 /* move skb->data to current_tx_ptr payload */
666 data = (u16 *)(skb->data) - 1;
667 *data = (u16)(skb->len);
668 current_tx_ptr->desc_a.start_addr = (u32)data;
669 /* this is important! */
670 blackfin_dcache_flush_range(
671 (u32)data,
672 (u32)((u8 *)data + skb->len + 4));
673 } else {
674 u16 sysctl = bfin_read_EMAC_SYSCTL();
675 sysctl &= ~TXDWA;
676 bfin_write_EMAC_SYSCTL(sysctl);
677
678 *((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len);
679 memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data,
680 skb->len);
681 current_tx_ptr->desc_a.start_addr =
682 (u32)current_tx_ptr->packet;
683 if (current_tx_ptr->status.status_word != 0)
684 current_tx_ptr->status.status_word = 0;
685 blackfin_dcache_flush_range(
686 (u32)current_tx_ptr->packet,
687 (u32)(current_tx_ptr->packet + skb->len + 2));
688 }
638 } 689 }
639 690
640 /* enable this packet's dma */ 691 /* enable this packet's dma */
@@ -691,7 +742,6 @@ static void bfin_mac_rx(struct net_device *dev)
691 (unsigned long)skb->tail); 742 (unsigned long)skb->tail);
692 743
693 dev->last_rx = jiffies; 744 dev->last_rx = jiffies;
694 skb->dev = dev;
695 skb->protocol = eth_type_trans(skb, dev); 745 skb->protocol = eth_type_trans(skb, dev);
696#if defined(BFIN_MAC_CSUM_OFFLOAD) 746#if defined(BFIN_MAC_CSUM_OFFLOAD)
697 skb->csum = current_rx_ptr->status.ip_payload_csum; 747 skb->csum = current_rx_ptr->status.ip_payload_csum;
@@ -920,6 +970,7 @@ static int bfin_mac_open(struct net_device *dev)
920 phy_start(lp->phydev); 970 phy_start(lp->phydev);
921 phy_write(lp->phydev, MII_BMCR, BMCR_RESET); 971 phy_write(lp->phydev, MII_BMCR, BMCR_RESET);
922 setup_system_regs(dev); 972 setup_system_regs(dev);
973 setup_mac_addr(dev->dev_addr);
923 bfin_mac_disable(); 974 bfin_mac_disable();
924 bfin_mac_enable(); 975 bfin_mac_enable();
925 pr_debug("hardware init finished\n"); 976 pr_debug("hardware init finished\n");
@@ -955,7 +1006,7 @@ static int bfin_mac_close(struct net_device *dev)
955 return 0; 1006 return 0;
956} 1007}
957 1008
958static int __init bfin_mac_probe(struct platform_device *pdev) 1009static int __devinit bfin_mac_probe(struct platform_device *pdev)
959{ 1010{
960 struct net_device *ndev; 1011 struct net_device *ndev;
961 struct bfin_mac_local *lp; 1012 struct bfin_mac_local *lp;
@@ -1081,7 +1132,7 @@ out_err_probe_mac:
1081 return rc; 1132 return rc;
1082} 1133}
1083 1134
1084static int bfin_mac_remove(struct platform_device *pdev) 1135static int __devexit bfin_mac_remove(struct platform_device *pdev)
1085{ 1136{
1086 struct net_device *ndev = platform_get_drvdata(pdev); 1137 struct net_device *ndev = platform_get_drvdata(pdev);
1087 struct bfin_mac_local *lp = netdev_priv(ndev); 1138 struct bfin_mac_local *lp = netdev_priv(ndev);
@@ -1128,7 +1179,7 @@ static int bfin_mac_resume(struct platform_device *pdev)
1128 1179
1129static struct platform_driver bfin_mac_driver = { 1180static struct platform_driver bfin_mac_driver = {
1130 .probe = bfin_mac_probe, 1181 .probe = bfin_mac_probe,
1131 .remove = bfin_mac_remove, 1182 .remove = __devexit_p(bfin_mac_remove),
1132 .resume = bfin_mac_resume, 1183 .resume = bfin_mac_resume,
1133 .suspend = bfin_mac_suspend, 1184 .suspend = bfin_mac_suspend,
1134 .driver = { 1185 .driver = {
diff --git a/drivers/net/cxgb3/t3_hw.c b/drivers/net/cxgb3/t3_hw.c
index 47d51788a462..04c0e90119af 100644
--- a/drivers/net/cxgb3/t3_hw.c
+++ b/drivers/net/cxgb3/t3_hw.c
@@ -683,7 +683,7 @@ enum {
683 SF_ERASE_SECTOR = 0xd8, /* erase sector */ 683 SF_ERASE_SECTOR = 0xd8, /* erase sector */
684 684
685 FW_FLASH_BOOT_ADDR = 0x70000, /* start address of FW in flash */ 685 FW_FLASH_BOOT_ADDR = 0x70000, /* start address of FW in flash */
686 FW_VERS_ADDR = 0x77ffc, /* flash address holding FW version */ 686 FW_VERS_ADDR = 0x7fffc, /* flash address holding FW version */
687 FW_MIN_SIZE = 8 /* at least version and csum */ 687 FW_MIN_SIZE = 8 /* at least version and csum */
688}; 688};
689 689
diff --git a/drivers/net/ehea/ehea_main.c b/drivers/net/ehea/ehea_main.c
index 0920b796bd78..b70c5314f537 100644
--- a/drivers/net/ehea/ehea_main.c
+++ b/drivers/net/ehea/ehea_main.c
@@ -2937,9 +2937,9 @@ static void ehea_rereg_mrs(struct work_struct *work)
2937 } 2937 }
2938 } 2938 }
2939 } 2939 }
2940 mutex_unlock(&dlpar_mem_lock); 2940 ehea_info("re-initializing driver complete");
2941 ehea_info("re-initializing driver complete");
2942out: 2941out:
2942 mutex_unlock(&dlpar_mem_lock);
2943 return; 2943 return;
2944} 2944}
2945 2945
diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c
index c05cb159c772..aa0bf6e1c694 100644
--- a/drivers/net/enc28j60.c
+++ b/drivers/net/enc28j60.c
@@ -1547,8 +1547,10 @@ static int __devinit enc28j60_probe(struct spi_device *spi)
1547 random_ether_addr(dev->dev_addr); 1547 random_ether_addr(dev->dev_addr);
1548 enc28j60_set_hw_macaddr(dev); 1548 enc28j60_set_hw_macaddr(dev);
1549 1549
1550 ret = request_irq(spi->irq, enc28j60_irq, IRQF_TRIGGER_FALLING, 1550 /* Board setup must set the relevant edge trigger type;
1551 DRV_NAME, priv); 1551 * level triggers won't currently work.
1552 */
1553 ret = request_irq(spi->irq, enc28j60_irq, 0, DRV_NAME, priv);
1552 if (ret < 0) { 1554 if (ret < 0) {
1553 if (netif_msg_probe(priv)) 1555 if (netif_msg_probe(priv))
1554 dev_err(&spi->dev, DRV_NAME ": request irq %d failed " 1556 dev_err(&spi->dev, DRV_NAME ": request irq %d failed "
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index 4ed89fa9ae46..01b38b092c76 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -333,6 +333,7 @@ enum {
333 NvRegPowerState2 = 0x600, 333 NvRegPowerState2 = 0x600,
334#define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11 334#define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11
335#define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001 335#define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
336#define NVREG_POWERSTATE2_PHY_RESET 0x0004
336}; 337};
337 338
338/* Big endian: should work, but is untested */ 339/* Big endian: should work, but is untested */
@@ -529,6 +530,7 @@ union ring_type {
529#define PHY_REALTEK_INIT_REG4 0x14 530#define PHY_REALTEK_INIT_REG4 0x14
530#define PHY_REALTEK_INIT_REG5 0x18 531#define PHY_REALTEK_INIT_REG5 0x18
531#define PHY_REALTEK_INIT_REG6 0x11 532#define PHY_REALTEK_INIT_REG6 0x11
533#define PHY_REALTEK_INIT_REG7 0x01
532#define PHY_REALTEK_INIT1 0x0000 534#define PHY_REALTEK_INIT1 0x0000
533#define PHY_REALTEK_INIT2 0x8e00 535#define PHY_REALTEK_INIT2 0x8e00
534#define PHY_REALTEK_INIT3 0x0001 536#define PHY_REALTEK_INIT3 0x0001
@@ -537,6 +539,9 @@ union ring_type {
537#define PHY_REALTEK_INIT6 0xf5c7 539#define PHY_REALTEK_INIT6 0xf5c7
538#define PHY_REALTEK_INIT7 0x1000 540#define PHY_REALTEK_INIT7 0x1000
539#define PHY_REALTEK_INIT8 0x0003 541#define PHY_REALTEK_INIT8 0x0003
542#define PHY_REALTEK_INIT9 0x0008
543#define PHY_REALTEK_INIT10 0x0005
544#define PHY_REALTEK_INIT11 0x0200
540#define PHY_REALTEK_INIT_MSK1 0x0003 545#define PHY_REALTEK_INIT_MSK1 0x0003
541 546
542#define PHY_GIGABIT 0x0100 547#define PHY_GIGABIT 0x0100
@@ -1149,6 +1154,42 @@ static int phy_init(struct net_device *dev)
1149 return PHY_ERROR; 1154 return PHY_ERROR;
1150 } 1155 }
1151 } 1156 }
1157 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1158 np->phy_rev == PHY_REV_REALTEK_8211C) {
1159 u32 powerstate = readl(base + NvRegPowerState2);
1160
1161 /* need to perform hw phy reset */
1162 powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1163 writel(powerstate, base + NvRegPowerState2);
1164 msleep(25);
1165
1166 powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1167 writel(powerstate, base + NvRegPowerState2);
1168 msleep(25);
1169
1170 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1171 reg |= PHY_REALTEK_INIT9;
1172 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) {
1173 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1174 return PHY_ERROR;
1175 }
1176 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) {
1177 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1178 return PHY_ERROR;
1179 }
1180 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1181 if (!(reg & PHY_REALTEK_INIT11)) {
1182 reg |= PHY_REALTEK_INIT11;
1183 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) {
1184 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1185 return PHY_ERROR;
1186 }
1187 }
1188 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1189 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1190 return PHY_ERROR;
1191 }
1192 }
1152 if (np->phy_model == PHY_MODEL_REALTEK_8201) { 1193 if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1153 if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 || 1194 if (np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
1154 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 || 1195 np->device_id == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
@@ -1201,12 +1242,23 @@ static int phy_init(struct net_device *dev)
1201 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); 1242 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1202 mii_control |= BMCR_ANENABLE; 1243 mii_control |= BMCR_ANENABLE;
1203 1244
1204 /* reset the phy 1245 if (np->phy_oui == PHY_OUI_REALTEK &&
1205 * (certain phys need bmcr to be setup with reset) 1246 np->phy_model == PHY_MODEL_REALTEK_8211 &&
1206 */ 1247 np->phy_rev == PHY_REV_REALTEK_8211C) {
1207 if (phy_reset(dev, mii_control)) { 1248 /* start autoneg since we already performed hw reset above */
1208 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev)); 1249 mii_control |= BMCR_ANRESTART;
1209 return PHY_ERROR; 1250 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1251 printk(KERN_INFO "%s: phy init failed\n", pci_name(np->pci_dev));
1252 return PHY_ERROR;
1253 }
1254 } else {
1255 /* reset the phy
1256 * (certain phys need bmcr to be setup with reset)
1257 */
1258 if (phy_reset(dev, mii_control)) {
1259 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1260 return PHY_ERROR;
1261 }
1210 } 1262 }
1211 1263
1212 /* phy vendor specific configuration */ 1264 /* phy vendor specific configuration */
diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
index 8a97a0066a88..46819af3b062 100644
--- a/drivers/net/mv643xx_eth.c
+++ b/drivers/net/mv643xx_eth.c
@@ -55,7 +55,7 @@
55#include <asm/system.h> 55#include <asm/system.h>
56 56
57static char mv643xx_eth_driver_name[] = "mv643xx_eth"; 57static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58static char mv643xx_eth_driver_version[] = "1.1"; 58static char mv643xx_eth_driver_version[] = "1.2";
59 59
60#define MV643XX_ETH_CHECKSUM_OFFLOAD_TX 60#define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61#define MV643XX_ETH_NAPI 61#define MV643XX_ETH_NAPI
@@ -90,12 +90,21 @@ static char mv643xx_eth_driver_version[] = "1.1";
90#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10)) 90#define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
91#define PORT_STATUS(p) (0x0444 + ((p) << 10)) 91#define PORT_STATUS(p) (0x0444 + ((p) << 10))
92#define TX_FIFO_EMPTY 0x00000400 92#define TX_FIFO_EMPTY 0x00000400
93#define TX_IN_PROGRESS 0x00000080
94#define PORT_SPEED_MASK 0x00000030
95#define PORT_SPEED_1000 0x00000010
96#define PORT_SPEED_100 0x00000020
97#define PORT_SPEED_10 0x00000000
98#define FLOW_CONTROL_ENABLED 0x00000008
99#define FULL_DUPLEX 0x00000004
100#define LINK_UP 0x00000002
93#define TXQ_COMMAND(p) (0x0448 + ((p) << 10)) 101#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
94#define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10)) 102#define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
95#define TX_BW_RATE(p) (0x0450 + ((p) << 10)) 103#define TX_BW_RATE(p) (0x0450 + ((p) << 10))
96#define TX_BW_MTU(p) (0x0458 + ((p) << 10)) 104#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
97#define TX_BW_BURST(p) (0x045c + ((p) << 10)) 105#define TX_BW_BURST(p) (0x045c + ((p) << 10))
98#define INT_CAUSE(p) (0x0460 + ((p) << 10)) 106#define INT_CAUSE(p) (0x0460 + ((p) << 10))
107#define INT_TX_END_0 0x00080000
99#define INT_TX_END 0x07f80000 108#define INT_TX_END 0x07f80000
100#define INT_RX 0x0007fbfc 109#define INT_RX 0x0007fbfc
101#define INT_EXT 0x00000002 110#define INT_EXT 0x00000002
@@ -127,21 +136,21 @@ static char mv643xx_eth_driver_version[] = "1.1";
127/* 136/*
128 * SDMA configuration register. 137 * SDMA configuration register.
129 */ 138 */
130#define RX_BURST_SIZE_4_64BIT (2 << 1) 139#define RX_BURST_SIZE_16_64BIT (4 << 1)
131#define BLM_RX_NO_SWAP (1 << 4) 140#define BLM_RX_NO_SWAP (1 << 4)
132#define BLM_TX_NO_SWAP (1 << 5) 141#define BLM_TX_NO_SWAP (1 << 5)
133#define TX_BURST_SIZE_4_64BIT (2 << 22) 142#define TX_BURST_SIZE_16_64BIT (4 << 22)
134 143
135#if defined(__BIG_ENDIAN) 144#if defined(__BIG_ENDIAN)
136#define PORT_SDMA_CONFIG_DEFAULT_VALUE \ 145#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
137 RX_BURST_SIZE_4_64BIT | \ 146 RX_BURST_SIZE_16_64BIT | \
138 TX_BURST_SIZE_4_64BIT 147 TX_BURST_SIZE_16_64BIT
139#elif defined(__LITTLE_ENDIAN) 148#elif defined(__LITTLE_ENDIAN)
140#define PORT_SDMA_CONFIG_DEFAULT_VALUE \ 149#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
141 RX_BURST_SIZE_4_64BIT | \ 150 RX_BURST_SIZE_16_64BIT | \
142 BLM_RX_NO_SWAP | \ 151 BLM_RX_NO_SWAP | \
143 BLM_TX_NO_SWAP | \ 152 BLM_TX_NO_SWAP | \
144 TX_BURST_SIZE_4_64BIT 153 TX_BURST_SIZE_16_64BIT
145#else 154#else
146#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined 155#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
147#endif 156#endif
@@ -153,9 +162,7 @@ static char mv643xx_eth_driver_version[] = "1.1";
153#define SET_MII_SPEED_TO_100 (1 << 24) 162#define SET_MII_SPEED_TO_100 (1 << 24)
154#define SET_GMII_SPEED_TO_1000 (1 << 23) 163#define SET_GMII_SPEED_TO_1000 (1 << 23)
155#define SET_FULL_DUPLEX_MODE (1 << 21) 164#define SET_FULL_DUPLEX_MODE (1 << 21)
156#define MAX_RX_PACKET_1522BYTE (1 << 17)
157#define MAX_RX_PACKET_9700BYTE (5 << 17) 165#define MAX_RX_PACKET_9700BYTE (5 << 17)
158#define MAX_RX_PACKET_MASK (7 << 17)
159#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13) 166#define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
160#define DO_NOT_FORCE_LINK_FAIL (1 << 10) 167#define DO_NOT_FORCE_LINK_FAIL (1 << 10)
161#define SERIAL_PORT_CONTROL_RESERVED (1 << 9) 168#define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
@@ -228,6 +235,8 @@ struct tx_desc {
228#define GEN_IP_V4_CHECKSUM 0x00040000 235#define GEN_IP_V4_CHECKSUM 0x00040000
229#define GEN_TCP_UDP_CHECKSUM 0x00020000 236#define GEN_TCP_UDP_CHECKSUM 0x00020000
230#define UDP_FRAME 0x00010000 237#define UDP_FRAME 0x00010000
238#define MAC_HDR_EXTRA_4_BYTES 0x00008000
239#define MAC_HDR_EXTRA_8_BYTES 0x00000200
231 240
232#define TX_IHL_SHIFT 11 241#define TX_IHL_SHIFT 11
233 242
@@ -404,6 +413,17 @@ static void rxq_disable(struct rx_queue *rxq)
404 udelay(10); 413 udelay(10);
405} 414}
406 415
416static void txq_reset_hw_ptr(struct tx_queue *txq)
417{
418 struct mv643xx_eth_private *mp = txq_to_mp(txq);
419 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
420 u32 addr;
421
422 addr = (u32)txq->tx_desc_dma;
423 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
424 wrl(mp, off, addr);
425}
426
407static void txq_enable(struct tx_queue *txq) 427static void txq_enable(struct tx_queue *txq)
408{ 428{
409 struct mv643xx_eth_private *mp = txq_to_mp(txq); 429 struct mv643xx_eth_private *mp = txq_to_mp(txq);
@@ -614,6 +634,12 @@ static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
614 for (i = 0; i < 8; i++) 634 for (i = 0; i < 8; i++)
615 if (mp->txq_mask & (1 << i)) 635 if (mp->txq_mask & (1 << i))
616 txq_reclaim(mp->txq + i, 0); 636 txq_reclaim(mp->txq + i, 0);
637
638 if (netif_carrier_ok(mp->dev)) {
639 spin_lock(&mp->lock);
640 __txq_maybe_wake(mp->txq + mp->txq_primary);
641 spin_unlock(&mp->lock);
642 }
617 } 643 }
618#endif 644#endif
619 645
@@ -706,6 +732,7 @@ static inline __be16 sum16_as_be(__sum16 sum)
706 732
707static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb) 733static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
708{ 734{
735 struct mv643xx_eth_private *mp = txq_to_mp(txq);
709 int nr_frags = skb_shinfo(skb)->nr_frags; 736 int nr_frags = skb_shinfo(skb)->nr_frags;
710 int tx_index; 737 int tx_index;
711 struct tx_desc *desc; 738 struct tx_desc *desc;
@@ -732,12 +759,36 @@ static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
732 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); 759 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
733 760
734 if (skb->ip_summed == CHECKSUM_PARTIAL) { 761 if (skb->ip_summed == CHECKSUM_PARTIAL) {
735 BUG_ON(skb->protocol != htons(ETH_P_IP)); 762 int mac_hdr_len;
763
764 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
765 skb->protocol != htons(ETH_P_8021Q));
736 766
737 cmd_sts |= GEN_TCP_UDP_CHECKSUM | 767 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
738 GEN_IP_V4_CHECKSUM | 768 GEN_IP_V4_CHECKSUM |
739 ip_hdr(skb)->ihl << TX_IHL_SHIFT; 769 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
740 770
771 mac_hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
772 switch (mac_hdr_len - ETH_HLEN) {
773 case 0:
774 break;
775 case 4:
776 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
777 break;
778 case 8:
779 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
780 break;
781 case 12:
782 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
783 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
784 break;
785 default:
786 if (net_ratelimit())
787 dev_printk(KERN_ERR, &txq_to_mp(txq)->dev->dev,
788 "mac header length is %d?!\n", mac_hdr_len);
789 break;
790 }
791
741 switch (ip_hdr(skb)->protocol) { 792 switch (ip_hdr(skb)->protocol) {
742 case IPPROTO_UDP: 793 case IPPROTO_UDP:
743 cmd_sts |= UDP_FRAME; 794 cmd_sts |= UDP_FRAME;
@@ -759,6 +810,10 @@ static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
759 wmb(); 810 wmb();
760 desc->cmd_sts = cmd_sts; 811 desc->cmd_sts = cmd_sts;
761 812
813 /* clear TX_END interrupt status */
814 wrl(mp, INT_CAUSE(mp->port_num), ~(INT_TX_END_0 << txq->index));
815 rdl(mp, INT_CAUSE(mp->port_num));
816
762 /* ensure all descriptors are written before poking hardware */ 817 /* ensure all descriptors are written before poking hardware */
763 wmb(); 818 wmb();
764 txq_enable(txq); 819 txq_enable(txq);
@@ -1112,10 +1167,28 @@ static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *
1112 1167
1113static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd) 1168static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1114{ 1169{
1170 struct mv643xx_eth_private *mp = netdev_priv(dev);
1171 u32 port_status;
1172
1173 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1174
1115 cmd->supported = SUPPORTED_MII; 1175 cmd->supported = SUPPORTED_MII;
1116 cmd->advertising = ADVERTISED_MII; 1176 cmd->advertising = ADVERTISED_MII;
1117 cmd->speed = SPEED_1000; 1177 switch (port_status & PORT_SPEED_MASK) {
1118 cmd->duplex = DUPLEX_FULL; 1178 case PORT_SPEED_10:
1179 cmd->speed = SPEED_10;
1180 break;
1181 case PORT_SPEED_100:
1182 cmd->speed = SPEED_100;
1183 break;
1184 case PORT_SPEED_1000:
1185 cmd->speed = SPEED_1000;
1186 break;
1187 default:
1188 cmd->speed = -1;
1189 break;
1190 }
1191 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1119 cmd->port = PORT_MII; 1192 cmd->port = PORT_MII;
1120 cmd->phy_address = 0; 1193 cmd->phy_address = 0;
1121 cmd->transceiver = XCVR_INTERNAL; 1194 cmd->transceiver = XCVR_INTERNAL;
@@ -1539,8 +1612,11 @@ static int txq_init(struct mv643xx_eth_private *mp, int index)
1539 1612
1540 tx_desc = (struct tx_desc *)txq->tx_desc_area; 1613 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1541 for (i = 0; i < txq->tx_ring_size; i++) { 1614 for (i = 0; i < txq->tx_ring_size; i++) {
1615 struct tx_desc *txd = tx_desc + i;
1542 int nexti = (i + 1) % txq->tx_ring_size; 1616 int nexti = (i + 1) % txq->tx_ring_size;
1543 tx_desc[i].next_desc_ptr = txq->tx_desc_dma + 1617
1618 txd->cmd_sts = 0;
1619 txd->next_desc_ptr = txq->tx_desc_dma +
1544 nexti * sizeof(struct tx_desc); 1620 nexti * sizeof(struct tx_desc);
1545 } 1621 }
1546 1622
@@ -1577,8 +1653,11 @@ static void txq_reclaim(struct tx_queue *txq, int force)
1577 desc = &txq->tx_desc_area[tx_index]; 1653 desc = &txq->tx_desc_area[tx_index];
1578 cmd_sts = desc->cmd_sts; 1654 cmd_sts = desc->cmd_sts;
1579 1655
1580 if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA)) 1656 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1581 break; 1657 if (!force)
1658 break;
1659 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1660 }
1582 1661
1583 txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size; 1662 txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
1584 txq->tx_desc_count--; 1663 txq->tx_desc_count--;
@@ -1632,49 +1711,61 @@ static void txq_deinit(struct tx_queue *txq)
1632 1711
1633 1712
1634/* netdev ops and related ***************************************************/ 1713/* netdev ops and related ***************************************************/
1635static void update_pscr(struct mv643xx_eth_private *mp, int speed, int duplex) 1714static void handle_link_event(struct mv643xx_eth_private *mp)
1636{ 1715{
1637 u32 pscr_o; 1716 struct net_device *dev = mp->dev;
1638 u32 pscr_n; 1717 u32 port_status;
1639 1718 int speed;
1640 pscr_o = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num)); 1719 int duplex;
1720 int fc;
1721
1722 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1723 if (!(port_status & LINK_UP)) {
1724 if (netif_carrier_ok(dev)) {
1725 int i;
1641 1726
1642 /* clear speed, duplex and rx buffer size fields */ 1727 printk(KERN_INFO "%s: link down\n", dev->name);
1643 pscr_n = pscr_o & ~(SET_MII_SPEED_TO_100 |
1644 SET_GMII_SPEED_TO_1000 |
1645 SET_FULL_DUPLEX_MODE |
1646 MAX_RX_PACKET_MASK);
1647 1728
1648 if (speed == SPEED_1000) { 1729 netif_carrier_off(dev);
1649 pscr_n |= SET_GMII_SPEED_TO_1000 | MAX_RX_PACKET_9700BYTE; 1730 netif_stop_queue(dev);
1650 } else {
1651 if (speed == SPEED_100)
1652 pscr_n |= SET_MII_SPEED_TO_100;
1653 pscr_n |= MAX_RX_PACKET_1522BYTE;
1654 }
1655 1731
1656 if (duplex == DUPLEX_FULL) 1732 for (i = 0; i < 8; i++) {
1657 pscr_n |= SET_FULL_DUPLEX_MODE; 1733 struct tx_queue *txq = mp->txq + i;
1658 1734
1659 if (pscr_n != pscr_o) { 1735 if (mp->txq_mask & (1 << i)) {
1660 if ((pscr_o & SERIAL_PORT_ENABLE) == 0) 1736 txq_reclaim(txq, 1);
1661 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n); 1737 txq_reset_hw_ptr(txq);
1662 else { 1738 }
1663 int i; 1739 }
1740 }
1741 return;
1742 }
1664 1743
1665 for (i = 0; i < 8; i++) 1744 switch (port_status & PORT_SPEED_MASK) {
1666 if (mp->txq_mask & (1 << i)) 1745 case PORT_SPEED_10:
1667 txq_disable(mp->txq + i); 1746 speed = 10;
1747 break;
1748 case PORT_SPEED_100:
1749 speed = 100;
1750 break;
1751 case PORT_SPEED_1000:
1752 speed = 1000;
1753 break;
1754 default:
1755 speed = -1;
1756 break;
1757 }
1758 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1759 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1668 1760
1669 pscr_o &= ~SERIAL_PORT_ENABLE; 1761 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1670 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_o); 1762 "flow control %sabled\n", dev->name,
1671 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n); 1763 speed, duplex ? "full" : "half",
1672 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n); 1764 fc ? "en" : "dis");
1673 1765
1674 for (i = 0; i < 8; i++) 1766 if (!netif_carrier_ok(dev)) {
1675 if (mp->txq_mask & (1 << i)) 1767 netif_carrier_on(dev);
1676 txq_enable(mp->txq + i); 1768 netif_wake_queue(dev);
1677 }
1678 } 1769 }
1679} 1770}
1680 1771
@@ -1684,7 +1775,6 @@ static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1684 struct mv643xx_eth_private *mp = netdev_priv(dev); 1775 struct mv643xx_eth_private *mp = netdev_priv(dev);
1685 u32 int_cause; 1776 u32 int_cause;
1686 u32 int_cause_ext; 1777 u32 int_cause_ext;
1687 u32 txq_active;
1688 1778
1689 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) & 1779 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1690 (INT_TX_END | INT_RX | INT_EXT); 1780 (INT_TX_END | INT_RX | INT_EXT);
@@ -1698,30 +1788,8 @@ static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1698 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext); 1788 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1699 } 1789 }
1700 1790
1701 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) { 1791 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK))
1702 if (mp->phy_addr == -1 || mii_link_ok(&mp->mii)) { 1792 handle_link_event(mp);
1703 int i;
1704
1705 if (mp->phy_addr != -1) {
1706 struct ethtool_cmd cmd;
1707
1708 mii_ethtool_gset(&mp->mii, &cmd);
1709 update_pscr(mp, cmd.speed, cmd.duplex);
1710 }
1711
1712 for (i = 0; i < 8; i++)
1713 if (mp->txq_mask & (1 << i))
1714 txq_enable(mp->txq + i);
1715
1716 if (!netif_carrier_ok(dev)) {
1717 netif_carrier_on(dev);
1718 __txq_maybe_wake(mp->txq + mp->txq_primary);
1719 }
1720 } else if (netif_carrier_ok(dev)) {
1721 netif_stop_queue(dev);
1722 netif_carrier_off(dev);
1723 }
1724 }
1725 1793
1726 /* 1794 /*
1727 * RxBuffer or RxError set for any of the 8 queues? 1795 * RxBuffer or RxError set for any of the 8 queues?
@@ -1743,8 +1811,6 @@ static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1743 } 1811 }
1744#endif 1812#endif
1745 1813
1746 txq_active = rdl(mp, TXQ_COMMAND(mp->port_num));
1747
1748 /* 1814 /*
1749 * TxBuffer or TxError set for any of the 8 queues? 1815 * TxBuffer or TxError set for any of the 8 queues?
1750 */ 1816 */
@@ -1754,6 +1820,16 @@ static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1754 for (i = 0; i < 8; i++) 1820 for (i = 0; i < 8; i++)
1755 if (mp->txq_mask & (1 << i)) 1821 if (mp->txq_mask & (1 << i))
1756 txq_reclaim(mp->txq + i, 0); 1822 txq_reclaim(mp->txq + i, 0);
1823
1824 /*
1825 * Enough space again in the primary TX queue for a
1826 * full packet?
1827 */
1828 if (netif_carrier_ok(dev)) {
1829 spin_lock(&mp->lock);
1830 __txq_maybe_wake(mp->txq + mp->txq_primary);
1831 spin_unlock(&mp->lock);
1832 }
1757 } 1833 }
1758 1834
1759 /* 1835 /*
@@ -1763,19 +1839,25 @@ static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1763 int i; 1839 int i;
1764 1840
1765 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END)); 1841 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
1842
1843 spin_lock(&mp->lock);
1766 for (i = 0; i < 8; i++) { 1844 for (i = 0; i < 8; i++) {
1767 struct tx_queue *txq = mp->txq + i; 1845 struct tx_queue *txq = mp->txq + i;
1768 if (txq->tx_desc_count && !((txq_active >> i) & 1)) 1846 u32 hw_desc_ptr;
1847 u32 expected_ptr;
1848
1849 if ((int_cause & (INT_TX_END_0 << i)) == 0)
1850 continue;
1851
1852 hw_desc_ptr =
1853 rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, i));
1854 expected_ptr = (u32)txq->tx_desc_dma +
1855 txq->tx_curr_desc * sizeof(struct tx_desc);
1856
1857 if (hw_desc_ptr != expected_ptr)
1769 txq_enable(txq); 1858 txq_enable(txq);
1770 } 1859 }
1771 } 1860 spin_unlock(&mp->lock);
1772
1773 /*
1774 * Enough space again in the primary TX queue for a full packet?
1775 */
1776 if (int_cause_ext & INT_EXT_TX) {
1777 struct tx_queue *txq = mp->txq + mp->txq_primary;
1778 __txq_maybe_wake(txq);
1779 } 1861 }
1780 1862
1781 return IRQ_HANDLED; 1863 return IRQ_HANDLED;
@@ -1785,14 +1867,14 @@ static void phy_reset(struct mv643xx_eth_private *mp)
1785{ 1867{
1786 unsigned int data; 1868 unsigned int data;
1787 1869
1788 smi_reg_read(mp, mp->phy_addr, 0, &data); 1870 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data);
1789 data |= 0x8000; 1871 data |= BMCR_RESET;
1790 smi_reg_write(mp, mp->phy_addr, 0, data); 1872 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
1791 1873
1792 do { 1874 do {
1793 udelay(1); 1875 udelay(1);
1794 smi_reg_read(mp, mp->phy_addr, 0, &data); 1876 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data);
1795 } while (data & 0x8000); 1877 } while (data & BMCR_RESET);
1796} 1878}
1797 1879
1798static void port_start(struct mv643xx_eth_private *mp) 1880static void port_start(struct mv643xx_eth_private *mp)
@@ -1801,23 +1883,6 @@ static void port_start(struct mv643xx_eth_private *mp)
1801 int i; 1883 int i;
1802 1884
1803 /* 1885 /*
1804 * Configure basic link parameters.
1805 */
1806 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1807 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
1808 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1809 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1810 DISABLE_AUTO_NEG_SPEED_GMII |
1811 DISABLE_AUTO_NEG_FOR_DUPLEX |
1812 DO_NOT_FORCE_LINK_FAIL |
1813 SERIAL_PORT_CONTROL_RESERVED;
1814 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1815 pscr |= SERIAL_PORT_ENABLE;
1816 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1817
1818 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1819
1820 /*
1821 * Perform PHY reset, if there is a PHY. 1886 * Perform PHY reset, if there is a PHY.
1822 */ 1887 */
1823 if (mp->phy_addr != -1) { 1888 if (mp->phy_addr != -1) {
@@ -1829,21 +1894,31 @@ static void port_start(struct mv643xx_eth_private *mp)
1829 } 1894 }
1830 1895
1831 /* 1896 /*
1897 * Configure basic link parameters.
1898 */
1899 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1900
1901 pscr |= SERIAL_PORT_ENABLE;
1902 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1903
1904 pscr |= DO_NOT_FORCE_LINK_FAIL;
1905 if (mp->phy_addr == -1)
1906 pscr |= FORCE_LINK_PASS;
1907 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1908
1909 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1910
1911 /*
1832 * Configure TX path and queues. 1912 * Configure TX path and queues.
1833 */ 1913 */
1834 tx_set_rate(mp, 1000000000, 16777216); 1914 tx_set_rate(mp, 1000000000, 16777216);
1835 for (i = 0; i < 8; i++) { 1915 for (i = 0; i < 8; i++) {
1836 struct tx_queue *txq = mp->txq + i; 1916 struct tx_queue *txq = mp->txq + i;
1837 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, i);
1838 u32 addr;
1839 1917
1840 if ((mp->txq_mask & (1 << i)) == 0) 1918 if ((mp->txq_mask & (1 << i)) == 0)
1841 continue; 1919 continue;
1842 1920
1843 addr = (u32)txq->tx_desc_dma; 1921 txq_reset_hw_ptr(txq);
1844 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
1845 wrl(mp, off, addr);
1846
1847 txq_set_rate(txq, 1000000000, 16777216); 1922 txq_set_rate(txq, 1000000000, 16777216);
1848 txq_set_fixed_prio_mode(txq); 1923 txq_set_fixed_prio_mode(txq);
1849 } 1924 }
@@ -1965,6 +2040,9 @@ static int mv643xx_eth_open(struct net_device *dev)
1965 napi_enable(&mp->napi); 2040 napi_enable(&mp->napi);
1966#endif 2041#endif
1967 2042
2043 netif_carrier_off(dev);
2044 netif_stop_queue(dev);
2045
1968 port_start(mp); 2046 port_start(mp);
1969 2047
1970 set_rx_coal(mp, 0); 2048 set_rx_coal(mp, 0);
@@ -1999,8 +2077,14 @@ static void port_reset(struct mv643xx_eth_private *mp)
1999 if (mp->txq_mask & (1 << i)) 2077 if (mp->txq_mask & (1 << i))
2000 txq_disable(mp->txq + i); 2078 txq_disable(mp->txq + i);
2001 } 2079 }
2002 while (!(rdl(mp, PORT_STATUS(mp->port_num)) & TX_FIFO_EMPTY)) 2080
2081 while (1) {
2082 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2083
2084 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2085 break;
2003 udelay(10); 2086 udelay(10);
2087 }
2004 2088
2005 /* Reset the Enable bit in the Configuration Register */ 2089 /* Reset the Enable bit in the Configuration Register */
2006 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num)); 2090 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
@@ -2202,7 +2286,8 @@ static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2202 int ret; 2286 int ret;
2203 2287
2204 if (!mv643xx_eth_version_printed++) 2288 if (!mv643xx_eth_version_printed++)
2205 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n"); 2289 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2290 "driver version %s\n", mv643xx_eth_driver_version);
2206 2291
2207 ret = -EINVAL; 2292 ret = -EINVAL;
2208 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2293 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -2338,14 +2423,14 @@ static int phy_detect(struct mv643xx_eth_private *mp)
2338 unsigned int data; 2423 unsigned int data;
2339 unsigned int data2; 2424 unsigned int data2;
2340 2425
2341 smi_reg_read(mp, mp->phy_addr, 0, &data); 2426 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data);
2342 smi_reg_write(mp, mp->phy_addr, 0, data ^ 0x1000); 2427 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE);
2343 2428
2344 smi_reg_read(mp, mp->phy_addr, 0, &data2); 2429 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data2);
2345 if (((data ^ data2) & 0x1000) == 0) 2430 if (((data ^ data2) & BMCR_ANENABLE) == 0)
2346 return -ENODEV; 2431 return -ENODEV;
2347 2432
2348 smi_reg_write(mp, mp->phy_addr, 0, data); 2433 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
2349 2434
2350 return 0; 2435 return 0;
2351} 2436}
@@ -2393,12 +2478,39 @@ static int phy_init(struct mv643xx_eth_private *mp,
2393 cmd.duplex = pd->duplex; 2478 cmd.duplex = pd->duplex;
2394 } 2479 }
2395 2480
2396 update_pscr(mp, cmd.speed, cmd.duplex);
2397 mv643xx_eth_set_settings(mp->dev, &cmd); 2481 mv643xx_eth_set_settings(mp->dev, &cmd);
2398 2482
2399 return 0; 2483 return 0;
2400} 2484}
2401 2485
2486static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2487{
2488 u32 pscr;
2489
2490 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2491 if (pscr & SERIAL_PORT_ENABLE) {
2492 pscr &= ~SERIAL_PORT_ENABLE;
2493 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2494 }
2495
2496 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2497 if (mp->phy_addr == -1) {
2498 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2499 if (speed == SPEED_1000)
2500 pscr |= SET_GMII_SPEED_TO_1000;
2501 else if (speed == SPEED_100)
2502 pscr |= SET_MII_SPEED_TO_100;
2503
2504 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2505
2506 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2507 if (duplex == DUPLEX_FULL)
2508 pscr |= SET_FULL_DUPLEX_MODE;
2509 }
2510
2511 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2512}
2513
2402static int mv643xx_eth_probe(struct platform_device *pdev) 2514static int mv643xx_eth_probe(struct platform_device *pdev)
2403{ 2515{
2404 struct mv643xx_eth_platform_data *pd; 2516 struct mv643xx_eth_platform_data *pd;
@@ -2452,6 +2564,7 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
2452 } else { 2564 } else {
2453 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless); 2565 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2454 } 2566 }
2567 init_pscr(mp, pd->speed, pd->duplex);
2455 2568
2456 2569
2457 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 2570 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
@@ -2478,6 +2591,7 @@ static int mv643xx_eth_probe(struct platform_device *pdev)
2478 * have to map the buffers to ISA memory which is only 16 MB 2591 * have to map the buffers to ISA memory which is only 16 MB
2479 */ 2592 */
2480 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM; 2593 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2594 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2481#endif 2595#endif
2482 2596
2483 SET_NETDEV_DEV(dev, &pdev->dev); 2597 SET_NETDEV_DEV(dev, &pdev->dev);
diff --git a/drivers/net/ne.c b/drivers/net/ne.c
index 2fec6122c7fa..42443d697423 100644
--- a/drivers/net/ne.c
+++ b/drivers/net/ne.c
@@ -536,7 +536,7 @@ static int __init ne_probe1(struct net_device *dev, unsigned long ioaddr)
536#ifdef CONFIG_NET_POLL_CONTROLLER 536#ifdef CONFIG_NET_POLL_CONTROLLER
537 dev->poll_controller = eip_poll; 537 dev->poll_controller = eip_poll;
538#endif 538#endif
539 NS8390_init(dev, 0); 539 NS8390p_init(dev, 0);
540 540
541 ret = register_netdev(dev); 541 ret = register_netdev(dev);
542 if (ret) 542 if (ret)
@@ -794,7 +794,7 @@ retry:
794 if (time_after(jiffies, dma_start + 2*HZ/100)) { /* 20ms */ 794 if (time_after(jiffies, dma_start + 2*HZ/100)) { /* 20ms */
795 printk(KERN_WARNING "%s: timeout waiting for Tx RDC.\n", dev->name); 795 printk(KERN_WARNING "%s: timeout waiting for Tx RDC.\n", dev->name);
796 ne_reset_8390(dev); 796 ne_reset_8390(dev);
797 NS8390_init(dev,1); 797 NS8390p_init(dev, 1);
798 break; 798 break;
799 } 799 }
800 800
@@ -855,7 +855,7 @@ static int ne_drv_resume(struct platform_device *pdev)
855 855
856 if (netif_running(dev)) { 856 if (netif_running(dev)) {
857 ne_reset_8390(dev); 857 ne_reset_8390(dev);
858 NS8390_init(dev, 1); 858 NS8390p_init(dev, 1);
859 netif_device_attach(dev); 859 netif_device_attach(dev);
860 } 860 }
861 return 0; 861 return 0;
diff --git a/drivers/net/s2io.c b/drivers/net/s2io.c
index 86d77d05190a..a2b073097e5c 100644
--- a/drivers/net/s2io.c
+++ b/drivers/net/s2io.c
@@ -3143,7 +3143,7 @@ static void tx_intr_handler(struct fifo_info *fifo_data)
3143 pkt_cnt++; 3143 pkt_cnt++;
3144 3144
3145 /* Updating the statistics block */ 3145 /* Updating the statistics block */
3146 nic->stats.tx_bytes += skb->len; 3146 nic->dev->stats.tx_bytes += skb->len;
3147 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize; 3147 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
3148 dev_kfree_skb_irq(skb); 3148 dev_kfree_skb_irq(skb);
3149 3149
@@ -4896,25 +4896,42 @@ static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4896 /* Configure Stats for immediate updt */ 4896 /* Configure Stats for immediate updt */
4897 s2io_updt_stats(sp); 4897 s2io_updt_stats(sp);
4898 4898
4899 /* Using sp->stats as a staging area, because reset (due to mtu
4900 change, for example) will clear some hardware counters */
4901 dev->stats.tx_packets +=
4902 le32_to_cpu(mac_control->stats_info->tmac_frms) -
4903 sp->stats.tx_packets;
4899 sp->stats.tx_packets = 4904 sp->stats.tx_packets =
4900 le32_to_cpu(mac_control->stats_info->tmac_frms); 4905 le32_to_cpu(mac_control->stats_info->tmac_frms);
4906 dev->stats.tx_errors +=
4907 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms) -
4908 sp->stats.tx_errors;
4901 sp->stats.tx_errors = 4909 sp->stats.tx_errors =
4902 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms); 4910 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4911 dev->stats.rx_errors +=
4912 le64_to_cpu(mac_control->stats_info->rmac_drop_frms) -
4913 sp->stats.rx_errors;
4903 sp->stats.rx_errors = 4914 sp->stats.rx_errors =
4904 le64_to_cpu(mac_control->stats_info->rmac_drop_frms); 4915 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
4916 dev->stats.multicast =
4917 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms) -
4918 sp->stats.multicast;
4905 sp->stats.multicast = 4919 sp->stats.multicast =
4906 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms); 4920 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
4921 dev->stats.rx_length_errors =
4922 le64_to_cpu(mac_control->stats_info->rmac_long_frms) -
4923 sp->stats.rx_length_errors;
4907 sp->stats.rx_length_errors = 4924 sp->stats.rx_length_errors =
4908 le64_to_cpu(mac_control->stats_info->rmac_long_frms); 4925 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
4909 4926
4910 /* collect per-ring rx_packets and rx_bytes */ 4927 /* collect per-ring rx_packets and rx_bytes */
4911 sp->stats.rx_packets = sp->stats.rx_bytes = 0; 4928 dev->stats.rx_packets = dev->stats.rx_bytes = 0;
4912 for (i = 0; i < config->rx_ring_num; i++) { 4929 for (i = 0; i < config->rx_ring_num; i++) {
4913 sp->stats.rx_packets += mac_control->rings[i].rx_packets; 4930 dev->stats.rx_packets += mac_control->rings[i].rx_packets;
4914 sp->stats.rx_bytes += mac_control->rings[i].rx_bytes; 4931 dev->stats.rx_bytes += mac_control->rings[i].rx_bytes;
4915 } 4932 }
4916 4933
4917 return (&sp->stats); 4934 return (&dev->stats);
4918} 4935}
4919 4936
4920/** 4937/**
@@ -7419,7 +7436,7 @@ static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
7419 if (err_mask != 0x5) { 7436 if (err_mask != 0x5) {
7420 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n", 7437 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7421 dev->name, err_mask); 7438 dev->name, err_mask);
7422 sp->stats.rx_crc_errors++; 7439 dev->stats.rx_crc_errors++;
7423 sp->mac_control.stats_info->sw_stat.mem_freed 7440 sp->mac_control.stats_info->sw_stat.mem_freed
7424 += skb->truesize; 7441 += skb->truesize;
7425 dev_kfree_skb(skb); 7442 dev_kfree_skb(skb);
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index c69ba1395fa9..6a06b9503e4f 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SuperH Ethernet device driver 2 * SuperH Ethernet device driver
3 * 3 *
4 * Copyright (C) 2006,2007 Nobuhiro Iwamatsu 4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
5 * Copyright (C) 2008 Renesas Solutions Corp. 5 * Copyright (C) 2008 Renesas Solutions Corp.
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
@@ -143,13 +143,39 @@ static struct mdiobb_ops bb_ops = {
143 .get_mdio_data = sh_get_mdio, 143 .get_mdio_data = sh_get_mdio,
144}; 144};
145 145
146/* Chip Reset */
146static void sh_eth_reset(struct net_device *ndev) 147static void sh_eth_reset(struct net_device *ndev)
147{ 148{
148 u32 ioaddr = ndev->base_addr; 149 u32 ioaddr = ndev->base_addr;
149 150
151#if defined(CONFIG_CPU_SUBTYPE_SH7763)
152 int cnt = 100;
153
154 ctrl_outl(EDSR_ENALL, ioaddr + EDSR);
155 ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
156 while (cnt > 0) {
157 if (!(ctrl_inl(ioaddr + EDMR) & 0x3))
158 break;
159 mdelay(1);
160 cnt--;
161 }
162 if (cnt < 0)
163 printk(KERN_ERR "Device reset fail\n");
164
165 /* Table Init */
166 ctrl_outl(0x0, ioaddr + TDLAR);
167 ctrl_outl(0x0, ioaddr + TDFAR);
168 ctrl_outl(0x0, ioaddr + TDFXR);
169 ctrl_outl(0x0, ioaddr + TDFFR);
170 ctrl_outl(0x0, ioaddr + RDLAR);
171 ctrl_outl(0x0, ioaddr + RDFAR);
172 ctrl_outl(0x0, ioaddr + RDFXR);
173 ctrl_outl(0x0, ioaddr + RDFFR);
174#else
150 ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR); 175 ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
151 mdelay(3); 176 mdelay(3);
152 ctrl_outl(ctrl_inl(ioaddr + EDMR) & ~EDMR_SRST, ioaddr + EDMR); 177 ctrl_outl(ctrl_inl(ioaddr + EDMR) & ~EDMR_SRST, ioaddr + EDMR);
178#endif
153} 179}
154 180
155/* free skb and descriptor buffer */ 181/* free skb and descriptor buffer */
@@ -180,6 +206,7 @@ static void sh_eth_ring_free(struct net_device *ndev)
180/* format skb and descriptor buffer */ 206/* format skb and descriptor buffer */
181static void sh_eth_ring_format(struct net_device *ndev) 207static void sh_eth_ring_format(struct net_device *ndev)
182{ 208{
209 u32 ioaddr = ndev->base_addr, reserve = 0;
183 struct sh_eth_private *mdp = netdev_priv(ndev); 210 struct sh_eth_private *mdp = netdev_priv(ndev);
184 int i; 211 int i;
185 struct sk_buff *skb; 212 struct sk_buff *skb;
@@ -201,9 +228,15 @@ static void sh_eth_ring_format(struct net_device *ndev)
201 mdp->rx_skbuff[i] = skb; 228 mdp->rx_skbuff[i] = skb;
202 if (skb == NULL) 229 if (skb == NULL)
203 break; 230 break;
204 skb->dev = ndev; /* Mark as being used by this device. */ 231 skb->dev = ndev; /* Mark as being used by this device. */
232#if defined(CONFIG_CPU_SUBTYPE_SH7763)
233 reserve = SH7763_SKB_ALIGN
234 - ((uint32_t)skb->data & (SH7763_SKB_ALIGN-1));
235 if (reserve)
236 skb_reserve(skb, reserve);
237#else
205 skb_reserve(skb, RX_OFFSET); 238 skb_reserve(skb, RX_OFFSET);
206 239#endif
207 /* RX descriptor */ 240 /* RX descriptor */
208 rxdesc = &mdp->rx_ring[i]; 241 rxdesc = &mdp->rx_ring[i];
209 rxdesc->addr = (u32)skb->data & ~0x3UL; 242 rxdesc->addr = (u32)skb->data & ~0x3UL;
@@ -211,12 +244,25 @@ static void sh_eth_ring_format(struct net_device *ndev)
211 244
212 /* The size of the buffer is 16 byte boundary. */ 245 /* The size of the buffer is 16 byte boundary. */
213 rxdesc->buffer_length = (mdp->rx_buf_sz + 16) & ~0x0F; 246 rxdesc->buffer_length = (mdp->rx_buf_sz + 16) & ~0x0F;
247 /* Rx descriptor address set */
248 if (i == 0) {
249 ctrl_outl((u32)rxdesc, ioaddr + RDLAR);
250#if defined(CONFIG_CPU_SUBTYPE_SH7763)
251 ctrl_outl((u32)rxdesc, ioaddr + RDFAR);
252#endif
253 }
214 } 254 }
215 255
256 /* Rx descriptor address set */
257#if defined(CONFIG_CPU_SUBTYPE_SH7763)
258 ctrl_outl((u32)rxdesc, ioaddr + RDFXR);
259 ctrl_outl(0x1, ioaddr + RDFFR);
260#endif
261
216 mdp->dirty_rx = (u32) (i - RX_RING_SIZE); 262 mdp->dirty_rx = (u32) (i - RX_RING_SIZE);
217 263
218 /* Mark the last entry as wrapping the ring. */ 264 /* Mark the last entry as wrapping the ring. */
219 rxdesc->status |= cpu_to_le32(RC_RDEL); 265 rxdesc->status |= cpu_to_le32(RD_RDEL);
220 266
221 memset(mdp->tx_ring, 0, tx_ringsize); 267 memset(mdp->tx_ring, 0, tx_ringsize);
222 268
@@ -226,8 +272,21 @@ static void sh_eth_ring_format(struct net_device *ndev)
226 txdesc = &mdp->tx_ring[i]; 272 txdesc = &mdp->tx_ring[i];
227 txdesc->status = cpu_to_le32(TD_TFP); 273 txdesc->status = cpu_to_le32(TD_TFP);
228 txdesc->buffer_length = 0; 274 txdesc->buffer_length = 0;
275 if (i == 0) {
276 /* Rx descriptor address set */
277 ctrl_outl((u32)txdesc, ioaddr + TDLAR);
278#if defined(CONFIG_CPU_SUBTYPE_SH7763)
279 ctrl_outl((u32)txdesc, ioaddr + TDFAR);
280#endif
281 }
229 } 282 }
230 283
284 /* Rx descriptor address set */
285#if defined(CONFIG_CPU_SUBTYPE_SH7763)
286 ctrl_outl((u32)txdesc, ioaddr + TDFXR);
287 ctrl_outl(0x1, ioaddr + TDFFR);
288#endif
289
231 txdesc->status |= cpu_to_le32(TD_TDLE); 290 txdesc->status |= cpu_to_le32(TD_TDLE);
232} 291}
233 292
@@ -311,31 +370,43 @@ static int sh_eth_dev_init(struct net_device *ndev)
311 /* Soft Reset */ 370 /* Soft Reset */
312 sh_eth_reset(ndev); 371 sh_eth_reset(ndev);
313 372
314 ctrl_outl(RPADIR_PADS1, ioaddr + RPADIR); /* SH7712-DMA-RX-PAD2 */ 373 /* Descriptor format */
374 sh_eth_ring_format(ndev);
375 ctrl_outl(RPADIR_INIT, ioaddr + RPADIR);
315 376
316 /* all sh_eth int mask */ 377 /* all sh_eth int mask */
317 ctrl_outl(0, ioaddr + EESIPR); 378 ctrl_outl(0, ioaddr + EESIPR);
318 379
319 /* FIFO size set */ 380#if defined(CONFIG_CPU_SUBTYPE_SH7763)
381 ctrl_outl(EDMR_EL, ioaddr + EDMR);
382#else
320 ctrl_outl(0, ioaddr + EDMR); /* Endian change */ 383 ctrl_outl(0, ioaddr + EDMR); /* Endian change */
384#endif
321 385
386 /* FIFO size set */
322 ctrl_outl((FIFO_SIZE_T | FIFO_SIZE_R), ioaddr + FDR); 387 ctrl_outl((FIFO_SIZE_T | FIFO_SIZE_R), ioaddr + FDR);
323 ctrl_outl(0, ioaddr + TFTR); 388 ctrl_outl(0, ioaddr + TFTR);
324 389
390 /* Frame recv control */
325 ctrl_outl(0, ioaddr + RMCR); 391 ctrl_outl(0, ioaddr + RMCR);
326 392
327 rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5; 393 rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
328 tx_int_var = mdp->tx_int_var = DESC_I_TINT2; 394 tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
329 ctrl_outl(rx_int_var | tx_int_var, ioaddr + TRSCER); 395 ctrl_outl(rx_int_var | tx_int_var, ioaddr + TRSCER);
330 396
397#if defined(CONFIG_CPU_SUBTYPE_SH7763)
398 /* Burst sycle set */
399 ctrl_outl(0x800, ioaddr + BCULR);
400#endif
401
331 ctrl_outl((FIFO_F_D_RFF | FIFO_F_D_RFD), ioaddr + FCFTR); 402 ctrl_outl((FIFO_F_D_RFF | FIFO_F_D_RFD), ioaddr + FCFTR);
332 ctrl_outl(0, ioaddr + TRIMD);
333 403
334 /* Descriptor format */ 404#if !defined(CONFIG_CPU_SUBTYPE_SH7763)
335 sh_eth_ring_format(ndev); 405 ctrl_outl(0, ioaddr + TRIMD);
406#endif
336 407
337 ctrl_outl((u32)mdp->rx_ring, ioaddr + RDLAR); 408 /* Recv frame limit set register */
338 ctrl_outl((u32)mdp->tx_ring, ioaddr + TDLAR); 409 ctrl_outl(RFLR_VALUE, ioaddr + RFLR);
339 410
340 ctrl_outl(ctrl_inl(ioaddr + EESR), ioaddr + EESR); 411 ctrl_outl(ctrl_inl(ioaddr + EESR), ioaddr + EESR);
341 ctrl_outl((DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff), ioaddr + EESIPR); 412 ctrl_outl((DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff), ioaddr + EESIPR);
@@ -345,21 +416,26 @@ static int sh_eth_dev_init(struct net_device *ndev)
345 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE; 416 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
346 417
347 ctrl_outl(val, ioaddr + ECMR); 418 ctrl_outl(val, ioaddr + ECMR);
348 ctrl_outl(ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | 419
349 ECSIPR_MPDIP, ioaddr + ECSR); 420 /* E-MAC Status Register clear */
350 ctrl_outl(ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | 421 ctrl_outl(ECSR_INIT, ioaddr + ECSR);
351 ECSIPR_ICDIP | ECSIPR_MPDIP, ioaddr + ECSIPR); 422
423 /* E-MAC Interrupt Enable register */
424 ctrl_outl(ECSIPR_INIT, ioaddr + ECSIPR);
352 425
353 /* Set MAC address */ 426 /* Set MAC address */
354 update_mac_address(ndev); 427 update_mac_address(ndev);
355 428
356 /* mask reset */ 429 /* mask reset */
357#if defined(CONFIG_CPU_SUBTYPE_SH7710) 430#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7763)
358 ctrl_outl(APR_AP, ioaddr + APR); 431 ctrl_outl(APR_AP, ioaddr + APR);
359 ctrl_outl(MPR_MP, ioaddr + MPR); 432 ctrl_outl(MPR_MP, ioaddr + MPR);
360 ctrl_outl(TPAUSER_UNLIMITED, ioaddr + TPAUSER); 433 ctrl_outl(TPAUSER_UNLIMITED, ioaddr + TPAUSER);
434#endif
435#if defined(CONFIG_CPU_SUBTYPE_SH7710)
361 ctrl_outl(BCFR_UNLIMITED, ioaddr + BCFR); 436 ctrl_outl(BCFR_UNLIMITED, ioaddr + BCFR);
362#endif 437#endif
438
363 /* Setting the Rx mode will start the Rx process. */ 439 /* Setting the Rx mode will start the Rx process. */
364 ctrl_outl(EDRRR_R, ioaddr + EDRRR); 440 ctrl_outl(EDRRR_R, ioaddr + EDRRR);
365 441
@@ -407,7 +483,7 @@ static int sh_eth_rx(struct net_device *ndev)
407 int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx; 483 int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx;
408 struct sk_buff *skb; 484 struct sk_buff *skb;
409 u16 pkt_len = 0; 485 u16 pkt_len = 0;
410 u32 desc_status; 486 u32 desc_status, reserve = 0;
411 487
412 rxdesc = &mdp->rx_ring[entry]; 488 rxdesc = &mdp->rx_ring[entry];
413 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) { 489 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
@@ -454,28 +530,38 @@ static int sh_eth_rx(struct net_device *ndev)
454 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { 530 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
455 entry = mdp->dirty_rx % RX_RING_SIZE; 531 entry = mdp->dirty_rx % RX_RING_SIZE;
456 rxdesc = &mdp->rx_ring[entry]; 532 rxdesc = &mdp->rx_ring[entry];
533 /* The size of the buffer is 16 byte boundary. */
534 rxdesc->buffer_length = (mdp->rx_buf_sz + 16) & ~0x0F;
535
457 if (mdp->rx_skbuff[entry] == NULL) { 536 if (mdp->rx_skbuff[entry] == NULL) {
458 skb = dev_alloc_skb(mdp->rx_buf_sz); 537 skb = dev_alloc_skb(mdp->rx_buf_sz);
459 mdp->rx_skbuff[entry] = skb; 538 mdp->rx_skbuff[entry] = skb;
460 if (skb == NULL) 539 if (skb == NULL)
461 break; /* Better luck next round. */ 540 break; /* Better luck next round. */
462 skb->dev = ndev; 541 skb->dev = ndev;
542#if defined(CONFIG_CPU_SUBTYPE_SH7763)
543 reserve = SH7763_SKB_ALIGN
544 - ((uint32_t)skb->data & (SH7763_SKB_ALIGN-1));
545 if (reserve)
546 skb_reserve(skb, reserve);
547#else
463 skb_reserve(skb, RX_OFFSET); 548 skb_reserve(skb, RX_OFFSET);
549#endif
550 skb->ip_summed = CHECKSUM_NONE;
464 rxdesc->addr = (u32)skb->data & ~0x3UL; 551 rxdesc->addr = (u32)skb->data & ~0x3UL;
465 } 552 }
466 /* The size of the buffer is 16 byte boundary. */
467 rxdesc->buffer_length = (mdp->rx_buf_sz + 16) & ~0x0F;
468 if (entry >= RX_RING_SIZE - 1) 553 if (entry >= RX_RING_SIZE - 1)
469 rxdesc->status |= 554 rxdesc->status |=
470 cpu_to_le32(RD_RACT | RD_RFP | RC_RDEL); 555 cpu_to_le32(RD_RACT | RD_RFP | RD_RDEL);
471 else 556 else
472 rxdesc->status |= 557 rxdesc->status |=
473 cpu_to_le32(RD_RACT | RD_RFP); 558 cpu_to_le32(RD_RACT | RD_RFP);
474 } 559 }
475 560
476 /* Restart Rx engine if stopped. */ 561 /* Restart Rx engine if stopped. */
477 /* If we don't need to check status, don't. -KDU */ 562 /* If we don't need to check status, don't. -KDU */
478 ctrl_outl(EDRRR_R, ndev->base_addr + EDRRR); 563 if (!(ctrl_inl(ndev->base_addr + EDRRR) & EDRRR_R))
564 ctrl_outl(EDRRR_R, ndev->base_addr + EDRRR);
479 565
480 return 0; 566 return 0;
481} 567}
@@ -529,13 +615,14 @@ static void sh_eth_error(struct net_device *ndev, int intr_status)
529 printk(KERN_ERR "Receive Frame Overflow\n"); 615 printk(KERN_ERR "Receive Frame Overflow\n");
530 } 616 }
531 } 617 }
532 618#if !defined(CONFIG_CPU_SUBTYPE_SH7763)
533 if (intr_status & EESR_ADE) { 619 if (intr_status & EESR_ADE) {
534 if (intr_status & EESR_TDE) { 620 if (intr_status & EESR_TDE) {
535 if (intr_status & EESR_TFE) 621 if (intr_status & EESR_TFE)
536 mdp->stats.tx_fifo_errors++; 622 mdp->stats.tx_fifo_errors++;
537 } 623 }
538 } 624 }
625#endif
539 626
540 if (intr_status & EESR_RDE) { 627 if (intr_status & EESR_RDE) {
541 /* Receive Descriptor Empty int */ 628 /* Receive Descriptor Empty int */
@@ -550,8 +637,11 @@ static void sh_eth_error(struct net_device *ndev, int intr_status)
550 mdp->stats.rx_fifo_errors++; 637 mdp->stats.rx_fifo_errors++;
551 printk(KERN_ERR "Receive FIFO Overflow\n"); 638 printk(KERN_ERR "Receive FIFO Overflow\n");
552 } 639 }
553 if (intr_status & 640 if (intr_status & (EESR_TWB | EESR_TABT |
554 (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)) { 641#if !defined(CONFIG_CPU_SUBTYPE_SH7763)
642 EESR_ADE |
643#endif
644 EESR_TDE | EESR_TFE)) {
555 /* Tx error */ 645 /* Tx error */
556 u32 edtrr = ctrl_inl(ndev->base_addr + EDTRR); 646 u32 edtrr = ctrl_inl(ndev->base_addr + EDTRR);
557 /* dmesg */ 647 /* dmesg */
@@ -582,17 +672,23 @@ static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
582 ioaddr = ndev->base_addr; 672 ioaddr = ndev->base_addr;
583 spin_lock(&mdp->lock); 673 spin_lock(&mdp->lock);
584 674
675 /* Get interrpt stat */
585 intr_status = ctrl_inl(ioaddr + EESR); 676 intr_status = ctrl_inl(ioaddr + EESR);
586 /* Clear interrupt */ 677 /* Clear interrupt */
587 ctrl_outl(intr_status, ioaddr + EESR); 678 ctrl_outl(intr_status, ioaddr + EESR);
588 679
589 if (intr_status & (EESR_FRC | EESR_RINT8 | 680 if (intr_status & (EESR_FRC | /* Frame recv*/
590 EESR_RINT5 | EESR_RINT4 | EESR_RINT3 | EESR_RINT2 | 681 EESR_RMAF | /* Multi cast address recv*/
591 EESR_RINT1)) 682 EESR_RRF | /* Bit frame recv */
683 EESR_RTLF | /* Long frame recv*/
684 EESR_RTSF | /* short frame recv */
685 EESR_PRE | /* PHY-LSI recv error */
686 EESR_CERF)){ /* recv frame CRC error */
592 sh_eth_rx(ndev); 687 sh_eth_rx(ndev);
593 if (intr_status & (EESR_FTC | 688 }
594 EESR_TINT4 | EESR_TINT3 | EESR_TINT2 | EESR_TINT1)) {
595 689
690 /* Tx Check */
691 if (intr_status & TX_CHECK) {
596 sh_eth_txfree(ndev); 692 sh_eth_txfree(ndev);
597 netif_wake_queue(ndev); 693 netif_wake_queue(ndev);
598 } 694 }
@@ -631,11 +727,32 @@ static void sh_eth_adjust_link(struct net_device *ndev)
631 if (phydev->duplex != mdp->duplex) { 727 if (phydev->duplex != mdp->duplex) {
632 new_state = 1; 728 new_state = 1;
633 mdp->duplex = phydev->duplex; 729 mdp->duplex = phydev->duplex;
730#if defined(CONFIG_CPU_SUBTYPE_SH7763)
731 if (mdp->duplex) { /* FULL */
732 ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM,
733 ioaddr + ECMR);
734 } else { /* Half */
735 ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM,
736 ioaddr + ECMR);
737 }
738#endif
634 } 739 }
635 740
636 if (phydev->speed != mdp->speed) { 741 if (phydev->speed != mdp->speed) {
637 new_state = 1; 742 new_state = 1;
638 mdp->speed = phydev->speed; 743 mdp->speed = phydev->speed;
744#if defined(CONFIG_CPU_SUBTYPE_SH7763)
745 switch (mdp->speed) {
746 case 10: /* 10BASE */
747 ctrl_outl(GECMR_10, ioaddr + GECMR); break;
748 case 100:/* 100BASE */
749 ctrl_outl(GECMR_100, ioaddr + GECMR); break;
750 case 1000: /* 1000BASE */
751 ctrl_outl(GECMR_1000, ioaddr + GECMR); break;
752 default:
753 break;
754 }
755#endif
639 } 756 }
640 if (mdp->link == PHY_DOWN) { 757 if (mdp->link == PHY_DOWN) {
641 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_TXF) 758 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_TXF)
@@ -730,7 +847,7 @@ static int sh_eth_open(struct net_device *ndev)
730 /* Set the timer to check for link beat. */ 847 /* Set the timer to check for link beat. */
731 init_timer(&mdp->timer); 848 init_timer(&mdp->timer);
732 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */ 849 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
733 setup_timer(&mdp->timer, sh_eth_timer, ndev); 850 setup_timer(&mdp->timer, sh_eth_timer, (unsigned long)ndev);
734 851
735 return ret; 852 return ret;
736 853
@@ -820,7 +937,9 @@ static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
820 937
821 mdp->cur_tx++; 938 mdp->cur_tx++;
822 939
823 ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR); 940 if (!(ctrl_inl(ndev->base_addr + EDTRR) & EDTRR_TRNS))
941 ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR);
942
824 ndev->trans_start = jiffies; 943 ndev->trans_start = jiffies;
825 944
826 return 0; 945 return 0;
@@ -877,9 +996,15 @@ static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
877 ctrl_outl(0, ioaddr + CDCR); /* (write clear) */ 996 ctrl_outl(0, ioaddr + CDCR); /* (write clear) */
878 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + LCCR); 997 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + LCCR);
879 ctrl_outl(0, ioaddr + LCCR); /* (write clear) */ 998 ctrl_outl(0, ioaddr + LCCR); /* (write clear) */
999#if defined(CONFIG_CPU_SUBTYPE_SH7763)
1000 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CERCR);/* CERCR */
1001 ctrl_outl(0, ioaddr + CERCR); /* (write clear) */
1002 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CEECR);/* CEECR */
1003 ctrl_outl(0, ioaddr + CEECR); /* (write clear) */
1004#else
880 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CNDCR); 1005 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CNDCR);
881 ctrl_outl(0, ioaddr + CNDCR); /* (write clear) */ 1006 ctrl_outl(0, ioaddr + CNDCR); /* (write clear) */
882 1007#endif
883 return &mdp->stats; 1008 return &mdp->stats;
884} 1009}
885 1010
@@ -929,8 +1054,13 @@ static void sh_eth_tsu_init(u32 ioaddr)
929 ctrl_outl(0, ioaddr + TSU_FWSL0); 1054 ctrl_outl(0, ioaddr + TSU_FWSL0);
930 ctrl_outl(0, ioaddr + TSU_FWSL1); 1055 ctrl_outl(0, ioaddr + TSU_FWSL1);
931 ctrl_outl(TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, ioaddr + TSU_FWSLC); 1056 ctrl_outl(TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, ioaddr + TSU_FWSLC);
1057#if defined(CONFIG_CPU_SUBTYPE_SH7763)
1058 ctrl_outl(0, ioaddr + TSU_QTAG0); /* Disable QTAG(0->1) */
1059 ctrl_outl(0, ioaddr + TSU_QTAG1); /* Disable QTAG(1->0) */
1060#else
932 ctrl_outl(0, ioaddr + TSU_QTAGM0); /* Disable QTAG(0->1) */ 1061 ctrl_outl(0, ioaddr + TSU_QTAGM0); /* Disable QTAG(0->1) */
933 ctrl_outl(0, ioaddr + TSU_QTAGM1); /* Disable QTAG(1->0) */ 1062 ctrl_outl(0, ioaddr + TSU_QTAGM1); /* Disable QTAG(1->0) */
1063#endif
934 ctrl_outl(0, ioaddr + TSU_FWSR); /* all interrupt status clear */ 1064 ctrl_outl(0, ioaddr + TSU_FWSR); /* all interrupt status clear */
935 ctrl_outl(0, ioaddr + TSU_FWINMK); /* Disable all interrupt */ 1065 ctrl_outl(0, ioaddr + TSU_FWINMK); /* Disable all interrupt */
936 ctrl_outl(0, ioaddr + TSU_TEN); /* Disable all CAM entry */ 1066 ctrl_outl(0, ioaddr + TSU_TEN); /* Disable all CAM entry */
@@ -1088,7 +1218,7 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
1088 /* First device only init */ 1218 /* First device only init */
1089 if (!devno) { 1219 if (!devno) {
1090 /* reset device */ 1220 /* reset device */
1091 ctrl_outl(ARSTR_ARSTR, ndev->base_addr + ARSTR); 1221 ctrl_outl(ARSTR_ARSTR, ARSTR);
1092 mdelay(1); 1222 mdelay(1);
1093 1223
1094 /* TSU init (Init only)*/ 1224 /* TSU init (Init only)*/
@@ -1110,8 +1240,8 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
1110 ndev->name, CARDNAME, (u32) ndev->base_addr); 1240 ndev->name, CARDNAME, (u32) ndev->base_addr);
1111 1241
1112 for (i = 0; i < 5; i++) 1242 for (i = 0; i < 5; i++)
1113 printk(KERN_INFO "%2.2x:", ndev->dev_addr[i]); 1243 printk(KERN_INFO "%02X:", ndev->dev_addr[i]);
1114 printk(KERN_INFO "%2.2x, IRQ %d.\n", ndev->dev_addr[i], ndev->irq); 1244 printk(KERN_INFO "%02X, IRQ %d.\n", ndev->dev_addr[i], ndev->irq);
1115 1245
1116 platform_set_drvdata(pdev, ndev); 1246 platform_set_drvdata(pdev, ndev);
1117 1247
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index e01e1c347715..45ad1b09ca5a 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -32,118 +32,249 @@
32 32
33#define CARDNAME "sh-eth" 33#define CARDNAME "sh-eth"
34#define TX_TIMEOUT (5*HZ) 34#define TX_TIMEOUT (5*HZ)
35 35#define TX_RING_SIZE 64 /* Tx ring size */
36#define TX_RING_SIZE 128 /* Tx ring size */ 36#define RX_RING_SIZE 64 /* Rx ring size */
37#define RX_RING_SIZE 128 /* Rx ring size */
38#define RX_OFFSET 2 /* skb offset */
39#define ETHERSMALL 60 37#define ETHERSMALL 60
40#define PKT_BUF_SZ 1538 38#define PKT_BUF_SZ 1538
41 39
40#ifdef CONFIG_CPU_SUBTYPE_SH7763
41
42#define SH7763_SKB_ALIGN 32
42/* Chip Base Address */ 43/* Chip Base Address */
43#define SH_TSU_ADDR 0xA7000804 44# define SH_TSU_ADDR 0xFFE01800
45# define ARSTR 0xFFE01800
46
47/* Chip Registers */
48/* E-DMAC */
49# define EDSR 0x000
50# define EDMR 0x400
51# define EDTRR 0x408
52# define EDRRR 0x410
53# define EESR 0x428
54# define EESIPR 0x430
55# define TDLAR 0x010
56# define TDFAR 0x014
57# define TDFXR 0x018
58# define TDFFR 0x01C
59# define RDLAR 0x030
60# define RDFAR 0x034
61# define RDFXR 0x038
62# define RDFFR 0x03C
63# define TRSCER 0x438
64# define RMFCR 0x440
65# define TFTR 0x448
66# define FDR 0x450
67# define RMCR 0x458
68# define RPADIR 0x460
69# define FCFTR 0x468
70
71/* Ether Register */
72# define ECMR 0x500
73# define ECSR 0x510
74# define ECSIPR 0x518
75# define PIR 0x520
76# define PSR 0x528
77# define PIPR 0x52C
78# define RFLR 0x508
79# define APR 0x554
80# define MPR 0x558
81# define PFTCR 0x55C
82# define PFRCR 0x560
83# define TPAUSER 0x564
84# define GECMR 0x5B0
85# define BCULR 0x5B4
86# define MAHR 0x5C0
87# define MALR 0x5C8
88# define TROCR 0x700
89# define CDCR 0x708
90# define LCCR 0x710
91# define CEFCR 0x740
92# define FRECR 0x748
93# define TSFRCR 0x750
94# define TLFRCR 0x758
95# define RFCR 0x760
96# define CERCR 0x768
97# define CEECR 0x770
98# define MAFCR 0x778
99
100/* TSU Absolute Address */
101# define TSU_CTRST 0x004
102# define TSU_FWEN0 0x010
103# define TSU_FWEN1 0x014
104# define TSU_FCM 0x18
105# define TSU_BSYSL0 0x20
106# define TSU_BSYSL1 0x24
107# define TSU_PRISL0 0x28
108# define TSU_PRISL1 0x2C
109# define TSU_FWSL0 0x30
110# define TSU_FWSL1 0x34
111# define TSU_FWSLC 0x38
112# define TSU_QTAG0 0x40
113# define TSU_QTAG1 0x44
114# define TSU_FWSR 0x50
115# define TSU_FWINMK 0x54
116# define TSU_ADQT0 0x48
117# define TSU_ADQT1 0x4C
118# define TSU_VTAG0 0x58
119# define TSU_VTAG1 0x5C
120# define TSU_ADSBSY 0x60
121# define TSU_TEN 0x64
122# define TSU_POST1 0x70
123# define TSU_POST2 0x74
124# define TSU_POST3 0x78
125# define TSU_POST4 0x7C
126# define TSU_ADRH0 0x100
127# define TSU_ADRL0 0x104
128# define TSU_ADRH31 0x1F8
129# define TSU_ADRL31 0x1FC
130
131# define TXNLCR0 0x80
132# define TXALCR0 0x84
133# define RXNLCR0 0x88
134# define RXALCR0 0x8C
135# define FWNLCR0 0x90
136# define FWALCR0 0x94
137# define TXNLCR1 0xA0
138# define TXALCR1 0xA4
139# define RXNLCR1 0xA8
140# define RXALCR1 0xAC
141# define FWNLCR1 0xB0
142# define FWALCR1 0x40
143
144#else /* CONFIG_CPU_SUBTYPE_SH7763 */
145# define RX_OFFSET 2 /* skb offset */
146/* Chip base address */
147# define SH_TSU_ADDR 0xA7000804
148# define ARSTR 0xA7000800
44 149
45/* Chip Registers */ 150/* Chip Registers */
46/* E-DMAC */ 151/* E-DMAC */
47#define EDMR 0x0000 152# define EDMR 0x0000
48#define EDTRR 0x0004 153# define EDTRR 0x0004
49#define EDRRR 0x0008 154# define EDRRR 0x0008
50#define TDLAR 0x000C 155# define TDLAR 0x000C
51#define RDLAR 0x0010 156# define RDLAR 0x0010
52#define EESR 0x0014 157# define EESR 0x0014
53#define EESIPR 0x0018 158# define EESIPR 0x0018
54#define TRSCER 0x001C 159# define TRSCER 0x001C
55#define RMFCR 0x0020 160# define RMFCR 0x0020
56#define TFTR 0x0024 161# define TFTR 0x0024
57#define FDR 0x0028 162# define FDR 0x0028
58#define RMCR 0x002C 163# define RMCR 0x002C
59#define EDOCR 0x0030 164# define EDOCR 0x0030
60#define FCFTR 0x0034 165# define FCFTR 0x0034
61#define RPADIR 0x0038 166# define RPADIR 0x0038
62#define TRIMD 0x003C 167# define TRIMD 0x003C
63#define RBWAR 0x0040 168# define RBWAR 0x0040
64#define RDFAR 0x0044 169# define RDFAR 0x0044
65#define TBRAR 0x004C 170# define TBRAR 0x004C
66#define TDFAR 0x0050 171# define TDFAR 0x0050
172
67/* Ether Register */ 173/* Ether Register */
68#define ECMR 0x0160 174# define ECMR 0x0160
69#define ECSR 0x0164 175# define ECSR 0x0164
70#define ECSIPR 0x0168 176# define ECSIPR 0x0168
71#define PIR 0x016C 177# define PIR 0x016C
72#define MAHR 0x0170 178# define MAHR 0x0170
73#define MALR 0x0174 179# define MALR 0x0174
74#define RFLR 0x0178 180# define RFLR 0x0178
75#define PSR 0x017C 181# define PSR 0x017C
76#define TROCR 0x0180 182# define TROCR 0x0180
77#define CDCR 0x0184 183# define CDCR 0x0184
78#define LCCR 0x0188 184# define LCCR 0x0188
79#define CNDCR 0x018C 185# define CNDCR 0x018C
80#define CEFCR 0x0194 186# define CEFCR 0x0194
81#define FRECR 0x0198 187# define FRECR 0x0198
82#define TSFRCR 0x019C 188# define TSFRCR 0x019C
83#define TLFRCR 0x01A0 189# define TLFRCR 0x01A0
84#define RFCR 0x01A4 190# define RFCR 0x01A4
85#define MAFCR 0x01A8 191# define MAFCR 0x01A8
86#define IPGR 0x01B4 192# define IPGR 0x01B4
87#if defined(CONFIG_CPU_SUBTYPE_SH7710) 193# if defined(CONFIG_CPU_SUBTYPE_SH7710)
88#define APR 0x01B8 194# define APR 0x01B8
89#define MPR 0x01BC 195# define MPR 0x01BC
90#define TPAUSER 0x1C4 196# define TPAUSER 0x1C4
91#define BCFR 0x1CC 197# define BCFR 0x1CC
92#endif /* CONFIG_CPU_SH7710 */ 198# endif /* CONFIG_CPU_SH7710 */
93
94#define ARSTR 0x0800
95 199
96/* TSU */ 200/* TSU */
97#define TSU_CTRST 0x004 201# define TSU_CTRST 0x004
98#define TSU_FWEN0 0x010 202# define TSU_FWEN0 0x010
99#define TSU_FWEN1 0x014 203# define TSU_FWEN1 0x014
100#define TSU_FCM 0x018 204# define TSU_FCM 0x018
101#define TSU_BSYSL0 0x020 205# define TSU_BSYSL0 0x020
102#define TSU_BSYSL1 0x024 206# define TSU_BSYSL1 0x024
103#define TSU_PRISL0 0x028 207# define TSU_PRISL0 0x028
104#define TSU_PRISL1 0x02C 208# define TSU_PRISL1 0x02C
105#define TSU_FWSL0 0x030 209# define TSU_FWSL0 0x030
106#define TSU_FWSL1 0x034 210# define TSU_FWSL1 0x034
107#define TSU_FWSLC 0x038 211# define TSU_FWSLC 0x038
108#define TSU_QTAGM0 0x040 212# define TSU_QTAGM0 0x040
109#define TSU_QTAGM1 0x044 213# define TSU_QTAGM1 0x044
110#define TSU_ADQT0 0x048 214# define TSU_ADQT0 0x048
111#define TSU_ADQT1 0x04C 215# define TSU_ADQT1 0x04C
112#define TSU_FWSR 0x050 216# define TSU_FWSR 0x050
113#define TSU_FWINMK 0x054 217# define TSU_FWINMK 0x054
114#define TSU_ADSBSY 0x060 218# define TSU_ADSBSY 0x060
115#define TSU_TEN 0x064 219# define TSU_TEN 0x064
116#define TSU_POST1 0x070 220# define TSU_POST1 0x070
117#define TSU_POST2 0x074 221# define TSU_POST2 0x074
118#define TSU_POST3 0x078 222# define TSU_POST3 0x078
119#define TSU_POST4 0x07C 223# define TSU_POST4 0x07C
120#define TXNLCR0 0x080 224# define TXNLCR0 0x080
121#define TXALCR0 0x084 225# define TXALCR0 0x084
122#define RXNLCR0 0x088 226# define RXNLCR0 0x088
123#define RXALCR0 0x08C 227# define RXALCR0 0x08C
124#define FWNLCR0 0x090 228# define FWNLCR0 0x090
125#define FWALCR0 0x094 229# define FWALCR0 0x094
126#define TXNLCR1 0x0A0 230# define TXNLCR1 0x0A0
127#define TXALCR1 0x0A4 231# define TXALCR1 0x0A4
128#define RXNLCR1 0x0A8 232# define RXNLCR1 0x0A8
129#define RXALCR1 0x0AC 233# define RXALCR1 0x0AC
130#define FWNLCR1 0x0B0 234# define FWNLCR1 0x0B0
131#define FWALCR1 0x0B4 235# define FWALCR1 0x0B4
132 236
133#define TSU_ADRH0 0x0100 237#define TSU_ADRH0 0x0100
134#define TSU_ADRL0 0x0104 238#define TSU_ADRL0 0x0104
135#define TSU_ADRL31 0x01FC 239#define TSU_ADRL31 0x01FC
136 240
137/* Register's bits */ 241#endif /* CONFIG_CPU_SUBTYPE_SH7763 */
242
243/*
244 * Register's bits
245 */
246#ifdef CONFIG_CPU_SUBTYPE_SH7763
247/* EDSR */
248enum EDSR_BIT {
249 EDSR_ENT = 0x01, EDSR_ENR = 0x02,
250};
251#define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
252
253/* GECMR */
254enum GECMR_BIT {
255 GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
256};
257#endif
138 258
139/* EDMR */ 259/* EDMR */
140enum DMAC_M_BIT { 260enum DMAC_M_BIT {
141 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, EDMR_SRST = 0x01, 261 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
262#ifdef CONFIG_CPU_SUBTYPE_SH7763
263 EDMR_SRST = 0x03,
264 EMDR_DESC_R = 0x30, /* Descriptor reserve size */
265 EDMR_EL = 0x40, /* Litte endian */
266#else /* CONFIG_CPU_SUBTYPE_SH7763 */
267 EDMR_SRST = 0x01,
268#endif
142}; 269};
143 270
144/* EDTRR */ 271/* EDTRR */
145enum DMAC_T_BIT { 272enum DMAC_T_BIT {
273#ifdef CONFIG_CPU_SUBTYPE_SH7763
274 EDTRR_TRNS = 0x03,
275#else
146 EDTRR_TRNS = 0x01, 276 EDTRR_TRNS = 0x01,
277#endif
147}; 278};
148 279
149/* EDRRR*/ 280/* EDRRR*/
@@ -173,21 +304,47 @@ enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
173 304
174/* EESR */ 305/* EESR */
175enum EESR_BIT { 306enum EESR_BIT {
176 EESR_TWB = 0x40000000, EESR_TABT = 0x04000000, 307#ifndef CONFIG_CPU_SUBTYPE_SH7763
308 EESR_TWB = 0x40000000,
309#else
310 EESR_TWB = 0xC0000000,
311 EESR_TC1 = 0x20000000,
312 EESR_TUC = 0x10000000,
313 EESR_ROC = 0x80000000,
314#endif
315 EESR_TABT = 0x04000000,
177 EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000, 316 EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
178 EESR_ADE = 0x00800000, EESR_ECI = 0x00400000, 317#ifndef CONFIG_CPU_SUBTYPE_SH7763
179 EESR_FTC = 0x00200000, EESR_TDE = 0x00100000, 318 EESR_ADE = 0x00800000,
180 EESR_TFE = 0x00080000, EESR_FRC = 0x00040000, 319#endif
181 EESR_RDE = 0x00020000, EESR_RFE = 0x00010000, 320 EESR_ECI = 0x00400000,
182 EESR_TINT4 = 0x00000800, EESR_TINT3 = 0x00000400, 321 EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
183 EESR_TINT2 = 0x00000200, EESR_TINT1 = 0x00000100, 322 EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
184 EESR_RINT8 = 0x00000080, EESR_RINT5 = 0x00000010, 323 EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
185 EESR_RINT4 = 0x00000008, EESR_RINT3 = 0x00000004, 324#ifndef CONFIG_CPU_SUBTYPE_SH7763
186 EESR_RINT2 = 0x00000002, EESR_RINT1 = 0x00000001, 325 EESR_CND = 0x00000800,
187}; 326#endif
188 327 EESR_DLC = 0x00000400,
189#define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \ 328 EESR_CD = 0x00000200, EESR_RTO = 0x00000100,
329 EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
330 EESR_CELF = 0x00000020, EESR_RRF = 0x00000010,
331 EESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
332 EESR_PRE = 0x00000002, EESR_CERF = 0x00000001,
333};
334
335
336#ifdef CONFIG_CPU_SUBTYPE_SH7763
337# define TX_CHECK (EESR_TC1 | EESR_FTC)
338# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
339 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
340# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)
341
342#else
343# define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
344# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
190 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI) 345 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
346# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
347#endif
191 348
192/* EESIPR */ 349/* EESIPR */
193enum DMAC_IM_BIT { 350enum DMAC_IM_BIT {
@@ -207,8 +364,8 @@ enum DMAC_IM_BIT {
207 364
208/* Receive descriptor bit */ 365/* Receive descriptor bit */
209enum RD_STS_BIT { 366enum RD_STS_BIT {
210 RD_RACT = 0x80000000, RC_RDEL = 0x40000000, 367 RD_RACT = 0x80000000, RD_RDEL = 0x40000000,
211 RC_RFP1 = 0x20000000, RC_RFP0 = 0x10000000, 368 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
212 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200, 369 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
213 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080, 370 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
214 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020, 371 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
@@ -216,9 +373,9 @@ enum RD_STS_BIT {
216 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002, 373 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
217 RD_RFS1 = 0x00000001, 374 RD_RFS1 = 0x00000001,
218}; 375};
219#define RDF1ST RC_RFP1 376#define RDF1ST RD_RFP1
220#define RDFEND RC_RFP0 377#define RDFEND RD_RFP0
221#define RD_RFP (RC_RFP1|RC_RFP0) 378#define RD_RFP (RD_RFP1|RD_RFP0)
222 379
223/* FCFTR */ 380/* FCFTR */
224enum FCFTR_BIT { 381enum FCFTR_BIT {
@@ -231,7 +388,8 @@ enum FCFTR_BIT {
231 388
232/* Transfer descriptor bit */ 389/* Transfer descriptor bit */
233enum TD_STS_BIT { 390enum TD_STS_BIT {
234 TD_TACT = 0x80000000, TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000, 391 TD_TACT = 0x80000000,
392 TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
235 TD_TFP0 = 0x10000000, 393 TD_TFP0 = 0x10000000,
236}; 394};
237#define TDF1ST TD_TFP1 395#define TDF1ST TD_TFP1
@@ -242,6 +400,10 @@ enum TD_STS_BIT {
242enum RECV_RST_BIT { RMCR_RST = 0x01, }; 400enum RECV_RST_BIT { RMCR_RST = 0x01, };
243/* ECMR */ 401/* ECMR */
244enum FELIC_MODE_BIT { 402enum FELIC_MODE_BIT {
403#ifdef CONFIG_CPU_SUBTYPE_SH7763
404 ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
405 ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
406#endif
245 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000, 407 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
246 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000, 408 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
247 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020, 409 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
@@ -249,18 +411,45 @@ enum FELIC_MODE_BIT {
249 ECMR_PRM = 0x00000001, 411 ECMR_PRM = 0x00000001,
250}; 412};
251 413
414#ifdef CONFIG_CPU_SUBTYPE_SH7763
415#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF |\
416 ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
417#else
418#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR ECMR_RXF | ECMR_TXF | ECMR_MCT)
419#endif
420
252/* ECSR */ 421/* ECSR */
253enum ECSR_STATUS_BIT { 422enum ECSR_STATUS_BIT {
254 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10, ECSR_LCHNG = 0x04, 423#ifndef CONFIG_CPU_SUBTYPE_SH7763
424 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
425#endif
426 ECSR_LCHNG = 0x04,
255 ECSR_MPD = 0x02, ECSR_ICD = 0x01, 427 ECSR_MPD = 0x02, ECSR_ICD = 0x01,
256}; 428};
257 429
430#ifdef CONFIG_CPU_SUBTYPE_SH7763
431# define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
432#else
433# define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
434 ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
435#endif
436
258/* ECSIPR */ 437/* ECSIPR */
259enum ECSIPR_STATUS_MASK_BIT { 438enum ECSIPR_STATUS_MASK_BIT {
260 ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10, ECSIPR_LCHNGIP = 0x04, 439#ifndef CONFIG_CPU_SUBTYPE_SH7763
440 ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
441#endif
442 ECSIPR_LCHNGIP = 0x04,
261 ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01, 443 ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
262}; 444};
263 445
446#ifdef CONFIG_CPU_SUBTYPE_SH7763
447# define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
448#else
449# define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
450 ECSIPR_ICDIP | ECSIPR_MPDIP)
451#endif
452
264/* APR */ 453/* APR */
265enum APR_BIT { 454enum APR_BIT {
266 APR_AP = 0x00000001, 455 APR_AP = 0x00000001,
@@ -285,6 +474,15 @@ enum RPADIR_BIT {
285 RPADIR_PADR = 0x0003f, 474 RPADIR_PADR = 0x0003f,
286}; 475};
287 476
477#if defined(CONFIG_CPU_SUBTYPE_SH7763)
478# define RPADIR_INIT (0x00)
479#else
480# define RPADIR_INIT (RPADIR_PADS1)
481#endif
482
483/* RFLR */
484#define RFLR_VALUE 0x1000
485
288/* FDR */ 486/* FDR */
289enum FIFO_SIZE_BIT { 487enum FIFO_SIZE_BIT {
290 FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007, 488 FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
@@ -316,7 +514,7 @@ enum PHY_ANA_BIT {
316 PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000, 514 PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000,
317 PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100, 515 PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100,
318 PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020, 516 PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020,
319 PHY_A_SEL = 0x001f, 517 PHY_A_SEL = 0x001e,
320}; 518};
321/* PHY_ANL */ 519/* PHY_ANL */
322enum PHY_ANL_BIT { 520enum PHY_ANL_BIT {
@@ -449,6 +647,10 @@ struct sh_eth_private {
449 struct net_device_stats tsu_stats; /* TSU forward status */ 647 struct net_device_stats tsu_stats; /* TSU forward status */
450}; 648};
451 649
650#ifdef CONFIG_CPU_SUBTYPE_SH7763
651/* SH7763 has endian control register */
652#define swaps(x, y)
653#else
452static void swaps(char *src, int len) 654static void swaps(char *src, int len)
453{ 655{
454#ifdef __LITTLE_ENDIAN__ 656#ifdef __LITTLE_ENDIAN__
@@ -460,5 +662,5 @@ static void swaps(char *src, int len)
460 *p = swab32(*p); 662 *p = swab32(*p);
461#endif 663#endif
462} 664}
463 665#endif /* CONFIG_CPU_SUBTYPE_SH7763 */
464#endif 666#endif
diff --git a/drivers/net/usb/dm9601.c b/drivers/net/usb/dm9601.c
index f7319d326912..78df2be8a728 100644
--- a/drivers/net/usb/dm9601.c
+++ b/drivers/net/usb/dm9601.c
@@ -55,12 +55,28 @@
55 55
56static int dm_read(struct usbnet *dev, u8 reg, u16 length, void *data) 56static int dm_read(struct usbnet *dev, u8 reg, u16 length, void *data)
57{ 57{
58 void *buf;
59 int err = -ENOMEM;
60
58 devdbg(dev, "dm_read() reg=0x%02x length=%d", reg, length); 61 devdbg(dev, "dm_read() reg=0x%02x length=%d", reg, length);
59 return usb_control_msg(dev->udev, 62
60 usb_rcvctrlpipe(dev->udev, 0), 63 buf = kmalloc(length, GFP_KERNEL);
61 DM_READ_REGS, 64 if (!buf)
62 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 65 goto out;
63 0, reg, data, length, USB_CTRL_SET_TIMEOUT); 66
67 err = usb_control_msg(dev->udev,
68 usb_rcvctrlpipe(dev->udev, 0),
69 DM_READ_REGS,
70 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
71 0, reg, buf, length, USB_CTRL_SET_TIMEOUT);
72 if (err == length)
73 memcpy(data, buf, length);
74 else if (err >= 0)
75 err = -EINVAL;
76 kfree(buf);
77
78 out:
79 return err;
64} 80}
65 81
66static int dm_read_reg(struct usbnet *dev, u8 reg, u8 *value) 82static int dm_read_reg(struct usbnet *dev, u8 reg, u8 *value)
@@ -70,12 +86,28 @@ static int dm_read_reg(struct usbnet *dev, u8 reg, u8 *value)
70 86
71static int dm_write(struct usbnet *dev, u8 reg, u16 length, void *data) 87static int dm_write(struct usbnet *dev, u8 reg, u16 length, void *data)
72{ 88{
89 void *buf = NULL;
90 int err = -ENOMEM;
91
73 devdbg(dev, "dm_write() reg=0x%02x, length=%d", reg, length); 92 devdbg(dev, "dm_write() reg=0x%02x, length=%d", reg, length);
74 return usb_control_msg(dev->udev, 93
75 usb_sndctrlpipe(dev->udev, 0), 94 if (data) {
76 DM_WRITE_REGS, 95 buf = kmalloc(length, GFP_KERNEL);
77 USB_DIR_OUT | USB_TYPE_VENDOR |USB_RECIP_DEVICE, 96 if (!buf)
78 0, reg, data, length, USB_CTRL_SET_TIMEOUT); 97 goto out;
98 memcpy(buf, data, length);
99 }
100
101 err = usb_control_msg(dev->udev,
102 usb_sndctrlpipe(dev->udev, 0),
103 DM_WRITE_REGS,
104 USB_DIR_OUT | USB_TYPE_VENDOR |USB_RECIP_DEVICE,
105 0, reg, buf, length, USB_CTRL_SET_TIMEOUT);
106 kfree(buf);
107 if (err >= 0 && err < length)
108 err = -EINVAL;
109 out:
110 return err;
79} 111}
80 112
81static int dm_write_reg(struct usbnet *dev, u8 reg, u8 value) 113static int dm_write_reg(struct usbnet *dev, u8 reg, u8 value)
diff --git a/drivers/net/wd.c b/drivers/net/wd.c
index fa14255282af..6f9aa1643743 100644
--- a/drivers/net/wd.c
+++ b/drivers/net/wd.c
@@ -337,7 +337,7 @@ static int __init wd_probe1(struct net_device *dev, int ioaddr)
337#ifdef CONFIG_NET_POLL_CONTROLLER 337#ifdef CONFIG_NET_POLL_CONTROLLER
338 dev->poll_controller = ei_poll; 338 dev->poll_controller = ei_poll;
339#endif 339#endif
340 NS8390_init(dev, 0); 340 NS8390p_init(dev, 0);
341 341
342#if 1 342#if 1
343 /* Enable interrupt generation on softconfig cards -- M.U */ 343 /* Enable interrupt generation on softconfig cards -- M.U */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 15:32:24 -0500