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authorLadislav Michl <ladis@linux-mips.org>2007-02-27 20:18:35 -0500
committerJeff Garzik <jeff@garzik.org>2007-04-28 11:00:56 -0400
commit78ee5b3cc88297bb98843c24b231e99f3f2886a0 (patch)
tree6fb146a1808e798841dd9ceb09ffd98fdeacfac9 /drivers/net
parent18604c54854549ee0ad65e27ca9cb91c96af784c (diff)
Add support for Seeq 8003 on Challenge S Mezz board.
Thanks to Jö Fahlke for donating hardware. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Forward porting of Ladis' 2.4 patch. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/sgiseeq.c28
1 files changed, 25 insertions, 3 deletions
diff --git a/drivers/net/sgiseeq.c b/drivers/net/sgiseeq.c
index d8c9c5d66d4f..1fc77300b055 100644
--- a/drivers/net/sgiseeq.c
+++ b/drivers/net/sgiseeq.c
@@ -624,7 +624,7 @@ static inline void setup_rx_ring(struct sgiseeq_rx_desc *buf, int nbufs)
624 624
625#define ALIGNED(x) ((((unsigned long)(x)) + 0xf) & ~(0xf)) 625#define ALIGNED(x) ((((unsigned long)(x)) + 0xf) & ~(0xf))
626 626
627static int sgiseeq_init(struct hpc3_regs* hpcregs, int irq) 627static int sgiseeq_init(struct hpc3_regs* hpcregs, int irq, int has_eeprom)
628{ 628{
629 struct sgiseeq_init_block *sr; 629 struct sgiseeq_init_block *sr;
630 struct sgiseeq_private *sp; 630 struct sgiseeq_private *sp;
@@ -650,7 +650,9 @@ static int sgiseeq_init(struct hpc3_regs* hpcregs, int irq)
650 650
651#define EADDR_NVOFS 250 651#define EADDR_NVOFS 250
652 for (i = 0; i < 3; i++) { 652 for (i = 0; i < 3; i++) {
653 unsigned short tmp = ip22_nvram_read(EADDR_NVOFS / 2 + i); 653 unsigned short tmp = has_eeprom ?
654 ip22_eeprom_read(&hpcregs->eeprom, EADDR_NVOFS / 2+i) :
655 ip22_nvram_read(EADDR_NVOFS / 2+i);
654 656
655 dev->dev_addr[2 * i] = tmp >> 8; 657 dev->dev_addr[2 * i] = tmp >> 8;
656 dev->dev_addr[2 * i + 1] = tmp & 0xff; 658 dev->dev_addr[2 * i + 1] = tmp & 0xff;
@@ -683,6 +685,11 @@ static int sgiseeq_init(struct hpc3_regs* hpcregs, int irq)
683 sp->hregs->dconfig = HPC3_EDCFG_FIRQ | HPC3_EDCFG_FEOP | 685 sp->hregs->dconfig = HPC3_EDCFG_FIRQ | HPC3_EDCFG_FEOP |
684 HPC3_EDCFG_FRXDC | HPC3_EDCFG_PTO | 0x026; 686 HPC3_EDCFG_FRXDC | HPC3_EDCFG_PTO | 0x026;
685 687
688 /* Setup PIO and DMA transfer timing */
689 sp->hregs->pconfig = 0x161;
690 sp->hregs->dconfig = HPC3_EDCFG_FIRQ | HPC3_EDCFG_FEOP |
691 HPC3_EDCFG_FRXDC | HPC3_EDCFG_PTO | 0x026;
692
686 /* Reset the chip. */ 693 /* Reset the chip. */
687 hpc3_eth_reset(sp->hregs); 694 hpc3_eth_reset(sp->hregs);
688 695
@@ -729,8 +736,23 @@ err_out:
729 736
730static int __init sgiseeq_probe(void) 737static int __init sgiseeq_probe(void)
731{ 738{
739 unsigned int tmp, ret1, ret2 = 0;
740
732 /* On board adapter on 1st HPC is always present */ 741 /* On board adapter on 1st HPC is always present */
733 return sgiseeq_init(hpc3c0, SGI_ENET_IRQ); 742 ret1 = sgiseeq_init(hpc3c0, SGI_ENET_IRQ, 0);
743 /* Let's see if second HPC is there */
744 if (!(ip22_is_fullhouse()) &&
745 get_dbe(tmp, (unsigned int *)&hpc3c1->pbdma[1]) == 0) {
746 sgimc->giopar |= SGIMC_GIOPAR_MASTEREXP1 |
747 SGIMC_GIOPAR_EXP164 |
748 SGIMC_GIOPAR_HPC264;
749 hpc3c1->pbus_piocfg[0][0] = 0x3ffff;
750 /* interrupt/config register on Challenge S Mezz board */
751 hpc3c1->pbus_extregs[0][0] = 0x30;
752 ret2 = sgiseeq_init(hpc3c1, SGI_GIO_0_IRQ, 1);
753 }
754
755 return (ret1 & ret2) ? ret1 : 0;
734} 756}
735 757
736static void __exit sgiseeq_exit(void) 758static void __exit sgiseeq_exit(void)