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authorBruno Randolf <br1@einfach.org>2010-06-16 06:12:34 -0400
committerJohn W. Linville <linville@tuxdriver.com>2010-06-16 14:59:07 -0400
commit8786123b51984c518436911048668f9673f30cdf (patch)
treeab547b4ac6c214537e31646084e49b8b7ad86243 /drivers/net
parent1884a3678c97c953dcfc2ee17bd43e354514d657 (diff)
ath5k: review RX descriptor functions
Reviewed RX descriptor functions against the HAL sources. Some minor changes: - check size before making changes to the descriptor - whitespace - add comments about 5210 timestamps. this needs to be adressed later! - FIFO overrun error only available on 5210 - rs_phyerr should not be OR'ed - clear the whole ath5k_rx_status structure before using, instead of zeroing specific fields. Signed-off-by: Bruno Randolf <br1@einfach.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/wireless/ath/ath5k/desc.c34
1 files changed, 20 insertions, 14 deletions
diff --git a/drivers/net/wireless/ath/ath5k/desc.c b/drivers/net/wireless/ath/ath5k/desc.c
index 019525d6c0eb..c0037b61e095 100644
--- a/drivers/net/wireless/ath/ath5k/desc.c
+++ b/drivers/net/wireless/ath/ath5k/desc.c
@@ -499,10 +499,11 @@ int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
499 */ 499 */
500 memset(&desc->ud.ds_rx, 0, sizeof(struct ath5k_hw_all_rx_desc)); 500 memset(&desc->ud.ds_rx, 0, sizeof(struct ath5k_hw_all_rx_desc));
501 501
502 if (unlikely(size & ~AR5K_DESC_RX_CTL1_BUF_LEN))
503 return -EINVAL;
504
502 /* Setup descriptor */ 505 /* Setup descriptor */
503 rx_ctl->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN; 506 rx_ctl->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN;
504 if (unlikely(rx_ctl->rx_control_1 != size))
505 return -EINVAL;
506 507
507 if (flags & AR5K_RXDESC_INTREQ) 508 if (flags & AR5K_RXDESC_INTREQ)
508 rx_ctl->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ; 509 rx_ctl->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ;
@@ -522,9 +523,11 @@ static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
522 523
523 /* No frame received / not ready */ 524 /* No frame received / not ready */
524 if (unlikely(!(rx_status->rx_status_1 & 525 if (unlikely(!(rx_status->rx_status_1 &
525 AR5K_5210_RX_DESC_STATUS1_DONE))) 526 AR5K_5210_RX_DESC_STATUS1_DONE)))
526 return -EINPROGRESS; 527 return -EINPROGRESS;
527 528
529 memset(rs, 0, sizeof(struct ath5k_rx_status));
530
528 /* 531 /*
529 * Frame receive status 532 * Frame receive status
530 */ 533 */
@@ -536,7 +539,11 @@ static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
536 AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE); 539 AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE);
537 rs->rs_more = !!(rx_status->rx_status_0 & 540 rs->rs_more = !!(rx_status->rx_status_0 &
538 AR5K_5210_RX_DESC_STATUS0_MORE); 541 AR5K_5210_RX_DESC_STATUS0_MORE);
539 /* TODO: this timestamp is 13 bit, later on we assume 15 bit */ 542 /* TODO: this timestamp is 13 bit, later on we assume 15 bit!
543 * also the HAL code for 5210 says the timestamp is bits [10..22] of the
544 * TSF, and extends the timestamp here to 15 bit.
545 * we need to check on 5210...
546 */
540 rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1, 547 rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
541 AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); 548 AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
542 549
@@ -548,9 +555,6 @@ static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
548 AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5210) 555 AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5210)
549 ? 2 : 1; 556 ? 2 : 1;
550 557
551 rs->rs_status = 0;
552 rs->rs_phyerr = 0;
553
554 /* 558 /*
555 * Key table status 559 * Key table status
556 */ 560 */
@@ -564,19 +568,21 @@ static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
564 * Receive/descriptor errors 568 * Receive/descriptor errors
565 */ 569 */
566 if (!(rx_status->rx_status_1 & 570 if (!(rx_status->rx_status_1 &
567 AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) { 571 AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) {
568 if (rx_status->rx_status_1 & 572 if (rx_status->rx_status_1 &
569 AR5K_5210_RX_DESC_STATUS1_CRC_ERROR) 573 AR5K_5210_RX_DESC_STATUS1_CRC_ERROR)
570 rs->rs_status |= AR5K_RXERR_CRC; 574 rs->rs_status |= AR5K_RXERR_CRC;
571 575
572 if (rx_status->rx_status_1 & 576 /* only on 5210 */
573 AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN_5210) 577 if ((ah->ah_version == AR5K_AR5210) &&
578 (rx_status->rx_status_1 &
579 AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN_5210))
574 rs->rs_status |= AR5K_RXERR_FIFO; 580 rs->rs_status |= AR5K_RXERR_FIFO;
575 581
576 if (rx_status->rx_status_1 & 582 if (rx_status->rx_status_1 &
577 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR) { 583 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR) {
578 rs->rs_status |= AR5K_RXERR_PHY; 584 rs->rs_status |= AR5K_RXERR_PHY;
579 rs->rs_phyerr |= AR5K_REG_MS(rx_status->rx_status_1, 585 rs->rs_phyerr = AR5K_REG_MS(rx_status->rx_status_1,
580 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR); 586 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR);
581 } 587 }
582 588
@@ -604,6 +610,8 @@ static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
604 AR5K_5212_RX_DESC_STATUS1_DONE))) 610 AR5K_5212_RX_DESC_STATUS1_DONE)))
605 return -EINPROGRESS; 611 return -EINPROGRESS;
606 612
613 memset(rs, 0, sizeof(struct ath5k_rx_status));
614
607 /* 615 /*
608 * Frame receive status 616 * Frame receive status
609 */ 617 */
@@ -619,8 +627,6 @@ static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
619 AR5K_5212_RX_DESC_STATUS0_MORE); 627 AR5K_5212_RX_DESC_STATUS0_MORE);
620 rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1, 628 rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
621 AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); 629 AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
622 rs->rs_status = 0;
623 rs->rs_phyerr = 0;
624 630
625 /* 631 /*
626 * Key table status 632 * Key table status
@@ -643,7 +649,7 @@ static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
643 if (rx_status->rx_status_1 & 649 if (rx_status->rx_status_1 &
644 AR5K_5212_RX_DESC_STATUS1_PHY_ERROR) { 650 AR5K_5212_RX_DESC_STATUS1_PHY_ERROR) {
645 rs->rs_status |= AR5K_RXERR_PHY; 651 rs->rs_status |= AR5K_RXERR_PHY;
646 rs->rs_phyerr |= AR5K_REG_MS(rx_status->rx_status_1, 652 rs->rs_phyerr = AR5K_REG_MS(rx_status->rx_status_1,
647 AR5K_5212_RX_DESC_STATUS1_PHY_ERROR_CODE); 653 AR5K_5212_RX_DESC_STATUS1_PHY_ERROR_CODE);
648 ath5k_ani_phy_error_report(ah, rs->rs_phyerr); 654 ath5k_ani_phy_error_report(ah, rs->rs_phyerr);
649 } 655 }