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authorSteve Glendinning <steve.glendinning@smsc.com>2008-12-11 23:54:30 -0500
committerDavid S. Miller <davem@davemloft.net>2008-12-11 23:54:30 -0500
commit2cb377283f3469d66f0ea7358015abfe8366e5d0 (patch)
tree1541f2f50d710b49cd3708c5246b2ac05d91915a /drivers/net
parentea943d41a8770857d50029fdc8fd111635c21a1f (diff)
smsc9420: SMSC LAN9420 10/100 PCI ethernet adapter
This patch adds a driver for the LAN9240 PCI ethernet adapter. Changes since initial submission: - debug msg_level has been changed to use standard definitions - convert to use net_device_ops Signed-off-by: Steve Glendinning <steve.glendinning@smsc.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/Kconfig16
-rw-r--r--drivers/net/Makefile1
-rw-r--r--drivers/net/smsc9420.c1608
-rw-r--r--drivers/net/smsc9420.h275
4 files changed, 1900 insertions, 0 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index e93f5d3f2277..4490c0882779 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1638,6 +1638,22 @@ config EPIC100
1638 More specific information and updates are available from 1638 More specific information and updates are available from
1639 <http://www.scyld.com/network/epic100.html>. 1639 <http://www.scyld.com/network/epic100.html>.
1640 1640
1641config SMSC9420
1642 tristate "SMSC LAN9420 PCI ethernet adapter support"
1643 depends on NET_PCI && PCI
1644 select CRC32
1645 select PHYLIB
1646 select SMSC_PHY
1647 help
1648 This is a driver for SMSC's LAN9420 PCI ethernet adapter.
1649 Say Y if you want it compiled into the kernel,
1650 and read the Ethernet-HOWTO, available from
1651 <http://www.linuxdoc.org/docs.html#howto>.
1652
1653 This driver is also available as a module. The module will be
1654 called smsc9420. If you want to compile it as a module, say M
1655 here and read <file:Documentation/kbuild/modules.txt>
1656
1641config SUNDANCE 1657config SUNDANCE
1642 tristate "Sundance Alta support" 1658 tristate "Sundance Alta support"
1643 depends on NET_PCI && PCI 1659 depends on NET_PCI && PCI
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 35fbe12473d3..e5c34b464211 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_PCNET32) += pcnet32.o
56obj-$(CONFIG_E100) += e100.o 56obj-$(CONFIG_E100) += e100.o
57obj-$(CONFIG_TLAN) += tlan.o 57obj-$(CONFIG_TLAN) += tlan.o
58obj-$(CONFIG_EPIC100) += epic100.o 58obj-$(CONFIG_EPIC100) += epic100.o
59obj-$(CONFIG_SMSC9420) += smsc9420.o
59obj-$(CONFIG_SIS190) += sis190.o 60obj-$(CONFIG_SIS190) += sis190.o
60obj-$(CONFIG_SIS900) += sis900.o 61obj-$(CONFIG_SIS900) += sis900.o
61obj-$(CONFIG_R6040) += r6040.o 62obj-$(CONFIG_R6040) += r6040.o
diff --git a/drivers/net/smsc9420.c b/drivers/net/smsc9420.c
new file mode 100644
index 000000000000..b04bfb2f6106
--- /dev/null
+++ b/drivers/net/smsc9420.c
@@ -0,0 +1,1608 @@
1 /***************************************************************************
2 *
3 * Copyright (C) 2007,2008 SMSC
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 *
19 ***************************************************************************
20 */
21
22#include <linux/kernel.h>
23#include <linux/netdevice.h>
24#include <linux/phy.h>
25#include <linux/pci.h>
26#include <linux/if_vlan.h>
27#include <linux/dma-mapping.h>
28#include <linux/crc32.h>
29#include <asm/unaligned.h>
30#include "smsc9420.h"
31
32#define DRV_NAME "smsc9420"
33#define PFX DRV_NAME ": "
34#define DRV_MDIONAME "smsc9420-mdio"
35#define DRV_DESCRIPTION "SMSC LAN9420 driver"
36#define DRV_VERSION "1.01"
37
38MODULE_LICENSE("GPL");
39MODULE_VERSION(DRV_VERSION);
40
41struct smsc9420_dma_desc {
42 u32 status;
43 u32 length;
44 u32 buffer1;
45 u32 buffer2;
46};
47
48struct smsc9420_ring_info {
49 struct sk_buff *skb;
50 dma_addr_t mapping;
51};
52
53struct smsc9420_pdata {
54 void __iomem *base_addr;
55 struct pci_dev *pdev;
56 struct net_device *dev;
57
58 struct smsc9420_dma_desc *rx_ring;
59 struct smsc9420_dma_desc *tx_ring;
60 struct smsc9420_ring_info *tx_buffers;
61 struct smsc9420_ring_info *rx_buffers;
62 dma_addr_t rx_dma_addr;
63 dma_addr_t tx_dma_addr;
64 int tx_ring_head, tx_ring_tail;
65 int rx_ring_head, rx_ring_tail;
66
67 spinlock_t int_lock;
68 spinlock_t phy_lock;
69
70 struct napi_struct napi;
71
72 bool software_irq_signal;
73 bool rx_csum;
74 u32 msg_enable;
75
76 struct phy_device *phy_dev;
77 struct mii_bus *mii_bus;
78 int phy_irq[PHY_MAX_ADDR];
79 int last_duplex;
80 int last_carrier;
81};
82
83static const struct pci_device_id smsc9420_id_table[] = {
84 { PCI_VENDOR_ID_9420, PCI_DEVICE_ID_9420, PCI_ANY_ID, PCI_ANY_ID, },
85 { 0, }
86};
87
88MODULE_DEVICE_TABLE(pci, smsc9420_id_table);
89
90#define SMSC_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
91
92static uint smsc_debug;
93static uint debug = -1;
94module_param(debug, uint, 0);
95MODULE_PARM_DESC(debug, "debug level");
96
97#define smsc_dbg(TYPE, f, a...) \
98do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
99 printk(KERN_DEBUG PFX f "\n", ## a); \
100} while (0)
101
102#define smsc_info(TYPE, f, a...) \
103do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
104 printk(KERN_INFO PFX f "\n", ## a); \
105} while (0)
106
107#define smsc_warn(TYPE, f, a...) \
108do { if ((pd)->msg_enable & NETIF_MSG_##TYPE) \
109 printk(KERN_WARNING PFX f "\n", ## a); \
110} while (0)
111
112static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset)
113{
114 return ioread32(pd->base_addr + offset);
115}
116
117static inline void
118smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value)
119{
120 iowrite32(value, pd->base_addr + offset);
121}
122
123static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd)
124{
125 /* to ensure PCI write completion, we must perform a PCI read */
126 smsc9420_reg_read(pd, ID_REV);
127}
128
129static int smsc9420_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
130{
131 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
132 unsigned long flags;
133 u32 addr;
134 int i, reg = -EIO;
135
136 spin_lock_irqsave(&pd->phy_lock, flags);
137
138 /* confirm MII not busy */
139 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
140 smsc_warn(DRV, "MII is busy???");
141 goto out;
142 }
143
144 /* set the address, index & direction (read from PHY) */
145 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
146 MII_ACCESS_MII_READ_;
147 smsc9420_reg_write(pd, MII_ACCESS, addr);
148
149 /* wait for read to complete with 50us timeout */
150 for (i = 0; i < 5; i++) {
151 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
152 MII_ACCESS_MII_BUSY_)) {
153 reg = (u16)smsc9420_reg_read(pd, MII_DATA);
154 goto out;
155 }
156 udelay(10);
157 }
158
159 smsc_warn(DRV, "MII busy timeout!");
160
161out:
162 spin_unlock_irqrestore(&pd->phy_lock, flags);
163 return reg;
164}
165
166static int smsc9420_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
167 u16 val)
168{
169 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
170 unsigned long flags;
171 u32 addr;
172 int i, reg = -EIO;
173
174 spin_lock_irqsave(&pd->phy_lock, flags);
175
176 /* confirm MII not busy */
177 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
178 smsc_warn(DRV, "MII is busy???");
179 goto out;
180 }
181
182 /* put the data to write in the MAC */
183 smsc9420_reg_write(pd, MII_DATA, (u32)val);
184
185 /* set the address, index & direction (write to PHY) */
186 addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
187 MII_ACCESS_MII_WRITE_;
188 smsc9420_reg_write(pd, MII_ACCESS, addr);
189
190 /* wait for write to complete with 50us timeout */
191 for (i = 0; i < 5; i++) {
192 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
193 MII_ACCESS_MII_BUSY_)) {
194 reg = 0;
195 goto out;
196 }
197 udelay(10);
198 }
199
200 smsc_warn(DRV, "MII busy timeout!");
201
202out:
203 spin_unlock_irqrestore(&pd->phy_lock, flags);
204 return reg;
205}
206
207/* Returns hash bit number for given MAC address
208 * Example:
209 * 01 00 5E 00 00 01 -> returns bit number 31 */
210static u32 smsc9420_hash(u8 addr[ETH_ALEN])
211{
212 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
213}
214
215static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd)
216{
217 int timeout = 100000;
218
219 BUG_ON(!pd);
220
221 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
222 smsc_dbg(DRV, "smsc9420_eeprom_reload: Eeprom busy");
223 return -EIO;
224 }
225
226 smsc9420_reg_write(pd, E2P_CMD,
227 (E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_RELOAD_));
228
229 do {
230 udelay(10);
231 if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_))
232 return 0;
233 } while (timeout--);
234
235 smsc_warn(DRV, "smsc9420_eeprom_reload: Eeprom timed out");
236 return -EIO;
237}
238
239/* Standard ioctls for mii-tool */
240static int smsc9420_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
241{
242 struct smsc9420_pdata *pd = netdev_priv(dev);
243
244 if (!netif_running(dev) || !pd->phy_dev)
245 return -EINVAL;
246
247 return phy_mii_ioctl(pd->phy_dev, if_mii(ifr), cmd);
248}
249
250static int smsc9420_ethtool_get_settings(struct net_device *dev,
251 struct ethtool_cmd *cmd)
252{
253 struct smsc9420_pdata *pd = netdev_priv(dev);
254
255 cmd->maxtxpkt = 1;
256 cmd->maxrxpkt = 1;
257 return phy_ethtool_gset(pd->phy_dev, cmd);
258}
259
260static int smsc9420_ethtool_set_settings(struct net_device *dev,
261 struct ethtool_cmd *cmd)
262{
263 struct smsc9420_pdata *pd = netdev_priv(dev);
264
265 return phy_ethtool_sset(pd->phy_dev, cmd);
266}
267
268static void smsc9420_ethtool_get_drvinfo(struct net_device *netdev,
269 struct ethtool_drvinfo *drvinfo)
270{
271 struct smsc9420_pdata *pd = netdev_priv(netdev);
272
273 strcpy(drvinfo->driver, DRV_NAME);
274 strcpy(drvinfo->bus_info, pci_name(pd->pdev));
275 strcpy(drvinfo->version, DRV_VERSION);
276}
277
278static u32 smsc9420_ethtool_get_msglevel(struct net_device *netdev)
279{
280 struct smsc9420_pdata *pd = netdev_priv(netdev);
281 return pd->msg_enable;
282}
283
284static void smsc9420_ethtool_set_msglevel(struct net_device *netdev, u32 data)
285{
286 struct smsc9420_pdata *pd = netdev_priv(netdev);
287 pd->msg_enable = data;
288}
289
290static int smsc9420_ethtool_nway_reset(struct net_device *netdev)
291{
292 struct smsc9420_pdata *pd = netdev_priv(netdev);
293 return phy_start_aneg(pd->phy_dev);
294}
295
296static const struct ethtool_ops smsc9420_ethtool_ops = {
297 .get_settings = smsc9420_ethtool_get_settings,
298 .set_settings = smsc9420_ethtool_set_settings,
299 .get_drvinfo = smsc9420_ethtool_get_drvinfo,
300 .get_msglevel = smsc9420_ethtool_get_msglevel,
301 .set_msglevel = smsc9420_ethtool_set_msglevel,
302 .nway_reset = smsc9420_ethtool_nway_reset,
303 .get_link = ethtool_op_get_link,
304};
305
306/* Sets the device MAC address to dev_addr */
307static void smsc9420_set_mac_address(struct net_device *dev)
308{
309 struct smsc9420_pdata *pd = netdev_priv(dev);
310 u8 *dev_addr = dev->dev_addr;
311 u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
312 u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
313 (dev_addr[1] << 8) | dev_addr[0];
314
315 smsc9420_reg_write(pd, ADDRH, mac_high16);
316 smsc9420_reg_write(pd, ADDRL, mac_low32);
317}
318
319static void smsc9420_check_mac_address(struct net_device *dev)
320{
321 struct smsc9420_pdata *pd = netdev_priv(dev);
322
323 /* Check if mac address has been specified when bringing interface up */
324 if (is_valid_ether_addr(dev->dev_addr)) {
325 smsc9420_set_mac_address(dev);
326 smsc_dbg(PROBE, "MAC Address is specified by configuration");
327 } else {
328 /* Try reading mac address from device. if EEPROM is present
329 * it will already have been set */
330 u32 mac_high16 = smsc9420_reg_read(pd, ADDRH);
331 u32 mac_low32 = smsc9420_reg_read(pd, ADDRL);
332 dev->dev_addr[0] = (u8)(mac_low32);
333 dev->dev_addr[1] = (u8)(mac_low32 >> 8);
334 dev->dev_addr[2] = (u8)(mac_low32 >> 16);
335 dev->dev_addr[3] = (u8)(mac_low32 >> 24);
336 dev->dev_addr[4] = (u8)(mac_high16);
337 dev->dev_addr[5] = (u8)(mac_high16 >> 8);
338
339 if (is_valid_ether_addr(dev->dev_addr)) {
340 /* eeprom values are valid so use them */
341 smsc_dbg(PROBE, "Mac Address is read from EEPROM");
342 } else {
343 /* eeprom values are invalid, generate random MAC */
344 random_ether_addr(dev->dev_addr);
345 smsc9420_set_mac_address(dev);
346 smsc_dbg(PROBE,
347 "MAC Address is set to random_ether_addr");
348 }
349 }
350}
351
352static void smsc9420_stop_tx(struct smsc9420_pdata *pd)
353{
354 u32 dmac_control, mac_cr, dma_intr_ena;
355 int timeOut = 1000;
356
357 /* disable TX DMAC */
358 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
359 dmac_control &= (~DMAC_CONTROL_ST_);
360 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
361
362 /* Wait max 10ms for transmit process to stop */
363 while (timeOut--) {
364 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_)
365 break;
366 udelay(10);
367 }
368
369 if (!timeOut)
370 smsc_warn(IFDOWN, "TX DMAC failed to stop");
371
372 /* ACK Tx DMAC stop bit */
373 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_);
374
375 /* mask TX DMAC interrupts */
376 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
377 dma_intr_ena &= ~(DMAC_INTR_ENA_TX_);
378 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
379 smsc9420_pci_flush_write(pd);
380
381 /* stop MAC TX */
382 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_);
383 smsc9420_reg_write(pd, MAC_CR, mac_cr);
384 smsc9420_pci_flush_write(pd);
385}
386
387static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd)
388{
389 int i;
390
391 BUG_ON(!pd->tx_ring);
392
393 if (!pd->tx_buffers)
394 return;
395
396 for (i = 0; i < TX_RING_SIZE; i++) {
397 struct sk_buff *skb = pd->tx_buffers[i].skb;
398
399 if (skb) {
400 BUG_ON(!pd->tx_buffers[i].mapping);
401 pci_unmap_single(pd->pdev, pd->tx_buffers[i].mapping,
402 skb->len, PCI_DMA_TODEVICE);
403 dev_kfree_skb_any(skb);
404 }
405
406 pd->tx_ring[i].status = 0;
407 pd->tx_ring[i].length = 0;
408 pd->tx_ring[i].buffer1 = 0;
409 pd->tx_ring[i].buffer2 = 0;
410 }
411 wmb();
412
413 kfree(pd->tx_buffers);
414 pd->tx_buffers = NULL;
415
416 pd->tx_ring_head = 0;
417 pd->tx_ring_tail = 0;
418}
419
420static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd)
421{
422 int i;
423
424 BUG_ON(!pd->rx_ring);
425
426 if (!pd->rx_buffers)
427 return;
428
429 for (i = 0; i < RX_RING_SIZE; i++) {
430 if (pd->rx_buffers[i].skb)
431 dev_kfree_skb_any(pd->rx_buffers[i].skb);
432
433 if (pd->rx_buffers[i].mapping)
434 pci_unmap_single(pd->pdev, pd->rx_buffers[i].mapping,
435 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
436
437 pd->rx_ring[i].status = 0;
438 pd->rx_ring[i].length = 0;
439 pd->rx_ring[i].buffer1 = 0;
440 pd->rx_ring[i].buffer2 = 0;
441 }
442 wmb();
443
444 kfree(pd->rx_buffers);
445 pd->rx_buffers = NULL;
446
447 pd->rx_ring_head = 0;
448 pd->rx_ring_tail = 0;
449}
450
451static void smsc9420_stop_rx(struct smsc9420_pdata *pd)
452{
453 int timeOut = 1000;
454 u32 mac_cr, dmac_control, dma_intr_ena;
455
456 /* mask RX DMAC interrupts */
457 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
458 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
459 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
460 smsc9420_pci_flush_write(pd);
461
462 /* stop RX MAC prior to stoping DMA */
463 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_);
464 smsc9420_reg_write(pd, MAC_CR, mac_cr);
465 smsc9420_pci_flush_write(pd);
466
467 /* stop RX DMAC */
468 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
469 dmac_control &= (~DMAC_CONTROL_SR_);
470 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
471 smsc9420_pci_flush_write(pd);
472
473 /* wait up to 10ms for receive to stop */
474 while (timeOut--) {
475 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_)
476 break;
477 udelay(10);
478 }
479
480 if (!timeOut)
481 smsc_warn(IFDOWN, "RX DMAC did not stop! timeout.");
482
483 /* ACK the Rx DMAC stop bit */
484 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_);
485}
486
487static irqreturn_t smsc9420_isr(int irq, void *dev_id)
488{
489 struct smsc9420_pdata *pd = dev_id;
490 u32 int_cfg, int_sts, int_ctl;
491 irqreturn_t ret = IRQ_NONE;
492 ulong flags;
493
494 BUG_ON(!pd);
495 BUG_ON(!pd->base_addr);
496
497 int_cfg = smsc9420_reg_read(pd, INT_CFG);
498
499 /* check if it's our interrupt */
500 if ((int_cfg & (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_)) !=
501 (INT_CFG_IRQ_EN_ | INT_CFG_IRQ_INT_))
502 return IRQ_NONE;
503
504 int_sts = smsc9420_reg_read(pd, INT_STAT);
505
506 if (likely(INT_STAT_DMAC_INT_ & int_sts)) {
507 u32 status = smsc9420_reg_read(pd, DMAC_STATUS);
508 u32 ints_to_clear = 0;
509
510 if (status & DMAC_STS_TX_) {
511 ints_to_clear |= (DMAC_STS_TX_ | DMAC_STS_NIS_);
512 netif_wake_queue(pd->dev);
513 }
514
515 if (status & DMAC_STS_RX_) {
516 /* mask RX DMAC interrupts */
517 u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
518 dma_intr_ena &= (~DMAC_INTR_ENA_RX_);
519 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
520 smsc9420_pci_flush_write(pd);
521
522 ints_to_clear |= (DMAC_STS_RX_ | DMAC_STS_NIS_);
523 netif_rx_schedule(pd->dev, &pd->napi);
524 }
525
526 if (ints_to_clear)
527 smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear);
528
529 ret = IRQ_HANDLED;
530 }
531
532 if (unlikely(INT_STAT_SW_INT_ & int_sts)) {
533 /* mask software interrupt */
534 spin_lock_irqsave(&pd->int_lock, flags);
535 int_ctl = smsc9420_reg_read(pd, INT_CTL);
536 int_ctl &= (~INT_CTL_SW_INT_EN_);
537 smsc9420_reg_write(pd, INT_CTL, int_ctl);
538 spin_unlock_irqrestore(&pd->int_lock, flags);
539
540 smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_);
541 pd->software_irq_signal = true;
542 smp_wmb();
543
544 ret = IRQ_HANDLED;
545 }
546
547 /* to ensure PCI write completion, we must perform a PCI read */
548 smsc9420_pci_flush_write(pd);
549
550 return ret;
551}
552
553static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd)
554{
555 smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_);
556 smsc9420_reg_read(pd, BUS_MODE);
557 udelay(2);
558 if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_)
559 smsc_warn(DRV, "Software reset not cleared");
560}
561
562static int smsc9420_stop(struct net_device *dev)
563{
564 struct smsc9420_pdata *pd = netdev_priv(dev);
565 u32 int_cfg;
566 ulong flags;
567
568 BUG_ON(!pd);
569 BUG_ON(!pd->phy_dev);
570
571 /* disable master interrupt */
572 spin_lock_irqsave(&pd->int_lock, flags);
573 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
574 smsc9420_reg_write(pd, INT_CFG, int_cfg);
575 spin_unlock_irqrestore(&pd->int_lock, flags);
576
577 netif_tx_disable(dev);
578 napi_disable(&pd->napi);
579
580 smsc9420_stop_tx(pd);
581 smsc9420_free_tx_ring(pd);
582
583 smsc9420_stop_rx(pd);
584 smsc9420_free_rx_ring(pd);
585
586 free_irq(dev->irq, pd);
587
588 smsc9420_dmac_soft_reset(pd);
589
590 phy_stop(pd->phy_dev);
591
592 phy_disconnect(pd->phy_dev);
593 pd->phy_dev = NULL;
594 mdiobus_unregister(pd->mii_bus);
595 mdiobus_free(pd->mii_bus);
596
597 return 0;
598}
599
600static void smsc9420_rx_count_stats(struct net_device *dev, u32 desc_status)
601{
602 if (unlikely(desc_status & RDES0_ERROR_SUMMARY_)) {
603 dev->stats.rx_errors++;
604 if (desc_status & RDES0_DESCRIPTOR_ERROR_)
605 dev->stats.rx_over_errors++;
606 else if (desc_status & (RDES0_FRAME_TOO_LONG_ |
607 RDES0_RUNT_FRAME_ | RDES0_COLLISION_SEEN_))
608 dev->stats.rx_frame_errors++;
609 else if (desc_status & RDES0_CRC_ERROR_)
610 dev->stats.rx_crc_errors++;
611 }
612
613 if (unlikely(desc_status & RDES0_LENGTH_ERROR_))
614 dev->stats.rx_length_errors++;
615
616 if (unlikely(!((desc_status & RDES0_LAST_DESCRIPTOR_) &&
617 (desc_status & RDES0_FIRST_DESCRIPTOR_))))
618 dev->stats.rx_length_errors++;
619
620 if (desc_status & RDES0_MULTICAST_FRAME_)
621 dev->stats.multicast++;
622}
623
624static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index,
625 const u32 status)
626{
627 struct net_device *dev = pd->dev;
628 struct sk_buff *skb;
629 u16 packet_length = (status & RDES0_FRAME_LENGTH_MASK_)
630 >> RDES0_FRAME_LENGTH_SHFT_;
631
632 /* remove crc from packet lendth */
633 packet_length -= 4;
634
635 if (pd->rx_csum)
636 packet_length -= 2;
637
638 dev->stats.rx_packets++;
639 dev->stats.rx_bytes += packet_length;
640
641 pci_unmap_single(pd->pdev, pd->rx_buffers[index].mapping,
642 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
643 pd->rx_buffers[index].mapping = 0;
644
645 skb = pd->rx_buffers[index].skb;
646 pd->rx_buffers[index].skb = NULL;
647
648 if (pd->rx_csum) {
649 u16 hw_csum = get_unaligned_le16(skb_tail_pointer(skb) +
650 NET_IP_ALIGN + packet_length + 4);
651 put_unaligned_le16(cpu_to_le16(hw_csum), &skb->csum);
652 skb->ip_summed = CHECKSUM_COMPLETE;
653 }
654
655 skb_reserve(skb, NET_IP_ALIGN);
656 skb_put(skb, packet_length);
657
658 skb->protocol = eth_type_trans(skb, dev);
659
660 netif_receive_skb(skb);
661 dev->last_rx = jiffies;
662}
663
664static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index)
665{
666 struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ);
667 dma_addr_t mapping;
668
669 BUG_ON(pd->rx_buffers[index].skb);
670 BUG_ON(pd->rx_buffers[index].mapping);
671
672 if (unlikely(!skb)) {
673 smsc_warn(RX_ERR, "Failed to allocate new skb!");
674 return -ENOMEM;
675 }
676
677 skb->dev = pd->dev;
678
679 mapping = pci_map_single(pd->pdev, skb_tail_pointer(skb),
680 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
681 if (pci_dma_mapping_error(pd->pdev, mapping)) {
682 dev_kfree_skb_any(skb);
683 smsc_warn(RX_ERR, "pci_map_single failed!");
684 return -ENOMEM;
685 }
686
687 pd->rx_buffers[index].skb = skb;
688 pd->rx_buffers[index].mapping = mapping;
689 pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN;
690 pd->rx_ring[index].status = RDES0_OWN_;
691 wmb();
692
693 return 0;
694}
695
696static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd)
697{
698 while (pd->rx_ring_tail != pd->rx_ring_head) {
699 if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail))
700 break;
701
702 pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE;
703 }
704}
705
706static int smsc9420_rx_poll(struct napi_struct *napi, int budget)
707{
708 struct smsc9420_pdata *pd =
709 container_of(napi, struct smsc9420_pdata, napi);
710 struct net_device *dev = pd->dev;
711 u32 drop_frame_cnt, dma_intr_ena, status;
712 int work_done;
713
714 for (work_done = 0; work_done < budget; work_done++) {
715 rmb();
716 status = pd->rx_ring[pd->rx_ring_head].status;
717
718 /* stop if DMAC owns this dma descriptor */
719 if (status & RDES0_OWN_)
720 break;
721
722 smsc9420_rx_count_stats(dev, status);
723 smsc9420_rx_handoff(pd, pd->rx_ring_head, status);
724 pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE;
725 smsc9420_alloc_new_rx_buffers(pd);
726 }
727
728 drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
729 dev->stats.rx_dropped +=
730 (drop_frame_cnt & 0xFFFF) + ((drop_frame_cnt >> 17) & 0x3FF);
731
732 /* Kick RXDMA */
733 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
734 smsc9420_pci_flush_write(pd);
735
736 if (work_done < budget) {
737 netif_rx_complete(dev, &pd->napi);
738
739 /* re-enable RX DMA interrupts */
740 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
741 dma_intr_ena |= (DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
742 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
743 smsc9420_pci_flush_write(pd);
744 }
745 return work_done;
746}
747
748static void
749smsc9420_tx_update_stats(struct net_device *dev, u32 status, u32 length)
750{
751 if (unlikely(status & TDES0_ERROR_SUMMARY_)) {
752 dev->stats.tx_errors++;
753 if (status & (TDES0_EXCESSIVE_DEFERRAL_ |
754 TDES0_EXCESSIVE_COLLISIONS_))
755 dev->stats.tx_aborted_errors++;
756
757 if (status & (TDES0_LOSS_OF_CARRIER_ | TDES0_NO_CARRIER_))
758 dev->stats.tx_carrier_errors++;
759 } else {
760 dev->stats.tx_packets++;
761 dev->stats.tx_bytes += (length & 0x7FF);
762 }
763
764 if (unlikely(status & TDES0_EXCESSIVE_COLLISIONS_)) {
765 dev->stats.collisions += 16;
766 } else {
767 dev->stats.collisions +=
768 (status & TDES0_COLLISION_COUNT_MASK_) >>
769 TDES0_COLLISION_COUNT_SHFT_;
770 }
771
772 if (unlikely(status & TDES0_HEARTBEAT_FAIL_))
773 dev->stats.tx_heartbeat_errors++;
774}
775
776/* Check for completed dma transfers, update stats and free skbs */
777static void smsc9420_complete_tx(struct net_device *dev)
778{
779 struct smsc9420_pdata *pd = netdev_priv(dev);
780
781 while (pd->tx_ring_tail != pd->tx_ring_head) {
782 int index = pd->tx_ring_tail;
783 u32 status, length;
784
785 rmb();
786 status = pd->tx_ring[index].status;
787 length = pd->tx_ring[index].length;
788
789 /* Check if DMA still owns this descriptor */
790 if (unlikely(TDES0_OWN_ & status))
791 break;
792
793 smsc9420_tx_update_stats(dev, status, length);
794
795 BUG_ON(!pd->tx_buffers[index].skb);
796 BUG_ON(!pd->tx_buffers[index].mapping);
797
798 pci_unmap_single(pd->pdev, pd->tx_buffers[index].mapping,
799 pd->tx_buffers[index].skb->len, PCI_DMA_TODEVICE);
800 pd->tx_buffers[index].mapping = 0;
801
802 dev_kfree_skb_any(pd->tx_buffers[index].skb);
803 pd->tx_buffers[index].skb = NULL;
804
805 pd->tx_ring[index].buffer1 = 0;
806 wmb();
807
808 pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE;
809 }
810}
811
812static int smsc9420_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
813{
814 struct smsc9420_pdata *pd = netdev_priv(dev);
815 dma_addr_t mapping;
816 int index = pd->tx_ring_head;
817 u32 tmp_desc1;
818 bool about_to_take_last_desc =
819 (((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail);
820
821 smsc9420_complete_tx(dev);
822
823 rmb();
824 BUG_ON(pd->tx_ring[index].status & TDES0_OWN_);
825 BUG_ON(pd->tx_buffers[index].skb);
826 BUG_ON(pd->tx_buffers[index].mapping);
827
828 mapping = pci_map_single(pd->pdev, skb->data,
829 skb->len, PCI_DMA_TODEVICE);
830 if (pci_dma_mapping_error(pd->pdev, mapping)) {
831 smsc_warn(TX_ERR, "pci_map_single failed, dropping packet");
832 return NETDEV_TX_BUSY;
833 }
834
835 pd->tx_buffers[index].skb = skb;
836 pd->tx_buffers[index].mapping = mapping;
837
838 tmp_desc1 = (TDES1_LS_ | ((u32)skb->len & 0x7FF));
839 if (unlikely(about_to_take_last_desc)) {
840 tmp_desc1 |= TDES1_IC_;
841 netif_stop_queue(pd->dev);
842 }
843
844 /* check if we are at the last descriptor and need to set EOR */
845 if (unlikely(index == (TX_RING_SIZE - 1)))
846 tmp_desc1 |= TDES1_TER_;
847
848 pd->tx_ring[index].buffer1 = mapping;
849 pd->tx_ring[index].length = tmp_desc1;
850 wmb();
851
852 /* increment head */
853 pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE;
854
855 /* assign ownership to DMAC */
856 pd->tx_ring[index].status = TDES0_OWN_;
857 wmb();
858
859 /* kick the DMA */
860 smsc9420_reg_write(pd, TX_POLL_DEMAND, 1);
861 smsc9420_pci_flush_write(pd);
862
863 dev->trans_start = jiffies;
864
865 return NETDEV_TX_OK;
866}
867
868static struct net_device_stats *smsc9420_get_stats(struct net_device *dev)
869{
870 struct smsc9420_pdata *pd = netdev_priv(dev);
871 u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
872 dev->stats.rx_dropped +=
873 (counter & 0x0000FFFF) + ((counter >> 17) & 0x000003FF);
874 return &dev->stats;
875}
876
877static void smsc9420_set_multicast_list(struct net_device *dev)
878{
879 struct smsc9420_pdata *pd = netdev_priv(dev);
880 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
881
882 if (dev->flags & IFF_PROMISC) {
883 smsc_dbg(HW, "Promiscuous Mode Enabled");
884 mac_cr |= MAC_CR_PRMS_;
885 mac_cr &= (~MAC_CR_MCPAS_);
886 mac_cr &= (~MAC_CR_HPFILT_);
887 } else if (dev->flags & IFF_ALLMULTI) {
888 smsc_dbg(HW, "Receive all Multicast Enabled");
889 mac_cr &= (~MAC_CR_PRMS_);
890 mac_cr |= MAC_CR_MCPAS_;
891 mac_cr &= (~MAC_CR_HPFILT_);
892 } else if (dev->mc_count > 0) {
893 struct dev_mc_list *mc_list = dev->mc_list;
894 u32 hash_lo = 0, hash_hi = 0;
895
896 smsc_dbg(HW, "Multicast filter enabled");
897 while (mc_list) {
898 u32 bit_num = smsc9420_hash(mc_list->dmi_addr);
899 u32 mask = 1 << (bit_num & 0x1F);
900
901 if (bit_num & 0x20)
902 hash_hi |= mask;
903 else
904 hash_lo |= mask;
905
906 mc_list = mc_list->next;
907 }
908 smsc9420_reg_write(pd, HASHH, hash_hi);
909 smsc9420_reg_write(pd, HASHL, hash_lo);
910
911 mac_cr &= (~MAC_CR_PRMS_);
912 mac_cr &= (~MAC_CR_MCPAS_);
913 mac_cr |= MAC_CR_HPFILT_;
914 } else {
915 smsc_dbg(HW, "Receive own packets only.");
916 smsc9420_reg_write(pd, HASHH, 0);
917 smsc9420_reg_write(pd, HASHL, 0);
918
919 mac_cr &= (~MAC_CR_PRMS_);
920 mac_cr &= (~MAC_CR_MCPAS_);
921 mac_cr &= (~MAC_CR_HPFILT_);
922 }
923
924 smsc9420_reg_write(pd, MAC_CR, mac_cr);
925 smsc9420_pci_flush_write(pd);
926}
927
928static u8 smsc9420_resolve_flowctrl_fulldplx(u16 lcladv, u16 rmtadv)
929{
930 u8 cap = 0;
931
932 if (lcladv & ADVERTISE_PAUSE_CAP) {
933 if (lcladv & ADVERTISE_PAUSE_ASYM) {
934 if (rmtadv & LPA_PAUSE_CAP)
935 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
936 else if (rmtadv & LPA_PAUSE_ASYM)
937 cap = FLOW_CTRL_RX;
938 } else {
939 if (rmtadv & LPA_PAUSE_CAP)
940 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
941 }
942 } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
943 if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
944 cap = FLOW_CTRL_TX;
945 }
946
947 return cap;
948}
949
950static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd)
951{
952 struct phy_device *phy_dev = pd->phy_dev;
953 u32 flow;
954
955 if (phy_dev->duplex == DUPLEX_FULL) {
956 u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
957 u16 rmtadv = phy_read(phy_dev, MII_LPA);
958 u8 cap = smsc9420_resolve_flowctrl_fulldplx(lcladv, rmtadv);
959
960 if (cap & FLOW_CTRL_RX)
961 flow = 0xFFFF0002;
962 else
963 flow = 0;
964
965 smsc_info(LINK, "rx pause %s, tx pause %s",
966 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
967 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
968 } else {
969 smsc_info(LINK, "half duplex");
970 flow = 0;
971 }
972
973 smsc9420_reg_write(pd, FLOW, flow);
974}
975
976/* Update link mode if anything has changed. Called periodically when the
977 * PHY is in polling mode, even if nothing has changed. */
978static void smsc9420_phy_adjust_link(struct net_device *dev)
979{
980 struct smsc9420_pdata *pd = netdev_priv(dev);
981 struct phy_device *phy_dev = pd->phy_dev;
982 int carrier;
983
984 if (phy_dev->duplex != pd->last_duplex) {
985 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
986 if (phy_dev->duplex) {
987 smsc_dbg(LINK, "full duplex mode");
988 mac_cr |= MAC_CR_FDPX_;
989 } else {
990 smsc_dbg(LINK, "half duplex mode");
991 mac_cr &= ~MAC_CR_FDPX_;
992 }
993 smsc9420_reg_write(pd, MAC_CR, mac_cr);
994
995 smsc9420_phy_update_flowcontrol(pd);
996 pd->last_duplex = phy_dev->duplex;
997 }
998
999 carrier = netif_carrier_ok(dev);
1000 if (carrier != pd->last_carrier) {
1001 if (carrier)
1002 smsc_dbg(LINK, "carrier OK");
1003 else
1004 smsc_dbg(LINK, "no carrier");
1005 pd->last_carrier = carrier;
1006 }
1007}
1008
1009static int smsc9420_mii_probe(struct net_device *dev)
1010{
1011 struct smsc9420_pdata *pd = netdev_priv(dev);
1012 struct phy_device *phydev = NULL;
1013
1014 BUG_ON(pd->phy_dev);
1015
1016 /* Device only supports internal PHY at address 1 */
1017 if (!pd->mii_bus->phy_map[1]) {
1018 pr_err("%s: no PHY found at address 1\n", dev->name);
1019 return -ENODEV;
1020 }
1021
1022 phydev = pd->mii_bus->phy_map[1];
1023 smsc_info(PROBE, "PHY addr %d, phy_id 0x%08X", phydev->addr,
1024 phydev->phy_id);
1025
1026 phydev = phy_connect(dev, phydev->dev.bus_id,
1027 &smsc9420_phy_adjust_link, 0, PHY_INTERFACE_MODE_MII);
1028
1029 if (IS_ERR(phydev)) {
1030 pr_err("%s: Could not attach to PHY\n", dev->name);
1031 return PTR_ERR(phydev);
1032 }
1033
1034 pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1035 dev->name, phydev->drv->name, phydev->dev.bus_id, phydev->irq);
1036
1037 /* mask with MAC supported features */
1038 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
1039 SUPPORTED_Asym_Pause);
1040 phydev->advertising = phydev->supported;
1041
1042 pd->phy_dev = phydev;
1043 pd->last_duplex = -1;
1044 pd->last_carrier = -1;
1045
1046 return 0;
1047}
1048
1049static int smsc9420_mii_init(struct net_device *dev)
1050{
1051 struct smsc9420_pdata *pd = netdev_priv(dev);
1052 int err = -ENXIO, i;
1053
1054 pd->mii_bus = mdiobus_alloc();
1055 if (!pd->mii_bus) {
1056 err = -ENOMEM;
1057 goto err_out_1;
1058 }
1059 pd->mii_bus->name = DRV_MDIONAME;
1060 snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x",
1061 (pd->pdev->bus->number << 8) | pd->pdev->devfn);
1062 pd->mii_bus->priv = pd;
1063 pd->mii_bus->read = smsc9420_mii_read;
1064 pd->mii_bus->write = smsc9420_mii_write;
1065 pd->mii_bus->irq = pd->phy_irq;
1066 for (i = 0; i < PHY_MAX_ADDR; ++i)
1067 pd->mii_bus->irq[i] = PHY_POLL;
1068
1069 /* Mask all PHYs except ID 1 (internal) */
1070 pd->mii_bus->phy_mask = ~(1 << 1);
1071
1072 if (mdiobus_register(pd->mii_bus)) {
1073 smsc_warn(PROBE, "Error registering mii bus");
1074 goto err_out_free_bus_2;
1075 }
1076
1077 if (smsc9420_mii_probe(dev) < 0) {
1078 smsc_warn(PROBE, "Error probing mii bus");
1079 goto err_out_unregister_bus_3;
1080 }
1081
1082 return 0;
1083
1084err_out_unregister_bus_3:
1085 mdiobus_unregister(pd->mii_bus);
1086err_out_free_bus_2:
1087 mdiobus_free(pd->mii_bus);
1088err_out_1:
1089 return err;
1090}
1091
1092static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd)
1093{
1094 int i;
1095
1096 BUG_ON(!pd->tx_ring);
1097
1098 pd->tx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) *
1099 TX_RING_SIZE), GFP_KERNEL);
1100 if (!pd->tx_buffers) {
1101 smsc_warn(IFUP, "Failed to allocated tx_buffers");
1102 return -ENOMEM;
1103 }
1104
1105 /* Initialize the TX Ring */
1106 for (i = 0; i < TX_RING_SIZE; i++) {
1107 pd->tx_buffers[i].skb = NULL;
1108 pd->tx_buffers[i].mapping = 0;
1109 pd->tx_ring[i].status = 0;
1110 pd->tx_ring[i].length = 0;
1111 pd->tx_ring[i].buffer1 = 0;
1112 pd->tx_ring[i].buffer2 = 0;
1113 }
1114 pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_;
1115 wmb();
1116
1117 pd->tx_ring_head = 0;
1118 pd->tx_ring_tail = 0;
1119
1120 smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr);
1121 smsc9420_pci_flush_write(pd);
1122
1123 return 0;
1124}
1125
1126static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd)
1127{
1128 int i;
1129
1130 BUG_ON(!pd->rx_ring);
1131
1132 pd->rx_buffers = kmalloc((sizeof(struct smsc9420_ring_info) *
1133 RX_RING_SIZE), GFP_KERNEL);
1134 if (pd->rx_buffers == NULL) {
1135 smsc_warn(IFUP, "Failed to allocated rx_buffers");
1136 goto out;
1137 }
1138
1139 /* initialize the rx ring */
1140 for (i = 0; i < RX_RING_SIZE; i++) {
1141 pd->rx_ring[i].status = 0;
1142 pd->rx_ring[i].length = PKT_BUF_SZ;
1143 pd->rx_ring[i].buffer2 = 0;
1144 pd->rx_buffers[i].skb = NULL;
1145 pd->rx_buffers[i].mapping = 0;
1146 }
1147 pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_);
1148
1149 /* now allocate the entire ring of skbs */
1150 for (i = 0; i < RX_RING_SIZE; i++) {
1151 if (smsc9420_alloc_rx_buffer(pd, i)) {
1152 smsc_warn(IFUP, "failed to allocate rx skb %d", i);
1153 goto out_free_rx_skbs;
1154 }
1155 }
1156
1157 pd->rx_ring_head = 0;
1158 pd->rx_ring_tail = 0;
1159
1160 smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q);
1161 smsc_dbg(IFUP, "VLAN1 = 0x%08x", smsc9420_reg_read(pd, VLAN1));
1162
1163 if (pd->rx_csum) {
1164 /* Enable RX COE */
1165 u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN;
1166 smsc9420_reg_write(pd, COE_CR, coe);
1167 smsc_dbg(IFUP, "COE_CR = 0x%08x", coe);
1168 }
1169
1170 smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr);
1171 smsc9420_pci_flush_write(pd);
1172
1173 return 0;
1174
1175out_free_rx_skbs:
1176 smsc9420_free_rx_ring(pd);
1177out:
1178 return -ENOMEM;
1179}
1180
1181static int smsc9420_open(struct net_device *dev)
1182{
1183 struct smsc9420_pdata *pd;
1184 u32 bus_mode, mac_cr, dmac_control, int_cfg, dma_intr_ena, int_ctl;
1185 unsigned long flags;
1186 int result = 0, timeout;
1187
1188 BUG_ON(!dev);
1189 pd = netdev_priv(dev);
1190 BUG_ON(!pd);
1191
1192 if (!is_valid_ether_addr(dev->dev_addr)) {
1193 smsc_warn(IFUP, "dev_addr is not a valid MAC address");
1194 result = -EADDRNOTAVAIL;
1195 goto out_0;
1196 }
1197
1198 netif_carrier_off(dev);
1199
1200 /* disable, mask and acknowlege all interrupts */
1201 spin_lock_irqsave(&pd->int_lock, flags);
1202 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1203 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1204 smsc9420_reg_write(pd, INT_CTL, 0);
1205 spin_unlock_irqrestore(&pd->int_lock, flags);
1206 smsc9420_reg_write(pd, DMAC_INTR_ENA, 0);
1207 smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF);
1208 smsc9420_pci_flush_write(pd);
1209
1210 if (request_irq(dev->irq, smsc9420_isr, IRQF_SHARED | IRQF_DISABLED,
1211 DRV_NAME, pd)) {
1212 smsc_warn(IFUP, "Unable to use IRQ = %d", dev->irq);
1213 result = -ENODEV;
1214 goto out_0;
1215 }
1216
1217 smsc9420_dmac_soft_reset(pd);
1218
1219 /* make sure MAC_CR is sane */
1220 smsc9420_reg_write(pd, MAC_CR, 0);
1221
1222 smsc9420_set_mac_address(dev);
1223
1224 /* Configure GPIO pins to drive LEDs */
1225 smsc9420_reg_write(pd, GPIO_CFG,
1226 (GPIO_CFG_LED_3_ | GPIO_CFG_LED_2_ | GPIO_CFG_LED_1_));
1227
1228 bus_mode = BUS_MODE_DMA_BURST_LENGTH_16;
1229
1230#ifdef __BIG_ENDIAN
1231 bus_mode |= BUS_MODE_DBO_;
1232#endif
1233
1234 smsc9420_reg_write(pd, BUS_MODE, bus_mode);
1235
1236 smsc9420_pci_flush_write(pd);
1237
1238 /* set bus master bridge arbitration priority for Rx and TX DMA */
1239 smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1);
1240
1241 smsc9420_reg_write(pd, DMAC_CONTROL,
1242 (DMAC_CONTROL_SF_ | DMAC_CONTROL_OSF_));
1243
1244 smsc9420_pci_flush_write(pd);
1245
1246 /* test the IRQ connection to the ISR */
1247 smsc_dbg(IFUP, "Testing ISR using IRQ %d", dev->irq);
1248
1249 spin_lock_irqsave(&pd->int_lock, flags);
1250 /* configure interrupt deassertion timer and enable interrupts */
1251 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1252 int_cfg &= ~(INT_CFG_INT_DEAS_MASK);
1253 int_cfg |= (INT_DEAS_TIME & INT_CFG_INT_DEAS_MASK);
1254 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1255
1256 /* unmask software interrupt */
1257 int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_;
1258 smsc9420_reg_write(pd, INT_CTL, int_ctl);
1259 spin_unlock_irqrestore(&pd->int_lock, flags);
1260 smsc9420_pci_flush_write(pd);
1261
1262 timeout = 1000;
1263 pd->software_irq_signal = false;
1264 smp_wmb();
1265 while (timeout--) {
1266 if (pd->software_irq_signal)
1267 break;
1268 msleep(1);
1269 }
1270
1271 /* disable interrupts */
1272 spin_lock_irqsave(&pd->int_lock, flags);
1273 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1274 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1275 spin_unlock_irqrestore(&pd->int_lock, flags);
1276
1277 if (!pd->software_irq_signal) {
1278 smsc_warn(IFUP, "ISR failed signaling test");
1279 result = -ENODEV;
1280 goto out_free_irq_1;
1281 }
1282
1283 smsc_dbg(IFUP, "ISR passed test using IRQ %d", dev->irq);
1284
1285 result = smsc9420_alloc_tx_ring(pd);
1286 if (result) {
1287 smsc_warn(IFUP, "Failed to Initialize tx dma ring");
1288 result = -ENOMEM;
1289 goto out_free_irq_1;
1290 }
1291
1292 result = smsc9420_alloc_rx_ring(pd);
1293 if (result) {
1294 smsc_warn(IFUP, "Failed to Initialize rx dma ring");
1295 result = -ENOMEM;
1296 goto out_free_tx_ring_2;
1297 }
1298
1299 result = smsc9420_mii_init(dev);
1300 if (result) {
1301 smsc_warn(IFUP, "Failed to initialize Phy");
1302 result = -ENODEV;
1303 goto out_free_rx_ring_3;
1304 }
1305
1306 /* Bring the PHY up */
1307 phy_start(pd->phy_dev);
1308
1309 napi_enable(&pd->napi);
1310
1311 /* start tx and rx */
1312 mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_;
1313 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1314
1315 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
1316 dmac_control |= DMAC_CONTROL_ST_ | DMAC_CONTROL_SR_;
1317 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
1318 smsc9420_pci_flush_write(pd);
1319
1320 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
1321 dma_intr_ena |=
1322 (DMAC_INTR_ENA_TX_ | DMAC_INTR_ENA_RX_ | DMAC_INTR_ENA_NIS_);
1323 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
1324 smsc9420_pci_flush_write(pd);
1325
1326 netif_wake_queue(dev);
1327
1328 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
1329
1330 /* enable interrupts */
1331 spin_lock_irqsave(&pd->int_lock, flags);
1332 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1333 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1334 spin_unlock_irqrestore(&pd->int_lock, flags);
1335
1336 return 0;
1337
1338out_free_rx_ring_3:
1339 smsc9420_free_rx_ring(pd);
1340out_free_tx_ring_2:
1341 smsc9420_free_tx_ring(pd);
1342out_free_irq_1:
1343 free_irq(dev->irq, pd);
1344out_0:
1345 return result;
1346}
1347
1348#ifdef CONFIG_PM
1349
1350static int smsc9420_suspend(struct pci_dev *pdev, pm_message_t state)
1351{
1352 struct net_device *dev = pci_get_drvdata(pdev);
1353 struct smsc9420_pdata *pd = netdev_priv(dev);
1354 u32 int_cfg;
1355 ulong flags;
1356
1357 /* disable interrupts */
1358 spin_lock_irqsave(&pd->int_lock, flags);
1359 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1360 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1361 spin_unlock_irqrestore(&pd->int_lock, flags);
1362
1363 if (netif_running(dev)) {
1364 netif_tx_disable(dev);
1365 smsc9420_stop_tx(pd);
1366 smsc9420_free_tx_ring(pd);
1367
1368 napi_disable(&pd->napi);
1369 smsc9420_stop_rx(pd);
1370 smsc9420_free_rx_ring(pd);
1371
1372 free_irq(dev->irq, pd);
1373
1374 netif_device_detach(dev);
1375 }
1376
1377 pci_save_state(pdev);
1378 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1379 pci_disable_device(pdev);
1380 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1381
1382 return 0;
1383}
1384
1385static int smsc9420_resume(struct pci_dev *pdev)
1386{
1387 struct net_device *dev = pci_get_drvdata(pdev);
1388 struct smsc9420_pdata *pd = netdev_priv(dev);
1389 int err;
1390
1391 pci_set_power_state(pdev, PCI_D0);
1392 pci_restore_state(pdev);
1393
1394 err = pci_enable_device(pdev);
1395 if (err)
1396 return err;
1397
1398 pci_set_master(pdev);
1399
1400 err = pci_enable_wake(pdev, 0, 0);
1401 if (err)
1402 smsc_warn(IFUP, "pci_enable_wake failed: %d", err);
1403
1404 if (netif_running(dev)) {
1405 err = smsc9420_open(dev);
1406 netif_device_attach(dev);
1407 }
1408 return err;
1409}
1410
1411#endif /* CONFIG_PM */
1412
1413static const struct net_device_ops smsc9420_netdev_ops = {
1414 .ndo_open = smsc9420_open,
1415 .ndo_stop = smsc9420_stop,
1416 .ndo_start_xmit = smsc9420_hard_start_xmit,
1417 .ndo_get_stats = smsc9420_get_stats,
1418 .ndo_set_multicast_list = smsc9420_set_multicast_list,
1419 .ndo_do_ioctl = smsc9420_do_ioctl,
1420 .ndo_validate_addr = eth_validate_addr,
1421};
1422
1423static int __devinit
1424smsc9420_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1425{
1426 struct net_device *dev;
1427 struct smsc9420_pdata *pd;
1428 void __iomem *virt_addr;
1429 int result = 0;
1430 u32 id_rev;
1431
1432 printk(KERN_INFO DRV_DESCRIPTION " version " DRV_VERSION "\n");
1433
1434 /* First do the PCI initialisation */
1435 result = pci_enable_device(pdev);
1436 if (unlikely(result)) {
1437 printk(KERN_ERR "Cannot enable smsc9420\n");
1438 goto out_0;
1439 }
1440
1441 pci_set_master(pdev);
1442
1443 dev = alloc_etherdev(sizeof(*pd));
1444 if (!dev) {
1445 printk(KERN_ERR "ether device alloc failed\n");
1446 goto out_disable_pci_device_1;
1447 }
1448
1449 SET_NETDEV_DEV(dev, &pdev->dev);
1450
1451 if (!(pci_resource_flags(pdev, SMSC_BAR) & IORESOURCE_MEM)) {
1452 printk(KERN_ERR "Cannot find PCI device base address\n");
1453 goto out_free_netdev_2;
1454 }
1455
1456 if ((pci_request_regions(pdev, DRV_NAME))) {
1457 printk(KERN_ERR "Cannot obtain PCI resources, aborting.\n");
1458 goto out_free_netdev_2;
1459 }
1460
1461 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1462 printk(KERN_ERR "No usable DMA configuration, aborting.\n");
1463 goto out_free_regions_3;
1464 }
1465
1466 virt_addr = ioremap(pci_resource_start(pdev, SMSC_BAR),
1467 pci_resource_len(pdev, SMSC_BAR));
1468 if (!virt_addr) {
1469 printk(KERN_ERR "Cannot map device registers, aborting.\n");
1470 goto out_free_regions_3;
1471 }
1472
1473 /* registers are double mapped with 0 offset for LE and 0x200 for BE */
1474 virt_addr += LAN9420_CPSR_ENDIAN_OFFSET;
1475
1476 dev->base_addr = (ulong)virt_addr;
1477
1478 pd = netdev_priv(dev);
1479
1480 /* pci descriptors are created in the PCI consistent area */
1481 pd->rx_ring = pci_alloc_consistent(pdev,
1482 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE +
1483 sizeof(struct smsc9420_dma_desc) * TX_RING_SIZE,
1484 &pd->rx_dma_addr);
1485
1486 if (!pd->rx_ring)
1487 goto out_free_io_4;
1488
1489 /* descriptors are aligned due to the nature of pci_alloc_consistent */
1490 pd->tx_ring = (struct smsc9420_dma_desc *)
1491 (pd->rx_ring + RX_RING_SIZE);
1492 pd->tx_dma_addr = pd->rx_dma_addr +
1493 sizeof(struct smsc9420_dma_desc) * RX_RING_SIZE;
1494
1495 pd->pdev = pdev;
1496 pd->dev = dev;
1497 pd->base_addr = virt_addr;
1498 pd->msg_enable = smsc_debug;
1499 pd->rx_csum = true;
1500
1501 smsc_dbg(PROBE, "lan_base=0x%08lx", (ulong)virt_addr);
1502
1503 id_rev = smsc9420_reg_read(pd, ID_REV);
1504 switch (id_rev & 0xFFFF0000) {
1505 case 0x94200000:
1506 smsc_info(PROBE, "LAN9420 identified, ID_REV=0x%08X", id_rev);
1507 break;
1508 default:
1509 smsc_warn(PROBE, "LAN9420 NOT identified");
1510 smsc_warn(PROBE, "ID_REV=0x%08X", id_rev);
1511 goto out_free_dmadesc_5;
1512 }
1513
1514 smsc9420_dmac_soft_reset(pd);
1515 smsc9420_eeprom_reload(pd);
1516 smsc9420_check_mac_address(dev);
1517
1518 dev->netdev_ops = &smsc9420_netdev_ops;
1519 dev->ethtool_ops = &smsc9420_ethtool_ops;
1520 dev->irq = pdev->irq;
1521
1522 netif_napi_add(dev, &pd->napi, smsc9420_rx_poll, NAPI_WEIGHT);
1523
1524 result = register_netdev(dev);
1525 if (result) {
1526 smsc_warn(PROBE, "error %i registering device", result);
1527 goto out_free_dmadesc_5;
1528 }
1529
1530 pci_set_drvdata(pdev, dev);
1531
1532 spin_lock_init(&pd->int_lock);
1533 spin_lock_init(&pd->phy_lock);
1534
1535 dev_info(&dev->dev, "MAC Address: %pM\n", dev->dev_addr);
1536
1537 return 0;
1538
1539out_free_dmadesc_5:
1540 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) *
1541 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1542out_free_io_4:
1543 iounmap(virt_addr - LAN9420_CPSR_ENDIAN_OFFSET);
1544out_free_regions_3:
1545 pci_release_regions(pdev);
1546out_free_netdev_2:
1547 free_netdev(dev);
1548out_disable_pci_device_1:
1549 pci_disable_device(pdev);
1550out_0:
1551 return -ENODEV;
1552}
1553
1554static void __devexit smsc9420_remove(struct pci_dev *pdev)
1555{
1556 struct net_device *dev;
1557 struct smsc9420_pdata *pd;
1558
1559 dev = pci_get_drvdata(pdev);
1560 if (!dev)
1561 return;
1562
1563 pci_set_drvdata(pdev, NULL);
1564
1565 pd = netdev_priv(dev);
1566 unregister_netdev(dev);
1567
1568 /* tx_buffers and rx_buffers are freed in stop */
1569 BUG_ON(pd->tx_buffers);
1570 BUG_ON(pd->rx_buffers);
1571
1572 BUG_ON(!pd->tx_ring);
1573 BUG_ON(!pd->rx_ring);
1574
1575 pci_free_consistent(pdev, sizeof(struct smsc9420_dma_desc) *
1576 (RX_RING_SIZE + TX_RING_SIZE), pd->rx_ring, pd->rx_dma_addr);
1577
1578 iounmap(pd->base_addr - LAN9420_CPSR_ENDIAN_OFFSET);
1579 pci_release_regions(pdev);
1580 free_netdev(dev);
1581 pci_disable_device(pdev);
1582}
1583
1584static struct pci_driver smsc9420_driver = {
1585 .name = DRV_NAME,
1586 .id_table = smsc9420_id_table,
1587 .probe = smsc9420_probe,
1588 .remove = __devexit_p(smsc9420_remove),
1589#ifdef CONFIG_PM
1590 .suspend = smsc9420_suspend,
1591 .resume = smsc9420_resume,
1592#endif /* CONFIG_PM */
1593};
1594
1595static int __init smsc9420_init_module(void)
1596{
1597 smsc_debug = netif_msg_init(debug, SMSC_MSG_DEFAULT);
1598
1599 return pci_register_driver(&smsc9420_driver);
1600}
1601
1602static void __exit smsc9420_exit_module(void)
1603{
1604 pci_unregister_driver(&smsc9420_driver);
1605}
1606
1607module_init(smsc9420_init_module);
1608module_exit(smsc9420_exit_module);
diff --git a/drivers/net/smsc9420.h b/drivers/net/smsc9420.h
new file mode 100644
index 000000000000..afda2d249eb6
--- /dev/null
+++ b/drivers/net/smsc9420.h
@@ -0,0 +1,275 @@
1 /***************************************************************************
2 *
3 * Copyright (C) 2007,2008 SMSC
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 *
19 ***************************************************************************
20 */
21
22#ifndef _SMSC9420_H
23#define _SMSC9420_H
24
25#define TX_RING_SIZE (32)
26#define RX_RING_SIZE (128)
27
28/* interrupt deassertion in multiples of 10us */
29#define INT_DEAS_TIME (50)
30
31#define NAPI_WEIGHT (64)
32#define SMSC_BAR (3)
33
34#ifdef __BIG_ENDIAN
35/* Register set is duplicated for BE at an offset of 0x200 */
36#define LAN9420_CPSR_ENDIAN_OFFSET (0x200)
37#else
38#define LAN9420_CPSR_ENDIAN_OFFSET (0)
39#endif
40
41#define PCI_VENDOR_ID_9420 (0x1055)
42#define PCI_DEVICE_ID_9420 (0xE420)
43
44#define LAN_REGISTER_EXTENT (0x400)
45
46#define FLOW_CTRL_TX (1)
47#define FLOW_CTRL_RX (2)
48
49#define PKT_BUF_SZ (VLAN_ETH_FRAME_LEN + NET_IP_ALIGN + 4)
50
51/***********************************************/
52/* DMA Controller Control and Status Registers */
53/***********************************************/
54#define BUS_MODE (0x00)
55#define BUS_MODE_SWR_ (BIT(0))
56#define BUS_MODE_DMA_BURST_LENGTH_1 (BIT(8))
57#define BUS_MODE_DMA_BURST_LENGTH_2 (BIT(9))
58#define BUS_MODE_DMA_BURST_LENGTH_4 (BIT(10))
59#define BUS_MODE_DMA_BURST_LENGTH_8 (BIT(11))
60#define BUS_MODE_DMA_BURST_LENGTH_16 (BIT(12))
61#define BUS_MODE_DMA_BURST_LENGTH_32 (BIT(13))
62#define BUS_MODE_DBO_ (BIT(20))
63
64#define TX_POLL_DEMAND (0x04)
65
66#define RX_POLL_DEMAND (0x08)
67
68#define RX_BASE_ADDR (0x0C)
69
70#define TX_BASE_ADDR (0x10)
71
72#define DMAC_STATUS (0x14)
73#define DMAC_STS_TS_ (7 << 20)
74#define DMAC_STS_RS_ (7 << 17)
75#define DMAC_STS_NIS_ (BIT(16))
76#define DMAC_STS_AIS_ (BIT(15))
77#define DMAC_STS_RWT_ (BIT(9))
78#define DMAC_STS_RXPS_ (BIT(8))
79#define DMAC_STS_RXBU_ (BIT(7))
80#define DMAC_STS_RX_ (BIT(6))
81#define DMAC_STS_TXUNF_ (BIT(5))
82#define DMAC_STS_TXBU_ (BIT(2))
83#define DMAC_STS_TXPS_ (BIT(1))
84#define DMAC_STS_TX_ (BIT(0))
85
86#define DMAC_CONTROL (0x18)
87#define DMAC_CONTROL_TTM_ (BIT(22))
88#define DMAC_CONTROL_SF_ (BIT(21))
89#define DMAC_CONTROL_ST_ (BIT(13))
90#define DMAC_CONTROL_OSF_ (BIT(2))
91#define DMAC_CONTROL_SR_ (BIT(1))
92
93#define DMAC_INTR_ENA (0x1C)
94#define DMAC_INTR_ENA_NIS_ (BIT(16))
95#define DMAC_INTR_ENA_AIS_ (BIT(15))
96#define DMAC_INTR_ENA_RWT_ (BIT(9))
97#define DMAC_INTR_ENA_RXPS_ (BIT(8))
98#define DMAC_INTR_ENA_RXBU_ (BIT(7))
99#define DMAC_INTR_ENA_RX_ (BIT(6))
100#define DMAC_INTR_ENA_TXBU_ (BIT(2))
101#define DMAC_INTR_ENA_TXPS_ (BIT(1))
102#define DMAC_INTR_ENA_TX_ (BIT(0))
103
104#define MISS_FRAME_CNTR (0x20)
105
106#define TX_BUFF_ADDR (0x50)
107
108#define RX_BUFF_ADDR (0x54)
109
110/* Transmit Descriptor Bit Defs */
111#define TDES0_OWN_ (0x80000000)
112#define TDES0_ERROR_SUMMARY_ (0x00008000)
113#define TDES0_LOSS_OF_CARRIER_ (0x00000800)
114#define TDES0_NO_CARRIER_ (0x00000400)
115#define TDES0_LATE_COLLISION_ (0x00000200)
116#define TDES0_EXCESSIVE_COLLISIONS_ (0x00000100)
117#define TDES0_HEARTBEAT_FAIL_ (0x00000080)
118#define TDES0_COLLISION_COUNT_MASK_ (0x00000078)
119#define TDES0_COLLISION_COUNT_SHFT_ (3)
120#define TDES0_EXCESSIVE_DEFERRAL_ (0x00000004)
121#define TDES0_DEFERRED_ (0x00000001)
122
123#define TDES1_IC_ 0x80000000
124#define TDES1_LS_ 0x40000000
125#define TDES1_FS_ 0x20000000
126#define TDES1_TXCSEN_ 0x08000000
127#define TDES1_TER_ (BIT(25))
128#define TDES1_TCH_ 0x01000000
129
130/* Receive Descriptor 0 Bit Defs */
131#define RDES0_OWN_ (0x80000000)
132#define RDES0_FRAME_LENGTH_MASK_ (0x07FF0000)
133#define RDES0_FRAME_LENGTH_SHFT_ (16)
134#define RDES0_ERROR_SUMMARY_ (0x00008000)
135#define RDES0_DESCRIPTOR_ERROR_ (0x00004000)
136#define RDES0_LENGTH_ERROR_ (0x00001000)
137#define RDES0_RUNT_FRAME_ (0x00000800)
138#define RDES0_MULTICAST_FRAME_ (0x00000400)
139#define RDES0_FIRST_DESCRIPTOR_ (0x00000200)
140#define RDES0_LAST_DESCRIPTOR_ (0x00000100)
141#define RDES0_FRAME_TOO_LONG_ (0x00000080)
142#define RDES0_COLLISION_SEEN_ (0x00000040)
143#define RDES0_FRAME_TYPE_ (0x00000020)
144#define RDES0_WATCHDOG_TIMEOUT_ (0x00000010)
145#define RDES0_MII_ERROR_ (0x00000008)
146#define RDES0_DRIBBLING_BIT_ (0x00000004)
147#define RDES0_CRC_ERROR_ (0x00000002)
148
149/* Receive Descriptor 1 Bit Defs */
150#define RDES1_RER_ (0x02000000)
151
152/***********************************************/
153/* MAC Control and Status Registers */
154/***********************************************/
155#define MAC_CR (0x80)
156#define MAC_CR_RXALL_ (0x80000000)
157#define MAC_CR_DIS_RXOWN_ (0x00800000)
158#define MAC_CR_LOOPBK_ (0x00200000)
159#define MAC_CR_FDPX_ (0x00100000)
160#define MAC_CR_MCPAS_ (0x00080000)
161#define MAC_CR_PRMS_ (0x00040000)
162#define MAC_CR_INVFILT_ (0x00020000)
163#define MAC_CR_PASSBAD_ (0x00010000)
164#define MAC_CR_HFILT_ (0x00008000)
165#define MAC_CR_HPFILT_ (0x00002000)
166#define MAC_CR_LCOLL_ (0x00001000)
167#define MAC_CR_DIS_BCAST_ (0x00000800)
168#define MAC_CR_DIS_RTRY_ (0x00000400)
169#define MAC_CR_PADSTR_ (0x00000100)
170#define MAC_CR_BOLMT_MSK (0x000000C0)
171#define MAC_CR_MFCHK_ (0x00000020)
172#define MAC_CR_TXEN_ (0x00000008)
173#define MAC_CR_RXEN_ (0x00000004)
174
175#define ADDRH (0x84)
176
177#define ADDRL (0x88)
178
179#define HASHH (0x8C)
180
181#define HASHL (0x90)
182
183#define MII_ACCESS (0x94)
184#define MII_ACCESS_MII_BUSY_ (0x00000001)
185#define MII_ACCESS_MII_WRITE_ (0x00000002)
186#define MII_ACCESS_MII_READ_ (0x00000000)
187#define MII_ACCESS_INDX_MSK_ (0x000007C0)
188#define MII_ACCESS_PHYADDR_MSK_ (0x0000F8C0)
189#define MII_ACCESS_INDX_SHFT_CNT (6)
190#define MII_ACCESS_PHYADDR_SHFT_CNT (11)
191
192#define MII_DATA (0x98)
193
194#define FLOW (0x9C)
195
196#define VLAN1 (0xA0)
197
198#define VLAN2 (0xA4)
199
200#define WUFF (0xA8)
201
202#define WUCSR (0xAC)
203
204#define COE_CR (0xB0)
205#define TX_COE_EN (0x00010000)
206#define RX_COE_MODE (0x00000002)
207#define RX_COE_EN (0x00000001)
208
209/***********************************************/
210/* System Control and Status Registers */
211/***********************************************/
212#define ID_REV (0xC0)
213
214#define INT_CTL (0xC4)
215#define INT_CTL_SW_INT_EN_ (0x00008000)
216#define INT_CTL_SBERR_INT_EN_ (1 << 12)
217#define INT_CTL_MBERR_INT_EN_ (1 << 13)
218#define INT_CTL_GPT_INT_EN_ (0x00000008)
219#define INT_CTL_PHY_INT_EN_ (0x00000004)
220#define INT_CTL_WAKE_INT_EN_ (0x00000002)
221
222#define INT_STAT (0xC8)
223#define INT_STAT_SW_INT_ (1 << 15)
224#define INT_STAT_MBERR_INT_ (1 << 13)
225#define INT_STAT_SBERR_INT_ (1 << 12)
226#define INT_STAT_GPT_INT_ (1 << 3)
227#define INT_STAT_PHY_INT_ (0x00000004)
228#define INT_STAT_WAKE_INT_ (0x00000002)
229#define INT_STAT_DMAC_INT_ (0x00000001)
230
231#define INT_CFG (0xCC)
232#define INT_CFG_IRQ_INT_ (0x00080000)
233#define INT_CFG_IRQ_EN_ (0x00040000)
234#define INT_CFG_INT_DEAS_CLR_ (0x00000200)
235#define INT_CFG_INT_DEAS_MASK (0x000000FF)
236
237#define GPIO_CFG (0xD0)
238#define GPIO_CFG_LED_3_ (0x40000000)
239#define GPIO_CFG_LED_2_ (0x20000000)
240#define GPIO_CFG_LED_1_ (0x10000000)
241
242#define GPT_CFG (0xD4)
243#define GPT_CFG_TIMER_EN_ (0x20000000)
244
245#define GPT_CNT (0xD8)
246
247#define BUS_CFG (0xDC)
248#define BUS_CFG_RXTXWEIGHT_1_1 (0 << 25)
249#define BUS_CFG_RXTXWEIGHT_2_1 (1 << 25)
250#define BUS_CFG_RXTXWEIGHT_3_1 (2 << 25)
251#define BUS_CFG_RXTXWEIGHT_4_1 (3 << 25)
252
253#define PMT_CTRL (0xE0)
254
255#define FREE_RUN (0xF4)
256
257#define E2P_CMD (0xF8)
258#define E2P_CMD_EPC_BUSY_ (0x80000000)
259#define E2P_CMD_EPC_CMD_ (0x70000000)
260#define E2P_CMD_EPC_CMD_READ_ (0x00000000)
261#define E2P_CMD_EPC_CMD_EWDS_ (0x10000000)
262#define E2P_CMD_EPC_CMD_EWEN_ (0x20000000)
263#define E2P_CMD_EPC_CMD_WRITE_ (0x30000000)
264#define E2P_CMD_EPC_CMD_WRAL_ (0x40000000)
265#define E2P_CMD_EPC_CMD_ERASE_ (0x50000000)
266#define E2P_CMD_EPC_CMD_ERAL_ (0x60000000)
267#define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000)
268#define E2P_CMD_EPC_TIMEOUT_ (0x00000200)
269#define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100)
270#define E2P_CMD_EPC_ADDR_ (0x000000FF)
271
272#define E2P_DATA (0xFC)
273#define E2P_DATA_EEPROM_DATA_ (0x000000FF)
274
275#endif /* _SMSC9420_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 20:50:14 -0500