diff options
author | Matt Carlson <mcarlson@broadcom.com> | 2009-02-25 09:24:28 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-02-27 02:16:35 -0500 |
commit | ffbcfed441b9ba74ce77f215eed6925f6a0b82a3 (patch) | |
tree | 45e7ffd90dcc21f33f2cf4f26f2086419fbf8485 /drivers/net | |
parent | 844b3eed8a9efffa4225c811b989c8ff41691a78 (diff) |
tg3: Eliminate nvram routine forward declarations
This patch moves all NVRAM routines earlier in the source file to
eliminate forward declarations.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Benjamin Li <benli@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r-- | drivers/net/tg3.c | 388 |
1 files changed, 191 insertions, 197 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index ce29097cc759..d32b3efb2175 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -2050,8 +2050,6 @@ static int tg3_setup_phy(struct tg3 *, int); | |||
2050 | 2050 | ||
2051 | static void tg3_write_sig_post_reset(struct tg3 *, int); | 2051 | static void tg3_write_sig_post_reset(struct tg3 *, int); |
2052 | static int tg3_halt_cpu(struct tg3 *, u32); | 2052 | static int tg3_halt_cpu(struct tg3 *, u32); |
2053 | static int tg3_nvram_lock(struct tg3 *); | ||
2054 | static void tg3_nvram_unlock(struct tg3 *); | ||
2055 | 2053 | ||
2056 | static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) | 2054 | static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) |
2057 | { | 2055 | { |
@@ -2108,6 +2106,197 @@ static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) | |||
2108 | } | 2106 | } |
2109 | 2107 | ||
2110 | /* tp->lock is held. */ | 2108 | /* tp->lock is held. */ |
2109 | static int tg3_nvram_lock(struct tg3 *tp) | ||
2110 | { | ||
2111 | if (tp->tg3_flags & TG3_FLAG_NVRAM) { | ||
2112 | int i; | ||
2113 | |||
2114 | if (tp->nvram_lock_cnt == 0) { | ||
2115 | tw32(NVRAM_SWARB, SWARB_REQ_SET1); | ||
2116 | for (i = 0; i < 8000; i++) { | ||
2117 | if (tr32(NVRAM_SWARB) & SWARB_GNT1) | ||
2118 | break; | ||
2119 | udelay(20); | ||
2120 | } | ||
2121 | if (i == 8000) { | ||
2122 | tw32(NVRAM_SWARB, SWARB_REQ_CLR1); | ||
2123 | return -ENODEV; | ||
2124 | } | ||
2125 | } | ||
2126 | tp->nvram_lock_cnt++; | ||
2127 | } | ||
2128 | return 0; | ||
2129 | } | ||
2130 | |||
2131 | /* tp->lock is held. */ | ||
2132 | static void tg3_nvram_unlock(struct tg3 *tp) | ||
2133 | { | ||
2134 | if (tp->tg3_flags & TG3_FLAG_NVRAM) { | ||
2135 | if (tp->nvram_lock_cnt > 0) | ||
2136 | tp->nvram_lock_cnt--; | ||
2137 | if (tp->nvram_lock_cnt == 0) | ||
2138 | tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1); | ||
2139 | } | ||
2140 | } | ||
2141 | |||
2142 | /* tp->lock is held. */ | ||
2143 | static void tg3_enable_nvram_access(struct tg3 *tp) | ||
2144 | { | ||
2145 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | ||
2146 | !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) { | ||
2147 | u32 nvaccess = tr32(NVRAM_ACCESS); | ||
2148 | |||
2149 | tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); | ||
2150 | } | ||
2151 | } | ||
2152 | |||
2153 | /* tp->lock is held. */ | ||
2154 | static void tg3_disable_nvram_access(struct tg3 *tp) | ||
2155 | { | ||
2156 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | ||
2157 | !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) { | ||
2158 | u32 nvaccess = tr32(NVRAM_ACCESS); | ||
2159 | |||
2160 | tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); | ||
2161 | } | ||
2162 | } | ||
2163 | |||
2164 | static int tg3_nvram_read_using_eeprom(struct tg3 *tp, | ||
2165 | u32 offset, u32 *val) | ||
2166 | { | ||
2167 | u32 tmp; | ||
2168 | int i; | ||
2169 | |||
2170 | if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0) | ||
2171 | return -EINVAL; | ||
2172 | |||
2173 | tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | | ||
2174 | EEPROM_ADDR_DEVID_MASK | | ||
2175 | EEPROM_ADDR_READ); | ||
2176 | tw32(GRC_EEPROM_ADDR, | ||
2177 | tmp | | ||
2178 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | ||
2179 | ((offset << EEPROM_ADDR_ADDR_SHIFT) & | ||
2180 | EEPROM_ADDR_ADDR_MASK) | | ||
2181 | EEPROM_ADDR_READ | EEPROM_ADDR_START); | ||
2182 | |||
2183 | for (i = 0; i < 1000; i++) { | ||
2184 | tmp = tr32(GRC_EEPROM_ADDR); | ||
2185 | |||
2186 | if (tmp & EEPROM_ADDR_COMPLETE) | ||
2187 | break; | ||
2188 | msleep(1); | ||
2189 | } | ||
2190 | if (!(tmp & EEPROM_ADDR_COMPLETE)) | ||
2191 | return -EBUSY; | ||
2192 | |||
2193 | *val = tr32(GRC_EEPROM_DATA); | ||
2194 | return 0; | ||
2195 | } | ||
2196 | |||
2197 | #define NVRAM_CMD_TIMEOUT 10000 | ||
2198 | |||
2199 | static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) | ||
2200 | { | ||
2201 | int i; | ||
2202 | |||
2203 | tw32(NVRAM_CMD, nvram_cmd); | ||
2204 | for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) { | ||
2205 | udelay(10); | ||
2206 | if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { | ||
2207 | udelay(10); | ||
2208 | break; | ||
2209 | } | ||
2210 | } | ||
2211 | |||
2212 | if (i == NVRAM_CMD_TIMEOUT) | ||
2213 | return -EBUSY; | ||
2214 | |||
2215 | return 0; | ||
2216 | } | ||
2217 | |||
2218 | static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) | ||
2219 | { | ||
2220 | if ((tp->tg3_flags & TG3_FLAG_NVRAM) && | ||
2221 | (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && | ||
2222 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && | ||
2223 | !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && | ||
2224 | (tp->nvram_jedecnum == JEDEC_ATMEL)) | ||
2225 | |||
2226 | addr = ((addr / tp->nvram_pagesize) << | ||
2227 | ATMEL_AT45DB0X1B_PAGE_POS) + | ||
2228 | (addr % tp->nvram_pagesize); | ||
2229 | |||
2230 | return addr; | ||
2231 | } | ||
2232 | |||
2233 | static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) | ||
2234 | { | ||
2235 | if ((tp->tg3_flags & TG3_FLAG_NVRAM) && | ||
2236 | (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && | ||
2237 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && | ||
2238 | !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && | ||
2239 | (tp->nvram_jedecnum == JEDEC_ATMEL)) | ||
2240 | |||
2241 | addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) * | ||
2242 | tp->nvram_pagesize) + | ||
2243 | (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); | ||
2244 | |||
2245 | return addr; | ||
2246 | } | ||
2247 | |||
2248 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) | ||
2249 | { | ||
2250 | int ret; | ||
2251 | |||
2252 | if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) | ||
2253 | return tg3_nvram_read_using_eeprom(tp, offset, val); | ||
2254 | |||
2255 | offset = tg3_nvram_phys_addr(tp, offset); | ||
2256 | |||
2257 | if (offset > NVRAM_ADDR_MSK) | ||
2258 | return -EINVAL; | ||
2259 | |||
2260 | ret = tg3_nvram_lock(tp); | ||
2261 | if (ret) | ||
2262 | return ret; | ||
2263 | |||
2264 | tg3_enable_nvram_access(tp); | ||
2265 | |||
2266 | tw32(NVRAM_ADDR, offset); | ||
2267 | ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | | ||
2268 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); | ||
2269 | |||
2270 | if (ret == 0) | ||
2271 | *val = swab32(tr32(NVRAM_RDDATA)); | ||
2272 | |||
2273 | tg3_disable_nvram_access(tp); | ||
2274 | |||
2275 | tg3_nvram_unlock(tp); | ||
2276 | |||
2277 | return ret; | ||
2278 | } | ||
2279 | |||
2280 | static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val) | ||
2281 | { | ||
2282 | int err; | ||
2283 | u32 tmp; | ||
2284 | |||
2285 | err = tg3_nvram_read(tp, offset, &tmp); | ||
2286 | *val = swab32(tmp); | ||
2287 | return err; | ||
2288 | } | ||
2289 | |||
2290 | static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val) | ||
2291 | { | ||
2292 | u32 v; | ||
2293 | int res = tg3_nvram_read(tp, offset, &v); | ||
2294 | if (!res) | ||
2295 | *val = cpu_to_le32(v); | ||
2296 | return res; | ||
2297 | } | ||
2298 | |||
2299 | /* tp->lock is held. */ | ||
2111 | static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1) | 2300 | static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1) |
2112 | { | 2301 | { |
2113 | u32 addr_high, addr_low; | 2302 | u32 addr_high, addr_low; |
@@ -5638,62 +5827,6 @@ static int tg3_abort_hw(struct tg3 *tp, int silent) | |||
5638 | return err; | 5827 | return err; |
5639 | } | 5828 | } |
5640 | 5829 | ||
5641 | /* tp->lock is held. */ | ||
5642 | static int tg3_nvram_lock(struct tg3 *tp) | ||
5643 | { | ||
5644 | if (tp->tg3_flags & TG3_FLAG_NVRAM) { | ||
5645 | int i; | ||
5646 | |||
5647 | if (tp->nvram_lock_cnt == 0) { | ||
5648 | tw32(NVRAM_SWARB, SWARB_REQ_SET1); | ||
5649 | for (i = 0; i < 8000; i++) { | ||
5650 | if (tr32(NVRAM_SWARB) & SWARB_GNT1) | ||
5651 | break; | ||
5652 | udelay(20); | ||
5653 | } | ||
5654 | if (i == 8000) { | ||
5655 | tw32(NVRAM_SWARB, SWARB_REQ_CLR1); | ||
5656 | return -ENODEV; | ||
5657 | } | ||
5658 | } | ||
5659 | tp->nvram_lock_cnt++; | ||
5660 | } | ||
5661 | return 0; | ||
5662 | } | ||
5663 | |||
5664 | /* tp->lock is held. */ | ||
5665 | static void tg3_nvram_unlock(struct tg3 *tp) | ||
5666 | { | ||
5667 | if (tp->tg3_flags & TG3_FLAG_NVRAM) { | ||
5668 | if (tp->nvram_lock_cnt > 0) | ||
5669 | tp->nvram_lock_cnt--; | ||
5670 | if (tp->nvram_lock_cnt == 0) | ||
5671 | tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1); | ||
5672 | } | ||
5673 | } | ||
5674 | |||
5675 | /* tp->lock is held. */ | ||
5676 | static void tg3_enable_nvram_access(struct tg3 *tp) | ||
5677 | { | ||
5678 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | ||
5679 | !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) { | ||
5680 | u32 nvaccess = tr32(NVRAM_ACCESS); | ||
5681 | |||
5682 | tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); | ||
5683 | } | ||
5684 | } | ||
5685 | |||
5686 | /* tp->lock is held. */ | ||
5687 | static void tg3_disable_nvram_access(struct tg3 *tp) | ||
5688 | { | ||
5689 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | ||
5690 | !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) { | ||
5691 | u32 nvaccess = tr32(NVRAM_ACCESS); | ||
5692 | |||
5693 | tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); | ||
5694 | } | ||
5695 | } | ||
5696 | |||
5697 | static void tg3_ape_send_event(struct tg3 *tp, u32 event) | 5830 | static void tg3_ape_send_event(struct tg3 *tp, u32 event) |
5698 | { | 5831 | { |
5699 | int i; | 5832 | int i; |
@@ -8394,10 +8527,6 @@ static int tg3_get_eeprom_len(struct net_device *dev) | |||
8394 | return tp->nvram_size; | 8527 | return tp->nvram_size; |
8395 | } | 8528 | } |
8396 | 8529 | ||
8397 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val); | ||
8398 | static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val); | ||
8399 | static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val); | ||
8400 | |||
8401 | static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) | 8530 | static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) |
8402 | { | 8531 | { |
8403 | struct tg3 *tp = netdev_priv(dev); | 8532 | struct tg3 *tp = netdev_priv(dev); |
@@ -10511,141 +10640,6 @@ static void __devinit tg3_nvram_init(struct tg3 *tp) | |||
10511 | } | 10640 | } |
10512 | } | 10641 | } |
10513 | 10642 | ||
10514 | static int tg3_nvram_read_using_eeprom(struct tg3 *tp, | ||
10515 | u32 offset, u32 *val) | ||
10516 | { | ||
10517 | u32 tmp; | ||
10518 | int i; | ||
10519 | |||
10520 | if (offset > EEPROM_ADDR_ADDR_MASK || | ||
10521 | (offset % 4) != 0) | ||
10522 | return -EINVAL; | ||
10523 | |||
10524 | tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | | ||
10525 | EEPROM_ADDR_DEVID_MASK | | ||
10526 | EEPROM_ADDR_READ); | ||
10527 | tw32(GRC_EEPROM_ADDR, | ||
10528 | tmp | | ||
10529 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | ||
10530 | ((offset << EEPROM_ADDR_ADDR_SHIFT) & | ||
10531 | EEPROM_ADDR_ADDR_MASK) | | ||
10532 | EEPROM_ADDR_READ | EEPROM_ADDR_START); | ||
10533 | |||
10534 | for (i = 0; i < 1000; i++) { | ||
10535 | tmp = tr32(GRC_EEPROM_ADDR); | ||
10536 | |||
10537 | if (tmp & EEPROM_ADDR_COMPLETE) | ||
10538 | break; | ||
10539 | msleep(1); | ||
10540 | } | ||
10541 | if (!(tmp & EEPROM_ADDR_COMPLETE)) | ||
10542 | return -EBUSY; | ||
10543 | |||
10544 | *val = tr32(GRC_EEPROM_DATA); | ||
10545 | return 0; | ||
10546 | } | ||
10547 | |||
10548 | #define NVRAM_CMD_TIMEOUT 10000 | ||
10549 | |||
10550 | static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) | ||
10551 | { | ||
10552 | int i; | ||
10553 | |||
10554 | tw32(NVRAM_CMD, nvram_cmd); | ||
10555 | for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) { | ||
10556 | udelay(10); | ||
10557 | if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { | ||
10558 | udelay(10); | ||
10559 | break; | ||
10560 | } | ||
10561 | } | ||
10562 | if (i == NVRAM_CMD_TIMEOUT) { | ||
10563 | return -EBUSY; | ||
10564 | } | ||
10565 | return 0; | ||
10566 | } | ||
10567 | |||
10568 | static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) | ||
10569 | { | ||
10570 | if ((tp->tg3_flags & TG3_FLAG_NVRAM) && | ||
10571 | (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && | ||
10572 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && | ||
10573 | !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && | ||
10574 | (tp->nvram_jedecnum == JEDEC_ATMEL)) | ||
10575 | |||
10576 | addr = ((addr / tp->nvram_pagesize) << | ||
10577 | ATMEL_AT45DB0X1B_PAGE_POS) + | ||
10578 | (addr % tp->nvram_pagesize); | ||
10579 | |||
10580 | return addr; | ||
10581 | } | ||
10582 | |||
10583 | static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) | ||
10584 | { | ||
10585 | if ((tp->tg3_flags & TG3_FLAG_NVRAM) && | ||
10586 | (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && | ||
10587 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && | ||
10588 | !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && | ||
10589 | (tp->nvram_jedecnum == JEDEC_ATMEL)) | ||
10590 | |||
10591 | addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) * | ||
10592 | tp->nvram_pagesize) + | ||
10593 | (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); | ||
10594 | |||
10595 | return addr; | ||
10596 | } | ||
10597 | |||
10598 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) | ||
10599 | { | ||
10600 | int ret; | ||
10601 | |||
10602 | if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) | ||
10603 | return tg3_nvram_read_using_eeprom(tp, offset, val); | ||
10604 | |||
10605 | offset = tg3_nvram_phys_addr(tp, offset); | ||
10606 | |||
10607 | if (offset > NVRAM_ADDR_MSK) | ||
10608 | return -EINVAL; | ||
10609 | |||
10610 | ret = tg3_nvram_lock(tp); | ||
10611 | if (ret) | ||
10612 | return ret; | ||
10613 | |||
10614 | tg3_enable_nvram_access(tp); | ||
10615 | |||
10616 | tw32(NVRAM_ADDR, offset); | ||
10617 | ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | | ||
10618 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); | ||
10619 | |||
10620 | if (ret == 0) | ||
10621 | *val = swab32(tr32(NVRAM_RDDATA)); | ||
10622 | |||
10623 | tg3_disable_nvram_access(tp); | ||
10624 | |||
10625 | tg3_nvram_unlock(tp); | ||
10626 | |||
10627 | return ret; | ||
10628 | } | ||
10629 | |||
10630 | static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val) | ||
10631 | { | ||
10632 | u32 v; | ||
10633 | int res = tg3_nvram_read(tp, offset, &v); | ||
10634 | if (!res) | ||
10635 | *val = cpu_to_le32(v); | ||
10636 | return res; | ||
10637 | } | ||
10638 | |||
10639 | static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val) | ||
10640 | { | ||
10641 | int err; | ||
10642 | u32 tmp; | ||
10643 | |||
10644 | err = tg3_nvram_read(tp, offset, &tmp); | ||
10645 | *val = swab32(tmp); | ||
10646 | return err; | ||
10647 | } | ||
10648 | |||
10649 | static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, | 10643 | static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, |
10650 | u32 offset, u32 len, u8 *buf) | 10644 | u32 offset, u32 len, u8 *buf) |
10651 | { | 10645 | { |