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authorJoe Perches <joe@perches.com>2008-03-07 17:21:16 -0500
committerJohn W. Linville <linville@tuxdriver.com>2008-03-13 16:02:32 -0400
commite9010e2fdfe68360da374e31f7008a6d9935c783 (patch)
tree3b182e515d6ff7a9ff6823460324f96399eff347 /drivers/net
parent52933d815bff78605a490582a2212a8131482e00 (diff)
drivers/net/wireless/ath5k - convert == (true|false) to simple logical tests
(test == true) is not nice. Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/wireless/ath5k/hw.c36
-rw-r--r--drivers/net/wireless/ath5k/phy.c10
2 files changed, 23 insertions, 23 deletions
diff --git a/drivers/net/wireless/ath5k/hw.c b/drivers/net/wireless/ath5k/hw.c
index a4e312d4226e..677600b302d9 100644
--- a/drivers/net/wireless/ath5k/hw.c
+++ b/drivers/net/wireless/ath5k/hw.c
@@ -1,4 +1,4 @@
1 /* 1/*
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com> 3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007 Matthew W. S. Bell <mentor@madwifi.org> 4 * Copyright (c) 2007 Matthew W. S. Bell <mentor@madwifi.org>
@@ -85,12 +85,12 @@ static int ath5k_hw_disable_pspoll(struct ath5k_hw *);
85 85
86static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo) 86static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
87{ 87{
88 return turbo == true ? (usec * 80) : (usec * 40); 88 return turbo ? (usec * 80) : (usec * 40);
89} 89}
90 90
91static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo) 91static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo)
92{ 92{
93 return turbo == true ? (clock / 80) : (clock / 40); 93 return turbo ? (clock / 80) : (clock / 40);
94} 94}
95 95
96/* 96/*
@@ -104,7 +104,7 @@ int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
104 104
105 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) { 105 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
106 data = ath5k_hw_reg_read(ah, reg); 106 data = ath5k_hw_reg_read(ah, reg);
107 if ((is_set == true) && (data & flag)) 107 if (is_set && (data & flag))
108 break; 108 break;
109 else if ((data & flag) == val) 109 else if ((data & flag) == val)
110 break; 110 break;
@@ -617,7 +617,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
617 */ 617 */
618 /*DCU/Antenna selection not available on 5210*/ 618 /*DCU/Antenna selection not available on 5210*/
619 if (ah->ah_version != AR5K_AR5210) { 619 if (ah->ah_version != AR5K_AR5210) {
620 if (change_channel == true) { 620 if (change_channel) {
621 /* Seq number for queue 0 -do this for all queues ? */ 621 /* Seq number for queue 0 -do this for all queues ? */
622 s_seq = ath5k_hw_reg_read(ah, 622 s_seq = ath5k_hw_reg_read(ah,
623 AR5K_QUEUE_DFS_SEQNUM(0)); 623 AR5K_QUEUE_DFS_SEQNUM(0));
@@ -631,7 +631,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
631 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR); 631 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
632 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO); 632 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
633 633
634 if (change_channel == true && ah->ah_rf_banks != NULL) 634 if (change_channel && ah->ah_rf_banks != NULL)
635 ath5k_hw_get_rf_gain(ah); 635 ath5k_hw_get_rf_gain(ah);
636 636
637 637
@@ -1122,7 +1122,7 @@ int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
1122 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA; 1122 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
1123 /* fallthrough */ 1123 /* fallthrough */
1124 case AR5K_PM_NETWORK_SLEEP: 1124 case AR5K_PM_NETWORK_SLEEP:
1125 if (set_chip == true) 1125 if (set_chip)
1126 ath5k_hw_reg_write(ah, 1126 ath5k_hw_reg_write(ah,
1127 AR5K_SLEEP_CTL_SLE | sleep_duration, 1127 AR5K_SLEEP_CTL_SLE | sleep_duration,
1128 AR5K_SLEEP_CTL); 1128 AR5K_SLEEP_CTL);
@@ -1131,7 +1131,7 @@ int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
1131 break; 1131 break;
1132 1132
1133 case AR5K_PM_FULL_SLEEP: 1133 case AR5K_PM_FULL_SLEEP:
1134 if (set_chip == true) 1134 if (set_chip)
1135 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP, 1135 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
1136 AR5K_SLEEP_CTL); 1136 AR5K_SLEEP_CTL);
1137 1137
@@ -1139,7 +1139,7 @@ int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
1139 break; 1139 break;
1140 1140
1141 case AR5K_PM_AWAKE: 1141 case AR5K_PM_AWAKE:
1142 if (set_chip == false) 1142 if (!set_chip)
1143 goto commit; 1143 goto commit;
1144 1144
1145 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_WAKE, 1145 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_WAKE,
@@ -1446,7 +1446,7 @@ int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase)
1446 trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG), 1446 trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG),
1447 AR5K_TXCFG_TXFULL); 1447 AR5K_TXCFG_TXFULL);
1448 1448
1449 if (increase == false) { 1449 if (!increase) {
1450 if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) 1450 if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES)
1451 goto done; 1451 goto done;
1452 } else 1452 } else
@@ -3205,19 +3205,19 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
3205 return 0; 3205 return 0;
3206 3206
3207 /* Set Slot time */ 3207 /* Set Slot time */
3208 ath5k_hw_reg_write(ah, ah->ah_turbo == true ? 3208 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3209 AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME, 3209 AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME,
3210 AR5K_SLOT_TIME); 3210 AR5K_SLOT_TIME);
3211 /* Set ACK_CTS timeout */ 3211 /* Set ACK_CTS timeout */
3212 ath5k_hw_reg_write(ah, ah->ah_turbo == true ? 3212 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3213 AR5K_INIT_ACK_CTS_TIMEOUT_TURBO : 3213 AR5K_INIT_ACK_CTS_TIMEOUT_TURBO :
3214 AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME); 3214 AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME);
3215 /* Set Transmit Latency */ 3215 /* Set Transmit Latency */
3216 ath5k_hw_reg_write(ah, ah->ah_turbo == true ? 3216 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3217 AR5K_INIT_TRANSMIT_LATENCY_TURBO : 3217 AR5K_INIT_TRANSMIT_LATENCY_TURBO :
3218 AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210); 3218 AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210);
3219 /* Set IFS0 */ 3219 /* Set IFS0 */
3220 if (ah->ah_turbo == true) 3220 if (ah->ah_turbo)
3221 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO + 3221 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO +
3222 (ah->ah_aifs + tq->tqi_aifs) * 3222 (ah->ah_aifs + tq->tqi_aifs) *
3223 AR5K_INIT_SLOT_TIME_TURBO) << 3223 AR5K_INIT_SLOT_TIME_TURBO) <<
@@ -3230,16 +3230,16 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
3230 AR5K_INIT_SIFS, AR5K_IFS0); 3230 AR5K_INIT_SIFS, AR5K_IFS0);
3231 3231
3232 /* Set IFS1 */ 3232 /* Set IFS1 */
3233 ath5k_hw_reg_write(ah, ah->ah_turbo == true ? 3233 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3234 AR5K_INIT_PROTO_TIME_CNTRL_TURBO : 3234 AR5K_INIT_PROTO_TIME_CNTRL_TURBO :
3235 AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1); 3235 AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1);
3236 /* Set PHY register 0x9844 (??) */ 3236 /* Set PHY register 0x9844 (??) */
3237 ath5k_hw_reg_write(ah, ah->ah_turbo == true ? 3237 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3238 (ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x38 : 3238 (ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x38 :
3239 (ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x1C, 3239 (ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x1C,
3240 AR5K_PHY(17)); 3240 AR5K_PHY(17));
3241 /* Set Frame Control Register */ 3241 /* Set Frame Control Register */
3242 ath5k_hw_reg_write(ah, ah->ah_turbo == true ? 3242 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3243 (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE | 3243 (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE |
3244 AR5K_PHY_TURBO_SHORT | 0x2020) : 3244 AR5K_PHY_TURBO_SHORT | 0x2020) :
3245 (AR5K_PHY_FRAME_CTL_INI | 0x1020), 3245 (AR5K_PHY_FRAME_CTL_INI | 0x1020),
@@ -3278,7 +3278,7 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
3278 /* 3278 /*
3279 * Calculate and set retry limits 3279 * Calculate and set retry limits
3280 */ 3280 */
3281 if (ah->ah_software_retry == true) { 3281 if (ah->ah_software_retry) {
3282 /* XXX Need to test this */ 3282 /* XXX Need to test this */
3283 retry_lg = ah->ah_limit_tx_retries; 3283 retry_lg = ah->ah_limit_tx_retries;
3284 retry_sh = retry_lg = retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ? 3284 retry_sh = retry_lg = retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ?
diff --git a/drivers/net/wireless/ath5k/phy.c b/drivers/net/wireless/ath5k/phy.c
index ee1dc0fc6ea2..890ecce8bedc 100644
--- a/drivers/net/wireless/ath5k/phy.c
+++ b/drivers/net/wireless/ath5k/phy.c
@@ -981,14 +981,14 @@ static unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits,
981 entry = ((first - 1) / 8) + offset; 981 entry = ((first - 1) / 8) + offset;
982 position = (first - 1) % 8; 982 position = (first - 1) % 8;
983 983
984 if (set == true) 984 if (set)
985 data = ath5k_hw_bitswap(reg, bits); 985 data = ath5k_hw_bitswap(reg, bits);
986 986
987 for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) { 987 for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) {
988 last = (position + left > 8) ? 8 : position + left; 988 last = (position + left > 8) ? 8 : position + left;
989 mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << (col * 8); 989 mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << (col * 8);
990 990
991 if (set == true) { 991 if (set) {
992 rf[entry] &= ~mask; 992 rf[entry] &= ~mask;
993 rf[entry] |= ((data << position) << (col * 8)) & mask; 993 rf[entry] |= ((data << position) << (col * 8)) & mask;
994 data >>= (8 - position); 994 data >>= (8 - position);
@@ -1001,7 +1001,7 @@ static unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits,
1001 left -= 8 - position; 1001 left -= 8 - position;
1002 } 1002 }
1003 1003
1004 data = set == true ? 1 : ath5k_hw_bitswap(data, bits); 1004 data = set ? 1 : ath5k_hw_bitswap(data, bits);
1005 1005
1006 return data; 1006 return data;
1007} 1007}
@@ -1986,7 +1986,7 @@ static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah,
1986 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; 1986 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
1987 ATH5K_TRACE(ah->ah_sc); 1987 ATH5K_TRACE(ah->ah_sc);
1988 1988
1989 if (ah->ah_calibration == false || 1989 if (!ah->ah_calibration ||
1990 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) 1990 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
1991 goto done; 1991 goto done;
1992 1992
@@ -2218,7 +2218,7 @@ ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
2218 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) | 2218 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
2219 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4); 2219 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
2220 2220
2221 if (ah->ah_txpower.txp_tpc == true) 2221 if (ah->ah_txpower.txp_tpc)
2222 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | 2222 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
2223 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 2223 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
2224 else 2224 else