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authorMohamed Abbas <mohamed.abbas@intel.com>2009-05-22 14:01:47 -0400
committerJohn W. Linville <linville@tuxdriver.com>2009-05-22 14:06:04 -0400
commita8b50a0a966d7ac313f624c6ab4996231a5fe25a (patch)
tree8c000ee1d429f1e639fde9613cb48b268aee1ff6 /drivers/net
parent0848e297c2107dbc12a91a1709c879c73bd188d8 (diff)
iwlcore: register locks
Add new lock to be used when accessing some registers. Also move the register lock and iwl_grab_nic_access inside the function for register access. This will prevent from forgetting to hold locks and nic access in the right way and make code easier to maintain. We over use the priv->lock spin lock and I guess we need to add new one for Tx queue after that we might need to change most of these lock to BH and just keep priv->lock as irq type. Signed-off-by: Mohamed Abbas <mohamed.abbas@intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945.c144
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-4965.c60
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-5000.c54
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn.c56
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-core.c34
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-debugfs.c2
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-dev.h1
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-eeprom.c2
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-io.h253
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-rx.c31
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-tx.c17
-rw-r--r--drivers/net/wireless/iwlwifi/iwl3945-base.c73
12 files changed, 203 insertions, 524 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.c b/drivers/net/wireless/iwlwifi/iwl-3945.c
index 5b0c6e5bda92..8bed0445ff5d 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945.c
+++ b/drivers/net/wireless/iwlwifi/iwl-3945.c
@@ -98,7 +98,6 @@ const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
98 * ... and set IWL_EVT_DISABLE to 1. */ 98 * ... and set IWL_EVT_DISABLE to 1. */
99void iwl3945_disable_events(struct iwl_priv *priv) 99void iwl3945_disable_events(struct iwl_priv *priv)
100{ 100{
101 int ret;
102 int i; 101 int i;
103 u32 base; /* SRAM address of event log header */ 102 u32 base; /* SRAM address of event log header */
104 u32 disable_ptr; /* SRAM address of event-disable bitmap array */ 103 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
@@ -159,26 +158,17 @@ void iwl3945_disable_events(struct iwl_priv *priv)
159 return; 158 return;
160 } 159 }
161 160
162 ret = iwl_grab_nic_access(priv);
163 if (ret) {
164 IWL_WARN(priv, "Can not read from adapter at this time.\n");
165 return;
166 }
167
168 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32))); 161 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
169 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32))); 162 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
170 iwl_release_nic_access(priv);
171 163
172 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) { 164 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
173 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n", 165 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
174 disable_ptr); 166 disable_ptr);
175 ret = iwl_grab_nic_access(priv);
176 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++) 167 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
177 iwl_write_targ_mem(priv, 168 iwl_write_targ_mem(priv,
178 disable_ptr + (i * sizeof(u32)), 169 disable_ptr + (i * sizeof(u32)),
179 evt_disable[i]); 170 evt_disable[i]);
180 171
181 iwl_release_nic_access(priv);
182 } else { 172 } else {
183 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n"); 173 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
184 IWL_DEBUG_INFO(priv, " by writing \"1\"s into disable bitmap\n"); 174 IWL_DEBUG_INFO(priv, " by writing \"1\"s into disable bitmap\n");
@@ -908,55 +898,30 @@ u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
908 898
909static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src) 899static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
910{ 900{
911 int ret;
912 unsigned long flags;
913
914 spin_lock_irqsave(&priv->lock, flags);
915 ret = iwl_grab_nic_access(priv);
916 if (ret) {
917 spin_unlock_irqrestore(&priv->lock, flags);
918 return ret;
919 }
920
921 if (src == IWL_PWR_SRC_VAUX) { 901 if (src == IWL_PWR_SRC_VAUX) {
922 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) { 902 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
923 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 903 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
924 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 904 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
925 ~APMG_PS_CTRL_MSK_PWR_SRC); 905 ~APMG_PS_CTRL_MSK_PWR_SRC);
926 iwl_release_nic_access(priv);
927 906
928 iwl_poll_bit(priv, CSR_GPIO_IN, 907 iwl_poll_bit(priv, CSR_GPIO_IN,
929 CSR_GPIO_IN_VAL_VAUX_PWR_SRC, 908 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
930 CSR_GPIO_IN_BIT_AUX_POWER, 5000); 909 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
931 } else {
932 iwl_release_nic_access(priv);
933 } 910 }
934 } else { 911 } else {
935 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 912 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
936 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 913 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
937 ~APMG_PS_CTRL_MSK_PWR_SRC); 914 ~APMG_PS_CTRL_MSK_PWR_SRC);
938 915
939 iwl_release_nic_access(priv);
940 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC, 916 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
941 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */ 917 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
942 } 918 }
943 spin_unlock_irqrestore(&priv->lock, flags);
944 919
945 return ret; 920 return 0;
946} 921}
947 922
948static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq) 923static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
949{ 924{
950 int rc;
951 unsigned long flags;
952
953 spin_lock_irqsave(&priv->lock, flags);
954 rc = iwl_grab_nic_access(priv);
955 if (rc) {
956 spin_unlock_irqrestore(&priv->lock, flags);
957 return rc;
958 }
959
960 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr); 925 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
961 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma); 926 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
962 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0); 927 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
@@ -973,23 +938,11 @@ static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
973 /* fake read to flush all prev I/O */ 938 /* fake read to flush all prev I/O */
974 iwl_read_direct32(priv, FH39_RSSR_CTRL); 939 iwl_read_direct32(priv, FH39_RSSR_CTRL);
975 940
976 iwl_release_nic_access(priv);
977 spin_unlock_irqrestore(&priv->lock, flags);
978
979 return 0; 941 return 0;
980} 942}
981 943
982static int iwl3945_tx_reset(struct iwl_priv *priv) 944static int iwl3945_tx_reset(struct iwl_priv *priv)
983{ 945{
984 int rc;
985 unsigned long flags;
986
987 spin_lock_irqsave(&priv->lock, flags);
988 rc = iwl_grab_nic_access(priv);
989 if (rc) {
990 spin_unlock_irqrestore(&priv->lock, flags);
991 return rc;
992 }
993 946
994 /* bypass mode */ 947 /* bypass mode */
995 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2); 948 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
@@ -1017,8 +970,6 @@ static int iwl3945_tx_reset(struct iwl_priv *priv)
1017 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH | 970 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1018 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH); 971 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
1019 972
1020 iwl_release_nic_access(priv);
1021 spin_unlock_irqrestore(&priv->lock, flags);
1022 973
1023 return 0; 974 return 0;
1024} 975}
@@ -1061,7 +1012,7 @@ static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
1061 1012
1062static int iwl3945_apm_init(struct iwl_priv *priv) 1013static int iwl3945_apm_init(struct iwl_priv *priv)
1063{ 1014{
1064 int ret = 0; 1015 int ret;
1065 1016
1066 iwl_power_initialize(priv); 1017 iwl_power_initialize(priv);
1067 1018
@@ -1083,10 +1034,6 @@ static int iwl3945_apm_init(struct iwl_priv *priv)
1083 goto out; 1034 goto out;
1084 } 1035 }
1085 1036
1086 ret = iwl_grab_nic_access(priv);
1087 if (ret)
1088 goto out;
1089
1090 /* enable DMA */ 1037 /* enable DMA */
1091 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT | 1038 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1092 APMG_CLK_VAL_BSM_CLK_RQT); 1039 APMG_CLK_VAL_BSM_CLK_RQT);
@@ -1097,7 +1044,6 @@ static int iwl3945_apm_init(struct iwl_priv *priv)
1097 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 1044 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1098 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 1045 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1099 1046
1100 iwl_release_nic_access(priv);
1101out: 1047out:
1102 return ret; 1048 return ret;
1103} 1049}
@@ -1196,22 +1142,13 @@ int iwl3945_hw_nic_init(struct iwl_priv *priv)
1196 1142
1197 iwl3945_rx_init(priv, rxq); 1143 iwl3945_rx_init(priv, rxq);
1198 1144
1199 spin_lock_irqsave(&priv->lock, flags);
1200 1145
1201 /* Look at using this instead: 1146 /* Look at using this instead:
1202 rxq->need_update = 1; 1147 rxq->need_update = 1;
1203 iwl_rx_queue_update_write_ptr(priv, rxq); 1148 iwl_rx_queue_update_write_ptr(priv, rxq);
1204 */ 1149 */
1205 1150
1206 rc = iwl_grab_nic_access(priv);
1207 if (rc) {
1208 spin_unlock_irqrestore(&priv->lock, flags);
1209 return rc;
1210 }
1211 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7); 1151 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1212 iwl_release_nic_access(priv);
1213
1214 spin_unlock_irqrestore(&priv->lock, flags);
1215 1152
1216 rc = iwl3945_txq_ctx_reset(priv); 1153 rc = iwl3945_txq_ctx_reset(priv);
1217 if (rc) 1154 if (rc)
@@ -1243,14 +1180,6 @@ void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1243void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv) 1180void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1244{ 1181{
1245 int txq_id; 1182 int txq_id;
1246 unsigned long flags;
1247
1248 spin_lock_irqsave(&priv->lock, flags);
1249 if (iwl_grab_nic_access(priv)) {
1250 spin_unlock_irqrestore(&priv->lock, flags);
1251 iwl3945_hw_txq_ctx_free(priv);
1252 return;
1253 }
1254 1183
1255 /* stop SCD */ 1184 /* stop SCD */
1256 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0); 1185 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
@@ -1263,9 +1192,6 @@ void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1263 1000); 1192 1000);
1264 } 1193 }
1265 1194
1266 iwl_release_nic_access(priv);
1267 spin_unlock_irqrestore(&priv->lock, flags);
1268
1269 iwl3945_hw_txq_ctx_free(priv); 1195 iwl3945_hw_txq_ctx_free(priv);
1270} 1196}
1271 1197
@@ -1310,12 +1236,8 @@ static void iwl3945_apm_stop(struct iwl_priv *priv)
1310 1236
1311static int iwl3945_apm_reset(struct iwl_priv *priv) 1237static int iwl3945_apm_reset(struct iwl_priv *priv)
1312{ 1238{
1313 int rc;
1314 unsigned long flags;
1315
1316 iwl3945_apm_stop_master(priv); 1239 iwl3945_apm_stop_master(priv);
1317 1240
1318 spin_lock_irqsave(&priv->lock, flags);
1319 1241
1320 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 1242 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1321 udelay(10); 1243 udelay(10);
@@ -1325,36 +1247,31 @@ static int iwl3945_apm_reset(struct iwl_priv *priv)
1325 iwl_poll_direct_bit(priv, CSR_GP_CNTRL, 1247 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1326 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 1248 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1327 1249
1328 rc = iwl_grab_nic_access(priv); 1250 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
1329 if (!rc) { 1251 APMG_CLK_VAL_BSM_CLK_RQT);
1330 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
1331 APMG_CLK_VAL_BSM_CLK_RQT);
1332 1252
1333 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0); 1253 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1334 iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 1254 iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
1335 0xFFFFFFFF); 1255 0xFFFFFFFF);
1336 1256
1337 /* enable DMA */ 1257 /* enable DMA */
1338 iwl_write_prph(priv, APMG_CLK_EN_REG, 1258 iwl_write_prph(priv, APMG_CLK_EN_REG,
1339 APMG_CLK_VAL_DMA_CLK_RQT | 1259 APMG_CLK_VAL_DMA_CLK_RQT |
1340 APMG_CLK_VAL_BSM_CLK_RQT); 1260 APMG_CLK_VAL_BSM_CLK_RQT);
1341 udelay(10); 1261 udelay(10);
1342 1262
1343 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, 1263 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
1344 APMG_PS_CTRL_VAL_RESET_REQ); 1264 APMG_PS_CTRL_VAL_RESET_REQ);
1345 udelay(5); 1265 udelay(5);
1346 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, 1266 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
1347 APMG_PS_CTRL_VAL_RESET_REQ); 1267 APMG_PS_CTRL_VAL_RESET_REQ);
1348 iwl_release_nic_access(priv);
1349 }
1350 1268
1351 /* Clear the 'host command active' bit... */ 1269 /* Clear the 'host command active' bit... */
1352 clear_bit(STATUS_HCMD_ACTIVE, &priv->status); 1270 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1353 1271
1354 wake_up_interruptible(&priv->wait_command_queue); 1272 wake_up_interruptible(&priv->wait_command_queue);
1355 spin_unlock_irqrestore(&priv->lock, flags);
1356 1273
1357 return rc; 1274 return 0;
1358} 1275}
1359 1276
1360/** 1277/**
@@ -2500,14 +2417,6 @@ int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2500int iwl3945_hw_rxq_stop(struct iwl_priv *priv) 2417int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2501{ 2418{
2502 int rc; 2419 int rc;
2503 unsigned long flags;
2504
2505 spin_lock_irqsave(&priv->lock, flags);
2506 rc = iwl_grab_nic_access(priv);
2507 if (rc) {
2508 spin_unlock_irqrestore(&priv->lock, flags);
2509 return rc;
2510 }
2511 2420
2512 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0); 2421 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2513 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS, 2422 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
@@ -2515,28 +2424,17 @@ int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2515 if (rc < 0) 2424 if (rc < 0)
2516 IWL_ERR(priv, "Can't stop Rx DMA.\n"); 2425 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2517 2426
2518 iwl_release_nic_access(priv);
2519 spin_unlock_irqrestore(&priv->lock, flags);
2520
2521 return 0; 2427 return 0;
2522} 2428}
2523 2429
2524int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq) 2430int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2525{ 2431{
2526 int rc;
2527 unsigned long flags;
2528 int txq_id = txq->q.id; 2432 int txq_id = txq->q.id;
2529 2433
2530 struct iwl3945_shared *shared_data = priv->shared_virt; 2434 struct iwl3945_shared *shared_data = priv->shared_virt;
2531 2435
2532 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr); 2436 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2533 2437
2534 spin_lock_irqsave(&priv->lock, flags);
2535 rc = iwl_grab_nic_access(priv);
2536 if (rc) {
2537 spin_unlock_irqrestore(&priv->lock, flags);
2538 return rc;
2539 }
2540 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0); 2438 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2541 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0); 2439 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2542 2440
@@ -2546,11 +2444,9 @@ int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2546 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD | 2444 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2547 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL | 2445 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2548 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE); 2446 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2549 iwl_release_nic_access(priv);
2550 2447
2551 /* fake read to flush all prev. writes */ 2448 /* fake read to flush all prev. writes */
2552 iwl_read32(priv, FH39_TSSR_CBB_BASE); 2449 iwl_read32(priv, FH39_TSSR_CBB_BASE);
2553 spin_unlock_irqrestore(&priv->lock, flags);
2554 2450
2555 return 0; 2451 return 0;
2556} 2452}
@@ -2858,10 +2754,6 @@ static int iwl3945_load_bsm(struct iwl_priv *priv)
2858 inst_len = priv->ucode_init.len; 2754 inst_len = priv->ucode_init.len;
2859 data_len = priv->ucode_init_data.len; 2755 data_len = priv->ucode_init_data.len;
2860 2756
2861 rc = iwl_grab_nic_access(priv);
2862 if (rc)
2863 return rc;
2864
2865 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); 2757 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2866 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); 2758 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2867 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len); 2759 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
@@ -2875,10 +2767,8 @@ static int iwl3945_load_bsm(struct iwl_priv *priv)
2875 le32_to_cpu(*image)); 2767 le32_to_cpu(*image));
2876 2768
2877 rc = iwl3945_verify_bsm(priv); 2769 rc = iwl3945_verify_bsm(priv);
2878 if (rc) { 2770 if (rc)
2879 iwl_release_nic_access(priv);
2880 return rc; 2771 return rc;
2881 }
2882 2772
2883 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */ 2773 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2884 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0); 2774 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
@@ -2910,8 +2800,6 @@ static int iwl3945_load_bsm(struct iwl_priv *priv)
2910 iwl_write_prph(priv, BSM_WR_CTRL_REG, 2800 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2911 BSM_WR_CTRL_REG_BIT_START_EN); 2801 BSM_WR_CTRL_REG_BIT_START_EN);
2912 2802
2913 iwl_release_nic_access(priv);
2914
2915 return 0; 2803 return 0;
2916} 2804}
2917 2805
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965.c b/drivers/net/wireless/iwlwifi/iwl-4965.c
index 97131e63397e..4be7bd29ef6d 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965.c
+++ b/drivers/net/wireless/iwlwifi/iwl-4965.c
@@ -163,10 +163,6 @@ static int iwl4965_load_bsm(struct iwl_priv *priv)
163 inst_len = priv->ucode_init.len; 163 inst_len = priv->ucode_init.len;
164 data_len = priv->ucode_init_data.len; 164 data_len = priv->ucode_init_data.len;
165 165
166 ret = iwl_grab_nic_access(priv);
167 if (ret)
168 return ret;
169
170 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); 166 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
171 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); 167 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
172 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len); 168 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
@@ -179,10 +175,8 @@ static int iwl4965_load_bsm(struct iwl_priv *priv)
179 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image)); 175 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
180 176
181 ret = iwl4965_verify_bsm(priv); 177 ret = iwl4965_verify_bsm(priv);
182 if (ret) { 178 if (ret)
183 iwl_release_nic_access(priv);
184 return ret; 179 return ret;
185 }
186 180
187 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */ 181 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
188 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0); 182 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
@@ -211,7 +205,6 @@ static int iwl4965_load_bsm(struct iwl_priv *priv)
211 * (e.g. when powering back up after power-save shutdown) */ 205 * (e.g. when powering back up after power-save shutdown) */
212 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN); 206 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
213 207
214 iwl_release_nic_access(priv);
215 208
216 return 0; 209 return 0;
217} 210}
@@ -229,20 +222,12 @@ static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
229{ 222{
230 dma_addr_t pinst; 223 dma_addr_t pinst;
231 dma_addr_t pdata; 224 dma_addr_t pdata;
232 unsigned long flags;
233 int ret = 0; 225 int ret = 0;
234 226
235 /* bits 35:4 for 4965 */ 227 /* bits 35:4 for 4965 */
236 pinst = priv->ucode_code.p_addr >> 4; 228 pinst = priv->ucode_code.p_addr >> 4;
237 pdata = priv->ucode_data_backup.p_addr >> 4; 229 pdata = priv->ucode_data_backup.p_addr >> 4;
238 230
239 spin_lock_irqsave(&priv->lock, flags);
240 ret = iwl_grab_nic_access(priv);
241 if (ret) {
242 spin_unlock_irqrestore(&priv->lock, flags);
243 return ret;
244 }
245
246 /* Tell bootstrap uCode where to find image to load */ 231 /* Tell bootstrap uCode where to find image to load */
247 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); 232 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
248 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); 233 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
@@ -253,10 +238,6 @@ static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
253 * that all new ptr/size info is in place */ 238 * that all new ptr/size info is in place */
254 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, 239 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
255 priv->ucode_code.len | BSM_DRAM_INST_LOAD); 240 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
256 iwl_release_nic_access(priv);
257
258 spin_unlock_irqrestore(&priv->lock, flags);
259
260 IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n"); 241 IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
261 242
262 return ret; 243 return ret;
@@ -358,10 +339,6 @@ static int iwl4965_apm_init(struct iwl_priv *priv)
358 goto out; 339 goto out;
359 } 340 }
360 341
361 ret = iwl_grab_nic_access(priv);
362 if (ret)
363 goto out;
364
365 /* enable DMA */ 342 /* enable DMA */
366 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT | 343 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
367 APMG_CLK_VAL_BSM_CLK_RQT); 344 APMG_CLK_VAL_BSM_CLK_RQT);
@@ -372,7 +349,6 @@ static int iwl4965_apm_init(struct iwl_priv *priv)
372 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 349 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
373 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 350 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
374 351
375 iwl_release_nic_access(priv);
376out: 352out:
377 return ret; 353 return ret;
378} 354}
@@ -454,11 +430,9 @@ static void iwl4965_apm_stop(struct iwl_priv *priv)
454static int iwl4965_apm_reset(struct iwl_priv *priv) 430static int iwl4965_apm_reset(struct iwl_priv *priv)
455{ 431{
456 int ret = 0; 432 int ret = 0;
457 unsigned long flags;
458 433
459 iwl4965_apm_stop_master(priv); 434 iwl4965_apm_stop_master(priv);
460 435
461 spin_lock_irqsave(&priv->lock, flags);
462 436
463 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 437 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
464 438
@@ -475,9 +449,6 @@ static int iwl4965_apm_reset(struct iwl_priv *priv)
475 449
476 udelay(10); 450 udelay(10);
477 451
478 ret = iwl_grab_nic_access(priv);
479 if (ret)
480 goto out;
481 /* Enable DMA and BSM Clock */ 452 /* Enable DMA and BSM Clock */
482 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT | 453 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT |
483 APMG_CLK_VAL_BSM_CLK_RQT); 454 APMG_CLK_VAL_BSM_CLK_RQT);
@@ -488,14 +459,10 @@ static int iwl4965_apm_reset(struct iwl_priv *priv)
488 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 459 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
489 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 460 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
490 461
491 iwl_release_nic_access(priv);
492
493 clear_bit(STATUS_HCMD_ACTIVE, &priv->status); 462 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
494 wake_up_interruptible(&priv->wait_command_queue); 463 wake_up_interruptible(&priv->wait_command_queue);
495 464
496out: 465out:
497 spin_unlock_irqrestore(&priv->lock, flags);
498
499 return ret; 466 return ret;
500} 467}
501 468
@@ -681,18 +648,11 @@ static int iwl4965_alive_notify(struct iwl_priv *priv)
681{ 648{
682 u32 a; 649 u32 a;
683 unsigned long flags; 650 unsigned long flags;
684 int ret;
685 int i, chan; 651 int i, chan;
686 u32 reg_val; 652 u32 reg_val;
687 653
688 spin_lock_irqsave(&priv->lock, flags); 654 spin_lock_irqsave(&priv->lock, flags);
689 655
690 ret = iwl_grab_nic_access(priv);
691 if (ret) {
692 spin_unlock_irqrestore(&priv->lock, flags);
693 return ret;
694 }
695
696 /* Clear 4965's internal Tx Scheduler data base */ 656 /* Clear 4965's internal Tx Scheduler data base */
697 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR); 657 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
698 a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET; 658 a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
@@ -759,10 +719,9 @@ static int iwl4965_alive_notify(struct iwl_priv *priv)
759 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0); 719 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
760 } 720 }
761 721
762 iwl_release_nic_access(priv);
763 spin_unlock_irqrestore(&priv->lock, flags); 722 spin_unlock_irqrestore(&priv->lock, flags);
764 723
765 return ret; 724 return 0;
766} 725}
767 726
768static struct iwl_sensitivity_ranges iwl4965_sensitivity = { 727static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
@@ -1840,8 +1799,6 @@ static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
1840static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, 1799static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1841 u16 ssn_idx, u8 tx_fifo) 1800 u16 ssn_idx, u8 tx_fifo)
1842{ 1801{
1843 int ret = 0;
1844
1845 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) || 1802 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1846 (IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES <= txq_id)) { 1803 (IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES <= txq_id)) {
1847 IWL_WARN(priv, 1804 IWL_WARN(priv,
@@ -1851,10 +1808,6 @@ static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1851 return -EINVAL; 1808 return -EINVAL;
1852 } 1809 }
1853 1810
1854 ret = iwl_grab_nic_access(priv);
1855 if (ret)
1856 return ret;
1857
1858 iwl4965_tx_queue_stop_scheduler(priv, txq_id); 1811 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1859 1812
1860 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id)); 1813 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
@@ -1868,8 +1821,6 @@ static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1868 iwl_txq_ctx_deactivate(priv, txq_id); 1821 iwl_txq_ctx_deactivate(priv, txq_id);
1869 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); 1822 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1870 1823
1871 iwl_release_nic_access(priv);
1872
1873 return 0; 1824 return 0;
1874} 1825}
1875 1826
@@ -1911,7 +1862,6 @@ static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1911 int tx_fifo, int sta_id, int tid, u16 ssn_idx) 1862 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
1912{ 1863{
1913 unsigned long flags; 1864 unsigned long flags;
1914 int ret;
1915 u16 ra_tid; 1865 u16 ra_tid;
1916 1866
1917 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) || 1867 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
@@ -1929,11 +1879,6 @@ static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1929 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid); 1879 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
1930 1880
1931 spin_lock_irqsave(&priv->lock, flags); 1881 spin_lock_irqsave(&priv->lock, flags);
1932 ret = iwl_grab_nic_access(priv);
1933 if (ret) {
1934 spin_unlock_irqrestore(&priv->lock, flags);
1935 return ret;
1936 }
1937 1882
1938 /* Stop this Tx queue before configuring it */ 1883 /* Stop this Tx queue before configuring it */
1939 iwl4965_tx_queue_stop_scheduler(priv, txq_id); 1884 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
@@ -1966,7 +1911,6 @@ static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1966 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ 1911 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1967 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); 1912 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1968 1913
1969 iwl_release_nic_access(priv);
1970 spin_unlock_irqrestore(&priv->lock, flags); 1914 spin_unlock_irqrestore(&priv->lock, flags);
1971 1915
1972 return 0; 1916 return 0;
diff --git a/drivers/net/wireless/iwlwifi/iwl-5000.c b/drivers/net/wireless/iwlwifi/iwl-5000.c
index e61b67d0a18b..bec5f8c6841f 100644
--- a/drivers/net/wireless/iwlwifi/iwl-5000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-5000.c
@@ -124,10 +124,6 @@ static int iwl5000_apm_init(struct iwl_priv *priv)
124 return ret; 124 return ret;
125 } 125 }
126 126
127 ret = iwl_grab_nic_access(priv);
128 if (ret)
129 return ret;
130
131 /* enable DMA */ 127 /* enable DMA */
132 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); 128 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
133 129
@@ -137,8 +133,6 @@ static int iwl5000_apm_init(struct iwl_priv *priv)
137 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 133 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
138 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 134 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
139 135
140 iwl_release_nic_access(priv);
141
142 return ret; 136 return ret;
143} 137}
144 138
@@ -165,12 +159,9 @@ static void iwl5000_apm_stop(struct iwl_priv *priv)
165static int iwl5000_apm_reset(struct iwl_priv *priv) 159static int iwl5000_apm_reset(struct iwl_priv *priv)
166{ 160{
167 int ret = 0; 161 int ret = 0;
168 unsigned long flags;
169 162
170 iwl5000_apm_stop_master(priv); 163 iwl5000_apm_stop_master(priv);
171 164
172 spin_lock_irqsave(&priv->lock, flags);
173
174 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 165 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
175 166
176 udelay(10); 167 udelay(10);
@@ -193,10 +184,6 @@ static int iwl5000_apm_reset(struct iwl_priv *priv)
193 goto out; 184 goto out;
194 } 185 }
195 186
196 ret = iwl_grab_nic_access(priv);
197 if (ret)
198 goto out;
199
200 /* enable DMA */ 187 /* enable DMA */
201 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); 188 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
202 189
@@ -205,11 +192,7 @@ static int iwl5000_apm_reset(struct iwl_priv *priv)
205 /* disable L1-Active */ 192 /* disable L1-Active */
206 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 193 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
207 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 194 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
208
209 iwl_release_nic_access(priv);
210
211out: 195out:
212 spin_unlock_irqrestore(&priv->lock, flags);
213 196
214 return ret; 197 return ret;
215} 198}
@@ -252,11 +235,9 @@ static void iwl5000_nic_config(struct iwl_priv *priv)
252 * (PCIe power is lost before PERST# is asserted), 235 * (PCIe power is lost before PERST# is asserted),
253 * causing ME FW to lose ownership and not being able to obtain it back. 236 * causing ME FW to lose ownership and not being able to obtain it back.
254 */ 237 */
255 iwl_grab_nic_access(priv);
256 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 238 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
257 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS, 239 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
258 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS); 240 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
259 iwl_release_nic_access(priv);
260 241
261 spin_unlock_irqrestore(&priv->lock, flags); 242 spin_unlock_irqrestore(&priv->lock, flags);
262} 243}
@@ -537,19 +518,9 @@ static int iwl5000_load_section(struct iwl_priv *priv,
537 struct fw_desc *image, 518 struct fw_desc *image,
538 u32 dst_addr) 519 u32 dst_addr)
539{ 520{
540 int ret = 0;
541 unsigned long flags;
542
543 dma_addr_t phy_addr = image->p_addr; 521 dma_addr_t phy_addr = image->p_addr;
544 u32 byte_cnt = image->len; 522 u32 byte_cnt = image->len;
545 523
546 spin_lock_irqsave(&priv->lock, flags);
547 ret = iwl_grab_nic_access(priv);
548 if (ret) {
549 spin_unlock_irqrestore(&priv->lock, flags);
550 return ret;
551 }
552
553 iwl_write_direct32(priv, 524 iwl_write_direct32(priv,
554 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 525 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
555 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 526 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
@@ -578,8 +549,6 @@ static int iwl5000_load_section(struct iwl_priv *priv,
578 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 549 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
579 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 550 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
580 551
581 iwl_release_nic_access(priv);
582 spin_unlock_irqrestore(&priv->lock, flags);
583 return 0; 552 return 0;
584} 553}
585 554
@@ -740,18 +709,11 @@ static int iwl5000_alive_notify(struct iwl_priv *priv)
740{ 709{
741 u32 a; 710 u32 a;
742 unsigned long flags; 711 unsigned long flags;
743 int ret;
744 int i, chan; 712 int i, chan;
745 u32 reg_val; 713 u32 reg_val;
746 714
747 spin_lock_irqsave(&priv->lock, flags); 715 spin_lock_irqsave(&priv->lock, flags);
748 716
749 ret = iwl_grab_nic_access(priv);
750 if (ret) {
751 spin_unlock_irqrestore(&priv->lock, flags);
752 return ret;
753 }
754
755 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR); 717 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
756 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET; 718 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
757 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET; 719 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
@@ -819,7 +781,6 @@ static int iwl5000_alive_notify(struct iwl_priv *priv)
819 iwl_txq_ctx_activate(priv, 8); 781 iwl_txq_ctx_activate(priv, 8);
820 iwl_txq_ctx_activate(priv, 9); 782 iwl_txq_ctx_activate(priv, 9);
821 783
822 iwl_release_nic_access(priv);
823 spin_unlock_irqrestore(&priv->lock, flags); 784 spin_unlock_irqrestore(&priv->lock, flags);
824 785
825 786
@@ -1000,7 +961,6 @@ static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1000 int tx_fifo, int sta_id, int tid, u16 ssn_idx) 961 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
1001{ 962{
1002 unsigned long flags; 963 unsigned long flags;
1003 int ret;
1004 u16 ra_tid; 964 u16 ra_tid;
1005 965
1006 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || 966 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
@@ -1018,11 +978,6 @@ static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1018 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid); 978 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
1019 979
1020 spin_lock_irqsave(&priv->lock, flags); 980 spin_lock_irqsave(&priv->lock, flags);
1021 ret = iwl_grab_nic_access(priv);
1022 if (ret) {
1023 spin_unlock_irqrestore(&priv->lock, flags);
1024 return ret;
1025 }
1026 981
1027 /* Stop this Tx queue before configuring it */ 982 /* Stop this Tx queue before configuring it */
1028 iwl5000_tx_queue_stop_scheduler(priv, txq_id); 983 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
@@ -1058,7 +1013,6 @@ static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1058 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ 1013 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1059 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); 1014 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1060 1015
1061 iwl_release_nic_access(priv);
1062 spin_unlock_irqrestore(&priv->lock, flags); 1016 spin_unlock_irqrestore(&priv->lock, flags);
1063 1017
1064 return 0; 1018 return 0;
@@ -1067,8 +1021,6 @@ static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1067static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, 1021static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1068 u16 ssn_idx, u8 tx_fifo) 1022 u16 ssn_idx, u8 tx_fifo)
1069{ 1023{
1070 int ret;
1071
1072 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || 1024 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1073 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) { 1025 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1074 IWL_ERR(priv, 1026 IWL_ERR(priv,
@@ -1078,10 +1030,6 @@ static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1078 return -EINVAL; 1030 return -EINVAL;
1079 } 1031 }
1080 1032
1081 ret = iwl_grab_nic_access(priv);
1082 if (ret)
1083 return ret;
1084
1085 iwl5000_tx_queue_stop_scheduler(priv, txq_id); 1033 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1086 1034
1087 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id)); 1035 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
@@ -1095,8 +1043,6 @@ static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1095 iwl_txq_ctx_deactivate(priv, txq_id); 1043 iwl_txq_ctx_deactivate(priv, txq_id);
1096 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); 1044 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1097 1045
1098 iwl_release_nic_access(priv);
1099
1100 return 0; 1046 return 0;
1101} 1047}
1102 1048
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.c b/drivers/net/wireless/iwlwifi/iwl-agn.c
index fd3673448d7a..4e41038a92c1 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn.c
@@ -503,24 +503,12 @@ int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
503int iwl_hw_tx_queue_init(struct iwl_priv *priv, 503int iwl_hw_tx_queue_init(struct iwl_priv *priv,
504 struct iwl_tx_queue *txq) 504 struct iwl_tx_queue *txq)
505{ 505{
506 int ret;
507 unsigned long flags;
508 int txq_id = txq->q.id; 506 int txq_id = txq->q.id;
509 507
510 spin_lock_irqsave(&priv->lock, flags);
511 ret = iwl_grab_nic_access(priv);
512 if (ret) {
513 spin_unlock_irqrestore(&priv->lock, flags);
514 return ret;
515 }
516
517 /* Circular buffer (TFD queue in DRAM) physical base address */ 508 /* Circular buffer (TFD queue in DRAM) physical base address */
518 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), 509 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
519 txq->q.dma_addr >> 8); 510 txq->q.dma_addr >> 8);
520 511
521 iwl_release_nic_access(priv);
522 spin_unlock_irqrestore(&priv->lock, flags);
523
524 return 0; 512 return 0;
525} 513}
526 514
@@ -709,6 +697,7 @@ static void iwl_rx_card_state_notif(struct iwl_priv *priv,
709 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; 697 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
710 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); 698 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
711 unsigned long status = priv->status; 699 unsigned long status = priv->status;
700 unsigned long reg_flags;
712 701
713 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n", 702 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
714 (flags & HW_CARD_DISABLED) ? "Kill" : "On", 703 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
@@ -720,32 +709,25 @@ static void iwl_rx_card_state_notif(struct iwl_priv *priv,
720 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, 709 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
721 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 710 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
722 711
723 if (!iwl_grab_nic_access(priv)) { 712 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
724 iwl_write_direct32( 713 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
725 priv, HBUS_TARG_MBX_C,
726 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
727
728 iwl_release_nic_access(priv);
729 }
730 714
731 if (!(flags & RXON_CARD_DISABLED)) { 715 if (!(flags & RXON_CARD_DISABLED)) {
732 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, 716 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
733 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 717 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
734 if (!iwl_grab_nic_access(priv)) { 718 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
735 iwl_write_direct32(
736 priv, HBUS_TARG_MBX_C,
737 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); 719 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
738 720
739 iwl_release_nic_access(priv);
740 }
741 } 721 }
742 722
743 if (flags & RF_CARD_DISABLED) { 723 if (flags & RF_CARD_DISABLED) {
744 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, 724 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
745 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); 725 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
746 iwl_read32(priv, CSR_UCODE_DRV_GP1); 726 iwl_read32(priv, CSR_UCODE_DRV_GP1);
727 spin_lock_irqsave(&priv->reg_lock, reg_flags);
747 if (!iwl_grab_nic_access(priv)) 728 if (!iwl_grab_nic_access(priv))
748 iwl_release_nic_access(priv); 729 iwl_release_nic_access(priv);
730 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
749 } 731 }
750 } 732 }
751 733
@@ -774,14 +756,6 @@ static void iwl_rx_card_state_notif(struct iwl_priv *priv,
774 756
775int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src) 757int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
776{ 758{
777 int ret;
778 unsigned long flags;
779
780 spin_lock_irqsave(&priv->lock, flags);
781 ret = iwl_grab_nic_access(priv);
782 if (ret)
783 goto err;
784
785 if (src == IWL_PWR_SRC_VAUX) { 759 if (src == IWL_PWR_SRC_VAUX) {
786 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) 760 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
787 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 761 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
@@ -793,10 +767,7 @@ int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
793 ~APMG_PS_CTRL_MSK_PWR_SRC); 767 ~APMG_PS_CTRL_MSK_PWR_SRC);
794 } 768 }
795 769
796 iwl_release_nic_access(priv); 770 return 0;
797err:
798 spin_unlock_irqrestore(&priv->lock, flags);
799 return ret;
800} 771}
801 772
802/** 773/**
@@ -1587,13 +1558,8 @@ static void __iwl_down(struct iwl_priv *priv)
1587 iwl_txq_ctx_stop(priv); 1558 iwl_txq_ctx_stop(priv);
1588 iwl_rxq_stop(priv); 1559 iwl_rxq_stop(priv);
1589 1560
1590 spin_lock_irqsave(&priv->lock, flags); 1561 iwl_write_prph(priv, APMG_CLK_DIS_REG,
1591 if (!iwl_grab_nic_access(priv)) { 1562 APMG_CLK_VAL_DMA_CLK_RQT);
1592 iwl_write_prph(priv, APMG_CLK_DIS_REG,
1593 APMG_CLK_VAL_DMA_CLK_RQT);
1594 iwl_release_nic_access(priv);
1595 }
1596 spin_unlock_irqrestore(&priv->lock, flags);
1597 1563
1598 udelay(5); 1564 udelay(5);
1599 1565
@@ -2707,6 +2673,10 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2707 (unsigned long long) pci_resource_len(pdev, 0)); 2673 (unsigned long long) pci_resource_len(pdev, 0));
2708 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base); 2674 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
2709 2675
2676 /* this spin lock will be used in apm_ops.init and EEPROM access
2677 * we should init now
2678 */
2679 spin_lock_init(&priv->reg_lock);
2710 iwl_hw_detect(priv); 2680 iwl_hw_detect(priv);
2711 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n", 2681 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
2712 priv->cfg->name, priv->hw_rev); 2682 priv->cfg->name, priv->hw_rev);
diff --git a/drivers/net/wireless/iwlwifi/iwl-core.c b/drivers/net/wireless/iwlwifi/iwl-core.c
index 6c1b171d92be..c7cbb2e80903 100644
--- a/drivers/net/wireless/iwlwifi/iwl-core.c
+++ b/drivers/net/wireless/iwlwifi/iwl-core.c
@@ -1588,10 +1588,6 @@ static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32
1588 1588
1589 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len); 1589 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
1590 1590
1591 ret = iwl_grab_nic_access(priv);
1592 if (ret)
1593 return ret;
1594
1595 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { 1591 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
1596 /* read data comes through single port, auto-incr addr */ 1592 /* read data comes through single port, auto-incr addr */
1597 /* NOTE: Use the debugless read so we don't flood kernel log 1593 /* NOTE: Use the debugless read so we don't flood kernel log
@@ -1607,8 +1603,6 @@ static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32
1607 } 1603 }
1608 } 1604 }
1609 1605
1610 iwl_release_nic_access(priv);
1611
1612 return ret; 1606 return ret;
1613} 1607}
1614 1608
@@ -1626,10 +1620,6 @@ static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
1626 1620
1627 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len); 1621 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
1628 1622
1629 ret = iwl_grab_nic_access(priv);
1630 if (ret)
1631 return ret;
1632
1633 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, 1623 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
1634 IWL49_RTC_INST_LOWER_BOUND); 1624 IWL49_RTC_INST_LOWER_BOUND);
1635 1625
@@ -1650,8 +1640,6 @@ static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
1650 } 1640 }
1651 } 1641 }
1652 1642
1653 iwl_release_nic_access(priv);
1654
1655 if (!errcnt) 1643 if (!errcnt)
1656 IWL_DEBUG_INFO(priv, 1644 IWL_DEBUG_INFO(priv,
1657 "ucode image in INSTRUCTION memory is good\n"); 1645 "ucode image in INSTRUCTION memory is good\n");
@@ -1760,7 +1748,6 @@ void iwl_dump_nic_error_log(struct iwl_priv *priv)
1760 u32 data2, line; 1748 u32 data2, line;
1761 u32 desc, time, count, base, data1; 1749 u32 desc, time, count, base, data1;
1762 u32 blink1, blink2, ilink1, ilink2; 1750 u32 blink1, blink2, ilink1, ilink2;
1763 int ret;
1764 1751
1765 if (priv->ucode_type == UCODE_INIT) 1752 if (priv->ucode_type == UCODE_INIT)
1766 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr); 1753 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
@@ -1772,12 +1759,6 @@ void iwl_dump_nic_error_log(struct iwl_priv *priv)
1772 return; 1759 return;
1773 } 1760 }
1774 1761
1775 ret = iwl_grab_nic_access(priv);
1776 if (ret) {
1777 IWL_WARN(priv, "Can not read from adapter at this time.\n");
1778 return;
1779 }
1780
1781 count = iwl_read_targ_mem(priv, base); 1762 count = iwl_read_targ_mem(priv, base);
1782 1763
1783 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { 1764 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
@@ -1804,7 +1785,6 @@ void iwl_dump_nic_error_log(struct iwl_priv *priv)
1804 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2, 1785 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1805 ilink1, ilink2); 1786 ilink1, ilink2);
1806 1787
1807 iwl_release_nic_access(priv);
1808} 1788}
1809EXPORT_SYMBOL(iwl_dump_nic_error_log); 1789EXPORT_SYMBOL(iwl_dump_nic_error_log);
1810 1790
@@ -1813,7 +1793,6 @@ EXPORT_SYMBOL(iwl_dump_nic_error_log);
1813/** 1793/**
1814 * iwl_print_event_log - Dump error event log to syslog 1794 * iwl_print_event_log - Dump error event log to syslog
1815 * 1795 *
1816 * NOTE: Must be called with iwl_grab_nic_access() already obtained!
1817 */ 1796 */
1818static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx, 1797static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1819 u32 num_events, u32 mode) 1798 u32 num_events, u32 mode)
@@ -1859,7 +1838,6 @@ static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1859 1838
1860void iwl_dump_nic_event_log(struct iwl_priv *priv) 1839void iwl_dump_nic_event_log(struct iwl_priv *priv)
1861{ 1840{
1862 int ret;
1863 u32 base; /* SRAM byte address of event log header */ 1841 u32 base; /* SRAM byte address of event log header */
1864 u32 capacity; /* event log capacity in # entries */ 1842 u32 capacity; /* event log capacity in # entries */
1865 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ 1843 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
@@ -1877,12 +1855,6 @@ void iwl_dump_nic_event_log(struct iwl_priv *priv)
1877 return; 1855 return;
1878 } 1856 }
1879 1857
1880 ret = iwl_grab_nic_access(priv);
1881 if (ret) {
1882 IWL_WARN(priv, "Can not read from adapter at this time.\n");
1883 return;
1884 }
1885
1886 /* event log header */ 1858 /* event log header */
1887 capacity = iwl_read_targ_mem(priv, base); 1859 capacity = iwl_read_targ_mem(priv, base);
1888 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); 1860 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
@@ -1894,7 +1866,6 @@ void iwl_dump_nic_event_log(struct iwl_priv *priv)
1894 /* bail out if nothing in log */ 1866 /* bail out if nothing in log */
1895 if (size == 0) { 1867 if (size == 0) {
1896 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n"); 1868 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
1897 iwl_release_nic_access(priv);
1898 return; 1869 return;
1899 } 1870 }
1900 1871
@@ -1909,7 +1880,6 @@ void iwl_dump_nic_event_log(struct iwl_priv *priv)
1909 /* (then/else) start at top of log */ 1880 /* (then/else) start at top of log */
1910 iwl_print_event_log(priv, 0, next_entry, mode); 1881 iwl_print_event_log(priv, 0, next_entry, mode);
1911 1882
1912 iwl_release_nic_access(priv);
1913} 1883}
1914EXPORT_SYMBOL(iwl_dump_nic_event_log); 1884EXPORT_SYMBOL(iwl_dump_nic_event_log);
1915 1885
@@ -2016,11 +1986,11 @@ int iwl_radio_kill_sw_enable_radio(struct iwl_priv *priv)
2016 /* wake up ucode */ 1986 /* wake up ucode */
2017 msleep(10); 1987 msleep(10);
2018 1988
2019 spin_lock_irqsave(&priv->lock, flags);
2020 iwl_read32(priv, CSR_UCODE_DRV_GP1); 1989 iwl_read32(priv, CSR_UCODE_DRV_GP1);
1990 spin_lock_irqsave(&priv->reg_lock, flags);
2021 if (!iwl_grab_nic_access(priv)) 1991 if (!iwl_grab_nic_access(priv))
2022 iwl_release_nic_access(priv); 1992 iwl_release_nic_access(priv);
2023 spin_unlock_irqrestore(&priv->lock, flags); 1993 spin_unlock_irqrestore(&priv->reg_lock, flags);
2024 1994
2025 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) { 1995 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
2026 IWL_DEBUG_RF_KILL(priv, "Can not turn radio back on - " 1996 IWL_DEBUG_RF_KILL(priv, "Can not turn radio back on - "
diff --git a/drivers/net/wireless/iwlwifi/iwl-debugfs.c b/drivers/net/wireless/iwlwifi/iwl-debugfs.c
index 713f9edd055d..03006c66a20e 100644
--- a/drivers/net/wireless/iwlwifi/iwl-debugfs.c
+++ b/drivers/net/wireless/iwlwifi/iwl-debugfs.c
@@ -172,7 +172,6 @@ static ssize_t iwl_dbgfs_sram_read(struct file *file,
172 struct iwl_priv *priv = (struct iwl_priv *)file->private_data; 172 struct iwl_priv *priv = (struct iwl_priv *)file->private_data;
173 const size_t bufsz = sizeof(buf); 173 const size_t bufsz = sizeof(buf);
174 174
175 iwl_grab_nic_access(priv);
176 for (i = priv->dbgfs->sram_len; i > 0; i -= 4) { 175 for (i = priv->dbgfs->sram_len; i > 0; i -= 4) {
177 val = iwl_read_targ_mem(priv, priv->dbgfs->sram_offset + \ 176 val = iwl_read_targ_mem(priv, priv->dbgfs->sram_offset + \
178 priv->dbgfs->sram_len - i); 177 priv->dbgfs->sram_len - i);
@@ -192,7 +191,6 @@ static ssize_t iwl_dbgfs_sram_read(struct file *file,
192 pos += scnprintf(buf + pos, bufsz - pos, "0x%08x ", val); 191 pos += scnprintf(buf + pos, bufsz - pos, "0x%08x ", val);
193 } 192 }
194 pos += scnprintf(buf + pos, bufsz - pos, "\n"); 193 pos += scnprintf(buf + pos, bufsz - pos, "\n");
195 iwl_release_nic_access(priv);
196 194
197 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 195 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
198 return ret; 196 return ret;
diff --git a/drivers/net/wireless/iwlwifi/iwl-dev.h b/drivers/net/wireless/iwlwifi/iwl-dev.h
index 8282def00832..1310c4122199 100644
--- a/drivers/net/wireless/iwlwifi/iwl-dev.h
+++ b/drivers/net/wireless/iwlwifi/iwl-dev.h
@@ -896,6 +896,7 @@ struct iwl_priv {
896 /* spinlock */ 896 /* spinlock */
897 spinlock_t lock; /* protect general shared data */ 897 spinlock_t lock; /* protect general shared data */
898 spinlock_t hcmd_lock; /* protect hcmd */ 898 spinlock_t hcmd_lock; /* protect hcmd */
899 spinlock_t reg_lock; /* protect hw register access */
899 struct mutex mutex; 900 struct mutex mutex;
900 901
901 /* basic pci-network driver stuff */ 902 /* basic pci-network driver stuff */
diff --git a/drivers/net/wireless/iwlwifi/iwl-eeprom.c b/drivers/net/wireless/iwlwifi/iwl-eeprom.c
index 9cc063b8b2d6..cefa501e5971 100644
--- a/drivers/net/wireless/iwlwifi/iwl-eeprom.c
+++ b/drivers/net/wireless/iwlwifi/iwl-eeprom.c
@@ -240,14 +240,12 @@ static int iwl_init_otp_access(struct iwl_priv *priv)
240 if (ret < 0) 240 if (ret < 0)
241 IWL_ERR(priv, "Time out access OTP\n"); 241 IWL_ERR(priv, "Time out access OTP\n");
242 else { 242 else {
243 ret = iwl_grab_nic_access(priv);
244 if (!ret) { 243 if (!ret) {
245 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, 244 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
246 APMG_PS_CTRL_VAL_RESET_REQ); 245 APMG_PS_CTRL_VAL_RESET_REQ);
247 udelay(5); 246 udelay(5);
248 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, 247 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
249 APMG_PS_CTRL_VAL_RESET_REQ); 248 APMG_PS_CTRL_VAL_RESET_REQ);
250 iwl_release_nic_access(priv);
251 } 249 }
252 } 250 }
253 return ret; 251 return ret;
diff --git a/drivers/net/wireless/iwlwifi/iwl-io.h b/drivers/net/wireless/iwlwifi/iwl-io.h
index 083ea1ffbe87..d30cb0275d19 100644
--- a/drivers/net/wireless/iwlwifi/iwl-io.h
+++ b/drivers/net/wireless/iwlwifi/iwl-io.h
@@ -131,9 +131,23 @@ static inline void __iwl_set_bit(const char *f, u32 l,
131 IWL_DEBUG_IO(priv, "set_bit(0x%08X, 0x%08X) = 0x%08X\n", reg, mask, val); 131 IWL_DEBUG_IO(priv, "set_bit(0x%08X, 0x%08X) = 0x%08X\n", reg, mask, val);
132 _iwl_write32(priv, reg, val); 132 _iwl_write32(priv, reg, val);
133} 133}
134#define iwl_set_bit(p, r, m) __iwl_set_bit(__FILE__, __LINE__, p, r, m) 134static inline void iwl_set_bit(struct iwl_priv *p, u32 r, u32 m)
135{
136 unsigned long reg_flags;
137
138 spin_lock_irqsave(&p->reg_lock, reg_flags);
139 __iwl_set_bit(__FILE__, __LINE__, p, r, m);
140 spin_unlock_irqrestore(&p->reg_lock, reg_flags);
141}
135#else 142#else
136#define iwl_set_bit(p, r, m) _iwl_set_bit(p, r, m) 143static inline void iwl_set_bit(struct iwl_priv *p, u32 r, u32 m)
144{
145 unsigned long reg_flags;
146
147 spin_lock_irqsave(&p->reg_lock, reg_flags);
148 _iwl_set_bit(p, r, m);
149 spin_unlock_irqrestore(&p->reg_lock, reg_flags);
150}
137#endif 151#endif
138 152
139static inline void _iwl_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask) 153static inline void _iwl_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask)
@@ -148,19 +162,30 @@ static inline void __iwl_clear_bit(const char *f, u32 l,
148 IWL_DEBUG_IO(priv, "clear_bit(0x%08X, 0x%08X) = 0x%08X\n", reg, mask, val); 162 IWL_DEBUG_IO(priv, "clear_bit(0x%08X, 0x%08X) = 0x%08X\n", reg, mask, val);
149 _iwl_write32(priv, reg, val); 163 _iwl_write32(priv, reg, val);
150} 164}
151#define iwl_clear_bit(p, r, m) __iwl_clear_bit(__FILE__, __LINE__, p, r, m) 165static inline void iwl_clear_bit(struct iwl_priv *p, u32 r, u32 m)
166{
167 unsigned long reg_flags;
168
169 spin_lock_irqsave(&p->reg_lock, reg_flags);
170 __iwl_clear_bit(__FILE__, __LINE__, p, r, m);
171 spin_unlock_irqrestore(&p->reg_lock, reg_flags);
172}
152#else 173#else
153#define iwl_clear_bit(p, r, m) _iwl_clear_bit(p, r, m) 174static inline void iwl_clear_bit(struct iwl_priv *p, u32 r, u32 m)
175{
176 unsigned long reg_flags;
177
178 spin_lock_irqsave(&p->reg_lock, reg_flags);
179 _iwl_clear_bit(p, r, m);
180 spin_unlock_irqrestore(&p->reg_lock, reg_flags);
181}
154#endif 182#endif
155 183
156static inline int _iwl_grab_nic_access(struct iwl_priv *priv) 184static inline int _iwl_grab_nic_access(struct iwl_priv *priv)
157{ 185{
158 int ret; 186 int ret;
159 u32 val; 187 u32 val;
160#ifdef CONFIG_IWLWIFI_DEBUG 188
161 if (atomic_read(&priv->restrict_refcnt))
162 return 0;
163#endif
164 /* this bit wakes up the NIC */ 189 /* this bit wakes up the NIC */
165 _iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 190 _iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
166 ret = _iwl_poll_bit(priv, CSR_GP_CNTRL, 191 ret = _iwl_poll_bit(priv, CSR_GP_CNTRL,
@@ -170,12 +195,10 @@ static inline int _iwl_grab_nic_access(struct iwl_priv *priv)
170 if (ret < 0) { 195 if (ret < 0) {
171 val = _iwl_read32(priv, CSR_GP_CNTRL); 196 val = _iwl_read32(priv, CSR_GP_CNTRL);
172 IWL_ERR(priv, "MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val); 197 IWL_ERR(priv, "MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val);
198 _iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
173 return -EIO; 199 return -EIO;
174 } 200 }
175 201
176#ifdef CONFIG_IWLWIFI_DEBUG
177 atomic_inc(&priv->restrict_refcnt);
178#endif
179 return 0; 202 return 0;
180} 203}
181 204
@@ -183,9 +206,6 @@ static inline int _iwl_grab_nic_access(struct iwl_priv *priv)
183static inline int __iwl_grab_nic_access(const char *f, u32 l, 206static inline int __iwl_grab_nic_access(const char *f, u32 l,
184 struct iwl_priv *priv) 207 struct iwl_priv *priv)
185{ 208{
186 if (atomic_read(&priv->restrict_refcnt))
187 IWL_ERR(priv, "Grabbing access while already held %s %d.\n", f, l);
188
189 IWL_DEBUG_IO(priv, "grabbing nic access - %s %d\n", f, l); 209 IWL_DEBUG_IO(priv, "grabbing nic access - %s %d\n", f, l);
190 return _iwl_grab_nic_access(priv); 210 return _iwl_grab_nic_access(priv);
191} 211}
@@ -198,18 +218,13 @@ static inline int __iwl_grab_nic_access(const char *f, u32 l,
198 218
199static inline void _iwl_release_nic_access(struct iwl_priv *priv) 219static inline void _iwl_release_nic_access(struct iwl_priv *priv)
200{ 220{
201#ifdef CONFIG_IWLWIFI_DEBUG 221 _iwl_clear_bit(priv, CSR_GP_CNTRL,
202 if (atomic_dec_and_test(&priv->restrict_refcnt)) 222 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
203#endif
204 _iwl_clear_bit(priv, CSR_GP_CNTRL,
205 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
206} 223}
207#ifdef CONFIG_IWLWIFI_DEBUG 224#ifdef CONFIG_IWLWIFI_DEBUG
208static inline void __iwl_release_nic_access(const char *f, u32 l, 225static inline void __iwl_release_nic_access(const char *f, u32 l,
209 struct iwl_priv *priv) 226 struct iwl_priv *priv)
210{ 227{
211 if (atomic_read(&priv->restrict_refcnt) <= 0)
212 IWL_ERR(priv, "Release unheld nic access at line %s %d.\n", f, l);
213 228
214 IWL_DEBUG_IO(priv, "releasing nic access - %s %d\n", f, l); 229 IWL_DEBUG_IO(priv, "releasing nic access - %s %d\n", f, l);
215 _iwl_release_nic_access(priv); 230 _iwl_release_nic_access(priv);
@@ -230,16 +245,37 @@ static inline u32 __iwl_read_direct32(const char *f, u32 l,
230 struct iwl_priv *priv, u32 reg) 245 struct iwl_priv *priv, u32 reg)
231{ 246{
232 u32 value = _iwl_read_direct32(priv, reg); 247 u32 value = _iwl_read_direct32(priv, reg);
233 if (!atomic_read(&priv->restrict_refcnt))
234 IWL_ERR(priv, "Nic access not held from %s %d\n", f, l);
235 IWL_DEBUG_IO(priv, "read_direct32(0x%4X) = 0x%08x - %s %d \n", reg, value, 248 IWL_DEBUG_IO(priv, "read_direct32(0x%4X) = 0x%08x - %s %d \n", reg, value,
236 f, l); 249 f, l);
237 return value; 250 return value;
238} 251}
239#define iwl_read_direct32(priv, reg) \ 252static inline u32 iwl_read_direct32(struct iwl_priv *priv, u32 reg)
240 __iwl_read_direct32(__FILE__, __LINE__, priv, reg) 253{
254 u32 value;
255 unsigned long reg_flags;
256
257 spin_lock_irqsave(&priv->reg_lock, reg_flags);
258 iwl_grab_nic_access(priv);
259 value = __iwl_read_direct32(__FILE__, __LINE__, priv, reg);
260 iwl_release_nic_access(priv);
261 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
262 return value;
263}
264
241#else 265#else
242#define iwl_read_direct32 _iwl_read_direct32 266static inline u32 iwl_read_direct32(struct iwl_priv *priv, u32 reg)
267{
268 u32 value;
269 unsigned long reg_flags;
270
271 spin_lock_irqsave(&priv->reg_lock, reg_flags);
272 iwl_grab_nic_access(priv);
273 value = _iwl_read_direct32(priv, reg);
274 iwl_release_nic_access(priv);
275 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
276 return value;
277
278}
243#endif 279#endif
244 280
245static inline void _iwl_write_direct32(struct iwl_priv *priv, 281static inline void _iwl_write_direct32(struct iwl_priv *priv,
@@ -247,19 +283,17 @@ static inline void _iwl_write_direct32(struct iwl_priv *priv,
247{ 283{
248 _iwl_write32(priv, reg, value); 284 _iwl_write32(priv, reg, value);
249} 285}
250#ifdef CONFIG_IWLWIFI_DEBUG 286static inline void iwl_write_direct32(struct iwl_priv *priv, u32 reg, u32 value)
251static void __iwl_write_direct32(const char *f , u32 line,
252 struct iwl_priv *priv, u32 reg, u32 value)
253{ 287{
254 if (!atomic_read(&priv->restrict_refcnt)) 288 unsigned long reg_flags;
255 IWL_ERR(priv, "Nic access not held from %s line %d\n", f, line); 289
256 _iwl_write_direct32(priv, reg, value); 290 spin_lock_irqsave(&priv->reg_lock, reg_flags);
291 if (!iwl_grab_nic_access(priv)) {
292 _iwl_write_direct32(priv, reg, value);
293 iwl_release_nic_access(priv);
294 }
295 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
257} 296}
258#define iwl_write_direct32(priv, reg, value) \
259 __iwl_write_direct32(__func__, __LINE__, priv, reg, value)
260#else
261#define iwl_write_direct32 _iwl_write_direct32
262#endif
263 297
264static inline void iwl_write_reg_buf(struct iwl_priv *priv, 298static inline void iwl_write_reg_buf(struct iwl_priv *priv,
265 u32 reg, u32 len, u32 *values) 299 u32 reg, u32 len, u32 *values)
@@ -268,14 +302,23 @@ static inline void iwl_write_reg_buf(struct iwl_priv *priv,
268 302
269 if ((priv != NULL) && (values != NULL)) { 303 if ((priv != NULL) && (values != NULL)) {
270 for (; 0 < len; len -= count, reg += count, values++) 304 for (; 0 < len; len -= count, reg += count, values++)
271 _iwl_write_direct32(priv, reg, *values); 305 iwl_write_direct32(priv, reg, *values);
272 } 306 }
273} 307}
274 308
275static inline int _iwl_poll_direct_bit(struct iwl_priv *priv, u32 addr, 309static inline int _iwl_poll_direct_bit(struct iwl_priv *priv, u32 addr,
276 u32 mask, int timeout) 310 u32 mask, int timeout)
277{ 311{
278 return _iwl_poll_bit(priv, addr, mask, mask, timeout); 312 int t = 0;
313
314 do {
315 if ((iwl_read_direct32(priv, addr) & mask) == mask)
316 return t;
317 udelay(IWL_POLL_INTERVAL);
318 t += IWL_POLL_INTERVAL;
319 } while (t < timeout);
320
321 return -ETIMEDOUT;
279} 322}
280 323
281#ifdef CONFIG_IWLWIFI_DEBUG 324#ifdef CONFIG_IWLWIFI_DEBUG
@@ -305,20 +348,18 @@ static inline u32 _iwl_read_prph(struct iwl_priv *priv, u32 reg)
305 rmb(); 348 rmb();
306 return _iwl_read_direct32(priv, HBUS_TARG_PRPH_RDAT); 349 return _iwl_read_direct32(priv, HBUS_TARG_PRPH_RDAT);
307} 350}
308#ifdef CONFIG_IWLWIFI_DEBUG 351static inline u32 iwl_read_prph(struct iwl_priv *priv, u32 reg)
309static inline u32 __iwl_read_prph(const char *f, u32 line,
310 struct iwl_priv *priv, u32 reg)
311{ 352{
312 if (!atomic_read(&priv->restrict_refcnt)) 353 unsigned long reg_flags;
313 IWL_ERR(priv, "Nic access not held from %s line %d\n", f, line); 354 u32 val;
314 return _iwl_read_prph(priv, reg);
315}
316 355
317#define iwl_read_prph(priv, reg) \ 356 spin_lock_irqsave(&priv->reg_lock, reg_flags);
318 __iwl_read_prph(__func__, __LINE__, priv, reg) 357 iwl_grab_nic_access(priv);
319#else 358 val = _iwl_read_prph(priv, reg);
320#define iwl_read_prph _iwl_read_prph 359 iwl_release_nic_access(priv);
321#endif 360 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
361 return val;
362}
322 363
323static inline void _iwl_write_prph(struct iwl_priv *priv, 364static inline void _iwl_write_prph(struct iwl_priv *priv,
324 u32 addr, u32 val) 365 u32 addr, u32 val)
@@ -328,83 +369,107 @@ static inline void _iwl_write_prph(struct iwl_priv *priv,
328 wmb(); 369 wmb();
329 _iwl_write_direct32(priv, HBUS_TARG_PRPH_WDAT, val); 370 _iwl_write_direct32(priv, HBUS_TARG_PRPH_WDAT, val);
330} 371}
331#ifdef CONFIG_IWLWIFI_DEBUG 372
332static inline void __iwl_write_prph(const char *f, u32 line, 373static inline void iwl_write_prph(struct iwl_priv *priv, u32 addr, u32 val)
333 struct iwl_priv *priv, u32 addr, u32 val)
334{ 374{
335 if (!atomic_read(&priv->restrict_refcnt)) 375 unsigned long reg_flags;
336 IWL_ERR(priv, "Nic access not held from %s line %d\n", f, line);
337 _iwl_write_prph(priv, addr, val);
338}
339 376
340#define iwl_write_prph(priv, addr, val) \ 377 spin_lock_irqsave(&priv->reg_lock, reg_flags);
341 __iwl_write_prph(__func__, __LINE__, priv, addr, val); 378 if (!iwl_grab_nic_access(priv)) {
342#else 379 _iwl_write_prph(priv, addr, val);
343#define iwl_write_prph _iwl_write_prph 380 iwl_release_nic_access(priv);
344#endif 381 }
382 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
383}
345 384
346#define _iwl_set_bits_prph(priv, reg, mask) \ 385#define _iwl_set_bits_prph(priv, reg, mask) \
347 _iwl_write_prph(priv, reg, (_iwl_read_prph(priv, reg) | mask)) 386 _iwl_write_prph(priv, reg, (_iwl_read_prph(priv, reg) | mask))
348#ifdef CONFIG_IWLWIFI_DEBUG 387
349static inline void __iwl_set_bits_prph(const char *f, u32 line, 388static inline void iwl_set_bits_prph(struct iwl_priv *priv, u32 reg, u32 mask)
350 struct iwl_priv *priv,
351 u32 reg, u32 mask)
352{ 389{
353 if (!atomic_read(&priv->restrict_refcnt)) 390 unsigned long reg_flags;
354 IWL_ERR(priv, "Nic access not held from %s line %d\n", f, line);
355 391
392 spin_lock_irqsave(&priv->reg_lock, reg_flags);
393 iwl_grab_nic_access(priv);
356 _iwl_set_bits_prph(priv, reg, mask); 394 _iwl_set_bits_prph(priv, reg, mask);
395 iwl_release_nic_access(priv);
396 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
357} 397}
358#define iwl_set_bits_prph(priv, reg, mask) \
359 __iwl_set_bits_prph(__func__, __LINE__, priv, reg, mask)
360#else
361#define iwl_set_bits_prph _iwl_set_bits_prph
362#endif
363 398
364#define _iwl_set_bits_mask_prph(priv, reg, bits, mask) \ 399#define _iwl_set_bits_mask_prph(priv, reg, bits, mask) \
365 _iwl_write_prph(priv, reg, ((_iwl_read_prph(priv, reg) & mask) | bits)) 400 _iwl_write_prph(priv, reg, ((_iwl_read_prph(priv, reg) & mask) | bits))
366 401
367#ifdef CONFIG_IWLWIFI_DEBUG 402static inline void iwl_set_bits_mask_prph(struct iwl_priv *priv, u32 reg,
368static inline void __iwl_set_bits_mask_prph(const char *f, u32 line, 403 u32 bits, u32 mask)
369 struct iwl_priv *priv, u32 reg, u32 bits, u32 mask)
370{ 404{
371 if (!atomic_read(&priv->restrict_refcnt)) 405 unsigned long reg_flags;
372 IWL_ERR(priv, "Nic access not held from %s line %d\n", f, line); 406
407 spin_lock_irqsave(&priv->reg_lock, reg_flags);
408 iwl_grab_nic_access(priv);
373 _iwl_set_bits_mask_prph(priv, reg, bits, mask); 409 _iwl_set_bits_mask_prph(priv, reg, bits, mask);
410 iwl_release_nic_access(priv);
411 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
374} 412}
375#define iwl_set_bits_mask_prph(priv, reg, bits, mask) \
376 __iwl_set_bits_mask_prph(__func__, __LINE__, priv, reg, bits, mask)
377#else
378#define iwl_set_bits_mask_prph _iwl_set_bits_mask_prph
379#endif
380 413
381static inline void iwl_clear_bits_prph(struct iwl_priv 414static inline void iwl_clear_bits_prph(struct iwl_priv
382 *priv, u32 reg, u32 mask) 415 *priv, u32 reg, u32 mask)
383{ 416{
384 u32 val = _iwl_read_prph(priv, reg); 417 unsigned long reg_flags;
418 u32 val;
419
420 spin_lock_irqsave(&priv->reg_lock, reg_flags);
421 iwl_grab_nic_access(priv);
422 val = _iwl_read_prph(priv, reg);
385 _iwl_write_prph(priv, reg, (val & ~mask)); 423 _iwl_write_prph(priv, reg, (val & ~mask));
424 iwl_release_nic_access(priv);
425 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
386} 426}
387 427
388static inline u32 iwl_read_targ_mem(struct iwl_priv *priv, u32 addr) 428static inline u32 iwl_read_targ_mem(struct iwl_priv *priv, u32 addr)
389{ 429{
390 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, addr); 430 unsigned long reg_flags;
431 u32 value;
432
433 spin_lock_irqsave(&priv->reg_lock, reg_flags);
434 iwl_grab_nic_access(priv);
435
436 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, addr);
391 rmb(); 437 rmb();
392 return iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); 438 value = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
439
440 iwl_release_nic_access(priv);
441 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
442 return value;
393} 443}
394 444
395static inline void iwl_write_targ_mem(struct iwl_priv *priv, u32 addr, u32 val) 445static inline void iwl_write_targ_mem(struct iwl_priv *priv, u32 addr, u32 val)
396{ 446{
397 iwl_write_direct32(priv, HBUS_TARG_MEM_WADDR, addr); 447 unsigned long reg_flags;
398 wmb(); 448
399 iwl_write_direct32(priv, HBUS_TARG_MEM_WDAT, val); 449 spin_lock_irqsave(&priv->reg_lock, reg_flags);
450 if (!iwl_grab_nic_access(priv)) {
451 _iwl_write_direct32(priv, HBUS_TARG_MEM_WADDR, addr);
452 wmb();
453 _iwl_write_direct32(priv, HBUS_TARG_MEM_WDAT, val);
454 iwl_release_nic_access(priv);
455 }
456 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
400} 457}
401 458
402static inline void iwl_write_targ_mem_buf(struct iwl_priv *priv, u32 addr, 459static inline void iwl_write_targ_mem_buf(struct iwl_priv *priv, u32 addr,
403 u32 len, u32 *values) 460 u32 len, u32 *values)
404{ 461{
405 iwl_write_direct32(priv, HBUS_TARG_MEM_WADDR, addr); 462 unsigned long reg_flags;
406 wmb(); 463
407 for (; 0 < len; len -= sizeof(u32), values++) 464 spin_lock_irqsave(&priv->reg_lock, reg_flags);
408 iwl_write_direct32(priv, HBUS_TARG_MEM_WDAT, *values); 465 if (!iwl_grab_nic_access(priv)) {
466 _iwl_write_direct32(priv, HBUS_TARG_MEM_WADDR, addr);
467 wmb();
468 for (; 0 < len; len -= sizeof(u32), values++)
469 _iwl_write_direct32(priv, HBUS_TARG_MEM_WDAT, *values);
470
471 iwl_release_nic_access(priv);
472 }
473 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
409} 474}
410#endif 475#endif
diff --git a/drivers/net/wireless/iwlwifi/iwl-rx.c b/drivers/net/wireless/iwlwifi/iwl-rx.c
index 73739cfd8047..7a432829e79f 100644
--- a/drivers/net/wireless/iwlwifi/iwl-rx.c
+++ b/drivers/net/wireless/iwlwifi/iwl-rx.c
@@ -145,13 +145,7 @@ int iwl_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q)
145 goto exit_unlock; 145 goto exit_unlock;
146 } 146 }
147 147
148 ret = iwl_grab_nic_access(priv);
149 if (ret)
150 goto exit_unlock;
151
152 /* Device expects a multiple of 8 */
153 iwl_write_direct32(priv, rx_wrt_ptr_reg, q->write & ~0x7); 148 iwl_write_direct32(priv, rx_wrt_ptr_reg, q->write & ~0x7);
154 iwl_release_nic_access(priv);
155 149
156 /* Else device is assumed to be awake */ 150 /* Else device is assumed to be awake */
157 } else { 151 } else {
@@ -403,19 +397,10 @@ EXPORT_SYMBOL(iwl_rx_queue_reset);
403 397
404int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq) 398int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
405{ 399{
406 int ret;
407 unsigned long flags;
408 u32 rb_size; 400 u32 rb_size;
409 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ 401 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
410 const u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT why this stalls RX */ 402 const u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT why this stalls RX */
411 403
412 spin_lock_irqsave(&priv->lock, flags);
413 ret = iwl_grab_nic_access(priv);
414 if (ret) {
415 spin_unlock_irqrestore(&priv->lock, flags);
416 return ret;
417 }
418
419 if (priv->cfg->mod_params->amsdu_size_8K) 404 if (priv->cfg->mod_params->amsdu_size_8K)
420 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; 405 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
421 else 406 else
@@ -452,35 +437,19 @@ int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
452 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)| 437 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
453 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); 438 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
454 439
455 iwl_release_nic_access(priv);
456
457 iwl_write32(priv, CSR_INT_COALESCING, 0x40); 440 iwl_write32(priv, CSR_INT_COALESCING, 0x40);
458 441
459 spin_unlock_irqrestore(&priv->lock, flags);
460
461 return 0; 442 return 0;
462} 443}
463 444
464int iwl_rxq_stop(struct iwl_priv *priv) 445int iwl_rxq_stop(struct iwl_priv *priv)
465{ 446{
466 int ret;
467 unsigned long flags;
468
469 spin_lock_irqsave(&priv->lock, flags);
470 ret = iwl_grab_nic_access(priv);
471 if (unlikely(ret)) {
472 spin_unlock_irqrestore(&priv->lock, flags);
473 return ret;
474 }
475 447
476 /* stop Rx DMA */ 448 /* stop Rx DMA */
477 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 449 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
478 iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG, 450 iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
479 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); 451 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
480 452
481 iwl_release_nic_access(priv);
482 spin_unlock_irqrestore(&priv->lock, flags);
483
484 return 0; 453 return 0;
485} 454}
486EXPORT_SYMBOL(iwl_rxq_stop); 455EXPORT_SYMBOL(iwl_rxq_stop);
diff --git a/drivers/net/wireless/iwlwifi/iwl-tx.c b/drivers/net/wireless/iwlwifi/iwl-tx.c
index a82cca0a30c7..85ae7a62109c 100644
--- a/drivers/net/wireless/iwlwifi/iwl-tx.c
+++ b/drivers/net/wireless/iwlwifi/iwl-tx.c
@@ -102,13 +102,8 @@ int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
102 return ret; 102 return ret;
103 } 103 }
104 104
105 /* restore this queue's parameters in nic hardware. */
106 ret = iwl_grab_nic_access(priv);
107 if (ret)
108 return ret;
109 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 105 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
110 txq->q.write_ptr | (txq_id << 8)); 106 txq->q.write_ptr | (txq_id << 8));
111 iwl_release_nic_access(priv);
112 107
113 /* else not in power-save mode, uCode will never sleep when we're 108 /* else not in power-save mode, uCode will never sleep when we're
114 * trying to tx (during RFKILL, we're not trying to tx). */ 109 * trying to tx (during RFKILL, we're not trying to tx). */
@@ -429,11 +424,6 @@ int iwl_txq_ctx_reset(struct iwl_priv *priv)
429 goto error_kw; 424 goto error_kw;
430 } 425 }
431 spin_lock_irqsave(&priv->lock, flags); 426 spin_lock_irqsave(&priv->lock, flags);
432 ret = iwl_grab_nic_access(priv);
433 if (unlikely(ret)) {
434 spin_unlock_irqrestore(&priv->lock, flags);
435 goto error_reset;
436 }
437 427
438 /* Turn off all Tx DMA fifos */ 428 /* Turn off all Tx DMA fifos */
439 priv->cfg->ops->lib->txq_set_sched(priv, 0); 429 priv->cfg->ops->lib->txq_set_sched(priv, 0);
@@ -441,7 +431,6 @@ int iwl_txq_ctx_reset(struct iwl_priv *priv)
441 /* Tell NIC where to find the "keep warm" buffer */ 431 /* Tell NIC where to find the "keep warm" buffer */
442 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4); 432 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
443 433
444 iwl_release_nic_access(priv);
445 spin_unlock_irqrestore(&priv->lock, flags); 434 spin_unlock_irqrestore(&priv->lock, flags);
446 435
447 /* Alloc and init all Tx queues, including the command queue (#4) */ 436 /* Alloc and init all Tx queues, including the command queue (#4) */
@@ -460,7 +449,6 @@ int iwl_txq_ctx_reset(struct iwl_priv *priv)
460 449
461 error: 450 error:
462 iwl_hw_txq_ctx_free(priv); 451 iwl_hw_txq_ctx_free(priv);
463 error_reset:
464 iwl_free_dma_ptr(priv, &priv->kw); 452 iwl_free_dma_ptr(priv, &priv->kw);
465 error_kw: 453 error_kw:
466 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls); 454 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
@@ -478,10 +466,6 @@ void iwl_txq_ctx_stop(struct iwl_priv *priv)
478 466
479 /* Turn off all Tx DMA fifos */ 467 /* Turn off all Tx DMA fifos */
480 spin_lock_irqsave(&priv->lock, flags); 468 spin_lock_irqsave(&priv->lock, flags);
481 if (iwl_grab_nic_access(priv)) {
482 spin_unlock_irqrestore(&priv->lock, flags);
483 return;
484 }
485 469
486 priv->cfg->ops->lib->txq_set_sched(priv, 0); 470 priv->cfg->ops->lib->txq_set_sched(priv, 0);
487 471
@@ -492,7 +476,6 @@ void iwl_txq_ctx_stop(struct iwl_priv *priv)
492 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 476 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
493 1000); 477 1000);
494 } 478 }
495 iwl_release_nic_access(priv);
496 spin_unlock_irqrestore(&priv->lock, flags); 479 spin_unlock_irqrestore(&priv->lock, flags);
497 480
498 /* Deallocate memory for all Tx queues */ 481 /* Deallocate memory for all Tx queues */
diff --git a/drivers/net/wireless/iwlwifi/iwl3945-base.c b/drivers/net/wireless/iwlwifi/iwl3945-base.c
index 5d52f2275b6d..8e68803cdc62 100644
--- a/drivers/net/wireless/iwlwifi/iwl3945-base.c
+++ b/drivers/net/wireless/iwlwifi/iwl3945-base.c
@@ -1686,7 +1686,6 @@ static void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
1686 u32 i; 1686 u32 i;
1687 u32 desc, time, count, base, data1; 1687 u32 desc, time, count, base, data1;
1688 u32 blink1, blink2, ilink1, ilink2; 1688 u32 blink1, blink2, ilink1, ilink2;
1689 int rc;
1690 1689
1691 base = le32_to_cpu(priv->card_alive.error_event_table_ptr); 1690 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1692 1691
@@ -1695,11 +1694,6 @@ static void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
1695 return; 1694 return;
1696 } 1695 }
1697 1696
1698 rc = iwl_grab_nic_access(priv);
1699 if (rc) {
1700 IWL_WARN(priv, "Can not read from adapter at this time.\n");
1701 return;
1702 }
1703 1697
1704 count = iwl_read_targ_mem(priv, base); 1698 count = iwl_read_targ_mem(priv, base);
1705 1699
@@ -1734,8 +1728,6 @@ static void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
1734 ilink1, ilink2, data1); 1728 ilink1, ilink2, data1);
1735 } 1729 }
1736 1730
1737 iwl_release_nic_access(priv);
1738
1739} 1731}
1740 1732
1741#define EVENT_START_OFFSET (6 * sizeof(u32)) 1733#define EVENT_START_OFFSET (6 * sizeof(u32))
@@ -1743,7 +1735,6 @@ static void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
1743/** 1735/**
1744 * iwl3945_print_event_log - Dump error event log to syslog 1736 * iwl3945_print_event_log - Dump error event log to syslog
1745 * 1737 *
1746 * NOTE: Must be called with iwl_grab_nic_access() already obtained!
1747 */ 1738 */
1748static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx, 1739static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
1749 u32 num_events, u32 mode) 1740 u32 num_events, u32 mode)
@@ -1786,7 +1777,6 @@ static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
1786 1777
1787static void iwl3945_dump_nic_event_log(struct iwl_priv *priv) 1778static void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
1788{ 1779{
1789 int rc;
1790 u32 base; /* SRAM byte address of event log header */ 1780 u32 base; /* SRAM byte address of event log header */
1791 u32 capacity; /* event log capacity in # entries */ 1781 u32 capacity; /* event log capacity in # entries */
1792 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ 1782 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
@@ -1800,12 +1790,6 @@ static void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
1800 return; 1790 return;
1801 } 1791 }
1802 1792
1803 rc = iwl_grab_nic_access(priv);
1804 if (rc) {
1805 IWL_WARN(priv, "Can not read from adapter at this time.\n");
1806 return;
1807 }
1808
1809 /* event log header */ 1793 /* event log header */
1810 capacity = iwl_read_targ_mem(priv, base); 1794 capacity = iwl_read_targ_mem(priv, base);
1811 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); 1795 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
@@ -1817,7 +1801,6 @@ static void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
1817 /* bail out if nothing in log */ 1801 /* bail out if nothing in log */
1818 if (size == 0) { 1802 if (size == 0) {
1819 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n"); 1803 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
1820 iwl_release_nic_access(priv);
1821 return; 1804 return;
1822 } 1805 }
1823 1806
@@ -1833,7 +1816,6 @@ static void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
1833 /* (then/else) start at top of log */ 1816 /* (then/else) start at top of log */
1834 iwl3945_print_event_log(priv, 0, next_entry, mode); 1817 iwl3945_print_event_log(priv, 0, next_entry, mode);
1835 1818
1836 iwl_release_nic_access(priv);
1837} 1819}
1838 1820
1839static void iwl3945_irq_tasklet(struct iwl_priv *priv) 1821static void iwl3945_irq_tasklet(struct iwl_priv *priv)
@@ -1952,11 +1934,8 @@ static void iwl3945_irq_tasklet(struct iwl_priv *priv)
1952 priv->isr_stats.tx++; 1934 priv->isr_stats.tx++;
1953 1935
1954 iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6)); 1936 iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
1955 if (!iwl_grab_nic_access(priv)) { 1937 iwl_write_direct32(priv, FH39_TCSR_CREDIT
1956 iwl_write_direct32(priv, FH39_TCSR_CREDIT 1938 (FH39_SRVC_CHNL), 0x0);
1957 (FH39_SRVC_CHNL), 0x0);
1958 iwl_release_nic_access(priv);
1959 }
1960 handled |= CSR_INT_BIT_FH_TX; 1939 handled |= CSR_INT_BIT_FH_TX;
1961 } 1940 }
1962 1941
@@ -2131,10 +2110,6 @@ static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 le
2131 2110
2132 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len); 2111 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
2133 2112
2134 rc = iwl_grab_nic_access(priv);
2135 if (rc)
2136 return rc;
2137
2138 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, 2113 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
2139 IWL39_RTC_INST_LOWER_BOUND); 2114 IWL39_RTC_INST_LOWER_BOUND);
2140 2115
@@ -2155,7 +2130,6 @@ static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 le
2155 } 2130 }
2156 } 2131 }
2157 2132
2158 iwl_release_nic_access(priv);
2159 2133
2160 if (!errcnt) 2134 if (!errcnt)
2161 IWL_DEBUG_INFO(priv, 2135 IWL_DEBUG_INFO(priv,
@@ -2179,10 +2153,6 @@ static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32
2179 2153
2180 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len); 2154 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
2181 2155
2182 rc = iwl_grab_nic_access(priv);
2183 if (rc)
2184 return rc;
2185
2186 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { 2156 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
2187 /* read data comes through single port, auto-incr addr */ 2157 /* read data comes through single port, auto-incr addr */
2188 /* NOTE: Use the debugless read so we don't flood kernel log 2158 /* NOTE: Use the debugless read so we don't flood kernel log
@@ -2203,8 +2173,6 @@ static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32
2203 } 2173 }
2204 } 2174 }
2205 2175
2206 iwl_release_nic_access(priv);
2207
2208 return rc; 2176 return rc;
2209} 2177}
2210 2178
@@ -2528,20 +2496,11 @@ static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
2528{ 2496{
2529 dma_addr_t pinst; 2497 dma_addr_t pinst;
2530 dma_addr_t pdata; 2498 dma_addr_t pdata;
2531 int rc = 0;
2532 unsigned long flags;
2533 2499
2534 /* bits 31:0 for 3945 */ 2500 /* bits 31:0 for 3945 */
2535 pinst = priv->ucode_code.p_addr; 2501 pinst = priv->ucode_code.p_addr;
2536 pdata = priv->ucode_data_backup.p_addr; 2502 pdata = priv->ucode_data_backup.p_addr;
2537 2503
2538 spin_lock_irqsave(&priv->lock, flags);
2539 rc = iwl_grab_nic_access(priv);
2540 if (rc) {
2541 spin_unlock_irqrestore(&priv->lock, flags);
2542 return rc;
2543 }
2544
2545 /* Tell bootstrap uCode where to find image to load */ 2504 /* Tell bootstrap uCode where to find image to load */
2546 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); 2505 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2547 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); 2506 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
@@ -2553,13 +2512,9 @@ static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
2553 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, 2512 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
2554 priv->ucode_code.len | BSM_DRAM_INST_LOAD); 2513 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
2555 2514
2556 iwl_release_nic_access(priv);
2557
2558 spin_unlock_irqrestore(&priv->lock, flags);
2559
2560 IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n"); 2515 IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
2561 2516
2562 return rc; 2517 return 0;
2563} 2518}
2564 2519
2565/** 2520/**
@@ -2612,7 +2567,6 @@ static void iwl3945_init_alive_start(struct iwl_priv *priv)
2612 */ 2567 */
2613static void iwl3945_alive_start(struct iwl_priv *priv) 2568static void iwl3945_alive_start(struct iwl_priv *priv)
2614{ 2569{
2615 int rc = 0;
2616 int thermal_spin = 0; 2570 int thermal_spin = 0;
2617 u32 rfkill; 2571 u32 rfkill;
2618 2572
@@ -2637,15 +2591,8 @@ static void iwl3945_alive_start(struct iwl_priv *priv)
2637 2591
2638 priv->cfg->ops->smgmt->clear_station_table(priv); 2592 priv->cfg->ops->smgmt->clear_station_table(priv);
2639 2593
2640 rc = iwl_grab_nic_access(priv);
2641 if (rc) {
2642 IWL_WARN(priv, "Can not read RFKILL status from adapter\n");
2643 return;
2644 }
2645
2646 rfkill = iwl_read_prph(priv, APMG_RFKILL_REG); 2594 rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
2647 IWL_DEBUG_INFO(priv, "RFKILL status: 0x%x\n", rfkill); 2595 IWL_DEBUG_INFO(priv, "RFKILL status: 0x%x\n", rfkill);
2648 iwl_release_nic_access(priv);
2649 2596
2650 if (rfkill & 0x1) { 2597 if (rfkill & 0x1) {
2651 clear_bit(STATUS_RF_KILL_HW, &priv->status); 2598 clear_bit(STATUS_RF_KILL_HW, &priv->status);
@@ -2791,13 +2738,8 @@ static void __iwl3945_down(struct iwl_priv *priv)
2791 iwl3945_hw_txq_ctx_stop(priv); 2738 iwl3945_hw_txq_ctx_stop(priv);
2792 iwl3945_hw_rxq_stop(priv); 2739 iwl3945_hw_rxq_stop(priv);
2793 2740
2794 spin_lock_irqsave(&priv->lock, flags); 2741 iwl_write_prph(priv, APMG_CLK_DIS_REG,
2795 if (!iwl_grab_nic_access(priv)) { 2742 APMG_CLK_VAL_DMA_CLK_RQT);
2796 iwl_write_prph(priv, APMG_CLK_DIS_REG,
2797 APMG_CLK_VAL_DMA_CLK_RQT);
2798 iwl_release_nic_access(priv);
2799 }
2800 spin_unlock_irqrestore(&priv->lock, flags);
2801 2743
2802 udelay(5); 2744 udelay(5);
2803 2745
@@ -4288,6 +4230,11 @@ static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e
4288 * PCI Tx retries from interfering with C3 CPU state */ 4230 * PCI Tx retries from interfering with C3 CPU state */
4289 pci_write_config_byte(pdev, 0x41, 0x00); 4231 pci_write_config_byte(pdev, 0x41, 0x00);
4290 4232
4233 /* this spin lock will be used in apm_ops.init and EEPROM access
4234 * we should init now
4235 */
4236 spin_lock_init(&priv->reg_lock);
4237
4291 /* amp init */ 4238 /* amp init */
4292 err = priv->cfg->ops->lib->apm_ops.init(priv); 4239 err = priv->cfg->ops->lib->apm_ops.init(priv);
4293 if (err < 0) { 4240 if (err < 0) {
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-08 21:11:44 -0400