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authorJeff Kirsher <jeffrey.t.kirsher@intel.com>2006-01-12 19:51:16 -0500
committerJeff Garzik <jgarzik@pobox.com>2006-01-17 07:48:03 -0500
commit1e613fd9d64aba9945ddb3b7f1107127ee8a9835 (patch)
treeaa6de84f7790d96daffcb20a6ffc22ee498db724 /drivers/net
parente8da8be146e6043fb4b60a222be0014a0fb46d24 (diff)
[PATCH] e1000: Added interrupt auto mask support
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Signed-off-by: John Ronciak <john.ronciak@intel.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/e1000/e1000_main.c31
1 files changed, 25 insertions, 6 deletions
diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c
index 6d7f9c9df085..53f87fe511c5 100644
--- a/drivers/net/e1000/e1000_main.c
+++ b/drivers/net/e1000/e1000_main.c
@@ -1736,10 +1736,15 @@ e1000_configure_rx(struct e1000_adapter *adapter)
1736 } 1736 }
1737 1737
1738 if (hw->mac_type >= e1000_82571) { 1738 if (hw->mac_type >= e1000_82571) {
1739 /* Reset delay timers after every interrupt */
1740 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1739 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1740 /* Reset delay timers after every interrupt */
1741 ctrl_ext |= E1000_CTRL_EXT_CANC; 1741 ctrl_ext |= E1000_CTRL_EXT_CANC;
1742#ifdef CONFIG_E1000_NAPI
1743 /* Auto-Mask interrupts upon ICR read. */
1744 ctrl_ext |= E1000_CTRL_EXT_IAME;
1745#endif
1742 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1746 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1747 E1000_WRITE_REG(hw, IAM, ~0);
1743 E1000_WRITE_FLUSH(hw); 1748 E1000_WRITE_FLUSH(hw);
1744 } 1749 }
1745 1750
@@ -3244,12 +3249,24 @@ e1000_intr(int irq, void *data, struct pt_regs *regs)
3244 struct e1000_adapter *adapter = netdev_priv(netdev); 3249 struct e1000_adapter *adapter = netdev_priv(netdev);
3245 struct e1000_hw *hw = &adapter->hw; 3250 struct e1000_hw *hw = &adapter->hw;
3246 uint32_t icr = E1000_READ_REG(hw, ICR); 3251 uint32_t icr = E1000_READ_REG(hw, ICR);
3247#if defined(CONFIG_E1000_NAPI) && defined(CONFIG_E1000_MQ) || !defined(CONFIG_E1000_NAPI) 3252#ifndef CONFIG_E1000_NAPI
3248 int i; 3253 int i;
3254#else
3255 /* Interrupt Auto-Mask...upon reading ICR,
3256 * interrupts are masked. No need for the
3257 * IMC write, but it does mean we should
3258 * account for it ASAP. */
3259 if (likely(hw->mac_type >= e1000_82571))
3260 atomic_inc(&adapter->irq_sem);
3249#endif 3261#endif
3250 3262
3251 if(unlikely(!icr)) 3263 if (unlikely(!icr)) {
3264#ifdef CONFIG_E1000_NAPI
3265 if (hw->mac_type >= e1000_82571)
3266 e1000_irq_enable(adapter);
3267#endif
3252 return IRQ_NONE; /* Not our interrupt */ 3268 return IRQ_NONE; /* Not our interrupt */
3269 }
3253 3270
3254 if(unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) { 3271 if(unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
3255 hw->get_link_status = 1; 3272 hw->get_link_status = 1;
@@ -3257,9 +3274,11 @@ e1000_intr(int irq, void *data, struct pt_regs *regs)
3257 } 3274 }
3258 3275
3259#ifdef CONFIG_E1000_NAPI 3276#ifdef CONFIG_E1000_NAPI
3260 atomic_inc(&adapter->irq_sem); 3277 if (unlikely(hw->mac_type < e1000_82571)) {
3261 E1000_WRITE_REG(hw, IMC, ~0); 3278 atomic_inc(&adapter->irq_sem);
3262 E1000_WRITE_FLUSH(hw); 3279 E1000_WRITE_REG(hw, IMC, ~0);
3280 E1000_WRITE_FLUSH(hw);
3281 }
3263#ifdef CONFIG_E1000_MQ 3282#ifdef CONFIG_E1000_MQ
3264 if (atomic_read(&adapter->rx_sched_call_data.count) == 0) { 3283 if (atomic_read(&adapter->rx_sched_call_data.count) == 0) {
3265 /* We must setup the cpumask once count == 0 since 3284 /* We must setup the cpumask once count == 0 since