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authorYitchak Gertner <gertner@broadcom.com>2008-08-13 18:52:08 -0400
committerDavid S. Miller <davem@davemloft.net>2008-08-13 19:03:37 -0400
commit12469401bc5aebb1c1482db1253c986cf8221281 (patch)
tree34efb2b4d7eb2d13b9560b0e9a6d425969fba68e /drivers/net
parent5c862848172846a7aa88d0a564eb8998ecac2f0d (diff)
bnx2x: Delay in while loops
Delay in while loops The delay in the loop should be after the change. This has very little effect (can save one delay) but it is the right thing to do Signed-off-by: Yitchak Gertner <gertner@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/bnx2x_main.c25
1 files changed, 11 insertions, 14 deletions
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c
index b2886db57048..ea6fcf3514b9 100644
--- a/drivers/net/bnx2x_main.c
+++ b/drivers/net/bnx2x_main.c
@@ -235,17 +235,16 @@ void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
235 while (*wb_comp != DMAE_COMP_VAL) { 235 while (*wb_comp != DMAE_COMP_VAL) {
236 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp); 236 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
237 237
238 /* adjust delay for emulation/FPGA */
239 if (CHIP_REV_IS_SLOW(bp))
240 msleep(100);
241 else
242 udelay(5);
243
244 if (!cnt) { 238 if (!cnt) {
245 BNX2X_ERR("dmae timeout!\n"); 239 BNX2X_ERR("dmae timeout!\n");
246 break; 240 break;
247 } 241 }
248 cnt--; 242 cnt--;
243 /* adjust delay for emulation/FPGA */
244 if (CHIP_REV_IS_SLOW(bp))
245 msleep(100);
246 else
247 udelay(5);
249 } 248 }
250 249
251 mutex_unlock(&bp->dmae_mutex); 250 mutex_unlock(&bp->dmae_mutex);
@@ -308,17 +307,16 @@ void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
308 307
309 while (*wb_comp != DMAE_COMP_VAL) { 308 while (*wb_comp != DMAE_COMP_VAL) {
310 309
311 /* adjust delay for emulation/FPGA */
312 if (CHIP_REV_IS_SLOW(bp))
313 msleep(100);
314 else
315 udelay(5);
316
317 if (!cnt) { 310 if (!cnt) {
318 BNX2X_ERR("dmae timeout!\n"); 311 BNX2X_ERR("dmae timeout!\n");
319 break; 312 break;
320 } 313 }
321 cnt--; 314 cnt--;
315 /* adjust delay for emulation/FPGA */
316 if (CHIP_REV_IS_SLOW(bp))
317 msleep(100);
318 else
319 udelay(5);
322 } 320 }
323 DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n", 321 DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
324 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], 322 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
@@ -3094,12 +3092,12 @@ static int bnx2x_stats_comp(struct bnx2x *bp)
3094 3092
3095 might_sleep(); 3093 might_sleep();
3096 while (*stats_comp != DMAE_COMP_VAL) { 3094 while (*stats_comp != DMAE_COMP_VAL) {
3097 msleep(1);
3098 if (!cnt) { 3095 if (!cnt) {
3099 BNX2X_ERR("timeout waiting for stats finished\n"); 3096 BNX2X_ERR("timeout waiting for stats finished\n");
3100 break; 3097 break;
3101 } 3098 }
3102 cnt--; 3099 cnt--;
3100 msleep(1);
3103 } 3101 }
3104 return 1; 3102 return 1;
3105} 3103}
@@ -6483,7 +6481,6 @@ static int bnx2x_stop_leading(struct bnx2x *bp)
6483 so there is not much to do if this times out 6481 so there is not much to do if this times out
6484 */ 6482 */
6485 while (dsb_sp_prod_idx == *bp->dsb_sp_prod) { 6483 while (dsb_sp_prod_idx == *bp->dsb_sp_prod) {
6486 msleep(1);
6487 if (!cnt) { 6484 if (!cnt) {
6488 DP(NETIF_MSG_IFDOWN, "timeout waiting for port del " 6485 DP(NETIF_MSG_IFDOWN, "timeout waiting for port del "
6489 "dsb_sp_prod 0x%x != dsb_sp_prod_idx 0x%x\n", 6486 "dsb_sp_prod 0x%x != dsb_sp_prod_idx 0x%x\n",