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authorJeff Garzik <jgarzik@pretzel.yyz.us>2005-06-26 17:11:03 -0400
committerJeff Garzik <jgarzik@pobox.com>2005-06-26 17:11:03 -0400
commit8b0ee07e108b2eefdab5bb73f33223f18926c3b2 (patch)
treef68ca04180c5488301a40ec212ef2eb2467cf56c /drivers/net
parent4638aef40ba9ebb9734caeed1f373c24015259fd (diff)
parent8678887e7fb43cd6c9be6c9807b05e77848e0920 (diff)
Merge upstream (approx. 2.6.12-git8) into 'janitor' branch of netdev-2.6.
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/3c59x.c5
-rw-r--r--drivers/net/8139cp.c100
-rw-r--r--drivers/net/8139too.c196
-rw-r--r--drivers/net/8390.c4
-rw-r--r--drivers/net/Kconfig57
-rw-r--r--drivers/net/Makefile7
-rw-r--r--drivers/net/Space.c6
-rwxr-xr-xdrivers/net/amd8111e.c24
-rw-r--r--drivers/net/appletalk/ltpc.c6
-rw-r--r--drivers/net/arm/etherh.c16
-rw-r--r--drivers/net/au1000_eth.c10
-rw-r--r--drivers/net/bmac.c2
-rw-r--r--drivers/net/bnx2.c5530
-rw-r--r--drivers/net/bnx2.h4352
-rw-r--r--drivers/net/bnx2_fw.h2468
-rw-r--r--drivers/net/bonding/bond_main.c2
-rw-r--r--drivers/net/dm9000.c1219
-rw-r--r--drivers/net/dm9000.h135
-rw-r--r--drivers/net/e100.c165
-rw-r--r--drivers/net/e1000/e1000.h37
-rw-r--r--drivers/net/e1000/e1000_ethtool.c105
-rw-r--r--drivers/net/e1000/e1000_hw.c1987
-rw-r--r--drivers/net/e1000/e1000_hw.h570
-rw-r--r--drivers/net/e1000/e1000_main.c1148
-rw-r--r--drivers/net/e1000/e1000_osdep.h32
-rw-r--r--drivers/net/e1000/e1000_param.c3
-rw-r--r--drivers/net/fmv18x.c689
-rw-r--r--drivers/net/forcedeth.c103
-rw-r--r--drivers/net/hamradio/6pack.c2
-rw-r--r--drivers/net/hamradio/baycom_epp.c126
-rw-r--r--drivers/net/hamradio/mkiss.c2
-rw-r--r--drivers/net/ibm_emac/ibm_emac_core.c2
-rw-r--r--drivers/net/irda/Kconfig2
-rw-r--r--drivers/net/irda/irtty-sir.c2
-rw-r--r--drivers/net/irda/sir_kthread.c3
-rw-r--r--drivers/net/irda/stir4200.c4
-rw-r--r--drivers/net/iseries_veth.c41
-rw-r--r--drivers/net/ixgb/ixgb.h2
-rw-r--r--drivers/net/ixgb/ixgb_ee.c24
-rw-r--r--drivers/net/ixgb/ixgb_ethtool.c4
-rw-r--r--drivers/net/ixgb/ixgb_main.c154
-rw-r--r--drivers/net/ixgb/ixgb_osdep.h3
-rw-r--r--drivers/net/natsemi.c6
-rw-r--r--drivers/net/ns83820.c69
-rw-r--r--drivers/net/pcmcia/3c574_cs.c3
-rw-r--r--drivers/net/pcmcia/pcnet_cs.c17
-rw-r--r--drivers/net/pcnet32.c7
-rw-r--r--drivers/net/ppp_async.c2
-rw-r--r--drivers/net/ppp_generic.c191
-rw-r--r--drivers/net/ppp_synctty.c2
-rw-r--r--drivers/net/r8169.c345
-rw-r--r--drivers/net/shaper.c86
-rw-r--r--drivers/net/sis900.c52
-rw-r--r--drivers/net/sk98lin/skge.c8
-rw-r--r--drivers/net/sk_g16.c2066
-rw-r--r--drivers/net/sk_g16.h165
-rw-r--r--drivers/net/skge.c3386
-rw-r--r--drivers/net/skge.h3005
-rw-r--r--drivers/net/slip.c16
-rw-r--r--drivers/net/smc91x.c58
-rw-r--r--drivers/net/smc91x.h15
-rw-r--r--drivers/net/starfire.c142
-rw-r--r--drivers/net/starfire_firmware.h346
-rw-r--r--drivers/net/tg3.c1383
-rw-r--r--drivers/net/tg3.h32
-rw-r--r--drivers/net/tlan.c16
-rw-r--r--drivers/net/tokenring/ibmtr.c11
-rw-r--r--drivers/net/tulip/media.c1
-rw-r--r--drivers/net/tulip/tulip_core.c2
-rw-r--r--drivers/net/wan/Kconfig2
-rw-r--r--drivers/net/wan/cosa.c12
-rw-r--r--drivers/net/wan/hdlc_fr.c320
-rw-r--r--drivers/net/wan/hdlc_generic.c16
-rw-r--r--drivers/net/wan/lmc/lmc_main.c8
-rw-r--r--drivers/net/wan/x25_asy.c2
-rw-r--r--drivers/net/wireless/Kconfig2
-rw-r--r--drivers/net/wireless/airo.c152
-rw-r--r--drivers/net/wireless/atmel_cs.c1
-rw-r--r--drivers/net/wireless/orinoco.c332
-rw-r--r--drivers/net/wireless/orinoco.h1
-rw-r--r--drivers/net/wireless/strip.c2
81 files changed, 26303 insertions, 5328 deletions
diff --git a/drivers/net/3c59x.c b/drivers/net/3c59x.c
index b5e076043431..80ec9aa575bb 100644
--- a/drivers/net/3c59x.c
+++ b/drivers/net/3c59x.c
@@ -2202,9 +2202,8 @@ boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2202 2202
2203 if (vortex_debug > 6) { 2203 if (vortex_debug > 6) {
2204 printk(KERN_DEBUG "boomerang_start_xmit()\n"); 2204 printk(KERN_DEBUG "boomerang_start_xmit()\n");
2205 if (vortex_debug > 3) 2205 printk(KERN_DEBUG "%s: Trying to send a packet, Tx index %d.\n",
2206 printk(KERN_DEBUG "%s: Trying to send a packet, Tx index %d.\n", 2206 dev->name, vp->cur_tx);
2207 dev->name, vp->cur_tx);
2208 } 2207 }
2209 2208
2210 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) { 2209 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
diff --git a/drivers/net/8139cp.c b/drivers/net/8139cp.c
index ca4c9ac7e115..ca7746dd164f 100644
--- a/drivers/net/8139cp.c
+++ b/drivers/net/8139cp.c
@@ -54,6 +54,7 @@
54 54
55#include <linux/config.h> 55#include <linux/config.h>
56#include <linux/module.h> 56#include <linux/module.h>
57#include <linux/moduleparam.h>
57#include <linux/kernel.h> 58#include <linux/kernel.h>
58#include <linux/compiler.h> 59#include <linux/compiler.h>
59#include <linux/netdevice.h> 60#include <linux/netdevice.h>
@@ -92,16 +93,17 @@ KERN_INFO DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE
92 93
93MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>"); 94MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
94MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver"); 95MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
96MODULE_VERSION(DRV_VERSION);
95MODULE_LICENSE("GPL"); 97MODULE_LICENSE("GPL");
96 98
97static int debug = -1; 99static int debug = -1;
98MODULE_PARM (debug, "i"); 100module_param(debug, int, 0);
99MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number"); 101MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
100 102
101/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 103/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
102 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 104 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
103static int multicast_filter_limit = 32; 105static int multicast_filter_limit = 32;
104MODULE_PARM (multicast_filter_limit, "i"); 106module_param(multicast_filter_limit, int, 0);
105MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses"); 107MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
106 108
107#define PFX DRV_NAME ": " 109#define PFX DRV_NAME ": "
@@ -187,6 +189,9 @@ enum {
187 RingEnd = (1 << 30), /* End of descriptor ring */ 189 RingEnd = (1 << 30), /* End of descriptor ring */
188 FirstFrag = (1 << 29), /* First segment of a packet */ 190 FirstFrag = (1 << 29), /* First segment of a packet */
189 LastFrag = (1 << 28), /* Final segment of a packet */ 191 LastFrag = (1 << 28), /* Final segment of a packet */
192 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
193 MSSShift = 16, /* MSS value position */
194 MSSMask = 0xfff, /* MSS value: 11 bits */
190 TxError = (1 << 23), /* Tx error summary */ 195 TxError = (1 << 23), /* Tx error summary */
191 RxError = (1 << 20), /* Rx error summary */ 196 RxError = (1 << 20), /* Rx error summary */
192 IPCS = (1 << 18), /* Calculate IP checksum */ 197 IPCS = (1 << 18), /* Calculate IP checksum */
@@ -313,7 +318,7 @@ struct cp_desc {
313struct ring_info { 318struct ring_info {
314 struct sk_buff *skb; 319 struct sk_buff *skb;
315 dma_addr_t mapping; 320 dma_addr_t mapping;
316 unsigned frag; 321 u32 len;
317}; 322};
318 323
319struct cp_dma_stats { 324struct cp_dma_stats {
@@ -395,6 +400,9 @@ struct cp_private {
395static void __cp_set_rx_mode (struct net_device *dev); 400static void __cp_set_rx_mode (struct net_device *dev);
396static void cp_tx (struct cp_private *cp); 401static void cp_tx (struct cp_private *cp);
397static void cp_clean_rings (struct cp_private *cp); 402static void cp_clean_rings (struct cp_private *cp);
403#ifdef CONFIG_NET_POLL_CONTROLLER
404static void cp_poll_controller(struct net_device *dev);
405#endif
398 406
399static struct pci_device_id cp_pci_tbl[] = { 407static struct pci_device_id cp_pci_tbl[] = {
400 { PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139, 408 { PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139,
@@ -689,6 +697,19 @@ cp_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
689 return IRQ_HANDLED; 697 return IRQ_HANDLED;
690} 698}
691 699
700#ifdef CONFIG_NET_POLL_CONTROLLER
701/*
702 * Polling receive - used by netconsole and other diagnostic tools
703 * to allow network i/o with interrupts disabled.
704 */
705static void cp_poll_controller(struct net_device *dev)
706{
707 disable_irq(dev->irq);
708 cp_interrupt(dev->irq, dev, NULL);
709 enable_irq(dev->irq);
710}
711#endif
712
692static void cp_tx (struct cp_private *cp) 713static void cp_tx (struct cp_private *cp)
693{ 714{
694 unsigned tx_head = cp->tx_head; 715 unsigned tx_head = cp->tx_head;
@@ -708,7 +729,7 @@ static void cp_tx (struct cp_private *cp)
708 BUG(); 729 BUG();
709 730
710 pci_unmap_single(cp->pdev, cp->tx_skb[tx_tail].mapping, 731 pci_unmap_single(cp->pdev, cp->tx_skb[tx_tail].mapping,
711 skb->len, PCI_DMA_TODEVICE); 732 cp->tx_skb[tx_tail].len, PCI_DMA_TODEVICE);
712 733
713 if (status & LastFrag) { 734 if (status & LastFrag) {
714 if (status & (TxError | TxFIFOUnder)) { 735 if (status & (TxError | TxFIFOUnder)) {
@@ -750,10 +771,11 @@ static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
750{ 771{
751 struct cp_private *cp = netdev_priv(dev); 772 struct cp_private *cp = netdev_priv(dev);
752 unsigned entry; 773 unsigned entry;
753 u32 eor; 774 u32 eor, flags;
754#if CP_VLAN_TAG_USED 775#if CP_VLAN_TAG_USED
755 u32 vlan_tag = 0; 776 u32 vlan_tag = 0;
756#endif 777#endif
778 int mss = 0;
757 779
758 spin_lock_irq(&cp->lock); 780 spin_lock_irq(&cp->lock);
759 781
@@ -773,6 +795,9 @@ static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
773 795
774 entry = cp->tx_head; 796 entry = cp->tx_head;
775 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0; 797 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
798 if (dev->features & NETIF_F_TSO)
799 mss = skb_shinfo(skb)->tso_size;
800
776 if (skb_shinfo(skb)->nr_frags == 0) { 801 if (skb_shinfo(skb)->nr_frags == 0) {
777 struct cp_desc *txd = &cp->tx_ring[entry]; 802 struct cp_desc *txd = &cp->tx_ring[entry];
778 u32 len; 803 u32 len;
@@ -784,26 +809,26 @@ static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
784 txd->addr = cpu_to_le64(mapping); 809 txd->addr = cpu_to_le64(mapping);
785 wmb(); 810 wmb();
786 811
787 if (skb->ip_summed == CHECKSUM_HW) { 812 flags = eor | len | DescOwn | FirstFrag | LastFrag;
813
814 if (mss)
815 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
816 else if (skb->ip_summed == CHECKSUM_HW) {
788 const struct iphdr *ip = skb->nh.iph; 817 const struct iphdr *ip = skb->nh.iph;
789 if (ip->protocol == IPPROTO_TCP) 818 if (ip->protocol == IPPROTO_TCP)
790 txd->opts1 = cpu_to_le32(eor | len | DescOwn | 819 flags |= IPCS | TCPCS;
791 FirstFrag | LastFrag |
792 IPCS | TCPCS);
793 else if (ip->protocol == IPPROTO_UDP) 820 else if (ip->protocol == IPPROTO_UDP)
794 txd->opts1 = cpu_to_le32(eor | len | DescOwn | 821 flags |= IPCS | UDPCS;
795 FirstFrag | LastFrag |
796 IPCS | UDPCS);
797 else 822 else
798 BUG(); 823 WARN_ON(1); /* we need a WARN() */
799 } else 824 }
800 txd->opts1 = cpu_to_le32(eor | len | DescOwn | 825
801 FirstFrag | LastFrag); 826 txd->opts1 = cpu_to_le32(flags);
802 wmb(); 827 wmb();
803 828
804 cp->tx_skb[entry].skb = skb; 829 cp->tx_skb[entry].skb = skb;
805 cp->tx_skb[entry].mapping = mapping; 830 cp->tx_skb[entry].mapping = mapping;
806 cp->tx_skb[entry].frag = 0; 831 cp->tx_skb[entry].len = len;
807 entry = NEXT_TX(entry); 832 entry = NEXT_TX(entry);
808 } else { 833 } else {
809 struct cp_desc *txd; 834 struct cp_desc *txd;
@@ -821,7 +846,7 @@ static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
821 first_len, PCI_DMA_TODEVICE); 846 first_len, PCI_DMA_TODEVICE);
822 cp->tx_skb[entry].skb = skb; 847 cp->tx_skb[entry].skb = skb;
823 cp->tx_skb[entry].mapping = first_mapping; 848 cp->tx_skb[entry].mapping = first_mapping;
824 cp->tx_skb[entry].frag = 1; 849 cp->tx_skb[entry].len = first_len;
825 entry = NEXT_TX(entry); 850 entry = NEXT_TX(entry);
826 851
827 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { 852 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
@@ -837,16 +862,19 @@ static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
837 len, PCI_DMA_TODEVICE); 862 len, PCI_DMA_TODEVICE);
838 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0; 863 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
839 864
840 if (skb->ip_summed == CHECKSUM_HW) { 865 ctrl = eor | len | DescOwn;
841 ctrl = eor | len | DescOwn | IPCS; 866
867 if (mss)
868 ctrl |= LargeSend |
869 ((mss & MSSMask) << MSSShift);
870 else if (skb->ip_summed == CHECKSUM_HW) {
842 if (ip->protocol == IPPROTO_TCP) 871 if (ip->protocol == IPPROTO_TCP)
843 ctrl |= TCPCS; 872 ctrl |= IPCS | TCPCS;
844 else if (ip->protocol == IPPROTO_UDP) 873 else if (ip->protocol == IPPROTO_UDP)
845 ctrl |= UDPCS; 874 ctrl |= IPCS | UDPCS;
846 else 875 else
847 BUG(); 876 BUG();
848 } else 877 }
849 ctrl = eor | len | DescOwn;
850 878
851 if (frag == skb_shinfo(skb)->nr_frags - 1) 879 if (frag == skb_shinfo(skb)->nr_frags - 1)
852 ctrl |= LastFrag; 880 ctrl |= LastFrag;
@@ -861,7 +889,7 @@ static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
861 889
862 cp->tx_skb[entry].skb = skb; 890 cp->tx_skb[entry].skb = skb;
863 cp->tx_skb[entry].mapping = mapping; 891 cp->tx_skb[entry].mapping = mapping;
864 cp->tx_skb[entry].frag = frag + 2; 892 cp->tx_skb[entry].len = len;
865 entry = NEXT_TX(entry); 893 entry = NEXT_TX(entry);
866 } 894 }
867 895
@@ -1075,7 +1103,6 @@ static int cp_refill_rx (struct cp_private *cp)
1075 cp->rx_skb[i].mapping = pci_map_single(cp->pdev, 1103 cp->rx_skb[i].mapping = pci_map_single(cp->pdev,
1076 skb->tail, cp->rx_buf_sz, PCI_DMA_FROMDEVICE); 1104 skb->tail, cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1077 cp->rx_skb[i].skb = skb; 1105 cp->rx_skb[i].skb = skb;
1078 cp->rx_skb[i].frag = 0;
1079 1106
1080 cp->rx_ring[i].opts2 = 0; 1107 cp->rx_ring[i].opts2 = 0;
1081 cp->rx_ring[i].addr = cpu_to_le64(cp->rx_skb[i].mapping); 1108 cp->rx_ring[i].addr = cpu_to_le64(cp->rx_skb[i].mapping);
@@ -1127,9 +1154,6 @@ static void cp_clean_rings (struct cp_private *cp)
1127{ 1154{
1128 unsigned i; 1155 unsigned i;
1129 1156
1130 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1131 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1132
1133 for (i = 0; i < CP_RX_RING_SIZE; i++) { 1157 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1134 if (cp->rx_skb[i].skb) { 1158 if (cp->rx_skb[i].skb) {
1135 pci_unmap_single(cp->pdev, cp->rx_skb[i].mapping, 1159 pci_unmap_single(cp->pdev, cp->rx_skb[i].mapping,
@@ -1141,13 +1165,18 @@ static void cp_clean_rings (struct cp_private *cp)
1141 for (i = 0; i < CP_TX_RING_SIZE; i++) { 1165 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1142 if (cp->tx_skb[i].skb) { 1166 if (cp->tx_skb[i].skb) {
1143 struct sk_buff *skb = cp->tx_skb[i].skb; 1167 struct sk_buff *skb = cp->tx_skb[i].skb;
1168
1144 pci_unmap_single(cp->pdev, cp->tx_skb[i].mapping, 1169 pci_unmap_single(cp->pdev, cp->tx_skb[i].mapping,
1145 skb->len, PCI_DMA_TODEVICE); 1170 cp->tx_skb[i].len, PCI_DMA_TODEVICE);
1146 dev_kfree_skb(skb); 1171 if (le32_to_cpu(cp->tx_ring[i].opts1) & LastFrag)
1172 dev_kfree_skb(skb);
1147 cp->net_stats.tx_dropped++; 1173 cp->net_stats.tx_dropped++;
1148 } 1174 }
1149 } 1175 }
1150 1176
1177 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1178 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1179
1151 memset(&cp->rx_skb, 0, sizeof(struct ring_info) * CP_RX_RING_SIZE); 1180 memset(&cp->rx_skb, 0, sizeof(struct ring_info) * CP_RX_RING_SIZE);
1152 memset(&cp->tx_skb, 0, sizeof(struct ring_info) * CP_TX_RING_SIZE); 1181 memset(&cp->tx_skb, 0, sizeof(struct ring_info) * CP_TX_RING_SIZE);
1153} 1182}
@@ -1539,6 +1568,8 @@ static struct ethtool_ops cp_ethtool_ops = {
1539 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */ 1568 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */
1540 .get_sg = ethtool_op_get_sg, 1569 .get_sg = ethtool_op_get_sg,
1541 .set_sg = ethtool_op_set_sg, 1570 .set_sg = ethtool_op_set_sg,
1571 .get_tso = ethtool_op_get_tso,
1572 .set_tso = ethtool_op_set_tso,
1542 .get_regs = cp_get_regs, 1573 .get_regs = cp_get_regs,
1543 .get_wol = cp_get_wol, 1574 .get_wol = cp_get_wol,
1544 .set_wol = cp_set_wol, 1575 .set_wol = cp_set_wol,
@@ -1750,6 +1781,9 @@ static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1750 dev->get_stats = cp_get_stats; 1781 dev->get_stats = cp_get_stats;
1751 dev->do_ioctl = cp_ioctl; 1782 dev->do_ioctl = cp_ioctl;
1752 dev->poll = cp_rx_poll; 1783 dev->poll = cp_rx_poll;
1784#ifdef CONFIG_NET_POLL_CONTROLLER
1785 dev->poll_controller = cp_poll_controller;
1786#endif
1753 dev->weight = 16; /* arbitrary? from NAPI_HOWTO.txt. */ 1787 dev->weight = 16; /* arbitrary? from NAPI_HOWTO.txt. */
1754#ifdef BROKEN 1788#ifdef BROKEN
1755 dev->change_mtu = cp_change_mtu; 1789 dev->change_mtu = cp_change_mtu;
@@ -1769,6 +1803,10 @@ static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1769 if (pci_using_dac) 1803 if (pci_using_dac)
1770 dev->features |= NETIF_F_HIGHDMA; 1804 dev->features |= NETIF_F_HIGHDMA;
1771 1805
1806#if 0 /* disabled by default until verified */
1807 dev->features |= NETIF_F_TSO;
1808#endif
1809
1772 dev->irq = pdev->irq; 1810 dev->irq = pdev->irq;
1773 1811
1774 rc = register_netdev(dev); 1812 rc = register_netdev(dev);
diff --git a/drivers/net/8139too.c b/drivers/net/8139too.c
index d4bd20c21a1f..5a4a08a7c951 100644
--- a/drivers/net/8139too.c
+++ b/drivers/net/8139too.c
@@ -569,7 +569,7 @@ struct rtl_extra_stats {
569}; 569};
570 570
571struct rtl8139_private { 571struct rtl8139_private {
572 void *mmio_addr; 572 void __iomem *mmio_addr;
573 int drv_flags; 573 int drv_flags;
574 struct pci_dev *pci_dev; 574 struct pci_dev *pci_dev;
575 u32 msg_enable; 575 u32 msg_enable;
@@ -614,7 +614,7 @@ MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered mu
614MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps"); 614MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
615MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)"); 615MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
616 616
617static int read_eeprom (void *ioaddr, int location, int addr_len); 617static int read_eeprom (void __iomem *ioaddr, int location, int addr_len);
618static int rtl8139_open (struct net_device *dev); 618static int rtl8139_open (struct net_device *dev);
619static int mdio_read (struct net_device *dev, int phy_id, int location); 619static int mdio_read (struct net_device *dev, int phy_id, int location);
620static void mdio_write (struct net_device *dev, int phy_id, int location, 620static void mdio_write (struct net_device *dev, int phy_id, int location,
@@ -638,46 +638,20 @@ static void __set_rx_mode (struct net_device *dev);
638static void rtl8139_hw_start (struct net_device *dev); 638static void rtl8139_hw_start (struct net_device *dev);
639static struct ethtool_ops rtl8139_ethtool_ops; 639static struct ethtool_ops rtl8139_ethtool_ops;
640 640
641#ifdef USE_IO_OPS
642
643#define RTL_R8(reg) inb (((unsigned long)ioaddr) + (reg))
644#define RTL_R16(reg) inw (((unsigned long)ioaddr) + (reg))
645#define RTL_R32(reg) ((unsigned long) inl (((unsigned long)ioaddr) + (reg)))
646#define RTL_W8(reg, val8) outb ((val8), ((unsigned long)ioaddr) + (reg))
647#define RTL_W16(reg, val16) outw ((val16), ((unsigned long)ioaddr) + (reg))
648#define RTL_W32(reg, val32) outl ((val32), ((unsigned long)ioaddr) + (reg))
649#define RTL_W8_F RTL_W8
650#define RTL_W16_F RTL_W16
651#define RTL_W32_F RTL_W32
652#undef readb
653#undef readw
654#undef readl
655#undef writeb
656#undef writew
657#undef writel
658#define readb(addr) inb((unsigned long)(addr))
659#define readw(addr) inw((unsigned long)(addr))
660#define readl(addr) inl((unsigned long)(addr))
661#define writeb(val,addr) outb((val),(unsigned long)(addr))
662#define writew(val,addr) outw((val),(unsigned long)(addr))
663#define writel(val,addr) outl((val),(unsigned long)(addr))
664
665#else
666
667/* write MMIO register, with flush */ 641/* write MMIO register, with flush */
668/* Flush avoids rtl8139 bug w/ posted MMIO writes */ 642/* Flush avoids rtl8139 bug w/ posted MMIO writes */
669#define RTL_W8_F(reg, val8) do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0) 643#define RTL_W8_F(reg, val8) do { iowrite8 ((val8), ioaddr + (reg)); ioread8 (ioaddr + (reg)); } while (0)
670#define RTL_W16_F(reg, val16) do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0) 644#define RTL_W16_F(reg, val16) do { iowrite16 ((val16), ioaddr + (reg)); ioread16 (ioaddr + (reg)); } while (0)
671#define RTL_W32_F(reg, val32) do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0) 645#define RTL_W32_F(reg, val32) do { iowrite32 ((val32), ioaddr + (reg)); ioread32 (ioaddr + (reg)); } while (0)
672 646
673 647
674#define MMIO_FLUSH_AUDIT_COMPLETE 1 648#define MMIO_FLUSH_AUDIT_COMPLETE 1
675#if MMIO_FLUSH_AUDIT_COMPLETE 649#if MMIO_FLUSH_AUDIT_COMPLETE
676 650
677/* write MMIO register */ 651/* write MMIO register */
678#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) 652#define RTL_W8(reg, val8) iowrite8 ((val8), ioaddr + (reg))
679#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) 653#define RTL_W16(reg, val16) iowrite16 ((val16), ioaddr + (reg))
680#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) 654#define RTL_W32(reg, val32) iowrite32 ((val32), ioaddr + (reg))
681 655
682#else 656#else
683 657
@@ -689,11 +663,9 @@ static struct ethtool_ops rtl8139_ethtool_ops;
689#endif /* MMIO_FLUSH_AUDIT_COMPLETE */ 663#endif /* MMIO_FLUSH_AUDIT_COMPLETE */
690 664
691/* read MMIO register */ 665/* read MMIO register */
692#define RTL_R8(reg) readb (ioaddr + (reg)) 666#define RTL_R8(reg) ioread8 (ioaddr + (reg))
693#define RTL_R16(reg) readw (ioaddr + (reg)) 667#define RTL_R16(reg) ioread16 (ioaddr + (reg))
694#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) 668#define RTL_R32(reg) ((unsigned long) ioread32 (ioaddr + (reg)))
695
696#endif /* USE_IO_OPS */
697 669
698 670
699static const u16 rtl8139_intr_mask = 671static const u16 rtl8139_intr_mask =
@@ -740,10 +712,13 @@ static void __rtl8139_cleanup_dev (struct net_device *dev)
740 assert (tp->pci_dev != NULL); 712 assert (tp->pci_dev != NULL);
741 pdev = tp->pci_dev; 713 pdev = tp->pci_dev;
742 714
743#ifndef USE_IO_OPS 715#ifdef USE_IO_OPS
716 if (tp->mmio_addr)
717 ioport_unmap (tp->mmio_addr);
718#else
744 if (tp->mmio_addr) 719 if (tp->mmio_addr)
745 iounmap (tp->mmio_addr); 720 pci_iounmap (pdev, tp->mmio_addr);
746#endif /* !USE_IO_OPS */ 721#endif /* USE_IO_OPS */
747 722
748 /* it's ok to call this even if we have no regions to free */ 723 /* it's ok to call this even if we have no regions to free */
749 pci_release_regions (pdev); 724 pci_release_regions (pdev);
@@ -753,7 +728,7 @@ static void __rtl8139_cleanup_dev (struct net_device *dev)
753} 728}
754 729
755 730
756static void rtl8139_chip_reset (void *ioaddr) 731static void rtl8139_chip_reset (void __iomem *ioaddr)
757{ 732{
758 int i; 733 int i;
759 734
@@ -773,7 +748,7 @@ static void rtl8139_chip_reset (void *ioaddr)
773static int __devinit rtl8139_init_board (struct pci_dev *pdev, 748static int __devinit rtl8139_init_board (struct pci_dev *pdev,
774 struct net_device **dev_out) 749 struct net_device **dev_out)
775{ 750{
776 void *ioaddr; 751 void __iomem *ioaddr;
777 struct net_device *dev; 752 struct net_device *dev;
778 struct rtl8139_private *tp; 753 struct rtl8139_private *tp;
779 u8 tmp8; 754 u8 tmp8;
@@ -855,13 +830,18 @@ static int __devinit rtl8139_init_board (struct pci_dev *pdev,
855 pci_set_master (pdev); 830 pci_set_master (pdev);
856 831
857#ifdef USE_IO_OPS 832#ifdef USE_IO_OPS
858 ioaddr = (void *) pio_start; 833 ioaddr = ioport_map(pio_start, pio_len);
834 if (!ioaddr) {
835 printk (KERN_ERR PFX "%s: cannot map PIO, aborting\n", pci_name(pdev));
836 rc = -EIO;
837 goto err_out;
838 }
859 dev->base_addr = pio_start; 839 dev->base_addr = pio_start;
860 tp->mmio_addr = ioaddr; 840 tp->mmio_addr = ioaddr;
861 tp->regs_len = pio_len; 841 tp->regs_len = pio_len;
862#else 842#else
863 /* ioremap MMIO region */ 843 /* ioremap MMIO region */
864 ioaddr = ioremap (mmio_start, mmio_len); 844 ioaddr = pci_iomap(pdev, 1, 0);
865 if (ioaddr == NULL) { 845 if (ioaddr == NULL) {
866 printk (KERN_ERR PFX "%s: cannot remap MMIO, aborting\n", pci_name(pdev)); 846 printk (KERN_ERR PFX "%s: cannot remap MMIO, aborting\n", pci_name(pdev));
867 rc = -EIO; 847 rc = -EIO;
@@ -947,7 +927,7 @@ static int __devinit rtl8139_init_one (struct pci_dev *pdev,
947 struct net_device *dev = NULL; 927 struct net_device *dev = NULL;
948 struct rtl8139_private *tp; 928 struct rtl8139_private *tp;
949 int i, addr_len, option; 929 int i, addr_len, option;
950 void *ioaddr; 930 void __iomem *ioaddr;
951 static int board_idx = -1; 931 static int board_idx = -1;
952 u8 pci_rev; 932 u8 pci_rev;
953 933
@@ -1147,47 +1127,46 @@ static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1147 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this. 1127 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1148 */ 1128 */
1149 1129
1150#define eeprom_delay() readl(ee_addr) 1130#define eeprom_delay() RTL_R32(Cfg9346)
1151 1131
1152/* The EEPROM commands include the alway-set leading bit. */ 1132/* The EEPROM commands include the alway-set leading bit. */
1153#define EE_WRITE_CMD (5) 1133#define EE_WRITE_CMD (5)
1154#define EE_READ_CMD (6) 1134#define EE_READ_CMD (6)
1155#define EE_ERASE_CMD (7) 1135#define EE_ERASE_CMD (7)
1156 1136
1157static int __devinit read_eeprom (void *ioaddr, int location, int addr_len) 1137static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1158{ 1138{
1159 int i; 1139 int i;
1160 unsigned retval = 0; 1140 unsigned retval = 0;
1161 void *ee_addr = ioaddr + Cfg9346;
1162 int read_cmd = location | (EE_READ_CMD << addr_len); 1141 int read_cmd = location | (EE_READ_CMD << addr_len);
1163 1142
1164 writeb (EE_ENB & ~EE_CS, ee_addr); 1143 RTL_W8 (Cfg9346, EE_ENB & ~EE_CS);
1165 writeb (EE_ENB, ee_addr); 1144 RTL_W8 (Cfg9346, EE_ENB);
1166 eeprom_delay (); 1145 eeprom_delay ();
1167 1146
1168 /* Shift the read command bits out. */ 1147 /* Shift the read command bits out. */
1169 for (i = 4 + addr_len; i >= 0; i--) { 1148 for (i = 4 + addr_len; i >= 0; i--) {
1170 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 1149 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1171 writeb (EE_ENB | dataval, ee_addr); 1150 RTL_W8 (Cfg9346, EE_ENB | dataval);
1172 eeprom_delay (); 1151 eeprom_delay ();
1173 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr); 1152 RTL_W8 (Cfg9346, EE_ENB | dataval | EE_SHIFT_CLK);
1174 eeprom_delay (); 1153 eeprom_delay ();
1175 } 1154 }
1176 writeb (EE_ENB, ee_addr); 1155 RTL_W8 (Cfg9346, EE_ENB);
1177 eeprom_delay (); 1156 eeprom_delay ();
1178 1157
1179 for (i = 16; i > 0; i--) { 1158 for (i = 16; i > 0; i--) {
1180 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr); 1159 RTL_W8 (Cfg9346, EE_ENB | EE_SHIFT_CLK);
1181 eeprom_delay (); 1160 eeprom_delay ();
1182 retval = 1161 retval =
1183 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 : 1162 (retval << 1) | ((RTL_R8 (Cfg9346) & EE_DATA_READ) ? 1 :
1184 0); 1163 0);
1185 writeb (EE_ENB, ee_addr); 1164 RTL_W8 (Cfg9346, EE_ENB);
1186 eeprom_delay (); 1165 eeprom_delay ();
1187 } 1166 }
1188 1167
1189 /* Terminate the EEPROM access. */ 1168 /* Terminate the EEPROM access. */
1190 writeb (~EE_CS, ee_addr); 1169 RTL_W8 (Cfg9346, ~EE_CS);
1191 eeprom_delay (); 1170 eeprom_delay ();
1192 1171
1193 return retval; 1172 return retval;
@@ -1206,7 +1185,7 @@ static int __devinit read_eeprom (void *ioaddr, int location, int addr_len)
1206#define MDIO_WRITE0 (MDIO_DIR) 1185#define MDIO_WRITE0 (MDIO_DIR)
1207#define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT) 1186#define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1208 1187
1209#define mdio_delay(mdio_addr) readb(mdio_addr) 1188#define mdio_delay() RTL_R8(Config4)
1210 1189
1211 1190
1212static char mii_2_8139_map[8] = { 1191static char mii_2_8139_map[8] = {
@@ -1223,15 +1202,15 @@ static char mii_2_8139_map[8] = {
1223 1202
1224#ifdef CONFIG_8139TOO_8129 1203#ifdef CONFIG_8139TOO_8129
1225/* Syncronize the MII management interface by shifting 32 one bits out. */ 1204/* Syncronize the MII management interface by shifting 32 one bits out. */
1226static void mdio_sync (void *mdio_addr) 1205static void mdio_sync (void __iomem *ioaddr)
1227{ 1206{
1228 int i; 1207 int i;
1229 1208
1230 for (i = 32; i >= 0; i--) { 1209 for (i = 32; i >= 0; i--) {
1231 writeb (MDIO_WRITE1, mdio_addr); 1210 RTL_W8 (Config4, MDIO_WRITE1);
1232 mdio_delay (mdio_addr); 1211 mdio_delay ();
1233 writeb (MDIO_WRITE1 | MDIO_CLK, mdio_addr); 1212 RTL_W8 (Config4, MDIO_WRITE1 | MDIO_CLK);
1234 mdio_delay (mdio_addr); 1213 mdio_delay ();
1235 } 1214 }
1236} 1215}
1237#endif 1216#endif
@@ -1241,35 +1220,36 @@ static int mdio_read (struct net_device *dev, int phy_id, int location)
1241 struct rtl8139_private *tp = netdev_priv(dev); 1220 struct rtl8139_private *tp = netdev_priv(dev);
1242 int retval = 0; 1221 int retval = 0;
1243#ifdef CONFIG_8139TOO_8129 1222#ifdef CONFIG_8139TOO_8129
1244 void *mdio_addr = tp->mmio_addr + Config4; 1223 void __iomem *ioaddr = tp->mmio_addr;
1245 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location; 1224 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1246 int i; 1225 int i;
1247#endif 1226#endif
1248 1227
1249 if (phy_id > 31) { /* Really a 8139. Use internal registers. */ 1228 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1229 void __iomem *ioaddr = tp->mmio_addr;
1250 return location < 8 && mii_2_8139_map[location] ? 1230 return location < 8 && mii_2_8139_map[location] ?
1251 readw (tp->mmio_addr + mii_2_8139_map[location]) : 0; 1231 RTL_R16 (mii_2_8139_map[location]) : 0;
1252 } 1232 }
1253 1233
1254#ifdef CONFIG_8139TOO_8129 1234#ifdef CONFIG_8139TOO_8129
1255 mdio_sync (mdio_addr); 1235 mdio_sync (ioaddr);
1256 /* Shift the read command bits out. */ 1236 /* Shift the read command bits out. */
1257 for (i = 15; i >= 0; i--) { 1237 for (i = 15; i >= 0; i--) {
1258 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0; 1238 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1259 1239
1260 writeb (MDIO_DIR | dataval, mdio_addr); 1240 RTL_W8 (Config4, MDIO_DIR | dataval);
1261 mdio_delay (mdio_addr); 1241 mdio_delay ();
1262 writeb (MDIO_DIR | dataval | MDIO_CLK, mdio_addr); 1242 RTL_W8 (Config4, MDIO_DIR | dataval | MDIO_CLK);
1263 mdio_delay (mdio_addr); 1243 mdio_delay ();
1264 } 1244 }
1265 1245
1266 /* Read the two transition, 16 data, and wire-idle bits. */ 1246 /* Read the two transition, 16 data, and wire-idle bits. */
1267 for (i = 19; i > 0; i--) { 1247 for (i = 19; i > 0; i--) {
1268 writeb (0, mdio_addr); 1248 RTL_W8 (Config4, 0);
1269 mdio_delay (mdio_addr); 1249 mdio_delay ();
1270 retval = (retval << 1) | ((readb (mdio_addr) & MDIO_DATA_IN) ? 1 : 0); 1250 retval = (retval << 1) | ((RTL_R8 (Config4) & MDIO_DATA_IN) ? 1 : 0);
1271 writeb (MDIO_CLK, mdio_addr); 1251 RTL_W8 (Config4, MDIO_CLK);
1272 mdio_delay (mdio_addr); 1252 mdio_delay ();
1273 } 1253 }
1274#endif 1254#endif
1275 1255
@@ -1282,13 +1262,13 @@ static void mdio_write (struct net_device *dev, int phy_id, int location,
1282{ 1262{
1283 struct rtl8139_private *tp = netdev_priv(dev); 1263 struct rtl8139_private *tp = netdev_priv(dev);
1284#ifdef CONFIG_8139TOO_8129 1264#ifdef CONFIG_8139TOO_8129
1285 void *mdio_addr = tp->mmio_addr + Config4; 1265 void __iomem *ioaddr = tp->mmio_addr;
1286 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value; 1266 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1287 int i; 1267 int i;
1288#endif 1268#endif
1289 1269
1290 if (phy_id > 31) { /* Really a 8139. Use internal registers. */ 1270 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1291 void *ioaddr = tp->mmio_addr; 1271 void __iomem *ioaddr = tp->mmio_addr;
1292 if (location == 0) { 1272 if (location == 0) {
1293 RTL_W8 (Cfg9346, Cfg9346_Unlock); 1273 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1294 RTL_W16 (BasicModeCtrl, value); 1274 RTL_W16 (BasicModeCtrl, value);
@@ -1299,23 +1279,23 @@ static void mdio_write (struct net_device *dev, int phy_id, int location,
1299 } 1279 }
1300 1280
1301#ifdef CONFIG_8139TOO_8129 1281#ifdef CONFIG_8139TOO_8129
1302 mdio_sync (mdio_addr); 1282 mdio_sync (ioaddr);
1303 1283
1304 /* Shift the command bits out. */ 1284 /* Shift the command bits out. */
1305 for (i = 31; i >= 0; i--) { 1285 for (i = 31; i >= 0; i--) {
1306 int dataval = 1286 int dataval =
1307 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; 1287 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1308 writeb (dataval, mdio_addr); 1288 RTL_W8 (Config4, dataval);
1309 mdio_delay (mdio_addr); 1289 mdio_delay ();
1310 writeb (dataval | MDIO_CLK, mdio_addr); 1290 RTL_W8 (Config4, dataval | MDIO_CLK);
1311 mdio_delay (mdio_addr); 1291 mdio_delay ();
1312 } 1292 }
1313 /* Clear out extra bits. */ 1293 /* Clear out extra bits. */
1314 for (i = 2; i > 0; i--) { 1294 for (i = 2; i > 0; i--) {
1315 writeb (0, mdio_addr); 1295 RTL_W8 (Config4, 0);
1316 mdio_delay (mdio_addr); 1296 mdio_delay ();
1317 writeb (MDIO_CLK, mdio_addr); 1297 RTL_W8 (Config4, MDIO_CLK);
1318 mdio_delay (mdio_addr); 1298 mdio_delay ();
1319 } 1299 }
1320#endif 1300#endif
1321} 1301}
@@ -1325,7 +1305,7 @@ static int rtl8139_open (struct net_device *dev)
1325{ 1305{
1326 struct rtl8139_private *tp = netdev_priv(dev); 1306 struct rtl8139_private *tp = netdev_priv(dev);
1327 int retval; 1307 int retval;
1328 void *ioaddr = tp->mmio_addr; 1308 void __iomem *ioaddr = tp->mmio_addr;
1329 1309
1330 retval = request_irq (dev->irq, rtl8139_interrupt, SA_SHIRQ, dev->name, dev); 1310 retval = request_irq (dev->irq, rtl8139_interrupt, SA_SHIRQ, dev->name, dev);
1331 if (retval) 1311 if (retval)
@@ -1382,7 +1362,7 @@ static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1382static void rtl8139_hw_start (struct net_device *dev) 1362static void rtl8139_hw_start (struct net_device *dev)
1383{ 1363{
1384 struct rtl8139_private *tp = netdev_priv(dev); 1364 struct rtl8139_private *tp = netdev_priv(dev);
1385 void *ioaddr = tp->mmio_addr; 1365 void __iomem *ioaddr = tp->mmio_addr;
1386 u32 i; 1366 u32 i;
1387 u8 tmp; 1367 u8 tmp;
1388 1368
@@ -1484,7 +1464,7 @@ static void rtl8139_tune_twister (struct net_device *dev,
1484 struct rtl8139_private *tp) 1464 struct rtl8139_private *tp)
1485{ 1465{
1486 int linkcase; 1466 int linkcase;
1487 void *ioaddr = tp->mmio_addr; 1467 void __iomem *ioaddr = tp->mmio_addr;
1488 1468
1489 /* This is a complicated state machine to configure the "twister" for 1469 /* This is a complicated state machine to configure the "twister" for
1490 impedance/echos based on the cable length. 1470 impedance/echos based on the cable length.
@@ -1568,7 +1548,7 @@ static void rtl8139_tune_twister (struct net_device *dev,
1568 1548
1569static inline void rtl8139_thread_iter (struct net_device *dev, 1549static inline void rtl8139_thread_iter (struct net_device *dev,
1570 struct rtl8139_private *tp, 1550 struct rtl8139_private *tp,
1571 void *ioaddr) 1551 void __iomem *ioaddr)
1572{ 1552{
1573 int mii_lpa; 1553 int mii_lpa;
1574 1554
@@ -1626,7 +1606,7 @@ static int rtl8139_thread (void *data)
1626 do { 1606 do {
1627 timeout = interruptible_sleep_on_timeout (&tp->thr_wait, timeout); 1607 timeout = interruptible_sleep_on_timeout (&tp->thr_wait, timeout);
1628 /* make swsusp happy with our thread */ 1608 /* make swsusp happy with our thread */
1629 try_to_freeze(PF_FREEZE); 1609 try_to_freeze();
1630 } while (!signal_pending (current) && (timeout > 0)); 1610 } while (!signal_pending (current) && (timeout > 0));
1631 1611
1632 if (signal_pending (current)) { 1612 if (signal_pending (current)) {
@@ -1676,7 +1656,7 @@ static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1676static void rtl8139_tx_timeout (struct net_device *dev) 1656static void rtl8139_tx_timeout (struct net_device *dev)
1677{ 1657{
1678 struct rtl8139_private *tp = netdev_priv(dev); 1658 struct rtl8139_private *tp = netdev_priv(dev);
1679 void *ioaddr = tp->mmio_addr; 1659 void __iomem *ioaddr = tp->mmio_addr;
1680 int i; 1660 int i;
1681 u8 tmp8; 1661 u8 tmp8;
1682 unsigned long flags; 1662 unsigned long flags;
@@ -1721,7 +1701,7 @@ static void rtl8139_tx_timeout (struct net_device *dev)
1721static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev) 1701static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1722{ 1702{
1723 struct rtl8139_private *tp = netdev_priv(dev); 1703 struct rtl8139_private *tp = netdev_priv(dev);
1724 void *ioaddr = tp->mmio_addr; 1704 void __iomem *ioaddr = tp->mmio_addr;
1725 unsigned int entry; 1705 unsigned int entry;
1726 unsigned int len = skb->len; 1706 unsigned int len = skb->len;
1727 1707
@@ -1763,7 +1743,7 @@ static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1763 1743
1764static void rtl8139_tx_interrupt (struct net_device *dev, 1744static void rtl8139_tx_interrupt (struct net_device *dev,
1765 struct rtl8139_private *tp, 1745 struct rtl8139_private *tp,
1766 void *ioaddr) 1746 void __iomem *ioaddr)
1767{ 1747{
1768 unsigned long dirty_tx, tx_left; 1748 unsigned long dirty_tx, tx_left;
1769 1749
@@ -1833,7 +1813,7 @@ static void rtl8139_tx_interrupt (struct net_device *dev,
1833 1813
1834/* TODO: clean this up! Rx reset need not be this intensive */ 1814/* TODO: clean this up! Rx reset need not be this intensive */
1835static void rtl8139_rx_err (u32 rx_status, struct net_device *dev, 1815static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1836 struct rtl8139_private *tp, void *ioaddr) 1816 struct rtl8139_private *tp, void __iomem *ioaddr)
1837{ 1817{
1838 u8 tmp8; 1818 u8 tmp8;
1839#ifdef CONFIG_8139_OLD_RX_RESET 1819#ifdef CONFIG_8139_OLD_RX_RESET
@@ -1930,7 +1910,7 @@ static __inline__ void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1930 1910
1931static void rtl8139_isr_ack(struct rtl8139_private *tp) 1911static void rtl8139_isr_ack(struct rtl8139_private *tp)
1932{ 1912{
1933 void *ioaddr = tp->mmio_addr; 1913 void __iomem *ioaddr = tp->mmio_addr;
1934 u16 status; 1914 u16 status;
1935 1915
1936 status = RTL_R16 (IntrStatus) & RxAckBits; 1916 status = RTL_R16 (IntrStatus) & RxAckBits;
@@ -1949,7 +1929,7 @@ static void rtl8139_isr_ack(struct rtl8139_private *tp)
1949static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp, 1929static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1950 int budget) 1930 int budget)
1951{ 1931{
1952 void *ioaddr = tp->mmio_addr; 1932 void __iomem *ioaddr = tp->mmio_addr;
1953 int received = 0; 1933 int received = 0;
1954 unsigned char *rx_ring = tp->rx_ring; 1934 unsigned char *rx_ring = tp->rx_ring;
1955 unsigned int cur_rx = tp->cur_rx; 1935 unsigned int cur_rx = tp->cur_rx;
@@ -2087,7 +2067,7 @@ out:
2087 2067
2088static void rtl8139_weird_interrupt (struct net_device *dev, 2068static void rtl8139_weird_interrupt (struct net_device *dev,
2089 struct rtl8139_private *tp, 2069 struct rtl8139_private *tp,
2090 void *ioaddr, 2070 void __iomem *ioaddr,
2091 int status, int link_changed) 2071 int status, int link_changed)
2092{ 2072{
2093 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n", 2073 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
@@ -2127,7 +2107,7 @@ static void rtl8139_weird_interrupt (struct net_device *dev,
2127static int rtl8139_poll(struct net_device *dev, int *budget) 2107static int rtl8139_poll(struct net_device *dev, int *budget)
2128{ 2108{
2129 struct rtl8139_private *tp = netdev_priv(dev); 2109 struct rtl8139_private *tp = netdev_priv(dev);
2130 void *ioaddr = tp->mmio_addr; 2110 void __iomem *ioaddr = tp->mmio_addr;
2131 int orig_budget = min(*budget, dev->quota); 2111 int orig_budget = min(*budget, dev->quota);
2132 int done = 1; 2112 int done = 1;
2133 2113
@@ -2165,7 +2145,7 @@ static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,
2165{ 2145{
2166 struct net_device *dev = (struct net_device *) dev_instance; 2146 struct net_device *dev = (struct net_device *) dev_instance;
2167 struct rtl8139_private *tp = netdev_priv(dev); 2147 struct rtl8139_private *tp = netdev_priv(dev);
2168 void *ioaddr = tp->mmio_addr; 2148 void __iomem *ioaddr = tp->mmio_addr;
2169 u16 status, ackstat; 2149 u16 status, ackstat;
2170 int link_changed = 0; /* avoid bogus "uninit" warning */ 2150 int link_changed = 0; /* avoid bogus "uninit" warning */
2171 int handled = 0; 2151 int handled = 0;
@@ -2241,7 +2221,7 @@ static void rtl8139_poll_controller(struct net_device *dev)
2241static int rtl8139_close (struct net_device *dev) 2221static int rtl8139_close (struct net_device *dev)
2242{ 2222{
2243 struct rtl8139_private *tp = netdev_priv(dev); 2223 struct rtl8139_private *tp = netdev_priv(dev);
2244 void *ioaddr = tp->mmio_addr; 2224 void __iomem *ioaddr = tp->mmio_addr;
2245 int ret = 0; 2225 int ret = 0;
2246 unsigned long flags; 2226 unsigned long flags;
2247 2227
@@ -2304,7 +2284,7 @@ static int rtl8139_close (struct net_device *dev)
2304static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2284static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2305{ 2285{
2306 struct rtl8139_private *np = netdev_priv(dev); 2286 struct rtl8139_private *np = netdev_priv(dev);
2307 void *ioaddr = np->mmio_addr; 2287 void __iomem *ioaddr = np->mmio_addr;
2308 2288
2309 spin_lock_irq(&np->lock); 2289 spin_lock_irq(&np->lock);
2310 if (rtl_chip_info[np->chipset].flags & HasLWake) { 2290 if (rtl_chip_info[np->chipset].flags & HasLWake) {
@@ -2338,7 +2318,7 @@ static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2338static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2318static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2339{ 2319{
2340 struct rtl8139_private *np = netdev_priv(dev); 2320 struct rtl8139_private *np = netdev_priv(dev);
2341 void *ioaddr = np->mmio_addr; 2321 void __iomem *ioaddr = np->mmio_addr;
2342 u32 support; 2322 u32 support;
2343 u8 cfg3, cfg5; 2323 u8 cfg3, cfg5;
2344 2324
@@ -2506,7 +2486,7 @@ static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2506static struct net_device_stats *rtl8139_get_stats (struct net_device *dev) 2486static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2507{ 2487{
2508 struct rtl8139_private *tp = netdev_priv(dev); 2488 struct rtl8139_private *tp = netdev_priv(dev);
2509 void *ioaddr = tp->mmio_addr; 2489 void __iomem *ioaddr = tp->mmio_addr;
2510 unsigned long flags; 2490 unsigned long flags;
2511 2491
2512 if (netif_running(dev)) { 2492 if (netif_running(dev)) {
@@ -2525,7 +2505,7 @@ static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2525static void __set_rx_mode (struct net_device *dev) 2505static void __set_rx_mode (struct net_device *dev)
2526{ 2506{
2527 struct rtl8139_private *tp = netdev_priv(dev); 2507 struct rtl8139_private *tp = netdev_priv(dev);
2528 void *ioaddr = tp->mmio_addr; 2508 void __iomem *ioaddr = tp->mmio_addr;
2529 u32 mc_filter[2]; /* Multicast hash filter */ 2509 u32 mc_filter[2]; /* Multicast hash filter */
2530 int i, rx_mode; 2510 int i, rx_mode;
2531 u32 tmp; 2511 u32 tmp;
@@ -2586,7 +2566,7 @@ static int rtl8139_suspend (struct pci_dev *pdev, pm_message_t state)
2586{ 2566{
2587 struct net_device *dev = pci_get_drvdata (pdev); 2567 struct net_device *dev = pci_get_drvdata (pdev);
2588 struct rtl8139_private *tp = netdev_priv(dev); 2568 struct rtl8139_private *tp = netdev_priv(dev);
2589 void *ioaddr = tp->mmio_addr; 2569 void __iomem *ioaddr = tp->mmio_addr;
2590 unsigned long flags; 2570 unsigned long flags;
2591 2571
2592 pci_save_state (pdev); 2572 pci_save_state (pdev);
diff --git a/drivers/net/8390.c b/drivers/net/8390.c
index bab16bcc9ae5..6d76f3a99b17 100644
--- a/drivers/net/8390.c
+++ b/drivers/net/8390.c
@@ -225,9 +225,9 @@ void ei_tx_timeout(struct net_device *dev)
225 unsigned long icucr; 225 unsigned long icucr;
226 226
227 local_irq_save(flags); 227 local_irq_save(flags);
228 icucr = inl(ICUCR1); 228 icucr = inl(M32R_ICU_CR1_PORTL);
229 icucr |= M32R_ICUCR_ISMOD11; 229 icucr |= M32R_ICUCR_ISMOD11;
230 outl(icucr, ICUCR1); 230 outl(icucr, M32R_ICU_CR1_PORTL);
231 local_irq_restore(flags); 231 local_irq_restore(flags);
232#endif 232#endif
233 ei_local->stat.tx_errors++; 233 ei_local->stat.tx_errors++;
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 3a0a55b62aaf..fa9f76c953dd 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -824,6 +824,18 @@ config SMC9194
824 <file:Documentation/networking/net-modules.txt>. The module 824 <file:Documentation/networking/net-modules.txt>. The module
825 will be called smc9194. 825 will be called smc9194.
826 826
827config DM9000
828 tristate "DM9000 support"
829 depends on ARM && NET_ETHERNET
830 select CRC32
831 select MII
832 ---help---
833 Support for DM9000 chipset.
834
835 To compile this driver as a module, choose M here and read
836 <file:Documentation/networking/net-modules.txt>. The module will be
837 called dm9000.
838
827config NET_VENDOR_RACAL 839config NET_VENDOR_RACAL
828 bool "Racal-Interlan (Micom) NI cards" 840 bool "Racal-Interlan (Micom) NI cards"
829 depends on NET_ETHERNET && ISA 841 depends on NET_ETHERNET && ISA
@@ -989,21 +1001,6 @@ config EEXPRESS_PRO
989 <file:Documentation/networking/net-modules.txt>. The module 1001 <file:Documentation/networking/net-modules.txt>. The module
990 will be called eepro. 1002 will be called eepro.
991 1003
992config FMV18X
993 tristate "FMV-181/182/183/184 support (OBSOLETE)"
994 depends on NET_ISA && OBSOLETE
995 ---help---
996 If you have a Fujitsu FMV-181/182/183/184 network (Ethernet) card,
997 say Y and read the Ethernet-HOWTO, available from
998 <http://www.tldp.org/docs.html#howto>.
999
1000 If you use an FMV-183 or FMV-184 and it is not working, you may need
1001 to disable Plug & Play mode of the card.
1002
1003 To compile this driver as a module, choose M here and read
1004 <file:Documentation/networking/net-modules.txt>. The module
1005 will be called fmv18x.
1006
1007config HPLAN_PLUS 1004config HPLAN_PLUS
1008 tristate "HP PCLAN+ (27247B and 27252A) support" 1005 tristate "HP PCLAN+ (27247B and 27252A) support"
1009 depends on NET_ISA 1006 depends on NET_ISA
@@ -1092,14 +1089,6 @@ config SEEQ8005
1092 <file:Documentation/networking/net-modules.txt>. The module 1089 <file:Documentation/networking/net-modules.txt>. The module
1093 will be called seeq8005. 1090 will be called seeq8005.
1094 1091
1095config SK_G16
1096 tristate "SK_G16 support (OBSOLETE)"
1097 depends on NET_ISA && OBSOLETE
1098 help
1099 If you have a network (Ethernet) card of this type, say Y and read
1100 the Ethernet-HOWTO, available from
1101 <http://www.tldp.org/docs.html#howto>.
1102
1103config SKMC 1092config SKMC
1104 tristate "SKnet MCA support" 1093 tristate "SKnet MCA support"
1105 depends on NET_ETHERNET && MCA && BROKEN 1094 depends on NET_ETHERNET && MCA && BROKEN
@@ -1555,6 +1544,7 @@ config SIS900
1555 tristate "SiS 900/7016 PCI Fast Ethernet Adapter support" 1544 tristate "SiS 900/7016 PCI Fast Ethernet Adapter support"
1556 depends on NET_PCI && PCI 1545 depends on NET_PCI && PCI
1557 select CRC32 1546 select CRC32
1547 select MII
1558 ---help--- 1548 ---help---
1559 This is a driver for the Fast Ethernet PCI network cards based on 1549 This is a driver for the Fast Ethernet PCI network cards based on
1560 the SiS 900 and SiS 7016 chips. The SiS 900 core is also embedded in 1550 the SiS 900 and SiS 7016 chips. The SiS 900 core is also embedded in
@@ -1931,6 +1921,18 @@ config R8169_VLAN
1931 1921
1932 If in doubt, say Y. 1922 If in doubt, say Y.
1933 1923
1924config SKGE
1925 tristate "New SysKonnect GigaEthernet support (EXPERIMENTAL)"
1926 depends on PCI && EXPERIMENTAL
1927 select CRC32
1928 ---help---
1929 This driver support the Marvell Yukon or SysKonnect SK-98xx/SK-95xx
1930 and related Gigabit Ethernet adapters. It is a new smaller driver
1931 driver with better performance and more complete ethtool support.
1932
1933 It does not support the link failover and network management
1934 features that "portable" vendor supplied sk98lin driver does.
1935
1934config SK98LIN 1936config SK98LIN
1935 tristate "Marvell Yukon Chipset / SysKonnect SK-98xx Support" 1937 tristate "Marvell Yukon Chipset / SysKonnect SK-98xx Support"
1936 depends on PCI 1938 depends on PCI
@@ -2031,6 +2033,15 @@ config TIGON3
2031 To compile this driver as a module, choose M here: the module 2033 To compile this driver as a module, choose M here: the module
2032 will be called tg3. This is recommended. 2034 will be called tg3. This is recommended.
2033 2035
2036config BNX2
2037 tristate "Broadcom NetXtremeII support"
2038 depends on PCI
2039 help
2040 This driver supports Broadcom NetXtremeII gigabit Ethernet cards.
2041
2042 To compile this driver as a module, choose M here: the module
2043 will be called bnx2. This is recommended.
2044
2034config GIANFAR 2045config GIANFAR
2035 tristate "Gianfar Ethernet" 2046 tristate "Gianfar Ethernet"
2036 depends on 85xx || 83xx 2047 depends on 85xx || 83xx
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 6202b10dbb4d..63c6d1e6d4d9 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -51,7 +51,9 @@ obj-$(CONFIG_NS83820) += ns83820.o
51obj-$(CONFIG_STNIC) += stnic.o 8390.o 51obj-$(CONFIG_STNIC) += stnic.o 8390.o
52obj-$(CONFIG_FEALNX) += fealnx.o 52obj-$(CONFIG_FEALNX) += fealnx.o
53obj-$(CONFIG_TIGON3) += tg3.o 53obj-$(CONFIG_TIGON3) += tg3.o
54obj-$(CONFIG_BNX2) += bnx2.o
54obj-$(CONFIG_TC35815) += tc35815.o 55obj-$(CONFIG_TC35815) += tc35815.o
56obj-$(CONFIG_SKGE) += skge.o
55obj-$(CONFIG_SK98LIN) += sk98lin/ 57obj-$(CONFIG_SK98LIN) += sk98lin/
56obj-$(CONFIG_SKFP) += skfp/ 58obj-$(CONFIG_SKFP) += skfp/
57obj-$(CONFIG_VIA_RHINE) += via-rhine.o 59obj-$(CONFIG_VIA_RHINE) += via-rhine.o
@@ -73,7 +75,6 @@ obj-$(CONFIG_MAC8390) += mac8390.o 8390.o
73obj-$(CONFIG_APNE) += apne.o 8390.o 75obj-$(CONFIG_APNE) += apne.o 8390.o
74obj-$(CONFIG_PCMCIA_PCNET) += 8390.o 76obj-$(CONFIG_PCMCIA_PCNET) += 8390.o
75obj-$(CONFIG_SHAPER) += shaper.o 77obj-$(CONFIG_SHAPER) += shaper.o
76obj-$(CONFIG_SK_G16) += sk_g16.o
77obj-$(CONFIG_HP100) += hp100.o 78obj-$(CONFIG_HP100) += hp100.o
78obj-$(CONFIG_SMC9194) += smc9194.o 79obj-$(CONFIG_SMC9194) += smc9194.o
79obj-$(CONFIG_FEC) += fec.o 80obj-$(CONFIG_FEC) += fec.o
@@ -121,7 +122,6 @@ obj-$(CONFIG_DEFXX) += defxx.o
121obj-$(CONFIG_SGISEEQ) += sgiseeq.o 122obj-$(CONFIG_SGISEEQ) += sgiseeq.o
122obj-$(CONFIG_SGI_O2MACE_ETH) += meth.o 123obj-$(CONFIG_SGI_O2MACE_ETH) += meth.o
123obj-$(CONFIG_AT1700) += at1700.o 124obj-$(CONFIG_AT1700) += at1700.o
124obj-$(CONFIG_FMV18X) += fmv18x.o
125obj-$(CONFIG_EL1) += 3c501.o 125obj-$(CONFIG_EL1) += 3c501.o
126obj-$(CONFIG_EL16) += 3c507.o 126obj-$(CONFIG_EL16) += 3c507.o
127obj-$(CONFIG_ELMC) += 3c523.o 127obj-$(CONFIG_ELMC) += 3c523.o
@@ -179,6 +179,7 @@ obj-$(CONFIG_AMD8111_ETH) += amd8111e.o
179obj-$(CONFIG_IBMVETH) += ibmveth.o 179obj-$(CONFIG_IBMVETH) += ibmveth.o
180obj-$(CONFIG_S2IO) += s2io.o 180obj-$(CONFIG_S2IO) += s2io.o
181obj-$(CONFIG_SMC91X) += smc91x.o 181obj-$(CONFIG_SMC91X) += smc91x.o
182obj-$(CONFIG_DM9000) += dm9000.o
182obj-$(CONFIG_FEC_8XX) += fec_8xx/ 183obj-$(CONFIG_FEC_8XX) += fec_8xx/
183 184
184obj-$(CONFIG_ARM) += arm/ 185obj-$(CONFIG_ARM) += arm/
@@ -187,7 +188,7 @@ obj-$(CONFIG_TR) += tokenring/
187obj-$(CONFIG_WAN) += wan/ 188obj-$(CONFIG_WAN) += wan/
188obj-$(CONFIG_ARCNET) += arcnet/ 189obj-$(CONFIG_ARCNET) += arcnet/
189obj-$(CONFIG_NET_PCMCIA) += pcmcia/ 190obj-$(CONFIG_NET_PCMCIA) += pcmcia/
190obj-$(CONFIG_NET_WIRELESS) += wireless/ 191obj-$(CONFIG_NET_RADIO) += wireless/
191obj-$(CONFIG_NET_TULIP) += tulip/ 192obj-$(CONFIG_NET_TULIP) += tulip/
192obj-$(CONFIG_HAMRADIO) += hamradio/ 193obj-$(CONFIG_HAMRADIO) += hamradio/
193obj-$(CONFIG_IRDA) += irda/ 194obj-$(CONFIG_IRDA) += irda/
diff --git a/drivers/net/Space.c b/drivers/net/Space.c
index fb433325aa27..3707df6b0cfa 100644
--- a/drivers/net/Space.c
+++ b/drivers/net/Space.c
@@ -210,9 +210,6 @@ static struct devprobe2 isa_probes[] __initdata = {
210#ifdef CONFIG_AT1700 210#ifdef CONFIG_AT1700
211 {at1700_probe, 0}, 211 {at1700_probe, 0},
212#endif 212#endif
213#ifdef CONFIG_FMV18X /* Fujitsu FMV-181/182 */
214 {fmv18x_probe, 0},
215#endif
216#ifdef CONFIG_ETH16I 213#ifdef CONFIG_ETH16I
217 {eth16i_probe, 0}, /* ICL EtherTeam 16i/32 */ 214 {eth16i_probe, 0}, /* ICL EtherTeam 16i/32 */
218#endif 215#endif
@@ -243,9 +240,6 @@ static struct devprobe2 isa_probes[] __initdata = {
243#ifdef CONFIG_ELPLUS /* 3c505 */ 240#ifdef CONFIG_ELPLUS /* 3c505 */
244 {elplus_probe, 0}, 241 {elplus_probe, 0},
245#endif 242#endif
246#ifdef CONFIG_SK_G16
247 {SK_init, 0},
248#endif
249#ifdef CONFIG_NI5010 243#ifdef CONFIG_NI5010
250 {ni5010_probe, 0}, 244 {ni5010_probe, 0},
251#endif 245#endif
diff --git a/drivers/net/amd8111e.c b/drivers/net/amd8111e.c
index f2e937abf7b4..b7dd7260cafb 100755
--- a/drivers/net/amd8111e.c
+++ b/drivers/net/amd8111e.c
@@ -738,6 +738,7 @@ static int amd8111e_rx_poll(struct net_device *dev, int * budget)
738 short vtag; 738 short vtag;
739#endif 739#endif
740 int rx_pkt_limit = dev->quota; 740 int rx_pkt_limit = dev->quota;
741 unsigned long flags;
741 742
742 do{ 743 do{
743 /* process receive packets until we use the quota*/ 744 /* process receive packets until we use the quota*/
@@ -841,18 +842,19 @@ static int amd8111e_rx_poll(struct net_device *dev, int * budget)
841 /* Receive descriptor is empty now */ 842 /* Receive descriptor is empty now */
842 dev->quota -= num_rx_pkt; 843 dev->quota -= num_rx_pkt;
843 *budget -= num_rx_pkt; 844 *budget -= num_rx_pkt;
845
846 spin_lock_irqsave(&lp->lock, flags);
844 netif_rx_complete(dev); 847 netif_rx_complete(dev);
845 /* enable receive interrupt */
846 writel(VAL0|RINTEN0, mmio + INTEN0); 848 writel(VAL0|RINTEN0, mmio + INTEN0);
847 writel(VAL2 | RDMD0, mmio + CMD0); 849 writel(VAL2 | RDMD0, mmio + CMD0);
850 spin_unlock_irqrestore(&lp->lock, flags);
848 return 0; 851 return 0;
852
849rx_not_empty: 853rx_not_empty:
850 /* Do not call a netif_rx_complete */ 854 /* Do not call a netif_rx_complete */
851 dev->quota -= num_rx_pkt; 855 dev->quota -= num_rx_pkt;
852 *budget -= num_rx_pkt; 856 *budget -= num_rx_pkt;
853 return 1; 857 return 1;
854
855
856} 858}
857 859
858#else 860#else
@@ -1261,18 +1263,20 @@ static irqreturn_t amd8111e_interrupt(int irq, void *dev_id, struct pt_regs *reg
1261 struct net_device * dev = (struct net_device *) dev_id; 1263 struct net_device * dev = (struct net_device *) dev_id;
1262 struct amd8111e_priv *lp = netdev_priv(dev); 1264 struct amd8111e_priv *lp = netdev_priv(dev);
1263 void __iomem *mmio = lp->mmio; 1265 void __iomem *mmio = lp->mmio;
1264 unsigned int intr0; 1266 unsigned int intr0, intren0;
1265 unsigned int handled = 1; 1267 unsigned int handled = 1;
1266 1268
1267 if(dev == NULL) 1269 if(unlikely(dev == NULL))
1268 return IRQ_NONE; 1270 return IRQ_NONE;
1269 1271
1270 if (regs) spin_lock (&lp->lock); 1272 spin_lock(&lp->lock);
1273
1271 /* disabling interrupt */ 1274 /* disabling interrupt */
1272 writel(INTREN, mmio + CMD0); 1275 writel(INTREN, mmio + CMD0);
1273 1276
1274 /* Read interrupt status */ 1277 /* Read interrupt status */
1275 intr0 = readl(mmio + INT0); 1278 intr0 = readl(mmio + INT0);
1279 intren0 = readl(mmio + INTEN0);
1276 1280
1277 /* Process all the INT event until INTR bit is clear. */ 1281 /* Process all the INT event until INTR bit is clear. */
1278 1282
@@ -1293,11 +1297,11 @@ static irqreturn_t amd8111e_interrupt(int irq, void *dev_id, struct pt_regs *reg
1293 /* Schedule a polling routine */ 1297 /* Schedule a polling routine */
1294 __netif_rx_schedule(dev); 1298 __netif_rx_schedule(dev);
1295 } 1299 }
1296 else { 1300 else if (intren0 & RINTEN0) {
1297 printk("************Driver bug! \ 1301 printk("************Driver bug! \
1298 interrupt while in poll\n"); 1302 interrupt while in poll\n");
1299 /* Fix by disabling interrupts */ 1303 /* Fix by disable receive interrupts */
1300 writel(RINT0, mmio + INT0); 1304 writel(RINTEN0, mmio + INTEN0);
1301 } 1305 }
1302 } 1306 }
1303#else 1307#else
@@ -1321,7 +1325,7 @@ static irqreturn_t amd8111e_interrupt(int irq, void *dev_id, struct pt_regs *reg
1321err_no_interrupt: 1325err_no_interrupt:
1322 writel( VAL0 | INTREN,mmio + CMD0); 1326 writel( VAL0 | INTREN,mmio + CMD0);
1323 1327
1324 if (regs) spin_unlock(&lp->lock); 1328 spin_unlock(&lp->lock);
1325 1329
1326 return IRQ_RETVAL(handled); 1330 return IRQ_RETVAL(handled);
1327} 1331}
diff --git a/drivers/net/appletalk/ltpc.c b/drivers/net/appletalk/ltpc.c
index db4f369637b6..d5666c37cb0d 100644
--- a/drivers/net/appletalk/ltpc.c
+++ b/drivers/net/appletalk/ltpc.c
@@ -1109,8 +1109,7 @@ struct net_device * __init ltpc_probe(void)
1109 inb_p(io+1); 1109 inb_p(io+1);
1110 inb_p(io+3); 1110 inb_p(io+3);
1111 1111
1112 set_current_state(TASK_UNINTERRUPTIBLE); 1112 msleep(20);
1113 schedule_timeout(2*HZ/100);
1114 1113
1115 inb_p(io+0); 1114 inb_p(io+0);
1116 inb_p(io+2); 1115 inb_p(io+2);
@@ -1120,8 +1119,7 @@ struct net_device * __init ltpc_probe(void)
1120 inb_p(io+5); /* enable dma */ 1119 inb_p(io+5); /* enable dma */
1121 inb_p(io+6); /* tri-state interrupt line */ 1120 inb_p(io+6); /* tri-state interrupt line */
1122 1121
1123 set_current_state(TASK_UNINTERRUPTIBLE); 1122 ssleep(1);
1124 schedule_timeout(HZ);
1125 1123
1126 /* now, figure out which dma channel we're using, unless it's 1124 /* now, figure out which dma channel we're using, unless it's
1127 already been specified */ 1125 already been specified */
diff --git a/drivers/net/arm/etherh.c b/drivers/net/arm/etherh.c
index 942a2819576c..2e28c201dcc0 100644
--- a/drivers/net/arm/etherh.c
+++ b/drivers/net/arm/etherh.c
@@ -68,6 +68,7 @@ struct etherh_priv {
68 void __iomem *dma_base; 68 void __iomem *dma_base;
69 unsigned int id; 69 unsigned int id;
70 void __iomem *ctrl_port; 70 void __iomem *ctrl_port;
71 void __iomem *base;
71 unsigned char ctrl; 72 unsigned char ctrl;
72 u32 supported; 73 u32 supported;
73}; 74};
@@ -177,7 +178,7 @@ etherh_setif(struct net_device *dev)
177 switch (etherh_priv(dev)->id) { 178 switch (etherh_priv(dev)->id) {
178 case PROD_I3_ETHERLAN600: 179 case PROD_I3_ETHERLAN600:
179 case PROD_I3_ETHERLAN600A: 180 case PROD_I3_ETHERLAN600A:
180 addr = (void *)dev->base_addr + EN0_RCNTHI; 181 addr = etherh_priv(dev)->base + EN0_RCNTHI;
181 182
182 switch (dev->if_port) { 183 switch (dev->if_port) {
183 case IF_PORT_10BASE2: 184 case IF_PORT_10BASE2:
@@ -218,7 +219,7 @@ etherh_getifstat(struct net_device *dev)
218 switch (etherh_priv(dev)->id) { 219 switch (etherh_priv(dev)->id) {
219 case PROD_I3_ETHERLAN600: 220 case PROD_I3_ETHERLAN600:
220 case PROD_I3_ETHERLAN600A: 221 case PROD_I3_ETHERLAN600A:
221 addr = (void *)dev->base_addr + EN0_RCNTHI; 222 addr = etherh_priv(dev)->base + EN0_RCNTHI;
222 switch (dev->if_port) { 223 switch (dev->if_port) {
223 case IF_PORT_10BASE2: 224 case IF_PORT_10BASE2:
224 stat = 1; 225 stat = 1;
@@ -281,7 +282,7 @@ static void
281etherh_reset(struct net_device *dev) 282etherh_reset(struct net_device *dev)
282{ 283{
283 struct ei_device *ei_local = netdev_priv(dev); 284 struct ei_device *ei_local = netdev_priv(dev);
284 void __iomem *addr = (void *)dev->base_addr; 285 void __iomem *addr = etherh_priv(dev)->base;
285 286
286 writeb(E8390_NODMA+E8390_PAGE0+E8390_STOP, addr); 287 writeb(E8390_NODMA+E8390_PAGE0+E8390_STOP, addr);
287 288
@@ -327,7 +328,7 @@ etherh_block_output (struct net_device *dev, int count, const unsigned char *buf
327 328
328 ei_local->dmaing = 1; 329 ei_local->dmaing = 1;
329 330
330 addr = (void *)dev->base_addr; 331 addr = etherh_priv(dev)->base;
331 dma_base = etherh_priv(dev)->dma_base; 332 dma_base = etherh_priv(dev)->dma_base;
332 333
333 count = (count + 1) & ~1; 334 count = (count + 1) & ~1;
@@ -387,7 +388,7 @@ etherh_block_input (struct net_device *dev, int count, struct sk_buff *skb, int
387 388
388 ei_local->dmaing = 1; 389 ei_local->dmaing = 1;
389 390
390 addr = (void *)dev->base_addr; 391 addr = etherh_priv(dev)->base;
391 dma_base = etherh_priv(dev)->dma_base; 392 dma_base = etherh_priv(dev)->dma_base;
392 393
393 buf = skb->data; 394 buf = skb->data;
@@ -427,7 +428,7 @@ etherh_get_header (struct net_device *dev, struct e8390_pkt_hdr *hdr, int ring_p
427 428
428 ei_local->dmaing = 1; 429 ei_local->dmaing = 1;
429 430
430 addr = (void *)dev->base_addr; 431 addr = etherh_priv(dev)->base;
431 dma_base = etherh_priv(dev)->dma_base; 432 dma_base = etherh_priv(dev)->dma_base;
432 433
433 writeb (E8390_NODMA | E8390_PAGE0 | E8390_START, addr + E8390_CMD); 434 writeb (E8390_NODMA | E8390_PAGE0 | E8390_START, addr + E8390_CMD);
@@ -696,7 +697,8 @@ etherh_probe(struct expansion_card *ec, const struct ecard_id *id)
696 eh->ctrl_port = eh->ioc_fast; 697 eh->ctrl_port = eh->ioc_fast;
697 } 698 }
698 699
699 dev->base_addr = (unsigned long)eh->memc + data->ns8390_offset; 700 eh->base = eh->memc + data->ns8390_offset;
701 dev->base_addr = (unsigned long)eh->base;
700 eh->dma_base = eh->memc + data->dataport_offset; 702 eh->dma_base = eh->memc + data->dataport_offset;
701 eh->ctrl_port += data->ctrlport_offset; 703 eh->ctrl_port += data->ctrlport_offset;
702 704
diff --git a/drivers/net/au1000_eth.c b/drivers/net/au1000_eth.c
index 5a2efd343db4..c82b9cd1c924 100644
--- a/drivers/net/au1000_eth.c
+++ b/drivers/net/au1000_eth.c
@@ -1681,10 +1681,6 @@ static int au1000_init(struct net_device *dev)
1681 control |= MAC_FULL_DUPLEX; 1681 control |= MAC_FULL_DUPLEX;
1682 } 1682 }
1683 1683
1684 /* fix for startup without cable */
1685 if (!link)
1686 dev->flags &= ~IFF_RUNNING;
1687
1688 aup->mac->control = control; 1684 aup->mac->control = control;
1689 aup->mac->vlan1_tag = 0x8100; /* activate vlan support */ 1685 aup->mac->vlan1_tag = 0x8100; /* activate vlan support */
1690 au_sync(); 1686 au_sync();
@@ -1709,16 +1705,14 @@ static void au1000_timer(unsigned long data)
1709 if_port = dev->if_port; 1705 if_port = dev->if_port;
1710 if (aup->phy_ops->phy_status(dev, aup->phy_addr, &link, &speed) == 0) { 1706 if (aup->phy_ops->phy_status(dev, aup->phy_addr, &link, &speed) == 0) {
1711 if (link) { 1707 if (link) {
1712 if (!(dev->flags & IFF_RUNNING)) { 1708 if (!netif_carrier_ok(dev)) {
1713 netif_carrier_on(dev); 1709 netif_carrier_on(dev);
1714 dev->flags |= IFF_RUNNING;
1715 printk(KERN_INFO "%s: link up\n", dev->name); 1710 printk(KERN_INFO "%s: link up\n", dev->name);
1716 } 1711 }
1717 } 1712 }
1718 else { 1713 else {
1719 if (dev->flags & IFF_RUNNING) { 1714 if (netif_carrier_ok(dev)) {
1720 netif_carrier_off(dev); 1715 netif_carrier_off(dev);
1721 dev->flags &= ~IFF_RUNNING;
1722 dev->if_port = 0; 1716 dev->if_port = 0;
1723 printk(KERN_INFO "%s: link down\n", dev->name); 1717 printk(KERN_INFO "%s: link down\n", dev->name);
1724 } 1718 }
diff --git a/drivers/net/bmac.c b/drivers/net/bmac.c
index 734bd4ee3f9b..00e5257b176f 100644
--- a/drivers/net/bmac.c
+++ b/drivers/net/bmac.c
@@ -1412,7 +1412,6 @@ static int bmac_open(struct net_device *dev)
1412 bp->opened = 1; 1412 bp->opened = 1;
1413 bmac_reset_and_enable(dev); 1413 bmac_reset_and_enable(dev);
1414 enable_irq(dev->irq); 1414 enable_irq(dev->irq);
1415 dev->flags |= IFF_RUNNING;
1416 return 0; 1415 return 0;
1417} 1416}
1418 1417
@@ -1425,7 +1424,6 @@ static int bmac_close(struct net_device *dev)
1425 int i; 1424 int i;
1426 1425
1427 bp->sleeping = 1; 1426 bp->sleeping = 1;
1428 dev->flags &= ~(IFF_UP | IFF_RUNNING);
1429 1427
1430 /* disable rx and tx */ 1428 /* disable rx and tx */
1431 config = bmread(dev, RXCFG); 1429 config = bmread(dev, RXCFG);
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
new file mode 100644
index 000000000000..8acc655ec1e8
--- /dev/null
+++ b/drivers/net/bnx2.c
@@ -0,0 +1,5530 @@
1/* bnx2.c: Broadcom NX2 network driver.
2 *
3 * Copyright (c) 2004, 2005 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
12#include "bnx2.h"
13#include "bnx2_fw.h"
14
15#define DRV_MODULE_NAME "bnx2"
16#define PFX DRV_MODULE_NAME ": "
17#define DRV_MODULE_VERSION "1.2.19"
18#define DRV_MODULE_RELDATE "May 23, 2005"
19
20#define RUN_AT(x) (jiffies + (x))
21
22/* Time in jiffies before concluding the transmitter is hung. */
23#define TX_TIMEOUT (5*HZ)
24
25static char version[] __devinitdata =
26 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
27
28MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
29MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706 Driver");
30MODULE_LICENSE("GPL");
31MODULE_VERSION(DRV_MODULE_VERSION);
32
33static int disable_msi = 0;
34
35module_param(disable_msi, int, 0);
36MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
37
38typedef enum {
39 BCM5706 = 0,
40 NC370T,
41 NC370I,
42 BCM5706S,
43 NC370F,
44} board_t;
45
46/* indexed by board_t, above */
47static struct {
48 char *name;
49} board_info[] __devinitdata = {
50 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
51 { "HP NC370T Multifunction Gigabit Server Adapter" },
52 { "HP NC370i Multifunction Gigabit Server Adapter" },
53 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
54 { "HP NC370F Multifunction Gigabit Server Adapter" },
55 { 0 },
56 };
57
58static struct pci_device_id bnx2_pci_tbl[] = {
59 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
60 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
61 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
62 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
63 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
64 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
65 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
66 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
67 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
68 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
69 { 0, }
70};
71
72static struct flash_spec flash_table[] =
73{
74 /* Slow EEPROM */
75 {0x00000000, 0x40030380, 0x009f0081, 0xa184a053, 0xaf000400,
76 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
77 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
78 "EEPROM - slow"},
79 /* Fast EEPROM */
80 {0x02000000, 0x62008380, 0x009f0081, 0xa184a053, 0xaf000400,
81 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
82 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
83 "EEPROM - fast"},
84 /* ATMEL AT45DB011B (buffered flash) */
85 {0x02000003, 0x6e008173, 0x00570081, 0x68848353, 0xaf000400,
86 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
87 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
88 "Buffered flash"},
89 /* Saifun SA25F005 (non-buffered flash) */
90 /* strap, cfg1, & write1 need updates */
91 {0x01000003, 0x5f008081, 0x00050081, 0x03840253, 0xaf020406,
92 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
93 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
94 "Non-buffered flash (64kB)"},
95 /* Saifun SA25F010 (non-buffered flash) */
96 /* strap, cfg1, & write1 need updates */
97 {0x00000001, 0x47008081, 0x00050081, 0x03840253, 0xaf020406,
98 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
99 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
100 "Non-buffered flash (128kB)"},
101 /* Saifun SA25F020 (non-buffered flash) */
102 /* strap, cfg1, & write1 need updates */
103 {0x00000003, 0x4f008081, 0x00050081, 0x03840253, 0xaf020406,
104 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
105 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
106 "Non-buffered flash (256kB)"},
107};
108
109MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
110
111static u32
112bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
113{
114 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
115 return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
116}
117
118static void
119bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
120{
121 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
122 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
123}
124
125static void
126bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
127{
128 offset += cid_addr;
129 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
130 REG_WR(bp, BNX2_CTX_DATA, val);
131}
132
133static int
134bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
135{
136 u32 val1;
137 int i, ret;
138
139 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
140 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
141 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
142
143 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
144 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
145
146 udelay(40);
147 }
148
149 val1 = (bp->phy_addr << 21) | (reg << 16) |
150 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
151 BNX2_EMAC_MDIO_COMM_START_BUSY;
152 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
153
154 for (i = 0; i < 50; i++) {
155 udelay(10);
156
157 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
158 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
159 udelay(5);
160
161 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
162 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
163
164 break;
165 }
166 }
167
168 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
169 *val = 0x0;
170 ret = -EBUSY;
171 }
172 else {
173 *val = val1;
174 ret = 0;
175 }
176
177 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
178 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
179 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
180
181 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
182 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
183
184 udelay(40);
185 }
186
187 return ret;
188}
189
190static int
191bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
192{
193 u32 val1;
194 int i, ret;
195
196 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
197 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
198 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
199
200 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
201 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
202
203 udelay(40);
204 }
205
206 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
207 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
208 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
209 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
210
211 for (i = 0; i < 50; i++) {
212 udelay(10);
213
214 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
215 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
216 udelay(5);
217 break;
218 }
219 }
220
221 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
222 ret = -EBUSY;
223 else
224 ret = 0;
225
226 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
227 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
228 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
229
230 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
231 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
232
233 udelay(40);
234 }
235
236 return ret;
237}
238
239static void
240bnx2_disable_int(struct bnx2 *bp)
241{
242 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
243 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
244 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
245}
246
247static void
248bnx2_enable_int(struct bnx2 *bp)
249{
250 u32 val;
251
252 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
253 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
254
255 val = REG_RD(bp, BNX2_HC_COMMAND);
256 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
257}
258
259static void
260bnx2_disable_int_sync(struct bnx2 *bp)
261{
262 atomic_inc(&bp->intr_sem);
263 bnx2_disable_int(bp);
264 synchronize_irq(bp->pdev->irq);
265}
266
267static void
268bnx2_netif_stop(struct bnx2 *bp)
269{
270 bnx2_disable_int_sync(bp);
271 if (netif_running(bp->dev)) {
272 netif_poll_disable(bp->dev);
273 netif_tx_disable(bp->dev);
274 bp->dev->trans_start = jiffies; /* prevent tx timeout */
275 }
276}
277
278static void
279bnx2_netif_start(struct bnx2 *bp)
280{
281 if (atomic_dec_and_test(&bp->intr_sem)) {
282 if (netif_running(bp->dev)) {
283 netif_wake_queue(bp->dev);
284 netif_poll_enable(bp->dev);
285 bnx2_enable_int(bp);
286 }
287 }
288}
289
290static void
291bnx2_free_mem(struct bnx2 *bp)
292{
293 if (bp->stats_blk) {
294 pci_free_consistent(bp->pdev, sizeof(struct statistics_block),
295 bp->stats_blk, bp->stats_blk_mapping);
296 bp->stats_blk = NULL;
297 }
298 if (bp->status_blk) {
299 pci_free_consistent(bp->pdev, sizeof(struct status_block),
300 bp->status_blk, bp->status_blk_mapping);
301 bp->status_blk = NULL;
302 }
303 if (bp->tx_desc_ring) {
304 pci_free_consistent(bp->pdev,
305 sizeof(struct tx_bd) * TX_DESC_CNT,
306 bp->tx_desc_ring, bp->tx_desc_mapping);
307 bp->tx_desc_ring = NULL;
308 }
309 if (bp->tx_buf_ring) {
310 kfree(bp->tx_buf_ring);
311 bp->tx_buf_ring = NULL;
312 }
313 if (bp->rx_desc_ring) {
314 pci_free_consistent(bp->pdev,
315 sizeof(struct rx_bd) * RX_DESC_CNT,
316 bp->rx_desc_ring, bp->rx_desc_mapping);
317 bp->rx_desc_ring = NULL;
318 }
319 if (bp->rx_buf_ring) {
320 kfree(bp->rx_buf_ring);
321 bp->rx_buf_ring = NULL;
322 }
323}
324
325static int
326bnx2_alloc_mem(struct bnx2 *bp)
327{
328 bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
329 GFP_KERNEL);
330 if (bp->tx_buf_ring == NULL)
331 return -ENOMEM;
332
333 memset(bp->tx_buf_ring, 0, sizeof(struct sw_bd) * TX_DESC_CNT);
334 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
335 sizeof(struct tx_bd) *
336 TX_DESC_CNT,
337 &bp->tx_desc_mapping);
338 if (bp->tx_desc_ring == NULL)
339 goto alloc_mem_err;
340
341 bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT,
342 GFP_KERNEL);
343 if (bp->rx_buf_ring == NULL)
344 goto alloc_mem_err;
345
346 memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT);
347 bp->rx_desc_ring = pci_alloc_consistent(bp->pdev,
348 sizeof(struct rx_bd) *
349 RX_DESC_CNT,
350 &bp->rx_desc_mapping);
351 if (bp->rx_desc_ring == NULL)
352 goto alloc_mem_err;
353
354 bp->status_blk = pci_alloc_consistent(bp->pdev,
355 sizeof(struct status_block),
356 &bp->status_blk_mapping);
357 if (bp->status_blk == NULL)
358 goto alloc_mem_err;
359
360 memset(bp->status_blk, 0, sizeof(struct status_block));
361
362 bp->stats_blk = pci_alloc_consistent(bp->pdev,
363 sizeof(struct statistics_block),
364 &bp->stats_blk_mapping);
365 if (bp->stats_blk == NULL)
366 goto alloc_mem_err;
367
368 memset(bp->stats_blk, 0, sizeof(struct statistics_block));
369
370 return 0;
371
372alloc_mem_err:
373 bnx2_free_mem(bp);
374 return -ENOMEM;
375}
376
377static void
378bnx2_report_link(struct bnx2 *bp)
379{
380 if (bp->link_up) {
381 netif_carrier_on(bp->dev);
382 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
383
384 printk("%d Mbps ", bp->line_speed);
385
386 if (bp->duplex == DUPLEX_FULL)
387 printk("full duplex");
388 else
389 printk("half duplex");
390
391 if (bp->flow_ctrl) {
392 if (bp->flow_ctrl & FLOW_CTRL_RX) {
393 printk(", receive ");
394 if (bp->flow_ctrl & FLOW_CTRL_TX)
395 printk("& transmit ");
396 }
397 else {
398 printk(", transmit ");
399 }
400 printk("flow control ON");
401 }
402 printk("\n");
403 }
404 else {
405 netif_carrier_off(bp->dev);
406 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
407 }
408}
409
410static void
411bnx2_resolve_flow_ctrl(struct bnx2 *bp)
412{
413 u32 local_adv, remote_adv;
414
415 bp->flow_ctrl = 0;
416 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
417 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
418
419 if (bp->duplex == DUPLEX_FULL) {
420 bp->flow_ctrl = bp->req_flow_ctrl;
421 }
422 return;
423 }
424
425 if (bp->duplex != DUPLEX_FULL) {
426 return;
427 }
428
429 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
430 bnx2_read_phy(bp, MII_LPA, &remote_adv);
431
432 if (bp->phy_flags & PHY_SERDES_FLAG) {
433 u32 new_local_adv = 0;
434 u32 new_remote_adv = 0;
435
436 if (local_adv & ADVERTISE_1000XPAUSE)
437 new_local_adv |= ADVERTISE_PAUSE_CAP;
438 if (local_adv & ADVERTISE_1000XPSE_ASYM)
439 new_local_adv |= ADVERTISE_PAUSE_ASYM;
440 if (remote_adv & ADVERTISE_1000XPAUSE)
441 new_remote_adv |= ADVERTISE_PAUSE_CAP;
442 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
443 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
444
445 local_adv = new_local_adv;
446 remote_adv = new_remote_adv;
447 }
448
449 /* See Table 28B-3 of 802.3ab-1999 spec. */
450 if (local_adv & ADVERTISE_PAUSE_CAP) {
451 if(local_adv & ADVERTISE_PAUSE_ASYM) {
452 if (remote_adv & ADVERTISE_PAUSE_CAP) {
453 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
454 }
455 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
456 bp->flow_ctrl = FLOW_CTRL_RX;
457 }
458 }
459 else {
460 if (remote_adv & ADVERTISE_PAUSE_CAP) {
461 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
462 }
463 }
464 }
465 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
466 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
467 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
468
469 bp->flow_ctrl = FLOW_CTRL_TX;
470 }
471 }
472}
473
474static int
475bnx2_serdes_linkup(struct bnx2 *bp)
476{
477 u32 bmcr, local_adv, remote_adv, common;
478
479 bp->link_up = 1;
480 bp->line_speed = SPEED_1000;
481
482 bnx2_read_phy(bp, MII_BMCR, &bmcr);
483 if (bmcr & BMCR_FULLDPLX) {
484 bp->duplex = DUPLEX_FULL;
485 }
486 else {
487 bp->duplex = DUPLEX_HALF;
488 }
489
490 if (!(bmcr & BMCR_ANENABLE)) {
491 return 0;
492 }
493
494 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
495 bnx2_read_phy(bp, MII_LPA, &remote_adv);
496
497 common = local_adv & remote_adv;
498 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
499
500 if (common & ADVERTISE_1000XFULL) {
501 bp->duplex = DUPLEX_FULL;
502 }
503 else {
504 bp->duplex = DUPLEX_HALF;
505 }
506 }
507
508 return 0;
509}
510
511static int
512bnx2_copper_linkup(struct bnx2 *bp)
513{
514 u32 bmcr;
515
516 bnx2_read_phy(bp, MII_BMCR, &bmcr);
517 if (bmcr & BMCR_ANENABLE) {
518 u32 local_adv, remote_adv, common;
519
520 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
521 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
522
523 common = local_adv & (remote_adv >> 2);
524 if (common & ADVERTISE_1000FULL) {
525 bp->line_speed = SPEED_1000;
526 bp->duplex = DUPLEX_FULL;
527 }
528 else if (common & ADVERTISE_1000HALF) {
529 bp->line_speed = SPEED_1000;
530 bp->duplex = DUPLEX_HALF;
531 }
532 else {
533 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
534 bnx2_read_phy(bp, MII_LPA, &remote_adv);
535
536 common = local_adv & remote_adv;
537 if (common & ADVERTISE_100FULL) {
538 bp->line_speed = SPEED_100;
539 bp->duplex = DUPLEX_FULL;
540 }
541 else if (common & ADVERTISE_100HALF) {
542 bp->line_speed = SPEED_100;
543 bp->duplex = DUPLEX_HALF;
544 }
545 else if (common & ADVERTISE_10FULL) {
546 bp->line_speed = SPEED_10;
547 bp->duplex = DUPLEX_FULL;
548 }
549 else if (common & ADVERTISE_10HALF) {
550 bp->line_speed = SPEED_10;
551 bp->duplex = DUPLEX_HALF;
552 }
553 else {
554 bp->line_speed = 0;
555 bp->link_up = 0;
556 }
557 }
558 }
559 else {
560 if (bmcr & BMCR_SPEED100) {
561 bp->line_speed = SPEED_100;
562 }
563 else {
564 bp->line_speed = SPEED_10;
565 }
566 if (bmcr & BMCR_FULLDPLX) {
567 bp->duplex = DUPLEX_FULL;
568 }
569 else {
570 bp->duplex = DUPLEX_HALF;
571 }
572 }
573
574 return 0;
575}
576
577static int
578bnx2_set_mac_link(struct bnx2 *bp)
579{
580 u32 val;
581
582 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
583 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
584 (bp->duplex == DUPLEX_HALF)) {
585 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
586 }
587
588 /* Configure the EMAC mode register. */
589 val = REG_RD(bp, BNX2_EMAC_MODE);
590
591 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
592 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK);
593
594 if (bp->link_up) {
595 if (bp->line_speed != SPEED_1000)
596 val |= BNX2_EMAC_MODE_PORT_MII;
597 else
598 val |= BNX2_EMAC_MODE_PORT_GMII;
599 }
600 else {
601 val |= BNX2_EMAC_MODE_PORT_GMII;
602 }
603
604 /* Set the MAC to operate in the appropriate duplex mode. */
605 if (bp->duplex == DUPLEX_HALF)
606 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
607 REG_WR(bp, BNX2_EMAC_MODE, val);
608
609 /* Enable/disable rx PAUSE. */
610 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
611
612 if (bp->flow_ctrl & FLOW_CTRL_RX)
613 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
614 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
615
616 /* Enable/disable tx PAUSE. */
617 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
618 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
619
620 if (bp->flow_ctrl & FLOW_CTRL_TX)
621 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
622 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
623
624 /* Acknowledge the interrupt. */
625 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
626
627 return 0;
628}
629
630static int
631bnx2_set_link(struct bnx2 *bp)
632{
633 u32 bmsr;
634 u8 link_up;
635
636 if (bp->loopback == MAC_LOOPBACK) {
637 bp->link_up = 1;
638 return 0;
639 }
640
641 link_up = bp->link_up;
642
643 bnx2_read_phy(bp, MII_BMSR, &bmsr);
644 bnx2_read_phy(bp, MII_BMSR, &bmsr);
645
646 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
647 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
648 u32 val;
649
650 val = REG_RD(bp, BNX2_EMAC_STATUS);
651 if (val & BNX2_EMAC_STATUS_LINK)
652 bmsr |= BMSR_LSTATUS;
653 else
654 bmsr &= ~BMSR_LSTATUS;
655 }
656
657 if (bmsr & BMSR_LSTATUS) {
658 bp->link_up = 1;
659
660 if (bp->phy_flags & PHY_SERDES_FLAG) {
661 bnx2_serdes_linkup(bp);
662 }
663 else {
664 bnx2_copper_linkup(bp);
665 }
666 bnx2_resolve_flow_ctrl(bp);
667 }
668 else {
669 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
670 (bp->autoneg & AUTONEG_SPEED)) {
671
672 u32 bmcr;
673
674 bnx2_read_phy(bp, MII_BMCR, &bmcr);
675 if (!(bmcr & BMCR_ANENABLE)) {
676 bnx2_write_phy(bp, MII_BMCR, bmcr |
677 BMCR_ANENABLE);
678 }
679 }
680 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
681 bp->link_up = 0;
682 }
683
684 if (bp->link_up != link_up) {
685 bnx2_report_link(bp);
686 }
687
688 bnx2_set_mac_link(bp);
689
690 return 0;
691}
692
693static int
694bnx2_reset_phy(struct bnx2 *bp)
695{
696 int i;
697 u32 reg;
698
699 bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
700
701#define PHY_RESET_MAX_WAIT 100
702 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
703 udelay(10);
704
705 bnx2_read_phy(bp, MII_BMCR, &reg);
706 if (!(reg & BMCR_RESET)) {
707 udelay(20);
708 break;
709 }
710 }
711 if (i == PHY_RESET_MAX_WAIT) {
712 return -EBUSY;
713 }
714 return 0;
715}
716
717static u32
718bnx2_phy_get_pause_adv(struct bnx2 *bp)
719{
720 u32 adv = 0;
721
722 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
723 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
724
725 if (bp->phy_flags & PHY_SERDES_FLAG) {
726 adv = ADVERTISE_1000XPAUSE;
727 }
728 else {
729 adv = ADVERTISE_PAUSE_CAP;
730 }
731 }
732 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
733 if (bp->phy_flags & PHY_SERDES_FLAG) {
734 adv = ADVERTISE_1000XPSE_ASYM;
735 }
736 else {
737 adv = ADVERTISE_PAUSE_ASYM;
738 }
739 }
740 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
741 if (bp->phy_flags & PHY_SERDES_FLAG) {
742 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
743 }
744 else {
745 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
746 }
747 }
748 return adv;
749}
750
751static int
752bnx2_setup_serdes_phy(struct bnx2 *bp)
753{
754 u32 adv, bmcr;
755 u32 new_adv = 0;
756
757 if (!(bp->autoneg & AUTONEG_SPEED)) {
758 u32 new_bmcr;
759
760 bnx2_read_phy(bp, MII_BMCR, &bmcr);
761 new_bmcr = bmcr & ~BMCR_ANENABLE;
762 new_bmcr |= BMCR_SPEED1000;
763 if (bp->req_duplex == DUPLEX_FULL) {
764 new_bmcr |= BMCR_FULLDPLX;
765 }
766 else {
767 new_bmcr &= ~BMCR_FULLDPLX;
768 }
769 if (new_bmcr != bmcr) {
770 /* Force a link down visible on the other side */
771 if (bp->link_up) {
772 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
773 adv &= ~(ADVERTISE_1000XFULL |
774 ADVERTISE_1000XHALF);
775 bnx2_write_phy(bp, MII_ADVERTISE, adv);
776 bnx2_write_phy(bp, MII_BMCR, bmcr |
777 BMCR_ANRESTART | BMCR_ANENABLE);
778
779 bp->link_up = 0;
780 netif_carrier_off(bp->dev);
781 }
782 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
783 }
784 return 0;
785 }
786
787 if (bp->advertising & ADVERTISED_1000baseT_Full)
788 new_adv |= ADVERTISE_1000XFULL;
789
790 new_adv |= bnx2_phy_get_pause_adv(bp);
791
792 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
793 bnx2_read_phy(bp, MII_BMCR, &bmcr);
794
795 bp->serdes_an_pending = 0;
796 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
797 /* Force a link down visible on the other side */
798 if (bp->link_up) {
799 int i;
800
801 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
802 for (i = 0; i < 110; i++) {
803 udelay(100);
804 }
805 }
806
807 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
808 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
809 BMCR_ANENABLE);
810 bp->serdes_an_pending = SERDES_AN_TIMEOUT / bp->timer_interval;
811 }
812
813 return 0;
814}
815
816#define ETHTOOL_ALL_FIBRE_SPEED \
817 (ADVERTISED_1000baseT_Full)
818
819#define ETHTOOL_ALL_COPPER_SPEED \
820 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
821 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
822 ADVERTISED_1000baseT_Full)
823
824#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
825 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
826
827#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
828
829static int
830bnx2_setup_copper_phy(struct bnx2 *bp)
831{
832 u32 bmcr;
833 u32 new_bmcr;
834
835 bnx2_read_phy(bp, MII_BMCR, &bmcr);
836
837 if (bp->autoneg & AUTONEG_SPEED) {
838 u32 adv_reg, adv1000_reg;
839 u32 new_adv_reg = 0;
840 u32 new_adv1000_reg = 0;
841
842 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
843 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
844 ADVERTISE_PAUSE_ASYM);
845
846 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
847 adv1000_reg &= PHY_ALL_1000_SPEED;
848
849 if (bp->advertising & ADVERTISED_10baseT_Half)
850 new_adv_reg |= ADVERTISE_10HALF;
851 if (bp->advertising & ADVERTISED_10baseT_Full)
852 new_adv_reg |= ADVERTISE_10FULL;
853 if (bp->advertising & ADVERTISED_100baseT_Half)
854 new_adv_reg |= ADVERTISE_100HALF;
855 if (bp->advertising & ADVERTISED_100baseT_Full)
856 new_adv_reg |= ADVERTISE_100FULL;
857 if (bp->advertising & ADVERTISED_1000baseT_Full)
858 new_adv1000_reg |= ADVERTISE_1000FULL;
859
860 new_adv_reg |= ADVERTISE_CSMA;
861
862 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
863
864 if ((adv1000_reg != new_adv1000_reg) ||
865 (adv_reg != new_adv_reg) ||
866 ((bmcr & BMCR_ANENABLE) == 0)) {
867
868 bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
869 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
870 bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
871 BMCR_ANENABLE);
872 }
873 else if (bp->link_up) {
874 /* Flow ctrl may have changed from auto to forced */
875 /* or vice-versa. */
876
877 bnx2_resolve_flow_ctrl(bp);
878 bnx2_set_mac_link(bp);
879 }
880 return 0;
881 }
882
883 new_bmcr = 0;
884 if (bp->req_line_speed == SPEED_100) {
885 new_bmcr |= BMCR_SPEED100;
886 }
887 if (bp->req_duplex == DUPLEX_FULL) {
888 new_bmcr |= BMCR_FULLDPLX;
889 }
890 if (new_bmcr != bmcr) {
891 u32 bmsr;
892 int i = 0;
893
894 bnx2_read_phy(bp, MII_BMSR, &bmsr);
895 bnx2_read_phy(bp, MII_BMSR, &bmsr);
896
897 if (bmsr & BMSR_LSTATUS) {
898 /* Force link down */
899 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
900 do {
901 udelay(100);
902 bnx2_read_phy(bp, MII_BMSR, &bmsr);
903 bnx2_read_phy(bp, MII_BMSR, &bmsr);
904 i++;
905 } while ((bmsr & BMSR_LSTATUS) && (i < 620));
906 }
907
908 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
909
910 /* Normally, the new speed is setup after the link has
911 * gone down and up again. In some cases, link will not go
912 * down so we need to set up the new speed here.
913 */
914 if (bmsr & BMSR_LSTATUS) {
915 bp->line_speed = bp->req_line_speed;
916 bp->duplex = bp->req_duplex;
917 bnx2_resolve_flow_ctrl(bp);
918 bnx2_set_mac_link(bp);
919 }
920 }
921 return 0;
922}
923
924static int
925bnx2_setup_phy(struct bnx2 *bp)
926{
927 if (bp->loopback == MAC_LOOPBACK)
928 return 0;
929
930 if (bp->phy_flags & PHY_SERDES_FLAG) {
931 return (bnx2_setup_serdes_phy(bp));
932 }
933 else {
934 return (bnx2_setup_copper_phy(bp));
935 }
936}
937
938static int
939bnx2_init_serdes_phy(struct bnx2 *bp)
940{
941 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
942
943 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
944 REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
945 }
946
947 if (bp->dev->mtu > 1500) {
948 u32 val;
949
950 /* Set extended packet length bit */
951 bnx2_write_phy(bp, 0x18, 0x7);
952 bnx2_read_phy(bp, 0x18, &val);
953 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
954
955 bnx2_write_phy(bp, 0x1c, 0x6c00);
956 bnx2_read_phy(bp, 0x1c, &val);
957 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
958 }
959 else {
960 u32 val;
961
962 bnx2_write_phy(bp, 0x18, 0x7);
963 bnx2_read_phy(bp, 0x18, &val);
964 bnx2_write_phy(bp, 0x18, val & ~0x4007);
965
966 bnx2_write_phy(bp, 0x1c, 0x6c00);
967 bnx2_read_phy(bp, 0x1c, &val);
968 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
969 }
970
971 return 0;
972}
973
974static int
975bnx2_init_copper_phy(struct bnx2 *bp)
976{
977 bp->phy_flags |= PHY_CRC_FIX_FLAG;
978
979 if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
980 bnx2_write_phy(bp, 0x18, 0x0c00);
981 bnx2_write_phy(bp, 0x17, 0x000a);
982 bnx2_write_phy(bp, 0x15, 0x310b);
983 bnx2_write_phy(bp, 0x17, 0x201f);
984 bnx2_write_phy(bp, 0x15, 0x9506);
985 bnx2_write_phy(bp, 0x17, 0x401f);
986 bnx2_write_phy(bp, 0x15, 0x14e2);
987 bnx2_write_phy(bp, 0x18, 0x0400);
988 }
989
990 if (bp->dev->mtu > 1500) {
991 u32 val;
992
993 /* Set extended packet length bit */
994 bnx2_write_phy(bp, 0x18, 0x7);
995 bnx2_read_phy(bp, 0x18, &val);
996 bnx2_write_phy(bp, 0x18, val | 0x4000);
997
998 bnx2_read_phy(bp, 0x10, &val);
999 bnx2_write_phy(bp, 0x10, val | 0x1);
1000 }
1001 else {
1002 u32 val;
1003
1004 bnx2_write_phy(bp, 0x18, 0x7);
1005 bnx2_read_phy(bp, 0x18, &val);
1006 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1007
1008 bnx2_read_phy(bp, 0x10, &val);
1009 bnx2_write_phy(bp, 0x10, val & ~0x1);
1010 }
1011
1012 return 0;
1013}
1014
1015
1016static int
1017bnx2_init_phy(struct bnx2 *bp)
1018{
1019 u32 val;
1020 int rc = 0;
1021
1022 bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1023 bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1024
1025 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1026
1027 bnx2_reset_phy(bp);
1028
1029 bnx2_read_phy(bp, MII_PHYSID1, &val);
1030 bp->phy_id = val << 16;
1031 bnx2_read_phy(bp, MII_PHYSID2, &val);
1032 bp->phy_id |= val & 0xffff;
1033
1034 if (bp->phy_flags & PHY_SERDES_FLAG) {
1035 rc = bnx2_init_serdes_phy(bp);
1036 }
1037 else {
1038 rc = bnx2_init_copper_phy(bp);
1039 }
1040
1041 bnx2_setup_phy(bp);
1042
1043 return rc;
1044}
1045
1046static int
1047bnx2_set_mac_loopback(struct bnx2 *bp)
1048{
1049 u32 mac_mode;
1050
1051 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1052 mac_mode &= ~BNX2_EMAC_MODE_PORT;
1053 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1054 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1055 bp->link_up = 1;
1056 return 0;
1057}
1058
1059static int
1060bnx2_fw_sync(struct bnx2 *bp, u32 msg_data)
1061{
1062 int i;
1063 u32 val;
1064
1065 if (bp->fw_timed_out)
1066 return -EBUSY;
1067
1068 bp->fw_wr_seq++;
1069 msg_data |= bp->fw_wr_seq;
1070
1071 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);
1072
1073 /* wait for an acknowledgement. */
1074 for (i = 0; i < (FW_ACK_TIME_OUT_MS * 1000)/5; i++) {
1075 udelay(5);
1076
1077 val = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_FW_MB);
1078
1079 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1080 break;
1081 }
1082
1083 /* If we timed out, inform the firmware that this is the case. */
1084 if (((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) &&
1085 ((msg_data & BNX2_DRV_MSG_DATA) != BNX2_DRV_MSG_DATA_WAIT0)) {
1086
1087 msg_data &= ~BNX2_DRV_MSG_CODE;
1088 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1089
1090 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);
1091
1092 bp->fw_timed_out = 1;
1093
1094 return -EBUSY;
1095 }
1096
1097 return 0;
1098}
1099
1100static void
1101bnx2_init_context(struct bnx2 *bp)
1102{
1103 u32 vcid;
1104
1105 vcid = 96;
1106 while (vcid) {
1107 u32 vcid_addr, pcid_addr, offset;
1108
1109 vcid--;
1110
1111 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1112 u32 new_vcid;
1113
1114 vcid_addr = GET_PCID_ADDR(vcid);
1115 if (vcid & 0x8) {
1116 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1117 }
1118 else {
1119 new_vcid = vcid;
1120 }
1121 pcid_addr = GET_PCID_ADDR(new_vcid);
1122 }
1123 else {
1124 vcid_addr = GET_CID_ADDR(vcid);
1125 pcid_addr = vcid_addr;
1126 }
1127
1128 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1129 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1130
1131 /* Zero out the context. */
1132 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
1133 CTX_WR(bp, 0x00, offset, 0);
1134 }
1135
1136 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1137 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1138 }
1139}
1140
1141static int
1142bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1143{
1144 u16 *good_mbuf;
1145 u32 good_mbuf_cnt;
1146 u32 val;
1147
1148 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
1149 if (good_mbuf == NULL) {
1150 printk(KERN_ERR PFX "Failed to allocate memory in "
1151 "bnx2_alloc_bad_rbuf\n");
1152 return -ENOMEM;
1153 }
1154
1155 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1156 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1157
1158 good_mbuf_cnt = 0;
1159
1160 /* Allocate a bunch of mbufs and save the good ones in an array. */
1161 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1162 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1163 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1164
1165 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1166
1167 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1168
1169 /* The addresses with Bit 9 set are bad memory blocks. */
1170 if (!(val & (1 << 9))) {
1171 good_mbuf[good_mbuf_cnt] = (u16) val;
1172 good_mbuf_cnt++;
1173 }
1174
1175 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1176 }
1177
1178 /* Free the good ones back to the mbuf pool thus discarding
1179 * all the bad ones. */
1180 while (good_mbuf_cnt) {
1181 good_mbuf_cnt--;
1182
1183 val = good_mbuf[good_mbuf_cnt];
1184 val = (val << 9) | val | 1;
1185
1186 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1187 }
1188 kfree(good_mbuf);
1189 return 0;
1190}
1191
1192static void
1193bnx2_set_mac_addr(struct bnx2 *bp)
1194{
1195 u32 val;
1196 u8 *mac_addr = bp->dev->dev_addr;
1197
1198 val = (mac_addr[0] << 8) | mac_addr[1];
1199
1200 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1201
1202 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
1203 (mac_addr[4] << 8) | mac_addr[5];
1204
1205 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1206}
1207
1208static inline int
1209bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
1210{
1211 struct sk_buff *skb;
1212 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
1213 dma_addr_t mapping;
1214 struct rx_bd *rxbd = &bp->rx_desc_ring[index];
1215 unsigned long align;
1216
1217 skb = dev_alloc_skb(bp->rx_buf_size);
1218 if (skb == NULL) {
1219 return -ENOMEM;
1220 }
1221
1222 if (unlikely((align = (unsigned long) skb->data & 0x7))) {
1223 skb_reserve(skb, 8 - align);
1224 }
1225
1226 skb->dev = bp->dev;
1227 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1228 PCI_DMA_FROMDEVICE);
1229
1230 rx_buf->skb = skb;
1231 pci_unmap_addr_set(rx_buf, mapping, mapping);
1232
1233 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
1234 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
1235
1236 bp->rx_prod_bseq += bp->rx_buf_use_size;
1237
1238 return 0;
1239}
1240
1241static void
1242bnx2_phy_int(struct bnx2 *bp)
1243{
1244 u32 new_link_state, old_link_state;
1245
1246 new_link_state = bp->status_blk->status_attn_bits &
1247 STATUS_ATTN_BITS_LINK_STATE;
1248 old_link_state = bp->status_blk->status_attn_bits_ack &
1249 STATUS_ATTN_BITS_LINK_STATE;
1250 if (new_link_state != old_link_state) {
1251 if (new_link_state) {
1252 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
1253 STATUS_ATTN_BITS_LINK_STATE);
1254 }
1255 else {
1256 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
1257 STATUS_ATTN_BITS_LINK_STATE);
1258 }
1259 bnx2_set_link(bp);
1260 }
1261}
1262
1263static void
1264bnx2_tx_int(struct bnx2 *bp)
1265{
1266 u16 hw_cons, sw_cons, sw_ring_cons;
1267 int tx_free_bd = 0;
1268
1269 hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
1270 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1271 hw_cons++;
1272 }
1273 sw_cons = bp->tx_cons;
1274
1275 while (sw_cons != hw_cons) {
1276 struct sw_bd *tx_buf;
1277 struct sk_buff *skb;
1278 int i, last;
1279
1280 sw_ring_cons = TX_RING_IDX(sw_cons);
1281
1282 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
1283 skb = tx_buf->skb;
1284#ifdef BCM_TSO
1285 /* partial BD completions possible with TSO packets */
1286 if (skb_shinfo(skb)->tso_size) {
1287 u16 last_idx, last_ring_idx;
1288
1289 last_idx = sw_cons +
1290 skb_shinfo(skb)->nr_frags + 1;
1291 last_ring_idx = sw_ring_cons +
1292 skb_shinfo(skb)->nr_frags + 1;
1293 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
1294 last_idx++;
1295 }
1296 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
1297 break;
1298 }
1299 }
1300#endif
1301 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
1302 skb_headlen(skb), PCI_DMA_TODEVICE);
1303
1304 tx_buf->skb = NULL;
1305 last = skb_shinfo(skb)->nr_frags;
1306
1307 for (i = 0; i < last; i++) {
1308 sw_cons = NEXT_TX_BD(sw_cons);
1309
1310 pci_unmap_page(bp->pdev,
1311 pci_unmap_addr(
1312 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
1313 mapping),
1314 skb_shinfo(skb)->frags[i].size,
1315 PCI_DMA_TODEVICE);
1316 }
1317
1318 sw_cons = NEXT_TX_BD(sw_cons);
1319
1320 tx_free_bd += last + 1;
1321
1322 dev_kfree_skb_irq(skb);
1323
1324 hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
1325 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1326 hw_cons++;
1327 }
1328 }
1329
1330 atomic_add(tx_free_bd, &bp->tx_avail_bd);
1331
1332 if (unlikely(netif_queue_stopped(bp->dev))) {
1333 unsigned long flags;
1334
1335 spin_lock_irqsave(&bp->tx_lock, flags);
1336 if ((netif_queue_stopped(bp->dev)) &&
1337 (atomic_read(&bp->tx_avail_bd) > MAX_SKB_FRAGS)) {
1338
1339 netif_wake_queue(bp->dev);
1340 }
1341 spin_unlock_irqrestore(&bp->tx_lock, flags);
1342 }
1343
1344 bp->tx_cons = sw_cons;
1345
1346}
1347
1348static inline void
1349bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
1350 u16 cons, u16 prod)
1351{
1352 struct sw_bd *cons_rx_buf = &bp->rx_buf_ring[cons];
1353 struct sw_bd *prod_rx_buf = &bp->rx_buf_ring[prod];
1354 struct rx_bd *cons_bd = &bp->rx_desc_ring[cons];
1355 struct rx_bd *prod_bd = &bp->rx_desc_ring[prod];
1356
1357 pci_dma_sync_single_for_device(bp->pdev,
1358 pci_unmap_addr(cons_rx_buf, mapping),
1359 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1360
1361 prod_rx_buf->skb = cons_rx_buf->skb;
1362 pci_unmap_addr_set(prod_rx_buf, mapping,
1363 pci_unmap_addr(cons_rx_buf, mapping));
1364
1365 memcpy(prod_bd, cons_bd, 8);
1366
1367 bp->rx_prod_bseq += bp->rx_buf_use_size;
1368
1369}
1370
1371static int
1372bnx2_rx_int(struct bnx2 *bp, int budget)
1373{
1374 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
1375 struct l2_fhdr *rx_hdr;
1376 int rx_pkt = 0;
1377
1378 hw_cons = bp->status_blk->status_rx_quick_consumer_index0;
1379 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
1380 hw_cons++;
1381 }
1382 sw_cons = bp->rx_cons;
1383 sw_prod = bp->rx_prod;
1384
1385 /* Memory barrier necessary as speculative reads of the rx
1386 * buffer can be ahead of the index in the status block
1387 */
1388 rmb();
1389 while (sw_cons != hw_cons) {
1390 unsigned int len;
1391 u16 status;
1392 struct sw_bd *rx_buf;
1393 struct sk_buff *skb;
1394
1395 sw_ring_cons = RX_RING_IDX(sw_cons);
1396 sw_ring_prod = RX_RING_IDX(sw_prod);
1397
1398 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
1399 skb = rx_buf->skb;
1400 pci_dma_sync_single_for_cpu(bp->pdev,
1401 pci_unmap_addr(rx_buf, mapping),
1402 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1403
1404 rx_hdr = (struct l2_fhdr *) skb->data;
1405 len = rx_hdr->l2_fhdr_pkt_len - 4;
1406
1407 if (rx_hdr->l2_fhdr_errors &
1408 (L2_FHDR_ERRORS_BAD_CRC |
1409 L2_FHDR_ERRORS_PHY_DECODE |
1410 L2_FHDR_ERRORS_ALIGNMENT |
1411 L2_FHDR_ERRORS_TOO_SHORT |
1412 L2_FHDR_ERRORS_GIANT_FRAME)) {
1413
1414 goto reuse_rx;
1415 }
1416
1417 /* Since we don't have a jumbo ring, copy small packets
1418 * if mtu > 1500
1419 */
1420 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
1421 struct sk_buff *new_skb;
1422
1423 new_skb = dev_alloc_skb(len + 2);
1424 if (new_skb == NULL)
1425 goto reuse_rx;
1426
1427 /* aligned copy */
1428 memcpy(new_skb->data,
1429 skb->data + bp->rx_offset - 2,
1430 len + 2);
1431
1432 skb_reserve(new_skb, 2);
1433 skb_put(new_skb, len);
1434 new_skb->dev = bp->dev;
1435
1436 bnx2_reuse_rx_skb(bp, skb,
1437 sw_ring_cons, sw_ring_prod);
1438
1439 skb = new_skb;
1440 }
1441 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
1442 pci_unmap_single(bp->pdev,
1443 pci_unmap_addr(rx_buf, mapping),
1444 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1445
1446 skb_reserve(skb, bp->rx_offset);
1447 skb_put(skb, len);
1448 }
1449 else {
1450reuse_rx:
1451 bnx2_reuse_rx_skb(bp, skb,
1452 sw_ring_cons, sw_ring_prod);
1453 goto next_rx;
1454 }
1455
1456 skb->protocol = eth_type_trans(skb, bp->dev);
1457
1458 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
1459 (htons(skb->protocol) != 0x8100)) {
1460
1461 dev_kfree_skb_irq(skb);
1462 goto next_rx;
1463
1464 }
1465
1466 status = rx_hdr->l2_fhdr_status;
1467 skb->ip_summed = CHECKSUM_NONE;
1468 if (bp->rx_csum &&
1469 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
1470 L2_FHDR_STATUS_UDP_DATAGRAM))) {
1471
1472 u16 cksum = rx_hdr->l2_fhdr_tcp_udp_xsum;
1473
1474 if (cksum == 0xffff)
1475 skb->ip_summed = CHECKSUM_UNNECESSARY;
1476 }
1477
1478#ifdef BCM_VLAN
1479 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
1480 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1481 rx_hdr->l2_fhdr_vlan_tag);
1482 }
1483 else
1484#endif
1485 netif_receive_skb(skb);
1486
1487 bp->dev->last_rx = jiffies;
1488 rx_pkt++;
1489
1490next_rx:
1491 rx_buf->skb = NULL;
1492
1493 sw_cons = NEXT_RX_BD(sw_cons);
1494 sw_prod = NEXT_RX_BD(sw_prod);
1495
1496 if ((rx_pkt == budget))
1497 break;
1498 }
1499 bp->rx_cons = sw_cons;
1500 bp->rx_prod = sw_prod;
1501
1502 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
1503
1504 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
1505
1506 mmiowb();
1507
1508 return rx_pkt;
1509
1510}
1511
1512/* MSI ISR - The only difference between this and the INTx ISR
1513 * is that the MSI interrupt is always serviced.
1514 */
1515static irqreturn_t
1516bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs)
1517{
1518 struct net_device *dev = dev_instance;
1519 struct bnx2 *bp = dev->priv;
1520
1521 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1522 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1523 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1524
1525 /* Return here if interrupt is disabled. */
1526 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1527 return IRQ_RETVAL(1);
1528 }
1529
1530 if (netif_rx_schedule_prep(dev)) {
1531 __netif_rx_schedule(dev);
1532 }
1533
1534 return IRQ_RETVAL(1);
1535}
1536
1537static irqreturn_t
1538bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1539{
1540 struct net_device *dev = dev_instance;
1541 struct bnx2 *bp = dev->priv;
1542
1543 /* When using INTx, it is possible for the interrupt to arrive
1544 * at the CPU before the status block posted prior to the
1545 * interrupt. Reading a register will flush the status block.
1546 * When using MSI, the MSI message will always complete after
1547 * the status block write.
1548 */
1549 if ((bp->status_blk->status_idx == bp->last_status_idx) ||
1550 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
1551 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
1552 return IRQ_RETVAL(0);
1553
1554 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1555 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1556 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1557
1558 /* Return here if interrupt is shared and is disabled. */
1559 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1560 return IRQ_RETVAL(1);
1561 }
1562
1563 if (netif_rx_schedule_prep(dev)) {
1564 __netif_rx_schedule(dev);
1565 }
1566
1567 return IRQ_RETVAL(1);
1568}
1569
1570static int
1571bnx2_poll(struct net_device *dev, int *budget)
1572{
1573 struct bnx2 *bp = dev->priv;
1574 int rx_done = 1;
1575
1576 bp->last_status_idx = bp->status_blk->status_idx;
1577
1578 rmb();
1579 if ((bp->status_blk->status_attn_bits &
1580 STATUS_ATTN_BITS_LINK_STATE) !=
1581 (bp->status_blk->status_attn_bits_ack &
1582 STATUS_ATTN_BITS_LINK_STATE)) {
1583
1584 unsigned long flags;
1585
1586 spin_lock_irqsave(&bp->phy_lock, flags);
1587 bnx2_phy_int(bp);
1588 spin_unlock_irqrestore(&bp->phy_lock, flags);
1589 }
1590
1591 if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_cons) {
1592 bnx2_tx_int(bp);
1593 }
1594
1595 if (bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) {
1596 int orig_budget = *budget;
1597 int work_done;
1598
1599 if (orig_budget > dev->quota)
1600 orig_budget = dev->quota;
1601
1602 work_done = bnx2_rx_int(bp, orig_budget);
1603 *budget -= work_done;
1604 dev->quota -= work_done;
1605
1606 if (work_done >= orig_budget) {
1607 rx_done = 0;
1608 }
1609 }
1610
1611 if (rx_done) {
1612 netif_rx_complete(dev);
1613 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1614 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1615 bp->last_status_idx);
1616 return 0;
1617 }
1618
1619 return 1;
1620}
1621
1622/* Called with rtnl_lock from vlan functions and also dev->xmit_lock
1623 * from set_multicast.
1624 */
1625static void
1626bnx2_set_rx_mode(struct net_device *dev)
1627{
1628 struct bnx2 *bp = dev->priv;
1629 u32 rx_mode, sort_mode;
1630 int i;
1631 unsigned long flags;
1632
1633 spin_lock_irqsave(&bp->phy_lock, flags);
1634
1635 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
1636 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
1637 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
1638#ifdef BCM_VLAN
1639 if (!bp->vlgrp) {
1640 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1641 }
1642#else
1643 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1644#endif
1645 if (dev->flags & IFF_PROMISC) {
1646 /* Promiscuous mode. */
1647 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
1648 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN;
1649 }
1650 else if (dev->flags & IFF_ALLMULTI) {
1651 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1652 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1653 0xffffffff);
1654 }
1655 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
1656 }
1657 else {
1658 /* Accept one or more multicast(s). */
1659 struct dev_mc_list *mclist;
1660 u32 mc_filter[NUM_MC_HASH_REGISTERS];
1661 u32 regidx;
1662 u32 bit;
1663 u32 crc;
1664
1665 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
1666
1667 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1668 i++, mclist = mclist->next) {
1669
1670 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1671 bit = crc & 0xff;
1672 regidx = (bit & 0xe0) >> 5;
1673 bit &= 0x1f;
1674 mc_filter[regidx] |= (1 << bit);
1675 }
1676
1677 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1678 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1679 mc_filter[i]);
1680 }
1681
1682 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
1683 }
1684
1685 if (rx_mode != bp->rx_mode) {
1686 bp->rx_mode = rx_mode;
1687 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
1688 }
1689
1690 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
1691 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
1692 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
1693
1694 spin_unlock_irqrestore(&bp->phy_lock, flags);
1695}
1696
1697static void
1698load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
1699 u32 rv2p_proc)
1700{
1701 int i;
1702 u32 val;
1703
1704
1705 for (i = 0; i < rv2p_code_len; i += 8) {
1706 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code);
1707 rv2p_code++;
1708 REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code);
1709 rv2p_code++;
1710
1711 if (rv2p_proc == RV2P_PROC1) {
1712 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
1713 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
1714 }
1715 else {
1716 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
1717 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
1718 }
1719 }
1720
1721 /* Reset the processor, un-stall is done later. */
1722 if (rv2p_proc == RV2P_PROC1) {
1723 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
1724 }
1725 else {
1726 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
1727 }
1728}
1729
1730static void
1731load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
1732{
1733 u32 offset;
1734 u32 val;
1735
1736 /* Halt the CPU. */
1737 val = REG_RD_IND(bp, cpu_reg->mode);
1738 val |= cpu_reg->mode_value_halt;
1739 REG_WR_IND(bp, cpu_reg->mode, val);
1740 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1741
1742 /* Load the Text area. */
1743 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
1744 if (fw->text) {
1745 int j;
1746
1747 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
1748 REG_WR_IND(bp, offset, fw->text[j]);
1749 }
1750 }
1751
1752 /* Load the Data area. */
1753 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
1754 if (fw->data) {
1755 int j;
1756
1757 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
1758 REG_WR_IND(bp, offset, fw->data[j]);
1759 }
1760 }
1761
1762 /* Load the SBSS area. */
1763 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
1764 if (fw->sbss) {
1765 int j;
1766
1767 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
1768 REG_WR_IND(bp, offset, fw->sbss[j]);
1769 }
1770 }
1771
1772 /* Load the BSS area. */
1773 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
1774 if (fw->bss) {
1775 int j;
1776
1777 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
1778 REG_WR_IND(bp, offset, fw->bss[j]);
1779 }
1780 }
1781
1782 /* Load the Read-Only area. */
1783 offset = cpu_reg->spad_base +
1784 (fw->rodata_addr - cpu_reg->mips_view_base);
1785 if (fw->rodata) {
1786 int j;
1787
1788 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
1789 REG_WR_IND(bp, offset, fw->rodata[j]);
1790 }
1791 }
1792
1793 /* Clear the pre-fetch instruction. */
1794 REG_WR_IND(bp, cpu_reg->inst, 0);
1795 REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
1796
1797 /* Start the CPU. */
1798 val = REG_RD_IND(bp, cpu_reg->mode);
1799 val &= ~cpu_reg->mode_value_halt;
1800 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1801 REG_WR_IND(bp, cpu_reg->mode, val);
1802}
1803
1804static void
1805bnx2_init_cpus(struct bnx2 *bp)
1806{
1807 struct cpu_reg cpu_reg;
1808 struct fw_info fw;
1809
1810 /* Initialize the RV2P processor. */
1811 load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1);
1812 load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2);
1813
1814 /* Initialize the RX Processor. */
1815 cpu_reg.mode = BNX2_RXP_CPU_MODE;
1816 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
1817 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
1818 cpu_reg.state = BNX2_RXP_CPU_STATE;
1819 cpu_reg.state_value_clear = 0xffffff;
1820 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
1821 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
1822 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
1823 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
1824 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
1825 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
1826 cpu_reg.mips_view_base = 0x8000000;
1827
1828 fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
1829 fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
1830 fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
1831 fw.start_addr = bnx2_RXP_b06FwStartAddr;
1832
1833 fw.text_addr = bnx2_RXP_b06FwTextAddr;
1834 fw.text_len = bnx2_RXP_b06FwTextLen;
1835 fw.text_index = 0;
1836 fw.text = bnx2_RXP_b06FwText;
1837
1838 fw.data_addr = bnx2_RXP_b06FwDataAddr;
1839 fw.data_len = bnx2_RXP_b06FwDataLen;
1840 fw.data_index = 0;
1841 fw.data = bnx2_RXP_b06FwData;
1842
1843 fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
1844 fw.sbss_len = bnx2_RXP_b06FwSbssLen;
1845 fw.sbss_index = 0;
1846 fw.sbss = bnx2_RXP_b06FwSbss;
1847
1848 fw.bss_addr = bnx2_RXP_b06FwBssAddr;
1849 fw.bss_len = bnx2_RXP_b06FwBssLen;
1850 fw.bss_index = 0;
1851 fw.bss = bnx2_RXP_b06FwBss;
1852
1853 fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
1854 fw.rodata_len = bnx2_RXP_b06FwRodataLen;
1855 fw.rodata_index = 0;
1856 fw.rodata = bnx2_RXP_b06FwRodata;
1857
1858 load_cpu_fw(bp, &cpu_reg, &fw);
1859
1860 /* Initialize the TX Processor. */
1861 cpu_reg.mode = BNX2_TXP_CPU_MODE;
1862 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
1863 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
1864 cpu_reg.state = BNX2_TXP_CPU_STATE;
1865 cpu_reg.state_value_clear = 0xffffff;
1866 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
1867 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
1868 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
1869 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
1870 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
1871 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
1872 cpu_reg.mips_view_base = 0x8000000;
1873
1874 fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
1875 fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
1876 fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
1877 fw.start_addr = bnx2_TXP_b06FwStartAddr;
1878
1879 fw.text_addr = bnx2_TXP_b06FwTextAddr;
1880 fw.text_len = bnx2_TXP_b06FwTextLen;
1881 fw.text_index = 0;
1882 fw.text = bnx2_TXP_b06FwText;
1883
1884 fw.data_addr = bnx2_TXP_b06FwDataAddr;
1885 fw.data_len = bnx2_TXP_b06FwDataLen;
1886 fw.data_index = 0;
1887 fw.data = bnx2_TXP_b06FwData;
1888
1889 fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
1890 fw.sbss_len = bnx2_TXP_b06FwSbssLen;
1891 fw.sbss_index = 0;
1892 fw.sbss = bnx2_TXP_b06FwSbss;
1893
1894 fw.bss_addr = bnx2_TXP_b06FwBssAddr;
1895 fw.bss_len = bnx2_TXP_b06FwBssLen;
1896 fw.bss_index = 0;
1897 fw.bss = bnx2_TXP_b06FwBss;
1898
1899 fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
1900 fw.rodata_len = bnx2_TXP_b06FwRodataLen;
1901 fw.rodata_index = 0;
1902 fw.rodata = bnx2_TXP_b06FwRodata;
1903
1904 load_cpu_fw(bp, &cpu_reg, &fw);
1905
1906 /* Initialize the TX Patch-up Processor. */
1907 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
1908 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
1909 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
1910 cpu_reg.state = BNX2_TPAT_CPU_STATE;
1911 cpu_reg.state_value_clear = 0xffffff;
1912 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
1913 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
1914 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
1915 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
1916 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
1917 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
1918 cpu_reg.mips_view_base = 0x8000000;
1919
1920 fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
1921 fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
1922 fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
1923 fw.start_addr = bnx2_TPAT_b06FwStartAddr;
1924
1925 fw.text_addr = bnx2_TPAT_b06FwTextAddr;
1926 fw.text_len = bnx2_TPAT_b06FwTextLen;
1927 fw.text_index = 0;
1928 fw.text = bnx2_TPAT_b06FwText;
1929
1930 fw.data_addr = bnx2_TPAT_b06FwDataAddr;
1931 fw.data_len = bnx2_TPAT_b06FwDataLen;
1932 fw.data_index = 0;
1933 fw.data = bnx2_TPAT_b06FwData;
1934
1935 fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
1936 fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
1937 fw.sbss_index = 0;
1938 fw.sbss = bnx2_TPAT_b06FwSbss;
1939
1940 fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
1941 fw.bss_len = bnx2_TPAT_b06FwBssLen;
1942 fw.bss_index = 0;
1943 fw.bss = bnx2_TPAT_b06FwBss;
1944
1945 fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
1946 fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
1947 fw.rodata_index = 0;
1948 fw.rodata = bnx2_TPAT_b06FwRodata;
1949
1950 load_cpu_fw(bp, &cpu_reg, &fw);
1951
1952 /* Initialize the Completion Processor. */
1953 cpu_reg.mode = BNX2_COM_CPU_MODE;
1954 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
1955 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
1956 cpu_reg.state = BNX2_COM_CPU_STATE;
1957 cpu_reg.state_value_clear = 0xffffff;
1958 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
1959 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
1960 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
1961 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
1962 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
1963 cpu_reg.spad_base = BNX2_COM_SCRATCH;
1964 cpu_reg.mips_view_base = 0x8000000;
1965
1966 fw.ver_major = bnx2_COM_b06FwReleaseMajor;
1967 fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
1968 fw.ver_fix = bnx2_COM_b06FwReleaseFix;
1969 fw.start_addr = bnx2_COM_b06FwStartAddr;
1970
1971 fw.text_addr = bnx2_COM_b06FwTextAddr;
1972 fw.text_len = bnx2_COM_b06FwTextLen;
1973 fw.text_index = 0;
1974 fw.text = bnx2_COM_b06FwText;
1975
1976 fw.data_addr = bnx2_COM_b06FwDataAddr;
1977 fw.data_len = bnx2_COM_b06FwDataLen;
1978 fw.data_index = 0;
1979 fw.data = bnx2_COM_b06FwData;
1980
1981 fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
1982 fw.sbss_len = bnx2_COM_b06FwSbssLen;
1983 fw.sbss_index = 0;
1984 fw.sbss = bnx2_COM_b06FwSbss;
1985
1986 fw.bss_addr = bnx2_COM_b06FwBssAddr;
1987 fw.bss_len = bnx2_COM_b06FwBssLen;
1988 fw.bss_index = 0;
1989 fw.bss = bnx2_COM_b06FwBss;
1990
1991 fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
1992 fw.rodata_len = bnx2_COM_b06FwRodataLen;
1993 fw.rodata_index = 0;
1994 fw.rodata = bnx2_COM_b06FwRodata;
1995
1996 load_cpu_fw(bp, &cpu_reg, &fw);
1997
1998}
1999
2000static int
2001bnx2_set_power_state(struct bnx2 *bp, int state)
2002{
2003 u16 pmcsr;
2004
2005 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
2006
2007 switch (state) {
2008 case 0: {
2009 u32 val;
2010
2011 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2012 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
2013 PCI_PM_CTRL_PME_STATUS);
2014
2015 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
2016 /* delay required during transition out of D3hot */
2017 msleep(20);
2018
2019 val = REG_RD(bp, BNX2_EMAC_MODE);
2020 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
2021 val &= ~BNX2_EMAC_MODE_MPKT;
2022 REG_WR(bp, BNX2_EMAC_MODE, val);
2023
2024 val = REG_RD(bp, BNX2_RPM_CONFIG);
2025 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2026 REG_WR(bp, BNX2_RPM_CONFIG, val);
2027 break;
2028 }
2029 case 3: {
2030 int i;
2031 u32 val, wol_msg;
2032
2033 if (bp->wol) {
2034 u32 advertising;
2035 u8 autoneg;
2036
2037 autoneg = bp->autoneg;
2038 advertising = bp->advertising;
2039
2040 bp->autoneg = AUTONEG_SPEED;
2041 bp->advertising = ADVERTISED_10baseT_Half |
2042 ADVERTISED_10baseT_Full |
2043 ADVERTISED_100baseT_Half |
2044 ADVERTISED_100baseT_Full |
2045 ADVERTISED_Autoneg;
2046
2047 bnx2_setup_copper_phy(bp);
2048
2049 bp->autoneg = autoneg;
2050 bp->advertising = advertising;
2051
2052 bnx2_set_mac_addr(bp);
2053
2054 val = REG_RD(bp, BNX2_EMAC_MODE);
2055
2056 /* Enable port mode. */
2057 val &= ~BNX2_EMAC_MODE_PORT;
2058 val |= BNX2_EMAC_MODE_PORT_MII |
2059 BNX2_EMAC_MODE_MPKT_RCVD |
2060 BNX2_EMAC_MODE_ACPI_RCVD |
2061 BNX2_EMAC_MODE_FORCE_LINK |
2062 BNX2_EMAC_MODE_MPKT;
2063
2064 REG_WR(bp, BNX2_EMAC_MODE, val);
2065
2066 /* receive all multicast */
2067 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2068 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2069 0xffffffff);
2070 }
2071 REG_WR(bp, BNX2_EMAC_RX_MODE,
2072 BNX2_EMAC_RX_MODE_SORT_MODE);
2073
2074 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
2075 BNX2_RPM_SORT_USER0_MC_EN;
2076 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2077 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
2078 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
2079 BNX2_RPM_SORT_USER0_ENA);
2080
2081 /* Need to enable EMAC and RPM for WOL. */
2082 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2083 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
2084 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
2085 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
2086
2087 val = REG_RD(bp, BNX2_RPM_CONFIG);
2088 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2089 REG_WR(bp, BNX2_RPM_CONFIG, val);
2090
2091 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
2092 }
2093 else {
2094 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
2095 }
2096
2097 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg);
2098
2099 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2100 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2101 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
2102
2103 if (bp->wol)
2104 pmcsr |= 3;
2105 }
2106 else {
2107 pmcsr |= 3;
2108 }
2109 if (bp->wol) {
2110 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2111 }
2112 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2113 pmcsr);
2114
2115 /* No more memory access after this point until
2116 * device is brought back to D0.
2117 */
2118 udelay(50);
2119 break;
2120 }
2121 default:
2122 return -EINVAL;
2123 }
2124 return 0;
2125}
2126
2127static int
2128bnx2_acquire_nvram_lock(struct bnx2 *bp)
2129{
2130 u32 val;
2131 int j;
2132
2133 /* Request access to the flash interface. */
2134 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
2135 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2136 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2137 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
2138 break;
2139
2140 udelay(5);
2141 }
2142
2143 if (j >= NVRAM_TIMEOUT_COUNT)
2144 return -EBUSY;
2145
2146 return 0;
2147}
2148
2149static int
2150bnx2_release_nvram_lock(struct bnx2 *bp)
2151{
2152 int j;
2153 u32 val;
2154
2155 /* Relinquish nvram interface. */
2156 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
2157
2158 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2159 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2160 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
2161 break;
2162
2163 udelay(5);
2164 }
2165
2166 if (j >= NVRAM_TIMEOUT_COUNT)
2167 return -EBUSY;
2168
2169 return 0;
2170}
2171
2172
2173static int
2174bnx2_enable_nvram_write(struct bnx2 *bp)
2175{
2176 u32 val;
2177
2178 val = REG_RD(bp, BNX2_MISC_CFG);
2179 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
2180
2181 if (!bp->flash_info->buffered) {
2182 int j;
2183
2184 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2185 REG_WR(bp, BNX2_NVM_COMMAND,
2186 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
2187
2188 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2189 udelay(5);
2190
2191 val = REG_RD(bp, BNX2_NVM_COMMAND);
2192 if (val & BNX2_NVM_COMMAND_DONE)
2193 break;
2194 }
2195
2196 if (j >= NVRAM_TIMEOUT_COUNT)
2197 return -EBUSY;
2198 }
2199 return 0;
2200}
2201
2202static void
2203bnx2_disable_nvram_write(struct bnx2 *bp)
2204{
2205 u32 val;
2206
2207 val = REG_RD(bp, BNX2_MISC_CFG);
2208 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
2209}
2210
2211
2212static void
2213bnx2_enable_nvram_access(struct bnx2 *bp)
2214{
2215 u32 val;
2216
2217 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2218 /* Enable both bits, even on read. */
2219 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2220 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
2221}
2222
2223static void
2224bnx2_disable_nvram_access(struct bnx2 *bp)
2225{
2226 u32 val;
2227
2228 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2229 /* Disable both bits, even after read. */
2230 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2231 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
2232 BNX2_NVM_ACCESS_ENABLE_WR_EN));
2233}
2234
2235static int
2236bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
2237{
2238 u32 cmd;
2239 int j;
2240
2241 if (bp->flash_info->buffered)
2242 /* Buffered flash, no erase needed */
2243 return 0;
2244
2245 /* Build an erase command */
2246 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
2247 BNX2_NVM_COMMAND_DOIT;
2248
2249 /* Need to clear DONE bit separately. */
2250 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2251
2252 /* Address of the NVRAM to read from. */
2253 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2254
2255 /* Issue an erase command. */
2256 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2257
2258 /* Wait for completion. */
2259 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2260 u32 val;
2261
2262 udelay(5);
2263
2264 val = REG_RD(bp, BNX2_NVM_COMMAND);
2265 if (val & BNX2_NVM_COMMAND_DONE)
2266 break;
2267 }
2268
2269 if (j >= NVRAM_TIMEOUT_COUNT)
2270 return -EBUSY;
2271
2272 return 0;
2273}
2274
2275static int
2276bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
2277{
2278 u32 cmd;
2279 int j;
2280
2281 /* Build the command word. */
2282 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
2283
2284 /* Calculate an offset of a buffered flash. */
2285 if (bp->flash_info->buffered) {
2286 offset = ((offset / bp->flash_info->page_size) <<
2287 bp->flash_info->page_bits) +
2288 (offset % bp->flash_info->page_size);
2289 }
2290
2291 /* Need to clear DONE bit separately. */
2292 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2293
2294 /* Address of the NVRAM to read from. */
2295 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2296
2297 /* Issue a read command. */
2298 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2299
2300 /* Wait for completion. */
2301 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2302 u32 val;
2303
2304 udelay(5);
2305
2306 val = REG_RD(bp, BNX2_NVM_COMMAND);
2307 if (val & BNX2_NVM_COMMAND_DONE) {
2308 val = REG_RD(bp, BNX2_NVM_READ);
2309
2310 val = be32_to_cpu(val);
2311 memcpy(ret_val, &val, 4);
2312 break;
2313 }
2314 }
2315 if (j >= NVRAM_TIMEOUT_COUNT)
2316 return -EBUSY;
2317
2318 return 0;
2319}
2320
2321
2322static int
2323bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
2324{
2325 u32 cmd, val32;
2326 int j;
2327
2328 /* Build the command word. */
2329 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
2330
2331 /* Calculate an offset of a buffered flash. */
2332 if (bp->flash_info->buffered) {
2333 offset = ((offset / bp->flash_info->page_size) <<
2334 bp->flash_info->page_bits) +
2335 (offset % bp->flash_info->page_size);
2336 }
2337
2338 /* Need to clear DONE bit separately. */
2339 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2340
2341 memcpy(&val32, val, 4);
2342 val32 = cpu_to_be32(val32);
2343
2344 /* Write the data. */
2345 REG_WR(bp, BNX2_NVM_WRITE, val32);
2346
2347 /* Address of the NVRAM to write to. */
2348 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2349
2350 /* Issue the write command. */
2351 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2352
2353 /* Wait for completion. */
2354 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2355 udelay(5);
2356
2357 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
2358 break;
2359 }
2360 if (j >= NVRAM_TIMEOUT_COUNT)
2361 return -EBUSY;
2362
2363 return 0;
2364}
2365
2366static int
2367bnx2_init_nvram(struct bnx2 *bp)
2368{
2369 u32 val;
2370 int j, entry_count, rc;
2371 struct flash_spec *flash;
2372
2373 /* Determine the selected interface. */
2374 val = REG_RD(bp, BNX2_NVM_CFG1);
2375
2376 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2377
2378 rc = 0;
2379 if (val & 0x40000000) {
2380
2381 /* Flash interface has been reconfigured */
2382 for (j = 0, flash = &flash_table[0]; j < entry_count;
2383 j++, flash++) {
2384
2385 if (val == flash->config1) {
2386 bp->flash_info = flash;
2387 break;
2388 }
2389 }
2390 }
2391 else {
2392 /* Not yet been reconfigured */
2393
2394 for (j = 0, flash = &flash_table[0]; j < entry_count;
2395 j++, flash++) {
2396
2397 if ((val & FLASH_STRAP_MASK) == flash->strapping) {
2398 bp->flash_info = flash;
2399
2400 /* Request access to the flash interface. */
2401 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2402 return rc;
2403
2404 /* Enable access to flash interface */
2405 bnx2_enable_nvram_access(bp);
2406
2407 /* Reconfigure the flash interface */
2408 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
2409 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
2410 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
2411 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
2412
2413 /* Disable access to flash interface */
2414 bnx2_disable_nvram_access(bp);
2415 bnx2_release_nvram_lock(bp);
2416
2417 break;
2418 }
2419 }
2420 } /* if (val & 0x40000000) */
2421
2422 if (j == entry_count) {
2423 bp->flash_info = NULL;
2424 printk(KERN_ALERT "Unknown flash/EEPROM type.\n");
2425 rc = -ENODEV;
2426 }
2427
2428 return rc;
2429}
2430
2431static int
2432bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
2433 int buf_size)
2434{
2435 int rc = 0;
2436 u32 cmd_flags, offset32, len32, extra;
2437
2438 if (buf_size == 0)
2439 return 0;
2440
2441 /* Request access to the flash interface. */
2442 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2443 return rc;
2444
2445 /* Enable access to flash interface */
2446 bnx2_enable_nvram_access(bp);
2447
2448 len32 = buf_size;
2449 offset32 = offset;
2450 extra = 0;
2451
2452 cmd_flags = 0;
2453
2454 if (offset32 & 3) {
2455 u8 buf[4];
2456 u32 pre_len;
2457
2458 offset32 &= ~3;
2459 pre_len = 4 - (offset & 3);
2460
2461 if (pre_len >= len32) {
2462 pre_len = len32;
2463 cmd_flags = BNX2_NVM_COMMAND_FIRST |
2464 BNX2_NVM_COMMAND_LAST;
2465 }
2466 else {
2467 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2468 }
2469
2470 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2471
2472 if (rc)
2473 return rc;
2474
2475 memcpy(ret_buf, buf + (offset & 3), pre_len);
2476
2477 offset32 += 4;
2478 ret_buf += pre_len;
2479 len32 -= pre_len;
2480 }
2481 if (len32 & 3) {
2482 extra = 4 - (len32 & 3);
2483 len32 = (len32 + 4) & ~3;
2484 }
2485
2486 if (len32 == 4) {
2487 u8 buf[4];
2488
2489 if (cmd_flags)
2490 cmd_flags = BNX2_NVM_COMMAND_LAST;
2491 else
2492 cmd_flags = BNX2_NVM_COMMAND_FIRST |
2493 BNX2_NVM_COMMAND_LAST;
2494
2495 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2496
2497 memcpy(ret_buf, buf, 4 - extra);
2498 }
2499 else if (len32 > 0) {
2500 u8 buf[4];
2501
2502 /* Read the first word. */
2503 if (cmd_flags)
2504 cmd_flags = 0;
2505 else
2506 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2507
2508 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
2509
2510 /* Advance to the next dword. */
2511 offset32 += 4;
2512 ret_buf += 4;
2513 len32 -= 4;
2514
2515 while (len32 > 4 && rc == 0) {
2516 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
2517
2518 /* Advance to the next dword. */
2519 offset32 += 4;
2520 ret_buf += 4;
2521 len32 -= 4;
2522 }
2523
2524 if (rc)
2525 return rc;
2526
2527 cmd_flags = BNX2_NVM_COMMAND_LAST;
2528 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2529
2530 memcpy(ret_buf, buf, 4 - extra);
2531 }
2532
2533 /* Disable access to flash interface */
2534 bnx2_disable_nvram_access(bp);
2535
2536 bnx2_release_nvram_lock(bp);
2537
2538 return rc;
2539}
2540
2541static int
2542bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
2543 int buf_size)
2544{
2545 u32 written, offset32, len32;
2546 u8 *buf, start[4], end[4];
2547 int rc = 0;
2548 int align_start, align_end;
2549
2550 buf = data_buf;
2551 offset32 = offset;
2552 len32 = buf_size;
2553 align_start = align_end = 0;
2554
2555 if ((align_start = (offset32 & 3))) {
2556 offset32 &= ~3;
2557 len32 += align_start;
2558 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
2559 return rc;
2560 }
2561
2562 if (len32 & 3) {
2563 if ((len32 > 4) || !align_start) {
2564 align_end = 4 - (len32 & 3);
2565 len32 += align_end;
2566 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4,
2567 end, 4))) {
2568 return rc;
2569 }
2570 }
2571 }
2572
2573 if (align_start || align_end) {
2574 buf = kmalloc(len32, GFP_KERNEL);
2575 if (buf == 0)
2576 return -ENOMEM;
2577 if (align_start) {
2578 memcpy(buf, start, 4);
2579 }
2580 if (align_end) {
2581 memcpy(buf + len32 - 4, end, 4);
2582 }
2583 memcpy(buf + align_start, data_buf, buf_size);
2584 }
2585
2586 written = 0;
2587 while ((written < len32) && (rc == 0)) {
2588 u32 page_start, page_end, data_start, data_end;
2589 u32 addr, cmd_flags;
2590 int i;
2591 u8 flash_buffer[264];
2592
2593 /* Find the page_start addr */
2594 page_start = offset32 + written;
2595 page_start -= (page_start % bp->flash_info->page_size);
2596 /* Find the page_end addr */
2597 page_end = page_start + bp->flash_info->page_size;
2598 /* Find the data_start addr */
2599 data_start = (written == 0) ? offset32 : page_start;
2600 /* Find the data_end addr */
2601 data_end = (page_end > offset32 + len32) ?
2602 (offset32 + len32) : page_end;
2603
2604 /* Request access to the flash interface. */
2605 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2606 goto nvram_write_end;
2607
2608 /* Enable access to flash interface */
2609 bnx2_enable_nvram_access(bp);
2610
2611 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2612 if (bp->flash_info->buffered == 0) {
2613 int j;
2614
2615 /* Read the whole page into the buffer
2616 * (non-buffer flash only) */
2617 for (j = 0; j < bp->flash_info->page_size; j += 4) {
2618 if (j == (bp->flash_info->page_size - 4)) {
2619 cmd_flags |= BNX2_NVM_COMMAND_LAST;
2620 }
2621 rc = bnx2_nvram_read_dword(bp,
2622 page_start + j,
2623 &flash_buffer[j],
2624 cmd_flags);
2625
2626 if (rc)
2627 goto nvram_write_end;
2628
2629 cmd_flags = 0;
2630 }
2631 }
2632
2633 /* Enable writes to flash interface (unlock write-protect) */
2634 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
2635 goto nvram_write_end;
2636
2637 /* Erase the page */
2638 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
2639 goto nvram_write_end;
2640
2641 /* Re-enable the write again for the actual write */
2642 bnx2_enable_nvram_write(bp);
2643
2644 /* Loop to write back the buffer data from page_start to
2645 * data_start */
2646 i = 0;
2647 if (bp->flash_info->buffered == 0) {
2648 for (addr = page_start; addr < data_start;
2649 addr += 4, i += 4) {
2650
2651 rc = bnx2_nvram_write_dword(bp, addr,
2652 &flash_buffer[i], cmd_flags);
2653
2654 if (rc != 0)
2655 goto nvram_write_end;
2656
2657 cmd_flags = 0;
2658 }
2659 }
2660
2661 /* Loop to write the new data from data_start to data_end */
2662 for (addr = data_start; addr < data_end; addr += 4, i++) {
2663 if ((addr == page_end - 4) ||
2664 ((bp->flash_info->buffered) &&
2665 (addr == data_end - 4))) {
2666
2667 cmd_flags |= BNX2_NVM_COMMAND_LAST;
2668 }
2669 rc = bnx2_nvram_write_dword(bp, addr, buf,
2670 cmd_flags);
2671
2672 if (rc != 0)
2673 goto nvram_write_end;
2674
2675 cmd_flags = 0;
2676 buf += 4;
2677 }
2678
2679 /* Loop to write back the buffer data from data_end
2680 * to page_end */
2681 if (bp->flash_info->buffered == 0) {
2682 for (addr = data_end; addr < page_end;
2683 addr += 4, i += 4) {
2684
2685 if (addr == page_end-4) {
2686 cmd_flags = BNX2_NVM_COMMAND_LAST;
2687 }
2688 rc = bnx2_nvram_write_dword(bp, addr,
2689 &flash_buffer[i], cmd_flags);
2690
2691 if (rc != 0)
2692 goto nvram_write_end;
2693
2694 cmd_flags = 0;
2695 }
2696 }
2697
2698 /* Disable writes to flash interface (lock write-protect) */
2699 bnx2_disable_nvram_write(bp);
2700
2701 /* Disable access to flash interface */
2702 bnx2_disable_nvram_access(bp);
2703 bnx2_release_nvram_lock(bp);
2704
2705 /* Increment written */
2706 written += data_end - data_start;
2707 }
2708
2709nvram_write_end:
2710 if (align_start || align_end)
2711 kfree(buf);
2712 return rc;
2713}
2714
2715static int
2716bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
2717{
2718 u32 val;
2719 int i, rc = 0;
2720
2721 /* Wait for the current PCI transaction to complete before
2722 * issuing a reset. */
2723 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
2724 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
2725 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
2726 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
2727 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
2728 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
2729 udelay(5);
2730
2731 /* Deposit a driver reset signature so the firmware knows that
2732 * this is a soft reset. */
2733 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_RESET_SIGNATURE,
2734 BNX2_DRV_RESET_SIGNATURE_MAGIC);
2735
2736 bp->fw_timed_out = 0;
2737
2738 /* Wait for the firmware to tell us it is ok to issue a reset. */
2739 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code);
2740
2741 /* Do a dummy read to force the chip to complete all current transaction
2742 * before we issue a reset. */
2743 val = REG_RD(bp, BNX2_MISC_ID);
2744
2745 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2746 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
2747 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
2748
2749 /* Chip reset. */
2750 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
2751
2752 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2753 (CHIP_ID(bp) == CHIP_ID_5706_A1))
2754 msleep(15);
2755
2756 /* Reset takes approximate 30 usec */
2757 for (i = 0; i < 10; i++) {
2758 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
2759 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2760 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
2761 break;
2762 }
2763 udelay(10);
2764 }
2765
2766 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2767 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
2768 printk(KERN_ERR PFX "Chip reset did not complete\n");
2769 return -EBUSY;
2770 }
2771
2772 /* Make sure byte swapping is properly configured. */
2773 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
2774 if (val != 0x01020304) {
2775 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
2776 return -ENODEV;
2777 }
2778
2779 bp->fw_timed_out = 0;
2780
2781 /* Wait for the firmware to finish its initialization. */
2782 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code);
2783
2784 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2785 /* Adjust the voltage regular to two steps lower. The default
2786 * of this register is 0x0000000e. */
2787 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
2788
2789 /* Remove bad rbuf memory from the free pool. */
2790 rc = bnx2_alloc_bad_rbuf(bp);
2791 }
2792
2793 return rc;
2794}
2795
2796static int
2797bnx2_init_chip(struct bnx2 *bp)
2798{
2799 u32 val;
2800
2801 /* Make sure the interrupt is not active. */
2802 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2803
2804 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
2805 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
2806#ifdef __BIG_ENDIAN
2807 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
2808#endif
2809 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
2810 DMA_READ_CHANS << 12 |
2811 DMA_WRITE_CHANS << 16;
2812
2813 val |= (0x2 << 20) | (1 << 11);
2814
2815 if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz = 133))
2816 val |= (1 << 23);
2817
2818 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
2819 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
2820 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
2821
2822 REG_WR(bp, BNX2_DMA_CONFIG, val);
2823
2824 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2825 val = REG_RD(bp, BNX2_TDMA_CONFIG);
2826 val |= BNX2_TDMA_CONFIG_ONE_DMA;
2827 REG_WR(bp, BNX2_TDMA_CONFIG, val);
2828 }
2829
2830 if (bp->flags & PCIX_FLAG) {
2831 u16 val16;
2832
2833 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
2834 &val16);
2835 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
2836 val16 & ~PCI_X_CMD_ERO);
2837 }
2838
2839 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2840 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
2841 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
2842 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
2843
2844 /* Initialize context mapping and zero out the quick contexts. The
2845 * context block must have already been enabled. */
2846 bnx2_init_context(bp);
2847
2848 bnx2_init_cpus(bp);
2849 bnx2_init_nvram(bp);
2850
2851 bnx2_set_mac_addr(bp);
2852
2853 val = REG_RD(bp, BNX2_MQ_CONFIG);
2854 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
2855 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
2856 REG_WR(bp, BNX2_MQ_CONFIG, val);
2857
2858 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
2859 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
2860 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
2861
2862 val = (BCM_PAGE_BITS - 8) << 24;
2863 REG_WR(bp, BNX2_RV2P_CONFIG, val);
2864
2865 /* Configure page size. */
2866 val = REG_RD(bp, BNX2_TBDR_CONFIG);
2867 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
2868 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
2869 REG_WR(bp, BNX2_TBDR_CONFIG, val);
2870
2871 val = bp->mac_addr[0] +
2872 (bp->mac_addr[1] << 8) +
2873 (bp->mac_addr[2] << 16) +
2874 bp->mac_addr[3] +
2875 (bp->mac_addr[4] << 8) +
2876 (bp->mac_addr[5] << 16);
2877 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
2878
2879 /* Program the MTU. Also include 4 bytes for CRC32. */
2880 val = bp->dev->mtu + ETH_HLEN + 4;
2881 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
2882 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
2883 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
2884
2885 bp->last_status_idx = 0;
2886 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
2887
2888 /* Set up how to generate a link change interrupt. */
2889 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2890
2891 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
2892 (u64) bp->status_blk_mapping & 0xffffffff);
2893 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
2894
2895 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
2896 (u64) bp->stats_blk_mapping & 0xffffffff);
2897 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
2898 (u64) bp->stats_blk_mapping >> 32);
2899
2900 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
2901 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
2902
2903 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
2904 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
2905
2906 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
2907 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
2908
2909 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
2910
2911 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
2912
2913 REG_WR(bp, BNX2_HC_COM_TICKS,
2914 (bp->com_ticks_int << 16) | bp->com_ticks);
2915
2916 REG_WR(bp, BNX2_HC_CMD_TICKS,
2917 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
2918
2919 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
2920 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
2921
2922 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
2923 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
2924 else {
2925 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
2926 BNX2_HC_CONFIG_TX_TMR_MODE |
2927 BNX2_HC_CONFIG_COLLECT_STATS);
2928 }
2929
2930 /* Clear internal stats counters. */
2931 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
2932
2933 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
2934
2935 /* Initialize the receive filter. */
2936 bnx2_set_rx_mode(bp->dev);
2937
2938 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET);
2939
2940 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
2941 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
2942
2943 udelay(20);
2944
2945 return 0;
2946}
2947
2948
2949static void
2950bnx2_init_tx_ring(struct bnx2 *bp)
2951{
2952 struct tx_bd *txbd;
2953 u32 val;
2954
2955 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
2956
2957 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
2958 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
2959
2960 bp->tx_prod = 0;
2961 bp->tx_cons = 0;
2962 bp->tx_prod_bseq = 0;
2963 atomic_set(&bp->tx_avail_bd, bp->tx_ring_size);
2964
2965 val = BNX2_L2CTX_TYPE_TYPE_L2;
2966 val |= BNX2_L2CTX_TYPE_SIZE_L2;
2967 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
2968
2969 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
2970 val |= 8 << 16;
2971 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
2972
2973 val = (u64) bp->tx_desc_mapping >> 32;
2974 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val);
2975
2976 val = (u64) bp->tx_desc_mapping & 0xffffffff;
2977 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
2978}
2979
2980static void
2981bnx2_init_rx_ring(struct bnx2 *bp)
2982{
2983 struct rx_bd *rxbd;
2984 int i;
2985 u16 prod, ring_prod;
2986 u32 val;
2987
2988 /* 8 for CRC and VLAN */
2989 bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
2990 /* 8 for alignment */
2991 bp->rx_buf_size = bp->rx_buf_use_size + 8;
2992
2993 ring_prod = prod = bp->rx_prod = 0;
2994 bp->rx_cons = 0;
2995 bp->rx_prod_bseq = 0;
2996
2997 rxbd = &bp->rx_desc_ring[0];
2998 for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
2999 rxbd->rx_bd_len = bp->rx_buf_use_size;
3000 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3001 }
3002
3003 rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32;
3004 rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
3005
3006 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3007 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
3008 val |= 0x02 << 8;
3009 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
3010
3011 val = (u64) bp->rx_desc_mapping >> 32;
3012 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
3013
3014 val = (u64) bp->rx_desc_mapping & 0xffffffff;
3015 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
3016
3017 for ( ;ring_prod < bp->rx_ring_size; ) {
3018 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
3019 break;
3020 }
3021 prod = NEXT_RX_BD(prod);
3022 ring_prod = RX_RING_IDX(prod);
3023 }
3024 bp->rx_prod = prod;
3025
3026 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
3027
3028 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
3029}
3030
3031static void
3032bnx2_free_tx_skbs(struct bnx2 *bp)
3033{
3034 int i;
3035
3036 if (bp->tx_buf_ring == NULL)
3037 return;
3038
3039 for (i = 0; i < TX_DESC_CNT; ) {
3040 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
3041 struct sk_buff *skb = tx_buf->skb;
3042 int j, last;
3043
3044 if (skb == NULL) {
3045 i++;
3046 continue;
3047 }
3048
3049 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
3050 skb_headlen(skb), PCI_DMA_TODEVICE);
3051
3052 tx_buf->skb = NULL;
3053
3054 last = skb_shinfo(skb)->nr_frags;
3055 for (j = 0; j < last; j++) {
3056 tx_buf = &bp->tx_buf_ring[i + j + 1];
3057 pci_unmap_page(bp->pdev,
3058 pci_unmap_addr(tx_buf, mapping),
3059 skb_shinfo(skb)->frags[j].size,
3060 PCI_DMA_TODEVICE);
3061 }
3062 dev_kfree_skb_any(skb);
3063 i += j + 1;
3064 }
3065
3066}
3067
3068static void
3069bnx2_free_rx_skbs(struct bnx2 *bp)
3070{
3071 int i;
3072
3073 if (bp->rx_buf_ring == NULL)
3074 return;
3075
3076 for (i = 0; i < RX_DESC_CNT; i++) {
3077 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
3078 struct sk_buff *skb = rx_buf->skb;
3079
3080 if (skb == 0)
3081 continue;
3082
3083 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
3084 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
3085
3086 rx_buf->skb = NULL;
3087
3088 dev_kfree_skb_any(skb);
3089 }
3090}
3091
3092static void
3093bnx2_free_skbs(struct bnx2 *bp)
3094{
3095 bnx2_free_tx_skbs(bp);
3096 bnx2_free_rx_skbs(bp);
3097}
3098
3099static int
3100bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
3101{
3102 int rc;
3103
3104 rc = bnx2_reset_chip(bp, reset_code);
3105 bnx2_free_skbs(bp);
3106 if (rc)
3107 return rc;
3108
3109 bnx2_init_chip(bp);
3110 bnx2_init_tx_ring(bp);
3111 bnx2_init_rx_ring(bp);
3112 return 0;
3113}
3114
3115static int
3116bnx2_init_nic(struct bnx2 *bp)
3117{
3118 int rc;
3119
3120 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
3121 return rc;
3122
3123 bnx2_init_phy(bp);
3124 bnx2_set_link(bp);
3125 return 0;
3126}
3127
3128static int
3129bnx2_test_registers(struct bnx2 *bp)
3130{
3131 int ret;
3132 int i;
3133 static struct {
3134 u16 offset;
3135 u16 flags;
3136 u32 rw_mask;
3137 u32 ro_mask;
3138 } reg_tbl[] = {
3139 { 0x006c, 0, 0x00000000, 0x0000003f },
3140 { 0x0090, 0, 0xffffffff, 0x00000000 },
3141 { 0x0094, 0, 0x00000000, 0x00000000 },
3142
3143 { 0x0404, 0, 0x00003f00, 0x00000000 },
3144 { 0x0418, 0, 0x00000000, 0xffffffff },
3145 { 0x041c, 0, 0x00000000, 0xffffffff },
3146 { 0x0420, 0, 0x00000000, 0x80ffffff },
3147 { 0x0424, 0, 0x00000000, 0x00000000 },
3148 { 0x0428, 0, 0x00000000, 0x00000001 },
3149 { 0x0450, 0, 0x00000000, 0x0000ffff },
3150 { 0x0454, 0, 0x00000000, 0xffffffff },
3151 { 0x0458, 0, 0x00000000, 0xffffffff },
3152
3153 { 0x0808, 0, 0x00000000, 0xffffffff },
3154 { 0x0854, 0, 0x00000000, 0xffffffff },
3155 { 0x0868, 0, 0x00000000, 0x77777777 },
3156 { 0x086c, 0, 0x00000000, 0x77777777 },
3157 { 0x0870, 0, 0x00000000, 0x77777777 },
3158 { 0x0874, 0, 0x00000000, 0x77777777 },
3159
3160 { 0x0c00, 0, 0x00000000, 0x00000001 },
3161 { 0x0c04, 0, 0x00000000, 0x03ff0001 },
3162 { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
3163 { 0x0c0c, 0, 0x00ffffff, 0x00000000 },
3164 { 0x0c30, 0, 0x00000000, 0xffffffff },
3165 { 0x0c34, 0, 0x00000000, 0xffffffff },
3166 { 0x0c38, 0, 0x00000000, 0xffffffff },
3167 { 0x0c3c, 0, 0x00000000, 0xffffffff },
3168 { 0x0c40, 0, 0x00000000, 0xffffffff },
3169 { 0x0c44, 0, 0x00000000, 0xffffffff },
3170 { 0x0c48, 0, 0x00000000, 0x0007ffff },
3171 { 0x0c4c, 0, 0x00000000, 0xffffffff },
3172 { 0x0c50, 0, 0x00000000, 0xffffffff },
3173 { 0x0c54, 0, 0x00000000, 0xffffffff },
3174 { 0x0c58, 0, 0x00000000, 0xffffffff },
3175 { 0x0c5c, 0, 0x00000000, 0xffffffff },
3176 { 0x0c60, 0, 0x00000000, 0xffffffff },
3177 { 0x0c64, 0, 0x00000000, 0xffffffff },
3178 { 0x0c68, 0, 0x00000000, 0xffffffff },
3179 { 0x0c6c, 0, 0x00000000, 0xffffffff },
3180 { 0x0c70, 0, 0x00000000, 0xffffffff },
3181 { 0x0c74, 0, 0x00000000, 0xffffffff },
3182 { 0x0c78, 0, 0x00000000, 0xffffffff },
3183 { 0x0c7c, 0, 0x00000000, 0xffffffff },
3184 { 0x0c80, 0, 0x00000000, 0xffffffff },
3185 { 0x0c84, 0, 0x00000000, 0xffffffff },
3186 { 0x0c88, 0, 0x00000000, 0xffffffff },
3187 { 0x0c8c, 0, 0x00000000, 0xffffffff },
3188 { 0x0c90, 0, 0x00000000, 0xffffffff },
3189 { 0x0c94, 0, 0x00000000, 0xffffffff },
3190 { 0x0c98, 0, 0x00000000, 0xffffffff },
3191 { 0x0c9c, 0, 0x00000000, 0xffffffff },
3192 { 0x0ca0, 0, 0x00000000, 0xffffffff },
3193 { 0x0ca4, 0, 0x00000000, 0xffffffff },
3194 { 0x0ca8, 0, 0x00000000, 0x0007ffff },
3195 { 0x0cac, 0, 0x00000000, 0xffffffff },
3196 { 0x0cb0, 0, 0x00000000, 0xffffffff },
3197 { 0x0cb4, 0, 0x00000000, 0xffffffff },
3198 { 0x0cb8, 0, 0x00000000, 0xffffffff },
3199 { 0x0cbc, 0, 0x00000000, 0xffffffff },
3200 { 0x0cc0, 0, 0x00000000, 0xffffffff },
3201 { 0x0cc4, 0, 0x00000000, 0xffffffff },
3202 { 0x0cc8, 0, 0x00000000, 0xffffffff },
3203 { 0x0ccc, 0, 0x00000000, 0xffffffff },
3204 { 0x0cd0, 0, 0x00000000, 0xffffffff },
3205 { 0x0cd4, 0, 0x00000000, 0xffffffff },
3206 { 0x0cd8, 0, 0x00000000, 0xffffffff },
3207 { 0x0cdc, 0, 0x00000000, 0xffffffff },
3208 { 0x0ce0, 0, 0x00000000, 0xffffffff },
3209 { 0x0ce4, 0, 0x00000000, 0xffffffff },
3210 { 0x0ce8, 0, 0x00000000, 0xffffffff },
3211 { 0x0cec, 0, 0x00000000, 0xffffffff },
3212 { 0x0cf0, 0, 0x00000000, 0xffffffff },
3213 { 0x0cf4, 0, 0x00000000, 0xffffffff },
3214 { 0x0cf8, 0, 0x00000000, 0xffffffff },
3215 { 0x0cfc, 0, 0x00000000, 0xffffffff },
3216 { 0x0d00, 0, 0x00000000, 0xffffffff },
3217 { 0x0d04, 0, 0x00000000, 0xffffffff },
3218
3219 { 0x1000, 0, 0x00000000, 0x00000001 },
3220 { 0x1004, 0, 0x00000000, 0x000f0001 },
3221 { 0x1044, 0, 0x00000000, 0xffc003ff },
3222 { 0x1080, 0, 0x00000000, 0x0001ffff },
3223 { 0x1084, 0, 0x00000000, 0xffffffff },
3224 { 0x1088, 0, 0x00000000, 0xffffffff },
3225 { 0x108c, 0, 0x00000000, 0xffffffff },
3226 { 0x1090, 0, 0x00000000, 0xffffffff },
3227 { 0x1094, 0, 0x00000000, 0xffffffff },
3228 { 0x1098, 0, 0x00000000, 0xffffffff },
3229 { 0x109c, 0, 0x00000000, 0xffffffff },
3230 { 0x10a0, 0, 0x00000000, 0xffffffff },
3231
3232 { 0x1408, 0, 0x01c00800, 0x00000000 },
3233 { 0x149c, 0, 0x8000ffff, 0x00000000 },
3234 { 0x14a8, 0, 0x00000000, 0x000001ff },
3235 { 0x14ac, 0, 0x4fffffff, 0x10000000 },
3236 { 0x14b0, 0, 0x00000002, 0x00000001 },
3237 { 0x14b8, 0, 0x00000000, 0x00000000 },
3238 { 0x14c0, 0, 0x00000000, 0x00000009 },
3239 { 0x14c4, 0, 0x00003fff, 0x00000000 },
3240 { 0x14cc, 0, 0x00000000, 0x00000001 },
3241 { 0x14d0, 0, 0xffffffff, 0x00000000 },
3242 { 0x1500, 0, 0x00000000, 0xffffffff },
3243 { 0x1504, 0, 0x00000000, 0xffffffff },
3244 { 0x1508, 0, 0x00000000, 0xffffffff },
3245 { 0x150c, 0, 0x00000000, 0xffffffff },
3246 { 0x1510, 0, 0x00000000, 0xffffffff },
3247 { 0x1514, 0, 0x00000000, 0xffffffff },
3248 { 0x1518, 0, 0x00000000, 0xffffffff },
3249 { 0x151c, 0, 0x00000000, 0xffffffff },
3250 { 0x1520, 0, 0x00000000, 0xffffffff },
3251 { 0x1524, 0, 0x00000000, 0xffffffff },
3252 { 0x1528, 0, 0x00000000, 0xffffffff },
3253 { 0x152c, 0, 0x00000000, 0xffffffff },
3254 { 0x1530, 0, 0x00000000, 0xffffffff },
3255 { 0x1534, 0, 0x00000000, 0xffffffff },
3256 { 0x1538, 0, 0x00000000, 0xffffffff },
3257 { 0x153c, 0, 0x00000000, 0xffffffff },
3258 { 0x1540, 0, 0x00000000, 0xffffffff },
3259 { 0x1544, 0, 0x00000000, 0xffffffff },
3260 { 0x1548, 0, 0x00000000, 0xffffffff },
3261 { 0x154c, 0, 0x00000000, 0xffffffff },
3262 { 0x1550, 0, 0x00000000, 0xffffffff },
3263 { 0x1554, 0, 0x00000000, 0xffffffff },
3264 { 0x1558, 0, 0x00000000, 0xffffffff },
3265 { 0x1600, 0, 0x00000000, 0xffffffff },
3266 { 0x1604, 0, 0x00000000, 0xffffffff },
3267 { 0x1608, 0, 0x00000000, 0xffffffff },
3268 { 0x160c, 0, 0x00000000, 0xffffffff },
3269 { 0x1610, 0, 0x00000000, 0xffffffff },
3270 { 0x1614, 0, 0x00000000, 0xffffffff },
3271 { 0x1618, 0, 0x00000000, 0xffffffff },
3272 { 0x161c, 0, 0x00000000, 0xffffffff },
3273 { 0x1620, 0, 0x00000000, 0xffffffff },
3274 { 0x1624, 0, 0x00000000, 0xffffffff },
3275 { 0x1628, 0, 0x00000000, 0xffffffff },
3276 { 0x162c, 0, 0x00000000, 0xffffffff },
3277 { 0x1630, 0, 0x00000000, 0xffffffff },
3278 { 0x1634, 0, 0x00000000, 0xffffffff },
3279 { 0x1638, 0, 0x00000000, 0xffffffff },
3280 { 0x163c, 0, 0x00000000, 0xffffffff },
3281 { 0x1640, 0, 0x00000000, 0xffffffff },
3282 { 0x1644, 0, 0x00000000, 0xffffffff },
3283 { 0x1648, 0, 0x00000000, 0xffffffff },
3284 { 0x164c, 0, 0x00000000, 0xffffffff },
3285 { 0x1650, 0, 0x00000000, 0xffffffff },
3286 { 0x1654, 0, 0x00000000, 0xffffffff },
3287
3288 { 0x1800, 0, 0x00000000, 0x00000001 },
3289 { 0x1804, 0, 0x00000000, 0x00000003 },
3290 { 0x1840, 0, 0x00000000, 0xffffffff },
3291 { 0x1844, 0, 0x00000000, 0xffffffff },
3292 { 0x1848, 0, 0x00000000, 0xffffffff },
3293 { 0x184c, 0, 0x00000000, 0xffffffff },
3294 { 0x1850, 0, 0x00000000, 0xffffffff },
3295 { 0x1900, 0, 0x7ffbffff, 0x00000000 },
3296 { 0x1904, 0, 0xffffffff, 0x00000000 },
3297 { 0x190c, 0, 0xffffffff, 0x00000000 },
3298 { 0x1914, 0, 0xffffffff, 0x00000000 },
3299 { 0x191c, 0, 0xffffffff, 0x00000000 },
3300 { 0x1924, 0, 0xffffffff, 0x00000000 },
3301 { 0x192c, 0, 0xffffffff, 0x00000000 },
3302 { 0x1934, 0, 0xffffffff, 0x00000000 },
3303 { 0x193c, 0, 0xffffffff, 0x00000000 },
3304 { 0x1944, 0, 0xffffffff, 0x00000000 },
3305 { 0x194c, 0, 0xffffffff, 0x00000000 },
3306 { 0x1954, 0, 0xffffffff, 0x00000000 },
3307 { 0x195c, 0, 0xffffffff, 0x00000000 },
3308 { 0x1964, 0, 0xffffffff, 0x00000000 },
3309 { 0x196c, 0, 0xffffffff, 0x00000000 },
3310 { 0x1974, 0, 0xffffffff, 0x00000000 },
3311 { 0x197c, 0, 0xffffffff, 0x00000000 },
3312 { 0x1980, 0, 0x0700ffff, 0x00000000 },
3313
3314 { 0x1c00, 0, 0x00000000, 0x00000001 },
3315 { 0x1c04, 0, 0x00000000, 0x00000003 },
3316 { 0x1c08, 0, 0x0000000f, 0x00000000 },
3317 { 0x1c40, 0, 0x00000000, 0xffffffff },
3318 { 0x1c44, 0, 0x00000000, 0xffffffff },
3319 { 0x1c48, 0, 0x00000000, 0xffffffff },
3320 { 0x1c4c, 0, 0x00000000, 0xffffffff },
3321 { 0x1c50, 0, 0x00000000, 0xffffffff },
3322 { 0x1d00, 0, 0x7ffbffff, 0x00000000 },
3323 { 0x1d04, 0, 0xffffffff, 0x00000000 },
3324 { 0x1d0c, 0, 0xffffffff, 0x00000000 },
3325 { 0x1d14, 0, 0xffffffff, 0x00000000 },
3326 { 0x1d1c, 0, 0xffffffff, 0x00000000 },
3327 { 0x1d24, 0, 0xffffffff, 0x00000000 },
3328 { 0x1d2c, 0, 0xffffffff, 0x00000000 },
3329 { 0x1d34, 0, 0xffffffff, 0x00000000 },
3330 { 0x1d3c, 0, 0xffffffff, 0x00000000 },
3331 { 0x1d44, 0, 0xffffffff, 0x00000000 },
3332 { 0x1d4c, 0, 0xffffffff, 0x00000000 },
3333 { 0x1d54, 0, 0xffffffff, 0x00000000 },
3334 { 0x1d5c, 0, 0xffffffff, 0x00000000 },
3335 { 0x1d64, 0, 0xffffffff, 0x00000000 },
3336 { 0x1d6c, 0, 0xffffffff, 0x00000000 },
3337 { 0x1d74, 0, 0xffffffff, 0x00000000 },
3338 { 0x1d7c, 0, 0xffffffff, 0x00000000 },
3339 { 0x1d80, 0, 0x0700ffff, 0x00000000 },
3340
3341 { 0x2004, 0, 0x00000000, 0x0337000f },
3342 { 0x2008, 0, 0xffffffff, 0x00000000 },
3343 { 0x200c, 0, 0xffffffff, 0x00000000 },
3344 { 0x2010, 0, 0xffffffff, 0x00000000 },
3345 { 0x2014, 0, 0x801fff80, 0x00000000 },
3346 { 0x2018, 0, 0x000003ff, 0x00000000 },
3347
3348 { 0x2800, 0, 0x00000000, 0x00000001 },
3349 { 0x2804, 0, 0x00000000, 0x00003f01 },
3350 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
3351 { 0x2810, 0, 0xffff0000, 0x00000000 },
3352 { 0x2814, 0, 0xffff0000, 0x00000000 },
3353 { 0x2818, 0, 0xffff0000, 0x00000000 },
3354 { 0x281c, 0, 0xffff0000, 0x00000000 },
3355 { 0x2834, 0, 0xffffffff, 0x00000000 },
3356 { 0x2840, 0, 0x00000000, 0xffffffff },
3357 { 0x2844, 0, 0x00000000, 0xffffffff },
3358 { 0x2848, 0, 0xffffffff, 0x00000000 },
3359 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
3360
3361 { 0x2c00, 0, 0x00000000, 0x00000011 },
3362 { 0x2c04, 0, 0x00000000, 0x00030007 },
3363
3364 { 0x3000, 0, 0x00000000, 0x00000001 },
3365 { 0x3004, 0, 0x00000000, 0x007007ff },
3366 { 0x3008, 0, 0x00000003, 0x00000000 },
3367 { 0x300c, 0, 0xffffffff, 0x00000000 },
3368 { 0x3010, 0, 0xffffffff, 0x00000000 },
3369 { 0x3014, 0, 0xffffffff, 0x00000000 },
3370 { 0x3034, 0, 0xffffffff, 0x00000000 },
3371 { 0x3038, 0, 0xffffffff, 0x00000000 },
3372 { 0x3050, 0, 0x00000001, 0x00000000 },
3373
3374 { 0x3c00, 0, 0x00000000, 0x00000001 },
3375 { 0x3c04, 0, 0x00000000, 0x00070000 },
3376 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
3377 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
3378 { 0x3c10, 0, 0xffffffff, 0x00000000 },
3379 { 0x3c14, 0, 0x00000000, 0xffffffff },
3380 { 0x3c18, 0, 0x00000000, 0xffffffff },
3381 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
3382 { 0x3c20, 0, 0xffffff00, 0x00000000 },
3383 { 0x3c24, 0, 0xffffffff, 0x00000000 },
3384 { 0x3c28, 0, 0xffffffff, 0x00000000 },
3385 { 0x3c2c, 0, 0xffffffff, 0x00000000 },
3386 { 0x3c30, 0, 0xffffffff, 0x00000000 },
3387 { 0x3c34, 0, 0xffffffff, 0x00000000 },
3388 { 0x3c38, 0, 0xffffffff, 0x00000000 },
3389 { 0x3c3c, 0, 0xffffffff, 0x00000000 },
3390 { 0x3c40, 0, 0xffffffff, 0x00000000 },
3391 { 0x3c44, 0, 0xffffffff, 0x00000000 },
3392 { 0x3c48, 0, 0xffffffff, 0x00000000 },
3393 { 0x3c4c, 0, 0xffffffff, 0x00000000 },
3394 { 0x3c50, 0, 0xffffffff, 0x00000000 },
3395 { 0x3c54, 0, 0xffffffff, 0x00000000 },
3396 { 0x3c58, 0, 0xffffffff, 0x00000000 },
3397 { 0x3c5c, 0, 0xffffffff, 0x00000000 },
3398 { 0x3c60, 0, 0xffffffff, 0x00000000 },
3399 { 0x3c64, 0, 0xffffffff, 0x00000000 },
3400 { 0x3c68, 0, 0xffffffff, 0x00000000 },
3401 { 0x3c6c, 0, 0xffffffff, 0x00000000 },
3402 { 0x3c70, 0, 0xffffffff, 0x00000000 },
3403 { 0x3c74, 0, 0x0000003f, 0x00000000 },
3404 { 0x3c78, 0, 0x00000000, 0x00000000 },
3405 { 0x3c7c, 0, 0x00000000, 0x00000000 },
3406 { 0x3c80, 0, 0x3fffffff, 0x00000000 },
3407 { 0x3c84, 0, 0x0000003f, 0x00000000 },
3408 { 0x3c88, 0, 0x00000000, 0xffffffff },
3409 { 0x3c8c, 0, 0x00000000, 0xffffffff },
3410
3411 { 0x4000, 0, 0x00000000, 0x00000001 },
3412 { 0x4004, 0, 0x00000000, 0x00030000 },
3413 { 0x4008, 0, 0x00000ff0, 0x00000000 },
3414 { 0x400c, 0, 0xffffffff, 0x00000000 },
3415 { 0x4088, 0, 0x00000000, 0x00070303 },
3416
3417 { 0x4400, 0, 0x00000000, 0x00000001 },
3418 { 0x4404, 0, 0x00000000, 0x00003f01 },
3419 { 0x4408, 0, 0x7fff00ff, 0x00000000 },
3420 { 0x440c, 0, 0xffffffff, 0x00000000 },
3421 { 0x4410, 0, 0xffff, 0x0000 },
3422 { 0x4414, 0, 0xffff, 0x0000 },
3423 { 0x4418, 0, 0xffff, 0x0000 },
3424 { 0x441c, 0, 0xffff, 0x0000 },
3425 { 0x4428, 0, 0xffffffff, 0x00000000 },
3426 { 0x442c, 0, 0xffffffff, 0x00000000 },
3427 { 0x4430, 0, 0xffffffff, 0x00000000 },
3428 { 0x4434, 0, 0xffffffff, 0x00000000 },
3429 { 0x4438, 0, 0xffffffff, 0x00000000 },
3430 { 0x443c, 0, 0xffffffff, 0x00000000 },
3431 { 0x4440, 0, 0xffffffff, 0x00000000 },
3432 { 0x4444, 0, 0xffffffff, 0x00000000 },
3433
3434 { 0x4c00, 0, 0x00000000, 0x00000001 },
3435 { 0x4c04, 0, 0x00000000, 0x0000003f },
3436 { 0x4c08, 0, 0xffffffff, 0x00000000 },
3437 { 0x4c0c, 0, 0x0007fc00, 0x00000000 },
3438 { 0x4c10, 0, 0x80003fe0, 0x00000000 },
3439 { 0x4c14, 0, 0xffffffff, 0x00000000 },
3440 { 0x4c44, 0, 0x00000000, 0x9fff9fff },
3441 { 0x4c48, 0, 0x00000000, 0xb3009fff },
3442 { 0x4c4c, 0, 0x00000000, 0x77f33b30 },
3443 { 0x4c50, 0, 0x00000000, 0xffffffff },
3444
3445 { 0x5004, 0, 0x00000000, 0x0000007f },
3446 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
3447 { 0x500c, 0, 0xf800f800, 0x07ff07ff },
3448
3449 { 0x5400, 0, 0x00000008, 0x00000001 },
3450 { 0x5404, 0, 0x00000000, 0x0000003f },
3451 { 0x5408, 0, 0x0000001f, 0x00000000 },
3452 { 0x540c, 0, 0xffffffff, 0x00000000 },
3453 { 0x5410, 0, 0xffffffff, 0x00000000 },
3454 { 0x5414, 0, 0x0000ffff, 0x00000000 },
3455 { 0x5418, 0, 0x0000ffff, 0x00000000 },
3456 { 0x541c, 0, 0x0000ffff, 0x00000000 },
3457 { 0x5420, 0, 0x0000ffff, 0x00000000 },
3458 { 0x5428, 0, 0x000000ff, 0x00000000 },
3459 { 0x542c, 0, 0xff00ffff, 0x00000000 },
3460 { 0x5430, 0, 0x001fff80, 0x00000000 },
3461 { 0x5438, 0, 0xffffffff, 0x00000000 },
3462 { 0x543c, 0, 0xffffffff, 0x00000000 },
3463 { 0x5440, 0, 0xf800f800, 0x07ff07ff },
3464
3465 { 0x5c00, 0, 0x00000000, 0x00000001 },
3466 { 0x5c04, 0, 0x00000000, 0x0003000f },
3467 { 0x5c08, 0, 0x00000003, 0x00000000 },
3468 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
3469 { 0x5c10, 0, 0x00000000, 0xffffffff },
3470 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
3471 { 0x5c84, 0, 0x00000000, 0x0000f333 },
3472 { 0x5c88, 0, 0x00000000, 0x00077373 },
3473 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
3474
3475 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
3476 { 0x680c, 0, 0xffffffff, 0x00000000 },
3477 { 0x6810, 0, 0xffffffff, 0x00000000 },
3478 { 0x6814, 0, 0xffffffff, 0x00000000 },
3479 { 0x6818, 0, 0xffffffff, 0x00000000 },
3480 { 0x681c, 0, 0xffffffff, 0x00000000 },
3481 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
3482 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
3483 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
3484 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
3485 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
3486 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
3487 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
3488 { 0x683c, 0, 0x0000ffff, 0x00000000 },
3489 { 0x6840, 0, 0x00000ff0, 0x00000000 },
3490 { 0x6844, 0, 0x00ffff00, 0x00000000 },
3491 { 0x684c, 0, 0xffffffff, 0x00000000 },
3492 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
3493 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
3494 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
3495 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
3496 { 0x6908, 0, 0x00000000, 0x0001ff0f },
3497 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
3498
3499 { 0xffff, 0, 0x00000000, 0x00000000 },
3500 };
3501
3502 ret = 0;
3503 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
3504 u32 offset, rw_mask, ro_mask, save_val, val;
3505
3506 offset = (u32) reg_tbl[i].offset;
3507 rw_mask = reg_tbl[i].rw_mask;
3508 ro_mask = reg_tbl[i].ro_mask;
3509
3510 save_val = readl((u8 *) bp->regview + offset);
3511
3512 writel(0, (u8 *) bp->regview + offset);
3513
3514 val = readl((u8 *) bp->regview + offset);
3515 if ((val & rw_mask) != 0) {
3516 goto reg_test_err;
3517 }
3518
3519 if ((val & ro_mask) != (save_val & ro_mask)) {
3520 goto reg_test_err;
3521 }
3522
3523 writel(0xffffffff, (u8 *) bp->regview + offset);
3524
3525 val = readl((u8 *) bp->regview + offset);
3526 if ((val & rw_mask) != rw_mask) {
3527 goto reg_test_err;
3528 }
3529
3530 if ((val & ro_mask) != (save_val & ro_mask)) {
3531 goto reg_test_err;
3532 }
3533
3534 writel(save_val, (u8 *) bp->regview + offset);
3535 continue;
3536
3537reg_test_err:
3538 writel(save_val, (u8 *) bp->regview + offset);
3539 ret = -ENODEV;
3540 break;
3541 }
3542 return ret;
3543}
3544
3545static int
3546bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
3547{
3548 static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
3549 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
3550 int i;
3551
3552 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
3553 u32 offset;
3554
3555 for (offset = 0; offset < size; offset += 4) {
3556
3557 REG_WR_IND(bp, start + offset, test_pattern[i]);
3558
3559 if (REG_RD_IND(bp, start + offset) !=
3560 test_pattern[i]) {
3561 return -ENODEV;
3562 }
3563 }
3564 }
3565 return 0;
3566}
3567
3568static int
3569bnx2_test_memory(struct bnx2 *bp)
3570{
3571 int ret = 0;
3572 int i;
3573 static struct {
3574 u32 offset;
3575 u32 len;
3576 } mem_tbl[] = {
3577 { 0x60000, 0x4000 },
3578 { 0xa0000, 0x4000 },
3579 { 0xe0000, 0x4000 },
3580 { 0x120000, 0x4000 },
3581 { 0x1a0000, 0x4000 },
3582 { 0x160000, 0x4000 },
3583 { 0xffffffff, 0 },
3584 };
3585
3586 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
3587 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
3588 mem_tbl[i].len)) != 0) {
3589 return ret;
3590 }
3591 }
3592
3593 return ret;
3594}
3595
3596static int
3597bnx2_test_loopback(struct bnx2 *bp)
3598{
3599 unsigned int pkt_size, num_pkts, i;
3600 struct sk_buff *skb, *rx_skb;
3601 unsigned char *packet;
3602 u16 rx_start_idx, rx_idx, send_idx;
3603 u32 send_bseq, val;
3604 dma_addr_t map;
3605 struct tx_bd *txbd;
3606 struct sw_bd *rx_buf;
3607 struct l2_fhdr *rx_hdr;
3608 int ret = -ENODEV;
3609
3610 if (!netif_running(bp->dev))
3611 return -ENODEV;
3612
3613 bp->loopback = MAC_LOOPBACK;
3614 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_DIAG);
3615 bnx2_set_mac_loopback(bp);
3616
3617 pkt_size = 1514;
3618 skb = dev_alloc_skb(pkt_size);
3619 packet = skb_put(skb, pkt_size);
3620 memcpy(packet, bp->mac_addr, 6);
3621 memset(packet + 6, 0x0, 8);
3622 for (i = 14; i < pkt_size; i++)
3623 packet[i] = (unsigned char) (i & 0xff);
3624
3625 map = pci_map_single(bp->pdev, skb->data, pkt_size,
3626 PCI_DMA_TODEVICE);
3627
3628 val = REG_RD(bp, BNX2_HC_COMMAND);
3629 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3630 REG_RD(bp, BNX2_HC_COMMAND);
3631
3632 udelay(5);
3633 rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
3634
3635 send_idx = 0;
3636 send_bseq = 0;
3637 num_pkts = 0;
3638
3639 txbd = &bp->tx_desc_ring[send_idx];
3640
3641 txbd->tx_bd_haddr_hi = (u64) map >> 32;
3642 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
3643 txbd->tx_bd_mss_nbytes = pkt_size;
3644 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
3645
3646 num_pkts++;
3647 send_idx = NEXT_TX_BD(send_idx);
3648
3649 send_bseq += pkt_size;
3650
3651 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, send_idx);
3652 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, send_bseq);
3653
3654
3655 udelay(100);
3656
3657 val = REG_RD(bp, BNX2_HC_COMMAND);
3658 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3659 REG_RD(bp, BNX2_HC_COMMAND);
3660
3661 udelay(5);
3662
3663 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
3664 dev_kfree_skb_irq(skb);
3665
3666 if (bp->status_blk->status_tx_quick_consumer_index0 != send_idx) {
3667 goto loopback_test_done;
3668 }
3669
3670 rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
3671 if (rx_idx != rx_start_idx + num_pkts) {
3672 goto loopback_test_done;
3673 }
3674
3675 rx_buf = &bp->rx_buf_ring[rx_start_idx];
3676 rx_skb = rx_buf->skb;
3677
3678 rx_hdr = (struct l2_fhdr *) rx_skb->data;
3679 skb_reserve(rx_skb, bp->rx_offset);
3680
3681 pci_dma_sync_single_for_cpu(bp->pdev,
3682 pci_unmap_addr(rx_buf, mapping),
3683 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
3684
3685 if (rx_hdr->l2_fhdr_errors &
3686 (L2_FHDR_ERRORS_BAD_CRC |
3687 L2_FHDR_ERRORS_PHY_DECODE |
3688 L2_FHDR_ERRORS_ALIGNMENT |
3689 L2_FHDR_ERRORS_TOO_SHORT |
3690 L2_FHDR_ERRORS_GIANT_FRAME)) {
3691
3692 goto loopback_test_done;
3693 }
3694
3695 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
3696 goto loopback_test_done;
3697 }
3698
3699 for (i = 14; i < pkt_size; i++) {
3700 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
3701 goto loopback_test_done;
3702 }
3703 }
3704
3705 ret = 0;
3706
3707loopback_test_done:
3708 bp->loopback = 0;
3709 return ret;
3710}
3711
3712#define NVRAM_SIZE 0x200
3713#define CRC32_RESIDUAL 0xdebb20e3
3714
3715static int
3716bnx2_test_nvram(struct bnx2 *bp)
3717{
3718 u32 buf[NVRAM_SIZE / 4];
3719 u8 *data = (u8 *) buf;
3720 int rc = 0;
3721 u32 magic, csum;
3722
3723 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
3724 goto test_nvram_done;
3725
3726 magic = be32_to_cpu(buf[0]);
3727 if (magic != 0x669955aa) {
3728 rc = -ENODEV;
3729 goto test_nvram_done;
3730 }
3731
3732 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
3733 goto test_nvram_done;
3734
3735 csum = ether_crc_le(0x100, data);
3736 if (csum != CRC32_RESIDUAL) {
3737 rc = -ENODEV;
3738 goto test_nvram_done;
3739 }
3740
3741 csum = ether_crc_le(0x100, data + 0x100);
3742 if (csum != CRC32_RESIDUAL) {
3743 rc = -ENODEV;
3744 }
3745
3746test_nvram_done:
3747 return rc;
3748}
3749
3750static int
3751bnx2_test_link(struct bnx2 *bp)
3752{
3753 u32 bmsr;
3754
3755 spin_lock_irq(&bp->phy_lock);
3756 bnx2_read_phy(bp, MII_BMSR, &bmsr);
3757 bnx2_read_phy(bp, MII_BMSR, &bmsr);
3758 spin_unlock_irq(&bp->phy_lock);
3759
3760 if (bmsr & BMSR_LSTATUS) {
3761 return 0;
3762 }
3763 return -ENODEV;
3764}
3765
3766static int
3767bnx2_test_intr(struct bnx2 *bp)
3768{
3769 int i;
3770 u32 val;
3771 u16 status_idx;
3772
3773 if (!netif_running(bp->dev))
3774 return -ENODEV;
3775
3776 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
3777
3778 /* This register is not touched during run-time. */
3779 val = REG_RD(bp, BNX2_HC_COMMAND);
3780 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
3781 REG_RD(bp, BNX2_HC_COMMAND);
3782
3783 for (i = 0; i < 10; i++) {
3784 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
3785 status_idx) {
3786
3787 break;
3788 }
3789
3790 msleep_interruptible(10);
3791 }
3792 if (i < 10)
3793 return 0;
3794
3795 return -ENODEV;
3796}
3797
3798static void
3799bnx2_timer(unsigned long data)
3800{
3801 struct bnx2 *bp = (struct bnx2 *) data;
3802 u32 msg;
3803
3804 if (atomic_read(&bp->intr_sem) != 0)
3805 goto bnx2_restart_timer;
3806
3807 msg = (u32) ++bp->fw_drv_pulse_wr_seq;
3808 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_PULSE_MB, msg);
3809
3810 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
3811 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
3812 unsigned long flags;
3813
3814 spin_lock_irqsave(&bp->phy_lock, flags);
3815 if (bp->serdes_an_pending) {
3816 bp->serdes_an_pending--;
3817 }
3818 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
3819 u32 bmcr;
3820
3821 bnx2_read_phy(bp, MII_BMCR, &bmcr);
3822
3823 if (bmcr & BMCR_ANENABLE) {
3824 u32 phy1, phy2;
3825
3826 bnx2_write_phy(bp, 0x1c, 0x7c00);
3827 bnx2_read_phy(bp, 0x1c, &phy1);
3828
3829 bnx2_write_phy(bp, 0x17, 0x0f01);
3830 bnx2_read_phy(bp, 0x15, &phy2);
3831 bnx2_write_phy(bp, 0x17, 0x0f01);
3832 bnx2_read_phy(bp, 0x15, &phy2);
3833
3834 if ((phy1 & 0x10) && /* SIGNAL DETECT */
3835 !(phy2 & 0x20)) { /* no CONFIG */
3836
3837 bmcr &= ~BMCR_ANENABLE;
3838 bmcr |= BMCR_SPEED1000 |
3839 BMCR_FULLDPLX;
3840 bnx2_write_phy(bp, MII_BMCR, bmcr);
3841 bp->phy_flags |=
3842 PHY_PARALLEL_DETECT_FLAG;
3843 }
3844 }
3845 }
3846 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
3847 (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
3848 u32 phy2;
3849
3850 bnx2_write_phy(bp, 0x17, 0x0f01);
3851 bnx2_read_phy(bp, 0x15, &phy2);
3852 if (phy2 & 0x20) {
3853 u32 bmcr;
3854
3855 bnx2_read_phy(bp, MII_BMCR, &bmcr);
3856 bmcr |= BMCR_ANENABLE;
3857 bnx2_write_phy(bp, MII_BMCR, bmcr);
3858
3859 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
3860
3861 }
3862 }
3863
3864 spin_unlock_irqrestore(&bp->phy_lock, flags);
3865 }
3866
3867bnx2_restart_timer:
3868 bp->timer.expires = RUN_AT(bp->timer_interval);
3869
3870 add_timer(&bp->timer);
3871}
3872
3873/* Called with rtnl_lock */
3874static int
3875bnx2_open(struct net_device *dev)
3876{
3877 struct bnx2 *bp = dev->priv;
3878 int rc;
3879
3880 bnx2_set_power_state(bp, 0);
3881 bnx2_disable_int(bp);
3882
3883 rc = bnx2_alloc_mem(bp);
3884 if (rc)
3885 return rc;
3886
3887 if ((CHIP_ID(bp) != CHIP_ID_5706_A0) &&
3888 (CHIP_ID(bp) != CHIP_ID_5706_A1) &&
3889 !disable_msi) {
3890
3891 if (pci_enable_msi(bp->pdev) == 0) {
3892 bp->flags |= USING_MSI_FLAG;
3893 rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name,
3894 dev);
3895 }
3896 else {
3897 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
3898 SA_SHIRQ, dev->name, dev);
3899 }
3900 }
3901 else {
3902 rc = request_irq(bp->pdev->irq, bnx2_interrupt, SA_SHIRQ,
3903 dev->name, dev);
3904 }
3905 if (rc) {
3906 bnx2_free_mem(bp);
3907 return rc;
3908 }
3909
3910 rc = bnx2_init_nic(bp);
3911
3912 if (rc) {
3913 free_irq(bp->pdev->irq, dev);
3914 if (bp->flags & USING_MSI_FLAG) {
3915 pci_disable_msi(bp->pdev);
3916 bp->flags &= ~USING_MSI_FLAG;
3917 }
3918 bnx2_free_skbs(bp);
3919 bnx2_free_mem(bp);
3920 return rc;
3921 }
3922
3923 init_timer(&bp->timer);
3924
3925 bp->timer.expires = RUN_AT(bp->timer_interval);
3926 bp->timer.data = (unsigned long) bp;
3927 bp->timer.function = bnx2_timer;
3928 add_timer(&bp->timer);
3929
3930 atomic_set(&bp->intr_sem, 0);
3931
3932 bnx2_enable_int(bp);
3933
3934 if (bp->flags & USING_MSI_FLAG) {
3935 /* Test MSI to make sure it is working
3936 * If MSI test fails, go back to INTx mode
3937 */
3938 if (bnx2_test_intr(bp) != 0) {
3939 printk(KERN_WARNING PFX "%s: No interrupt was generated"
3940 " using MSI, switching to INTx mode. Please"
3941 " report this failure to the PCI maintainer"
3942 " and include system chipset information.\n",
3943 bp->dev->name);
3944
3945 bnx2_disable_int(bp);
3946 free_irq(bp->pdev->irq, dev);
3947 pci_disable_msi(bp->pdev);
3948 bp->flags &= ~USING_MSI_FLAG;
3949
3950 rc = bnx2_init_nic(bp);
3951
3952 if (!rc) {
3953 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
3954 SA_SHIRQ, dev->name, dev);
3955 }
3956 if (rc) {
3957 bnx2_free_skbs(bp);
3958 bnx2_free_mem(bp);
3959 del_timer_sync(&bp->timer);
3960 return rc;
3961 }
3962 bnx2_enable_int(bp);
3963 }
3964 }
3965 if (bp->flags & USING_MSI_FLAG) {
3966 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
3967 }
3968
3969 netif_start_queue(dev);
3970
3971 return 0;
3972}
3973
3974static void
3975bnx2_reset_task(void *data)
3976{
3977 struct bnx2 *bp = data;
3978
3979 bnx2_netif_stop(bp);
3980
3981 bnx2_init_nic(bp);
3982
3983 atomic_set(&bp->intr_sem, 1);
3984 bnx2_netif_start(bp);
3985}
3986
3987static void
3988bnx2_tx_timeout(struct net_device *dev)
3989{
3990 struct bnx2 *bp = dev->priv;
3991
3992 /* This allows the netif to be shutdown gracefully before resetting */
3993 schedule_work(&bp->reset_task);
3994}
3995
3996#ifdef BCM_VLAN
3997/* Called with rtnl_lock */
3998static void
3999bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
4000{
4001 struct bnx2 *bp = dev->priv;
4002
4003 bnx2_netif_stop(bp);
4004
4005 bp->vlgrp = vlgrp;
4006 bnx2_set_rx_mode(dev);
4007
4008 bnx2_netif_start(bp);
4009}
4010
4011/* Called with rtnl_lock */
4012static void
4013bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
4014{
4015 struct bnx2 *bp = dev->priv;
4016
4017 bnx2_netif_stop(bp);
4018
4019 if (bp->vlgrp)
4020 bp->vlgrp->vlan_devices[vid] = NULL;
4021 bnx2_set_rx_mode(dev);
4022
4023 bnx2_netif_start(bp);
4024}
4025#endif
4026
4027/* Called with dev->xmit_lock.
4028 * hard_start_xmit is pseudo-lockless - a lock is only required when
4029 * the tx queue is full. This way, we get the benefit of lockless
4030 * operations most of the time without the complexities to handle
4031 * netif_stop_queue/wake_queue race conditions.
4032 */
4033static int
4034bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
4035{
4036 struct bnx2 *bp = dev->priv;
4037 dma_addr_t mapping;
4038 struct tx_bd *txbd;
4039 struct sw_bd *tx_buf;
4040 u32 len, vlan_tag_flags, last_frag, mss;
4041 u16 prod, ring_prod;
4042 int i;
4043
4044 if (unlikely(atomic_read(&bp->tx_avail_bd) <
4045 (skb_shinfo(skb)->nr_frags + 1))) {
4046
4047 netif_stop_queue(dev);
4048 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
4049 dev->name);
4050
4051 return NETDEV_TX_BUSY;
4052 }
4053 len = skb_headlen(skb);
4054 prod = bp->tx_prod;
4055 ring_prod = TX_RING_IDX(prod);
4056
4057 vlan_tag_flags = 0;
4058 if (skb->ip_summed == CHECKSUM_HW) {
4059 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4060 }
4061
4062 if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
4063 vlan_tag_flags |=
4064 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
4065 }
4066#ifdef BCM_TSO
4067 if ((mss = skb_shinfo(skb)->tso_size) &&
4068 (skb->len > (bp->dev->mtu + ETH_HLEN))) {
4069 u32 tcp_opt_len, ip_tcp_len;
4070
4071 if (skb_header_cloned(skb) &&
4072 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4073 dev_kfree_skb(skb);
4074 return NETDEV_TX_OK;
4075 }
4076
4077 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4078 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
4079
4080 tcp_opt_len = 0;
4081 if (skb->h.th->doff > 5) {
4082 tcp_opt_len = (skb->h.th->doff - 5) << 2;
4083 }
4084 ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr);
4085
4086 skb->nh.iph->check = 0;
4087 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
4088 skb->h.th->check =
4089 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4090 skb->nh.iph->daddr,
4091 0, IPPROTO_TCP, 0);
4092
4093 if (tcp_opt_len || (skb->nh.iph->ihl > 5)) {
4094 vlan_tag_flags |= ((skb->nh.iph->ihl - 5) +
4095 (tcp_opt_len >> 2)) << 8;
4096 }
4097 }
4098 else
4099#endif
4100 {
4101 mss = 0;
4102 }
4103
4104 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4105
4106 tx_buf = &bp->tx_buf_ring[ring_prod];
4107 tx_buf->skb = skb;
4108 pci_unmap_addr_set(tx_buf, mapping, mapping);
4109
4110 txbd = &bp->tx_desc_ring[ring_prod];
4111
4112 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4113 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4114 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4115 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
4116
4117 last_frag = skb_shinfo(skb)->nr_frags;
4118
4119 for (i = 0; i < last_frag; i++) {
4120 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4121
4122 prod = NEXT_TX_BD(prod);
4123 ring_prod = TX_RING_IDX(prod);
4124 txbd = &bp->tx_desc_ring[ring_prod];
4125
4126 len = frag->size;
4127 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
4128 len, PCI_DMA_TODEVICE);
4129 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
4130 mapping, mapping);
4131
4132 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4133 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4134 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4135 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
4136
4137 }
4138 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
4139
4140 prod = NEXT_TX_BD(prod);
4141 bp->tx_prod_bseq += skb->len;
4142
4143 atomic_sub(last_frag + 1, &bp->tx_avail_bd);
4144
4145 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
4146 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
4147
4148 mmiowb();
4149
4150 bp->tx_prod = prod;
4151 dev->trans_start = jiffies;
4152
4153 if (unlikely(atomic_read(&bp->tx_avail_bd) <= MAX_SKB_FRAGS)) {
4154 unsigned long flags;
4155
4156 spin_lock_irqsave(&bp->tx_lock, flags);
4157 if (atomic_read(&bp->tx_avail_bd) <= MAX_SKB_FRAGS) {
4158 netif_stop_queue(dev);
4159
4160 if (atomic_read(&bp->tx_avail_bd) > MAX_SKB_FRAGS)
4161 netif_wake_queue(dev);
4162 }
4163 spin_unlock_irqrestore(&bp->tx_lock, flags);
4164 }
4165
4166 return NETDEV_TX_OK;
4167}
4168
4169/* Called with rtnl_lock */
4170static int
4171bnx2_close(struct net_device *dev)
4172{
4173 struct bnx2 *bp = dev->priv;
4174 u32 reset_code;
4175
4176 flush_scheduled_work();
4177 bnx2_netif_stop(bp);
4178 del_timer_sync(&bp->timer);
4179 if (bp->wol)
4180 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4181 else
4182 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4183 bnx2_reset_chip(bp, reset_code);
4184 free_irq(bp->pdev->irq, dev);
4185 if (bp->flags & USING_MSI_FLAG) {
4186 pci_disable_msi(bp->pdev);
4187 bp->flags &= ~USING_MSI_FLAG;
4188 }
4189 bnx2_free_skbs(bp);
4190 bnx2_free_mem(bp);
4191 bp->link_up = 0;
4192 netif_carrier_off(bp->dev);
4193 bnx2_set_power_state(bp, 3);
4194 return 0;
4195}
4196
4197#define GET_NET_STATS64(ctr) \
4198 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
4199 (unsigned long) (ctr##_lo)
4200
4201#define GET_NET_STATS32(ctr) \
4202 (ctr##_lo)
4203
4204#if (BITS_PER_LONG == 64)
4205#define GET_NET_STATS GET_NET_STATS64
4206#else
4207#define GET_NET_STATS GET_NET_STATS32
4208#endif
4209
4210static struct net_device_stats *
4211bnx2_get_stats(struct net_device *dev)
4212{
4213 struct bnx2 *bp = dev->priv;
4214 struct statistics_block *stats_blk = bp->stats_blk;
4215 struct net_device_stats *net_stats = &bp->net_stats;
4216
4217 if (bp->stats_blk == NULL) {
4218 return net_stats;
4219 }
4220 net_stats->rx_packets =
4221 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
4222 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
4223 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
4224
4225 net_stats->tx_packets =
4226 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
4227 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
4228 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
4229
4230 net_stats->rx_bytes =
4231 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
4232
4233 net_stats->tx_bytes =
4234 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
4235
4236 net_stats->multicast =
4237 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
4238
4239 net_stats->collisions =
4240 (unsigned long) stats_blk->stat_EtherStatsCollisions;
4241
4242 net_stats->rx_length_errors =
4243 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
4244 stats_blk->stat_EtherStatsOverrsizePkts);
4245
4246 net_stats->rx_over_errors =
4247 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
4248
4249 net_stats->rx_frame_errors =
4250 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
4251
4252 net_stats->rx_crc_errors =
4253 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
4254
4255 net_stats->rx_errors = net_stats->rx_length_errors +
4256 net_stats->rx_over_errors + net_stats->rx_frame_errors +
4257 net_stats->rx_crc_errors;
4258
4259 net_stats->tx_aborted_errors =
4260 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
4261 stats_blk->stat_Dot3StatsLateCollisions);
4262
4263 if (CHIP_NUM(bp) == CHIP_NUM_5706)
4264 net_stats->tx_carrier_errors = 0;
4265 else {
4266 net_stats->tx_carrier_errors =
4267 (unsigned long)
4268 stats_blk->stat_Dot3StatsCarrierSenseErrors;
4269 }
4270
4271 net_stats->tx_errors =
4272 (unsigned long)
4273 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
4274 +
4275 net_stats->tx_aborted_errors +
4276 net_stats->tx_carrier_errors;
4277
4278 return net_stats;
4279}
4280
4281/* All ethtool functions called with rtnl_lock */
4282
4283static int
4284bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4285{
4286 struct bnx2 *bp = dev->priv;
4287
4288 cmd->supported = SUPPORTED_Autoneg;
4289 if (bp->phy_flags & PHY_SERDES_FLAG) {
4290 cmd->supported |= SUPPORTED_1000baseT_Full |
4291 SUPPORTED_FIBRE;
4292
4293 cmd->port = PORT_FIBRE;
4294 }
4295 else {
4296 cmd->supported |= SUPPORTED_10baseT_Half |
4297 SUPPORTED_10baseT_Full |
4298 SUPPORTED_100baseT_Half |
4299 SUPPORTED_100baseT_Full |
4300 SUPPORTED_1000baseT_Full |
4301 SUPPORTED_TP;
4302
4303 cmd->port = PORT_TP;
4304 }
4305
4306 cmd->advertising = bp->advertising;
4307
4308 if (bp->autoneg & AUTONEG_SPEED) {
4309 cmd->autoneg = AUTONEG_ENABLE;
4310 }
4311 else {
4312 cmd->autoneg = AUTONEG_DISABLE;
4313 }
4314
4315 if (netif_carrier_ok(dev)) {
4316 cmd->speed = bp->line_speed;
4317 cmd->duplex = bp->duplex;
4318 }
4319 else {
4320 cmd->speed = -1;
4321 cmd->duplex = -1;
4322 }
4323
4324 cmd->transceiver = XCVR_INTERNAL;
4325 cmd->phy_address = bp->phy_addr;
4326
4327 return 0;
4328}
4329
4330static int
4331bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4332{
4333 struct bnx2 *bp = dev->priv;
4334 u8 autoneg = bp->autoneg;
4335 u8 req_duplex = bp->req_duplex;
4336 u16 req_line_speed = bp->req_line_speed;
4337 u32 advertising = bp->advertising;
4338
4339 if (cmd->autoneg == AUTONEG_ENABLE) {
4340 autoneg |= AUTONEG_SPEED;
4341
4342 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
4343
4344 /* allow advertising 1 speed */
4345 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
4346 (cmd->advertising == ADVERTISED_10baseT_Full) ||
4347 (cmd->advertising == ADVERTISED_100baseT_Half) ||
4348 (cmd->advertising == ADVERTISED_100baseT_Full)) {
4349
4350 if (bp->phy_flags & PHY_SERDES_FLAG)
4351 return -EINVAL;
4352
4353 advertising = cmd->advertising;
4354
4355 }
4356 else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
4357 advertising = cmd->advertising;
4358 }
4359 else if (cmd->advertising == ADVERTISED_1000baseT_Half) {
4360 return -EINVAL;
4361 }
4362 else {
4363 if (bp->phy_flags & PHY_SERDES_FLAG) {
4364 advertising = ETHTOOL_ALL_FIBRE_SPEED;
4365 }
4366 else {
4367 advertising = ETHTOOL_ALL_COPPER_SPEED;
4368 }
4369 }
4370 advertising |= ADVERTISED_Autoneg;
4371 }
4372 else {
4373 if (bp->phy_flags & PHY_SERDES_FLAG) {
4374 if ((cmd->speed != SPEED_1000) ||
4375 (cmd->duplex != DUPLEX_FULL)) {
4376 return -EINVAL;
4377 }
4378 }
4379 else if (cmd->speed == SPEED_1000) {
4380 return -EINVAL;
4381 }
4382 autoneg &= ~AUTONEG_SPEED;
4383 req_line_speed = cmd->speed;
4384 req_duplex = cmd->duplex;
4385 advertising = 0;
4386 }
4387
4388 bp->autoneg = autoneg;
4389 bp->advertising = advertising;
4390 bp->req_line_speed = req_line_speed;
4391 bp->req_duplex = req_duplex;
4392
4393 spin_lock_irq(&bp->phy_lock);
4394
4395 bnx2_setup_phy(bp);
4396
4397 spin_unlock_irq(&bp->phy_lock);
4398
4399 return 0;
4400}
4401
4402static void
4403bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4404{
4405 struct bnx2 *bp = dev->priv;
4406
4407 strcpy(info->driver, DRV_MODULE_NAME);
4408 strcpy(info->version, DRV_MODULE_VERSION);
4409 strcpy(info->bus_info, pci_name(bp->pdev));
4410 info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0';
4411 info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0';
4412 info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0';
4413 info->fw_version[6] = (bp->fw_ver & 0xff) + '0';
4414 info->fw_version[1] = info->fw_version[3] = info->fw_version[5] = '.';
4415 info->fw_version[7] = 0;
4416}
4417
4418static void
4419bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4420{
4421 struct bnx2 *bp = dev->priv;
4422
4423 if (bp->flags & NO_WOL_FLAG) {
4424 wol->supported = 0;
4425 wol->wolopts = 0;
4426 }
4427 else {
4428 wol->supported = WAKE_MAGIC;
4429 if (bp->wol)
4430 wol->wolopts = WAKE_MAGIC;
4431 else
4432 wol->wolopts = 0;
4433 }
4434 memset(&wol->sopass, 0, sizeof(wol->sopass));
4435}
4436
4437static int
4438bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4439{
4440 struct bnx2 *bp = dev->priv;
4441
4442 if (wol->wolopts & ~WAKE_MAGIC)
4443 return -EINVAL;
4444
4445 if (wol->wolopts & WAKE_MAGIC) {
4446 if (bp->flags & NO_WOL_FLAG)
4447 return -EINVAL;
4448
4449 bp->wol = 1;
4450 }
4451 else {
4452 bp->wol = 0;
4453 }
4454 return 0;
4455}
4456
4457static int
4458bnx2_nway_reset(struct net_device *dev)
4459{
4460 struct bnx2 *bp = dev->priv;
4461 u32 bmcr;
4462
4463 if (!(bp->autoneg & AUTONEG_SPEED)) {
4464 return -EINVAL;
4465 }
4466
4467 spin_lock_irq(&bp->phy_lock);
4468
4469 /* Force a link down visible on the other side */
4470 if (bp->phy_flags & PHY_SERDES_FLAG) {
4471 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
4472 spin_unlock_irq(&bp->phy_lock);
4473
4474 msleep(20);
4475
4476 spin_lock_irq(&bp->phy_lock);
4477 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
4478 bp->serdes_an_pending = SERDES_AN_TIMEOUT /
4479 bp->timer_interval;
4480 }
4481 }
4482
4483 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4484 bmcr &= ~BMCR_LOOPBACK;
4485 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
4486
4487 spin_unlock_irq(&bp->phy_lock);
4488
4489 return 0;
4490}
4491
4492static int
4493bnx2_get_eeprom_len(struct net_device *dev)
4494{
4495 struct bnx2 *bp = dev->priv;
4496
4497 if (bp->flash_info == 0)
4498 return 0;
4499
4500 return (int) bp->flash_info->total_size;
4501}
4502
4503static int
4504bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4505 u8 *eebuf)
4506{
4507 struct bnx2 *bp = dev->priv;
4508 int rc;
4509
4510 if (eeprom->offset > bp->flash_info->total_size)
4511 return -EINVAL;
4512
4513 if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size)
4514 eeprom->len = bp->flash_info->total_size - eeprom->offset;
4515
4516 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
4517
4518 return rc;
4519}
4520
4521static int
4522bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4523 u8 *eebuf)
4524{
4525 struct bnx2 *bp = dev->priv;
4526 int rc;
4527
4528 if (eeprom->offset > bp->flash_info->total_size)
4529 return -EINVAL;
4530
4531 if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size)
4532 eeprom->len = bp->flash_info->total_size - eeprom->offset;
4533
4534 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
4535
4536 return rc;
4537}
4538
4539static int
4540bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4541{
4542 struct bnx2 *bp = dev->priv;
4543
4544 memset(coal, 0, sizeof(struct ethtool_coalesce));
4545
4546 coal->rx_coalesce_usecs = bp->rx_ticks;
4547 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
4548 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
4549 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
4550
4551 coal->tx_coalesce_usecs = bp->tx_ticks;
4552 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
4553 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
4554 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
4555
4556 coal->stats_block_coalesce_usecs = bp->stats_ticks;
4557
4558 return 0;
4559}
4560
4561static int
4562bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4563{
4564 struct bnx2 *bp = dev->priv;
4565
4566 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
4567 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
4568
4569 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
4570 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
4571
4572 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
4573 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
4574
4575 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
4576 if (bp->rx_quick_cons_trip_int > 0xff)
4577 bp->rx_quick_cons_trip_int = 0xff;
4578
4579 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
4580 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
4581
4582 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
4583 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
4584
4585 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
4586 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
4587
4588 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
4589 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
4590 0xff;
4591
4592 bp->stats_ticks = coal->stats_block_coalesce_usecs;
4593 if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00;
4594 bp->stats_ticks &= 0xffff00;
4595
4596 if (netif_running(bp->dev)) {
4597 bnx2_netif_stop(bp);
4598 bnx2_init_nic(bp);
4599 bnx2_netif_start(bp);
4600 }
4601
4602 return 0;
4603}
4604
4605static void
4606bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4607{
4608 struct bnx2 *bp = dev->priv;
4609
4610 ering->rx_max_pending = MAX_RX_DESC_CNT;
4611 ering->rx_mini_max_pending = 0;
4612 ering->rx_jumbo_max_pending = 0;
4613
4614 ering->rx_pending = bp->rx_ring_size;
4615 ering->rx_mini_pending = 0;
4616 ering->rx_jumbo_pending = 0;
4617
4618 ering->tx_max_pending = MAX_TX_DESC_CNT;
4619 ering->tx_pending = bp->tx_ring_size;
4620}
4621
4622static int
4623bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4624{
4625 struct bnx2 *bp = dev->priv;
4626
4627 if ((ering->rx_pending > MAX_RX_DESC_CNT) ||
4628 (ering->tx_pending > MAX_TX_DESC_CNT) ||
4629 (ering->tx_pending <= MAX_SKB_FRAGS)) {
4630
4631 return -EINVAL;
4632 }
4633 bp->rx_ring_size = ering->rx_pending;
4634 bp->tx_ring_size = ering->tx_pending;
4635
4636 if (netif_running(bp->dev)) {
4637 bnx2_netif_stop(bp);
4638 bnx2_init_nic(bp);
4639 bnx2_netif_start(bp);
4640 }
4641
4642 return 0;
4643}
4644
4645static void
4646bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4647{
4648 struct bnx2 *bp = dev->priv;
4649
4650 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
4651 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
4652 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
4653}
4654
4655static int
4656bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4657{
4658 struct bnx2 *bp = dev->priv;
4659
4660 bp->req_flow_ctrl = 0;
4661 if (epause->rx_pause)
4662 bp->req_flow_ctrl |= FLOW_CTRL_RX;
4663 if (epause->tx_pause)
4664 bp->req_flow_ctrl |= FLOW_CTRL_TX;
4665
4666 if (epause->autoneg) {
4667 bp->autoneg |= AUTONEG_FLOW_CTRL;
4668 }
4669 else {
4670 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
4671 }
4672
4673 spin_lock_irq(&bp->phy_lock);
4674
4675 bnx2_setup_phy(bp);
4676
4677 spin_unlock_irq(&bp->phy_lock);
4678
4679 return 0;
4680}
4681
4682static u32
4683bnx2_get_rx_csum(struct net_device *dev)
4684{
4685 struct bnx2 *bp = dev->priv;
4686
4687 return bp->rx_csum;
4688}
4689
4690static int
4691bnx2_set_rx_csum(struct net_device *dev, u32 data)
4692{
4693 struct bnx2 *bp = dev->priv;
4694
4695 bp->rx_csum = data;
4696 return 0;
4697}
4698
4699#define BNX2_NUM_STATS 45
4700
4701struct {
4702 char string[ETH_GSTRING_LEN];
4703} bnx2_stats_str_arr[BNX2_NUM_STATS] = {
4704 { "rx_bytes" },
4705 { "rx_error_bytes" },
4706 { "tx_bytes" },
4707 { "tx_error_bytes" },
4708 { "rx_ucast_packets" },
4709 { "rx_mcast_packets" },
4710 { "rx_bcast_packets" },
4711 { "tx_ucast_packets" },
4712 { "tx_mcast_packets" },
4713 { "tx_bcast_packets" },
4714 { "tx_mac_errors" },
4715 { "tx_carrier_errors" },
4716 { "rx_crc_errors" },
4717 { "rx_align_errors" },
4718 { "tx_single_collisions" },
4719 { "tx_multi_collisions" },
4720 { "tx_deferred" },
4721 { "tx_excess_collisions" },
4722 { "tx_late_collisions" },
4723 { "tx_total_collisions" },
4724 { "rx_fragments" },
4725 { "rx_jabbers" },
4726 { "rx_undersize_packets" },
4727 { "rx_oversize_packets" },
4728 { "rx_64_byte_packets" },
4729 { "rx_65_to_127_byte_packets" },
4730 { "rx_128_to_255_byte_packets" },
4731 { "rx_256_to_511_byte_packets" },
4732 { "rx_512_to_1023_byte_packets" },
4733 { "rx_1024_to_1522_byte_packets" },
4734 { "rx_1523_to_9022_byte_packets" },
4735 { "tx_64_byte_packets" },
4736 { "tx_65_to_127_byte_packets" },
4737 { "tx_128_to_255_byte_packets" },
4738 { "tx_256_to_511_byte_packets" },
4739 { "tx_512_to_1023_byte_packets" },
4740 { "tx_1024_to_1522_byte_packets" },
4741 { "tx_1523_to_9022_byte_packets" },
4742 { "rx_xon_frames" },
4743 { "rx_xoff_frames" },
4744 { "tx_xon_frames" },
4745 { "tx_xoff_frames" },
4746 { "rx_mac_ctrl_frames" },
4747 { "rx_filtered_packets" },
4748 { "rx_discards" },
4749};
4750
4751#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
4752
4753unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
4754 STATS_OFFSET32(stat_IfHCInOctets_hi),
4755 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
4756 STATS_OFFSET32(stat_IfHCOutOctets_hi),
4757 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
4758 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
4759 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
4760 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
4761 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
4762 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
4763 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
4764 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
4765 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
4766 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
4767 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
4768 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
4769 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
4770 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
4771 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
4772 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
4773 STATS_OFFSET32(stat_EtherStatsCollisions),
4774 STATS_OFFSET32(stat_EtherStatsFragments),
4775 STATS_OFFSET32(stat_EtherStatsJabbers),
4776 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
4777 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
4778 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
4779 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
4780 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
4781 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
4782 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
4783 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
4784 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
4785 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
4786 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
4787 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
4788 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
4789 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
4790 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
4791 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
4792 STATS_OFFSET32(stat_XonPauseFramesReceived),
4793 STATS_OFFSET32(stat_XoffPauseFramesReceived),
4794 STATS_OFFSET32(stat_OutXonSent),
4795 STATS_OFFSET32(stat_OutXoffSent),
4796 STATS_OFFSET32(stat_MacControlFramesReceived),
4797 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
4798 STATS_OFFSET32(stat_IfInMBUFDiscards),
4799};
4800
4801/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
4802 * skipped because of errata.
4803 */
4804u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
4805 8,0,8,8,8,8,8,8,8,8,
4806 4,0,4,4,4,4,4,4,4,4,
4807 4,4,4,4,4,4,4,4,4,4,
4808 4,4,4,4,4,4,4,4,4,4,
4809 4,4,4,4,4,
4810};
4811
4812#define BNX2_NUM_TESTS 6
4813
4814struct {
4815 char string[ETH_GSTRING_LEN];
4816} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
4817 { "register_test (offline)" },
4818 { "memory_test (offline)" },
4819 { "loopback_test (offline)" },
4820 { "nvram_test (online)" },
4821 { "interrupt_test (online)" },
4822 { "link_test (online)" },
4823};
4824
4825static int
4826bnx2_self_test_count(struct net_device *dev)
4827{
4828 return BNX2_NUM_TESTS;
4829}
4830
4831static void
4832bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
4833{
4834 struct bnx2 *bp = dev->priv;
4835
4836 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
4837 if (etest->flags & ETH_TEST_FL_OFFLINE) {
4838 bnx2_netif_stop(bp);
4839 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
4840 bnx2_free_skbs(bp);
4841
4842 if (bnx2_test_registers(bp) != 0) {
4843 buf[0] = 1;
4844 etest->flags |= ETH_TEST_FL_FAILED;
4845 }
4846 if (bnx2_test_memory(bp) != 0) {
4847 buf[1] = 1;
4848 etest->flags |= ETH_TEST_FL_FAILED;
4849 }
4850 if (bnx2_test_loopback(bp) != 0) {
4851 buf[2] = 1;
4852 etest->flags |= ETH_TEST_FL_FAILED;
4853 }
4854
4855 if (!netif_running(bp->dev)) {
4856 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
4857 }
4858 else {
4859 bnx2_init_nic(bp);
4860 bnx2_netif_start(bp);
4861 }
4862
4863 /* wait for link up */
4864 msleep_interruptible(3000);
4865 if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG))
4866 msleep_interruptible(4000);
4867 }
4868
4869 if (bnx2_test_nvram(bp) != 0) {
4870 buf[3] = 1;
4871 etest->flags |= ETH_TEST_FL_FAILED;
4872 }
4873 if (bnx2_test_intr(bp) != 0) {
4874 buf[4] = 1;
4875 etest->flags |= ETH_TEST_FL_FAILED;
4876 }
4877
4878 if (bnx2_test_link(bp) != 0) {
4879 buf[5] = 1;
4880 etest->flags |= ETH_TEST_FL_FAILED;
4881
4882 }
4883}
4884
4885static void
4886bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
4887{
4888 switch (stringset) {
4889 case ETH_SS_STATS:
4890 memcpy(buf, bnx2_stats_str_arr,
4891 sizeof(bnx2_stats_str_arr));
4892 break;
4893 case ETH_SS_TEST:
4894 memcpy(buf, bnx2_tests_str_arr,
4895 sizeof(bnx2_tests_str_arr));
4896 break;
4897 }
4898}
4899
4900static int
4901bnx2_get_stats_count(struct net_device *dev)
4902{
4903 return BNX2_NUM_STATS;
4904}
4905
4906static void
4907bnx2_get_ethtool_stats(struct net_device *dev,
4908 struct ethtool_stats *stats, u64 *buf)
4909{
4910 struct bnx2 *bp = dev->priv;
4911 int i;
4912 u32 *hw_stats = (u32 *) bp->stats_blk;
4913 u8 *stats_len_arr = 0;
4914
4915 if (hw_stats == NULL) {
4916 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
4917 return;
4918 }
4919
4920 if (CHIP_NUM(bp) == CHIP_NUM_5706)
4921 stats_len_arr = bnx2_5706_stats_len_arr;
4922
4923 for (i = 0; i < BNX2_NUM_STATS; i++) {
4924 if (stats_len_arr[i] == 0) {
4925 /* skip this counter */
4926 buf[i] = 0;
4927 continue;
4928 }
4929 if (stats_len_arr[i] == 4) {
4930 /* 4-byte counter */
4931 buf[i] = (u64)
4932 *(hw_stats + bnx2_stats_offset_arr[i]);
4933 continue;
4934 }
4935 /* 8-byte counter */
4936 buf[i] = (((u64) *(hw_stats +
4937 bnx2_stats_offset_arr[i])) << 32) +
4938 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
4939 }
4940}
4941
4942static int
4943bnx2_phys_id(struct net_device *dev, u32 data)
4944{
4945 struct bnx2 *bp = dev->priv;
4946 int i;
4947 u32 save;
4948
4949 if (data == 0)
4950 data = 2;
4951
4952 save = REG_RD(bp, BNX2_MISC_CFG);
4953 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
4954
4955 for (i = 0; i < (data * 2); i++) {
4956 if ((i % 2) == 0) {
4957 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
4958 }
4959 else {
4960 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
4961 BNX2_EMAC_LED_1000MB_OVERRIDE |
4962 BNX2_EMAC_LED_100MB_OVERRIDE |
4963 BNX2_EMAC_LED_10MB_OVERRIDE |
4964 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
4965 BNX2_EMAC_LED_TRAFFIC);
4966 }
4967 msleep_interruptible(500);
4968 if (signal_pending(current))
4969 break;
4970 }
4971 REG_WR(bp, BNX2_EMAC_LED, 0);
4972 REG_WR(bp, BNX2_MISC_CFG, save);
4973 return 0;
4974}
4975
4976static struct ethtool_ops bnx2_ethtool_ops = {
4977 .get_settings = bnx2_get_settings,
4978 .set_settings = bnx2_set_settings,
4979 .get_drvinfo = bnx2_get_drvinfo,
4980 .get_wol = bnx2_get_wol,
4981 .set_wol = bnx2_set_wol,
4982 .nway_reset = bnx2_nway_reset,
4983 .get_link = ethtool_op_get_link,
4984 .get_eeprom_len = bnx2_get_eeprom_len,
4985 .get_eeprom = bnx2_get_eeprom,
4986 .set_eeprom = bnx2_set_eeprom,
4987 .get_coalesce = bnx2_get_coalesce,
4988 .set_coalesce = bnx2_set_coalesce,
4989 .get_ringparam = bnx2_get_ringparam,
4990 .set_ringparam = bnx2_set_ringparam,
4991 .get_pauseparam = bnx2_get_pauseparam,
4992 .set_pauseparam = bnx2_set_pauseparam,
4993 .get_rx_csum = bnx2_get_rx_csum,
4994 .set_rx_csum = bnx2_set_rx_csum,
4995 .get_tx_csum = ethtool_op_get_tx_csum,
4996 .set_tx_csum = ethtool_op_set_tx_csum,
4997 .get_sg = ethtool_op_get_sg,
4998 .set_sg = ethtool_op_set_sg,
4999#ifdef BCM_TSO
5000 .get_tso = ethtool_op_get_tso,
5001 .set_tso = ethtool_op_set_tso,
5002#endif
5003 .self_test_count = bnx2_self_test_count,
5004 .self_test = bnx2_self_test,
5005 .get_strings = bnx2_get_strings,
5006 .phys_id = bnx2_phys_id,
5007 .get_stats_count = bnx2_get_stats_count,
5008 .get_ethtool_stats = bnx2_get_ethtool_stats,
5009};
5010
5011/* Called with rtnl_lock */
5012static int
5013bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5014{
5015 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&ifr->ifr_data;
5016 struct bnx2 *bp = dev->priv;
5017 int err;
5018
5019 switch(cmd) {
5020 case SIOCGMIIPHY:
5021 data->phy_id = bp->phy_addr;
5022
5023 /* fallthru */
5024 case SIOCGMIIREG: {
5025 u32 mii_regval;
5026
5027 spin_lock_irq(&bp->phy_lock);
5028 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
5029 spin_unlock_irq(&bp->phy_lock);
5030
5031 data->val_out = mii_regval;
5032
5033 return err;
5034 }
5035
5036 case SIOCSMIIREG:
5037 if (!capable(CAP_NET_ADMIN))
5038 return -EPERM;
5039
5040 spin_lock_irq(&bp->phy_lock);
5041 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
5042 spin_unlock_irq(&bp->phy_lock);
5043
5044 return err;
5045
5046 default:
5047 /* do nothing */
5048 break;
5049 }
5050 return -EOPNOTSUPP;
5051}
5052
5053/* Called with rtnl_lock */
5054static int
5055bnx2_change_mac_addr(struct net_device *dev, void *p)
5056{
5057 struct sockaddr *addr = p;
5058 struct bnx2 *bp = dev->priv;
5059
5060 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5061 if (netif_running(dev))
5062 bnx2_set_mac_addr(bp);
5063
5064 return 0;
5065}
5066
5067/* Called with rtnl_lock */
5068static int
5069bnx2_change_mtu(struct net_device *dev, int new_mtu)
5070{
5071 struct bnx2 *bp = dev->priv;
5072
5073 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
5074 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
5075 return -EINVAL;
5076
5077 dev->mtu = new_mtu;
5078 if (netif_running(dev)) {
5079 bnx2_netif_stop(bp);
5080
5081 bnx2_init_nic(bp);
5082
5083 bnx2_netif_start(bp);
5084 }
5085 return 0;
5086}
5087
5088#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5089static void
5090poll_bnx2(struct net_device *dev)
5091{
5092 struct bnx2 *bp = dev->priv;
5093
5094 disable_irq(bp->pdev->irq);
5095 bnx2_interrupt(bp->pdev->irq, dev, NULL);
5096 enable_irq(bp->pdev->irq);
5097}
5098#endif
5099
5100static int __devinit
5101bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5102{
5103 struct bnx2 *bp;
5104 unsigned long mem_len;
5105 int rc;
5106 u32 reg;
5107
5108 SET_MODULE_OWNER(dev);
5109 SET_NETDEV_DEV(dev, &pdev->dev);
5110 bp = dev->priv;
5111
5112 bp->flags = 0;
5113 bp->phy_flags = 0;
5114
5115 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5116 rc = pci_enable_device(pdev);
5117 if (rc) {
5118 printk(KERN_ERR PFX "Cannot enable PCI device, aborting.");
5119 goto err_out;
5120 }
5121
5122 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5123 printk(KERN_ERR PFX "Cannot find PCI device base address, "
5124 "aborting.\n");
5125 rc = -ENODEV;
5126 goto err_out_disable;
5127 }
5128
5129 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5130 if (rc) {
5131 printk(KERN_ERR PFX "Cannot obtain PCI resources, aborting.\n");
5132 goto err_out_disable;
5133 }
5134
5135 pci_set_master(pdev);
5136
5137 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
5138 if (bp->pm_cap == 0) {
5139 printk(KERN_ERR PFX "Cannot find power management capability, "
5140 "aborting.\n");
5141 rc = -EIO;
5142 goto err_out_release;
5143 }
5144
5145 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
5146 if (bp->pcix_cap == 0) {
5147 printk(KERN_ERR PFX "Cannot find PCIX capability, aborting.\n");
5148 rc = -EIO;
5149 goto err_out_release;
5150 }
5151
5152 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
5153 bp->flags |= USING_DAC_FLAG;
5154 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
5155 printk(KERN_ERR PFX "pci_set_consistent_dma_mask "
5156 "failed, aborting.\n");
5157 rc = -EIO;
5158 goto err_out_release;
5159 }
5160 }
5161 else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
5162 printk(KERN_ERR PFX "System does not support DMA, aborting.\n");
5163 rc = -EIO;
5164 goto err_out_release;
5165 }
5166
5167 bp->dev = dev;
5168 bp->pdev = pdev;
5169
5170 spin_lock_init(&bp->phy_lock);
5171 spin_lock_init(&bp->tx_lock);
5172 INIT_WORK(&bp->reset_task, bnx2_reset_task, bp);
5173
5174 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
5175 mem_len = MB_GET_CID_ADDR(17);
5176 dev->mem_end = dev->mem_start + mem_len;
5177 dev->irq = pdev->irq;
5178
5179 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
5180
5181 if (!bp->regview) {
5182 printk(KERN_ERR PFX "Cannot map register space, aborting.\n");
5183 rc = -ENOMEM;
5184 goto err_out_release;
5185 }
5186
5187 /* Configure byte swap and enable write to the reg_window registers.
5188 * Rely on CPU to do target byte swapping on big endian systems
5189 * The chip's target access swapping will not swap all accesses
5190 */
5191 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
5192 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5193 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
5194
5195 bnx2_set_power_state(bp, 0);
5196
5197 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
5198
5199 bp->phy_addr = 1;
5200
5201 /* Get bus information. */
5202 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
5203 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
5204 u32 clkreg;
5205
5206 bp->flags |= PCIX_FLAG;
5207
5208 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
5209
5210 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
5211 switch (clkreg) {
5212 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
5213 bp->bus_speed_mhz = 133;
5214 break;
5215
5216 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
5217 bp->bus_speed_mhz = 100;
5218 break;
5219
5220 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
5221 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
5222 bp->bus_speed_mhz = 66;
5223 break;
5224
5225 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
5226 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
5227 bp->bus_speed_mhz = 50;
5228 break;
5229
5230 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
5231 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
5232 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
5233 bp->bus_speed_mhz = 33;
5234 break;
5235 }
5236 }
5237 else {
5238 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
5239 bp->bus_speed_mhz = 66;
5240 else
5241 bp->bus_speed_mhz = 33;
5242 }
5243
5244 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
5245 bp->flags |= PCI_32BIT_FLAG;
5246
5247 /* 5706A0 may falsely detect SERR and PERR. */
5248 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5249 reg = REG_RD(bp, PCI_COMMAND);
5250 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
5251 REG_WR(bp, PCI_COMMAND, reg);
5252 }
5253 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
5254 !(bp->flags & PCIX_FLAG)) {
5255
5256 printk(KERN_ERR PFX "5706 A1 can only be used in a PCIX bus, "
5257 "aborting.\n");
5258 goto err_out_unmap;
5259 }
5260
5261 bnx2_init_nvram(bp);
5262
5263 /* Get the permanent MAC address. First we need to make sure the
5264 * firmware is actually running.
5265 */
5266 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DEV_INFO_SIGNATURE);
5267
5268 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5269 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
5270 printk(KERN_ERR PFX "Firmware not running, aborting.\n");
5271 rc = -ENODEV;
5272 goto err_out_unmap;
5273 }
5274
5275 bp->fw_ver = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
5276 BNX2_DEV_INFO_BC_REV);
5277
5278 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_UPPER);
5279 bp->mac_addr[0] = (u8) (reg >> 8);
5280 bp->mac_addr[1] = (u8) reg;
5281
5282 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_LOWER);
5283 bp->mac_addr[2] = (u8) (reg >> 24);
5284 bp->mac_addr[3] = (u8) (reg >> 16);
5285 bp->mac_addr[4] = (u8) (reg >> 8);
5286 bp->mac_addr[5] = (u8) reg;
5287
5288 bp->tx_ring_size = MAX_TX_DESC_CNT;
5289 bp->rx_ring_size = 100;
5290
5291 bp->rx_csum = 1;
5292
5293 bp->rx_offset = sizeof(struct l2_fhdr) + 2;
5294
5295 bp->tx_quick_cons_trip_int = 20;
5296 bp->tx_quick_cons_trip = 20;
5297 bp->tx_ticks_int = 80;
5298 bp->tx_ticks = 80;
5299
5300 bp->rx_quick_cons_trip_int = 6;
5301 bp->rx_quick_cons_trip = 6;
5302 bp->rx_ticks_int = 18;
5303 bp->rx_ticks = 18;
5304
5305 bp->stats_ticks = 1000000 & 0xffff00;
5306
5307 bp->timer_interval = HZ;
5308
5309 /* Disable WOL support if we are running on a SERDES chip. */
5310 if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
5311 bp->phy_flags |= PHY_SERDES_FLAG;
5312 bp->flags |= NO_WOL_FLAG;
5313 }
5314
5315 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5316 bp->tx_quick_cons_trip_int =
5317 bp->tx_quick_cons_trip;
5318 bp->tx_ticks_int = bp->tx_ticks;
5319 bp->rx_quick_cons_trip_int =
5320 bp->rx_quick_cons_trip;
5321 bp->rx_ticks_int = bp->rx_ticks;
5322 bp->comp_prod_trip_int = bp->comp_prod_trip;
5323 bp->com_ticks_int = bp->com_ticks;
5324 bp->cmd_ticks_int = bp->cmd_ticks;
5325 }
5326
5327 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
5328 bp->req_line_speed = 0;
5329 if (bp->phy_flags & PHY_SERDES_FLAG) {
5330 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
5331 }
5332 else {
5333 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
5334 }
5335
5336 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
5337
5338 return 0;
5339
5340err_out_unmap:
5341 if (bp->regview) {
5342 iounmap(bp->regview);
5343 }
5344
5345err_out_release:
5346 pci_release_regions(pdev);
5347
5348err_out_disable:
5349 pci_disable_device(pdev);
5350 pci_set_drvdata(pdev, NULL);
5351
5352err_out:
5353 return rc;
5354}
5355
5356static int __devinit
5357bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5358{
5359 static int version_printed = 0;
5360 struct net_device *dev = NULL;
5361 struct bnx2 *bp;
5362 int rc, i;
5363
5364 if (version_printed++ == 0)
5365 printk(KERN_INFO "%s", version);
5366
5367 /* dev zeroed in init_etherdev */
5368 dev = alloc_etherdev(sizeof(*bp));
5369
5370 if (!dev)
5371 return -ENOMEM;
5372
5373 rc = bnx2_init_board(pdev, dev);
5374 if (rc < 0) {
5375 free_netdev(dev);
5376 return rc;
5377 }
5378
5379 dev->open = bnx2_open;
5380 dev->hard_start_xmit = bnx2_start_xmit;
5381 dev->stop = bnx2_close;
5382 dev->get_stats = bnx2_get_stats;
5383 dev->set_multicast_list = bnx2_set_rx_mode;
5384 dev->do_ioctl = bnx2_ioctl;
5385 dev->set_mac_address = bnx2_change_mac_addr;
5386 dev->change_mtu = bnx2_change_mtu;
5387 dev->tx_timeout = bnx2_tx_timeout;
5388 dev->watchdog_timeo = TX_TIMEOUT;
5389#ifdef BCM_VLAN
5390 dev->vlan_rx_register = bnx2_vlan_rx_register;
5391 dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid;
5392#endif
5393 dev->poll = bnx2_poll;
5394 dev->ethtool_ops = &bnx2_ethtool_ops;
5395 dev->weight = 64;
5396
5397 bp = dev->priv;
5398
5399#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5400 dev->poll_controller = poll_bnx2;
5401#endif
5402
5403 if ((rc = register_netdev(dev))) {
5404 printk(KERN_ERR PFX "Cannot register net device\n");
5405 if (bp->regview)
5406 iounmap(bp->regview);
5407 pci_release_regions(pdev);
5408 pci_disable_device(pdev);
5409 pci_set_drvdata(pdev, NULL);
5410 free_netdev(dev);
5411 return rc;
5412 }
5413
5414 pci_set_drvdata(pdev, dev);
5415
5416 memcpy(dev->dev_addr, bp->mac_addr, 6);
5417 bp->name = board_info[ent->driver_data].name,
5418 printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, "
5419 "IRQ %d, ",
5420 dev->name,
5421 bp->name,
5422 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
5423 ((CHIP_ID(bp) & 0x0ff0) >> 4),
5424 ((bp->flags & PCIX_FLAG) ? "-X" : ""),
5425 ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
5426 bp->bus_speed_mhz,
5427 dev->base_addr,
5428 bp->pdev->irq);
5429
5430 printk("node addr ");
5431 for (i = 0; i < 6; i++)
5432 printk("%2.2x", dev->dev_addr[i]);
5433 printk("\n");
5434
5435 dev->features |= NETIF_F_SG;
5436 if (bp->flags & USING_DAC_FLAG)
5437 dev->features |= NETIF_F_HIGHDMA;
5438 dev->features |= NETIF_F_IP_CSUM;
5439#ifdef BCM_VLAN
5440 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
5441#endif
5442#ifdef BCM_TSO
5443 dev->features |= NETIF_F_TSO;
5444#endif
5445
5446 netif_carrier_off(bp->dev);
5447
5448 return 0;
5449}
5450
5451static void __devexit
5452bnx2_remove_one(struct pci_dev *pdev)
5453{
5454 struct net_device *dev = pci_get_drvdata(pdev);
5455 struct bnx2 *bp = dev->priv;
5456
5457 unregister_netdev(dev);
5458
5459 if (bp->regview)
5460 iounmap(bp->regview);
5461
5462 free_netdev(dev);
5463 pci_release_regions(pdev);
5464 pci_disable_device(pdev);
5465 pci_set_drvdata(pdev, NULL);
5466}
5467
5468static int
5469bnx2_suspend(struct pci_dev *pdev, u32 state)
5470{
5471 struct net_device *dev = pci_get_drvdata(pdev);
5472 struct bnx2 *bp = dev->priv;
5473 u32 reset_code;
5474
5475 if (!netif_running(dev))
5476 return 0;
5477
5478 bnx2_netif_stop(bp);
5479 netif_device_detach(dev);
5480 del_timer_sync(&bp->timer);
5481 if (bp->wol)
5482 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5483 else
5484 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5485 bnx2_reset_chip(bp, reset_code);
5486 bnx2_free_skbs(bp);
5487 bnx2_set_power_state(bp, state);
5488 return 0;
5489}
5490
5491static int
5492bnx2_resume(struct pci_dev *pdev)
5493{
5494 struct net_device *dev = pci_get_drvdata(pdev);
5495 struct bnx2 *bp = dev->priv;
5496
5497 if (!netif_running(dev))
5498 return 0;
5499
5500 bnx2_set_power_state(bp, 0);
5501 netif_device_attach(dev);
5502 bnx2_init_nic(bp);
5503 bnx2_netif_start(bp);
5504 return 0;
5505}
5506
5507static struct pci_driver bnx2_pci_driver = {
5508 name: DRV_MODULE_NAME,
5509 id_table: bnx2_pci_tbl,
5510 probe: bnx2_init_one,
5511 remove: __devexit_p(bnx2_remove_one),
5512 suspend: bnx2_suspend,
5513 resume: bnx2_resume,
5514};
5515
5516static int __init bnx2_init(void)
5517{
5518 return pci_module_init(&bnx2_pci_driver);
5519}
5520
5521static void __exit bnx2_cleanup(void)
5522{
5523 pci_unregister_driver(&bnx2_pci_driver);
5524}
5525
5526module_init(bnx2_init);
5527module_exit(bnx2_cleanup);
5528
5529
5530
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
new file mode 100644
index 000000000000..8214a2853d0d
--- /dev/null
+++ b/drivers/net/bnx2.h
@@ -0,0 +1,4352 @@
1/* bnx2.h: Broadcom NX2 network driver.
2 *
3 * Copyright (c) 2004, 2005 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
12
13#ifndef BNX2_H
14#define BNX2_H
15
16#include <linux/config.h>
17
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20
21#include <linux/kernel.h>
22#include <linux/timer.h>
23#include <linux/errno.h>
24#include <linux/ioport.h>
25#include <linux/slab.h>
26#include <linux/interrupt.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
31#include <linux/skbuff.h>
32#include <linux/dma-mapping.h>
33#include <asm/bitops.h>
34#include <asm/io.h>
35#include <asm/irq.h>
36#include <linux/delay.h>
37#include <asm/byteorder.h>
38#include <linux/time.h>
39#include <linux/ethtool.h>
40#include <linux/mii.h>
41#ifdef NETIF_F_HW_VLAN_TX
42#include <linux/if_vlan.h>
43#define BCM_VLAN 1
44#endif
45#ifdef NETIF_F_TSO
46#include <net/ip.h>
47#include <net/tcp.h>
48#include <net/checksum.h>
49#define BCM_TSO 1
50#endif
51#include <linux/workqueue.h>
52#include <linux/crc32.h>
53
54/* Hardware data structures and register definitions automatically
55 * generated from RTL code. Do not modify.
56 */
57
58/*
59 * tx_bd definition
60 */
61struct tx_bd {
62 u32 tx_bd_haddr_hi;
63 u32 tx_bd_haddr_lo;
64 u32 tx_bd_mss_nbytes;
65 u32 tx_bd_vlan_tag_flags;
66 #define TX_BD_FLAGS_CONN_FAULT (1<<0)
67 #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1)
68 #define TX_BD_FLAGS_IP_CKSUM (1<<2)
69 #define TX_BD_FLAGS_VLAN_TAG (1<<3)
70 #define TX_BD_FLAGS_COAL_NOW (1<<4)
71 #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5)
72 #define TX_BD_FLAGS_END (1<<6)
73 #define TX_BD_FLAGS_START (1<<7)
74 #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8)
75 #define TX_BD_FLAGS_SW_FLAGS (1<<13)
76 #define TX_BD_FLAGS_SW_SNAP (1<<14)
77 #define TX_BD_FLAGS_SW_LSO (1<<15)
78
79};
80
81
82/*
83 * rx_bd definition
84 */
85struct rx_bd {
86 u32 rx_bd_haddr_hi;
87 u32 rx_bd_haddr_lo;
88 u32 rx_bd_len;
89 u32 rx_bd_flags;
90 #define RX_BD_FLAGS_NOPUSH (1<<0)
91 #define RX_BD_FLAGS_DUMMY (1<<1)
92 #define RX_BD_FLAGS_END (1<<2)
93 #define RX_BD_FLAGS_START (1<<3)
94
95};
96
97
98/*
99 * status_block definition
100 */
101struct status_block {
102 u32 status_attn_bits;
103 #define STATUS_ATTN_BITS_LINK_STATE (1L<<0)
104 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1)
105 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2)
106 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3)
107 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4)
108 #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5)
109 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6)
110 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7)
111 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8)
112 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9)
113 #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10)
114 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11)
115 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12)
116 #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13)
117 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14)
118 #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15)
119 #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16)
120 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17)
121 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18)
122 #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19)
123 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20)
124 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21)
125 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22)
126 #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23)
127 #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24)
128 #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25)
129 #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26)
130 #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27)
131 #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31)
132
133 u32 status_attn_bits_ack;
134#if defined(__BIG_ENDIAN)
135 u16 status_tx_quick_consumer_index0;
136 u16 status_tx_quick_consumer_index1;
137 u16 status_tx_quick_consumer_index2;
138 u16 status_tx_quick_consumer_index3;
139 u16 status_rx_quick_consumer_index0;
140 u16 status_rx_quick_consumer_index1;
141 u16 status_rx_quick_consumer_index2;
142 u16 status_rx_quick_consumer_index3;
143 u16 status_rx_quick_consumer_index4;
144 u16 status_rx_quick_consumer_index5;
145 u16 status_rx_quick_consumer_index6;
146 u16 status_rx_quick_consumer_index7;
147 u16 status_rx_quick_consumer_index8;
148 u16 status_rx_quick_consumer_index9;
149 u16 status_rx_quick_consumer_index10;
150 u16 status_rx_quick_consumer_index11;
151 u16 status_rx_quick_consumer_index12;
152 u16 status_rx_quick_consumer_index13;
153 u16 status_rx_quick_consumer_index14;
154 u16 status_rx_quick_consumer_index15;
155 u16 status_completion_producer_index;
156 u16 status_cmd_consumer_index;
157 u16 status_idx;
158 u16 status_unused;
159#elif defined(__LITTLE_ENDIAN)
160 u16 status_tx_quick_consumer_index1;
161 u16 status_tx_quick_consumer_index0;
162 u16 status_tx_quick_consumer_index3;
163 u16 status_tx_quick_consumer_index2;
164 u16 status_rx_quick_consumer_index1;
165 u16 status_rx_quick_consumer_index0;
166 u16 status_rx_quick_consumer_index3;
167 u16 status_rx_quick_consumer_index2;
168 u16 status_rx_quick_consumer_index5;
169 u16 status_rx_quick_consumer_index4;
170 u16 status_rx_quick_consumer_index7;
171 u16 status_rx_quick_consumer_index6;
172 u16 status_rx_quick_consumer_index9;
173 u16 status_rx_quick_consumer_index8;
174 u16 status_rx_quick_consumer_index11;
175 u16 status_rx_quick_consumer_index10;
176 u16 status_rx_quick_consumer_index13;
177 u16 status_rx_quick_consumer_index12;
178 u16 status_rx_quick_consumer_index15;
179 u16 status_rx_quick_consumer_index14;
180 u16 status_cmd_consumer_index;
181 u16 status_completion_producer_index;
182 u16 status_unused;
183 u16 status_idx;
184#endif
185};
186
187
188/*
189 * statistics_block definition
190 */
191struct statistics_block {
192 u32 stat_IfHCInOctets_hi;
193 u32 stat_IfHCInOctets_lo;
194 u32 stat_IfHCInBadOctets_hi;
195 u32 stat_IfHCInBadOctets_lo;
196 u32 stat_IfHCOutOctets_hi;
197 u32 stat_IfHCOutOctets_lo;
198 u32 stat_IfHCOutBadOctets_hi;
199 u32 stat_IfHCOutBadOctets_lo;
200 u32 stat_IfHCInUcastPkts_hi;
201 u32 stat_IfHCInUcastPkts_lo;
202 u32 stat_IfHCInMulticastPkts_hi;
203 u32 stat_IfHCInMulticastPkts_lo;
204 u32 stat_IfHCInBroadcastPkts_hi;
205 u32 stat_IfHCInBroadcastPkts_lo;
206 u32 stat_IfHCOutUcastPkts_hi;
207 u32 stat_IfHCOutUcastPkts_lo;
208 u32 stat_IfHCOutMulticastPkts_hi;
209 u32 stat_IfHCOutMulticastPkts_lo;
210 u32 stat_IfHCOutBroadcastPkts_hi;
211 u32 stat_IfHCOutBroadcastPkts_lo;
212 u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
213 u32 stat_Dot3StatsCarrierSenseErrors;
214 u32 stat_Dot3StatsFCSErrors;
215 u32 stat_Dot3StatsAlignmentErrors;
216 u32 stat_Dot3StatsSingleCollisionFrames;
217 u32 stat_Dot3StatsMultipleCollisionFrames;
218 u32 stat_Dot3StatsDeferredTransmissions;
219 u32 stat_Dot3StatsExcessiveCollisions;
220 u32 stat_Dot3StatsLateCollisions;
221 u32 stat_EtherStatsCollisions;
222 u32 stat_EtherStatsFragments;
223 u32 stat_EtherStatsJabbers;
224 u32 stat_EtherStatsUndersizePkts;
225 u32 stat_EtherStatsOverrsizePkts;
226 u32 stat_EtherStatsPktsRx64Octets;
227 u32 stat_EtherStatsPktsRx65Octetsto127Octets;
228 u32 stat_EtherStatsPktsRx128Octetsto255Octets;
229 u32 stat_EtherStatsPktsRx256Octetsto511Octets;
230 u32 stat_EtherStatsPktsRx512Octetsto1023Octets;
231 u32 stat_EtherStatsPktsRx1024Octetsto1522Octets;
232 u32 stat_EtherStatsPktsRx1523Octetsto9022Octets;
233 u32 stat_EtherStatsPktsTx64Octets;
234 u32 stat_EtherStatsPktsTx65Octetsto127Octets;
235 u32 stat_EtherStatsPktsTx128Octetsto255Octets;
236 u32 stat_EtherStatsPktsTx256Octetsto511Octets;
237 u32 stat_EtherStatsPktsTx512Octetsto1023Octets;
238 u32 stat_EtherStatsPktsTx1024Octetsto1522Octets;
239 u32 stat_EtherStatsPktsTx1523Octetsto9022Octets;
240 u32 stat_XonPauseFramesReceived;
241 u32 stat_XoffPauseFramesReceived;
242 u32 stat_OutXonSent;
243 u32 stat_OutXoffSent;
244 u32 stat_FlowControlDone;
245 u32 stat_MacControlFramesReceived;
246 u32 stat_XoffStateEntered;
247 u32 stat_IfInFramesL2FilterDiscards;
248 u32 stat_IfInRuleCheckerDiscards;
249 u32 stat_IfInFTQDiscards;
250 u32 stat_IfInMBUFDiscards;
251 u32 stat_IfInRuleCheckerP4Hit;
252 u32 stat_CatchupInRuleCheckerDiscards;
253 u32 stat_CatchupInFTQDiscards;
254 u32 stat_CatchupInMBUFDiscards;
255 u32 stat_CatchupInRuleCheckerP4Hit;
256 u32 stat_GenStat00;
257 u32 stat_GenStat01;
258 u32 stat_GenStat02;
259 u32 stat_GenStat03;
260 u32 stat_GenStat04;
261 u32 stat_GenStat05;
262 u32 stat_GenStat06;
263 u32 stat_GenStat07;
264 u32 stat_GenStat08;
265 u32 stat_GenStat09;
266 u32 stat_GenStat10;
267 u32 stat_GenStat11;
268 u32 stat_GenStat12;
269 u32 stat_GenStat13;
270 u32 stat_GenStat14;
271 u32 stat_GenStat15;
272};
273
274
275/*
276 * l2_fhdr definition
277 */
278struct l2_fhdr {
279#if defined(__BIG_ENDIAN)
280 u16 l2_fhdr_errors;
281 u16 l2_fhdr_status;
282#elif defined(__LITTLE_ENDIAN)
283 u16 l2_fhdr_status;
284 u16 l2_fhdr_errors;
285#endif
286 #define L2_FHDR_ERRORS_BAD_CRC (1<<1)
287 #define L2_FHDR_ERRORS_PHY_DECODE (1<<2)
288 #define L2_FHDR_ERRORS_ALIGNMENT (1<<3)
289 #define L2_FHDR_ERRORS_TOO_SHORT (1<<4)
290 #define L2_FHDR_ERRORS_GIANT_FRAME (1<<5)
291
292 #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0)
293 #define L2_FHDR_STATUS_RULE_P2 (1<<3)
294 #define L2_FHDR_STATUS_RULE_P3 (1<<4)
295 #define L2_FHDR_STATUS_RULE_P4 (1<<5)
296 #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6)
297 #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7)
298 #define L2_FHDR_STATUS_RSS_HASH (1<<8)
299 #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13)
300 #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14)
301 #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15)
302
303 u32 l2_fhdr_hash;
304#if defined(__BIG_ENDIAN)
305 u16 l2_fhdr_pkt_len;
306 u16 l2_fhdr_vlan_tag;
307 u16 l2_fhdr_ip_xsum;
308 u16 l2_fhdr_tcp_udp_xsum;
309#elif defined(__LITTLE_ENDIAN)
310 u16 l2_fhdr_vlan_tag;
311 u16 l2_fhdr_pkt_len;
312 u16 l2_fhdr_tcp_udp_xsum;
313 u16 l2_fhdr_ip_xsum;
314#endif
315};
316
317
318/*
319 * l2_context definition
320 */
321#define BNX2_L2CTX_TYPE 0x00000000
322#define BNX2_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16)
323#define BNX2_L2CTX_TYPE_TYPE (0xf<<28)
324#define BNX2_L2CTX_TYPE_TYPE_EMPTY (0<<28)
325#define BNX2_L2CTX_TYPE_TYPE_L2 (1<<28)
326
327#define BNX2_L2CTX_TX_HOST_BIDX 0x00000088
328#define BNX2_L2CTX_EST_NBD 0x00000088
329#define BNX2_L2CTX_CMD_TYPE 0x00000088
330#define BNX2_L2CTX_CMD_TYPE_TYPE (0xf<<24)
331#define BNX2_L2CTX_CMD_TYPE_TYPE_L2 (0<<24)
332#define BNX2_L2CTX_CMD_TYPE_TYPE_TCP (1<<24)
333
334#define BNX2_L2CTX_TX_HOST_BSEQ 0x00000090
335#define BNX2_L2CTX_TSCH_BSEQ 0x00000094
336#define BNX2_L2CTX_TBDR_BSEQ 0x00000098
337#define BNX2_L2CTX_TBDR_BOFF 0x0000009c
338#define BNX2_L2CTX_TBDR_BIDX 0x0000009c
339#define BNX2_L2CTX_TBDR_BHADDR_HI 0x000000a0
340#define BNX2_L2CTX_TBDR_BHADDR_LO 0x000000a4
341#define BNX2_L2CTX_TXP_BOFF 0x000000a8
342#define BNX2_L2CTX_TXP_BIDX 0x000000a8
343#define BNX2_L2CTX_TXP_BSEQ 0x000000ac
344
345
346/*
347 * l2_bd_chain_context definition
348 */
349#define BNX2_L2CTX_BD_PRE_READ 0x00000000
350#define BNX2_L2CTX_CTX_SIZE 0x00000000
351#define BNX2_L2CTX_CTX_TYPE 0x00000000
352#define BNX2_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16)
353#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28)
354#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28)
355#define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28)
356
357#define BNX2_L2CTX_HOST_BDIDX 0x00000004
358#define BNX2_L2CTX_HOST_BSEQ 0x00000008
359#define BNX2_L2CTX_NX_BSEQ 0x0000000c
360#define BNX2_L2CTX_NX_BDHADDR_HI 0x00000010
361#define BNX2_L2CTX_NX_BDHADDR_LO 0x00000014
362#define BNX2_L2CTX_NX_BDIDX 0x00000018
363
364
365/*
366 * pci_config_l definition
367 * offset: 0000
368 */
369#define BNX2_PCICFG_MISC_CONFIG 0x00000068
370#define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2)
371#define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3)
372#define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5)
373#define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6)
374#define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7)
375#define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8)
376#define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9)
377#define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16)
378#define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24)
379#define BNX2_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28)
380
381#define BNX2_PCICFG_MISC_STATUS 0x0000006c
382#define BNX2_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0)
383#define BNX2_PCICFG_MISC_STATUS_32BIT_DET (1L<<1)
384#define BNX2_PCICFG_MISC_STATUS_M66EN (1L<<2)
385#define BNX2_PCICFG_MISC_STATUS_PCIX_DET (1L<<3)
386#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED (0x3L<<4)
387#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4)
388#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4)
389#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4)
390#define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4)
391
392#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070
393#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
394#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
395#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
396#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
397#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
398#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
399#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
400#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
401#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
402#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
403#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
404#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
405#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
406#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
407#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
408#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
409#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
410#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11)
411#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
412#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
413#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
414#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
415#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
416#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
417#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
418#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17)
419#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18)
420#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19)
421#define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20)
422
423#define BNX2_PCICFG_REG_WINDOW_ADDRESS 0x00000078
424#define BNX2_PCICFG_REG_WINDOW 0x00000080
425#define BNX2_PCICFG_INT_ACK_CMD 0x00000084
426#define BNX2_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0)
427#define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16)
428#define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17)
429#define BNX2_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18)
430
431#define BNX2_PCICFG_STATUS_BIT_SET_CMD 0x00000088
432#define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c
433#define BNX2_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090
434#define BNX2_PCICFG_MAILBOX_QUEUE_DATA 0x00000094
435
436
437/*
438 * pci_reg definition
439 * offset: 0x400
440 */
441#define BNX2_PCI_GRC_WINDOW_ADDR 0x00000400
442#define BNX2_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE (0x3ffffL<<8)
443
444#define BNX2_PCI_CONFIG_1 0x00000404
445#define BNX2_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8)
446#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8)
447#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8)
448#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8)
449#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8)
450#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8)
451#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8)
452#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8)
453#define BNX2_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8)
454#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY (0x7L<<11)
455#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11)
456#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11)
457#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11)
458#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11)
459#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11)
460#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11)
461#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11)
462#define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11)
463
464#define BNX2_PCI_CONFIG_2 0x00000408
465#define BNX2_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
466#define BNX2_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
467#define BNX2_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
468#define BNX2_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
469#define BNX2_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
470#define BNX2_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
471#define BNX2_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
472#define BNX2_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
473#define BNX2_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
474#define BNX2_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
475#define BNX2_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
476#define BNX2_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
477#define BNX2_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
478#define BNX2_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
479#define BNX2_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
480#define BNX2_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
481#define BNX2_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
482#define BNX2_PCI_CONFIG_2_BAR1_64ENA (1L<<4)
483#define BNX2_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
484#define BNX2_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
485#define BNX2_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
486#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
487#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
488#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8)
489#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8)
490#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8)
491#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8)
492#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8)
493#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8)
494#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8)
495#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8)
496#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8)
497#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8)
498#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8)
499#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8)
500#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8)
501#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8)
502#define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8)
503#define BNX2_PCI_CONFIG_2_MAX_SPLIT_LIMIT (0x1fL<<16)
504#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT (0x3L<<21)
505#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21)
506#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21)
507#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21)
508#define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21)
509#define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23)
510#define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24)
511#define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25)
512
513#define BNX2_PCI_CONFIG_3 0x0000040c
514#define BNX2_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
515#define BNX2_PCI_CONFIG_3_FORCE_PME (1L<<24)
516#define BNX2_PCI_CONFIG_3_PME_STATUS (1L<<25)
517#define BNX2_PCI_CONFIG_3_PME_ENABLE (1L<<26)
518#define BNX2_PCI_CONFIG_3_PM_STATE (0x3L<<27)
519#define BNX2_PCI_CONFIG_3_VAUX_PRESET (1L<<30)
520#define BNX2_PCI_CONFIG_3_PCI_POWER (1L<<31)
521
522#define BNX2_PCI_PM_DATA_A 0x00000410
523#define BNX2_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0)
524#define BNX2_PCI_PM_DATA_A_PM_DATA_1_PRG (0xffL<<8)
525#define BNX2_PCI_PM_DATA_A_PM_DATA_2_PRG (0xffL<<16)
526#define BNX2_PCI_PM_DATA_A_PM_DATA_3_PRG (0xffL<<24)
527
528#define BNX2_PCI_PM_DATA_B 0x00000414
529#define BNX2_PCI_PM_DATA_B_PM_DATA_4_PRG (0xffL<<0)
530#define BNX2_PCI_PM_DATA_B_PM_DATA_5_PRG (0xffL<<8)
531#define BNX2_PCI_PM_DATA_B_PM_DATA_6_PRG (0xffL<<16)
532#define BNX2_PCI_PM_DATA_B_PM_DATA_7_PRG (0xffL<<24)
533
534#define BNX2_PCI_SWAP_DIAG0 0x00000418
535#define BNX2_PCI_SWAP_DIAG1 0x0000041c
536#define BNX2_PCI_EXP_ROM_ADDR 0x00000420
537#define BNX2_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2)
538#define BNX2_PCI_EXP_ROM_ADDR_REQ (1L<<31)
539
540#define BNX2_PCI_EXP_ROM_DATA 0x00000424
541#define BNX2_PCI_VPD_INTF 0x00000428
542#define BNX2_PCI_VPD_INTF_INTF_REQ (1L<<0)
543
544#define BNX2_PCI_VPD_ADDR_FLAG 0x0000042c
545#define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2)
546#define BNX2_PCI_VPD_ADDR_FLAG_WR (1<<15)
547
548#define BNX2_PCI_VPD_DATA 0x00000430
549#define BNX2_PCI_ID_VAL1 0x00000434
550#define BNX2_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0)
551#define BNX2_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16)
552
553#define BNX2_PCI_ID_VAL2 0x00000438
554#define BNX2_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffL<<0)
555#define BNX2_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16)
556
557#define BNX2_PCI_ID_VAL3 0x0000043c
558#define BNX2_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0)
559#define BNX2_PCI_ID_VAL3_REVISION_ID (0xffL<<24)
560
561#define BNX2_PCI_ID_VAL4 0x00000440
562#define BNX2_PCI_ID_VAL4_CAP_ENA (0xfL<<0)
563#define BNX2_PCI_ID_VAL4_CAP_ENA_0 (0L<<0)
564#define BNX2_PCI_ID_VAL4_CAP_ENA_1 (1L<<0)
565#define BNX2_PCI_ID_VAL4_CAP_ENA_2 (2L<<0)
566#define BNX2_PCI_ID_VAL4_CAP_ENA_3 (3L<<0)
567#define BNX2_PCI_ID_VAL4_CAP_ENA_4 (4L<<0)
568#define BNX2_PCI_ID_VAL4_CAP_ENA_5 (5L<<0)
569#define BNX2_PCI_ID_VAL4_CAP_ENA_6 (6L<<0)
570#define BNX2_PCI_ID_VAL4_CAP_ENA_7 (7L<<0)
571#define BNX2_PCI_ID_VAL4_CAP_ENA_8 (8L<<0)
572#define BNX2_PCI_ID_VAL4_CAP_ENA_9 (9L<<0)
573#define BNX2_PCI_ID_VAL4_CAP_ENA_10 (10L<<0)
574#define BNX2_PCI_ID_VAL4_CAP_ENA_11 (11L<<0)
575#define BNX2_PCI_ID_VAL4_CAP_ENA_12 (12L<<0)
576#define BNX2_PCI_ID_VAL4_CAP_ENA_13 (13L<<0)
577#define BNX2_PCI_ID_VAL4_CAP_ENA_14 (14L<<0)
578#define BNX2_PCI_ID_VAL4_CAP_ENA_15 (15L<<0)
579#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6)
580#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6)
581#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6)
582#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6)
583#define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6)
584#define BNX2_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9)
585#define BNX2_PCI_ID_VAL4_MSI_ADVERTIZE (0x7L<<12)
586#define BNX2_PCI_ID_VAL4_MSI_ENABLE (1L<<15)
587#define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16)
588#define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17)
589#define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE (0x3L<<21)
590#define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE (0x7L<<23)
591#define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE (0x7L<<26)
592
593#define BNX2_PCI_ID_VAL5 0x00000444
594#define BNX2_PCI_ID_VAL5_D1_SUPPORT (1L<<0)
595#define BNX2_PCI_ID_VAL5_D2_SUPPORT (1L<<1)
596#define BNX2_PCI_ID_VAL5_PME_IN_D0 (1L<<2)
597#define BNX2_PCI_ID_VAL5_PME_IN_D1 (1L<<3)
598#define BNX2_PCI_ID_VAL5_PME_IN_D2 (1L<<4)
599#define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5)
600
601#define BNX2_PCI_PCIX_EXTENDED_STATUS 0x00000448
602#define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8)
603#define BNX2_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9)
604#define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfL<<16)
605#define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffL<<24)
606
607#define BNX2_PCI_ID_VAL6 0x0000044c
608#define BNX2_PCI_ID_VAL6_MAX_LAT (0xffL<<0)
609#define BNX2_PCI_ID_VAL6_MIN_GNT (0xffL<<8)
610#define BNX2_PCI_ID_VAL6_BIST (0xffL<<16)
611
612#define BNX2_PCI_MSI_DATA 0x00000450
613#define BNX2_PCI_MSI_DATA_PCI_MSI_DATA (0xffffL<<0)
614
615#define BNX2_PCI_MSI_ADDR_H 0x00000454
616#define BNX2_PCI_MSI_ADDR_L 0x00000458
617
618
619/*
620 * misc_reg definition
621 * offset: 0x800
622 */
623#define BNX2_MISC_COMMAND 0x00000800
624#define BNX2_MISC_COMMAND_ENABLE_ALL (1L<<0)
625#define BNX2_MISC_COMMAND_DISABLE_ALL (1L<<1)
626#define BNX2_MISC_COMMAND_CORE_RESET (1L<<4)
627#define BNX2_MISC_COMMAND_HARD_RESET (1L<<5)
628#define BNX2_MISC_COMMAND_PAR_ERROR (1L<<8)
629#define BNX2_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16)
630
631#define BNX2_MISC_CFG 0x00000804
632#define BNX2_MISC_CFG_PCI_GRC_TMOUT (1L<<0)
633#define BNX2_MISC_CFG_NVM_WR_EN (0x3L<<1)
634#define BNX2_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1)
635#define BNX2_MISC_CFG_NVM_WR_EN_PCI (1L<<1)
636#define BNX2_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1)
637#define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1)
638#define BNX2_MISC_CFG_BIST_EN (1L<<3)
639#define BNX2_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4)
640#define BNX2_MISC_CFG_BYPASS_BSCAN (1L<<5)
641#define BNX2_MISC_CFG_BYPASS_EJTAG (1L<<6)
642#define BNX2_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7)
643#define BNX2_MISC_CFG_LEDMODE (0x3L<<8)
644#define BNX2_MISC_CFG_LEDMODE_MAC (0L<<8)
645#define BNX2_MISC_CFG_LEDMODE_GPHY1 (1L<<8)
646#define BNX2_MISC_CFG_LEDMODE_GPHY2 (2L<<8)
647
648#define BNX2_MISC_ID 0x00000808
649#define BNX2_MISC_ID_BOND_ID (0xfL<<0)
650#define BNX2_MISC_ID_CHIP_METAL (0xffL<<4)
651#define BNX2_MISC_ID_CHIP_REV (0xfL<<12)
652#define BNX2_MISC_ID_CHIP_NUM (0xffffL<<16)
653
654#define BNX2_MISC_ENABLE_STATUS_BITS 0x0000080c
655#define BNX2_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0)
656#define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1)
657#define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2)
658#define BNX2_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3)
659#define BNX2_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4)
660#define BNX2_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5)
661#define BNX2_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
662#define BNX2_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7)
663#define BNX2_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
664#define BNX2_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9)
665#define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
666#define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
667#define BNX2_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12)
668#define BNX2_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13)
669#define BNX2_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14)
670#define BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15)
671#define BNX2_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16)
672#define BNX2_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17)
673#define BNX2_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18)
674#define BNX2_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19)
675#define BNX2_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
676#define BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21)
677#define BNX2_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
678#define BNX2_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
679#define BNX2_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
680#define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25)
681#define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26)
682#define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27)
683
684#define BNX2_MISC_ENABLE_SET_BITS 0x00000810
685#define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0)
686#define BNX2_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1)
687#define BNX2_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2)
688#define BNX2_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3)
689#define BNX2_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4)
690#define BNX2_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5)
691#define BNX2_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
692#define BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7)
693#define BNX2_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
694#define BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9)
695#define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
696#define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
697#define BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12)
698#define BNX2_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13)
699#define BNX2_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14)
700#define BNX2_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15)
701#define BNX2_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16)
702#define BNX2_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17)
703#define BNX2_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18)
704#define BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19)
705#define BNX2_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
706#define BNX2_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21)
707#define BNX2_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
708#define BNX2_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
709#define BNX2_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
710#define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25)
711#define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26)
712#define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27)
713
714#define BNX2_MISC_ENABLE_CLR_BITS 0x00000814
715#define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0)
716#define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1)
717#define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2)
718#define BNX2_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3)
719#define BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4)
720#define BNX2_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5)
721#define BNX2_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
722#define BNX2_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7)
723#define BNX2_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
724#define BNX2_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9)
725#define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
726#define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
727#define BNX2_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12)
728#define BNX2_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13)
729#define BNX2_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14)
730#define BNX2_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15)
731#define BNX2_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16)
732#define BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17)
733#define BNX2_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18)
734#define BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19)
735#define BNX2_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
736#define BNX2_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21)
737#define BNX2_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
738#define BNX2_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
739#define BNX2_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
740#define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25)
741#define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26)
742#define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27)
743
744#define BNX2_MISC_CLOCK_CONTROL_BITS 0x00000818
745#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
746#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
747#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
748#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
749#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
750#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
751#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
752#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
753#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
754#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
755#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
756#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
757#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
758#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
759#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
760#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
761#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
762#define BNX2_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11)
763#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
764#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
765#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
766#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
767#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
768#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
769#define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
770#define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17)
771#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18)
772#define BNX2_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19)
773#define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20)
774
775#define BNX2_MISC_GPIO 0x0000081c
776#define BNX2_MISC_GPIO_VALUE (0xffL<<0)
777#define BNX2_MISC_GPIO_SET (0xffL<<8)
778#define BNX2_MISC_GPIO_CLR (0xffL<<16)
779#define BNX2_MISC_GPIO_FLOAT (0xffL<<24)
780
781#define BNX2_MISC_GPIO_INT 0x00000820
782#define BNX2_MISC_GPIO_INT_INT_STATE (0xfL<<0)
783#define BNX2_MISC_GPIO_INT_OLD_VALUE (0xfL<<8)
784#define BNX2_MISC_GPIO_INT_OLD_SET (0xfL<<16)
785#define BNX2_MISC_GPIO_INT_OLD_CLR (0xfL<<24)
786
787#define BNX2_MISC_CONFIG_LFSR 0x00000824
788#define BNX2_MISC_CONFIG_LFSR_DIV (0xffffL<<0)
789
790#define BNX2_MISC_LFSR_MASK_BITS 0x00000828
791#define BNX2_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0)
792#define BNX2_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1)
793#define BNX2_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2)
794#define BNX2_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3)
795#define BNX2_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4)
796#define BNX2_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5)
797#define BNX2_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
798#define BNX2_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7)
799#define BNX2_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
800#define BNX2_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9)
801#define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
802#define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
803#define BNX2_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12)
804#define BNX2_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13)
805#define BNX2_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14)
806#define BNX2_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15)
807#define BNX2_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16)
808#define BNX2_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17)
809#define BNX2_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18)
810#define BNX2_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19)
811#define BNX2_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
812#define BNX2_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21)
813#define BNX2_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
814#define BNX2_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
815#define BNX2_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
816#define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25)
817#define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26)
818#define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27)
819
820#define BNX2_MISC_ARB_REQ0 0x0000082c
821#define BNX2_MISC_ARB_REQ1 0x00000830
822#define BNX2_MISC_ARB_REQ2 0x00000834
823#define BNX2_MISC_ARB_REQ3 0x00000838
824#define BNX2_MISC_ARB_REQ4 0x0000083c
825#define BNX2_MISC_ARB_FREE0 0x00000840
826#define BNX2_MISC_ARB_FREE1 0x00000844
827#define BNX2_MISC_ARB_FREE2 0x00000848
828#define BNX2_MISC_ARB_FREE3 0x0000084c
829#define BNX2_MISC_ARB_FREE4 0x00000850
830#define BNX2_MISC_ARB_REQ_STATUS0 0x00000854
831#define BNX2_MISC_ARB_REQ_STATUS1 0x00000858
832#define BNX2_MISC_ARB_REQ_STATUS2 0x0000085c
833#define BNX2_MISC_ARB_REQ_STATUS3 0x00000860
834#define BNX2_MISC_ARB_REQ_STATUS4 0x00000864
835#define BNX2_MISC_ARB_GNT0 0x00000868
836#define BNX2_MISC_ARB_GNT0_0 (0x7L<<0)
837#define BNX2_MISC_ARB_GNT0_1 (0x7L<<4)
838#define BNX2_MISC_ARB_GNT0_2 (0x7L<<8)
839#define BNX2_MISC_ARB_GNT0_3 (0x7L<<12)
840#define BNX2_MISC_ARB_GNT0_4 (0x7L<<16)
841#define BNX2_MISC_ARB_GNT0_5 (0x7L<<20)
842#define BNX2_MISC_ARB_GNT0_6 (0x7L<<24)
843#define BNX2_MISC_ARB_GNT0_7 (0x7L<<28)
844
845#define BNX2_MISC_ARB_GNT1 0x0000086c
846#define BNX2_MISC_ARB_GNT1_8 (0x7L<<0)
847#define BNX2_MISC_ARB_GNT1_9 (0x7L<<4)
848#define BNX2_MISC_ARB_GNT1_10 (0x7L<<8)
849#define BNX2_MISC_ARB_GNT1_11 (0x7L<<12)
850#define BNX2_MISC_ARB_GNT1_12 (0x7L<<16)
851#define BNX2_MISC_ARB_GNT1_13 (0x7L<<20)
852#define BNX2_MISC_ARB_GNT1_14 (0x7L<<24)
853#define BNX2_MISC_ARB_GNT1_15 (0x7L<<28)
854
855#define BNX2_MISC_ARB_GNT2 0x00000870
856#define BNX2_MISC_ARB_GNT2_16 (0x7L<<0)
857#define BNX2_MISC_ARB_GNT2_17 (0x7L<<4)
858#define BNX2_MISC_ARB_GNT2_18 (0x7L<<8)
859#define BNX2_MISC_ARB_GNT2_19 (0x7L<<12)
860#define BNX2_MISC_ARB_GNT2_20 (0x7L<<16)
861#define BNX2_MISC_ARB_GNT2_21 (0x7L<<20)
862#define BNX2_MISC_ARB_GNT2_22 (0x7L<<24)
863#define BNX2_MISC_ARB_GNT2_23 (0x7L<<28)
864
865#define BNX2_MISC_ARB_GNT3 0x00000874
866#define BNX2_MISC_ARB_GNT3_24 (0x7L<<0)
867#define BNX2_MISC_ARB_GNT3_25 (0x7L<<4)
868#define BNX2_MISC_ARB_GNT3_26 (0x7L<<8)
869#define BNX2_MISC_ARB_GNT3_27 (0x7L<<12)
870#define BNX2_MISC_ARB_GNT3_28 (0x7L<<16)
871#define BNX2_MISC_ARB_GNT3_29 (0x7L<<20)
872#define BNX2_MISC_ARB_GNT3_30 (0x7L<<24)
873#define BNX2_MISC_ARB_GNT3_31 (0x7L<<28)
874
875#define BNX2_MISC_PRBS_CONTROL 0x00000878
876#define BNX2_MISC_PRBS_CONTROL_EN (1L<<0)
877#define BNX2_MISC_PRBS_CONTROL_RSTB (1L<<1)
878#define BNX2_MISC_PRBS_CONTROL_INV (1L<<2)
879#define BNX2_MISC_PRBS_CONTROL_ERR_CLR (1L<<3)
880#define BNX2_MISC_PRBS_CONTROL_ORDER (0x3L<<4)
881#define BNX2_MISC_PRBS_CONTROL_ORDER_7TH (0L<<4)
882#define BNX2_MISC_PRBS_CONTROL_ORDER_15TH (1L<<4)
883#define BNX2_MISC_PRBS_CONTROL_ORDER_23RD (2L<<4)
884#define BNX2_MISC_PRBS_CONTROL_ORDER_31ST (3L<<4)
885
886#define BNX2_MISC_PRBS_STATUS 0x0000087c
887#define BNX2_MISC_PRBS_STATUS_LOCK (1L<<0)
888#define BNX2_MISC_PRBS_STATUS_STKY (1L<<1)
889#define BNX2_MISC_PRBS_STATUS_ERRORS (0x3fffL<<2)
890#define BNX2_MISC_PRBS_STATUS_STATE (0xfL<<16)
891
892#define BNX2_MISC_SM_ASF_CONTROL 0x00000880
893#define BNX2_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0)
894#define BNX2_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1)
895#define BNX2_MISC_SM_ASF_CONTROL_WG_TO (1L<<2)
896#define BNX2_MISC_SM_ASF_CONTROL_HB_TO (1L<<3)
897#define BNX2_MISC_SM_ASF_CONTROL_PA_TO (1L<<4)
898#define BNX2_MISC_SM_ASF_CONTROL_PL_TO (1L<<5)
899#define BNX2_MISC_SM_ASF_CONTROL_RT_TO (1L<<6)
900#define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7)
901#define BNX2_MISC_SM_ASF_CONTROL_RES (0xfL<<8)
902#define BNX2_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12)
903#define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13)
904#define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14)
905#define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15)
906#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x3fL<<16)
907#define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x3fL<<24)
908#define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30)
909#define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31)
910
911#define BNX2_MISC_SMB_IN 0x00000884
912#define BNX2_MISC_SMB_IN_DAT_IN (0xffL<<0)
913#define BNX2_MISC_SMB_IN_RDY (1L<<8)
914#define BNX2_MISC_SMB_IN_DONE (1L<<9)
915#define BNX2_MISC_SMB_IN_FIRSTBYTE (1L<<10)
916#define BNX2_MISC_SMB_IN_STATUS (0x7L<<11)
917#define BNX2_MISC_SMB_IN_STATUS_OK (0x0L<<11)
918#define BNX2_MISC_SMB_IN_STATUS_PEC (0x1L<<11)
919#define BNX2_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11)
920#define BNX2_MISC_SMB_IN_STATUS_STOP (0x3L<<11)
921#define BNX2_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11)
922
923#define BNX2_MISC_SMB_OUT 0x00000888
924#define BNX2_MISC_SMB_OUT_DAT_OUT (0xffL<<0)
925#define BNX2_MISC_SMB_OUT_RDY (1L<<8)
926#define BNX2_MISC_SMB_OUT_START (1L<<9)
927#define BNX2_MISC_SMB_OUT_LAST (1L<<10)
928#define BNX2_MISC_SMB_OUT_ACC_TYPE (1L<<11)
929#define BNX2_MISC_SMB_OUT_ENB_PEC (1L<<12)
930#define BNX2_MISC_SMB_OUT_GET_RX_LEN (1L<<13)
931#define BNX2_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14)
932#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20)
933#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20)
934#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20)
935#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20)
936#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20)
937#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20)
938#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20)
939#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20)
940#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20)
941#define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (0x6L<<20)
942#define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24)
943#define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25)
944#define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26)
945#define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27)
946#define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28)
947
948#define BNX2_MISC_SMB_WATCHDOG 0x0000088c
949#define BNX2_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0)
950
951#define BNX2_MISC_SMB_HEARTBEAT 0x00000890
952#define BNX2_MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffL<<0)
953
954#define BNX2_MISC_SMB_POLL_ASF 0x00000894
955#define BNX2_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0)
956
957#define BNX2_MISC_SMB_POLL_LEGACY 0x00000898
958#define BNX2_MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffL<<0)
959
960#define BNX2_MISC_SMB_RETRAN 0x0000089c
961#define BNX2_MISC_SMB_RETRAN_RETRAN (0xffL<<0)
962
963#define BNX2_MISC_SMB_TIMESTAMP 0x000008a0
964#define BNX2_MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffL<<0)
965
966#define BNX2_MISC_PERR_ENA0 0x000008a4
967#define BNX2_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0)
968#define BNX2_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1)
969#define BNX2_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2)
970#define BNX2_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3)
971#define BNX2_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4)
972#define BNX2_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5)
973#define BNX2_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6)
974#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7)
975#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8)
976#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9)
977#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10)
978#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11)
979#define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12)
980#define BNX2_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13)
981#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14)
982#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15)
983#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16)
984#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17)
985#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18)
986#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19)
987#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20)
988#define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21)
989#define BNX2_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22)
990#define BNX2_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23)
991#define BNX2_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24)
992#define BNX2_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25)
993#define BNX2_MISC_PERR_ENA0_RBDC_MISC (1L<<26)
994#define BNX2_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27)
995#define BNX2_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28)
996#define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29)
997#define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30)
998#define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31)
999
1000#define BNX2_MISC_PERR_ENA1 0x000008a8
1001#define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0)
1002#define BNX2_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1)
1003#define BNX2_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2)
1004#define BNX2_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3)
1005#define BNX2_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4)
1006#define BNX2_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5)
1007#define BNX2_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6)
1008#define BNX2_MISC_PERR_ENA1_TBDC_MISC (1L<<7)
1009#define BNX2_MISC_PERR_ENA1_TDMA_MISC (1L<<8)
1010#define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9)
1011#define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10)
1012#define BNX2_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11)
1013#define BNX2_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12)
1014#define BNX2_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13)
1015#define BNX2_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14)
1016#define BNX2_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15)
1017#define BNX2_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16)
1018#define BNX2_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17)
1019#define BNX2_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18)
1020#define BNX2_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19)
1021#define BNX2_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20)
1022#define BNX2_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21)
1023#define BNX2_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22)
1024#define BNX2_MISC_PERR_ENA1_CSQ_MISC (1L<<23)
1025#define BNX2_MISC_PERR_ENA1_CPQ_MISC (1L<<24)
1026#define BNX2_MISC_PERR_ENA1_MCPQ_MISC (1L<<25)
1027#define BNX2_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26)
1028#define BNX2_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27)
1029#define BNX2_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28)
1030#define BNX2_MISC_PERR_ENA1_RXPQ_MISC (1L<<29)
1031#define BNX2_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30)
1032#define BNX2_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31)
1033
1034#define BNX2_MISC_PERR_ENA2 0x000008ac
1035#define BNX2_MISC_PERR_ENA2_COMQ_MISC (1L<<0)
1036#define BNX2_MISC_PERR_ENA2_COMXQ_MISC (1L<<1)
1037#define BNX2_MISC_PERR_ENA2_COMTQ_MISC (1L<<2)
1038#define BNX2_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3)
1039#define BNX2_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4)
1040#define BNX2_MISC_PERR_ENA2_TXPQ_MISC (1L<<5)
1041#define BNX2_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6)
1042#define BNX2_MISC_PERR_ENA2_TPATQ_MISC (1L<<7)
1043#define BNX2_MISC_PERR_ENA2_TASQ_MISC (1L<<8)
1044
1045#define BNX2_MISC_DEBUG_VECTOR_SEL 0x000008b0
1046#define BNX2_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0)
1047#define BNX2_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12)
1048
1049#define BNX2_MISC_VREG_CONTROL 0x000008b4
1050#define BNX2_MISC_VREG_CONTROL_1_2 (0xfL<<0)
1051#define BNX2_MISC_VREG_CONTROL_2_5 (0xfL<<4)
1052
1053#define BNX2_MISC_FINAL_CLK_CTL_VAL 0x000008b8
1054#define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6)
1055
1056#define BNX2_MISC_UNUSED0 0x000008bc
1057
1058
1059/*
1060 * nvm_reg definition
1061 * offset: 0x6400
1062 */
1063#define BNX2_NVM_COMMAND 0x00006400
1064#define BNX2_NVM_COMMAND_RST (1L<<0)
1065#define BNX2_NVM_COMMAND_DONE (1L<<3)
1066#define BNX2_NVM_COMMAND_DOIT (1L<<4)
1067#define BNX2_NVM_COMMAND_WR (1L<<5)
1068#define BNX2_NVM_COMMAND_ERASE (1L<<6)
1069#define BNX2_NVM_COMMAND_FIRST (1L<<7)
1070#define BNX2_NVM_COMMAND_LAST (1L<<8)
1071#define BNX2_NVM_COMMAND_WREN (1L<<16)
1072#define BNX2_NVM_COMMAND_WRDI (1L<<17)
1073#define BNX2_NVM_COMMAND_EWSR (1L<<18)
1074#define BNX2_NVM_COMMAND_WRSR (1L<<19)
1075
1076#define BNX2_NVM_STATUS 0x00006404
1077#define BNX2_NVM_STATUS_PI_FSM_STATE (0xfL<<0)
1078#define BNX2_NVM_STATUS_EE_FSM_STATE (0xfL<<4)
1079#define BNX2_NVM_STATUS_EQ_FSM_STATE (0xfL<<8)
1080
1081#define BNX2_NVM_WRITE 0x00006408
1082#define BNX2_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0)
1083#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0)
1084#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0)
1085#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0)
1086#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0)
1087#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0)
1088#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0)
1089#define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0)
1090
1091#define BNX2_NVM_ADDR 0x0000640c
1092#define BNX2_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
1093#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0)
1094#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0)
1095#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0)
1096#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0)
1097#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0)
1098#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0)
1099#define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0)
1100
1101#define BNX2_NVM_READ 0x00006410
1102#define BNX2_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0)
1103#define BNX2_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0)
1104#define BNX2_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0)
1105#define BNX2_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0)
1106#define BNX2_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0)
1107#define BNX2_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0)
1108#define BNX2_NVM_READ_NVM_READ_VALUE_SO (16L<<0)
1109#define BNX2_NVM_READ_NVM_READ_VALUE_SI (32L<<0)
1110
1111#define BNX2_NVM_CFG1 0x00006414
1112#define BNX2_NVM_CFG1_FLASH_MODE (1L<<0)
1113#define BNX2_NVM_CFG1_BUFFER_MODE (1L<<1)
1114#define BNX2_NVM_CFG1_PASS_MODE (1L<<2)
1115#define BNX2_NVM_CFG1_BITBANG_MODE (1L<<3)
1116#define BNX2_NVM_CFG1_STATUS_BIT (0x7L<<4)
1117#define BNX2_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4)
1118#define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4)
1119#define BNX2_NVM_CFG1_SPI_CLK_DIV (0xfL<<7)
1120#define BNX2_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11)
1121#define BNX2_NVM_CFG1_PROTECT_MODE (1L<<24)
1122#define BNX2_NVM_CFG1_FLASH_SIZE (1L<<25)
1123#define BNX2_NVM_CFG1_COMPAT_BYPASSS (1L<<31)
1124
1125#define BNX2_NVM_CFG2 0x00006418
1126#define BNX2_NVM_CFG2_ERASE_CMD (0xffL<<0)
1127#define BNX2_NVM_CFG2_DUMMY (0xffL<<8)
1128#define BNX2_NVM_CFG2_STATUS_CMD (0xffL<<16)
1129
1130#define BNX2_NVM_CFG3 0x0000641c
1131#define BNX2_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0)
1132#define BNX2_NVM_CFG3_WRITE_CMD (0xffL<<8)
1133#define BNX2_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16)
1134#define BNX2_NVM_CFG3_READ_CMD (0xffL<<24)
1135
1136#define BNX2_NVM_SW_ARB 0x00006420
1137#define BNX2_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0)
1138#define BNX2_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
1139#define BNX2_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2)
1140#define BNX2_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3)
1141#define BNX2_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4)
1142#define BNX2_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
1143#define BNX2_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6)
1144#define BNX2_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7)
1145#define BNX2_NVM_SW_ARB_ARB_ARB0 (1L<<8)
1146#define BNX2_NVM_SW_ARB_ARB_ARB1 (1L<<9)
1147#define BNX2_NVM_SW_ARB_ARB_ARB2 (1L<<10)
1148#define BNX2_NVM_SW_ARB_ARB_ARB3 (1L<<11)
1149#define BNX2_NVM_SW_ARB_REQ0 (1L<<12)
1150#define BNX2_NVM_SW_ARB_REQ1 (1L<<13)
1151#define BNX2_NVM_SW_ARB_REQ2 (1L<<14)
1152#define BNX2_NVM_SW_ARB_REQ3 (1L<<15)
1153
1154#define BNX2_NVM_ACCESS_ENABLE 0x00006424
1155#define BNX2_NVM_ACCESS_ENABLE_EN (1L<<0)
1156#define BNX2_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
1157
1158#define BNX2_NVM_WRITE1 0x00006428
1159#define BNX2_NVM_WRITE1_WREN_CMD (0xffL<<0)
1160#define BNX2_NVM_WRITE1_WRDI_CMD (0xffL<<8)
1161#define BNX2_NVM_WRITE1_SR_DATA (0xffL<<16)
1162
1163
1164
1165/*
1166 * dma_reg definition
1167 * offset: 0xc00
1168 */
1169#define BNX2_DMA_COMMAND 0x00000c00
1170#define BNX2_DMA_COMMAND_ENABLE (1L<<0)
1171
1172#define BNX2_DMA_STATUS 0x00000c04
1173#define BNX2_DMA_STATUS_PAR_ERROR_STATE (1L<<0)
1174#define BNX2_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16)
1175#define BNX2_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17)
1176#define BNX2_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18)
1177#define BNX2_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19)
1178#define BNX2_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20)
1179#define BNX2_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21)
1180#define BNX2_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22)
1181#define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23)
1182#define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24)
1183#define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25)
1184
1185#define BNX2_DMA_CONFIG 0x00000c08
1186#define BNX2_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0)
1187#define BNX2_DMA_CONFIG_DATA_WORD_SWAP (1L<<1)
1188#define BNX2_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4)
1189#define BNX2_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5)
1190#define BNX2_DMA_CONFIG_ONE_DMA (1L<<6)
1191#define BNX2_DMA_CONFIG_CNTL_TWO_DMA (1L<<7)
1192#define BNX2_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8)
1193#define BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10)
1194#define BNX2_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11)
1195#define BNX2_DMA_CONFIG_NO_RCHANS_IN_USE (0xfL<<12)
1196#define BNX2_DMA_CONFIG_NO_WCHANS_IN_USE (0xfL<<16)
1197#define BNX2_DMA_CONFIG_PCI_CLK_CMP_BITS (0x7L<<20)
1198#define BNX2_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23)
1199#define BNX2_DMA_CONFIG_BIG_SIZE (0xfL<<24)
1200#define BNX2_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24)
1201#define BNX2_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24)
1202#define BNX2_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24)
1203#define BNX2_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24)
1204#define BNX2_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24)
1205
1206#define BNX2_DMA_BLACKOUT 0x00000c0c
1207#define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0)
1208#define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8)
1209#define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16)
1210
1211#define BNX2_DMA_RCHAN_STAT 0x00000c30
1212#define BNX2_DMA_RCHAN_STAT_COMP_CODE_0 (0x7L<<0)
1213#define BNX2_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3)
1214#define BNX2_DMA_RCHAN_STAT_COMP_CODE_1 (0x7L<<4)
1215#define BNX2_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7)
1216#define BNX2_DMA_RCHAN_STAT_COMP_CODE_2 (0x7L<<8)
1217#define BNX2_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11)
1218#define BNX2_DMA_RCHAN_STAT_COMP_CODE_3 (0x7L<<12)
1219#define BNX2_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15)
1220#define BNX2_DMA_RCHAN_STAT_COMP_CODE_4 (0x7L<<16)
1221#define BNX2_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19)
1222#define BNX2_DMA_RCHAN_STAT_COMP_CODE_5 (0x7L<<20)
1223#define BNX2_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23)
1224#define BNX2_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24)
1225#define BNX2_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27)
1226#define BNX2_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28)
1227#define BNX2_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31)
1228
1229#define BNX2_DMA_WCHAN_STAT 0x00000c34
1230#define BNX2_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0)
1231#define BNX2_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3)
1232#define BNX2_DMA_WCHAN_STAT_COMP_CODE_1 (0x7L<<4)
1233#define BNX2_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7)
1234#define BNX2_DMA_WCHAN_STAT_COMP_CODE_2 (0x7L<<8)
1235#define BNX2_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11)
1236#define BNX2_DMA_WCHAN_STAT_COMP_CODE_3 (0x7L<<12)
1237#define BNX2_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15)
1238#define BNX2_DMA_WCHAN_STAT_COMP_CODE_4 (0x7L<<16)
1239#define BNX2_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19)
1240#define BNX2_DMA_WCHAN_STAT_COMP_CODE_5 (0x7L<<20)
1241#define BNX2_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23)
1242#define BNX2_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24)
1243#define BNX2_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27)
1244#define BNX2_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28)
1245#define BNX2_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31)
1246
1247#define BNX2_DMA_RCHAN_ASSIGNMENT 0x00000c38
1248#define BNX2_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0)
1249#define BNX2_DMA_RCHAN_ASSIGNMENT_1 (0xfL<<4)
1250#define BNX2_DMA_RCHAN_ASSIGNMENT_2 (0xfL<<8)
1251#define BNX2_DMA_RCHAN_ASSIGNMENT_3 (0xfL<<12)
1252#define BNX2_DMA_RCHAN_ASSIGNMENT_4 (0xfL<<16)
1253#define BNX2_DMA_RCHAN_ASSIGNMENT_5 (0xfL<<20)
1254#define BNX2_DMA_RCHAN_ASSIGNMENT_6 (0xfL<<24)
1255#define BNX2_DMA_RCHAN_ASSIGNMENT_7 (0xfL<<28)
1256
1257#define BNX2_DMA_WCHAN_ASSIGNMENT 0x00000c3c
1258#define BNX2_DMA_WCHAN_ASSIGNMENT_0 (0xfL<<0)
1259#define BNX2_DMA_WCHAN_ASSIGNMENT_1 (0xfL<<4)
1260#define BNX2_DMA_WCHAN_ASSIGNMENT_2 (0xfL<<8)
1261#define BNX2_DMA_WCHAN_ASSIGNMENT_3 (0xfL<<12)
1262#define BNX2_DMA_WCHAN_ASSIGNMENT_4 (0xfL<<16)
1263#define BNX2_DMA_WCHAN_ASSIGNMENT_5 (0xfL<<20)
1264#define BNX2_DMA_WCHAN_ASSIGNMENT_6 (0xfL<<24)
1265#define BNX2_DMA_WCHAN_ASSIGNMENT_7 (0xfL<<28)
1266
1267#define BNX2_DMA_RCHAN_STAT_00 0x00000c40
1268#define BNX2_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0)
1269
1270#define BNX2_DMA_RCHAN_STAT_01 0x00000c44
1271#define BNX2_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0)
1272
1273#define BNX2_DMA_RCHAN_STAT_02 0x00000c48
1274#define BNX2_DMA_RCHAN_STAT_02_LENGTH (0xffffL<<0)
1275#define BNX2_DMA_RCHAN_STAT_02_WORD_SWAP (1L<<16)
1276#define BNX2_DMA_RCHAN_STAT_02_BYTE_SWAP (1L<<17)
1277#define BNX2_DMA_RCHAN_STAT_02_PRIORITY_LVL (1L<<18)
1278
1279#define BNX2_DMA_RCHAN_STAT_10 0x00000c4c
1280#define BNX2_DMA_RCHAN_STAT_11 0x00000c50
1281#define BNX2_DMA_RCHAN_STAT_12 0x00000c54
1282#define BNX2_DMA_RCHAN_STAT_20 0x00000c58
1283#define BNX2_DMA_RCHAN_STAT_21 0x00000c5c
1284#define BNX2_DMA_RCHAN_STAT_22 0x00000c60
1285#define BNX2_DMA_RCHAN_STAT_30 0x00000c64
1286#define BNX2_DMA_RCHAN_STAT_31 0x00000c68
1287#define BNX2_DMA_RCHAN_STAT_32 0x00000c6c
1288#define BNX2_DMA_RCHAN_STAT_40 0x00000c70
1289#define BNX2_DMA_RCHAN_STAT_41 0x00000c74
1290#define BNX2_DMA_RCHAN_STAT_42 0x00000c78
1291#define BNX2_DMA_RCHAN_STAT_50 0x00000c7c
1292#define BNX2_DMA_RCHAN_STAT_51 0x00000c80
1293#define BNX2_DMA_RCHAN_STAT_52 0x00000c84
1294#define BNX2_DMA_RCHAN_STAT_60 0x00000c88
1295#define BNX2_DMA_RCHAN_STAT_61 0x00000c8c
1296#define BNX2_DMA_RCHAN_STAT_62 0x00000c90
1297#define BNX2_DMA_RCHAN_STAT_70 0x00000c94
1298#define BNX2_DMA_RCHAN_STAT_71 0x00000c98
1299#define BNX2_DMA_RCHAN_STAT_72 0x00000c9c
1300#define BNX2_DMA_WCHAN_STAT_00 0x00000ca0
1301#define BNX2_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0)
1302
1303#define BNX2_DMA_WCHAN_STAT_01 0x00000ca4
1304#define BNX2_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0)
1305
1306#define BNX2_DMA_WCHAN_STAT_02 0x00000ca8
1307#define BNX2_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0)
1308#define BNX2_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16)
1309#define BNX2_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17)
1310#define BNX2_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18)
1311
1312#define BNX2_DMA_WCHAN_STAT_10 0x00000cac
1313#define BNX2_DMA_WCHAN_STAT_11 0x00000cb0
1314#define BNX2_DMA_WCHAN_STAT_12 0x00000cb4
1315#define BNX2_DMA_WCHAN_STAT_20 0x00000cb8
1316#define BNX2_DMA_WCHAN_STAT_21 0x00000cbc
1317#define BNX2_DMA_WCHAN_STAT_22 0x00000cc0
1318#define BNX2_DMA_WCHAN_STAT_30 0x00000cc4
1319#define BNX2_DMA_WCHAN_STAT_31 0x00000cc8
1320#define BNX2_DMA_WCHAN_STAT_32 0x00000ccc
1321#define BNX2_DMA_WCHAN_STAT_40 0x00000cd0
1322#define BNX2_DMA_WCHAN_STAT_41 0x00000cd4
1323#define BNX2_DMA_WCHAN_STAT_42 0x00000cd8
1324#define BNX2_DMA_WCHAN_STAT_50 0x00000cdc
1325#define BNX2_DMA_WCHAN_STAT_51 0x00000ce0
1326#define BNX2_DMA_WCHAN_STAT_52 0x00000ce4
1327#define BNX2_DMA_WCHAN_STAT_60 0x00000ce8
1328#define BNX2_DMA_WCHAN_STAT_61 0x00000cec
1329#define BNX2_DMA_WCHAN_STAT_62 0x00000cf0
1330#define BNX2_DMA_WCHAN_STAT_70 0x00000cf4
1331#define BNX2_DMA_WCHAN_STAT_71 0x00000cf8
1332#define BNX2_DMA_WCHAN_STAT_72 0x00000cfc
1333#define BNX2_DMA_ARB_STAT_00 0x00000d00
1334#define BNX2_DMA_ARB_STAT_00_MASTER (0xffffL<<0)
1335#define BNX2_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16)
1336#define BNX2_DMA_ARB_STAT_00_CUR_BINMSTR (0xffL<<24)
1337
1338#define BNX2_DMA_ARB_STAT_01 0x00000d04
1339#define BNX2_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0)
1340#define BNX2_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4)
1341#define BNX2_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8)
1342#define BNX2_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12)
1343#define BNX2_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16)
1344#define BNX2_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20)
1345#define BNX2_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24)
1346#define BNX2_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28)
1347
1348#define BNX2_DMA_FUSE_CTRL0_CMD 0x00000f00
1349#define BNX2_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0)
1350#define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1)
1351#define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2)
1352#define BNX2_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3)
1353#define BNX2_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8)
1354
1355#define BNX2_DMA_FUSE_CTRL0_DATA 0x00000f04
1356#define BNX2_DMA_FUSE_CTRL1_CMD 0x00000f08
1357#define BNX2_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0)
1358#define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1)
1359#define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2)
1360#define BNX2_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3)
1361#define BNX2_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8)
1362
1363#define BNX2_DMA_FUSE_CTRL1_DATA 0x00000f0c
1364#define BNX2_DMA_FUSE_CTRL2_CMD 0x00000f10
1365#define BNX2_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0)
1366#define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1)
1367#define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2)
1368#define BNX2_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3)
1369#define BNX2_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8)
1370
1371#define BNX2_DMA_FUSE_CTRL2_DATA 0x00000f14
1372
1373
1374/*
1375 * context_reg definition
1376 * offset: 0x1000
1377 */
1378#define BNX2_CTX_COMMAND 0x00001000
1379#define BNX2_CTX_COMMAND_ENABLED (1L<<0)
1380
1381#define BNX2_CTX_STATUS 0x00001004
1382#define BNX2_CTX_STATUS_LOCK_WAIT (1L<<0)
1383#define BNX2_CTX_STATUS_READ_STAT (1L<<16)
1384#define BNX2_CTX_STATUS_WRITE_STAT (1L<<17)
1385#define BNX2_CTX_STATUS_ACC_STALL_STAT (1L<<18)
1386#define BNX2_CTX_STATUS_LOCK_STALL_STAT (1L<<19)
1387
1388#define BNX2_CTX_VIRT_ADDR 0x00001008
1389#define BNX2_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6)
1390
1391#define BNX2_CTX_PAGE_TBL 0x0000100c
1392#define BNX2_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6)
1393
1394#define BNX2_CTX_DATA_ADR 0x00001010
1395#define BNX2_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2)
1396
1397#define BNX2_CTX_DATA 0x00001014
1398#define BNX2_CTX_LOCK 0x00001018
1399#define BNX2_CTX_LOCK_TYPE (0x7L<<0)
1400#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0)
1401#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0)
1402#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0)
1403#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0)
1404#define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0)
1405#define BNX2_CTX_LOCK_CID_VALUE (0x3fffL<<7)
1406#define BNX2_CTX_LOCK_GRANTED (1L<<26)
1407#define BNX2_CTX_LOCK_MODE (0x7L<<27)
1408#define BNX2_CTX_LOCK_MODE_UNLOCK (0x0L<<27)
1409#define BNX2_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27)
1410#define BNX2_CTX_LOCK_MODE_SURE (0x2L<<27)
1411#define BNX2_CTX_LOCK_STATUS (1L<<30)
1412#define BNX2_CTX_LOCK_REQ (1L<<31)
1413
1414#define BNX2_CTX_ACCESS_STATUS 0x00001040
1415#define BNX2_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0)
1416#define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10)
1417#define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12)
1418#define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14)
1419#define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17)
1420
1421#define BNX2_CTX_DBG_LOCK_STATUS 0x00001044
1422#define BNX2_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0)
1423#define BNX2_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22)
1424
1425#define BNX2_CTX_CHNL_LOCK_STATUS_0 0x00001080
1426#define BNX2_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0)
1427#define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14)
1428#define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16)
1429
1430#define BNX2_CTX_CHNL_LOCK_STATUS_1 0x00001084
1431#define BNX2_CTX_CHNL_LOCK_STATUS_2 0x00001088
1432#define BNX2_CTX_CHNL_LOCK_STATUS_3 0x0000108c
1433#define BNX2_CTX_CHNL_LOCK_STATUS_4 0x00001090
1434#define BNX2_CTX_CHNL_LOCK_STATUS_5 0x00001094
1435#define BNX2_CTX_CHNL_LOCK_STATUS_6 0x00001098
1436#define BNX2_CTX_CHNL_LOCK_STATUS_7 0x0000109c
1437#define BNX2_CTX_CHNL_LOCK_STATUS_8 0x000010a0
1438
1439
1440/*
1441 * emac_reg definition
1442 * offset: 0x1400
1443 */
1444#define BNX2_EMAC_MODE 0x00001400
1445#define BNX2_EMAC_MODE_RESET (1L<<0)
1446#define BNX2_EMAC_MODE_HALF_DUPLEX (1L<<1)
1447#define BNX2_EMAC_MODE_PORT (0x3L<<2)
1448#define BNX2_EMAC_MODE_PORT_NONE (0L<<2)
1449#define BNX2_EMAC_MODE_PORT_MII (1L<<2)
1450#define BNX2_EMAC_MODE_PORT_GMII (2L<<2)
1451#define BNX2_EMAC_MODE_PORT_UNDEF (3L<<2)
1452#define BNX2_EMAC_MODE_MAC_LOOP (1L<<4)
1453#define BNX2_EMAC_MODE_TAGGED_MAC_CTL (1L<<7)
1454#define BNX2_EMAC_MODE_TX_BURST (1L<<8)
1455#define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9)
1456#define BNX2_EMAC_MODE_EXT_LINK_POL (1L<<10)
1457#define BNX2_EMAC_MODE_FORCE_LINK (1L<<11)
1458#define BNX2_EMAC_MODE_MPKT (1L<<18)
1459#define BNX2_EMAC_MODE_MPKT_RCVD (1L<<19)
1460#define BNX2_EMAC_MODE_ACPI_RCVD (1L<<20)
1461
1462#define BNX2_EMAC_STATUS 0x00001404
1463#define BNX2_EMAC_STATUS_LINK (1L<<11)
1464#define BNX2_EMAC_STATUS_LINK_CHANGE (1L<<12)
1465#define BNX2_EMAC_STATUS_MI_COMPLETE (1L<<22)
1466#define BNX2_EMAC_STATUS_MI_INT (1L<<23)
1467#define BNX2_EMAC_STATUS_AP_ERROR (1L<<24)
1468#define BNX2_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31)
1469
1470#define BNX2_EMAC_ATTENTION_ENA 0x00001408
1471#define BNX2_EMAC_ATTENTION_ENA_LINK (1L<<11)
1472#define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22)
1473#define BNX2_EMAC_ATTENTION_ENA_MI_INT (1L<<23)
1474#define BNX2_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24)
1475
1476#define BNX2_EMAC_LED 0x0000140c
1477#define BNX2_EMAC_LED_OVERRIDE (1L<<0)
1478#define BNX2_EMAC_LED_1000MB_OVERRIDE (1L<<1)
1479#define BNX2_EMAC_LED_100MB_OVERRIDE (1L<<2)
1480#define BNX2_EMAC_LED_10MB_OVERRIDE (1L<<3)
1481#define BNX2_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4)
1482#define BNX2_EMAC_LED_BLNK_TRAFFIC (1L<<5)
1483#define BNX2_EMAC_LED_TRAFFIC (1L<<6)
1484#define BNX2_EMAC_LED_1000MB (1L<<7)
1485#define BNX2_EMAC_LED_100MB (1L<<8)
1486#define BNX2_EMAC_LED_10MB (1L<<9)
1487#define BNX2_EMAC_LED_TRAFFIC_STAT (1L<<10)
1488#define BNX2_EMAC_LED_BLNK_RATE (0xfffL<<19)
1489#define BNX2_EMAC_LED_BLNK_RATE_ENA (1L<<31)
1490
1491#define BNX2_EMAC_MAC_MATCH0 0x00001410
1492#define BNX2_EMAC_MAC_MATCH1 0x00001414
1493#define BNX2_EMAC_MAC_MATCH2 0x00001418
1494#define BNX2_EMAC_MAC_MATCH3 0x0000141c
1495#define BNX2_EMAC_MAC_MATCH4 0x00001420
1496#define BNX2_EMAC_MAC_MATCH5 0x00001424
1497#define BNX2_EMAC_MAC_MATCH6 0x00001428
1498#define BNX2_EMAC_MAC_MATCH7 0x0000142c
1499#define BNX2_EMAC_MAC_MATCH8 0x00001430
1500#define BNX2_EMAC_MAC_MATCH9 0x00001434
1501#define BNX2_EMAC_MAC_MATCH10 0x00001438
1502#define BNX2_EMAC_MAC_MATCH11 0x0000143c
1503#define BNX2_EMAC_MAC_MATCH12 0x00001440
1504#define BNX2_EMAC_MAC_MATCH13 0x00001444
1505#define BNX2_EMAC_MAC_MATCH14 0x00001448
1506#define BNX2_EMAC_MAC_MATCH15 0x0000144c
1507#define BNX2_EMAC_MAC_MATCH16 0x00001450
1508#define BNX2_EMAC_MAC_MATCH17 0x00001454
1509#define BNX2_EMAC_MAC_MATCH18 0x00001458
1510#define BNX2_EMAC_MAC_MATCH19 0x0000145c
1511#define BNX2_EMAC_MAC_MATCH20 0x00001460
1512#define BNX2_EMAC_MAC_MATCH21 0x00001464
1513#define BNX2_EMAC_MAC_MATCH22 0x00001468
1514#define BNX2_EMAC_MAC_MATCH23 0x0000146c
1515#define BNX2_EMAC_MAC_MATCH24 0x00001470
1516#define BNX2_EMAC_MAC_MATCH25 0x00001474
1517#define BNX2_EMAC_MAC_MATCH26 0x00001478
1518#define BNX2_EMAC_MAC_MATCH27 0x0000147c
1519#define BNX2_EMAC_MAC_MATCH28 0x00001480
1520#define BNX2_EMAC_MAC_MATCH29 0x00001484
1521#define BNX2_EMAC_MAC_MATCH30 0x00001488
1522#define BNX2_EMAC_MAC_MATCH31 0x0000148c
1523#define BNX2_EMAC_BACKOFF_SEED 0x00001498
1524#define BNX2_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0)
1525
1526#define BNX2_EMAC_RX_MTU_SIZE 0x0000149c
1527#define BNX2_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0)
1528#define BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
1529
1530#define BNX2_EMAC_SERDES_CNTL 0x000014a4
1531#define BNX2_EMAC_SERDES_CNTL_RXR (0x7L<<0)
1532#define BNX2_EMAC_SERDES_CNTL_RXG (0x3L<<3)
1533#define BNX2_EMAC_SERDES_CNTL_RXCKSEL (1L<<6)
1534#define BNX2_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7)
1535#define BNX2_EMAC_SERDES_CNTL_BGMAX (1L<<10)
1536#define BNX2_EMAC_SERDES_CNTL_BGMIN (1L<<11)
1537#define BNX2_EMAC_SERDES_CNTL_TXMODE (1L<<12)
1538#define BNX2_EMAC_SERDES_CNTL_TXEDGE (1L<<13)
1539#define BNX2_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14)
1540#define BNX2_EMAC_SERDES_CNTL_PLLTEST (1L<<15)
1541#define BNX2_EMAC_SERDES_CNTL_CDET_EN (1L<<16)
1542#define BNX2_EMAC_SERDES_CNTL_TBI_LBK (1L<<17)
1543#define BNX2_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18)
1544#define BNX2_EMAC_SERDES_CNTL_REV_PHASE (1L<<19)
1545#define BNX2_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20)
1546#define BNX2_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22)
1547
1548#define BNX2_EMAC_SERDES_STATUS 0x000014a8
1549#define BNX2_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0)
1550#define BNX2_EMAC_SERDES_STATUS_COMMA_DET (1L<<8)
1551
1552#define BNX2_EMAC_MDIO_COMM 0x000014ac
1553#define BNX2_EMAC_MDIO_COMM_DATA (0xffffL<<0)
1554#define BNX2_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16)
1555#define BNX2_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21)
1556#define BNX2_EMAC_MDIO_COMM_COMMAND (0x3L<<26)
1557#define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26)
1558#define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26)
1559#define BNX2_EMAC_MDIO_COMM_COMMAND_READ (2L<<26)
1560#define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26)
1561#define BNX2_EMAC_MDIO_COMM_FAIL (1L<<28)
1562#define BNX2_EMAC_MDIO_COMM_START_BUSY (1L<<29)
1563#define BNX2_EMAC_MDIO_COMM_DISEXT (1L<<30)
1564
1565#define BNX2_EMAC_MDIO_STATUS 0x000014b0
1566#define BNX2_EMAC_MDIO_STATUS_LINK (1L<<0)
1567#define BNX2_EMAC_MDIO_STATUS_10MB (1L<<1)
1568
1569#define BNX2_EMAC_MDIO_MODE 0x000014b4
1570#define BNX2_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1)
1571#define BNX2_EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
1572#define BNX2_EMAC_MDIO_MODE_BIT_BANG (1L<<8)
1573#define BNX2_EMAC_MDIO_MODE_MDIO (1L<<9)
1574#define BNX2_EMAC_MDIO_MODE_MDIO_OE (1L<<10)
1575#define BNX2_EMAC_MDIO_MODE_MDC (1L<<11)
1576#define BNX2_EMAC_MDIO_MODE_MDINT (1L<<12)
1577#define BNX2_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16)
1578
1579#define BNX2_EMAC_MDIO_AUTO_STATUS 0x000014b8
1580#define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0)
1581
1582#define BNX2_EMAC_TX_MODE 0x000014bc
1583#define BNX2_EMAC_TX_MODE_RESET (1L<<0)
1584#define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
1585#define BNX2_EMAC_TX_MODE_FLOW_EN (1L<<4)
1586#define BNX2_EMAC_TX_MODE_BIG_BACKOFF (1L<<5)
1587#define BNX2_EMAC_TX_MODE_LONG_PAUSE (1L<<6)
1588#define BNX2_EMAC_TX_MODE_LINK_AWARE (1L<<7)
1589
1590#define BNX2_EMAC_TX_STATUS 0x000014c0
1591#define BNX2_EMAC_TX_STATUS_XOFFED (1L<<0)
1592#define BNX2_EMAC_TX_STATUS_XOFF_SENT (1L<<1)
1593#define BNX2_EMAC_TX_STATUS_XON_SENT (1L<<2)
1594#define BNX2_EMAC_TX_STATUS_LINK_UP (1L<<3)
1595#define BNX2_EMAC_TX_STATUS_UNDERRUN (1L<<4)
1596
1597#define BNX2_EMAC_TX_LENGTHS 0x000014c4
1598#define BNX2_EMAC_TX_LENGTHS_SLOT (0xffL<<0)
1599#define BNX2_EMAC_TX_LENGTHS_IPG (0xfL<<8)
1600#define BNX2_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12)
1601
1602#define BNX2_EMAC_RX_MODE 0x000014c8
1603#define BNX2_EMAC_RX_MODE_RESET (1L<<0)
1604#define BNX2_EMAC_RX_MODE_FLOW_EN (1L<<2)
1605#define BNX2_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
1606#define BNX2_EMAC_RX_MODE_KEEP_PAUSE (1L<<4)
1607#define BNX2_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5)
1608#define BNX2_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6)
1609#define BNX2_EMAC_RX_MODE_LLC_CHK (1L<<7)
1610#define BNX2_EMAC_RX_MODE_PROMISCUOUS (1L<<8)
1611#define BNX2_EMAC_RX_MODE_NO_CRC_CHK (1L<<9)
1612#define BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
1613#define BNX2_EMAC_RX_MODE_FILT_BROADCAST (1L<<11)
1614#define BNX2_EMAC_RX_MODE_SORT_MODE (1L<<12)
1615
1616#define BNX2_EMAC_RX_STATUS 0x000014cc
1617#define BNX2_EMAC_RX_STATUS_FFED (1L<<0)
1618#define BNX2_EMAC_RX_STATUS_FF_RECEIVED (1L<<1)
1619#define BNX2_EMAC_RX_STATUS_N_RECEIVED (1L<<2)
1620
1621#define BNX2_EMAC_MULTICAST_HASH0 0x000014d0
1622#define BNX2_EMAC_MULTICAST_HASH1 0x000014d4
1623#define BNX2_EMAC_MULTICAST_HASH2 0x000014d8
1624#define BNX2_EMAC_MULTICAST_HASH3 0x000014dc
1625#define BNX2_EMAC_MULTICAST_HASH4 0x000014e0
1626#define BNX2_EMAC_MULTICAST_HASH5 0x000014e4
1627#define BNX2_EMAC_MULTICAST_HASH6 0x000014e8
1628#define BNX2_EMAC_MULTICAST_HASH7 0x000014ec
1629#define BNX2_EMAC_RX_STAT_IFHCINOCTETS 0x00001500
1630#define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504
1631#define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508
1632#define BNX2_EMAC_RX_STAT_IFHCINUCASTPKTS 0x0000150c
1633#define BNX2_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x00001510
1634#define BNX2_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x00001514
1635#define BNX2_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x00001518
1636#define BNX2_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x0000151c
1637#define BNX2_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x00001520
1638#define BNX2_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524
1639#define BNX2_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x00001528
1640#define BNX2_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x0000152c
1641#define BNX2_EMAC_RX_STAT_XOFFSTATEENTERED 0x00001530
1642#define BNX2_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534
1643#define BNX2_EMAC_RX_STAT_ETHERSTATSJABBERS 0x00001538
1644#define BNX2_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x0000153c
1645#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540
1646#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544
1647#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001548
1648#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c
1649#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550
1650#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554
1651#define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001558
1652#define BNX2_EMAC_RXMAC_DEBUG0 0x0000155c
1653#define BNX2_EMAC_RXMAC_DEBUG1 0x00001560
1654#define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0)
1655#define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1)
1656#define BNX2_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2)
1657#define BNX2_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3)
1658#define BNX2_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4)
1659#define BNX2_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5)
1660#define BNX2_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6)
1661#define BNX2_EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7)
1662#define BNX2_EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23)
1663
1664#define BNX2_EMAC_RXMAC_DEBUG2 0x00001564
1665#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0)
1666#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0x0L<<0)
1667#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SFD (0x1L<<0)
1668#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DATA (0x2L<<0)
1669#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (0x3L<<0)
1670#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_EXT (0x4L<<0)
1671#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DROP (0x5L<<0)
1672#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (0x6L<<0)
1673#define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_FC (0x7L<<0)
1674#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3)
1675#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0x0L<<3)
1676#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (0x1L<<3)
1677#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (0x2L<<3)
1678#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (0x3L<<3)
1679#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (0x4L<<3)
1680#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (0x5L<<3)
1681#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (0x6L<<3)
1682#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (0x7L<<3)
1683#define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (0x8L<<3)
1684#define BNX2_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7)
1685#define BNX2_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15)
1686#define BNX2_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16)
1687#define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18)
1688#define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18)
1689#define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18)
1690#define BNX2_EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19)
1691#define BNX2_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23)
1692
1693#define BNX2_EMAC_RXMAC_DEBUG3 0x00001568
1694#define BNX2_EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0)
1695#define BNX2_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16)
1696
1697#define BNX2_EMAC_RXMAC_DEBUG4 0x0000156c
1698#define BNX2_EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0)
1699#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16)
1700#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0x0L<<16)
1701#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16)
1702#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16)
1703#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16)
1704#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16)
1705#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16)
1706#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16)
1707#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16)
1708#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16)
1709#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16)
1710#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (0xaL<<16)
1711#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (0xeL<<16)
1712#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (0xfL<<16)
1713#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (0x10L<<16)
1714#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC (0x11L<<16)
1715#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (0x12L<<16)
1716#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (0x13L<<16)
1717#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (0x14L<<16)
1718#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (0x15L<<16)
1719#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (0x16L<<16)
1720#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (0x17L<<16)
1721#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC (0x18L<<16)
1722#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (0x19L<<16)
1723#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (0x1aL<<16)
1724#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (0x1bL<<16)
1725#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (0x1cL<<16)
1726#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (0x1dL<<16)
1727#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XON (0x1eL<<16)
1728#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (0x1fL<<16)
1729#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16)
1730#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (0x21L<<16)
1731#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (0x22L<<16)
1732#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (0x23L<<16)
1733#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (0x24L<<16)
1734#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (0x25L<<16)
1735#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (0x26L<<16)
1736#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (0x27L<<16)
1737#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (0x28L<<16)
1738#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (0x29L<<16)
1739#define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (0x2aL<<16)
1740#define BNX2_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22)
1741#define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23)
1742#define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24)
1743#define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25)
1744#define BNX2_EMAC_RXMAC_DEBUG4_sfd_FOUND (1L<<26)
1745#define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27)
1746#define BNX2_EMAC_RXMAC_DEBUG4_START (1L<<28)
1747
1748#define BNX2_EMAC_RXMAC_DEBUG5 0x00001570
1749#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0)
1750#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0)
1751#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0)
1752#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0)
1753#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0)
1754#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0)
1755#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0)
1756#define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0)
1757#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4)
1758#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0x0L<<4)
1759#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (0x1L<<4)
1760#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (0x2L<<4)
1761#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (0x3L<<4)
1762#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (0x4L<<4)
1763#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (0x6L<<4)
1764#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (0x7L<<4)
1765#define BNX2_EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7)
1766#define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8)
1767#define BNX2_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11)
1768#define BNX2_EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12)
1769#define BNX2_EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13)
1770#define BNX2_EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14)
1771#define BNX2_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15)
1772#define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16)
1773#define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19)
1774#define BNX2_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20)
1775
1776#define BNX2_EMAC_RX_STAT_AC0 0x00001580
1777#define BNX2_EMAC_RX_STAT_AC1 0x00001584
1778#define BNX2_EMAC_RX_STAT_AC2 0x00001588
1779#define BNX2_EMAC_RX_STAT_AC3 0x0000158c
1780#define BNX2_EMAC_RX_STAT_AC4 0x00001590
1781#define BNX2_EMAC_RX_STAT_AC5 0x00001594
1782#define BNX2_EMAC_RX_STAT_AC6 0x00001598
1783#define BNX2_EMAC_RX_STAT_AC7 0x0000159c
1784#define BNX2_EMAC_RX_STAT_AC8 0x000015a0
1785#define BNX2_EMAC_RX_STAT_AC9 0x000015a4
1786#define BNX2_EMAC_RX_STAT_AC10 0x000015a8
1787#define BNX2_EMAC_RX_STAT_AC11 0x000015ac
1788#define BNX2_EMAC_RX_STAT_AC12 0x000015b0
1789#define BNX2_EMAC_RX_STAT_AC13 0x000015b4
1790#define BNX2_EMAC_RX_STAT_AC14 0x000015b8
1791#define BNX2_EMAC_RX_STAT_AC15 0x000015bc
1792#define BNX2_EMAC_RX_STAT_AC16 0x000015c0
1793#define BNX2_EMAC_RX_STAT_AC17 0x000015c4
1794#define BNX2_EMAC_RX_STAT_AC18 0x000015c8
1795#define BNX2_EMAC_RX_STAT_AC19 0x000015cc
1796#define BNX2_EMAC_RX_STAT_AC20 0x000015d0
1797#define BNX2_EMAC_RX_STAT_AC21 0x000015d4
1798#define BNX2_EMAC_RX_STAT_AC22 0x000015d8
1799#define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc
1800#define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600
1801#define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604
1802#define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608
1803#define BNX2_EMAC_TX_STAT_OUTXONSENT 0x0000160c
1804#define BNX2_EMAC_TX_STAT_OUTXOFFSENT 0x00001610
1805#define BNX2_EMAC_TX_STAT_FLOWCONTROLDONE 0x00001614
1806#define BNX2_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x00001618
1807#define BNX2_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x0000161c
1808#define BNX2_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x00001620
1809#define BNX2_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x00001624
1810#define BNX2_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x00001628
1811#define BNX2_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x0000162c
1812#define BNX2_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x00001630
1813#define BNX2_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x00001634
1814#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x00001638
1815#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x0000163c
1816#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001640
1817#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644
1818#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648
1819#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c
1820#define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001650
1821#define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654
1822#define BNX2_EMAC_TXMAC_DEBUG0 0x00001658
1823#define BNX2_EMAC_TXMAC_DEBUG1 0x0000165c
1824#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0)
1825#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0x0L<<0)
1826#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (0x1L<<0)
1827#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (0x4L<<0)
1828#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (0x5L<<0)
1829#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (0x6L<<0)
1830#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (0x7L<<0)
1831#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (0x8L<<0)
1832#define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (0x9L<<0)
1833#define BNX2_EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4)
1834#define BNX2_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5)
1835#define BNX2_EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6)
1836#define BNX2_EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10)
1837#define BNX2_EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11)
1838#define BNX2_EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12)
1839#define BNX2_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13)
1840#define BNX2_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14)
1841#define BNX2_EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15)
1842#define BNX2_EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19)
1843
1844#define BNX2_EMAC_TXMAC_DEBUG2 0x00001660
1845#define BNX2_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0)
1846#define BNX2_EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10)
1847#define BNX2_EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26)
1848#define BNX2_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31)
1849
1850#define BNX2_EMAC_TXMAC_DEBUG3 0x00001664
1851#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0)
1852#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0x0L<<0)
1853#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (0x1L<<0)
1854#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (0x2L<<0)
1855#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SFD (0x3L<<0)
1856#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_DATA (0x4L<<0)
1857#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (0x5L<<0)
1858#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (0x6L<<0)
1859#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EXT (0x7L<<0)
1860#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATB (0x8L<<0)
1861#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATG (0x9L<<0)
1862#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_JAM (0xaL<<0)
1863#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (0xbL<<0)
1864#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (0xcL<<0)
1865#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (0xdL<<0)
1866#define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (0xeL<<0)
1867#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4)
1868#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0x0L<<4)
1869#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (0x1L<<4)
1870#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (0x2L<<4)
1871#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_MC (0x3L<<4)
1872#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (0x4L<<4)
1873#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (0x5L<<4)
1874#define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC (0x6L<<4)
1875#define BNX2_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7)
1876#define BNX2_EMAC_TXMAC_DEBUG3_XOFF (1L<<8)
1877#define BNX2_EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9)
1878#define BNX2_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13)
1879
1880#define BNX2_EMAC_TXMAC_DEBUG4 0x00001668
1881#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0)
1882#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16)
1883#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16)
1884#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16)
1885#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16)
1886#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16)
1887#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16)
1888#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16)
1889#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16)
1890#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16)
1891#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16)
1892#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16)
1893#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16)
1894#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16)
1895#define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16)
1896#define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20)
1897#define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21)
1898#define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22)
1899#define BNX2_EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23)
1900#define BNX2_EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24)
1901#define BNX2_EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25)
1902#define BNX2_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26)
1903#define BNX2_EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27)
1904#define BNX2_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28)
1905#define BNX2_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29)
1906#define BNX2_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30)
1907#define BNX2_EMAC_TXMAC_DEBUG4_GO (1L<<31)
1908
1909#define BNX2_EMAC_TX_STAT_AC0 0x00001680
1910#define BNX2_EMAC_TX_STAT_AC1 0x00001684
1911#define BNX2_EMAC_TX_STAT_AC2 0x00001688
1912#define BNX2_EMAC_TX_STAT_AC3 0x0000168c
1913#define BNX2_EMAC_TX_STAT_AC4 0x00001690
1914#define BNX2_EMAC_TX_STAT_AC5 0x00001694
1915#define BNX2_EMAC_TX_STAT_AC6 0x00001698
1916#define BNX2_EMAC_TX_STAT_AC7 0x0000169c
1917#define BNX2_EMAC_TX_STAT_AC8 0x000016a0
1918#define BNX2_EMAC_TX_STAT_AC9 0x000016a4
1919#define BNX2_EMAC_TX_STAT_AC10 0x000016a8
1920#define BNX2_EMAC_TX_STAT_AC11 0x000016ac
1921#define BNX2_EMAC_TX_STAT_AC12 0x000016b0
1922#define BNX2_EMAC_TX_STAT_AC13 0x000016b4
1923#define BNX2_EMAC_TX_STAT_AC14 0x000016b8
1924#define BNX2_EMAC_TX_STAT_AC15 0x000016bc
1925#define BNX2_EMAC_TX_STAT_AC16 0x000016c0
1926#define BNX2_EMAC_TX_STAT_AC17 0x000016c4
1927#define BNX2_EMAC_TX_STAT_AC18 0x000016c8
1928#define BNX2_EMAC_TX_STAT_AC19 0x000016cc
1929#define BNX2_EMAC_TX_STAT_AC20 0x000016d0
1930#define BNX2_EMAC_TX_STAT_AC21 0x000016d4
1931#define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8
1932
1933
1934/*
1935 * rpm_reg definition
1936 * offset: 0x1800
1937 */
1938#define BNX2_RPM_COMMAND 0x00001800
1939#define BNX2_RPM_COMMAND_ENABLED (1L<<0)
1940#define BNX2_RPM_COMMAND_OVERRUN_ABORT (1L<<4)
1941
1942#define BNX2_RPM_STATUS 0x00001804
1943#define BNX2_RPM_STATUS_MBUF_WAIT (1L<<0)
1944#define BNX2_RPM_STATUS_FREE_WAIT (1L<<1)
1945
1946#define BNX2_RPM_CONFIG 0x00001808
1947#define BNX2_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0)
1948#define BNX2_RPM_CONFIG_ACPI_ENA (1L<<1)
1949#define BNX2_RPM_CONFIG_ACPI_KEEP (1L<<2)
1950#define BNX2_RPM_CONFIG_MP_KEEP (1L<<3)
1951#define BNX2_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4)
1952#define BNX2_RPM_CONFIG_IGNORE_VLAN (1L<<31)
1953
1954#define BNX2_RPM_VLAN_MATCH0 0x00001810
1955#define BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0)
1956
1957#define BNX2_RPM_VLAN_MATCH1 0x00001814
1958#define BNX2_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffL<<0)
1959
1960#define BNX2_RPM_VLAN_MATCH2 0x00001818
1961#define BNX2_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffL<<0)
1962
1963#define BNX2_RPM_VLAN_MATCH3 0x0000181c
1964#define BNX2_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffL<<0)
1965
1966#define BNX2_RPM_SORT_USER0 0x00001820
1967#define BNX2_RPM_SORT_USER0_PM_EN (0xffffL<<0)
1968#define BNX2_RPM_SORT_USER0_BC_EN (1L<<16)
1969#define BNX2_RPM_SORT_USER0_MC_EN (1L<<17)
1970#define BNX2_RPM_SORT_USER0_MC_HSH_EN (1L<<18)
1971#define BNX2_RPM_SORT_USER0_PROM_EN (1L<<19)
1972#define BNX2_RPM_SORT_USER0_VLAN_EN (0xfL<<20)
1973#define BNX2_RPM_SORT_USER0_PROM_VLAN (1L<<24)
1974#define BNX2_RPM_SORT_USER0_ENA (1L<<31)
1975
1976#define BNX2_RPM_SORT_USER1 0x00001824
1977#define BNX2_RPM_SORT_USER1_PM_EN (0xffffL<<0)
1978#define BNX2_RPM_SORT_USER1_BC_EN (1L<<16)
1979#define BNX2_RPM_SORT_USER1_MC_EN (1L<<17)
1980#define BNX2_RPM_SORT_USER1_MC_HSH_EN (1L<<18)
1981#define BNX2_RPM_SORT_USER1_PROM_EN (1L<<19)
1982#define BNX2_RPM_SORT_USER1_VLAN_EN (0xfL<<20)
1983#define BNX2_RPM_SORT_USER1_PROM_VLAN (1L<<24)
1984#define BNX2_RPM_SORT_USER1_ENA (1L<<31)
1985
1986#define BNX2_RPM_SORT_USER2 0x00001828
1987#define BNX2_RPM_SORT_USER2_PM_EN (0xffffL<<0)
1988#define BNX2_RPM_SORT_USER2_BC_EN (1L<<16)
1989#define BNX2_RPM_SORT_USER2_MC_EN (1L<<17)
1990#define BNX2_RPM_SORT_USER2_MC_HSH_EN (1L<<18)
1991#define BNX2_RPM_SORT_USER2_PROM_EN (1L<<19)
1992#define BNX2_RPM_SORT_USER2_VLAN_EN (0xfL<<20)
1993#define BNX2_RPM_SORT_USER2_PROM_VLAN (1L<<24)
1994#define BNX2_RPM_SORT_USER2_ENA (1L<<31)
1995
1996#define BNX2_RPM_SORT_USER3 0x0000182c
1997#define BNX2_RPM_SORT_USER3_PM_EN (0xffffL<<0)
1998#define BNX2_RPM_SORT_USER3_BC_EN (1L<<16)
1999#define BNX2_RPM_SORT_USER3_MC_EN (1L<<17)
2000#define BNX2_RPM_SORT_USER3_MC_HSH_EN (1L<<18)
2001#define BNX2_RPM_SORT_USER3_PROM_EN (1L<<19)
2002#define BNX2_RPM_SORT_USER3_VLAN_EN (0xfL<<20)
2003#define BNX2_RPM_SORT_USER3_PROM_VLAN (1L<<24)
2004#define BNX2_RPM_SORT_USER3_ENA (1L<<31)
2005
2006#define BNX2_RPM_STAT_L2_FILTER_DISCARDS 0x00001840
2007#define BNX2_RPM_STAT_RULE_CHECKER_DISCARDS 0x00001844
2008#define BNX2_RPM_STAT_IFINFTQDISCARDS 0x00001848
2009#define BNX2_RPM_STAT_IFINMBUFDISCARD 0x0000184c
2010#define BNX2_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850
2011#define BNX2_RPM_STAT_AC0 0x00001880
2012#define BNX2_RPM_STAT_AC1 0x00001884
2013#define BNX2_RPM_STAT_AC2 0x00001888
2014#define BNX2_RPM_STAT_AC3 0x0000188c
2015#define BNX2_RPM_STAT_AC4 0x00001890
2016#define BNX2_RPM_RC_CNTL_0 0x00001900
2017#define BNX2_RPM_RC_CNTL_0_OFFSET (0xffL<<0)
2018#define BNX2_RPM_RC_CNTL_0_CLASS (0x7L<<8)
2019#define BNX2_RPM_RC_CNTL_0_PRIORITY (1L<<11)
2020#define BNX2_RPM_RC_CNTL_0_P4 (1L<<12)
2021#define BNX2_RPM_RC_CNTL_0_HDR_TYPE (0x7L<<13)
2022#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13)
2023#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13)
2024#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13)
2025#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13)
2026#define BNX2_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13)
2027#define BNX2_RPM_RC_CNTL_0_COMP (0x3L<<16)
2028#define BNX2_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16)
2029#define BNX2_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16)
2030#define BNX2_RPM_RC_CNTL_0_COMP_GREATER (2L<<16)
2031#define BNX2_RPM_RC_CNTL_0_COMP_LESS (3L<<16)
2032#define BNX2_RPM_RC_CNTL_0_SBIT (1L<<19)
2033#define BNX2_RPM_RC_CNTL_0_CMDSEL (0xfL<<20)
2034#define BNX2_RPM_RC_CNTL_0_MAP (1L<<24)
2035#define BNX2_RPM_RC_CNTL_0_DISCARD (1L<<25)
2036#define BNX2_RPM_RC_CNTL_0_MASK (1L<<26)
2037#define BNX2_RPM_RC_CNTL_0_P1 (1L<<27)
2038#define BNX2_RPM_RC_CNTL_0_P2 (1L<<28)
2039#define BNX2_RPM_RC_CNTL_0_P3 (1L<<29)
2040#define BNX2_RPM_RC_CNTL_0_NBIT (1L<<30)
2041
2042#define BNX2_RPM_RC_VALUE_MASK_0 0x00001904
2043#define BNX2_RPM_RC_VALUE_MASK_0_VALUE (0xffffL<<0)
2044#define BNX2_RPM_RC_VALUE_MASK_0_MASK (0xffffL<<16)
2045
2046#define BNX2_RPM_RC_CNTL_1 0x00001908
2047#define BNX2_RPM_RC_CNTL_1_A (0x3ffffL<<0)
2048#define BNX2_RPM_RC_CNTL_1_B (0xfffL<<19)
2049
2050#define BNX2_RPM_RC_VALUE_MASK_1 0x0000190c
2051#define BNX2_RPM_RC_CNTL_2 0x00001910
2052#define BNX2_RPM_RC_CNTL_2_A (0x3ffffL<<0)
2053#define BNX2_RPM_RC_CNTL_2_B (0xfffL<<19)
2054
2055#define BNX2_RPM_RC_VALUE_MASK_2 0x00001914
2056#define BNX2_RPM_RC_CNTL_3 0x00001918
2057#define BNX2_RPM_RC_CNTL_3_A (0x3ffffL<<0)
2058#define BNX2_RPM_RC_CNTL_3_B (0xfffL<<19)
2059
2060#define BNX2_RPM_RC_VALUE_MASK_3 0x0000191c
2061#define BNX2_RPM_RC_CNTL_4 0x00001920
2062#define BNX2_RPM_RC_CNTL_4_A (0x3ffffL<<0)
2063#define BNX2_RPM_RC_CNTL_4_B (0xfffL<<19)
2064
2065#define BNX2_RPM_RC_VALUE_MASK_4 0x00001924
2066#define BNX2_RPM_RC_CNTL_5 0x00001928
2067#define BNX2_RPM_RC_CNTL_5_A (0x3ffffL<<0)
2068#define BNX2_RPM_RC_CNTL_5_B (0xfffL<<19)
2069
2070#define BNX2_RPM_RC_VALUE_MASK_5 0x0000192c
2071#define BNX2_RPM_RC_CNTL_6 0x00001930
2072#define BNX2_RPM_RC_CNTL_6_A (0x3ffffL<<0)
2073#define BNX2_RPM_RC_CNTL_6_B (0xfffL<<19)
2074
2075#define BNX2_RPM_RC_VALUE_MASK_6 0x00001934
2076#define BNX2_RPM_RC_CNTL_7 0x00001938
2077#define BNX2_RPM_RC_CNTL_7_A (0x3ffffL<<0)
2078#define BNX2_RPM_RC_CNTL_7_B (0xfffL<<19)
2079
2080#define BNX2_RPM_RC_VALUE_MASK_7 0x0000193c
2081#define BNX2_RPM_RC_CNTL_8 0x00001940
2082#define BNX2_RPM_RC_CNTL_8_A (0x3ffffL<<0)
2083#define BNX2_RPM_RC_CNTL_8_B (0xfffL<<19)
2084
2085#define BNX2_RPM_RC_VALUE_MASK_8 0x00001944
2086#define BNX2_RPM_RC_CNTL_9 0x00001948
2087#define BNX2_RPM_RC_CNTL_9_A (0x3ffffL<<0)
2088#define BNX2_RPM_RC_CNTL_9_B (0xfffL<<19)
2089
2090#define BNX2_RPM_RC_VALUE_MASK_9 0x0000194c
2091#define BNX2_RPM_RC_CNTL_10 0x00001950
2092#define BNX2_RPM_RC_CNTL_10_A (0x3ffffL<<0)
2093#define BNX2_RPM_RC_CNTL_10_B (0xfffL<<19)
2094
2095#define BNX2_RPM_RC_VALUE_MASK_10 0x00001954
2096#define BNX2_RPM_RC_CNTL_11 0x00001958
2097#define BNX2_RPM_RC_CNTL_11_A (0x3ffffL<<0)
2098#define BNX2_RPM_RC_CNTL_11_B (0xfffL<<19)
2099
2100#define BNX2_RPM_RC_VALUE_MASK_11 0x0000195c
2101#define BNX2_RPM_RC_CNTL_12 0x00001960
2102#define BNX2_RPM_RC_CNTL_12_A (0x3ffffL<<0)
2103#define BNX2_RPM_RC_CNTL_12_B (0xfffL<<19)
2104
2105#define BNX2_RPM_RC_VALUE_MASK_12 0x00001964
2106#define BNX2_RPM_RC_CNTL_13 0x00001968
2107#define BNX2_RPM_RC_CNTL_13_A (0x3ffffL<<0)
2108#define BNX2_RPM_RC_CNTL_13_B (0xfffL<<19)
2109
2110#define BNX2_RPM_RC_VALUE_MASK_13 0x0000196c
2111#define BNX2_RPM_RC_CNTL_14 0x00001970
2112#define BNX2_RPM_RC_CNTL_14_A (0x3ffffL<<0)
2113#define BNX2_RPM_RC_CNTL_14_B (0xfffL<<19)
2114
2115#define BNX2_RPM_RC_VALUE_MASK_14 0x00001974
2116#define BNX2_RPM_RC_CNTL_15 0x00001978
2117#define BNX2_RPM_RC_CNTL_15_A (0x3ffffL<<0)
2118#define BNX2_RPM_RC_CNTL_15_B (0xfffL<<19)
2119
2120#define BNX2_RPM_RC_VALUE_MASK_15 0x0000197c
2121#define BNX2_RPM_RC_CONFIG 0x00001980
2122#define BNX2_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0)
2123#define BNX2_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24)
2124
2125#define BNX2_RPM_DEBUG0 0x00001984
2126#define BNX2_RPM_DEBUG0_FM_BCNT (0xffffL<<0)
2127#define BNX2_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16)
2128#define BNX2_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17)
2129#define BNX2_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18)
2130#define BNX2_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19)
2131#define BNX2_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20)
2132#define BNX2_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1L<<21)
2133#define BNX2_RPM_DEBUG0_LLC_SNAP (1L<<22)
2134#define BNX2_RPM_DEBUG0_FM_STARTED (1L<<23)
2135#define BNX2_RPM_DEBUG0_DONE (1L<<24)
2136#define BNX2_RPM_DEBUG0_WAIT_4_DONE (1L<<25)
2137#define BNX2_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26)
2138#define BNX2_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27)
2139#define BNX2_RPM_DEBUG0_IGNORE_VLAN (1L<<28)
2140#define BNX2_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31)
2141
2142#define BNX2_RPM_DEBUG1 0x00001988
2143#define BNX2_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0)
2144#define BNX2_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0)
2145#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0)
2146#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0)
2147#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0)
2148#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0)
2149#define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0)
2150#define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0)
2151#define BNX2_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0)
2152#define BNX2_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0)
2153#define BNX2_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0)
2154#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0)
2155#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0)
2156#define BNX2_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0)
2157#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (0x2000L<<0)
2158#define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (0x4000L<<0)
2159#define BNX2_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (0x8000L<<0)
2160#define BNX2_RPM_DEBUG1_HDR_BCNT (0x7ffL<<16)
2161#define BNX2_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28)
2162#define BNX2_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29)
2163#define BNX2_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30)
2164#define BNX2_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31)
2165
2166#define BNX2_RPM_DEBUG2 0x0000198c
2167#define BNX2_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0)
2168#define BNX2_RPM_DEBUG2_IP_BCNT (0xffL<<16)
2169#define BNX2_RPM_DEBUG2_THIS_CMD_M4 (1L<<24)
2170#define BNX2_RPM_DEBUG2_THIS_CMD_M3 (1L<<25)
2171#define BNX2_RPM_DEBUG2_THIS_CMD_M2 (1L<<26)
2172#define BNX2_RPM_DEBUG2_THIS_CMD_M1 (1L<<27)
2173#define BNX2_RPM_DEBUG2_IPIPE_EMPTY (1L<<28)
2174#define BNX2_RPM_DEBUG2_FM_DISCARD (1L<<29)
2175#define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30)
2176#define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31)
2177
2178#define BNX2_RPM_DEBUG3 0x00001990
2179#define BNX2_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0)
2180#define BNX2_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1L<<9)
2181#define BNX2_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1L<<10)
2182#define BNX2_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1L<<11)
2183#define BNX2_RPM_DEBUG3_RDE_RBUF_FREE_REQ (1L<<12)
2184#define BNX2_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1L<<13)
2185#define BNX2_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1L<<14)
2186#define BNX2_RPM_DEBUG3_RBUF_RDE_SOF_DROP (1L<<15)
2187#define BNX2_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfL<<16)
2188#define BNX2_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1L<<21)
2189#define BNX2_RPM_DEBUG3_DROP_NXT_VLD (1L<<22)
2190#define BNX2_RPM_DEBUG3_DROP_NXT (1L<<23)
2191#define BNX2_RPM_DEBUG3_FTQ_FSM (0x3L<<24)
2192#define BNX2_RPM_DEBUG3_FTQ_FSM_IDLE (0x0L<<24)
2193#define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_ACK (0x1L<<24)
2194#define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_FREE (0x2L<<24)
2195#define BNX2_RPM_DEBUG3_MBWRITE_FSM (0x3L<<26)
2196#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0x0L<<26)
2197#define BNX2_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (0x1L<<26)
2198#define BNX2_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (0x2L<<26)
2199#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (0x3L<<26)
2200#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (0x4L<<26)
2201#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (0x5L<<26)
2202#define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (0x6L<<26)
2203#define BNX2_RPM_DEBUG3_MBWRITE_FSM_DONE (0x7L<<26)
2204#define BNX2_RPM_DEBUG3_MBFREE_FSM (1L<<29)
2205#define BNX2_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29)
2206#define BNX2_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1L<<29)
2207#define BNX2_RPM_DEBUG3_MBALLOC_FSM (1L<<30)
2208#define BNX2_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0x0L<<30)
2209#define BNX2_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (0x1L<<30)
2210#define BNX2_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31)
2211
2212#define BNX2_RPM_DEBUG4 0x00001994
2213#define BNX2_RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffL<<0)
2214#define BNX2_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25)
2215#define BNX2_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28)
2216#define BNX2_RPM_DEBUG4_DFIFO_EMPTY (1L<<31)
2217
2218#define BNX2_RPM_DEBUG5 0x00001998
2219#define BNX2_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0)
2220#define BNX2_RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fL<<5)
2221#define BNX2_RPM_DEBUG5_RDROP_MC_RPTR (0x1fL<<10)
2222#define BNX2_RPM_DEBUG5_RDROP_RC_RPTR (0x1fL<<15)
2223#define BNX2_RPM_DEBUG5_RDROP_ACPI_EMPTY (1L<<20)
2224#define BNX2_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21)
2225#define BNX2_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1L<<22)
2226#define BNX2_RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1L<<23)
2227#define BNX2_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24)
2228#define BNX2_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1L<<25)
2229#define BNX2_RPM_DEBUG5_HOLDREG_MC_EMPTY (1L<<26)
2230#define BNX2_RPM_DEBUG5_HOLDREG_RC_EMPTY (1L<<27)
2231#define BNX2_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28)
2232#define BNX2_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29)
2233#define BNX2_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30)
2234#define BNX2_RPM_DEBUG5_HOLDREG_RD (1L<<31)
2235
2236#define BNX2_RPM_DEBUG6 0x0000199c
2237#define BNX2_RPM_DEBUG6_ACPI_VEC (0xffffL<<0)
2238#define BNX2_RPM_DEBUG6_VEC (0xffffL<<16)
2239
2240#define BNX2_RPM_DEBUG7 0x000019a0
2241#define BNX2_RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffL<<0)
2242
2243#define BNX2_RPM_DEBUG8 0x000019a4
2244#define BNX2_RPM_DEBUG8_PS_ACPI_FSM (0xfL<<0)
2245#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0)
2246#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0)
2247#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0)
2248#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0)
2249#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0)
2250#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0)
2251#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0)
2252#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0)
2253#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0)
2254#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0)
2255#define BNX2_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0)
2256#define BNX2_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4)
2257#define BNX2_RPM_DEBUG8_COMPARE_AT_W3_DATA (1L<<5)
2258#define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1L<<6)
2259#define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W3 (1L<<7)
2260#define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W2 (1L<<8)
2261#define BNX2_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1L<<9)
2262#define BNX2_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1L<<10)
2263#define BNX2_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1L<<11)
2264#define BNX2_RPM_DEBUG8_EOF_DET (1L<<12)
2265#define BNX2_RPM_DEBUG8_SOF_DET (1L<<13)
2266#define BNX2_RPM_DEBUG8_WAIT_4_SOF (1L<<14)
2267#define BNX2_RPM_DEBUG8_ALL_DONE (1L<<15)
2268#define BNX2_RPM_DEBUG8_THBUF_ADDR (0x7fL<<16)
2269#define BNX2_RPM_DEBUG8_BYTE_CTR (0xffL<<24)
2270
2271#define BNX2_RPM_DEBUG9 0x000019a8
2272#define BNX2_RPM_DEBUG9_OUTFIFO_COUNT (0x7L<<0)
2273#define BNX2_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3)
2274#define BNX2_RPM_DEBUG9_VLD_RD_ENTRY_CT (0x7L<<4)
2275#define BNX2_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28)
2276#define BNX2_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29)
2277#define BNX2_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30)
2278#define BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31)
2279
2280#define BNX2_RPM_ACPI_DBG_BUF_W00 0x000019c0
2281#define BNX2_RPM_ACPI_DBG_BUF_W01 0x000019c4
2282#define BNX2_RPM_ACPI_DBG_BUF_W02 0x000019c8
2283#define BNX2_RPM_ACPI_DBG_BUF_W03 0x000019cc
2284#define BNX2_RPM_ACPI_DBG_BUF_W10 0x000019d0
2285#define BNX2_RPM_ACPI_DBG_BUF_W11 0x000019d4
2286#define BNX2_RPM_ACPI_DBG_BUF_W12 0x000019d8
2287#define BNX2_RPM_ACPI_DBG_BUF_W13 0x000019dc
2288#define BNX2_RPM_ACPI_DBG_BUF_W20 0x000019e0
2289#define BNX2_RPM_ACPI_DBG_BUF_W21 0x000019e4
2290#define BNX2_RPM_ACPI_DBG_BUF_W22 0x000019e8
2291#define BNX2_RPM_ACPI_DBG_BUF_W23 0x000019ec
2292#define BNX2_RPM_ACPI_DBG_BUF_W30 0x000019f0
2293#define BNX2_RPM_ACPI_DBG_BUF_W31 0x000019f4
2294#define BNX2_RPM_ACPI_DBG_BUF_W32 0x000019f8
2295#define BNX2_RPM_ACPI_DBG_BUF_W33 0x000019fc
2296
2297
2298/*
2299 * rbuf_reg definition
2300 * offset: 0x200000
2301 */
2302#define BNX2_RBUF_COMMAND 0x00200000
2303#define BNX2_RBUF_COMMAND_ENABLED (1L<<0)
2304#define BNX2_RBUF_COMMAND_FREE_INIT (1L<<1)
2305#define BNX2_RBUF_COMMAND_RAM_INIT (1L<<2)
2306#define BNX2_RBUF_COMMAND_OVER_FREE (1L<<4)
2307#define BNX2_RBUF_COMMAND_ALLOC_REQ (1L<<5)
2308
2309#define BNX2_RBUF_STATUS1 0x00200004
2310#define BNX2_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0)
2311
2312#define BNX2_RBUF_STATUS2 0x00200008
2313#define BNX2_RBUF_STATUS2_FREE_TAIL (0x3ffL<<0)
2314#define BNX2_RBUF_STATUS2_FREE_HEAD (0x3ffL<<16)
2315
2316#define BNX2_RBUF_CONFIG 0x0020000c
2317#define BNX2_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0)
2318#define BNX2_RBUF_CONFIG_XON_TRIP (0x3ffL<<16)
2319
2320#define BNX2_RBUF_FW_BUF_ALLOC 0x00200010
2321#define BNX2_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7)
2322
2323#define BNX2_RBUF_FW_BUF_FREE 0x00200014
2324#define BNX2_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0)
2325#define BNX2_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7)
2326#define BNX2_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16)
2327
2328#define BNX2_RBUF_FW_BUF_SEL 0x00200018
2329#define BNX2_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0)
2330#define BNX2_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7)
2331#define BNX2_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16)
2332
2333#define BNX2_RBUF_CONFIG2 0x0020001c
2334#define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0)
2335#define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16)
2336
2337#define BNX2_RBUF_CONFIG3 0x00200020
2338#define BNX2_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0)
2339#define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16)
2340
2341#define BNX2_RBUF_PKT_DATA 0x00208000
2342#define BNX2_RBUF_CLIST_DATA 0x00210000
2343#define BNX2_RBUF_BUF_DATA 0x00220000
2344
2345
2346/*
2347 * rv2p_reg definition
2348 * offset: 0x2800
2349 */
2350#define BNX2_RV2P_COMMAND 0x00002800
2351#define BNX2_RV2P_COMMAND_ENABLED (1L<<0)
2352#define BNX2_RV2P_COMMAND_PROC1_INTRPT (1L<<1)
2353#define BNX2_RV2P_COMMAND_PROC2_INTRPT (1L<<2)
2354#define BNX2_RV2P_COMMAND_ABORT0 (1L<<4)
2355#define BNX2_RV2P_COMMAND_ABORT1 (1L<<5)
2356#define BNX2_RV2P_COMMAND_ABORT2 (1L<<6)
2357#define BNX2_RV2P_COMMAND_ABORT3 (1L<<7)
2358#define BNX2_RV2P_COMMAND_ABORT4 (1L<<8)
2359#define BNX2_RV2P_COMMAND_ABORT5 (1L<<9)
2360#define BNX2_RV2P_COMMAND_PROC1_RESET (1L<<16)
2361#define BNX2_RV2P_COMMAND_PROC2_RESET (1L<<17)
2362#define BNX2_RV2P_COMMAND_CTXIF_RESET (1L<<18)
2363
2364#define BNX2_RV2P_STATUS 0x00002804
2365#define BNX2_RV2P_STATUS_ALWAYS_0 (1L<<0)
2366#define BNX2_RV2P_STATUS_RV2P_GEN_STAT0_CNT (1L<<8)
2367#define BNX2_RV2P_STATUS_RV2P_GEN_STAT1_CNT (1L<<9)
2368#define BNX2_RV2P_STATUS_RV2P_GEN_STAT2_CNT (1L<<10)
2369#define BNX2_RV2P_STATUS_RV2P_GEN_STAT3_CNT (1L<<11)
2370#define BNX2_RV2P_STATUS_RV2P_GEN_STAT4_CNT (1L<<12)
2371#define BNX2_RV2P_STATUS_RV2P_GEN_STAT5_CNT (1L<<13)
2372
2373#define BNX2_RV2P_CONFIG 0x00002808
2374#define BNX2_RV2P_CONFIG_STALL_PROC1 (1L<<0)
2375#define BNX2_RV2P_CONFIG_STALL_PROC2 (1L<<1)
2376#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1L<<8)
2377#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1L<<9)
2378#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1L<<10)
2379#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1L<<11)
2380#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1L<<12)
2381#define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1L<<13)
2382#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1L<<16)
2383#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1L<<17)
2384#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1L<<18)
2385#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1L<<19)
2386#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1L<<20)
2387#define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1L<<21)
2388#define BNX2_RV2P_CONFIG_PAGE_SIZE (0xfL<<24)
2389#define BNX2_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24)
2390#define BNX2_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24)
2391#define BNX2_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24)
2392#define BNX2_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24)
2393#define BNX2_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24)
2394#define BNX2_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24)
2395#define BNX2_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24)
2396#define BNX2_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24)
2397#define BNX2_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24)
2398#define BNX2_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24)
2399#define BNX2_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24)
2400#define BNX2_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24)
2401#define BNX2_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24)
2402
2403#define BNX2_RV2P_GEN_BFR_ADDR_0 0x00002810
2404#define BNX2_RV2P_GEN_BFR_ADDR_0_VALUE (0xffffL<<16)
2405
2406#define BNX2_RV2P_GEN_BFR_ADDR_1 0x00002814
2407#define BNX2_RV2P_GEN_BFR_ADDR_1_VALUE (0xffffL<<16)
2408
2409#define BNX2_RV2P_GEN_BFR_ADDR_2 0x00002818
2410#define BNX2_RV2P_GEN_BFR_ADDR_2_VALUE (0xffffL<<16)
2411
2412#define BNX2_RV2P_GEN_BFR_ADDR_3 0x0000281c
2413#define BNX2_RV2P_GEN_BFR_ADDR_3_VALUE (0xffffL<<16)
2414
2415#define BNX2_RV2P_INSTR_HIGH 0x00002830
2416#define BNX2_RV2P_INSTR_HIGH_HIGH (0x1fL<<0)
2417
2418#define BNX2_RV2P_INSTR_LOW 0x00002834
2419#define BNX2_RV2P_PROC1_ADDR_CMD 0x00002838
2420#define BNX2_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0)
2421#define BNX2_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31)
2422
2423#define BNX2_RV2P_PROC2_ADDR_CMD 0x0000283c
2424#define BNX2_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0)
2425#define BNX2_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31)
2426
2427#define BNX2_RV2P_PROC1_GRC_DEBUG 0x00002840
2428#define BNX2_RV2P_PROC2_GRC_DEBUG 0x00002844
2429#define BNX2_RV2P_GRC_PROC_DEBUG 0x00002848
2430#define BNX2_RV2P_DEBUG_VECT_PEEK 0x0000284c
2431#define BNX2_RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
2432#define BNX2_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
2433#define BNX2_RV2P_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
2434#define BNX2_RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
2435#define BNX2_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
2436#define BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
2437
2438#define BNX2_RV2P_PFTQ_DATA 0x00002b40
2439#define BNX2_RV2P_PFTQ_CMD 0x00002b78
2440#define BNX2_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0)
2441#define BNX2_RV2P_PFTQ_CMD_WR_TOP (1L<<10)
2442#define BNX2_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10)
2443#define BNX2_RV2P_PFTQ_CMD_WR_TOP_1 (1L<<10)
2444#define BNX2_RV2P_PFTQ_CMD_SFT_RESET (1L<<25)
2445#define BNX2_RV2P_PFTQ_CMD_RD_DATA (1L<<26)
2446#define BNX2_RV2P_PFTQ_CMD_ADD_INTERVEN (1L<<27)
2447#define BNX2_RV2P_PFTQ_CMD_ADD_DATA (1L<<28)
2448#define BNX2_RV2P_PFTQ_CMD_INTERVENE_CLR (1L<<29)
2449#define BNX2_RV2P_PFTQ_CMD_POP (1L<<30)
2450#define BNX2_RV2P_PFTQ_CMD_BUSY (1L<<31)
2451
2452#define BNX2_RV2P_PFTQ_CTL 0x00002b7c
2453#define BNX2_RV2P_PFTQ_CTL_INTERVENE (1L<<0)
2454#define BNX2_RV2P_PFTQ_CTL_OVERFLOW (1L<<1)
2455#define BNX2_RV2P_PFTQ_CTL_FORCE_INTERVENE (1L<<2)
2456#define BNX2_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
2457#define BNX2_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
2458
2459#define BNX2_RV2P_TFTQ_DATA 0x00002b80
2460#define BNX2_RV2P_TFTQ_CMD 0x00002bb8
2461#define BNX2_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0)
2462#define BNX2_RV2P_TFTQ_CMD_WR_TOP (1L<<10)
2463#define BNX2_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10)
2464#define BNX2_RV2P_TFTQ_CMD_WR_TOP_1 (1L<<10)
2465#define BNX2_RV2P_TFTQ_CMD_SFT_RESET (1L<<25)
2466#define BNX2_RV2P_TFTQ_CMD_RD_DATA (1L<<26)
2467#define BNX2_RV2P_TFTQ_CMD_ADD_INTERVEN (1L<<27)
2468#define BNX2_RV2P_TFTQ_CMD_ADD_DATA (1L<<28)
2469#define BNX2_RV2P_TFTQ_CMD_INTERVENE_CLR (1L<<29)
2470#define BNX2_RV2P_TFTQ_CMD_POP (1L<<30)
2471#define BNX2_RV2P_TFTQ_CMD_BUSY (1L<<31)
2472
2473#define BNX2_RV2P_TFTQ_CTL 0x00002bbc
2474#define BNX2_RV2P_TFTQ_CTL_INTERVENE (1L<<0)
2475#define BNX2_RV2P_TFTQ_CTL_OVERFLOW (1L<<1)
2476#define BNX2_RV2P_TFTQ_CTL_FORCE_INTERVENE (1L<<2)
2477#define BNX2_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
2478#define BNX2_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
2479
2480#define BNX2_RV2P_MFTQ_DATA 0x00002bc0
2481#define BNX2_RV2P_MFTQ_CMD 0x00002bf8
2482#define BNX2_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0)
2483#define BNX2_RV2P_MFTQ_CMD_WR_TOP (1L<<10)
2484#define BNX2_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10)
2485#define BNX2_RV2P_MFTQ_CMD_WR_TOP_1 (1L<<10)
2486#define BNX2_RV2P_MFTQ_CMD_SFT_RESET (1L<<25)
2487#define BNX2_RV2P_MFTQ_CMD_RD_DATA (1L<<26)
2488#define BNX2_RV2P_MFTQ_CMD_ADD_INTERVEN (1L<<27)
2489#define BNX2_RV2P_MFTQ_CMD_ADD_DATA (1L<<28)
2490#define BNX2_RV2P_MFTQ_CMD_INTERVENE_CLR (1L<<29)
2491#define BNX2_RV2P_MFTQ_CMD_POP (1L<<30)
2492#define BNX2_RV2P_MFTQ_CMD_BUSY (1L<<31)
2493
2494#define BNX2_RV2P_MFTQ_CTL 0x00002bfc
2495#define BNX2_RV2P_MFTQ_CTL_INTERVENE (1L<<0)
2496#define BNX2_RV2P_MFTQ_CTL_OVERFLOW (1L<<1)
2497#define BNX2_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2)
2498#define BNX2_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
2499#define BNX2_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
2500
2501
2502
2503/*
2504 * mq_reg definition
2505 * offset: 0x3c00
2506 */
2507#define BNX2_MQ_COMMAND 0x00003c00
2508#define BNX2_MQ_COMMAND_ENABLED (1L<<0)
2509#define BNX2_MQ_COMMAND_OVERFLOW (1L<<4)
2510#define BNX2_MQ_COMMAND_WR_ERROR (1L<<5)
2511#define BNX2_MQ_COMMAND_RD_ERROR (1L<<6)
2512
2513#define BNX2_MQ_STATUS 0x00003c04
2514#define BNX2_MQ_STATUS_CTX_ACCESS_STAT (1L<<16)
2515#define BNX2_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17)
2516#define BNX2_MQ_STATUS_PCI_STALL_STAT (1L<<18)
2517
2518#define BNX2_MQ_CONFIG 0x00003c08
2519#define BNX2_MQ_CONFIG_TX_HIGH_PRI (1L<<0)
2520#define BNX2_MQ_CONFIG_HALT_DIS (1L<<1)
2521#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4)
2522#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4)
2523#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4)
2524#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4)
2525#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4)
2526#define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4)
2527#define BNX2_MQ_CONFIG_MAX_DEPTH (0x7fL<<8)
2528#define BNX2_MQ_CONFIG_CUR_DEPTH (0x7fL<<20)
2529
2530#define BNX2_MQ_ENQUEUE1 0x00003c0c
2531#define BNX2_MQ_ENQUEUE1_OFFSET (0x3fL<<2)
2532#define BNX2_MQ_ENQUEUE1_CID (0x3fffL<<8)
2533#define BNX2_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24)
2534#define BNX2_MQ_ENQUEUE1_KNL_MODE (1L<<28)
2535
2536#define BNX2_MQ_ENQUEUE2 0x00003c10
2537#define BNX2_MQ_BAD_WR_ADDR 0x00003c14
2538#define BNX2_MQ_BAD_RD_ADDR 0x00003c18
2539#define BNX2_MQ_KNL_BYP_WIND_START 0x00003c1c
2540#define BNX2_MQ_KNL_BYP_WIND_START_VALUE (0xfffffL<<12)
2541
2542#define BNX2_MQ_KNL_WIND_END 0x00003c20
2543#define BNX2_MQ_KNL_WIND_END_VALUE (0xffffffL<<8)
2544
2545#define BNX2_MQ_KNL_WRITE_MASK1 0x00003c24
2546#define BNX2_MQ_KNL_TX_MASK1 0x00003c28
2547#define BNX2_MQ_KNL_CMD_MASK1 0x00003c2c
2548#define BNX2_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30
2549#define BNX2_MQ_KNL_RX_V2P_MASK1 0x00003c34
2550#define BNX2_MQ_KNL_WRITE_MASK2 0x00003c38
2551#define BNX2_MQ_KNL_TX_MASK2 0x00003c3c
2552#define BNX2_MQ_KNL_CMD_MASK2 0x00003c40
2553#define BNX2_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44
2554#define BNX2_MQ_KNL_RX_V2P_MASK2 0x00003c48
2555#define BNX2_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c
2556#define BNX2_MQ_KNL_BYP_TX_MASK1 0x00003c50
2557#define BNX2_MQ_KNL_BYP_CMD_MASK1 0x00003c54
2558#define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK1 0x00003c58
2559#define BNX2_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c
2560#define BNX2_MQ_KNL_BYP_WRITE_MASK2 0x00003c60
2561#define BNX2_MQ_KNL_BYP_TX_MASK2 0x00003c64
2562#define BNX2_MQ_KNL_BYP_CMD_MASK2 0x00003c68
2563#define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK2 0x00003c6c
2564#define BNX2_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70
2565#define BNX2_MQ_MEM_WR_ADDR 0x00003c74
2566#define BNX2_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0)
2567
2568#define BNX2_MQ_MEM_WR_DATA0 0x00003c78
2569#define BNX2_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0)
2570
2571#define BNX2_MQ_MEM_WR_DATA1 0x00003c7c
2572#define BNX2_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0)
2573
2574#define BNX2_MQ_MEM_WR_DATA2 0x00003c80
2575#define BNX2_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0)
2576
2577#define BNX2_MQ_MEM_RD_ADDR 0x00003c84
2578#define BNX2_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0)
2579
2580#define BNX2_MQ_MEM_RD_DATA0 0x00003c88
2581#define BNX2_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0)
2582
2583#define BNX2_MQ_MEM_RD_DATA1 0x00003c8c
2584#define BNX2_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0)
2585
2586#define BNX2_MQ_MEM_RD_DATA2 0x00003c90
2587#define BNX2_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0)
2588
2589
2590
2591/*
2592 * tbdr_reg definition
2593 * offset: 0x5000
2594 */
2595#define BNX2_TBDR_COMMAND 0x00005000
2596#define BNX2_TBDR_COMMAND_ENABLE (1L<<0)
2597#define BNX2_TBDR_COMMAND_SOFT_RST (1L<<1)
2598#define BNX2_TBDR_COMMAND_MSTR_ABORT (1L<<4)
2599
2600#define BNX2_TBDR_STATUS 0x00005004
2601#define BNX2_TBDR_STATUS_DMA_WAIT (1L<<0)
2602#define BNX2_TBDR_STATUS_FTQ_WAIT (1L<<1)
2603#define BNX2_TBDR_STATUS_FIFO_OVERFLOW (1L<<2)
2604#define BNX2_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3)
2605#define BNX2_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4)
2606#define BNX2_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5)
2607#define BNX2_TBDR_STATUS_BURST_CNT (1L<<6)
2608
2609#define BNX2_TBDR_CONFIG 0x00005008
2610#define BNX2_TBDR_CONFIG_MAX_BDS (0xffL<<0)
2611#define BNX2_TBDR_CONFIG_SWAP_MODE (1L<<8)
2612#define BNX2_TBDR_CONFIG_PRIORITY (1L<<9)
2613#define BNX2_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10)
2614#define BNX2_TBDR_CONFIG_PAGE_SIZE (0xfL<<24)
2615#define BNX2_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24)
2616#define BNX2_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24)
2617#define BNX2_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24)
2618#define BNX2_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24)
2619#define BNX2_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24)
2620#define BNX2_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24)
2621#define BNX2_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24)
2622#define BNX2_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24)
2623#define BNX2_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24)
2624#define BNX2_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24)
2625#define BNX2_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24)
2626#define BNX2_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24)
2627#define BNX2_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24)
2628
2629#define BNX2_TBDR_DEBUG_VECT_PEEK 0x0000500c
2630#define BNX2_TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
2631#define BNX2_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
2632#define BNX2_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
2633#define BNX2_TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
2634#define BNX2_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
2635#define BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
2636
2637#define BNX2_TBDR_FTQ_DATA 0x000053c0
2638#define BNX2_TBDR_FTQ_CMD 0x000053f8
2639#define BNX2_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0)
2640#define BNX2_TBDR_FTQ_CMD_WR_TOP (1L<<10)
2641#define BNX2_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10)
2642#define BNX2_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10)
2643#define BNX2_TBDR_FTQ_CMD_SFT_RESET (1L<<25)
2644#define BNX2_TBDR_FTQ_CMD_RD_DATA (1L<<26)
2645#define BNX2_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27)
2646#define BNX2_TBDR_FTQ_CMD_ADD_DATA (1L<<28)
2647#define BNX2_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29)
2648#define BNX2_TBDR_FTQ_CMD_POP (1L<<30)
2649#define BNX2_TBDR_FTQ_CMD_BUSY (1L<<31)
2650
2651#define BNX2_TBDR_FTQ_CTL 0x000053fc
2652#define BNX2_TBDR_FTQ_CTL_INTERVENE (1L<<0)
2653#define BNX2_TBDR_FTQ_CTL_OVERFLOW (1L<<1)
2654#define BNX2_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2)
2655#define BNX2_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
2656#define BNX2_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
2657
2658
2659
2660/*
2661 * tdma_reg definition
2662 * offset: 0x5c00
2663 */
2664#define BNX2_TDMA_COMMAND 0x00005c00
2665#define BNX2_TDMA_COMMAND_ENABLED (1L<<0)
2666#define BNX2_TDMA_COMMAND_MASTER_ABORT (1L<<4)
2667#define BNX2_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7)
2668
2669#define BNX2_TDMA_STATUS 0x00005c04
2670#define BNX2_TDMA_STATUS_DMA_WAIT (1L<<0)
2671#define BNX2_TDMA_STATUS_PAYLOAD_WAIT (1L<<1)
2672#define BNX2_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2)
2673#define BNX2_TDMA_STATUS_LOCK_WAIT (1L<<3)
2674#define BNX2_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16)
2675#define BNX2_TDMA_STATUS_BURST_CNT (1L<<17)
2676
2677#define BNX2_TDMA_CONFIG 0x00005c08
2678#define BNX2_TDMA_CONFIG_ONE_DMA (1L<<0)
2679#define BNX2_TDMA_CONFIG_ONE_RECORD (1L<<1)
2680#define BNX2_TDMA_CONFIG_LIMIT_SZ (0xfL<<4)
2681#define BNX2_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4)
2682#define BNX2_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4)
2683#define BNX2_TDMA_CONFIG_LIMIT_SZ_256 (0x6L<<4)
2684#define BNX2_TDMA_CONFIG_LIMIT_SZ_512 (0x8L<<4)
2685#define BNX2_TDMA_CONFIG_LINE_SZ (0xfL<<8)
2686#define BNX2_TDMA_CONFIG_LINE_SZ_64 (0L<<8)
2687#define BNX2_TDMA_CONFIG_LINE_SZ_128 (4L<<8)
2688#define BNX2_TDMA_CONFIG_LINE_SZ_256 (6L<<8)
2689#define BNX2_TDMA_CONFIG_LINE_SZ_512 (8L<<8)
2690#define BNX2_TDMA_CONFIG_ALIGN_ENA (1L<<15)
2691#define BNX2_TDMA_CONFIG_CHK_L2_BD (1L<<16)
2692#define BNX2_TDMA_CONFIG_FIFO_CMP (0xfL<<20)
2693
2694#define BNX2_TDMA_PAYLOAD_PROD 0x00005c0c
2695#define BNX2_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3)
2696
2697#define BNX2_TDMA_DBG_WATCHDOG 0x00005c10
2698#define BNX2_TDMA_DBG_TRIGGER 0x00005c14
2699#define BNX2_TDMA_DMAD_FSM 0x00005c80
2700#define BNX2_TDMA_DMAD_FSM_BD_INVLD (1L<<0)
2701#define BNX2_TDMA_DMAD_FSM_PUSH (0xfL<<4)
2702#define BNX2_TDMA_DMAD_FSM_ARB_TBDC (0x3L<<8)
2703#define BNX2_TDMA_DMAD_FSM_ARB_CTX (1L<<12)
2704#define BNX2_TDMA_DMAD_FSM_DR_INTF (1L<<16)
2705#define BNX2_TDMA_DMAD_FSM_DMAD (0x7L<<20)
2706#define BNX2_TDMA_DMAD_FSM_BD (0xfL<<24)
2707
2708#define BNX2_TDMA_DMAD_STATUS 0x00005c84
2709#define BNX2_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY (0x3L<<0)
2710#define BNX2_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY (0x3L<<4)
2711#define BNX2_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY (0x3L<<8)
2712#define BNX2_TDMA_DMAD_STATUS_IFTQ_ENUM (0xfL<<12)
2713
2714#define BNX2_TDMA_DR_INTF_FSM 0x00005c88
2715#define BNX2_TDMA_DR_INTF_FSM_L2_COMP (0x3L<<0)
2716#define BNX2_TDMA_DR_INTF_FSM_TPATQ (0x7L<<4)
2717#define BNX2_TDMA_DR_INTF_FSM_TPBUF (0x3L<<8)
2718#define BNX2_TDMA_DR_INTF_FSM_DR_BUF (0x7L<<12)
2719#define BNX2_TDMA_DR_INTF_FSM_DMAD (0x7L<<16)
2720
2721#define BNX2_TDMA_DR_INTF_STATUS 0x00005c8c
2722#define BNX2_TDMA_DR_INTF_STATUS_HOLE_PHASE (0x7L<<0)
2723#define BNX2_TDMA_DR_INTF_STATUS_DATA_AVAIL (0x3L<<4)
2724#define BNX2_TDMA_DR_INTF_STATUS_SHIFT_ADDR (0x7L<<8)
2725#define BNX2_TDMA_DR_INTF_STATUS_NXT_PNTR (0xfL<<12)
2726#define BNX2_TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7L<<16)
2727
2728#define BNX2_TDMA_FTQ_DATA 0x00005fc0
2729#define BNX2_TDMA_FTQ_CMD 0x00005ff8
2730#define BNX2_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0)
2731#define BNX2_TDMA_FTQ_CMD_WR_TOP (1L<<10)
2732#define BNX2_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10)
2733#define BNX2_TDMA_FTQ_CMD_WR_TOP_1 (1L<<10)
2734#define BNX2_TDMA_FTQ_CMD_SFT_RESET (1L<<25)
2735#define BNX2_TDMA_FTQ_CMD_RD_DATA (1L<<26)
2736#define BNX2_TDMA_FTQ_CMD_ADD_INTERVEN (1L<<27)
2737#define BNX2_TDMA_FTQ_CMD_ADD_DATA (1L<<28)
2738#define BNX2_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29)
2739#define BNX2_TDMA_FTQ_CMD_POP (1L<<30)
2740#define BNX2_TDMA_FTQ_CMD_BUSY (1L<<31)
2741
2742#define BNX2_TDMA_FTQ_CTL 0x00005ffc
2743#define BNX2_TDMA_FTQ_CTL_INTERVENE (1L<<0)
2744#define BNX2_TDMA_FTQ_CTL_OVERFLOW (1L<<1)
2745#define BNX2_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2)
2746#define BNX2_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
2747#define BNX2_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
2748
2749
2750
2751/*
2752 * hc_reg definition
2753 * offset: 0x6800
2754 */
2755#define BNX2_HC_COMMAND 0x00006800
2756#define BNX2_HC_COMMAND_ENABLE (1L<<0)
2757#define BNX2_HC_COMMAND_SKIP_ABORT (1L<<4)
2758#define BNX2_HC_COMMAND_COAL_NOW (1L<<16)
2759#define BNX2_HC_COMMAND_COAL_NOW_WO_INT (1L<<17)
2760#define BNX2_HC_COMMAND_STATS_NOW (1L<<18)
2761#define BNX2_HC_COMMAND_FORCE_INT (0x3L<<19)
2762#define BNX2_HC_COMMAND_FORCE_INT_NULL (0L<<19)
2763#define BNX2_HC_COMMAND_FORCE_INT_HIGH (1L<<19)
2764#define BNX2_HC_COMMAND_FORCE_INT_LOW (2L<<19)
2765#define BNX2_HC_COMMAND_FORCE_INT_FREE (3L<<19)
2766#define BNX2_HC_COMMAND_CLR_STAT_NOW (1L<<21)
2767
2768#define BNX2_HC_STATUS 0x00006804
2769#define BNX2_HC_STATUS_MASTER_ABORT (1L<<0)
2770#define BNX2_HC_STATUS_PARITY_ERROR_STATE (1L<<1)
2771#define BNX2_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16)
2772#define BNX2_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17)
2773#define BNX2_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18)
2774#define BNX2_HC_STATUS_NUM_INT_GEN_STAT (1L<<19)
2775#define BNX2_HC_STATUS_NUM_INT_MBOX_WR_STAT (1L<<20)
2776#define BNX2_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1L<<23)
2777#define BNX2_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1L<<24)
2778#define BNX2_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1L<<25)
2779
2780#define BNX2_HC_CONFIG 0x00006808
2781#define BNX2_HC_CONFIG_COLLECT_STATS (1L<<0)
2782#define BNX2_HC_CONFIG_RX_TMR_MODE (1L<<1)
2783#define BNX2_HC_CONFIG_TX_TMR_MODE (1L<<2)
2784#define BNX2_HC_CONFIG_COM_TMR_MODE (1L<<3)
2785#define BNX2_HC_CONFIG_CMD_TMR_MODE (1L<<4)
2786#define BNX2_HC_CONFIG_STATISTIC_PRIORITY (1L<<5)
2787#define BNX2_HC_CONFIG_STATUS_PRIORITY (1L<<6)
2788#define BNX2_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8)
2789
2790#define BNX2_HC_ATTN_BITS_ENABLE 0x0000680c
2791#define BNX2_HC_STATUS_ADDR_L 0x00006810
2792#define BNX2_HC_STATUS_ADDR_H 0x00006814
2793#define BNX2_HC_STATISTICS_ADDR_L 0x00006818
2794#define BNX2_HC_STATISTICS_ADDR_H 0x0000681c
2795#define BNX2_HC_TX_QUICK_CONS_TRIP 0x00006820
2796#define BNX2_HC_TX_QUICK_CONS_TRIP_VALUE (0xffL<<0)
2797#define BNX2_HC_TX_QUICK_CONS_TRIP_INT (0xffL<<16)
2798
2799#define BNX2_HC_COMP_PROD_TRIP 0x00006824
2800#define BNX2_HC_COMP_PROD_TRIP_VALUE (0xffL<<0)
2801#define BNX2_HC_COMP_PROD_TRIP_INT (0xffL<<16)
2802
2803#define BNX2_HC_RX_QUICK_CONS_TRIP 0x00006828
2804#define BNX2_HC_RX_QUICK_CONS_TRIP_VALUE (0xffL<<0)
2805#define BNX2_HC_RX_QUICK_CONS_TRIP_INT (0xffL<<16)
2806
2807#define BNX2_HC_RX_TICKS 0x0000682c
2808#define BNX2_HC_RX_TICKS_VALUE (0x3ffL<<0)
2809#define BNX2_HC_RX_TICKS_INT (0x3ffL<<16)
2810
2811#define BNX2_HC_TX_TICKS 0x00006830
2812#define BNX2_HC_TX_TICKS_VALUE (0x3ffL<<0)
2813#define BNX2_HC_TX_TICKS_INT (0x3ffL<<16)
2814
2815#define BNX2_HC_COM_TICKS 0x00006834
2816#define BNX2_HC_COM_TICKS_VALUE (0x3ffL<<0)
2817#define BNX2_HC_COM_TICKS_INT (0x3ffL<<16)
2818
2819#define BNX2_HC_CMD_TICKS 0x00006838
2820#define BNX2_HC_CMD_TICKS_VALUE (0x3ffL<<0)
2821#define BNX2_HC_CMD_TICKS_INT (0x3ffL<<16)
2822
2823#define BNX2_HC_PERIODIC_TICKS 0x0000683c
2824#define BNX2_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0)
2825
2826#define BNX2_HC_STAT_COLLECT_TICKS 0x00006840
2827#define BNX2_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4)
2828
2829#define BNX2_HC_STATS_TICKS 0x00006844
2830#define BNX2_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8)
2831
2832#define BNX2_HC_STAT_MEM_DATA 0x0000684c
2833#define BNX2_HC_STAT_GEN_SEL_0 0x00006850
2834#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0)
2835#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0)
2836#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0)
2837#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0)
2838#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0)
2839#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0)
2840#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5L<<0)
2841#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6L<<0)
2842#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7L<<0)
2843#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8L<<0)
2844#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9L<<0)
2845#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10L<<0)
2846#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11L<<0)
2847#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12L<<0)
2848#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13L<<0)
2849#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14L<<0)
2850#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15L<<0)
2851#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16L<<0)
2852#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17L<<0)
2853#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18L<<0)
2854#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19L<<0)
2855#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20L<<0)
2856#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21L<<0)
2857#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22L<<0)
2858#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23L<<0)
2859#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24L<<0)
2860#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25L<<0)
2861#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26L<<0)
2862#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27L<<0)
2863#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28L<<0)
2864#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29L<<0)
2865#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30L<<0)
2866#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31L<<0)
2867#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32L<<0)
2868#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33L<<0)
2869#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34L<<0)
2870#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35L<<0)
2871#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36L<<0)
2872#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37L<<0)
2873#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38L<<0)
2874#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39L<<0)
2875#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40L<<0)
2876#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41L<<0)
2877#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42L<<0)
2878#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43L<<0)
2879#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44L<<0)
2880#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45L<<0)
2881#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46L<<0)
2882#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47L<<0)
2883#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48L<<0)
2884#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49L<<0)
2885#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50L<<0)
2886#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51L<<0)
2887#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT (52L<<0)
2888#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53L<<0)
2889#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54L<<0)
2890#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55L<<0)
2891#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56L<<0)
2892#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59L<<0)
2893#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60L<<0)
2894#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61L<<0)
2895#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62L<<0)
2896#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63L<<0)
2897#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64L<<0)
2898#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65L<<0)
2899#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66L<<0)
2900#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67L<<0)
2901#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68L<<0)
2902#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0)
2903#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0)
2904#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0)
2905#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72L<<0)
2906#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73L<<0)
2907#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74L<<0)
2908#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75L<<0)
2909#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76L<<0)
2910#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77L<<0)
2911#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78L<<0)
2912#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79L<<0)
2913#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80L<<0)
2914#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81L<<0)
2915#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82L<<0)
2916#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83L<<0)
2917#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84L<<0)
2918#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT (85L<<0)
2919#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT (86L<<0)
2920#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT (87L<<0)
2921#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT (88L<<0)
2922#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT (89L<<0)
2923#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT (90L<<0)
2924#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT (91L<<0)
2925#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT (92L<<0)
2926#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT (93L<<0)
2927#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT (94L<<0)
2928#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95L<<0)
2929#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96L<<0)
2930#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97L<<0)
2931#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98L<<0)
2932#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99L<<0)
2933#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100L<<0)
2934#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101L<<0)
2935#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102L<<0)
2936#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103L<<0)
2937#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104L<<0)
2938#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105L<<0)
2939#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106L<<0)
2940#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107L<<0)
2941#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108L<<0)
2942#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109L<<0)
2943#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110L<<0)
2944#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111L<<0)
2945#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112L<<0)
2946#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113L<<0)
2947#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114L<<0)
2948#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115L<<0)
2949#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116L<<0)
2950#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117L<<0)
2951#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118L<<0)
2952#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0)
2953#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0)
2954#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0)
2955#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0)
2956#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0)
2957#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8)
2958#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16)
2959#define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24)
2960
2961#define BNX2_HC_STAT_GEN_SEL_1 0x00006854
2962#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0)
2963#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8)
2964#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16)
2965#define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24)
2966
2967#define BNX2_HC_STAT_GEN_SEL_2 0x00006858
2968#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0)
2969#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8)
2970#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16)
2971#define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24)
2972
2973#define BNX2_HC_STAT_GEN_SEL_3 0x0000685c
2974#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0)
2975#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8)
2976#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16)
2977#define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24)
2978
2979#define BNX2_HC_STAT_GEN_STAT0 0x00006888
2980#define BNX2_HC_STAT_GEN_STAT1 0x0000688c
2981#define BNX2_HC_STAT_GEN_STAT2 0x00006890
2982#define BNX2_HC_STAT_GEN_STAT3 0x00006894
2983#define BNX2_HC_STAT_GEN_STAT4 0x00006898
2984#define BNX2_HC_STAT_GEN_STAT5 0x0000689c
2985#define BNX2_HC_STAT_GEN_STAT6 0x000068a0
2986#define BNX2_HC_STAT_GEN_STAT7 0x000068a4
2987#define BNX2_HC_STAT_GEN_STAT8 0x000068a8
2988#define BNX2_HC_STAT_GEN_STAT9 0x000068ac
2989#define BNX2_HC_STAT_GEN_STAT10 0x000068b0
2990#define BNX2_HC_STAT_GEN_STAT11 0x000068b4
2991#define BNX2_HC_STAT_GEN_STAT12 0x000068b8
2992#define BNX2_HC_STAT_GEN_STAT13 0x000068bc
2993#define BNX2_HC_STAT_GEN_STAT14 0x000068c0
2994#define BNX2_HC_STAT_GEN_STAT15 0x000068c4
2995#define BNX2_HC_STAT_GEN_STAT_AC0 0x000068c8
2996#define BNX2_HC_STAT_GEN_STAT_AC1 0x000068cc
2997#define BNX2_HC_STAT_GEN_STAT_AC2 0x000068d0
2998#define BNX2_HC_STAT_GEN_STAT_AC3 0x000068d4
2999#define BNX2_HC_STAT_GEN_STAT_AC4 0x000068d8
3000#define BNX2_HC_STAT_GEN_STAT_AC5 0x000068dc
3001#define BNX2_HC_STAT_GEN_STAT_AC6 0x000068e0
3002#define BNX2_HC_STAT_GEN_STAT_AC7 0x000068e4
3003#define BNX2_HC_STAT_GEN_STAT_AC8 0x000068e8
3004#define BNX2_HC_STAT_GEN_STAT_AC9 0x000068ec
3005#define BNX2_HC_STAT_GEN_STAT_AC10 0x000068f0
3006#define BNX2_HC_STAT_GEN_STAT_AC11 0x000068f4
3007#define BNX2_HC_STAT_GEN_STAT_AC12 0x000068f8
3008#define BNX2_HC_STAT_GEN_STAT_AC13 0x000068fc
3009#define BNX2_HC_STAT_GEN_STAT_AC14 0x00006900
3010#define BNX2_HC_STAT_GEN_STAT_AC15 0x00006904
3011#define BNX2_HC_VIS 0x00006908
3012#define BNX2_HC_VIS_STAT_BUILD_STATE (0xfL<<0)
3013#define BNX2_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0)
3014#define BNX2_HC_VIS_STAT_BUILD_STATE_START (1L<<0)
3015#define BNX2_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0)
3016#define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0)
3017#define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0)
3018#define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0)
3019#define BNX2_HC_VIS_STAT_BUILD_STATE_DMA (6L<<0)
3020#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7L<<0)
3021#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_LOW (8L<<0)
3022#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9L<<0)
3023#define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_DATA (10L<<0)
3024#define BNX2_HC_VIS_DMA_STAT_STATE (0xfL<<8)
3025#define BNX2_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8)
3026#define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1L<<8)
3027#define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_DMA (2L<<8)
3028#define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP (3L<<8)
3029#define BNX2_HC_VIS_DMA_STAT_STATE_COMP (4L<<8)
3030#define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5L<<8)
3031#define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6L<<8)
3032#define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7L<<8)
3033#define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8L<<8)
3034#define BNX2_HC_VIS_DMA_STAT_STATE_WAIT (9L<<8)
3035#define BNX2_HC_VIS_DMA_STAT_STATE_ABORT (15L<<8)
3036#define BNX2_HC_VIS_DMA_MSI_STATE (0x7L<<12)
3037#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE (0x3L<<15)
3038#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15)
3039#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1L<<15)
3040#define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_START (2L<<15)
3041
3042#define BNX2_HC_VIS_1 0x0000690c
3043#define BNX2_HC_VIS_1_HW_INTACK_STATE (1L<<4)
3044#define BNX2_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4)
3045#define BNX2_HC_VIS_1_HW_INTACK_STATE_COUNT (1L<<4)
3046#define BNX2_HC_VIS_1_SW_INTACK_STATE (1L<<5)
3047#define BNX2_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5)
3048#define BNX2_HC_VIS_1_SW_INTACK_STATE_COUNT (1L<<5)
3049#define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE (1L<<6)
3050#define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6)
3051#define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1L<<6)
3052#define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE (1L<<7)
3053#define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7)
3054#define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1L<<7)
3055#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE (0xfL<<17)
3056#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17)
3057#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_DMA (1L<<17)
3058#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2L<<17)
3059#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3L<<17)
3060#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4L<<17)
3061#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5L<<17)
3062#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6L<<17)
3063#define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7L<<17)
3064#define BNX2_HC_VIS_1_RAM_WR_ARB_STATE (0x3L<<21)
3065#define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21)
3066#define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1L<<21)
3067#define BNX2_HC_VIS_1_INT_GEN_STATE (1L<<23)
3068#define BNX2_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23)
3069#define BNX2_HC_VIS_1_INT_GEN_STATE_NTERRUPT (1L<<23)
3070#define BNX2_HC_VIS_1_STAT_CHAN_ID (0x7L<<24)
3071#define BNX2_HC_VIS_1_INT_B (1L<<27)
3072
3073#define BNX2_HC_DEBUG_VECT_PEEK 0x00006910
3074#define BNX2_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3075#define BNX2_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3076#define BNX2_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3077#define BNX2_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3078#define BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3079#define BNX2_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3080
3081
3082
3083/*
3084 * txp_reg definition
3085 * offset: 0x40000
3086 */
3087#define BNX2_TXP_CPU_MODE 0x00045000
3088#define BNX2_TXP_CPU_MODE_LOCAL_RST (1L<<0)
3089#define BNX2_TXP_CPU_MODE_STEP_ENA (1L<<1)
3090#define BNX2_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3091#define BNX2_TXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3092#define BNX2_TXP_CPU_MODE_MSG_BIT1 (1L<<6)
3093#define BNX2_TXP_CPU_MODE_INTERRUPT_ENA (1L<<7)
3094#define BNX2_TXP_CPU_MODE_SOFT_HALT (1L<<10)
3095#define BNX2_TXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3096#define BNX2_TXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3097#define BNX2_TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3098#define BNX2_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3099
3100#define BNX2_TXP_CPU_STATE 0x00045004
3101#define BNX2_TXP_CPU_STATE_BREAKPOINT (1L<<0)
3102#define BNX2_TXP_CPU_STATE_BAD_INST_HALTED (1L<<2)
3103#define BNX2_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3104#define BNX2_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3105#define BNX2_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3106#define BNX2_TXP_CPU_STATE_BAD_pc_HALTED (1L<<6)
3107#define BNX2_TXP_CPU_STATE_ALIGN_HALTED (1L<<7)
3108#define BNX2_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3109#define BNX2_TXP_CPU_STATE_SOFT_HALTED (1L<<10)
3110#define BNX2_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3111#define BNX2_TXP_CPU_STATE_INTERRRUPT (1L<<12)
3112#define BNX2_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3113#define BNX2_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15)
3114#define BNX2_TXP_CPU_STATE_BLOCKED_READ (1L<<31)
3115
3116#define BNX2_TXP_CPU_EVENT_MASK 0x00045008
3117#define BNX2_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3118#define BNX2_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3119#define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3120#define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3121#define BNX2_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3122#define BNX2_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3123#define BNX2_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3124#define BNX2_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3125#define BNX2_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3126#define BNX2_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3127#define BNX2_TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3128
3129#define BNX2_TXP_CPU_PROGRAM_COUNTER 0x0004501c
3130#define BNX2_TXP_CPU_INSTRUCTION 0x00045020
3131#define BNX2_TXP_CPU_DATA_ACCESS 0x00045024
3132#define BNX2_TXP_CPU_INTERRUPT_ENABLE 0x00045028
3133#define BNX2_TXP_CPU_INTERRUPT_VECTOR 0x0004502c
3134#define BNX2_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030
3135#define BNX2_TXP_CPU_HW_BREAKPOINT 0x00045034
3136#define BNX2_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3137#define BNX2_TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3138
3139#define BNX2_TXP_CPU_DEBUG_VECT_PEEK 0x00045038
3140#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3141#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3142#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3143#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3144#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3145#define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3146
3147#define BNX2_TXP_CPU_LAST_BRANCH_ADDR 0x00045048
3148#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3149#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3150#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3151#define BNX2_TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3152
3153#define BNX2_TXP_CPU_REG_FILE 0x00045200
3154#define BNX2_TXP_FTQ_DATA 0x000453c0
3155#define BNX2_TXP_FTQ_CMD 0x000453f8
3156#define BNX2_TXP_FTQ_CMD_OFFSET (0x3ffL<<0)
3157#define BNX2_TXP_FTQ_CMD_WR_TOP (1L<<10)
3158#define BNX2_TXP_FTQ_CMD_WR_TOP_0 (0L<<10)
3159#define BNX2_TXP_FTQ_CMD_WR_TOP_1 (1L<<10)
3160#define BNX2_TXP_FTQ_CMD_SFT_RESET (1L<<25)
3161#define BNX2_TXP_FTQ_CMD_RD_DATA (1L<<26)
3162#define BNX2_TXP_FTQ_CMD_ADD_INTERVEN (1L<<27)
3163#define BNX2_TXP_FTQ_CMD_ADD_DATA (1L<<28)
3164#define BNX2_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29)
3165#define BNX2_TXP_FTQ_CMD_POP (1L<<30)
3166#define BNX2_TXP_FTQ_CMD_BUSY (1L<<31)
3167
3168#define BNX2_TXP_FTQ_CTL 0x000453fc
3169#define BNX2_TXP_FTQ_CTL_INTERVENE (1L<<0)
3170#define BNX2_TXP_FTQ_CTL_OVERFLOW (1L<<1)
3171#define BNX2_TXP_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3172#define BNX2_TXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3173#define BNX2_TXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3174
3175#define BNX2_TXP_SCRATCH 0x00060000
3176
3177
3178/*
3179 * tpat_reg definition
3180 * offset: 0x80000
3181 */
3182#define BNX2_TPAT_CPU_MODE 0x00085000
3183#define BNX2_TPAT_CPU_MODE_LOCAL_RST (1L<<0)
3184#define BNX2_TPAT_CPU_MODE_STEP_ENA (1L<<1)
3185#define BNX2_TPAT_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3186#define BNX2_TPAT_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3187#define BNX2_TPAT_CPU_MODE_MSG_BIT1 (1L<<6)
3188#define BNX2_TPAT_CPU_MODE_INTERRUPT_ENA (1L<<7)
3189#define BNX2_TPAT_CPU_MODE_SOFT_HALT (1L<<10)
3190#define BNX2_TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3191#define BNX2_TPAT_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3192#define BNX2_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3193#define BNX2_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3194
3195#define BNX2_TPAT_CPU_STATE 0x00085004
3196#define BNX2_TPAT_CPU_STATE_BREAKPOINT (1L<<0)
3197#define BNX2_TPAT_CPU_STATE_BAD_INST_HALTED (1L<<2)
3198#define BNX2_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3199#define BNX2_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3200#define BNX2_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3201#define BNX2_TPAT_CPU_STATE_BAD_pc_HALTED (1L<<6)
3202#define BNX2_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7)
3203#define BNX2_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3204#define BNX2_TPAT_CPU_STATE_SOFT_HALTED (1L<<10)
3205#define BNX2_TPAT_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3206#define BNX2_TPAT_CPU_STATE_INTERRRUPT (1L<<12)
3207#define BNX2_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3208#define BNX2_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15)
3209#define BNX2_TPAT_CPU_STATE_BLOCKED_READ (1L<<31)
3210
3211#define BNX2_TPAT_CPU_EVENT_MASK 0x00085008
3212#define BNX2_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3213#define BNX2_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3214#define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3215#define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3216#define BNX2_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3217#define BNX2_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3218#define BNX2_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3219#define BNX2_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3220#define BNX2_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3221#define BNX2_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3222#define BNX2_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3223
3224#define BNX2_TPAT_CPU_PROGRAM_COUNTER 0x0008501c
3225#define BNX2_TPAT_CPU_INSTRUCTION 0x00085020
3226#define BNX2_TPAT_CPU_DATA_ACCESS 0x00085024
3227#define BNX2_TPAT_CPU_INTERRUPT_ENABLE 0x00085028
3228#define BNX2_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c
3229#define BNX2_TPAT_CPU_INTERRUPT_SAVED_PC 0x00085030
3230#define BNX2_TPAT_CPU_HW_BREAKPOINT 0x00085034
3231#define BNX2_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3232#define BNX2_TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3233
3234#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK 0x00085038
3235#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3236#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3237#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3238#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3239#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3240#define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3241
3242#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR 0x00085048
3243#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3244#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3245#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3246#define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3247
3248#define BNX2_TPAT_CPU_REG_FILE 0x00085200
3249#define BNX2_TPAT_FTQ_DATA 0x000853c0
3250#define BNX2_TPAT_FTQ_CMD 0x000853f8
3251#define BNX2_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0)
3252#define BNX2_TPAT_FTQ_CMD_WR_TOP (1L<<10)
3253#define BNX2_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10)
3254#define BNX2_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10)
3255#define BNX2_TPAT_FTQ_CMD_SFT_RESET (1L<<25)
3256#define BNX2_TPAT_FTQ_CMD_RD_DATA (1L<<26)
3257#define BNX2_TPAT_FTQ_CMD_ADD_INTERVEN (1L<<27)
3258#define BNX2_TPAT_FTQ_CMD_ADD_DATA (1L<<28)
3259#define BNX2_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29)
3260#define BNX2_TPAT_FTQ_CMD_POP (1L<<30)
3261#define BNX2_TPAT_FTQ_CMD_BUSY (1L<<31)
3262
3263#define BNX2_TPAT_FTQ_CTL 0x000853fc
3264#define BNX2_TPAT_FTQ_CTL_INTERVENE (1L<<0)
3265#define BNX2_TPAT_FTQ_CTL_OVERFLOW (1L<<1)
3266#define BNX2_TPAT_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3267#define BNX2_TPAT_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3268#define BNX2_TPAT_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3269
3270#define BNX2_TPAT_SCRATCH 0x000a0000
3271
3272
3273/*
3274 * rxp_reg definition
3275 * offset: 0xc0000
3276 */
3277#define BNX2_RXP_CPU_MODE 0x000c5000
3278#define BNX2_RXP_CPU_MODE_LOCAL_RST (1L<<0)
3279#define BNX2_RXP_CPU_MODE_STEP_ENA (1L<<1)
3280#define BNX2_RXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3281#define BNX2_RXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3282#define BNX2_RXP_CPU_MODE_MSG_BIT1 (1L<<6)
3283#define BNX2_RXP_CPU_MODE_INTERRUPT_ENA (1L<<7)
3284#define BNX2_RXP_CPU_MODE_SOFT_HALT (1L<<10)
3285#define BNX2_RXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3286#define BNX2_RXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3287#define BNX2_RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3288#define BNX2_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3289
3290#define BNX2_RXP_CPU_STATE 0x000c5004
3291#define BNX2_RXP_CPU_STATE_BREAKPOINT (1L<<0)
3292#define BNX2_RXP_CPU_STATE_BAD_INST_HALTED (1L<<2)
3293#define BNX2_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3294#define BNX2_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3295#define BNX2_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3296#define BNX2_RXP_CPU_STATE_BAD_pc_HALTED (1L<<6)
3297#define BNX2_RXP_CPU_STATE_ALIGN_HALTED (1L<<7)
3298#define BNX2_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3299#define BNX2_RXP_CPU_STATE_SOFT_HALTED (1L<<10)
3300#define BNX2_RXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3301#define BNX2_RXP_CPU_STATE_INTERRRUPT (1L<<12)
3302#define BNX2_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3303#define BNX2_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15)
3304#define BNX2_RXP_CPU_STATE_BLOCKED_READ (1L<<31)
3305
3306#define BNX2_RXP_CPU_EVENT_MASK 0x000c5008
3307#define BNX2_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3308#define BNX2_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3309#define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3310#define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3311#define BNX2_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3312#define BNX2_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3313#define BNX2_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3314#define BNX2_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3315#define BNX2_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3316#define BNX2_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3317#define BNX2_RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3318
3319#define BNX2_RXP_CPU_PROGRAM_COUNTER 0x000c501c
3320#define BNX2_RXP_CPU_INSTRUCTION 0x000c5020
3321#define BNX2_RXP_CPU_DATA_ACCESS 0x000c5024
3322#define BNX2_RXP_CPU_INTERRUPT_ENABLE 0x000c5028
3323#define BNX2_RXP_CPU_INTERRUPT_VECTOR 0x000c502c
3324#define BNX2_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030
3325#define BNX2_RXP_CPU_HW_BREAKPOINT 0x000c5034
3326#define BNX2_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3327#define BNX2_RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3328
3329#define BNX2_RXP_CPU_DEBUG_VECT_PEEK 0x000c5038
3330#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3331#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3332#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3333#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3334#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3335#define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3336
3337#define BNX2_RXP_CPU_LAST_BRANCH_ADDR 0x000c5048
3338#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3339#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3340#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3341#define BNX2_RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3342
3343#define BNX2_RXP_CPU_REG_FILE 0x000c5200
3344#define BNX2_RXP_CFTQ_DATA 0x000c5380
3345#define BNX2_RXP_CFTQ_CMD 0x000c53b8
3346#define BNX2_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0)
3347#define BNX2_RXP_CFTQ_CMD_WR_TOP (1L<<10)
3348#define BNX2_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10)
3349#define BNX2_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10)
3350#define BNX2_RXP_CFTQ_CMD_SFT_RESET (1L<<25)
3351#define BNX2_RXP_CFTQ_CMD_RD_DATA (1L<<26)
3352#define BNX2_RXP_CFTQ_CMD_ADD_INTERVEN (1L<<27)
3353#define BNX2_RXP_CFTQ_CMD_ADD_DATA (1L<<28)
3354#define BNX2_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29)
3355#define BNX2_RXP_CFTQ_CMD_POP (1L<<30)
3356#define BNX2_RXP_CFTQ_CMD_BUSY (1L<<31)
3357
3358#define BNX2_RXP_CFTQ_CTL 0x000c53bc
3359#define BNX2_RXP_CFTQ_CTL_INTERVENE (1L<<0)
3360#define BNX2_RXP_CFTQ_CTL_OVERFLOW (1L<<1)
3361#define BNX2_RXP_CFTQ_CTL_FORCE_INTERVENE (1L<<2)
3362#define BNX2_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3363#define BNX2_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3364
3365#define BNX2_RXP_FTQ_DATA 0x000c53c0
3366#define BNX2_RXP_FTQ_CMD 0x000c53f8
3367#define BNX2_RXP_FTQ_CMD_OFFSET (0x3ffL<<0)
3368#define BNX2_RXP_FTQ_CMD_WR_TOP (1L<<10)
3369#define BNX2_RXP_FTQ_CMD_WR_TOP_0 (0L<<10)
3370#define BNX2_RXP_FTQ_CMD_WR_TOP_1 (1L<<10)
3371#define BNX2_RXP_FTQ_CMD_SFT_RESET (1L<<25)
3372#define BNX2_RXP_FTQ_CMD_RD_DATA (1L<<26)
3373#define BNX2_RXP_FTQ_CMD_ADD_INTERVEN (1L<<27)
3374#define BNX2_RXP_FTQ_CMD_ADD_DATA (1L<<28)
3375#define BNX2_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29)
3376#define BNX2_RXP_FTQ_CMD_POP (1L<<30)
3377#define BNX2_RXP_FTQ_CMD_BUSY (1L<<31)
3378
3379#define BNX2_RXP_FTQ_CTL 0x000c53fc
3380#define BNX2_RXP_FTQ_CTL_INTERVENE (1L<<0)
3381#define BNX2_RXP_FTQ_CTL_OVERFLOW (1L<<1)
3382#define BNX2_RXP_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3383#define BNX2_RXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3384#define BNX2_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3385
3386#define BNX2_RXP_SCRATCH 0x000e0000
3387
3388
3389/*
3390 * com_reg definition
3391 * offset: 0x100000
3392 */
3393#define BNX2_COM_CPU_MODE 0x00105000
3394#define BNX2_COM_CPU_MODE_LOCAL_RST (1L<<0)
3395#define BNX2_COM_CPU_MODE_STEP_ENA (1L<<1)
3396#define BNX2_COM_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3397#define BNX2_COM_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3398#define BNX2_COM_CPU_MODE_MSG_BIT1 (1L<<6)
3399#define BNX2_COM_CPU_MODE_INTERRUPT_ENA (1L<<7)
3400#define BNX2_COM_CPU_MODE_SOFT_HALT (1L<<10)
3401#define BNX2_COM_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3402#define BNX2_COM_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3403#define BNX2_COM_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3404#define BNX2_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3405
3406#define BNX2_COM_CPU_STATE 0x00105004
3407#define BNX2_COM_CPU_STATE_BREAKPOINT (1L<<0)
3408#define BNX2_COM_CPU_STATE_BAD_INST_HALTED (1L<<2)
3409#define BNX2_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3410#define BNX2_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3411#define BNX2_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3412#define BNX2_COM_CPU_STATE_BAD_pc_HALTED (1L<<6)
3413#define BNX2_COM_CPU_STATE_ALIGN_HALTED (1L<<7)
3414#define BNX2_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3415#define BNX2_COM_CPU_STATE_SOFT_HALTED (1L<<10)
3416#define BNX2_COM_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3417#define BNX2_COM_CPU_STATE_INTERRRUPT (1L<<12)
3418#define BNX2_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3419#define BNX2_COM_CPU_STATE_INST_FETCH_STALL (1L<<15)
3420#define BNX2_COM_CPU_STATE_BLOCKED_READ (1L<<31)
3421
3422#define BNX2_COM_CPU_EVENT_MASK 0x00105008
3423#define BNX2_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3424#define BNX2_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3425#define BNX2_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3426#define BNX2_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3427#define BNX2_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3428#define BNX2_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3429#define BNX2_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3430#define BNX2_COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3431#define BNX2_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3432#define BNX2_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3433#define BNX2_COM_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3434
3435#define BNX2_COM_CPU_PROGRAM_COUNTER 0x0010501c
3436#define BNX2_COM_CPU_INSTRUCTION 0x00105020
3437#define BNX2_COM_CPU_DATA_ACCESS 0x00105024
3438#define BNX2_COM_CPU_INTERRUPT_ENABLE 0x00105028
3439#define BNX2_COM_CPU_INTERRUPT_VECTOR 0x0010502c
3440#define BNX2_COM_CPU_INTERRUPT_SAVED_PC 0x00105030
3441#define BNX2_COM_CPU_HW_BREAKPOINT 0x00105034
3442#define BNX2_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3443#define BNX2_COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3444
3445#define BNX2_COM_CPU_DEBUG_VECT_PEEK 0x00105038
3446#define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3447#define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3448#define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3449#define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3450#define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3451#define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3452
3453#define BNX2_COM_CPU_LAST_BRANCH_ADDR 0x00105048
3454#define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3455#define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3456#define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3457#define BNX2_COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3458
3459#define BNX2_COM_CPU_REG_FILE 0x00105200
3460#define BNX2_COM_COMXQ_FTQ_DATA 0x00105340
3461#define BNX2_COM_COMXQ_FTQ_CMD 0x00105378
3462#define BNX2_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0)
3463#define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10)
3464#define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10)
3465#define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10)
3466#define BNX2_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25)
3467#define BNX2_COM_COMXQ_FTQ_CMD_RD_DATA (1L<<26)
3468#define BNX2_COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
3469#define BNX2_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28)
3470#define BNX2_COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
3471#define BNX2_COM_COMXQ_FTQ_CMD_POP (1L<<30)
3472#define BNX2_COM_COMXQ_FTQ_CMD_BUSY (1L<<31)
3473
3474#define BNX2_COM_COMXQ_FTQ_CTL 0x0010537c
3475#define BNX2_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0)
3476#define BNX2_COM_COMXQ_FTQ_CTL_OVERFLOW (1L<<1)
3477#define BNX2_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3478#define BNX2_COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3479#define BNX2_COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3480
3481#define BNX2_COM_COMTQ_FTQ_DATA 0x00105380
3482#define BNX2_COM_COMTQ_FTQ_CMD 0x001053b8
3483#define BNX2_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0)
3484#define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10)
3485#define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10)
3486#define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_1 (1L<<10)
3487#define BNX2_COM_COMTQ_FTQ_CMD_SFT_RESET (1L<<25)
3488#define BNX2_COM_COMTQ_FTQ_CMD_RD_DATA (1L<<26)
3489#define BNX2_COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
3490#define BNX2_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28)
3491#define BNX2_COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
3492#define BNX2_COM_COMTQ_FTQ_CMD_POP (1L<<30)
3493#define BNX2_COM_COMTQ_FTQ_CMD_BUSY (1L<<31)
3494
3495#define BNX2_COM_COMTQ_FTQ_CTL 0x001053bc
3496#define BNX2_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0)
3497#define BNX2_COM_COMTQ_FTQ_CTL_OVERFLOW (1L<<1)
3498#define BNX2_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3499#define BNX2_COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3500#define BNX2_COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3501
3502#define BNX2_COM_COMQ_FTQ_DATA 0x001053c0
3503#define BNX2_COM_COMQ_FTQ_CMD 0x001053f8
3504#define BNX2_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0)
3505#define BNX2_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10)
3506#define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10)
3507#define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_1 (1L<<10)
3508#define BNX2_COM_COMQ_FTQ_CMD_SFT_RESET (1L<<25)
3509#define BNX2_COM_COMQ_FTQ_CMD_RD_DATA (1L<<26)
3510#define BNX2_COM_COMQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
3511#define BNX2_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28)
3512#define BNX2_COM_COMQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
3513#define BNX2_COM_COMQ_FTQ_CMD_POP (1L<<30)
3514#define BNX2_COM_COMQ_FTQ_CMD_BUSY (1L<<31)
3515
3516#define BNX2_COM_COMQ_FTQ_CTL 0x001053fc
3517#define BNX2_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0)
3518#define BNX2_COM_COMQ_FTQ_CTL_OVERFLOW (1L<<1)
3519#define BNX2_COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3520#define BNX2_COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3521#define BNX2_COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3522
3523#define BNX2_COM_SCRATCH 0x00120000
3524
3525
3526/*
3527 * cp_reg definition
3528 * offset: 0x180000
3529 */
3530#define BNX2_CP_CPU_MODE 0x00185000
3531#define BNX2_CP_CPU_MODE_LOCAL_RST (1L<<0)
3532#define BNX2_CP_CPU_MODE_STEP_ENA (1L<<1)
3533#define BNX2_CP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3534#define BNX2_CP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3535#define BNX2_CP_CPU_MODE_MSG_BIT1 (1L<<6)
3536#define BNX2_CP_CPU_MODE_INTERRUPT_ENA (1L<<7)
3537#define BNX2_CP_CPU_MODE_SOFT_HALT (1L<<10)
3538#define BNX2_CP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3539#define BNX2_CP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3540#define BNX2_CP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3541#define BNX2_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3542
3543#define BNX2_CP_CPU_STATE 0x00185004
3544#define BNX2_CP_CPU_STATE_BREAKPOINT (1L<<0)
3545#define BNX2_CP_CPU_STATE_BAD_INST_HALTED (1L<<2)
3546#define BNX2_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3547#define BNX2_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3548#define BNX2_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3549#define BNX2_CP_CPU_STATE_BAD_pc_HALTED (1L<<6)
3550#define BNX2_CP_CPU_STATE_ALIGN_HALTED (1L<<7)
3551#define BNX2_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3552#define BNX2_CP_CPU_STATE_SOFT_HALTED (1L<<10)
3553#define BNX2_CP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3554#define BNX2_CP_CPU_STATE_INTERRRUPT (1L<<12)
3555#define BNX2_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3556#define BNX2_CP_CPU_STATE_INST_FETCH_STALL (1L<<15)
3557#define BNX2_CP_CPU_STATE_BLOCKED_READ (1L<<31)
3558
3559#define BNX2_CP_CPU_EVENT_MASK 0x00185008
3560#define BNX2_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3561#define BNX2_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3562#define BNX2_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3563#define BNX2_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3564#define BNX2_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3565#define BNX2_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3566#define BNX2_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3567#define BNX2_CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3568#define BNX2_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3569#define BNX2_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3570#define BNX2_CP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3571
3572#define BNX2_CP_CPU_PROGRAM_COUNTER 0x0018501c
3573#define BNX2_CP_CPU_INSTRUCTION 0x00185020
3574#define BNX2_CP_CPU_DATA_ACCESS 0x00185024
3575#define BNX2_CP_CPU_INTERRUPT_ENABLE 0x00185028
3576#define BNX2_CP_CPU_INTERRUPT_VECTOR 0x0018502c
3577#define BNX2_CP_CPU_INTERRUPT_SAVED_PC 0x00185030
3578#define BNX2_CP_CPU_HW_BREAKPOINT 0x00185034
3579#define BNX2_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3580#define BNX2_CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3581
3582#define BNX2_CP_CPU_DEBUG_VECT_PEEK 0x00185038
3583#define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3584#define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3585#define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3586#define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3587#define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3588#define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3589
3590#define BNX2_CP_CPU_LAST_BRANCH_ADDR 0x00185048
3591#define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3592#define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3593#define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3594#define BNX2_CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3595
3596#define BNX2_CP_CPU_REG_FILE 0x00185200
3597#define BNX2_CP_CPQ_FTQ_DATA 0x001853c0
3598#define BNX2_CP_CPQ_FTQ_CMD 0x001853f8
3599#define BNX2_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
3600#define BNX2_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10)
3601#define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
3602#define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
3603#define BNX2_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25)
3604#define BNX2_CP_CPQ_FTQ_CMD_RD_DATA (1L<<26)
3605#define BNX2_CP_CPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
3606#define BNX2_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28)
3607#define BNX2_CP_CPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
3608#define BNX2_CP_CPQ_FTQ_CMD_POP (1L<<30)
3609#define BNX2_CP_CPQ_FTQ_CMD_BUSY (1L<<31)
3610
3611#define BNX2_CP_CPQ_FTQ_CTL 0x001853fc
3612#define BNX2_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0)
3613#define BNX2_CP_CPQ_FTQ_CTL_OVERFLOW (1L<<1)
3614#define BNX2_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3615#define BNX2_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3616#define BNX2_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3617
3618#define BNX2_CP_SCRATCH 0x001a0000
3619
3620
3621/*
3622 * mcp_reg definition
3623 * offset: 0x140000
3624 */
3625#define BNX2_MCP_CPU_MODE 0x00145000
3626#define BNX2_MCP_CPU_MODE_LOCAL_RST (1L<<0)
3627#define BNX2_MCP_CPU_MODE_STEP_ENA (1L<<1)
3628#define BNX2_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
3629#define BNX2_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
3630#define BNX2_MCP_CPU_MODE_MSG_BIT1 (1L<<6)
3631#define BNX2_MCP_CPU_MODE_INTERRUPT_ENA (1L<<7)
3632#define BNX2_MCP_CPU_MODE_SOFT_HALT (1L<<10)
3633#define BNX2_MCP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
3634#define BNX2_MCP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
3635#define BNX2_MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
3636#define BNX2_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
3637
3638#define BNX2_MCP_CPU_STATE 0x00145004
3639#define BNX2_MCP_CPU_STATE_BREAKPOINT (1L<<0)
3640#define BNX2_MCP_CPU_STATE_BAD_INST_HALTED (1L<<2)
3641#define BNX2_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
3642#define BNX2_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
3643#define BNX2_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
3644#define BNX2_MCP_CPU_STATE_BAD_pc_HALTED (1L<<6)
3645#define BNX2_MCP_CPU_STATE_ALIGN_HALTED (1L<<7)
3646#define BNX2_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
3647#define BNX2_MCP_CPU_STATE_SOFT_HALTED (1L<<10)
3648#define BNX2_MCP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
3649#define BNX2_MCP_CPU_STATE_INTERRRUPT (1L<<12)
3650#define BNX2_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
3651#define BNX2_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15)
3652#define BNX2_MCP_CPU_STATE_BLOCKED_READ (1L<<31)
3653
3654#define BNX2_MCP_CPU_EVENT_MASK 0x00145008
3655#define BNX2_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
3656#define BNX2_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
3657#define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
3658#define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
3659#define BNX2_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
3660#define BNX2_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
3661#define BNX2_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
3662#define BNX2_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
3663#define BNX2_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
3664#define BNX2_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
3665#define BNX2_MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
3666
3667#define BNX2_MCP_CPU_PROGRAM_COUNTER 0x0014501c
3668#define BNX2_MCP_CPU_INSTRUCTION 0x00145020
3669#define BNX2_MCP_CPU_DATA_ACCESS 0x00145024
3670#define BNX2_MCP_CPU_INTERRUPT_ENABLE 0x00145028
3671#define BNX2_MCP_CPU_INTERRUPT_VECTOR 0x0014502c
3672#define BNX2_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030
3673#define BNX2_MCP_CPU_HW_BREAKPOINT 0x00145034
3674#define BNX2_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
3675#define BNX2_MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
3676
3677#define BNX2_MCP_CPU_DEBUG_VECT_PEEK 0x00145038
3678#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3679#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3680#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3681#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3682#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3683#define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3684
3685#define BNX2_MCP_CPU_LAST_BRANCH_ADDR 0x00145048
3686#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
3687#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
3688#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
3689#define BNX2_MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
3690
3691#define BNX2_MCP_CPU_REG_FILE 0x00145200
3692#define BNX2_MCP_MCPQ_FTQ_DATA 0x001453c0
3693#define BNX2_MCP_MCPQ_FTQ_CMD 0x001453f8
3694#define BNX2_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
3695#define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10)
3696#define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
3697#define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
3698#define BNX2_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25)
3699#define BNX2_MCP_MCPQ_FTQ_CMD_RD_DATA (1L<<26)
3700#define BNX2_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
3701#define BNX2_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28)
3702#define BNX2_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
3703#define BNX2_MCP_MCPQ_FTQ_CMD_POP (1L<<30)
3704#define BNX2_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31)
3705
3706#define BNX2_MCP_MCPQ_FTQ_CTL 0x001453fc
3707#define BNX2_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0)
3708#define BNX2_MCP_MCPQ_FTQ_CTL_OVERFLOW (1L<<1)
3709#define BNX2_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3710#define BNX2_MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3711#define BNX2_MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3712
3713#define BNX2_MCP_ROM 0x00150000
3714#define BNX2_MCP_SCRATCH 0x00160000
3715
3716
3717#define NUM_MC_HASH_REGISTERS 8
3718
3719
3720/* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */
3721#define PHY_BCM5706_PHY_ID 0x00206160
3722
3723#define PHY_ID(id) ((id) & 0xfffffff0)
3724#define PHY_REV_ID(id) ((id) & 0xf)
3725
3726#define MIN_ETHERNET_PACKET_SIZE 60
3727#define MAX_ETHERNET_PACKET_SIZE 1514
3728#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9014
3729
3730#define RX_COPY_THRESH 92
3731
3732#define DMA_READ_CHANS 5
3733#define DMA_WRITE_CHANS 3
3734
3735#define BCM_PAGE_BITS 12
3736#define BCM_PAGE_SIZE (1 << BCM_PAGE_BITS)
3737
3738#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct tx_bd))
3739#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
3740
3741#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct rx_bd))
3742#define MAX_RX_DESC_CNT (RX_DESC_CNT - 1)
3743
3744#define NEXT_TX_BD(x) (((x) & (MAX_TX_DESC_CNT - 1)) == \
3745 (MAX_TX_DESC_CNT - 1)) ? \
3746 (x) + 2 : (x) + 1
3747
3748#define TX_RING_IDX(x) ((x) & MAX_TX_DESC_CNT)
3749
3750#define NEXT_RX_BD(x) (((x) & (MAX_RX_DESC_CNT - 1)) == \
3751 (MAX_RX_DESC_CNT - 1)) ? \
3752 (x) + 2 : (x) + 1
3753
3754#define RX_RING_IDX(x) ((x) & MAX_RX_DESC_CNT)
3755
3756
3757/* Context size. */
3758#define CTX_SHIFT 7
3759#define CTX_SIZE (1 << CTX_SHIFT)
3760#define CTX_MASK (CTX_SIZE - 1)
3761#define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT)
3762#define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT)
3763
3764#define PHY_CTX_SHIFT 6
3765#define PHY_CTX_SIZE (1 << PHY_CTX_SHIFT)
3766#define PHY_CTX_MASK (PHY_CTX_SIZE - 1)
3767#define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_CTX_SHIFT)
3768#define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_CTX_SHIFT)
3769
3770#define MB_KERNEL_CTX_SHIFT 8
3771#define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT)
3772#define MB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1)
3773#define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT))
3774
3775#define MAX_CID_CNT 0x4000
3776#define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT))
3777#define INVALID_CID_ADDR 0xffffffff
3778
3779#define TX_CID 16
3780#define RX_CID 0
3781
3782#define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID)
3783#define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID)
3784
3785struct sw_bd {
3786 struct sk_buff *skb;
3787 DECLARE_PCI_UNMAP_ADDR(mapping)
3788};
3789
3790/* Buffered flash (Atmel: AT45DB011B) specific information */
3791#define SEEPROM_PAGE_BITS 2
3792#define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS)
3793#define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1)
3794#define SEEPROM_PAGE_SIZE 4
3795#define SEEPROM_TOTAL_SIZE 65536
3796
3797#define BUFFERED_FLASH_PAGE_BITS 9
3798#define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS)
3799#define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1)
3800#define BUFFERED_FLASH_PAGE_SIZE 264
3801#define BUFFERED_FLASH_TOTAL_SIZE 131072
3802
3803#define SAIFUN_FLASH_PAGE_BITS 8
3804#define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS)
3805#define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1)
3806#define SAIFUN_FLASH_PAGE_SIZE 256
3807#define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536
3808
3809#define NVRAM_TIMEOUT_COUNT 30000
3810
3811
3812#define FLASH_STRAP_MASK (BNX2_NVM_CFG1_FLASH_MODE | \
3813 BNX2_NVM_CFG1_BUFFER_MODE | \
3814 BNX2_NVM_CFG1_PROTECT_MODE | \
3815 BNX2_NVM_CFG1_FLASH_SIZE)
3816
3817struct flash_spec {
3818 u32 strapping;
3819 u32 config1;
3820 u32 config2;
3821 u32 config3;
3822 u32 write1;
3823 u32 buffered;
3824 u32 page_bits;
3825 u32 page_size;
3826 u32 addr_mask;
3827 u32 total_size;
3828 u8 *name;
3829};
3830
3831struct bnx2 {
3832 /* Fields used in the tx and intr/napi performance paths are grouped */
3833 /* together in the beginning of the structure. */
3834 void __iomem *regview;
3835
3836 struct net_device *dev;
3837 struct pci_dev *pdev;
3838
3839 atomic_t intr_sem;
3840
3841 struct status_block *status_blk;
3842 u32 last_status_idx;
3843
3844 atomic_t tx_avail_bd;
3845 struct tx_bd *tx_desc_ring;
3846 struct sw_bd *tx_buf_ring;
3847 u32 tx_prod_bseq;
3848 u16 tx_prod;
3849 u16 tx_cons;
3850
3851#ifdef BCM_VLAN
3852 struct vlan_group *vlgrp;
3853#endif
3854
3855 u32 rx_offset;
3856 u32 rx_buf_use_size; /* useable size */
3857 u32 rx_buf_size; /* with alignment */
3858 struct rx_bd *rx_desc_ring;
3859 struct sw_bd *rx_buf_ring;
3860 u32 rx_prod_bseq;
3861 u16 rx_prod;
3862 u16 rx_cons;
3863
3864 u32 rx_csum;
3865
3866 /* Only used to synchronize netif_stop_queue/wake_queue when tx */
3867 /* ring is full */
3868 spinlock_t tx_lock;
3869
3870 /* End of fileds used in the performance code paths. */
3871
3872 char *name;
3873
3874 int timer_interval;
3875 struct timer_list timer;
3876 struct work_struct reset_task;
3877
3878 /* Used to synchronize phy accesses. */
3879 spinlock_t phy_lock;
3880
3881 u32 flags;
3882#define PCIX_FLAG 1
3883#define PCI_32BIT_FLAG 2
3884#define ONE_TDMA_FLAG 4 /* no longer used */
3885#define NO_WOL_FLAG 8
3886#define USING_DAC_FLAG 0x10
3887#define USING_MSI_FLAG 0x20
3888
3889 u32 phy_flags;
3890#define PHY_SERDES_FLAG 1
3891#define PHY_CRC_FIX_FLAG 2
3892#define PHY_PARALLEL_DETECT_FLAG 4
3893#define PHY_INT_MODE_MASK_FLAG 0x300
3894#define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100
3895#define PHY_INT_MODE_LINK_READY_FLAG 0x200
3896
3897 u32 chip_id;
3898 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
3899#define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000)
3900#define CHIP_NUM_5706 0x57060000
3901
3902#define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000)
3903#define CHIP_REV_Ax 0x00000000
3904#define CHIP_REV_Bx 0x00001000
3905#define CHIP_REV_Cx 0x00002000
3906
3907#define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0)
3908#define CHIP_BONDING(bp) (((bp)->chip_id) & 0x0000000f)
3909
3910#define CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0)
3911#define CHIP_ID_5706_A0 0x57060000
3912#define CHIP_ID_5706_A1 0x57060010
3913
3914#define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0xf)
3915
3916/* A serdes chip will have the first bit of the bond id set. */
3917#define CHIP_BOND_ID_SERDES_BIT 0x01
3918
3919 u32 phy_addr;
3920 u32 phy_id;
3921
3922 u16 bus_speed_mhz;
3923 u8 wol;
3924
3925 u8 fw_timed_out;
3926
3927 u16 fw_wr_seq;
3928 u16 fw_drv_pulse_wr_seq;
3929
3930 int tx_ring_size;
3931 dma_addr_t tx_desc_mapping;
3932
3933
3934 int rx_ring_size;
3935 dma_addr_t rx_desc_mapping;
3936
3937 u16 tx_quick_cons_trip;
3938 u16 tx_quick_cons_trip_int;
3939 u16 rx_quick_cons_trip;
3940 u16 rx_quick_cons_trip_int;
3941 u16 comp_prod_trip;
3942 u16 comp_prod_trip_int;
3943 u16 tx_ticks;
3944 u16 tx_ticks_int;
3945 u16 com_ticks;
3946 u16 com_ticks_int;
3947 u16 cmd_ticks;
3948 u16 cmd_ticks_int;
3949 u16 rx_ticks;
3950 u16 rx_ticks_int;
3951
3952 u32 stats_ticks;
3953
3954 dma_addr_t status_blk_mapping;
3955
3956 struct statistics_block *stats_blk;
3957 dma_addr_t stats_blk_mapping;
3958
3959 u32 rx_mode;
3960
3961 u16 req_line_speed;
3962 u8 req_duplex;
3963
3964 u8 link_up;
3965
3966 u16 line_speed;
3967 u8 duplex;
3968 u8 flow_ctrl; /* actual flow ctrl settings */
3969 /* may be different from */
3970 /* req_flow_ctrl if autoneg */
3971#define FLOW_CTRL_TX 1
3972#define FLOW_CTRL_RX 2
3973
3974 u32 advertising;
3975
3976 u8 req_flow_ctrl; /* flow ctrl advertisement */
3977 /* settings or forced */
3978 /* settings */
3979 u8 autoneg;
3980#define AUTONEG_SPEED 1
3981#define AUTONEG_FLOW_CTRL 2
3982
3983 u8 loopback;
3984#define MAC_LOOPBACK 1
3985#define PHY_LOOPBACK 2
3986
3987 u8 serdes_an_pending;
3988#define SERDES_AN_TIMEOUT (2 * HZ)
3989
3990 u8 mac_addr[8];
3991
3992 u32 fw_ver;
3993
3994 int pm_cap;
3995 int pcix_cap;
3996
3997 struct net_device_stats net_stats;
3998
3999 struct flash_spec *flash_info;
4000};
4001
4002static u32 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset);
4003static void bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val);
4004
4005#define REG_RD(bp, offset) \
4006 readl(bp->regview + offset)
4007
4008#define REG_WR(bp, offset, val) \
4009 writel(val, bp->regview + offset)
4010
4011#define REG_WR16(bp, offset, val) \
4012 writew(val, bp->regview + offset)
4013
4014#define REG_RD_IND(bp, offset) \
4015 bnx2_reg_rd_ind(bp, offset)
4016
4017#define REG_WR_IND(bp, offset, val) \
4018 bnx2_reg_wr_ind(bp, offset, val)
4019
4020/* Indirect context access. Unlike the MBQ_WR, these macros will not
4021 * trigger a chip event. */
4022static void bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val);
4023
4024#define CTX_WR(bp, cid_addr, offset, val) \
4025 bnx2_ctx_wr(bp, cid_addr, offset, val)
4026
4027struct cpu_reg {
4028 u32 mode;
4029 u32 mode_value_halt;
4030 u32 mode_value_sstep;
4031
4032 u32 state;
4033 u32 state_value_clear;
4034
4035 u32 gpr0;
4036 u32 evmask;
4037 u32 pc;
4038 u32 inst;
4039 u32 bp;
4040
4041 u32 spad_base;
4042
4043 u32 mips_view_base;
4044};
4045
4046struct fw_info {
4047 u32 ver_major;
4048 u32 ver_minor;
4049 u32 ver_fix;
4050
4051 u32 start_addr;
4052
4053 /* Text section. */
4054 u32 text_addr;
4055 u32 text_len;
4056 u32 text_index;
4057 u32 *text;
4058
4059 /* Data section. */
4060 u32 data_addr;
4061 u32 data_len;
4062 u32 data_index;
4063 u32 *data;
4064
4065 /* SBSS section. */
4066 u32 sbss_addr;
4067 u32 sbss_len;
4068 u32 sbss_index;
4069 u32 *sbss;
4070
4071 /* BSS section. */
4072 u32 bss_addr;
4073 u32 bss_len;
4074 u32 bss_index;
4075 u32 *bss;
4076
4077 /* Read-only section. */
4078 u32 rodata_addr;
4079 u32 rodata_len;
4080 u32 rodata_index;
4081 u32 *rodata;
4082};
4083
4084#define RV2P_PROC1 0
4085#define RV2P_PROC2 1
4086
4087
4088/* This value (in milliseconds) determines the frequency of the driver
4089 * issuing the PULSE message code. The firmware monitors this periodic
4090 * pulse to determine when to switch to an OS-absent mode. */
4091#define DRV_PULSE_PERIOD_MS 250
4092
4093/* This value (in milliseconds) determines how long the driver should
4094 * wait for an acknowledgement from the firmware before timing out. Once
4095 * the firmware has timed out, the driver will assume there is no firmware
4096 * running and there won't be any firmware-driver synchronization during a
4097 * driver reset. */
4098#define FW_ACK_TIME_OUT_MS 50
4099
4100
4101#define BNX2_DRV_RESET_SIGNATURE 0x00000000
4102#define BNX2_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */
4103//#define DRV_RESET_SIGNATURE_MAGIC 0x47495352 /* RSIG */
4104
4105#define BNX2_DRV_MB 0x00000004
4106#define BNX2_DRV_MSG_CODE 0xff000000
4107#define BNX2_DRV_MSG_CODE_RESET 0x01000000
4108#define BNX2_DRV_MSG_CODE_UNLOAD 0x02000000
4109#define BNX2_DRV_MSG_CODE_SHUTDOWN 0x03000000
4110#define BNX2_DRV_MSG_CODE_SUSPEND_WOL 0x04000000
4111#define BNX2_DRV_MSG_CODE_FW_TIMEOUT 0x05000000
4112#define BNX2_DRV_MSG_CODE_PULSE 0x06000000
4113#define BNX2_DRV_MSG_CODE_DIAG 0x07000000
4114#define BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000
4115
4116#define BNX2_DRV_MSG_DATA 0x00ff0000
4117#define BNX2_DRV_MSG_DATA_WAIT0 0x00010000
4118#define BNX2_DRV_MSG_DATA_WAIT1 0x00020000
4119#define BNX2_DRV_MSG_DATA_WAIT2 0x00030000
4120#define BNX2_DRV_MSG_DATA_WAIT3 0x00040000
4121
4122#define BNX2_DRV_MSG_SEQ 0x0000ffff
4123
4124#define BNX2_FW_MB 0x00000008
4125#define BNX2_FW_MSG_ACK 0x0000ffff
4126#define BNX2_FW_MSG_STATUS_MASK 0x00ff0000
4127#define BNX2_FW_MSG_STATUS_OK 0x00000000
4128#define BNX2_FW_MSG_STATUS_FAILURE 0x00ff0000
4129
4130#define BNX2_LINK_STATUS 0x0000000c
4131
4132#define BNX2_DRV_PULSE_MB 0x00000010
4133#define BNX2_DRV_PULSE_SEQ_MASK 0x0000ffff
4134
4135/* Indicate to the firmware not to go into the
4136 * OS absent when it is not getting driver pulse.
4137 * This is used for debugging. */
4138#define BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00010000
4139
4140#define BNX2_DEV_INFO_SIGNATURE 0x00000020
4141#define BNX2_DEV_INFO_SIGNATURE_MAGIC 0x44564900
4142#define BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00
4143#define BNX2_DEV_INFO_FEATURE_CFG_VALID 0x01
4144#define BNX2_DEV_INFO_SECONDARY_PORT 0x80
4145#define BNX2_DEV_INFO_DRV_ALWAYS_ALIVE 0x40
4146
4147#define BNX2_SHARED_HW_CFG_PART_NUM 0x00000024
4148
4149#define BNX2_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034
4150#define BNX2_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000
4151#define BNX2_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000
4152#define BNX2_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00
4153#define BNX2_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff
4154
4155#define BNX2_SHARED_HW_CFG POWER_CONSUMED 0x00000038
4156#define BNX2_SHARED_HW_CFG_CONFIG 0x0000003c
4157#define BNX2_SHARED_HW_CFG_DESIGN_NIC 0
4158#define BNX2_SHARED_HW_CFG_DESIGN_LOM 0x1
4159#define BNX2_SHARED_HW_CFG_PHY_COPPER 0
4160#define BNX2_SHARED_HW_CFG_PHY_FIBER 0x2
4161#define BNX2_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8
4162#define BNX2_SHARED_HW_CFG_LED_MODE_MASK 0x300
4163#define BNX2_SHARED_HW_CFG_LED_MODE_MAC 0
4164#define BNX2_SHARED_HW_CFG_LED_MODE_GPHY1 0x100
4165#define BNX2_SHARED_HW_CFG_LED_MODE_GPHY2 0x200
4166
4167#define BNX2_DEV_INFO_BC_REV 0x0000004c
4168
4169#define BNX2_PORT_HW_CFG_MAC_UPPER 0x00000050
4170#define BNX2_PORT_HW_CFG_UPPERMAC_MASK 0xffff
4171
4172#define BNX2_PORT_HW_CFG_MAC_LOWER 0x00000054
4173#define BNX2_PORT_HW_CFG_CONFIG 0x00000058
4174
4175#define BNX2_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068
4176#define BNX2_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c
4177#define BNX2_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070
4178#define BNX2_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074
4179#define BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078
4180#define BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c
4181
4182#define BNX2_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4
4183
4184#define BNX2_DEV_INFO_FORMAT_REV 0x000000c4
4185#define BNX2_DEV_INFO_FORMAT_REV_MASK 0xff000000
4186#define BNX2_DEV_INFO_FORMAT_REV_ID ('A' << 24)
4187
4188#define BNX2_SHARED_FEATURE 0x000000c8
4189#define BNX2_SHARED_FEATURE_MASK 0xffffffff
4190
4191#define BNX2_PORT_FEATURE 0x000000d8
4192#define BNX2_PORT2_FEATURE 0x00000014c
4193#define BNX2_PORT_FEATURE_WOL_ENABLED 0x01000000
4194#define BNX2_PORT_FEATURE_MBA_ENABLED 0x02000000
4195#define BNX2_PORT_FEATURE_ASF_ENABLED 0x04000000
4196#define BNX2_PORT_FEATURE_IMD_ENABLED 0x08000000
4197#define BNX2_PORT_FEATURE_BAR1_SIZE_MASK 0xf
4198#define BNX2_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0
4199#define BNX2_PORT_FEATURE_BAR1_SIZE_64K 0x1
4200#define BNX2_PORT_FEATURE_BAR1_SIZE_128K 0x2
4201#define BNX2_PORT_FEATURE_BAR1_SIZE_256K 0x3
4202#define BNX2_PORT_FEATURE_BAR1_SIZE_512K 0x4
4203#define BNX2_PORT_FEATURE_BAR1_SIZE_1M 0x5
4204#define BNX2_PORT_FEATURE_BAR1_SIZE_2M 0x6
4205#define BNX2_PORT_FEATURE_BAR1_SIZE_4M 0x7
4206#define BNX2_PORT_FEATURE_BAR1_SIZE_8M 0x8
4207#define BNX2_PORT_FEATURE_BAR1_SIZE_16M 0x9
4208#define BNX2_PORT_FEATURE_BAR1_SIZE_32M 0xa
4209#define BNX2_PORT_FEATURE_BAR1_SIZE_64M 0xb
4210#define BNX2_PORT_FEATURE_BAR1_SIZE_128M 0xc
4211#define BNX2_PORT_FEATURE_BAR1_SIZE_256M 0xd
4212#define BNX2_PORT_FEATURE_BAR1_SIZE_512M 0xe
4213#define BNX2_PORT_FEATURE_BAR1_SIZE_1G 0xf
4214
4215#define BNX2_PORT_FEATURE_WOL 0xdc
4216#define BNX2_PORT2_FEATURE_WOL 0x150
4217#define BNX2_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS 4
4218#define BNX2_PORT_FEATURE_WOL_DEFAULT_MASK 0x30
4219#define BNX2_PORT_FEATURE_WOL_DEFAULT_DISABLE 0
4220#define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10
4221#define BNX2_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20
4222#define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30
4223#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf
4224#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0
4225#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10HALF 1
4226#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10FULL 2
4227#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3
4228#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4
4229#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000HALF 5
4230#define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000FULL 6
4231#define BNX2_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40
4232#define BNX2_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400
4233#define BNX2_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800
4234
4235#define BNX2_PORT_FEATURE_MBA 0xe0
4236#define BNX2_PORT2_FEATURE_MBA 0x154
4237#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0
4238#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3
4239#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0
4240#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1
4241#define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2
4242#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2
4243#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c
4244#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0
4245#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4
4246#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8
4247#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc
4248#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10
4249#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14
4250#define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18
4251#define BNX2_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40
4252#define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0
4253#define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80
4254#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8
4255#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00
4256#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0
4257#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100
4258#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200
4259#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300
4260#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400
4261#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500
4262#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600
4263#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700
4264#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800
4265#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900
4266#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00
4267#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00
4268#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00
4269#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00
4270#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00
4271#define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00
4272#define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16
4273#define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000
4274#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20
4275#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000
4276#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0
4277#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000
4278#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000
4279#define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000
4280
4281#define BNX2_PORT_FEATURE_IMD 0xe4
4282#define BNX2_PORT2_FEATURE_IMD 0x158
4283#define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0
4284#define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE 1
4285
4286#define BNX2_PORT_FEATURE_VLAN 0xe8
4287#define BNX2_PORT2_FEATURE_VLAN 0x15c
4288#define BNX2_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff
4289#define BNX2_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000
4290
4291#define BNX2_BC_STATE_RESET_TYPE 0x000001c0
4292#define BNX2_BC_STATE_RESET_TYPE_SIG 0x00005254
4293#define BNX2_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff
4294#define BNX2_BC_STATE_RESET_TYPE_NONE (BNX2_BC_STATE_RESET_TYPE_SIG | \
4295 0x00010000)
4296#define BNX2_BC_STATE_RESET_TYPE_PCI (BNX2_BC_STATE_RESET_TYPE_SIG | \
4297 0x00020000)
4298#define BNX2_BC_STATE_RESET_TYPE_VAUX (BNX2_BC_STATE_RESET_TYPE_SIG | \
4299 0x00030000)
4300#define BNX2_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE
4301#define BNX2_BC_STATE_RESET_TYPE_DRV_RESET (BNX2_BC_STATE_RESET_TYPE_SIG | \
4302 DRV_MSG_CODE_RESET)
4303#define BNX2_BC_STATE_RESET_TYPE_DRV_UNLOAD (BNX2_BC_STATE_RESET_TYPE_SIG | \
4304 DRV_MSG_CODE_UNLOAD)
4305#define BNX2_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BNX2_BC_STATE_RESET_TYPE_SIG | \
4306 DRV_MSG_CODE_SHUTDOWN)
4307#define BNX2_BC_STATE_RESET_TYPE_DRV_WOL (BNX2_BC_STATE_RESET_TYPE_SIG | \
4308 DRV_MSG_CODE_WOL)
4309#define BNX2_BC_STATE_RESET_TYPE_DRV_DIAG (BNX2_BC_STATE_RESET_TYPE_SIG | \
4310 DRV_MSG_CODE_DIAG)
4311#define BNX2_BC_STATE_RESET_TYPE_VALUE(msg) (BNX2_BC_STATE_RESET_TYPE_SIG | \
4312 (msg))
4313
4314#define BNX2_BC_STATE 0x000001c4
4315#define BNX2_BC_STATE_ERR_MASK 0x0000ff00
4316#define BNX2_BC_STATE_SIGN 0x42530000
4317#define BNX2_BC_STATE_SIGN_MASK 0xffff0000
4318#define BNX2_BC_STATE_BC1_START (BNX2_BC_STATE_SIGN | 0x1)
4319#define BNX2_BC_STATE_GET_NVM_CFG1 (BNX2_BC_STATE_SIGN | 0x2)
4320#define BNX2_BC_STATE_PROG_BAR (BNX2_BC_STATE_SIGN | 0x3)
4321#define BNX2_BC_STATE_INIT_VID (BNX2_BC_STATE_SIGN | 0x4)
4322#define BNX2_BC_STATE_GET_NVM_CFG2 (BNX2_BC_STATE_SIGN | 0x5)
4323#define BNX2_BC_STATE_APPLY_WKARND (BNX2_BC_STATE_SIGN | 0x6)
4324#define BNX2_BC_STATE_LOAD_BC2 (BNX2_BC_STATE_SIGN | 0x7)
4325#define BNX2_BC_STATE_GOING_BC2 (BNX2_BC_STATE_SIGN | 0x8)
4326#define BNX2_BC_STATE_GOING_DIAG (BNX2_BC_STATE_SIGN | 0x9)
4327#define BNX2_BC_STATE_RT_FINAL_INIT (BNX2_BC_STATE_SIGN | 0x81)
4328#define BNX2_BC_STATE_RT_WKARND (BNX2_BC_STATE_SIGN | 0x82)
4329#define BNX2_BC_STATE_RT_DRV_PULSE (BNX2_BC_STATE_SIGN | 0x83)
4330#define BNX2_BC_STATE_RT_FIOEVTS (BNX2_BC_STATE_SIGN | 0x84)
4331#define BNX2_BC_STATE_RT_DRV_CMD (BNX2_BC_STATE_SIGN | 0x85)
4332#define BNX2_BC_STATE_RT_LOW_POWER (BNX2_BC_STATE_SIGN | 0x86)
4333#define BNX2_BC_STATE_RT_SET_WOL (BNX2_BC_STATE_SIGN | 0x87)
4334#define BNX2_BC_STATE_RT_OTHER_FW (BNX2_BC_STATE_SIGN | 0x88)
4335#define BNX2_BC_STATE_RT_GOING_D3 (BNX2_BC_STATE_SIGN | 0x89)
4336#define BNX2_BC_STATE_ERR_BAD_VERSION (BNX2_BC_STATE_SIGN | 0x0100)
4337#define BNX2_BC_STATE_ERR_BAD_BC2_CRC (BNX2_BC_STATE_SIGN | 0x0200)
4338#define BNX2_BC_STATE_ERR_BC1_LOOP (BNX2_BC_STATE_SIGN | 0x0300)
4339#define BNX2_BC_STATE_ERR_UNKNOWN_CMD (BNX2_BC_STATE_SIGN | 0x0400)
4340#define BNX2_BC_STATE_ERR_DRV_DEAD (BNX2_BC_STATE_SIGN | 0x0500)
4341#define BNX2_BC_STATE_ERR_NO_RXP (BNX2_BC_STATE_SIGN | 0x0600)
4342#define BNX2_BC_STATE_ERR_TOO_MANY_RBUF (BNX2_BC_STATE_SIGN | 0x0700)
4343
4344#define BNX2_BC_STATE_DEBUG_CMD 0x1dc
4345#define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000
4346#define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000
4347#define BNX2_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff
4348#define BNX2_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff
4349
4350#define HOST_VIEW_SHMEM_BASE 0x167c00
4351
4352#endif
diff --git a/drivers/net/bnx2_fw.h b/drivers/net/bnx2_fw.h
new file mode 100644
index 000000000000..35f3a2ae5ef1
--- /dev/null
+++ b/drivers/net/bnx2_fw.h
@@ -0,0 +1,2468 @@
1/* bnx2_fw.h: Broadcom NX2 network driver.
2 *
3 * Copyright (c) 2004, 2005 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation, except as noted below.
8 *
9 * This file contains firmware data derived from proprietary unpublished
10 * source code, Copyright (c) 2004, 2005 Broadcom Corporation.
11 *
12 * Permission is hereby granted for the distribution of this firmware data
13 * in hexadecimal or equivalent format, provided this copyright notice is
14 * accompanying it.
15 */
16
17
18static int bnx2_COM_b06FwReleaseMajor = 0x0;
19static int bnx2_COM_b06FwReleaseMinor = 0x0;
20static int bnx2_COM_b06FwReleaseFix = 0x0;
21static u32 bnx2_COM_b06FwStartAddr = 0x080004a0;
22static u32 bnx2_COM_b06FwTextAddr = 0x08000000;
23static int bnx2_COM_b06FwTextLen = 0x4594;
24static u32 bnx2_COM_b06FwDataAddr = 0x080045e0;
25static int bnx2_COM_b06FwDataLen = 0x0;
26static u32 bnx2_COM_b06FwRodataAddr = 0x08004598;
27static int bnx2_COM_b06FwRodataLen = 0x18;
28static u32 bnx2_COM_b06FwBssAddr = 0x08004600;
29static int bnx2_COM_b06FwBssLen = 0x88;
30static u32 bnx2_COM_b06FwSbssAddr = 0x080045e0;
31static int bnx2_COM_b06FwSbssLen = 0x1c;
32static u32 bnx2_COM_b06FwText[(0x4594/4) + 1] = {
33 0x0a000128, 0x00000000, 0x00000000, 0x0000000d, 0x636f6d20, 0x302e362e,
34 0x39000000, 0x00060902, 0x00000000, 0x00000003, 0x00000014, 0x00000032,
35 0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
36 0x00000010, 0x000003e8, 0x0000ea60, 0x00000001, 0x00000000, 0x00000000,
37 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
38 0x0000ffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
39 0x00000000, 0x00000000, 0x00000002, 0x00000020, 0x00000000, 0x00000000,
40 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
41 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
42 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
43 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
44 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
45 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
46 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
47 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
48 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
49 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
50 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
51 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
52 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
53 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
54 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
55 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
56 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
57 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
58 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
59 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
60 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
61 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
62 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
63 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
64 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
65 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
66 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
67 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
68 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
69 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
70 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
71 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
72 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
73 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
74 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
75 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
76 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
77 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
78 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
79 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
80 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
81 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
82 0x00000000, 0x00000000, 0x00000000, 0x10000003, 0x00000000, 0x0000000d,
83 0x0000000d, 0x3c020800, 0x244245e0, 0x3c030800, 0x24634688, 0xac400000,
84 0x0043202b, 0x1480fffd, 0x24420004, 0x3c1d0800, 0x37bd7ffc, 0x03a0f021,
85 0x3c100800, 0x261004a0, 0x3c1c0800, 0x279c45e0, 0x0e0001f2, 0x00000000,
86 0x0000000d, 0x27bdffe8, 0x3c1a8000, 0x3c020008, 0x0342d825, 0x3c036010,
87 0xafbf0010, 0x8c655000, 0x3c020800, 0x24470ac8, 0x3c040800, 0x24864600,
88 0x2402ff7f, 0x00a22824, 0x34a5380c, 0xac655000, 0x00002821, 0x24020037,
89 0x24030c80, 0xaf420008, 0xaf430024, 0xacc70000, 0x24a50001, 0x2ca20016,
90 0x1440fffc, 0x24c60004, 0x24844600, 0x3c020800, 0x24420ad4, 0x3c030800,
91 0x246309d4, 0xac820004, 0x3c020800, 0x24420618, 0x3c050800, 0x24a50ca0,
92 0xac82000c, 0x3c020800, 0x24423100, 0xac830008, 0x3c030800, 0x246325c8,
93 0xac820014, 0x3c020800, 0x24422b0c, 0xac830018, 0xac83001c, 0x3c030800,
94 0x24630adc, 0xac820024, 0x3c020800, 0x24423040, 0xac83002c, 0x3c030800,
95 0x24633060, 0xac820030, 0x3c020800, 0x24422f6c, 0xac830034, 0x3c030800,
96 0x24632c60, 0xac82003c, 0x3c020800, 0x24420b6c, 0xac850010, 0xac850020,
97 0xac830040, 0x0e000bd6, 0xac820050, 0x8fbf0010, 0x03e00008, 0x27bd0018,
98 0x27bdffe0, 0xafb00010, 0x27500100, 0xafbf0018, 0xafb10014, 0x9203000b,
99 0x24020003, 0x1462005b, 0x96110008, 0x32220001, 0x10400009, 0x27430080,
100 0x8e020000, 0x96040014, 0x000211c2, 0x00021040, 0x00621821, 0xa4640000,
101 0x0a0001cb, 0x3c020800, 0x3c020800, 0x8c430020, 0x1060002a, 0x3c030800,
102 0x0e001006, 0x00000000, 0x97420108, 0x8f850018, 0x9743010c, 0x3042003e,
103 0x00021400, 0x00621825, 0xaca30000, 0x8f840018, 0x8f420100, 0xac820004,
104 0x97430116, 0x9742010e, 0x8f840018, 0x00031c00, 0x00431025, 0xac820008,
105 0x97430110, 0x97440112, 0x8f850018, 0x00031c00, 0x00832025, 0xaca4000c,
106 0x97420114, 0x8f840018, 0x3042ffff, 0xac820010, 0x8f830018, 0xac600014,
107 0x8f820018, 0x3c030800, 0xac400018, 0x9462466e, 0x8f840018, 0x3c032000,
108 0x00431025, 0xac82001c, 0x0e001044, 0x24040001, 0x3c030800, 0x8c620040,
109 0x24420001, 0xac620040, 0x3c020800, 0x8c430044, 0x32240004, 0x24630001,
110 0x10800017, 0xac430044, 0x8f4202b8, 0x04430007, 0x8e020020, 0x3c040800,
111 0x8c830060, 0x24020001, 0x24630001, 0x0a0001ed, 0xac830060, 0x3c060800,
112 0x8cc4005c, 0xaf420280, 0x96030016, 0x00001021, 0xa7430284, 0x8e050004,
113 0x24840001, 0x3c031000, 0xaf450288, 0xaf4302b8, 0x0a0001ed, 0xacc4005c,
114 0x32220002, 0x0a0001ed, 0x0002102b, 0x3c026000, 0xac400808, 0x0000000d,
115 0x00001021, 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
116 0x27bdffc8, 0xafbf0034, 0xafbe0030, 0xafb7002c, 0xafb60028, 0xafb50024,
117 0xafb40020, 0xafb3001c, 0xafb20018, 0xafb10014, 0x0e00013f, 0xafb00010,
118 0x24110020, 0x24150030, 0x2794000c, 0x27930008, 0x3c124000, 0x3c1e0800,
119 0x3c170800, 0x3c160800, 0x8f820004, 0x3c040800, 0x8c830020, 0x10430004,
120 0x00000000, 0xaf830004, 0x0e00110b, 0x00000000, 0x8f500000, 0x32020007,
121 0x1040fff5, 0x32020001, 0x1040002b, 0x32020002, 0x8f420100, 0xaf420020,
122 0x8f430104, 0xaf4300a8, 0x9342010b, 0x93630000, 0x306300ff, 0x10710005,
123 0x304400ff, 0x10750006, 0x2c820016, 0x0a000227, 0x00000000, 0xaf940000,
124 0x0a000228, 0x2c820016, 0xaf930000, 0x0a000228, 0x00000000, 0xaf800000,
125 0x14400005, 0x00041880, 0x0e0002b2, 0x00000000, 0x0a000234, 0x00000000,
126 0x3c020800, 0x24424600, 0x00621821, 0x8c620000, 0x0040f809, 0x00000000,
127 0x10400005, 0x8fc20034, 0x8f420104, 0x3c016020, 0xac220014, 0x8fc20034,
128 0xaf520138, 0x24420001, 0xafc20034, 0x32020002, 0x10400019, 0x32020004,
129 0x8f420140, 0xaf420020, 0x93630000, 0x306300ff, 0x10710005, 0x00000000,
130 0x10750006, 0x00000000, 0x0a000250, 0x00000000, 0xaf940000, 0x0a000251,
131 0x00000000, 0xaf930000, 0x0a000251, 0x00000000, 0xaf800000, 0x0e0008b9,
132 0x00000000, 0x8ee20038, 0xaf520178, 0x24420001, 0xaee20038, 0x32020004,
133 0x1040ffad, 0x00000000, 0x8f420180, 0xaf420020, 0x93630000, 0x306300ff,
134 0x10710005, 0x00000000, 0x10750006, 0x00000000, 0x0a00026a, 0x00000000,
135 0xaf940000, 0x0a00026b, 0x00000000, 0xaf930000, 0x0a00026b, 0x00000000,
136 0xaf800000, 0x93620000, 0x14510004, 0x8ec2003c, 0x0e000835, 0x00000000,
137 0x8ec2003c, 0xaf5201b8, 0x24420001, 0x0a000206, 0xaec2003c, 0x27bdffe8,
138 0xafbf0010, 0x97420108, 0x24033000, 0x30447000, 0x10830012, 0x28823001,
139 0x10400007, 0x24024000, 0x1080000b, 0x24022000, 0x1082001a, 0x24020001,
140 0x0a000299, 0x00000000, 0x1082000c, 0x24025000, 0x1082000e, 0x00000000,
141 0x0a000299, 0x00000000, 0x0000000d, 0x0a00029b, 0x00001021, 0x0e000300,
142 0x00000000, 0x0a00029b, 0x00001021, 0x0e00048f, 0x00000000, 0x0a00029b,
143 0x00001021, 0x0e000fdf, 0x00000000, 0x0a00029b, 0x00001021, 0x0000000d,
144 0x00001021, 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x93620000, 0x24030020,
145 0x304400ff, 0x10830005, 0x24020030, 0x10820007, 0x00000000, 0x0a0002af,
146 0x00000000, 0x2782000c, 0xaf820000, 0x03e00008, 0x00000000, 0x27820008,
147 0xaf820000, 0x03e00008, 0x00000000, 0xaf800000, 0x03e00008, 0x00000000,
148 0x0000000d, 0x03e00008, 0x00001021, 0x03e00008, 0x00001021, 0x27440100,
149 0x94830008, 0x30620004, 0x10400017, 0x30620002, 0x8f4202b8, 0x04430007,
150 0x8c820020, 0x3c040800, 0x8c830060, 0x24020001, 0x24630001, 0x03e00008,
151 0xac830060, 0xaf420280, 0x94830016, 0x3c060800, 0xa7430284, 0x8c850004,
152 0x8cc4005c, 0x00001021, 0x3c031000, 0x24840001, 0xaf450288, 0xaf4302b8,
153 0x03e00008, 0xacc4005c, 0x14400003, 0x3c040800, 0x03e00008, 0x00001021,
154 0x8c830084, 0x24020001, 0x24630001, 0x03e00008, 0xac830084, 0x27450100,
155 0x3c040800, 0x8c820088, 0x94a3000c, 0x24420001, 0x007a1821, 0xac820088,
156 0x8ca40018, 0x90664000, 0xaf440038, 0x8ca2001c, 0x2403fff8, 0x00063600,
157 0x00431024, 0x34420004, 0x3c030005, 0xaf42003c, 0xaf430030, 0x00000000,
158 0x00000000, 0x00000000, 0xaf460404, 0x00000000, 0x00000000, 0x00000000,
159 0x3c020006, 0x34420001, 0xaf420030, 0x00000000, 0x00000000, 0x00000000,
160 0x8f420000, 0x30420010, 0x1040fffd, 0x00001021, 0x03e00008, 0x00000000,
161 0x3c020800, 0x8c430020, 0x27bdffe8, 0xafb00010, 0x27500100, 0x1060001e,
162 0xafbf0014, 0x0e001006, 0x00000000, 0x8f830018, 0x8e020018, 0xac620000,
163 0x8f840018, 0x9602000c, 0xac820004, 0x8f830018, 0xac600008, 0x8f820018,
164 0xac40000c, 0x8f830018, 0xac600010, 0x8f820018, 0xac400014, 0x8f840018,
165 0x3c026000, 0x8c434448, 0xac830018, 0x96020008, 0x3c030800, 0x9464466e,
166 0x8f850018, 0x00021400, 0x00441025, 0x24040001, 0x0e001044, 0xaca2001c,
167 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdffc8, 0xafb3001c,
168 0x00009821, 0xafb7002c, 0x0000b821, 0xafbe0030, 0x0000f021, 0xafb50024,
169 0x27550100, 0xafbf0034, 0xafb60028, 0xafb40020, 0xafb20018, 0xafb10014,
170 0xafb00010, 0x96a20008, 0x8f540100, 0x8eb20018, 0x30420001, 0x10400037,
171 0x02a0b021, 0x8f630054, 0x2642ffff, 0x00431023, 0x18400006, 0x00000000,
172 0x0000000d, 0x00000000, 0x24000128, 0x0a000372, 0x00002021, 0x8f62004c,
173 0x02421023, 0x18400028, 0x00002021, 0x93650120, 0x93640121, 0x3c030800,
174 0x8c62008c, 0x308400ff, 0x24420001, 0x30a500ff, 0x00803821, 0x1485000b,
175 0xac62008c, 0x3c040800, 0x8c830090, 0x24630001, 0xac830090, 0x93620122,
176 0x30420001, 0x00021023, 0x30420005, 0x0a000372, 0x34440004, 0x27660100,
177 0x00041080, 0x00c21021, 0x8c430000, 0x02431823, 0x04600004, 0x24820001,
178 0x30440007, 0x1485fff9, 0x00041080, 0x10870007, 0x3c030800, 0xa3640121,
179 0x8c620094, 0x24040005, 0x24420001, 0x0a000372, 0xac620094, 0x24040004,
180 0x00809821, 0x9362003f, 0x304400ff, 0x38830016, 0x2c630001, 0x38820010,
181 0x2c420001, 0x00621825, 0x1460000c, 0x24020001, 0x38830008, 0x2c630001,
182 0x38820014, 0x2c420001, 0x00621825, 0x14600005, 0x24020001, 0x24020012,
183 0x14820002, 0x00001021, 0x24020001, 0x50400007, 0x8eb10020, 0x8ea20020,
184 0x8f630040, 0x00408821, 0x00431023, 0x5c400001, 0x8f710040, 0x9343010b,
185 0x24020004, 0x54620005, 0x36730080, 0x96a20008, 0x36730002, 0x24170001,
186 0x305e0020, 0x2402fffb, 0x02628024, 0x1200002a, 0x3c030800, 0x8c620030,
187 0x02021024, 0x10400026, 0x3c020800, 0x8c430020, 0x10600024, 0x32620004,
188 0x0e001006, 0x00000000, 0x8f830018, 0x8f420100, 0xac620000, 0x8f840018,
189 0x02201821, 0x32620002, 0xac900004, 0x8f840018, 0x50400001, 0x8ec30014,
190 0xac830008, 0x8f830018, 0x8ec20020, 0xac62000c, 0x8f840018, 0x8f620040,
191 0xac820010, 0x8f830018, 0x8ec20018, 0xac620014, 0x8f840018, 0x3c026000,
192 0x8c434448, 0x3c020800, 0xac830018, 0x9443466e, 0x8f840018, 0x3c024010,
193 0x00621825, 0xac83001c, 0x0e001044, 0x24040001, 0x32620004, 0x10400076,
194 0x00003821, 0x3c029000, 0x34420001, 0x3c038000, 0x02821025, 0xa360007c,
195 0xaf420020, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93620023,
196 0x30420080, 0x10400011, 0x00000000, 0x8f65005c, 0x8f63004c, 0x9764003c,
197 0x8f620064, 0x00a32823, 0x00852821, 0x00a2102b, 0x54400006, 0x3c023fff,
198 0x93620023, 0x3042007f, 0xa3620023, 0xaf720064, 0x3c023fff, 0x0a0003f1,
199 0x3442ffff, 0x8f62005c, 0x02421023, 0x04400011, 0x00000000, 0x8f65005c,
200 0x8f630064, 0x9764003c, 0x3c023fff, 0x3442ffff, 0xaf720064, 0x00a32823,
201 0x00852821, 0x0045102b, 0x10400004, 0x02451021, 0x3c053fff, 0x34a5ffff,
202 0x02451021, 0xaf62005c, 0x24070001, 0xaf72004c, 0x8f620054, 0x16420005,
203 0x00000000, 0x93620023, 0x30420040, 0x10400017, 0x24020001, 0x9762006a,
204 0x00022880, 0x50a00001, 0x24050001, 0x97630068, 0x93640081, 0x3c020800,
205 0x8c46004c, 0x00652821, 0x00852804, 0x00c5102b, 0x54400001, 0x00a03021,
206 0x3c020800, 0x8c440050, 0x00c4182b, 0x54600001, 0x00c02021, 0x8f420074,
207 0x2403fffe, 0x00832824, 0x00a21021, 0xaf62000c, 0x3c028000, 0x34420001,
208 0x02821025, 0xa3600081, 0xaf420020, 0x9363007e, 0x9362007a, 0x10620004,
209 0x00000000, 0x0e000f2a, 0x00000000, 0x00403821, 0x10e00017, 0x3c029000,
210 0x34420001, 0x02821025, 0xaf420020, 0x3c038000, 0x8f420020, 0x00431024,
211 0x1440fffd, 0x3c028000, 0x9363007d, 0x34420001, 0x3c048000, 0x02821025,
212 0xa363007d, 0xaf420020, 0x8f4201f8, 0x00441024, 0x1440fffd, 0x24020002,
213 0x3c031000, 0xaf5401c0, 0xa34201c4, 0xaf4301f8, 0x8ea30014, 0x8f620040,
214 0x14430003, 0x00431023, 0x0a000443, 0x00001021, 0x28420001, 0x10400034,
215 0x00000000, 0x8f620040, 0xaf630040, 0x9362003e, 0x30420001, 0x1440000b,
216 0x3c029000, 0x93620022, 0x24420001, 0xa3620022, 0x93630022, 0x3c020800,
217 0x8c440098, 0x0064182b, 0x1460001e, 0x3c020800, 0x3c029000, 0x34420001,
218 0x02821025, 0xaf420020, 0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd,
219 0x00000000, 0x3c038000, 0x9362007d, 0x34630001, 0x3c048000, 0x02831825,
220 0x34420001, 0xa362007d, 0xaf430020, 0x8f4201f8, 0x00441024, 0x1440fffd,
221 0x24020002, 0x3c031000, 0xaf5401c0, 0xa34201c4, 0x24020001, 0xaf4301f8,
222 0xa7620012, 0x0a000476, 0xa3600022, 0x9743007a, 0x9444002a, 0x00641821,
223 0x3063fffe, 0xa7630012, 0x0e000b68, 0x00000000, 0x12e00003, 0x00000000,
224 0x0e000f27, 0x00000000, 0x53c00004, 0x96a20008, 0x0e000c10, 0x00000000,
225 0x96a20008, 0x8fbf0034, 0x8fbe0030, 0x8fb7002c, 0x8fb60028, 0x8fb50024,
226 0x8fb40020, 0x8fb3001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x00021042,
227 0x30420001, 0x03e00008, 0x27bd0038, 0x27bdffe8, 0xafbf0010, 0x97420108,
228 0x2403000b, 0x304400ff, 0x1083004e, 0x2882000c, 0x10400011, 0x24020006,
229 0x1082003e, 0x28820007, 0x10400007, 0x28820008, 0x1080002b, 0x24020001,
230 0x1082002e, 0x3c026000, 0x0a000504, 0x00000000, 0x14400061, 0x2882000a,
231 0x1440002b, 0x00000000, 0x0a0004ec, 0x00000000, 0x2402001c, 0x1082004e,
232 0x2882001d, 0x1040000e, 0x24020019, 0x10820041, 0x2882001a, 0x10400005,
233 0x2402000e, 0x10820036, 0x00000000, 0x0a000504, 0x00000000, 0x2402001b,
234 0x1082003c, 0x00000000, 0x0a000504, 0x00000000, 0x240200c1, 0x10820040,
235 0x288200c2, 0x10400005, 0x24020080, 0x1082001f, 0x00000000, 0x0a000504,
236 0x00000000, 0x240200c2, 0x1082003b, 0x00000000, 0x0a000504, 0x00000000,
237 0x3c026000, 0x0e000c7d, 0xac400808, 0x0a000506, 0x8fbf0010, 0x8c444448,
238 0x3c030800, 0xac640064, 0x0e000c7d, 0x00000000, 0x3c026000, 0x8c444448,
239 0x3c030800, 0x0a000505, 0xac640068, 0x8f440100, 0x0e000508, 0x00000000,
240 0x3c026000, 0x8c444448, 0x3c030800, 0x0a000505, 0xac64006c, 0x0e000cab,
241 0x00000000, 0x0a000506, 0x8fbf0010, 0x8f440100, 0x0e000cd5, 0x00000000,
242 0x0a000506, 0x8fbf0010, 0x0e000d1c, 0x00000000, 0x0a000506, 0x8fbf0010,
243 0x0000000d, 0x0a000506, 0x8fbf0010, 0x0e0005d7, 0x00000000, 0x0a000506,
244 0x8fbf0010, 0x8f440100, 0x0e000d7e, 0x00000000, 0x0a000506, 0x8fbf0010,
245 0x0e000e95, 0x00000000, 0x0a000506, 0x8fbf0010, 0x0e000626, 0x00000000,
246 0x0a000506, 0x8fbf0010, 0x0e000b68, 0x00000000, 0x0a000506, 0x8fbf0010,
247 0x0000000d, 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x27bdffe8, 0x3c029000,
248 0x34420001, 0xafb00010, 0x00808021, 0x02021025, 0x3c038000, 0xafbf0014,
249 0xaf420020, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93620005,
250 0x34420001, 0xa3620005, 0x8f63004c, 0x8f620054, 0x10620019, 0x3c028000,
251 0x9762006a, 0x00022880, 0x50a00001, 0x24050001, 0x97630068, 0x93640081,
252 0x3c020800, 0x8c46004c, 0x00652821, 0x00852804, 0x00c5102b, 0x54400001,
253 0x00a03021, 0x3c020800, 0x8c440050, 0x00c4182b, 0x54600001, 0x00c02021,
254 0x8f420074, 0x2403fffe, 0x00832824, 0x00a21021, 0xaf62000c, 0x3c028000,
255 0x34420001, 0x02021025, 0x0e000c7d, 0xaf420020, 0x3c029000, 0x34420001,
256 0x3c038000, 0x02021025, 0xaf420020, 0x8f420020, 0x00431024, 0x1440fffd,
257 0x3c028000, 0x9363007d, 0x34420001, 0x3c048000, 0x02021025, 0xa363007d,
258 0xaf420020, 0x8f4201f8, 0x00441024, 0x1440fffd, 0x8fbf0014, 0xaf5001c0,
259 0x8fb00010, 0x24020002, 0x3c031000, 0xa34201c4, 0xaf4301f8, 0x03e00008,
260 0x27bd0018, 0x27bdffd8, 0xafbf0020, 0xafb3001c, 0xafb20018, 0xafb10014,
261 0xafb00010, 0x93630005, 0x00809021, 0x24020030, 0x30630030, 0x14620072,
262 0x00a09821, 0x3c020800, 0x8c430020, 0x1060006c, 0x00000000, 0x0e001006,
263 0x00000000, 0x8f820018, 0xac520000, 0x9363003e, 0x9362003f, 0x8f840018,
264 0x00031a00, 0x00431025, 0xac820004, 0x93630081, 0x93620082, 0x8f850018,
265 0x00031e00, 0x00021400, 0x00621825, 0xaca30008, 0x8f840018, 0x8f620040,
266 0xac82000c, 0x8f830018, 0x8f620048, 0xac620010, 0x8f840018, 0x8f62004c,
267 0x3c110800, 0xac820014, 0x8f830018, 0x8f620050, 0x26304660, 0x00002021,
268 0xac620018, 0x9602000e, 0x8f850018, 0x3c03c00b, 0x00431025, 0x0e001044,
269 0xaca2001c, 0x8f830018, 0x8f620054, 0xac620000, 0x8f840018, 0x8f620058,
270 0xac820004, 0x8f830018, 0x8f62005c, 0xac620008, 0x8f840018, 0x8f620060,
271 0xac82000c, 0x8f850018, 0x8f620064, 0xaca20010, 0x97630068, 0x9762006a,
272 0x8f840018, 0x00031c00, 0x00431025, 0xac820014, 0x8f830018, 0x00002021,
273 0xac600018, 0x9602000e, 0x8f850018, 0x3c03c00c, 0x00431025, 0x0e001044,
274 0xaca2001c, 0x8f840018, 0x8f630018, 0xac830000, 0x936200c4, 0x30420002,
275 0x10400006, 0x00000000, 0x976200c8, 0x8f830018, 0x3042ffff, 0x0a0005b5,
276 0xac620004, 0x8f820018, 0xac400004, 0x8f830018, 0x8f62006c, 0xac620008,
277 0x8f840018, 0x8f6200dc, 0xac82000c, 0x8f830018, 0xac600010, 0x93620005,
278 0x8f830018, 0x00021600, 0x00531025, 0xac620014, 0x8f850018, 0x3c026000,
279 0x8c434448, 0x24040001, 0x26224660, 0xaca30018, 0x9443000e, 0x8f850018,
280 0x3c02400d, 0x00621825, 0x0e001044, 0xaca3001c, 0x0e000d48, 0x02402021,
281 0x8fbf0020, 0x8fb3001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
282 0x27bd0028, 0x27bdffe0, 0xafb00010, 0x27500100, 0xafbf0018, 0xafb10014,
283 0x9603000c, 0x240200c1, 0x5462001d, 0x8e040000, 0x3c029000, 0x8f440100,
284 0x34420001, 0x3c038000, 0x00821025, 0xaf420020, 0x8f420020, 0x00431024,
285 0x1440fffd, 0x00000000, 0x3c038000, 0x9362007d, 0x34630001, 0x3c058000,
286 0x00831825, 0x34420004, 0xa362007d, 0xaf430020, 0x8f4201f8, 0x00451024,
287 0x1440fffd, 0x24020002, 0x3c031000, 0xaf4401c0, 0xa34201c4, 0xaf4301f8,
288 0x0a000622, 0x8fbf0018, 0x8f65004c, 0x24060001, 0x0e000db5, 0x2407049f,
289 0x3c020800, 0x8c430020, 0x9611000c, 0x1060001d, 0x8e100000, 0x0e001006,
290 0x00000000, 0x8f820018, 0xac500000, 0x8f840018, 0x00111400, 0xac820004,
291 0x8f830018, 0xac600008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010,
292 0x8f840018, 0x240204a2, 0xac820014, 0x8f850018, 0x3c026000, 0x8c434448,
293 0x24040001, 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018, 0x3c024019,
294 0x00621825, 0x0e001044, 0xaca3001c, 0x8fbf0018, 0x8fb10014, 0x8fb00010,
295 0x03e00008, 0x27bd0020, 0x27bdffb0, 0xafb1002c, 0x27510100, 0xafbf004c,
296 0xafbe0048, 0xafb70044, 0xafb60040, 0xafb5003c, 0xafb40038, 0xafb30034,
297 0xafb20030, 0xafb00028, 0x8e350000, 0x9634000c, 0x3c026000, 0x8c434448,
298 0x0000f021, 0xaf630170, 0x8f620040, 0x8e230014, 0x0000b821, 0x00431023,
299 0x044001ec, 0x0000b021, 0x32820010, 0x1040002e, 0x3c026000, 0x9363003f,
300 0x9222000e, 0x10430006, 0x2402000c, 0x9223000f, 0x10620003, 0x24020014,
301 0x14620025, 0x3c026000, 0x32820004, 0x10400007, 0x241e0001, 0x8f620050,
302 0x24420001, 0xaf620050, 0x8f630054, 0x24630001, 0xaf630054, 0x32830102,
303 0x24020002, 0x5462000d, 0x9222000f, 0x8f620040, 0x24420001, 0xaf620040,
304 0x8f630048, 0x8f620040, 0x24630001, 0x54620005, 0x9222000f, 0x8f620048,
305 0x24420001, 0xaf620048, 0x9222000f, 0xa362003f, 0x9223000f, 0x24020012,
306 0x14620007, 0x3c026000, 0x3c030800, 0x8c620074, 0x24420001, 0x0e000f6e,
307 0xac620074, 0x3c026000, 0x8c434448, 0x32820040, 0xaf630174, 0x32830020,
308 0xafa30010, 0x32830080, 0xafa30014, 0x32830001, 0xafa3001c, 0x32830008,
309 0xafa30020, 0x32830100, 0x104000bb, 0xafa30018, 0x8e260010, 0x8f630054,
310 0x24c2ffff, 0x00431023, 0x18400006, 0x00000000, 0x0000000d, 0x00000000,
311 0x24000128, 0x0a0006b2, 0x00009021, 0x8f62004c, 0x00c21023, 0x18400028,
312 0x00009021, 0x93650120, 0x93640121, 0x3c030800, 0x8c62008c, 0x308400ff,
313 0x24420001, 0x30a500ff, 0x00804021, 0x1485000b, 0xac62008c, 0x3c040800,
314 0x8c830090, 0x24630001, 0xac830090, 0x93620122, 0x30420001, 0x00021023,
315 0x30420005, 0x0a0006b2, 0x34520004, 0x27670100, 0x00041080, 0x00e21021,
316 0x8c430000, 0x00c31823, 0x04600004, 0x24820001, 0x30440007, 0x1485fff9,
317 0x00041080, 0x10880007, 0x3c030800, 0xa3640121, 0x8c620094, 0x24120005,
318 0x24420001, 0x0a0006b2, 0xac620094, 0x24120004, 0x32420001, 0x10400020,
319 0x3c020800, 0x8c430020, 0x8e300000, 0x1060001c, 0x8e330010, 0x0e001006,
320 0x00000000, 0x8f820018, 0xac500000, 0x8f840018, 0x24020001, 0xac820004,
321 0x8f830018, 0xac600008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010,
322 0x8f820018, 0xac530014, 0x8f850018, 0x3c026000, 0x8c434448, 0x24040001,
323 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018, 0x3c024010, 0x00621825,
324 0x0e001044, 0xaca3001c, 0x32420004, 0x10400060, 0x00003821, 0x3c029000,
325 0x8e260010, 0x34420001, 0x3c038000, 0x02a21025, 0xa360007c, 0xaf420020,
326 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93620023, 0x30420080,
327 0x10400011, 0x00000000, 0x8f65005c, 0x8f63004c, 0x9764003c, 0x8f620064,
328 0x00a32823, 0x00852821, 0x00a2102b, 0x54400006, 0x3c023fff, 0x93620023,
329 0x3042007f, 0xa3620023, 0xaf660064, 0x3c023fff, 0x0a000702, 0x3442ffff,
330 0x8f62005c, 0x00c21023, 0x04400011, 0x00000000, 0x8f65005c, 0x8f630064,
331 0x9764003c, 0x3c023fff, 0x3442ffff, 0xaf660064, 0x00a32823, 0x00852821,
332 0x0045102b, 0x10400004, 0x00c51021, 0x3c053fff, 0x34a5ffff, 0x00c51021,
333 0xaf62005c, 0x24070001, 0xaf66004c, 0x8f620054, 0x14c20005, 0x00000000,
334 0x93620023, 0x30420040, 0x10400017, 0x24020001, 0x9762006a, 0x00022880,
335 0x50a00001, 0x24050001, 0x97630068, 0x93640081, 0x3c020800, 0x8c46004c,
336 0x00652821, 0x00852804, 0x00c5102b, 0x54400001, 0x00a03021, 0x3c020800,
337 0x8c440050, 0x00c4182b, 0x54600001, 0x00c02021, 0x8f420074, 0x2403fffe,
338 0x00832824, 0x00a21021, 0xaf62000c, 0x3c028000, 0x34420001, 0x02a21025,
339 0xa3600081, 0xaf420020, 0x9363007e, 0x9362007a, 0x10620005, 0x00e0b021,
340 0x0e000f2a, 0x00000000, 0x00403821, 0x00e0b021, 0x8fa20010, 0x10400008,
341 0x00000000, 0x8e220018, 0xaf620018, 0x8e23001c, 0xaf63001c, 0x8e220020,
342 0x24160001, 0xaf620058, 0x13c00036, 0x32820004, 0x10400035, 0x8fa30014,
343 0x93620023, 0x30420040, 0x10400031, 0x3c020800, 0x8c430020, 0x1060001c,
344 0x8e300000, 0x0e001006, 0x00000000, 0x8f820018, 0xac500000, 0x8f830018,
345 0xac600004, 0x8f820018, 0xac400008, 0x8f830018, 0xac60000c, 0x8f820018,
346 0xac400010, 0x8f830018, 0x24020587, 0xac620014, 0x8f850018, 0x3c026000,
347 0x8c434448, 0x24040001, 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018,
348 0x3c024019, 0x00621825, 0x0e001044, 0xaca3001c, 0x3c029000, 0x34420001,
349 0x02a21025, 0xaf420020, 0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd,
350 0x24020001, 0xaf62000c, 0x93630023, 0x3c028000, 0x34420001, 0x02a21025,
351 0x306300bf, 0xa3630023, 0xaf420020, 0x8fa30014, 0x10600012, 0x8fa3001c,
352 0x9362007c, 0x24420001, 0xa362007c, 0x9363007e, 0x9362007a, 0x1462000b,
353 0x8fa3001c, 0x9362007c, 0x3c030800, 0x8c640024, 0x0044102b, 0x14400005,
354 0x8fa3001c, 0x0e000f2a, 0x00000000, 0x02c2b025, 0x8fa3001c, 0x3062ffff,
355 0x10400003, 0x32820200, 0x0a000793, 0x24170004, 0x10400003, 0x00000000,
356 0x24170040, 0x24160001, 0x13c0005d, 0x32820002, 0x1040005c, 0x8fa20020,
357 0x9222000a, 0x30420020, 0x10400033, 0x3c100800, 0x93620023, 0x30420040,
358 0x1040002f, 0x8e020020, 0x1040001e, 0x3c029000, 0x0e001006, 0x00000000,
359 0x8f820018, 0xac550000, 0x8f840018, 0x3c02008d, 0xac820004, 0x8f830018,
360 0xac600008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010, 0x8f840018,
361 0x240205bf, 0xac820014, 0x8f850018, 0x3c026000, 0x8c434448, 0x24040001,
362 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018, 0x3c024019, 0x00621825,
363 0x0e001044, 0xaca3001c, 0x3c029000, 0x34420001, 0x02a21025, 0xaf420020,
364 0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93630023,
365 0x3c028000, 0x34420001, 0x02a21025, 0x306300bf, 0xa3630023, 0xaf420020,
366 0x8e020020, 0x10400023, 0x8fa20020, 0x0e001006, 0x00000000, 0x8f840018,
367 0x8e230000, 0xac830000, 0x9222000a, 0x8f830018, 0x00021600, 0xac620004,
368 0x8f840018, 0x8f620040, 0xac820008, 0x8f850018, 0x8f63004c, 0xaca3000c,
369 0x9362003f, 0x8f840018, 0x304200ff, 0xac820010, 0x8f830018, 0x3c026000,
370 0xac600014, 0x8f850018, 0x8c434448, 0x24040001, 0x3c020800, 0xaca30018,
371 0x9443466e, 0x8f850018, 0x3c02401a, 0x00621825, 0x0e001044, 0xaca3001c,
372 0x8fa20020, 0x1040000e, 0x8fa20018, 0x9222000a, 0xa3620082, 0x56e00005,
373 0x36f70008, 0x8fa30018, 0x10600004, 0x00000000, 0x36f70008, 0x0a000801,
374 0x24160001, 0x0e000de1, 0x02a02021, 0x8fa20018, 0x10400003, 0x00000000,
375 0x36f70010, 0x24160001, 0x12c00019, 0x3c029000, 0x34420001, 0x02a21025,
376 0xaf420020, 0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000,
377 0x3c038000, 0x9362007d, 0x34630001, 0x3c048000, 0x02a31825, 0x02e21025,
378 0xa362007d, 0xaf430020, 0x8f4201f8, 0x00441024, 0x1440fffd, 0x24020002,
379 0x3c031000, 0xaf5501c0, 0xa34201c4, 0xaf4301f8, 0x9363003f, 0x24020012,
380 0x14620004, 0x3c026000, 0x0e000f6e, 0x00000000, 0x3c026000, 0x8c434448,
381 0xaf630178, 0x8fbf004c, 0x8fbe0048, 0x8fb70044, 0x8fb60040, 0x8fb5003c,
382 0x8fb40038, 0x8fb30034, 0x8fb20030, 0x8fb1002c, 0x8fb00028, 0x03e00008,
383 0x27bd0050, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f500180, 0x97420184,
384 0x30420200, 0x14400015, 0x00000000, 0x8f430188, 0x3c02ff00, 0x00621824,
385 0x3c020200, 0x10620031, 0x0043102b, 0x14400007, 0x3c020300, 0x1060000b,
386 0x3c020100, 0x1062000d, 0x00000000, 0x0a0008b4, 0x00000000, 0x10620027,
387 0x3c020400, 0x1062003e, 0x02002021, 0x0a0008b4, 0x00000000, 0x0e000e1e,
388 0x02002021, 0x0a0008b6, 0x8fbf0014, 0x93620005, 0x30420020, 0x1440005e,
389 0x8fbf0014, 0x3c029000, 0x34420001, 0x02021025, 0xaf420020, 0x3c038000,
390 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93620005, 0x3c038000,
391 0x34630001, 0x02031825, 0x34420020, 0xa3620005, 0xaf430020, 0x93620005,
392 0x30420020, 0x14400003, 0x02002021, 0x0000000d, 0x02002021, 0x0e000553,
393 0x24055854, 0x0a0008b6, 0x8fbf0014, 0x93620005, 0x30420001, 0x1040003f,
394 0x3c029000, 0x34420001, 0x02021025, 0xaf420020, 0x3c038000, 0x8f420020,
395 0x00431024, 0x1440fffd, 0x00000000, 0x93620005, 0x3c048000, 0x3c030800,
396 0x304200fe, 0xa3620005, 0x8c620020, 0x34840001, 0x02042025, 0xaf440020,
397 0x1040002d, 0x8fbf0014, 0x0a000894, 0x00000000, 0x00002821, 0x00003021,
398 0x0e000f78, 0x240706a4, 0x3c020800, 0x8c430020, 0x10600023, 0x8fbf0014,
399 0x0e001006, 0x00000000, 0x8f820018, 0xac500000, 0x93630082, 0x9362003f,
400 0x8f840018, 0x00031a00, 0x00431025, 0xac820004, 0x8f830018, 0xac600008,
401 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010, 0x8f820018, 0xac400014,
402 0x8f850018, 0x3c026000, 0x8c434448, 0x24040001, 0x3c020800, 0xaca30018,
403 0x9443466e, 0x8f850018, 0x3c02400a, 0x00621825, 0x0e001044, 0xaca3001c,
404 0x0a0008b6, 0x8fbf0014, 0x0000000d, 0x8fbf0014, 0x8fb00010, 0x03e00008,
405 0x27bd0018, 0x27bdffe8, 0xafbf0010, 0x93420148, 0x2444ffff, 0x2c830005,
406 0x10600047, 0x3c020800, 0x24424598, 0x00041880, 0x00621821, 0x8c640000,
407 0x00800008, 0x00000000, 0x8f430144, 0x8f62000c, 0x14620006, 0x24020001,
408 0xaf62000c, 0x0e000909, 0x00000000, 0x0a000907, 0x8fbf0010, 0x8f62000c,
409 0x0a000900, 0x00000000, 0x97630010, 0x8f420144, 0x14430006, 0x24020001,
410 0xa7620010, 0x0e000eeb, 0x00000000, 0x0a000907, 0x8fbf0010, 0x97620010,
411 0x0a000900, 0x00000000, 0x97630012, 0x8f420144, 0x14430006, 0x24020001,
412 0xa7620012, 0x0e000f06, 0x00000000, 0x0a000907, 0x8fbf0010, 0x97620012,
413 0x0a000900, 0x00000000, 0x97630014, 0x8f420144, 0x14430006, 0x24020001,
414 0xa7620014, 0x0e000f21, 0x00000000, 0x0a000907, 0x8fbf0010, 0x97620014,
415 0x0a000900, 0x00000000, 0x97630016, 0x8f420144, 0x14430006, 0x24020001,
416 0xa7620016, 0x0e000f24, 0x00000000, 0x0a000907, 0x8fbf0010, 0x97620016,
417 0x14400006, 0x8fbf0010, 0x3c030800, 0x8c620070, 0x24420001, 0xac620070,
418 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x27bdffe8, 0xafbf0010, 0x93620081,
419 0x3c030800, 0x8c640048, 0x0044102b, 0x14400028, 0x3c029000, 0x8f460140,
420 0x34420001, 0x3c038000, 0x00c21025, 0xaf420020, 0x8f420020, 0x00431024,
421 0x1440fffd, 0x3c048000, 0x34840001, 0x3c059000, 0x34a50001, 0x3c078000,
422 0x24020012, 0x24030080, 0x00c42025, 0x00c52825, 0xa362003f, 0xa3630082,
423 0xaf440020, 0xaf450020, 0x8f420020, 0x00471024, 0x1440fffd, 0x3c038000,
424 0x9362007d, 0x34630001, 0x3c048000, 0x00c31825, 0x34420020, 0xa362007d,
425 0xaf430020, 0x8f4201f8, 0x00441024, 0x1440fffd, 0x24020002, 0x3c031000,
426 0x0a00096d, 0xaf4601c0, 0x93620081, 0x24420001, 0x0e000f2a, 0xa3620081,
427 0x9763006a, 0x00032880, 0x14a00002, 0x00403821, 0x24050001, 0x97630068,
428 0x93640081, 0x3c020800, 0x8c46004c, 0x00652821, 0x00852804, 0x00c5102b,
429 0x54400001, 0x00a03021, 0x3c020800, 0x8c440050, 0x00c4182b, 0x54600001,
430 0x00c02021, 0x8f420074, 0x2403fffe, 0x00832824, 0x00a21021, 0xaf62000c,
431 0x10e0001a, 0x3c029000, 0x8f440140, 0x34420001, 0x3c038000, 0x00821025,
432 0xaf420020, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x3c038000,
433 0x9362007d, 0x34630001, 0x3c058000, 0x00831825, 0x34420004, 0xa362007d,
434 0xaf430020, 0x8f4201f8, 0x00451024, 0x1440fffd, 0x24020002, 0x3c031000,
435 0xaf4401c0, 0xa34201c4, 0xaf4301f8, 0x8fbf0010, 0x03e00008, 0x27bd0018,
436 0x27bdffd8, 0xafb3001c, 0x27530100, 0xafbf0024, 0xafb40020, 0xafb20018,
437 0xafb10014, 0xafb00010, 0x96620008, 0x3c140800, 0x8f520100, 0x30420001,
438 0x104000cf, 0x00000000, 0x8e700018, 0x8f630054, 0x2602ffff, 0x00431023,
439 0x18400006, 0x00000000, 0x0000000d, 0x00000000, 0x24000128, 0x0a0009b6,
440 0x00008821, 0x8f62004c, 0x02021023, 0x18400028, 0x00008821, 0x93650120,
441 0x93640121, 0x3c030800, 0x8c62008c, 0x308400ff, 0x24420001, 0x30a500ff,
442 0x00803821, 0x1485000b, 0xac62008c, 0x3c040800, 0x8c830090, 0x24630001,
443 0xac830090, 0x93620122, 0x30420001, 0x00021023, 0x30420005, 0x0a0009b6,
444 0x34510004, 0x27660100, 0x00041080, 0x00c21021, 0x8c430000, 0x02031823,
445 0x04600004, 0x24820001, 0x30440007, 0x1485fff9, 0x00041080, 0x10870007,
446 0x3c030800, 0xa3640121, 0x8c620094, 0x24110005, 0x24420001, 0x0a0009b6,
447 0xac620094, 0x24110004, 0x32220001, 0x1040001e, 0x8e820020, 0x1040001d,
448 0x32220004, 0x0e001006, 0x00000000, 0x8f820018, 0xac520000, 0x8f840018,
449 0x24020001, 0xac820004, 0x8f830018, 0xac600008, 0x8f820018, 0xac40000c,
450 0x8f830018, 0xac600010, 0x8f820018, 0xac500014, 0x8f850018, 0x3c026000,
451 0x8c434448, 0x24040001, 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018,
452 0x3c024010, 0x00621825, 0x0e001044, 0xaca3001c, 0x32220004, 0x10400076,
453 0x00003821, 0x3c029000, 0x34420001, 0x3c038000, 0x02421025, 0xa360007c,
454 0xaf420020, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93620023,
455 0x30420080, 0x10400011, 0x00000000, 0x8f65005c, 0x8f63004c, 0x9764003c,
456 0x8f620064, 0x00a32823, 0x00852821, 0x00a2102b, 0x54400006, 0x3c023fff,
457 0x93620023, 0x3042007f, 0xa3620023, 0xaf700064, 0x3c023fff, 0x0a000a03,
458 0x3442ffff, 0x8f62005c, 0x02021023, 0x04400011, 0x00000000, 0x8f65005c,
459 0x8f630064, 0x9764003c, 0x3c023fff, 0x3442ffff, 0xaf700064, 0x00a32823,
460 0x00852821, 0x0045102b, 0x10400004, 0x02051021, 0x3c053fff, 0x34a5ffff,
461 0x02051021, 0xaf62005c, 0x24070001, 0xaf70004c, 0x8f620054, 0x16020005,
462 0x00000000, 0x93620023, 0x30420040, 0x10400017, 0x24020001, 0x9762006a,
463 0x00022880, 0x50a00001, 0x24050001, 0x97630068, 0x93640081, 0x3c020800,
464 0x8c46004c, 0x00652821, 0x00852804, 0x00c5102b, 0x54400001, 0x00a03021,
465 0x3c020800, 0x8c440050, 0x00c4182b, 0x54600001, 0x00c02021, 0x8f420074,
466 0x2403fffe, 0x00832824, 0x00a21021, 0xaf62000c, 0x3c028000, 0x34420001,
467 0x02421025, 0xa3600081, 0xaf420020, 0x9363007e, 0x9362007a, 0x10620004,
468 0x00000000, 0x0e000f2a, 0x00000000, 0x00403821, 0x10e00017, 0x3c029000,
469 0x34420001, 0x02421025, 0xaf420020, 0x3c038000, 0x8f420020, 0x00431024,
470 0x1440fffd, 0x3c028000, 0x9363007d, 0x34420001, 0x3c048000, 0x02421025,
471 0xa363007d, 0xaf420020, 0x8f4201f8, 0x00441024, 0x1440fffd, 0x24020002,
472 0x3c031000, 0xaf5201c0, 0xa34201c4, 0xaf4301f8, 0x9342010b, 0x8e830020,
473 0x27500100, 0x38420006, 0x10600029, 0x2c510001, 0x0e001006, 0x00000000,
474 0x8f830018, 0x8e020000, 0xac620000, 0x8f840018, 0x96020008, 0xac820004,
475 0x8f830018, 0x8e020014, 0xac620008, 0x8f850018, 0x3c026000, 0x8c434448,
476 0xaca3000c, 0x8f840018, 0x96020012, 0xac820010, 0x8f850018, 0x8e030020,
477 0xaca30014, 0x9602000c, 0x9603000e, 0x8f840018, 0x00021400, 0x00431025,
478 0xac820018, 0x12200005, 0x3c020800, 0x9443466e, 0x8f840018, 0x0a000a78,
479 0x3c024013, 0x9443466e, 0x8f840018, 0x3c024014, 0x00621825, 0xac83001c,
480 0x0e001044, 0x24040001, 0x8e630014, 0x8f620040, 0x14430003, 0x00431023,
481 0x0a000a83, 0x00001021, 0x28420001, 0x10400034, 0x00000000, 0x8f620040,
482 0xaf630040, 0x9362003e, 0x30420001, 0x1440000b, 0x3c029000, 0x93620022,
483 0x24420001, 0xa3620022, 0x93630022, 0x3c020800, 0x8c440098, 0x0064182b,
484 0x1460001e, 0x3c020800, 0x3c029000, 0x34420001, 0x02421025, 0xaf420020,
485 0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x3c038000,
486 0x9362007d, 0x34630001, 0x3c048000, 0x02431825, 0x34420001, 0xa362007d,
487 0xaf430020, 0x8f4201f8, 0x00441024, 0x1440fffd, 0x24020002, 0x3c031000,
488 0xaf5201c0, 0xa34201c4, 0x24020001, 0xaf4301f8, 0xa7620012, 0x0a000ab6,
489 0xa3600022, 0x9743007a, 0x9444002a, 0x00641821, 0x3063fffe, 0xa7630012,
490 0x0e000b68, 0x00000000, 0x97420108, 0x8fbf0024, 0x8fb40020, 0x8fb3001c,
491 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x00021042, 0x30420001, 0x03e00008,
492 0x27bd0028, 0x27bdffe0, 0xafb20018, 0x3c120800, 0x8e420020, 0xafb00010,
493 0x27500100, 0xafbf001c, 0x10400046, 0xafb10014, 0x0e001006, 0x00000000,
494 0x8f840018, 0x8e020000, 0xac820000, 0x936300b1, 0x936200c5, 0x8f850018,
495 0x00031e00, 0x00021400, 0x34420100, 0x00621825, 0xaca30004, 0x8f840018,
496 0x8e02001c, 0xac820008, 0x8f830018, 0x8f620048, 0xac62000c, 0x8f840018,
497 0x96020012, 0xac820010, 0x8f830018, 0x8f620040, 0x24040001, 0xac620014,
498 0x8f850018, 0x3c026000, 0x8c434448, 0x3c020800, 0x24514660, 0xaca30018,
499 0x9623000e, 0x8f850018, 0x3c024016, 0x00621825, 0x0e001044, 0xaca3001c,
500 0x96030008, 0x30630010, 0x1060001c, 0x8e420020, 0x1040001a, 0x8e100000,
501 0x0e001006, 0x00000000, 0x8f820018, 0xac500000, 0x8f830018, 0xac600004,
502 0x8f820018, 0xac400008, 0x8f830018, 0xac60000c, 0x8f820018, 0xac400010,
503 0x8f830018, 0xac600014, 0x8f850018, 0x3c036000, 0x8c634448, 0x24040001,
504 0xaca30018, 0x9622000e, 0x8f850018, 0x3c034015, 0x00431025, 0x0e001044,
505 0xaca2001c, 0x00001021, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010,
506 0x03e00008, 0x27bd0020, 0x27bdffe0, 0xafb20018, 0x3c120800, 0x8e420020,
507 0xafb00010, 0x27500100, 0xafbf001c, 0x10400041, 0xafb10014, 0x0e001006,
508 0x00000000, 0x8f830018, 0x8e020000, 0xac620000, 0x8f840018, 0x24020100,
509 0xac820004, 0x8f830018, 0x8e02001c, 0xac620008, 0x8f840018, 0x8e020018,
510 0xac82000c, 0x8f830018, 0x96020012, 0xac620010, 0x8f840018, 0x96020008,
511 0xac820014, 0x8f850018, 0x3c026000, 0x8c434448, 0x24040001, 0x3c020800,
512 0x24514660, 0xaca30018, 0x9623000e, 0x8f850018, 0x3c024017, 0x00621825,
513 0x0e001044, 0xaca3001c, 0x96030008, 0x30630010, 0x1060001c, 0x8e420020,
514 0x1040001a, 0x8e100000, 0x0e001006, 0x00000000, 0x8f820018, 0xac500000,
515 0x8f830018, 0xac600004, 0x8f820018, 0xac400008, 0x8f830018, 0xac60000c,
516 0x8f820018, 0xac400010, 0x8f830018, 0xac600014, 0x8f850018, 0x3c036000,
517 0x8c634448, 0x24040001, 0xaca30018, 0x9622000e, 0x8f850018, 0x3c034015,
518 0x00431025, 0x0e001044, 0xaca2001c, 0x00001021, 0x8fbf001c, 0x8fb20018,
519 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x27bdffe8, 0xafbf0010,
520 0x936200c4, 0x30420002, 0x10400019, 0x00000000, 0x936200c5, 0x936300b1,
521 0x00431023, 0x304400ff, 0x30830080, 0x10600004, 0x00000000, 0x0000000d,
522 0x00000000, 0x24000a6a, 0x93620004, 0x00441023, 0x304400ff, 0x30830080,
523 0x10600004, 0x2482ffff, 0x8f650024, 0x0a000b82, 0x00000000, 0x00022b00,
524 0x8f620024, 0x0045102b, 0x10400002, 0x00000000, 0x8f650024, 0x8f620048,
525 0x8f630040, 0x00431823, 0x0065202b, 0x10800004, 0x00000000, 0x8f620040,
526 0x00451021, 0xaf620048, 0x9762003c, 0x0062102b, 0x10400041, 0x8fbf0010,
527 0x10a0003f, 0x3c029000, 0x34420001, 0x3c040800, 0x8c830080, 0x8f450100,
528 0x3c068000, 0x24630001, 0x00a21025, 0xac830080, 0xaf420020, 0x8f420020,
529 0x00461024, 0x1440fffd, 0x3c038000, 0x9362007d, 0x34630001, 0x3c048000,
530 0x00a31825, 0x34420004, 0xa362007d, 0xaf430020, 0x8f4201f8, 0x00441024,
531 0x1440fffd, 0x24020002, 0x3c030800, 0xaf4501c0, 0xa34201c4, 0x8c640020,
532 0x3c021000, 0xaf4201f8, 0x1080001f, 0x8fbf0010, 0x0e001006, 0x00000000,
533 0x8f830018, 0x8f420100, 0xac620000, 0x8f840018, 0x8f620040, 0xac820004,
534 0x8f850018, 0x8f620048, 0xaca20008, 0x8f830018, 0xac60000c, 0x8f820018,
535 0xac400010, 0x8f830018, 0x3c026000, 0xac600014, 0x8f840018, 0x8c434448,
536 0x3c020800, 0xac830018, 0x9443466e, 0x8f840018, 0x3c0240c2, 0x00621825,
537 0xac83001c, 0x0e001044, 0x24040001, 0x8fbf0010, 0x03e00008, 0x27bd0018,
538 0x3c020800, 0x24423958, 0xaf82000c, 0x03e00008, 0x00000000, 0x27bdffe8,
539 0xafb00010, 0x27500100, 0xafbf0014, 0x8e02001c, 0x14400003, 0x3c020800,
540 0x0000000d, 0x3c020800, 0x8c430020, 0x10600026, 0x00001021, 0x0e001006,
541 0x00000000, 0x8f830018, 0x8e020000, 0xac620000, 0x8f840018, 0x8e02001c,
542 0xac820004, 0x8f830018, 0xac600008, 0x8f840018, 0x8e020018, 0xac82000c,
543 0x8f850018, 0x96020012, 0xaca20010, 0x8f830018, 0x3c106000, 0xac600014,
544 0x8f840018, 0x8e024448, 0x3c030800, 0xac820018, 0x9462466e, 0x8f840018,
545 0x3c034012, 0x00431025, 0xac82001c, 0x0e001044, 0x24040001, 0x8e036800,
546 0x00001021, 0x3c040001, 0x00641825, 0xae036800, 0x0a000c0d, 0x8fbf0014,
547 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c020800, 0x97430078,
548 0x9444002e, 0x00001021, 0x00641821, 0x3063fffe, 0x03e00008, 0xa7630010,
549 0x27450100, 0x8f640048, 0x8ca30018, 0x00641023, 0x18400021, 0x00000000,
550 0xaf630048, 0x8f620040, 0x9763003c, 0x00821023, 0x0043102a, 0x1040001a,
551 0x3c029000, 0x8ca40000, 0x34420001, 0x3c038000, 0x00821025, 0xaf420020,
552 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x3c038000, 0x9362007d,
553 0x34630001, 0x3c058000, 0x00831825, 0x34420004, 0xa362007d, 0xaf430020,
554 0x8f4201f8, 0x00451024, 0x1440fffd, 0x24020002, 0x3c031000, 0xaf4401c0,
555 0xa34201c4, 0xaf4301f8, 0x03e00008, 0x00001021, 0x8f420100, 0x34420001,
556 0xaf4200a4, 0x03e00008, 0x00001021, 0x27bdffe0, 0xafbf0018, 0xafb10014,
557 0xafb00010, 0x9362007e, 0x30d000ff, 0x16020029, 0x00808821, 0x93620080,
558 0x16020026, 0x00000000, 0x9362007f, 0x16020023, 0x00000000, 0x9362007a,
559 0x16020004, 0x00000000, 0x0000000d, 0x00000000, 0x24000771, 0x0e000f49,
560 0x00000000, 0x3c039000, 0x34630001, 0x3c048000, 0x02231825, 0xa370007a,
561 0xaf430020, 0x8f420020, 0x00441024, 0x1440fffd, 0x3c028000, 0x9363007d,
562 0x34420001, 0x3c048000, 0x02221025, 0xa363007d, 0xaf420020, 0x8f4201f8,
563 0x00441024, 0x1440fffd, 0x24020002, 0x3c031000, 0xaf5101c0, 0xa34201c4,
564 0xaf4301f8, 0x0a000c79, 0x8fbf0018, 0x0000000d, 0x00000000, 0x24000781,
565 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c020800,
566 0x8c430020, 0x27bdffe8, 0xafb00010, 0x27500100, 0x10600024, 0xafbf0014,
567 0x0e001006, 0x00000000, 0x8f830018, 0x8e020000, 0xac620000, 0x8f840018,
568 0x8e020004, 0xac820004, 0x8f830018, 0x8e020018, 0xac620008, 0x8f840018,
569 0x8e03001c, 0xac83000c, 0x9602000c, 0x9203000a, 0x8f840018, 0x00021400,
570 0x00431025, 0xac820010, 0x8f830018, 0x3c026000, 0xac600014, 0x8f840018,
571 0x8c434448, 0xac830018, 0x96020008, 0x3c030800, 0x9464466e, 0x8f850018,
572 0x00021400, 0x00441025, 0x24040001, 0x0e001044, 0xaca2001c, 0x8fbf0014,
573 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c020800, 0x8c430020, 0x27bdffe8,
574 0xafb00010, 0x27500100, 0x10600020, 0xafbf0014, 0x0e001006, 0x00000000,
575 0x8f820018, 0xac400000, 0x8f830018, 0xac600004, 0x8f820018, 0xac400008,
576 0x8f830018, 0xac60000c, 0x9602000c, 0x9603000e, 0x8f840018, 0x00021400,
577 0x00431025, 0xac820010, 0x8f830018, 0x3c026000, 0xac600014, 0x8f840018,
578 0x8c434448, 0xac830018, 0x96020008, 0x3c030800, 0x9464466e, 0x8f850018,
579 0x00021400, 0x00441025, 0x24040001, 0x0e001044, 0xaca2001c, 0x8fbf0014,
580 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdffe8, 0xafb00010, 0x27500100,
581 0xafbf0014, 0x9602000c, 0x10400024, 0x00802821, 0x3c020800, 0x8c430020,
582 0x1060003a, 0x8fbf0014, 0x0e001006, 0x00000000, 0x8f840018, 0x8e030000,
583 0xac830000, 0x9602000c, 0x8f840018, 0x00021400, 0xac820004, 0x8f830018,
584 0xac600008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010, 0x8f820018,
585 0xac400014, 0x8f850018, 0x3c026000, 0x8c434448, 0x24040001, 0x3c020800,
586 0xaca30018, 0x9443466e, 0x8f850018, 0x3c02400b, 0x00621825, 0x0e001044,
587 0xaca3001c, 0x0a000d19, 0x8fbf0014, 0x93620005, 0x30420010, 0x14400015,
588 0x3c029000, 0x34420001, 0x00a21025, 0xaf420020, 0x3c038000, 0x8f420020,
589 0x00431024, 0x1440fffd, 0x00000000, 0x3c038000, 0x93620005, 0x34630001,
590 0x00a02021, 0x00a31825, 0x24055852, 0x34420010, 0xa3620005, 0x0e000553,
591 0xaf430020, 0x0a000d19, 0x8fbf0014, 0x0000000d, 0x8fbf0014, 0x8fb00010,
592 0x03e00008, 0x27bd0018, 0x3c020800, 0x8c430020, 0x27bdffe8, 0xafb00010,
593 0x27500100, 0x10600022, 0xafbf0014, 0x0e001006, 0x00000000, 0x8f840018,
594 0x8e020004, 0xac820000, 0x9603000c, 0x9762002c, 0x8f840018, 0x00031c00,
595 0x00431025, 0xac820004, 0x8f830018, 0xac600008, 0x8f820018, 0xac40000c,
596 0x8f830018, 0xac600010, 0x8f820018, 0xac400014, 0x8f850018, 0x3c026000,
597 0x8c434448, 0x24040001, 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018,
598 0x3c02400e, 0x00621825, 0x0e001044, 0xaca3001c, 0x0e000d48, 0x8e040000,
599 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c038000, 0x8f420278,
600 0x00431024, 0x1440fffd, 0x24020002, 0x3c031000, 0xaf440240, 0xa3420244,
601 0x03e00008, 0xaf430278, 0x3c020800, 0x8c430020, 0x27bdffe0, 0xafb10014,
602 0x00808821, 0xafb20018, 0x00c09021, 0xafb00010, 0x30b0ffff, 0x1060001c,
603 0xafbf001c, 0x0e001006, 0x00000000, 0x8f820018, 0xac510000, 0x8f840018,
604 0x00101400, 0xac820004, 0x8f830018, 0xac600008, 0x8f820018, 0xac40000c,
605 0x8f830018, 0xac600010, 0x8f820018, 0xac520014, 0x8f840018, 0x3c026000,
606 0x8c434448, 0x3c020800, 0xac830018, 0x9443466e, 0x8f840018, 0x3c024019,
607 0x00621825, 0xac83001c, 0x0e001044, 0x24040001, 0x8fbf001c, 0x8fb20018,
608 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x27bdffe8, 0x27450100,
609 0xafbf0010, 0x94a3000c, 0x240200c1, 0x14620029, 0x00803021, 0x3c029000,
610 0x34420001, 0x00c21025, 0xaf420020, 0x3c038000, 0x8f420020, 0x00431024,
611 0x1440fffd, 0x3c028000, 0x34420001, 0x3c049000, 0x34840001, 0x3c058000,
612 0x24030012, 0x00c21025, 0x00c42025, 0xa363003f, 0xaf420020, 0xaf440020,
613 0x8f420020, 0x00451024, 0x1440fffd, 0x3c038000, 0x9362007d, 0x34630001,
614 0x3c048000, 0x00c31825, 0x34420020, 0xa362007d, 0xaf430020, 0x8f4201f8,
615 0x00441024, 0x1440fffd, 0x24020002, 0x3c031000, 0xaf4601c0, 0xa34201c4,
616 0xaf4301f8, 0x0a000db3, 0x8fbf0010, 0x00c02021, 0x94a5000c, 0x24060001,
617 0x0e000f78, 0x240706d8, 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x3c020800,
618 0x8c430020, 0x27bdffe0, 0xafb00010, 0x00808021, 0xafb20018, 0x00a09021,
619 0xafb10014, 0x30d100ff, 0x1060001c, 0xafbf001c, 0x0e001006, 0x00000000,
620 0x8f820018, 0xac500000, 0x8f840018, 0x24020001, 0xac820004, 0x8f830018,
621 0xac600008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010, 0x8f820018,
622 0xac520014, 0x8f840018, 0x3c026000, 0x8c434448, 0x3c020800, 0xac830018,
623 0x9443466e, 0x8f840018, 0x3c024010, 0x00621825, 0xac83001c, 0x0e001044,
624 0x02202021, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
625 0x27bd0020, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x93620005, 0x30420001,
626 0x10400033, 0x00808021, 0x3c029000, 0x34420001, 0x02021025, 0xaf420020,
627 0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93620005,
628 0x3c048000, 0x3c030800, 0x304200fe, 0xa3620005, 0x8c620020, 0x34840001,
629 0x02042025, 0xaf440020, 0x10400020, 0x8fbf0014, 0x0e001006, 0x00000000,
630 0x8f820018, 0xac500000, 0x93630082, 0x9362003f, 0x8f840018, 0x00031a00,
631 0x00431025, 0xac820004, 0x8f830018, 0xac600008, 0x8f820018, 0xac40000c,
632 0x8f830018, 0xac600010, 0x8f820018, 0xac400014, 0x8f840018, 0x3c026000,
633 0x8c434448, 0x3c020800, 0xac830018, 0x9443466e, 0x8f840018, 0x3c02400a,
634 0x00621825, 0xac83001c, 0x0e001044, 0x24040001, 0x8fbf0014, 0x8fb00010,
635 0x03e00008, 0x27bd0018, 0x27bdffe8, 0xafbf0010, 0x8f420188, 0x00803021,
636 0x9364003f, 0x24030012, 0x00021402, 0x1483001c, 0x304500ff, 0x3c029000,
637 0x34420001, 0x3c038000, 0x00c21025, 0xa3650080, 0xa365007a, 0xaf420020,
638 0x8f420020, 0x00431024, 0x1440fffd, 0x3c028000, 0x9363007d, 0x34420001,
639 0x3c048000, 0x00c21025, 0xa363007d, 0xaf420020, 0x8f4201f8, 0x00441024,
640 0x1440fffd, 0x24020002, 0x3c031000, 0xaf4601c0, 0xa34201c4, 0xaf4301f8,
641 0x0a000e54, 0x8fbf0010, 0x9362007e, 0x1445000e, 0x00000000, 0x93620080,
642 0x1045000b, 0x00000000, 0xa3650080, 0x8f820000, 0x93660080, 0x8f440180,
643 0x8f65004c, 0x8c430000, 0x0060f809, 0x00000000, 0x0a000e54, 0x8fbf0010,
644 0xa3650080, 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x3c020800, 0x8c430020,
645 0x27bdffe0, 0xafb10014, 0x00808821, 0xafb20018, 0x00a09021, 0xafb00010,
646 0x30d000ff, 0x1060002f, 0xafbf001c, 0x0e001006, 0x00000000, 0x8f820018,
647 0xac510000, 0x8f830018, 0xac700004, 0x8f820018, 0xac520008, 0x8f830018,
648 0xac60000c, 0x8f820018, 0xac400010, 0x9763006a, 0x00032880, 0x50a00001,
649 0x24050001, 0x97630068, 0x93640081, 0x3c020800, 0x8c46004c, 0x00652821,
650 0x00852804, 0x00c5102b, 0x54400001, 0x00a03021, 0x3c020800, 0x8c440050,
651 0x00c4182b, 0x54600001, 0x00c02021, 0x8f830018, 0x2402fffe, 0x00822824,
652 0x3c026000, 0xac650014, 0x8f840018, 0x8c434448, 0x3c020800, 0xac830018,
653 0x9443466e, 0x8f840018, 0x3c024011, 0x00621825, 0xac83001c, 0x0e001044,
654 0x24040001, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
655 0x27bd0020, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f440100, 0x27500100,
656 0x8f650050, 0x0e000c45, 0x9206001b, 0x3c020800, 0x8c430020, 0x1060001d,
657 0x8e100018, 0x0e001006, 0x00000000, 0x8f840018, 0x8f420100, 0xac820000,
658 0x8f830018, 0xac700004, 0x8f840018, 0x8f620050, 0xac820008, 0x8f830018,
659 0xac60000c, 0x8f820018, 0xac400010, 0x8f830018, 0x3c026000, 0xac600014,
660 0x8f850018, 0x8c434448, 0x24040001, 0x3c020800, 0xaca30018, 0x9443466e,
661 0x8f850018, 0x3c02401c, 0x00621825, 0x0e001044, 0xaca3001c, 0x8fbf0014,
662 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c029000, 0x8f460140, 0x34420001,
663 0x3c038000, 0x00c21025, 0xaf420020, 0x8f420020, 0x00431024, 0x1440fffd,
664 0x3c048000, 0x34840001, 0x3c059000, 0x34a50001, 0x3c078000, 0x24020012,
665 0x24030080, 0x00c42025, 0x00c52825, 0xa362003f, 0xa3630082, 0xaf440020,
666 0xaf450020, 0x8f420020, 0x00471024, 0x1440fffd, 0x3c038000, 0x9362007d,
667 0x34630001, 0x3c048000, 0x00c31825, 0x34420020, 0xa362007d, 0xaf430020,
668 0x8f4201f8, 0x00441024, 0x1440fffd, 0x24020002, 0x3c031000, 0xaf4601c0,
669 0xa34201c4, 0x03e00008, 0xaf4301f8, 0x8f430238, 0x3c020800, 0x04610013,
670 0x8c44009c, 0x2406fffe, 0x3c050800, 0x3c038000, 0x2484ffff, 0x14800009,
671 0x00000000, 0x97420078, 0x8ca3007c, 0x24420001, 0x00461024, 0x24630001,
672 0xa7620010, 0x03e00008, 0xaca3007c, 0x8f420238, 0x00431024, 0x1440fff3,
673 0x2484ffff, 0x8f420140, 0x3c031000, 0xaf420200, 0x03e00008, 0xaf430238,
674 0x3c029000, 0x8f440140, 0x34420001, 0x3c038000, 0x00821025, 0xaf420020,
675 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x3c038000, 0x9362007d,
676 0x34630001, 0x3c058000, 0x00831825, 0x34420001, 0xa362007d, 0xaf430020,
677 0x8f4201f8, 0x00451024, 0x1440fffd, 0x24020002, 0x3c031000, 0xaf4401c0,
678 0xa34201c4, 0x03e00008, 0xaf4301f8, 0x0000000d, 0x03e00008, 0x00000000,
679 0x0000000d, 0x03e00008, 0x00000000, 0x24020001, 0x03e00008, 0xa7620010,
680 0x9362003f, 0x304400ff, 0x3883000e, 0x2c630001, 0x38820010, 0x2c420001,
681 0x00621825, 0x14600003, 0x24020012, 0x14820003, 0x00000000, 0x03e00008,
682 0x00001021, 0x9363007e, 0x9362007a, 0x14620006, 0x00000000, 0x9363007e,
683 0x24020001, 0x24630001, 0x03e00008, 0xa363007e, 0x9363007e, 0x93620080,
684 0x14620004, 0x24020001, 0xa362000b, 0x03e00008, 0x24020001, 0x03e00008,
685 0x00001021, 0x9362000b, 0x10400021, 0x00001021, 0xa360000b, 0x9362003f,
686 0x304400ff, 0x3883000e, 0x2c630001, 0x38820010, 0x2c420001, 0x00621825,
687 0x14600015, 0x00001821, 0x24020012, 0x10820012, 0x00000000, 0x9363007e,
688 0x9362007a, 0x14620007, 0x00000000, 0x9362007e, 0x24030001, 0x24420001,
689 0xa362007e, 0x03e00008, 0x00601021, 0x9363007e, 0x93620080, 0x14620004,
690 0x00001821, 0x24020001, 0xa362000b, 0x24030001, 0x03e00008, 0x00601021,
691 0x03e00008, 0x00000000, 0x24040001, 0xaf64000c, 0x8f6300dc, 0x8f6200cc,
692 0x50620001, 0xa7640010, 0xa7640012, 0xa7640014, 0x03e00008, 0xa7640016,
693 0x27bdffd8, 0xafb00010, 0x00808021, 0xafb3001c, 0x00c09821, 0xafbf0020,
694 0xafb20018, 0xafb10014, 0x93620023, 0x00e09021, 0x30420040, 0x10400020,
695 0x30b1ffff, 0x3c020800, 0x8c430020, 0x1060001c, 0x00000000, 0x0e001006,
696 0x00000000, 0x8f820018, 0xac500000, 0x8f840018, 0x3c02008d, 0xac820004,
697 0x8f830018, 0xac600008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010,
698 0x8f820018, 0xac520014, 0x8f850018, 0x3c026000, 0x8c434448, 0x24040001,
699 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018, 0x3c024019, 0x00621825,
700 0x0e001044, 0xaca3001c, 0x93620023, 0x30420020, 0x14400003, 0x3c020800,
701 0x52600020, 0x3c029000, 0x8c430020, 0x1060001d, 0x3c029000, 0x0e001006,
702 0x00000000, 0x8f820018, 0xac500000, 0x8f840018, 0x00111400, 0xac820004,
703 0x8f830018, 0xac720008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010,
704 0x8f820018, 0xac400014, 0x8f850018, 0x3c026000, 0x8c434448, 0x24040001,
705 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018, 0x3c02401b, 0x00621825,
706 0x0e001044, 0xaca3001c, 0x3c029000, 0x34420001, 0x02021025, 0xaf420020,
707 0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93630023,
708 0x3c028000, 0x34420001, 0x02021025, 0x8fbf0020, 0x8fb3001c, 0x8fb20018,
709 0x8fb10014, 0x8fb00010, 0x3063009f, 0xa3630023, 0xaf420020, 0x03e00008,
710 0x27bd0028, 0x3c020800, 0x8c430020, 0x27bdffe8, 0xafb00010, 0x27500100,
711 0x1060001d, 0xafbf0014, 0x0e001006, 0x00000000, 0x8f830018, 0x8e020004,
712 0xac620000, 0x8f840018, 0x8e020018, 0xac820004, 0x8f850018, 0x8e020000,
713 0xaca20008, 0x8f830018, 0xac60000c, 0x8f820018, 0xac400010, 0x8f830018,
714 0xac600014, 0x8f820018, 0xac400018, 0x96030008, 0x3c020800, 0x9444466e,
715 0x8f850018, 0x00031c00, 0x00641825, 0x24040001, 0x0e001044, 0xaca3001c,
716 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c060800, 0x24c54660,
717 0x3c02000a, 0x03421821, 0x94640006, 0x94a2000a, 0x00441023, 0x00021400,
718 0x00021c03, 0x04610006, 0xa4a40006, 0x0000000d, 0x00000000, 0x2400005a,
719 0x0a00101b, 0x24020001, 0x8f820014, 0x0062102b, 0x14400002, 0x00001021,
720 0x24020001, 0x304200ff, 0x1040001c, 0x274a0400, 0x3c07000a, 0x3c020800,
721 0x24454660, 0x94a9000a, 0x8f880014, 0x03471021, 0x94430006, 0x00402021,
722 0xa4a30006, 0x94820006, 0xa4a20006, 0x01221023, 0x00021400, 0x00021403,
723 0x04410006, 0x0048102b, 0x0000000d, 0x00000000, 0x2400005a, 0x0a001036,
724 0x24020001, 0x14400002, 0x00001021, 0x24020001, 0x304200ff, 0x1440ffec,
725 0x03471021, 0x24c44660, 0x8c820010, 0xaf420038, 0x8c830014, 0x3c020005,
726 0xaf43003c, 0xaf420030, 0xaf800010, 0xaf8a0018, 0x03e00008, 0x00000000,
727 0x27bdffe0, 0x8f820010, 0x8f850018, 0x3c070800, 0x24e84660, 0xafbf001c,
728 0xafb20018, 0xafb10014, 0xafb00010, 0x9503000a, 0x8d060014, 0x00009021,
729 0x309000ff, 0x00e08821, 0x24420001, 0x24a50020, 0x24630001, 0xaf820010,
730 0xaf850018, 0xa503000a, 0x24c30020, 0x3c028000, 0x04c10007, 0xad030014,
731 0x00621024, 0x14400005, 0x26224660, 0x8d020010, 0x24420001, 0xad020010,
732 0x26224660, 0x9444000a, 0x94450018, 0x0010102b, 0x00a41826, 0x2c630001,
733 0x00621825, 0x1060001c, 0x3c030006, 0x8f820010, 0x24120001, 0x00021140,
734 0x00431025, 0xaf420030, 0x00000000, 0x00000000, 0x00000000, 0x27450400,
735 0x8f420000, 0x30420010, 0x1040fffd, 0x26224660, 0x9444000a, 0x94430018,
736 0xaf800010, 0xaf850018, 0x14830012, 0x26274660, 0x0e0010d2, 0x00000000,
737 0x1600000e, 0x26274660, 0x0e001006, 0x00000000, 0x0a00108f, 0x26274660,
738 0x00041c00, 0x00031c03, 0x00051400, 0x00021403, 0x00621823, 0x18600002,
739 0x3c026000, 0xac400808, 0x26274660, 0x94e2000e, 0x94e3000c, 0x24420001,
740 0xa4e2000e, 0x3042ffff, 0x50430001, 0xa4e0000e, 0x12000005, 0x3c02000a,
741 0x94e2000a, 0xa74200a2, 0x0a0010cc, 0x02401021, 0x03421821, 0x94640006,
742 0x94e2000a, 0x00441023, 0x00021400, 0x00021c03, 0x04610006, 0xa4e40006,
743 0x0000000d, 0x00000000, 0x2400005a, 0x0a0010ae, 0x24020001, 0x8f820014,
744 0x0062102b, 0x14400002, 0x00001021, 0x24020001, 0x304200ff, 0x1040001b,
745 0x3c020800, 0x3c06000a, 0x24454660, 0x94a8000a, 0x8f870014, 0x03461021,
746 0x94430006, 0x00402021, 0xa4a30006, 0x94820006, 0xa4a20006, 0x01021023,
747 0x00021400, 0x00021403, 0x04410006, 0x0047102b, 0x0000000d, 0x00000000,
748 0x2400005a, 0x0a0010c8, 0x24020001, 0x14400002, 0x00001021, 0x24020001,
749 0x304200ff, 0x1440ffec, 0x03461021, 0x02401021, 0x8fbf001c, 0x8fb20018,
750 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c020800, 0x24454660,
751 0x94a3001a, 0x8ca40024, 0x00403021, 0x000318c0, 0x00832021, 0xaf44003c,
752 0x8ca20020, 0xaf420038, 0x3c020050, 0x34420008, 0xaf420030, 0x00000000,
753 0x00000000, 0x00000000, 0x8f420000, 0x30420020, 0x1040fffd, 0x00000000,
754 0x8f430400, 0x24c64660, 0xacc30010, 0x8f420404, 0x3c030020, 0xacc20014,
755 0xaf430030, 0x94c40018, 0x94c3001c, 0x94c2001a, 0x94c5001e, 0x00832021,
756 0x24420001, 0xa4c2001a, 0x3042ffff, 0x14450002, 0xa4c40018, 0xa4c0001a,
757 0x03e00008, 0x00000000, 0x8f820010, 0x3c030006, 0x00021140, 0x00431025,
758 0xaf420030, 0x00000000, 0x00000000, 0x00000000, 0x27430400, 0x8f420000,
759 0x30420010, 0x1040fffd, 0x00000000, 0xaf800010, 0xaf830018, 0x03e00008,
760 0x00000000, 0x27bdffe8, 0xafb00010, 0x3c100800, 0x26104660, 0x3c05000a,
761 0x02002021, 0x03452821, 0xafbf0014, 0x0e001128, 0x2406000a, 0x96020002,
762 0x9603001e, 0x3042000f, 0x24420003, 0x00431804, 0x24027fff, 0x0043102b,
763 0xaf830014, 0x10400004, 0x00000000, 0x0000000d, 0x00000000, 0x24000043,
764 0x0e0010d2, 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018,
765 0x10c00007, 0x00000000, 0x8ca20000, 0x24c6ffff, 0x24a50004, 0xac820000,
766 0x14c0fffb, 0x24840004, 0x03e00008, 0x00000000, 0x0a001137, 0x00a01021,
767 0xac860000, 0x24840004, 0x00a01021, 0x1440fffc, 0x24a5ffff, 0x03e00008,
768 0x00000000, 0x3c036000, 0x8c642b7c, 0x3c036010, 0x8c6553fc, 0x00041582,
769 0x00042302, 0x308403ff, 0x00052d82, 0x00441026, 0x0002102b, 0x0005282b,
770 0x00451025, 0x1440000d, 0x3c020050, 0x34420004, 0xaf400038, 0xaf40003c,
771 0xaf420030, 0x00000000, 0x00000000, 0x8f420000, 0x30420020, 0x1040fffd,
772 0x3c020020, 0xaf420030, 0x0000000d, 0x03e00008, 0x00000000, 0x3c020050,
773 0x34420004, 0xaf440038, 0xaf45003c, 0xaf420030, 0x00000000, 0x00000000,
774 0x8f420000, 0x30420020, 0x1040fffd, 0x3c020020, 0xaf420030, 0x03e00008,
775 0x00000000, 0x00000000 };
776
777static u32 bnx2_COM_b06FwData[(0x0/4) + 1] = { 0x00000000 };
778static u32 bnx2_COM_b06FwRodata[(0x18/4) + 1] = {
779 0x08002318, 0x08002348, 0x08002378, 0x080023a8, 0x080023d8, 0x00000000,
780 0x00000000 };
781
782static u32 bnx2_COM_b06FwBss[(0x88/4) + 1] = { 0x00000000 };
783static u32 bnx2_COM_b06FwSbss[(0x1c/4) + 1] = { 0x00000000 };
784
785static int bnx2_RXP_b06FwReleaseMajor = 0x0;
786static int bnx2_RXP_b06FwReleaseMinor = 0x0;
787static int bnx2_RXP_b06FwReleaseFix = 0x0;
788static u32 bnx2_RXP_b06FwStartAddr = 0x08000060;
789static u32 bnx2_RXP_b06FwTextAddr = 0x08000000;
790static int bnx2_RXP_b06FwTextLen = 0x20b8;
791static u32 bnx2_RXP_b06FwDataAddr = 0x080020e0;
792static int bnx2_RXP_b06FwDataLen = 0x0;
793static u32 bnx2_RXP_b06FwRodataAddr = 0x00000000;
794static int bnx2_RXP_b06FwRodataLen = 0x0;
795static u32 bnx2_RXP_b06FwBssAddr = 0x08002100;
796static int bnx2_RXP_b06FwBssLen = 0x239c;
797static u32 bnx2_RXP_b06FwSbssAddr = 0x080020e0;
798static int bnx2_RXP_b06FwSbssLen = 0x14;
799
800static u32 bnx2_RXP_b06FwText[(0x20b8/4) + 1] = {
801 0x0a000018, 0x00000000, 0x00000000, 0x0000000d, 0x72787020, 0x302e362e,
802 0x39000000, 0x00060903, 0x00000000, 0x0000000d, 0x00000000, 0x00000000,
803 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
804 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
805 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c020800,
806 0x244220e0, 0x3c030800, 0x2463449c, 0xac400000, 0x0043202b, 0x1480fffd,
807 0x24420004, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100060,
808 0x3c1c0800, 0x279c20e0, 0x0e000329, 0x00000000, 0x0000000d, 0x8f870008,
809 0x2ce20080, 0x10400018, 0x3c030800, 0x24633490, 0x8f460100, 0x00072140,
810 0x00831021, 0xac460000, 0x8f450104, 0x00641021, 0xac450004, 0x8f460108,
811 0xac460008, 0x8f45010c, 0xac45000c, 0x8f460114, 0xac460010, 0x8f450118,
812 0xac450014, 0x8f460124, 0xac460018, 0x8f450128, 0x00641821, 0x24e20001,
813 0xaf820008, 0xac65001c, 0x03e00008, 0x00000000, 0x00804021, 0x8f830000,
814 0x24070001, 0x3c020001, 0x00621024, 0x10400037, 0x00603021, 0x9742010e,
815 0x3c038000, 0x3045ffff, 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020003,
816 0xa342018b, 0x8f840004, 0x24020080, 0x24030002, 0xaf420180, 0xa743018c,
817 0x10800005, 0xa745018e, 0x9743011c, 0x9742011e, 0x0a000069, 0x00021400,
818 0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c,
819 0x24020003, 0x30838000, 0x1060000d, 0xa7420188, 0x93420116, 0x304200fc,
820 0x005a1021, 0x24424004, 0x8c430000, 0x3063ffff, 0x14600005, 0x00000000,
821 0x3c02ffff, 0x34427fff, 0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c,
822 0x8f440104, 0x3042bfff, 0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6,
823 0xaf4301ac, 0x3c021000, 0xaf4201b8, 0x03e00008, 0x00001021, 0x30c21000,
824 0x1040000f, 0x00000000, 0x9742010c, 0x3042fc00, 0x5440000b, 0x24070005,
825 0x3c021000, 0x00c21024, 0x10400007, 0x3c030dff, 0x3463ffff, 0x3c020e00,
826 0x00c21024, 0x0062182b, 0x54600001, 0x24070005, 0x8f82000c, 0x30434000,
827 0x10600016, 0x00404821, 0x3c020f00, 0x00c21024, 0x14400012, 0x00000000,
828 0x93420116, 0x34424000, 0x03421821, 0x94650002, 0x2ca21389, 0x1040000b,
829 0x3c020800, 0x24422100, 0x00051942, 0x00031880, 0x00621821, 0x30a5001f,
830 0x8c640000, 0x24020001, 0x00a21004, 0x00822024, 0x01044025, 0x11000037,
831 0x3c021000, 0x9742010e, 0x34e60002, 0x3c038000, 0x24420004, 0x3045ffff,
832 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020003, 0xa342018b, 0x8f840004,
833 0x24020180, 0x24030002, 0xaf420180, 0xa743018c, 0x10800005, 0xa745018e,
834 0x9743011c, 0x9742011e, 0x0a0000cd, 0x00021400, 0x9743011e, 0x9742011c,
835 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c, 0x30828000, 0x1040000c,
836 0xa7460188, 0x93420116, 0x304200fc, 0x005a1021, 0x24424004, 0x8c430000,
837 0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff, 0x00821024, 0xaf82000c,
838 0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff, 0x00031c00, 0x3084ffff,
839 0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000, 0xaf4201b8, 0x03e00008,
840 0x00001021, 0x00c21024, 0x104000ba, 0x3c020800, 0x8c430030, 0x1060003e,
841 0x31224000, 0x1040003c, 0x3c030f00, 0x00c31824, 0x3c020100, 0x0043102b,
842 0x14400038, 0x3c030800, 0x9742010e, 0x34e60002, 0x3c038000, 0x24420004,
843 0x3045ffff, 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020003, 0xa342018b,
844 0x8f840004, 0x24020080, 0x24030002, 0xaf420180, 0xa743018c, 0x10800005,
845 0xa745018e, 0x9743011c, 0x9742011e, 0x0a000110, 0x00021400, 0x9743011e,
846 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c, 0x30828000,
847 0x1040000c, 0xa7460188, 0x93420116, 0x304200fc, 0x005a1021, 0x24424004,
848 0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff, 0x00821024,
849 0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff, 0x00031c00,
850 0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000, 0xaf4201b8,
851 0x03e00008, 0x00001021, 0x3c030800, 0x8c620024, 0x30420008, 0x1040003d,
852 0x34e80002, 0x3c020f00, 0x00c21024, 0x5440003a, 0x3107ffff, 0x9742010c,
853 0x30420200, 0x50400036, 0x3107ffff, 0x9742010e, 0x30e6fffb, 0x3c038000,
854 0x24420004, 0x3045ffff, 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020003,
855 0xa342018b, 0x8f840004, 0x24020180, 0x24030002, 0xaf420180, 0xa743018c,
856 0x10800005, 0xa745018e, 0x9743011c, 0x9742011e, 0x0a000153, 0x00021400,
857 0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c,
858 0x30828000, 0x1040000c, 0xa7460188, 0x93420116, 0x304200fc, 0x005a1021,
859 0x24424004, 0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff,
860 0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff,
861 0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000,
862 0xaf4201b8, 0x3107ffff, 0x8f820000, 0x3c068000, 0x9743010e, 0x00021442,
863 0x30440780, 0x24630004, 0x3065ffff, 0x8f4201b8, 0x00461024, 0x1440fffd,
864 0x24020003, 0xa342018b, 0x8f830004, 0x24020002, 0xaf440180, 0xa742018c,
865 0x10600005, 0xa745018e, 0x9743011c, 0x9742011e, 0x0a000189, 0x00021400,
866 0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c,
867 0x30828000, 0x1040000c, 0xa7470188, 0x93420116, 0x304200fc, 0x005a1021,
868 0x24424004, 0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff,
869 0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff,
870 0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000,
871 0xaf4201b8, 0x03e00008, 0x00001021, 0x8f424000, 0x30420100, 0x104000ef,
872 0x3c020800, 0x8c440024, 0x24030001, 0x14830036, 0x00404021, 0x9742010e,
873 0x34e50002, 0x3c038000, 0x24420004, 0x3044ffff, 0x8f4201b8, 0x00431024,
874 0x1440fffd, 0x24020003, 0xa342018b, 0x8f830004, 0x24020002, 0xaf400180,
875 0xa742018c, 0x10600005, 0xa744018e, 0x9743011c, 0x9742011e, 0x0a0001c6,
876 0x00021400, 0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8,
877 0x8f84000c, 0x30828000, 0x1040000c, 0xa7450188, 0x93420116, 0x304200fc,
878 0x005a1021, 0x24424004, 0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff,
879 0x34427fff, 0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104,
880 0x3042bfff, 0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac,
881 0x3c021000, 0xaf4201b8, 0x03e00008, 0x00001021, 0x30820001, 0x10400035,
882 0x30e90004, 0x9742010e, 0x30e6fffb, 0x3c038000, 0x24420004, 0x3044ffff,
883 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020003, 0xa342018b, 0x8f830004,
884 0x24020002, 0xaf400180, 0xa742018c, 0x10600005, 0xa744018e, 0x9743011c,
885 0x9742011e, 0x0a0001fe, 0x00021400, 0x9743011e, 0x9742011c, 0x00021400,
886 0x00621825, 0xaf4301a8, 0x8f84000c, 0x30828000, 0x1040000c, 0xa7470188,
887 0x93420116, 0x304200fc, 0x005a1021, 0x24424004, 0x8c430000, 0x3063ffff,
888 0x14600004, 0x3c02ffff, 0x34427fff, 0x00821024, 0xaf82000c, 0x9782000e,
889 0x9743010c, 0x8f440104, 0x3042bfff, 0x00031c00, 0x3084ffff, 0x00641825,
890 0xa74201a6, 0xaf4301ac, 0x3c021000, 0xaf4201b8, 0x30c7ffff, 0x8d020024,
891 0x30420004, 0x10400037, 0x8d020024, 0x9742010e, 0x30e6fffb, 0x3c038000,
892 0x24420004, 0x3045ffff, 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020003,
893 0xa342018b, 0x8f840004, 0x24020100, 0x24030002, 0xaf420180, 0xa743018c,
894 0x10800005, 0xa745018e, 0x9743011c, 0x9742011e, 0x0a000237, 0x00021400,
895 0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c,
896 0x30828000, 0x1040000c, 0xa7470188, 0x93420116, 0x304200fc, 0x005a1021,
897 0x24424004, 0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff,
898 0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff,
899 0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000,
900 0xaf4201b8, 0x30c7ffff, 0x8d020024, 0x30420008, 0x10400034, 0x00000000,
901 0x9742010e, 0x3c038000, 0x24420004, 0x3045ffff, 0x8f4201b8, 0x00431024,
902 0x1440fffd, 0x24020003, 0xa342018b, 0x8f840004, 0x24020180, 0x24030002,
903 0xaf420180, 0xa743018c, 0x10800005, 0xa745018e, 0x9743011c, 0x9742011e,
904 0x0a00026f, 0x00021400, 0x9743011e, 0x9742011c, 0x00021400, 0x00621825,
905 0xaf4301a8, 0x8f84000c, 0x30828000, 0x1040000c, 0xa7470188, 0x93420116,
906 0x304200fc, 0x005a1021, 0x24424004, 0x8c430000, 0x3063ffff, 0x14600004,
907 0x3c02ffff, 0x34427fff, 0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c,
908 0x8f440104, 0x3042bfff, 0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6,
909 0xaf4301ac, 0x3c021000, 0xaf4201b8, 0x15200046, 0x00001021, 0x3c038000,
910 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020002, 0x24032000, 0xa342018b,
911 0xa7430188, 0x3c021000, 0xaf4201b8, 0x03e00008, 0x00001021, 0x3c030800,
912 0x8c620024, 0x30420001, 0x10400035, 0x00001021, 0x9742010e, 0x34e50002,
913 0x3c038000, 0x24420004, 0x3044ffff, 0x8f4201b8, 0x00431024, 0x1440fffd,
914 0x24020003, 0xa342018b, 0x8f830004, 0x24020002, 0xaf400180, 0xa742018c,
915 0x10600005, 0xa744018e, 0x9743011c, 0x9742011e, 0x0a0002b5, 0x00021400,
916 0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c,
917 0x30828000, 0x1040000c, 0xa7450188, 0x93420116, 0x304200fc, 0x005a1021,
918 0x24424004, 0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff,
919 0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff,
920 0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000,
921 0xaf4201b8, 0x00001021, 0x03e00008, 0x00000000, 0x27bdffe0, 0xafbf0018,
922 0xafb10014, 0xafb00010, 0x8f420140, 0xaf420020, 0x8f430148, 0x3c027000,
923 0x00621824, 0x3c024000, 0x1062000c, 0x0043102b, 0x14400006, 0x3c025000,
924 0x3c023000, 0x1062000b, 0x3c024000, 0x0a00031f, 0x00000000, 0x10620034,
925 0x3c024000, 0x0a00031f, 0x00000000, 0x0e00067c, 0x00000000, 0x0a00031f,
926 0x3c024000, 0x8f420148, 0x24030002, 0x3044ffff, 0x00021402, 0x305000ff,
927 0x1203000c, 0x27510180, 0x2a020003, 0x10400005, 0x24020003, 0x0600001d,
928 0x36053000, 0x0a00030a, 0x3c038000, 0x12020007, 0x00000000, 0x0a000317,
929 0x00000000, 0x0e000423, 0x00000000, 0x0a000308, 0x00402021, 0x0e000435,
930 0x00000000, 0x00402021, 0x36053000, 0x3c038000, 0x8f4201b8, 0x00431024,
931 0x1440fffd, 0x24020002, 0xa6250008, 0xa222000b, 0xa6240010, 0x8f420144,
932 0x3c031000, 0xae220024, 0xaf4301b8, 0x0a00031f, 0x3c024000, 0x0000000d,
933 0x00000000, 0x240001c3, 0x0a00031f, 0x3c024000, 0x0e0007f7, 0x00000000,
934 0x3c024000, 0xaf420178, 0x00000000, 0x8fbf0018, 0x8fb10014, 0x8fb00010,
935 0x03e00008, 0x27bd0020, 0x24020800, 0x03e00008, 0xaf4201b8, 0x27bdffe8,
936 0x3c04600c, 0xafbf0014, 0xafb00010, 0x8c825000, 0x3c1a8000, 0x2403ff7f,
937 0x3c106000, 0x00431024, 0x3442380c, 0x24030003, 0xac825000, 0x3c040008,
938 0xaf430008, 0x8e020808, 0x3c030800, 0xac600020, 0x3042fff0, 0x2c420001,
939 0xaf820004, 0x0e000819, 0x0344d825, 0x0e000781, 0x00000000, 0x3c020400,
940 0x3442000c, 0x3c03ffff, 0x34630806, 0xae021948, 0xae03194c, 0x8e021980,
941 0x34420200, 0xae021980, 0x8f500000, 0x32020003, 0x1040fffd, 0x32020001,
942 0x10400004, 0x32020002, 0x0e0003bd, 0x00000000, 0x32020002, 0x1040fff6,
943 0x00000000, 0x0e0002d4, 0x00000000, 0x0a00034a, 0x00000000, 0x27bdffe8,
944 0x3c04600c, 0xafbf0014, 0xafb00010, 0x8c825000, 0x3c1a8000, 0x2403ff7f,
945 0x3c106000, 0x00431024, 0x3442380c, 0x24030003, 0xac825000, 0x3c040008,
946 0xaf430008, 0x8e020808, 0x3c030800, 0xac600020, 0x3042fff0, 0x2c420001,
947 0xaf820004, 0x0e000819, 0x0344d825, 0x0e000781, 0x00000000, 0x3c020400,
948 0x3442000c, 0x3c03ffff, 0x34630806, 0xae021948, 0xae03194c, 0x8e021980,
949 0x8fbf0014, 0x34420200, 0xae021980, 0x8fb00010, 0x03e00008, 0x27bd0018,
950 0x30a5ffff, 0x30c6ffff, 0x30e7ffff, 0x3c038000, 0x8f4201b8, 0x00431024,
951 0x1440fffd, 0x24020003, 0xa342018b, 0x8f830004, 0xaf440180, 0xa745018c,
952 0x10600005, 0xa746018e, 0x9743011c, 0x9742011e, 0x0a000393, 0x00021400,
953 0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c,
954 0x30828000, 0x1040000c, 0xa7470188, 0x93420116, 0x304200fc, 0x005a1021,
955 0x24424004, 0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff,
956 0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff,
957 0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000,
958 0xaf4201b8, 0x03e00008, 0x00000000, 0x3c038000, 0x8f4201b8, 0x00431024,
959 0x1440fffd, 0x24020002, 0x24032000, 0xa342018b, 0xa7430188, 0x3c021000,
960 0xaf4201b8, 0x03e00008, 0x00000000, 0x27bdffe8, 0xafbf0010, 0x8f460128,
961 0xaf460020, 0x8f420104, 0x8f450100, 0x24030800, 0x3c040010, 0xaf820000,
962 0x00441024, 0xaf85000c, 0xaf4301b8, 0x14400005, 0x3c02001f, 0x3c030800,
963 0x8c620020, 0x0a0003d5, 0x00002021, 0x3442ff00, 0x14c20009, 0x2402bfff,
964 0x3c030800, 0x8c620020, 0x24040001, 0x24420001, 0x0e00004c, 0xac620020,
965 0x0a0003e4, 0x00000000, 0x00a21024, 0x14400006, 0x00000000, 0xaf400048,
966 0x0e000448, 0xaf400040, 0x0a0003e4, 0x00000000, 0x0e000783, 0x00000000,
967 0x10400005, 0x3c024000, 0x8f430124, 0x3c026020, 0xac430014, 0x3c024000,
968 0xaf420138, 0x00000000, 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x27bdffe0,
969 0xafbf0018, 0xafb10014, 0xafb00010, 0x8f420148, 0x24030002, 0x3044ffff,
970 0x00021402, 0x305000ff, 0x1203000c, 0x27510180, 0x2a020003, 0x10400005,
971 0x24020003, 0x0600001d, 0x36053000, 0x0a00040e, 0x3c038000, 0x12020007,
972 0x00000000, 0x0a00041b, 0x00000000, 0x0e000423, 0x00000000, 0x0a00040c,
973 0x00402021, 0x0e000435, 0x00000000, 0x00402021, 0x36053000, 0x3c038000,
974 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020002, 0xa6250008, 0xa222000b,
975 0xa6240010, 0x8f420144, 0x3c031000, 0xae220024, 0xaf4301b8, 0x0a00041f,
976 0x8fbf0018, 0x0000000d, 0x00000000, 0x240001c3, 0x8fbf0018, 0x8fb10014,
977 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3084ffff, 0x2c821389, 0x1040000d,
978 0x00001021, 0x3c030800, 0x24632100, 0x00042942, 0x00052880, 0x00a32821,
979 0x3086001f, 0x8ca40000, 0x24030001, 0x00c31804, 0x00832025, 0x03e00008,
980 0xaca40000, 0x03e00008, 0x24020091, 0x3084ffff, 0x2c821389, 0x1040000e,
981 0x00001021, 0x3c030800, 0x24632100, 0x00042942, 0x00052880, 0x00a32821,
982 0x3086001f, 0x24030001, 0x8ca40000, 0x00c31804, 0x00031827, 0x00832024,
983 0x03e00008, 0xaca40000, 0x03e00008, 0x24020091, 0x27bdffb0, 0x3c026000,
984 0xafbf0048, 0x8c434448, 0xaf630140, 0x93620005, 0x30420001, 0x14400005,
985 0x00000000, 0x0e0007ed, 0x00000000, 0x0a00067a, 0x8fbf0048, 0x93420116,
986 0x93430112, 0x8f430104, 0x3c040020, 0x34424000, 0x00641824, 0x1060000d,
987 0x03426021, 0x8f430128, 0x27420180, 0xac430000, 0x8f650040, 0x24040008,
988 0x240340c1, 0xa4430008, 0x24030002, 0xa043000b, 0x3c031000, 0x0a000563,
989 0xa044000a, 0x8f420104, 0x3c030040, 0x00431024, 0x10400007, 0x00000000,
990 0x8f430128, 0x27420180, 0xac430000, 0x8f650040, 0x0a00055c, 0x24040010,
991 0xaf400048, 0xaf400054, 0xaf400040, 0x8f630048, 0x8f620040, 0x00624823,
992 0x05210004, 0x00000000, 0x0000000d, 0x00000000, 0x24000132, 0x9742011a,
993 0x3046ffff, 0x10c00004, 0x8d880004, 0x01061021, 0x0a000487, 0x2445ffff,
994 0x01002821, 0x918a000d, 0xa7a00020, 0xafa00028, 0x9364003f, 0x3c026000,
995 0x8c434448, 0x308700ff, 0x31420004, 0x10400033, 0xaf630144, 0x24090012,
996 0x14e90006, 0x3c040800, 0x8c830028, 0x24020001, 0x24630001, 0x0a00054e,
997 0xac830028, 0x8f620044, 0x15020012, 0x97a20020, 0x27a60010, 0x27450180,
998 0x3442001a, 0xa7a20020, 0x8f630040, 0x3c048000, 0x24020020, 0xa3a70022,
999 0xa3a90023, 0xa3a2001a, 0xafa30028, 0x8f4201b8, 0x00441024, 0x1440fffd,
1000 0x00000000, 0x0a000533, 0x00000000, 0x8f620044, 0x01021023, 0x0440009e,
1001 0x24020001, 0x8f620048, 0x01021023, 0x0441009a, 0x24020001, 0x97a20020,
1002 0x27a60010, 0x34420001, 0xa7a20020, 0x8f630040, 0x27450180, 0x3c048000,
1003 0xafa30028, 0x8f4201b8, 0x00441024, 0x1440fffd, 0x00000000, 0x0a000533,
1004 0x00000000, 0x3c026000, 0x8c424448, 0xaf620148, 0x8f630040, 0x00685823,
1005 0x19600013, 0x00cb102a, 0x54400007, 0x314a00fe, 0x5566000c, 0x010b4021,
1006 0x31420001, 0x54400009, 0x010b4021, 0x314a00fe, 0x24020001, 0xa7a20020,
1007 0x8f630040, 0x00c05821, 0x00003021, 0x0a0004dd, 0xafa30028, 0x00cb1023,
1008 0x0a0004dd, 0x3046ffff, 0x00005821, 0x8f620048, 0x2442ffff, 0x00a21823,
1009 0x18600019, 0x0066102a, 0x14400013, 0x24020001, 0xa7a20020, 0x8f630040,
1010 0xafa30028, 0x8f620040, 0x55020005, 0x27a60010, 0x55200003, 0x27a60010,
1011 0x0a0004f6, 0x00c01821, 0x27450180, 0x3c038000, 0x8f4201b8, 0x00431024,
1012 0x1440fffd, 0x00000000, 0x0a000533, 0x00000000, 0x8f650048, 0x00c31023,
1013 0x3046ffff, 0x314a00f6, 0x3c046000, 0x8c824448, 0x31430002, 0x1060001e,
1014 0xaf62014c, 0x8f620044, 0x1502000e, 0x97a20020, 0x27a60010, 0x34420200,
1015 0xa7a20020, 0x8f630040, 0x27450180, 0x3c048000, 0xafa30028, 0x8f4201b8,
1016 0x00441024, 0x1440fffd, 0x00000000, 0x0a000533, 0x00000000, 0x27a60010,
1017 0x34420001, 0xa7a20020, 0x8f630040, 0x27450180, 0x3c048000, 0xafa30028,
1018 0x8f4201b8, 0x00441024, 0x1440fffd, 0x00000000, 0x0a000533, 0x00000000,
1019 0x3c026000, 0x8c424448, 0x31430010, 0xaf620150, 0x54600003, 0x8d890008,
1020 0x0a00054e, 0x24020001, 0x8f630054, 0x2522ffff, 0x00431023, 0x1840002a,
1021 0x24020001, 0x27a60010, 0xa7a20020, 0x8f630040, 0x27450180, 0x3c048000,
1022 0xafa30028, 0x8f4201b8, 0x00441024, 0x1440fffd, 0x00000000, 0x8f420128,
1023 0xaca20000, 0x8cc30018, 0x240240c1, 0xa4a20008, 0xaca30018, 0x90c4000a,
1024 0x24020002, 0xa0a2000b, 0xa0a4000a, 0x94c20010, 0xa4a20010, 0x90c30012,
1025 0xa0a30012, 0x90c20013, 0xa0a20013, 0x8cc30014, 0xaca30014, 0x8cc20024,
1026 0xaca20024, 0x8cc30028, 0xaca30028, 0x8cc4002c, 0x24020001, 0x3c031000,
1027 0xaca4002c, 0xaf4301b8, 0xaf400044, 0xaf400050, 0x0a00067a, 0x8fbf0048,
1028 0x3c026000, 0x8c424448, 0x31430020, 0x10600019, 0xaf620154, 0x8f430128,
1029 0x27420180, 0xac430000, 0x8f650040, 0x24040004, 0x240340c1, 0xa4430008,
1030 0x24030002, 0xa044000a, 0x24040008, 0xa043000b, 0x3c031000, 0xa4440010,
1031 0xa0400012, 0xa0400013, 0xac400014, 0xac400024, 0xac400028, 0xac40002c,
1032 0xac450018, 0x0e0007ed, 0xaf4301b8, 0x0a00067a, 0x8fbf0048, 0x8f430104,
1033 0x8c824448, 0x38e3000a, 0x2c630001, 0xaf620158, 0x38e2000c, 0x2c420001,
1034 0x00621825, 0x14600003, 0x2402000e, 0x14e2002a, 0x00000000, 0x50c00008,
1035 0x9584000e, 0x10c00004, 0xa7a60040, 0x01061021, 0x0a000583, 0x2445ffff,
1036 0x01002821, 0x9584000e, 0x93630035, 0x8f62004c, 0x00642004, 0x00892021,
1037 0x00821023, 0x1840001f, 0x3c026000, 0x8f620018, 0x01021023, 0x1c40000f,
1038 0x97a20020, 0x8f620018, 0x15020018, 0x3c026000, 0x8f62001c, 0x01221023,
1039 0x1c400008, 0x97a20020, 0x8f62001c, 0x15220011, 0x3c026000, 0x8f620058,
1040 0x00821023, 0x1840000c, 0x97a20020, 0xafa50028, 0xafa80034, 0xafa90038,
1041 0xafa4003c, 0x34420020, 0x0a0005a8, 0xa7a20020, 0x8f680040, 0x00003021,
1042 0x8f640058, 0x01002821, 0x3c026000, 0x8c434448, 0xaf63015c, 0x8f62004c,
1043 0x01221023, 0x18400009, 0x00000000, 0x8f620054, 0x01221023, 0x1c400005,
1044 0x97a20020, 0xafa50028, 0xafa90024, 0x0a0005c3, 0x34420040, 0x9742011a,
1045 0x1440000c, 0x24020014, 0x8f620058, 0x14820009, 0x24020014, 0x8f63004c,
1046 0x8f620054, 0x10620004, 0x97a20020, 0xafa50028, 0x34420080, 0xa7a20020,
1047 0x24020014, 0x10e2000a, 0x28e20015, 0x10400005, 0x2402000c, 0x10e20006,
1048 0x3c026000, 0x0a000600, 0x00000000, 0x24020016, 0x14e20031, 0x3c026000,
1049 0x8f620054, 0x24420001, 0x1522002d, 0x3c026000, 0x24020014, 0x10e2001e,
1050 0x28e20015, 0x10400005, 0x2402000c, 0x10e20008, 0x3c026000, 0x0a000600,
1051 0x00000000, 0x24020016, 0x10e2000c, 0x97a20020, 0x0a000600, 0x3c026000,
1052 0x97a30020, 0x2402000e, 0xafa50028, 0xa3a70022, 0xa3a20023, 0xafa90024,
1053 0x34630054, 0x0a0005ff, 0xa7a30020, 0x24030010, 0x24040002, 0xafa50028,
1054 0xa3a70022, 0xa3a30023, 0xa3a4001a, 0xafa90024, 0x0a0005fe, 0x3442005d,
1055 0x97a20020, 0x24030012, 0x24040002, 0xafa50028, 0xa3a70022, 0xa3a30023,
1056 0xa3a4001a, 0xafa90024, 0x3042fffe, 0x3442005c, 0xa7a20020, 0x3c026000,
1057 0x8c434448, 0x31420001, 0xaf630160, 0x1040002c, 0x2402000c, 0x10e20014,
1058 0x28e2000d, 0x10400005, 0x2402000a, 0x10e20008, 0x97a20020, 0x0a000631,
1059 0x3c026000, 0x2402000e, 0x10e20018, 0x3c026000, 0x0a000631, 0x00000000,
1060 0x24030008, 0x24040002, 0xafa50028, 0xa3a70022, 0xa3a30023, 0xa3a4001a,
1061 0x0a00062f, 0x34420013, 0x97a30020, 0x30620004, 0x1440000b, 0x97a20020,
1062 0x3462001b, 0xa7a20020, 0x24020016, 0x24030002, 0xafa50028, 0xa3a70022,
1063 0xa3a20023, 0x0a000630, 0xa3a3001a, 0x97a20020, 0x24030010, 0x24040002,
1064 0xafa50028, 0xa3a70022, 0xa3a30023, 0xa3a4001a, 0x3442001b, 0xa7a20020,
1065 0x3c026000, 0x8c434448, 0x31420009, 0x0002102b, 0x00021023, 0x30420007,
1066 0x34440003, 0xaf630164, 0x10c00016, 0x24030800, 0x8f820010, 0x27450180,
1067 0x24420001, 0xaf820010, 0x24020004, 0xaf4301b8, 0xa4a40008, 0xa0a2000b,
1068 0x93440120, 0x3c031000, 0xa4a6000e, 0xaca90024, 0xaca80028, 0x008b2021,
1069 0xa4a4000c, 0xaf4301b8, 0x97a20020, 0x00003021, 0x3042ffbf, 0x0a000650,
1070 0xa7a20020, 0x24060001, 0x3c026000, 0x8c434448, 0xaf630168, 0x97a20020,
1071 0x10400020, 0x27450180, 0x3c038000, 0x8f4201b8, 0x00431024, 0x1440fffd,
1072 0x00000000, 0x8f420128, 0xaca20000, 0x8fa30028, 0x240240c1, 0xa4a20008,
1073 0xaca30018, 0x93a4001a, 0x24020002, 0xa0a2000b, 0xa0a4000a, 0x97a20020,
1074 0xa4a20010, 0x93a30022, 0xa0a30012, 0x93a20023, 0xa0a20013, 0x8fa30024,
1075 0xaca30014, 0x8fa20034, 0xaca20024, 0x8fa30038, 0xaca30028, 0x8fa2003c,
1076 0x3c031000, 0xaca2002c, 0xaf4301b8, 0x3c026000, 0x8c434448, 0x00c01021,
1077 0xaf63016c, 0x8fbf0048, 0x03e00008, 0x27bd0050, 0x8f460140, 0x8f470148,
1078 0x3c028000, 0x00e24024, 0x00072c02, 0x30a300ff, 0x2402000b, 0x1062008f,
1079 0x27440180, 0x2862000c, 0x10400011, 0x24020006, 0x1062005a, 0x28620007,
1080 0x10400007, 0x24020008, 0x10600024, 0x24020001, 0x10620037, 0x00000000,
1081 0x0a00077e, 0x00000000, 0x106200a9, 0x24020009, 0x106200bb, 0x00071c02,
1082 0x0a00077e, 0x00000000, 0x2402001b, 0x106200c7, 0x2862001c, 0x10400007,
1083 0x2402000e, 0x106200b1, 0x24020019, 0x106200c2, 0x00071c02, 0x0a00077e,
1084 0x00000000, 0x24020080, 0x10620060, 0x28620081, 0x10400005, 0x2402001c,
1085 0x10620094, 0x00071c02, 0x0a00077e, 0x00000000, 0x240200c2, 0x106200c5,
1086 0x00a01821, 0x0a00077e, 0x00000000, 0x00a01821, 0x3c058000, 0x8f4201b8,
1087 0x00451024, 0x1440fffd, 0x24020001, 0xa4830008, 0x24030002, 0xac860000,
1088 0xac800004, 0xa082000a, 0xa083000b, 0xa4870010, 0x8f430144, 0x3c021000,
1089 0xac800028, 0xac830024, 0x3c036000, 0xaf4201b8, 0x03e00008, 0xac600808,
1090 0x11000009, 0x00a01821, 0x3c020800, 0x24030002, 0xa0434490, 0x24424490,
1091 0xac460008, 0x8f430144, 0x03e00008, 0xac430004, 0x3c058000, 0x8f4201b8,
1092 0x00451024, 0x1440fffd, 0x24020002, 0xac800000, 0xac860004, 0xa4830008,
1093 0xa082000a, 0xa082000b, 0xa4870010, 0xac800024, 0x8f420144, 0x3c031000,
1094 0xac820028, 0x3c026000, 0xaf4301b8, 0x03e00008, 0xac400808, 0x00a01821,
1095 0x3c080800, 0x3c058000, 0x8f4201b8, 0x00451024, 0x1440fffd, 0x00000000,
1096 0xac860000, 0x91024490, 0x00002821, 0x10400002, 0x25064490, 0x8cc50008,
1097 0xac850004, 0xa4830008, 0x91034490, 0x24020002, 0xa082000b, 0xa4870010,
1098 0x34630001, 0xa083000a, 0x8f420144, 0xac820024, 0x91034490, 0x10600002,
1099 0x00001021, 0x8cc20004, 0xac820028, 0x3c021000, 0xaf4201b8, 0x3c026000,
1100 0xa1004490, 0x03e00008, 0xac400808, 0x00a01821, 0x3c058000, 0x8f4201b8,
1101 0x00451024, 0x1440fffd, 0x24020002, 0xa082000b, 0xa4830008, 0xa4870010,
1102 0x8f420144, 0x3c031000, 0xa4820012, 0x03e00008, 0xaf4301b8, 0x30e2ffff,
1103 0x14400028, 0x00071c02, 0x93620005, 0x30420004, 0x14400020, 0x3c029000,
1104 0x34420001, 0x00c21025, 0xaf420020, 0x3c038000, 0x8f420020, 0x00431024,
1105 0x1440fffd, 0x00000000, 0x93620005, 0x3c038000, 0x34630001, 0x00c31825,
1106 0x34420004, 0xa3620005, 0xaf430020, 0x93620005, 0x30420004, 0x14400003,
1107 0x3c038000, 0x0000000d, 0x3c038000, 0x8f4201b8, 0x00431024, 0x1440fffd,
1108 0x24020005, 0x3c031000, 0xac860000, 0xa082000b, 0xaf4301b8, 0x0a00073d,
1109 0x00071c02, 0x0000000d, 0x03e00008, 0x00000000, 0x00071c02, 0x3c058000,
1110 0x8f4201b8, 0x00451024, 0x1440fffd, 0x24020001, 0xa4830008, 0x24030002,
1111 0xac860000, 0xac800004, 0xa082000a, 0xa083000b, 0xa4870010, 0x8f430144,
1112 0x3c021000, 0xac800028, 0xac830024, 0x03e00008, 0xaf4201b8, 0x00071c02,
1113 0x3c058000, 0x8f4201b8, 0x00451024, 0x1440fffd, 0x24020002, 0xac800000,
1114 0xac860004, 0xa4830008, 0xa082000a, 0xa082000b, 0xa4870010, 0xac800024,
1115 0x8f420144, 0x3c031000, 0xac820028, 0x03e00008, 0xaf4301b8, 0x00071c02,
1116 0x3c058000, 0x8f4201b8, 0x00451024, 0x1440fffd, 0x24020001, 0xa4830008,
1117 0x24030002, 0xa082000a, 0x3c021000, 0xac860000, 0xac800004, 0xa083000b,
1118 0xa4870010, 0xac800024, 0xac800028, 0x03e00008, 0xaf4201b8, 0x3c058000,
1119 0x8f4201b8, 0x00451024, 0x1440fffd, 0x24020002, 0xac860000, 0xac800004,
1120 0xa4830008, 0xa080000a, 0x0a000748, 0xa082000b, 0x0000000d, 0x03e00008,
1121 0x00000000, 0x03e00008, 0x00000000, 0x8f420100, 0x3042003e, 0x14400011,
1122 0x24020001, 0xaf400048, 0x8f420100, 0x304207c0, 0x10400005, 0x00000000,
1123 0xaf40004c, 0xaf400050, 0x03e00008, 0x24020001, 0xaf400054, 0xaf400040,
1124 0x8f420100, 0x30423800, 0x54400001, 0xaf400044, 0x24020001, 0x03e00008,
1125 0x00000000, 0x3c029000, 0x34420001, 0x00822025, 0xaf440020, 0x3c038000,
1126 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x03e00008, 0x00000000,
1127 0x3c028000, 0x34420001, 0x00822025, 0x03e00008, 0xaf440020, 0x8f430128,
1128 0x27420180, 0xac430000, 0x8f650040, 0x240340c1, 0xa4430008, 0x24030002,
1129 0xa044000a, 0x24040008, 0xa043000b, 0x3c031000, 0xa4440010, 0xa0400012,
1130 0xa0400013, 0xac400014, 0xac400024, 0xac400028, 0xac40002c, 0xac450018,
1131 0x03e00008, 0xaf4301b8, 0x24020001, 0xacc40000, 0x03e00008, 0xa4e50000,
1132 0x03e00008, 0x24020001, 0x24020001, 0xaf400044, 0x03e00008, 0xaf400050,
1133 0x00803021, 0x27450180, 0x3c038000, 0x8f4201b8, 0x00431024, 0x1440fffd,
1134 0x00000000, 0x8f420128, 0xaca20000, 0x8cc30018, 0x240240c1, 0xa4a20008,
1135 0xaca30018, 0x90c4000a, 0x24020002, 0xa0a2000b, 0xa0a4000a, 0x94c20010,
1136 0xa4a20010, 0x90c30012, 0xa0a30012, 0x90c20013, 0xa0a20013, 0x8cc30014,
1137 0xaca30014, 0x8cc20024, 0xaca20024, 0x8cc30028, 0xaca30028, 0x8cc2002c,
1138 0x3c031000, 0xaca2002c, 0x24020001, 0xaf4301b8, 0xaf400044, 0x03e00008,
1139 0xaf400050, 0x27bdffe8, 0xafbf0010, 0x0e000326, 0x00000000, 0x00002021,
1140 0x0e00004c, 0xaf400180, 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x8f460148,
1141 0x27450180, 0x3c038000, 0x00061402, 0x304700ff, 0x8f4201b8, 0x00431024,
1142 0x1440fffd, 0x00000000, 0x8f440140, 0x00061202, 0x304200ff, 0x00061c02,
1143 0xaca20004, 0x24020002, 0xa4a30008, 0x30c300ff, 0xa0a2000b, 0xaca30024,
1144 0x10e0000a, 0xaca40000, 0x28e20004, 0x14400005, 0x24020001, 0x24020005,
1145 0x54e20005, 0xa0a0000a, 0x24020001, 0x0a000816, 0xa0a2000a, 0xa0a0000a,
1146 0x3c021000, 0x03e00008, 0xaf4201b8, 0x03e00008, 0x00001021, 0x10c00007,
1147 0x00000000, 0x8ca20000, 0x24c6ffff, 0x24a50004, 0xac820000, 0x14c0fffb,
1148 0x24840004, 0x03e00008, 0x00000000, 0x0a00082a, 0x00a01021, 0xac860000,
1149 0x24840004, 0x00a01021, 0x1440fffc, 0x24a5ffff, 0x03e00008, 0x00000000,
1150 0x00000000 };
1151
1152static u32 bnx2_RXP_b06FwData[(0x0/4) + 1] = { 0x00000000 };
1153static u32 bnx2_RXP_b06FwRodata[(0x0/4) + 1] = { 0x00000000 };
1154static u32 bnx2_RXP_b06FwBss[(0x239c/4) + 1] = { 0x00000000 };
1155static u32 bnx2_RXP_b06FwSbss[(0x14/4) + 1] = { 0x00000000 };
1156
1157static u32 bnx2_rv2p_proc1[] = {
1158 0x00000008, 0xac000001, 0x0000000c, 0x2f800001, 0x00000010, 0x213f0004,
1159 0x00000010, 0x20bf002c, 0x00000010, 0x203f0143, 0x00000018, 0x8000fffd,
1160 0x00000010, 0xb1b8b017, 0x0000000b, 0x2fdf0002, 0x00000000, 0x03d80000,
1161 0x00000000, 0x2c380000, 0x00000008, 0x2c800000, 0x00000008, 0x2d000000,
1162 0x00000010, 0x91d40000, 0x00000008, 0x2d800108, 0x00000008, 0x02000002,
1163 0x00000010, 0x91de0000, 0x0000000f, 0x42e0001c, 0x00000010, 0x91840a08,
1164 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008, 0x00000008, 0x2d800150,
1165 0x00000000, 0x00000000, 0x00000010, 0x91de0000, 0x00000010, 0x2c620002,
1166 0x00000018, 0x80000012, 0x0000000b, 0x2fdf0002, 0x0000000c, 0x1f800002,
1167 0x00000000, 0x2c070000, 0x00000018, 0x8000ffe6, 0x00000008, 0x02000002,
1168 0x0000000f, 0x42e0001c, 0x00000010, 0x91840a08, 0x00000008, 0x2c8000b0,
1169 0x00000008, 0x2d000008, 0x00000010, 0x91d40000, 0x00000008, 0x2d800108,
1170 0x00000000, 0x00000000, 0x00000010, 0x91de0000, 0x00000018, 0x80000004,
1171 0x0000000c, 0x1f800002, 0x00000000, 0x00000000, 0x00000018, 0x8000ffd9,
1172 0x0000000c, 0x29800002, 0x0000000c, 0x1f800002, 0x00000000, 0x2adf0000,
1173 0x00000008, 0x2a000005, 0x00000018, 0x8000ffd4, 0x00000008, 0x02240030,
1174 0x00000018, 0x00040000, 0x00000018, 0x80000015, 0x00000018, 0x80000017,
1175 0x00000018, 0x8000001b, 0x00000018, 0x8000004c, 0x00000018, 0x8000008c,
1176 0x00000018, 0x8000000f, 0x00000018, 0x8000000e, 0x00000018, 0x8000000d,
1177 0x00000018, 0x8000000c, 0x00000018, 0x800000c2, 0x00000018, 0x8000000a,
1178 0x00000018, 0x80000009, 0x00000018, 0x80000008, 0x00000018, 0x800000fd,
1179 0x00000018, 0x80000006, 0x00000018, 0x80000005, 0x00000018, 0x800000ff,
1180 0x00000018, 0x80000104, 0x00000018, 0x80000002, 0x00000018, 0x80000098,
1181 0x00000018, 0x80000000, 0x0000000c, 0x1f800001, 0x00000000, 0x00000000,
1182 0x00000018, 0x8000ffba, 0x00000010, 0x91d40000, 0x0000000c, 0x29800001,
1183 0x0000000c, 0x1f800001, 0x00000008, 0x2a000002, 0x00000018, 0x8000ffb5,
1184 0x00000010, 0xb1a0b012, 0x0000000b, 0x2fdf0002, 0x00000000, 0x2c200000,
1185 0x00000008, 0x2c800000, 0x00000008, 0x2d000000, 0x00000010, 0x91d40000,
1186 0x00000008, 0x2d80011c, 0x00000000, 0x00000000, 0x00000010, 0x91de0000,
1187 0x0000000f, 0x47600008, 0x0000000f, 0x060e0001, 0x00000010, 0x001f0000,
1188 0x00000000, 0x0f580000, 0x00000000, 0x0a640000, 0x00000000, 0x0ae50000,
1189 0x00000000, 0x0b660000, 0x00000000, 0x0d610000, 0x00000018, 0x80000013,
1190 0x0000000f, 0x47600008, 0x0000000b, 0x2fdf0002, 0x00000008, 0x2c800000,
1191 0x00000008, 0x2d000000, 0x00000010, 0x91d40000, 0x00000008, 0x2d80011c,
1192 0x0000000f, 0x060e0001, 0x00000010, 0x001f0000, 0x00000000, 0x0f580000,
1193 0x00000010, 0x91de0000, 0x00000000, 0x0a640000, 0x00000000, 0x0ae50000,
1194 0x00000000, 0x0b660000, 0x00000000, 0x0d610000, 0x00000000, 0x02620000,
1195 0x0000000b, 0x2fdf0002, 0x00000000, 0x309a0000, 0x00000000, 0x31040000,
1196 0x00000000, 0x0c961800, 0x00000009, 0x0c99ffff, 0x00000004, 0xcc993400,
1197 0x00000010, 0xb1963202, 0x00000008, 0x0f800000, 0x0000000c, 0x29800001,
1198 0x00000010, 0x00220002, 0x0000000c, 0x29520001, 0x0000000c, 0x29520000,
1199 0x00000008, 0x22000001, 0x0000000c, 0x1f800001, 0x00000000, 0x2adf0000,
1200 0x00000008, 0x2a000003, 0x00000018, 0x8000ff83, 0x00000010, 0xb1a0b01d,
1201 0x0000000b, 0x2fdf0002, 0x00000000, 0x2c200000, 0x00000008, 0x2c8000b0,
1202 0x00000008, 0x2d000008, 0x00000010, 0x91d40000, 0x00000008, 0x2d800150,
1203 0x00000000, 0x00000000, 0x00000010, 0x205f0000, 0x00000008, 0x2c800000,
1204 0x00000008, 0x2d000000, 0x00000008, 0x2d800108, 0x00000000, 0x00000000,
1205 0x00000010, 0x91de0000, 0x0000000f, 0x47600008, 0x00000000, 0x060e0000,
1206 0x00000010, 0x001f0000, 0x00000000, 0x0f580000, 0x00000010, 0x91de0000,
1207 0x00000000, 0x0a640000, 0x00000000, 0x0ae50000, 0x00000000, 0x0b670000,
1208 0x00000000, 0x0d620000, 0x00000000, 0x0ce71800, 0x00000009, 0x0c99ffff,
1209 0x00000004, 0xcc993400, 0x00000010, 0xb1963220, 0x00000008, 0x0f800000,
1210 0x00000018, 0x8000001e, 0x0000000f, 0x47600008, 0x0000000b, 0x2fdf0002,
1211 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008, 0x00000010, 0x91d40000,
1212 0x00000008, 0x2d80012c, 0x0000000f, 0x060e0001, 0x00000010, 0x001f0000,
1213 0x00000000, 0x0f580000, 0x00000010, 0x91de0000, 0x00000000, 0x0a640000,
1214 0x00000000, 0x0ae50000, 0x00000000, 0x0b670000, 0x00000000, 0x0d620000,
1215 0x00000000, 0x02630000, 0x0000000f, 0x47620010, 0x00000000, 0x0ce71800,
1216 0x0000000b, 0x2fdf0002, 0x00000000, 0x311a0000, 0x00000000, 0x31840000,
1217 0x0000000b, 0xc20000ff, 0x00000002, 0x42040000, 0x00000001, 0x31620800,
1218 0x0000000f, 0x020e0010, 0x00000002, 0x31620800, 0x00000009, 0x0c99ffff,
1219 0x00000004, 0xcc993400, 0x00000010, 0xb1963202, 0x00000008, 0x0f800000,
1220 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, 0x0000000c, 0x61420006,
1221 0x00000008, 0x22000008, 0x00000000, 0x2adf0000, 0x00000008, 0x2a000004,
1222 0x00000018, 0x8000ff42, 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008,
1223 0x00000010, 0x91a0b008, 0x00000010, 0x91d40000, 0x0000000c, 0x31620018,
1224 0x00000008, 0x2d800001, 0x00000000, 0x00000000, 0x00000010, 0x91de0000,
1225 0x00000008, 0xac000001, 0x00000018, 0x8000000e, 0x00000000, 0x0380b000,
1226 0x0000000b, 0x2fdf0002, 0x00000000, 0x2c004000, 0x00000010, 0x91d40000,
1227 0x00000008, 0x2d800101, 0x00000000, 0x00000000, 0x00000010, 0x91de0000,
1228 0x0000000c, 0x31620018, 0x00000008, 0x2d800001, 0x00000000, 0x00000000,
1229 0x00000010, 0x91de0000, 0x0000000b, 0x2fdf0002, 0x00000000, 0x2c000e00,
1230 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, 0x00000008, 0x2a000007,
1231 0x00000018, 0x8000ff27, 0x00000010, 0xb1a0b016, 0x0000000b, 0x2fdf0002,
1232 0x00000000, 0x03d80000, 0x00000000, 0x2c200000, 0x00000008, 0x2c8000b0,
1233 0x00000008, 0x2d000008, 0x00000010, 0x91d40000, 0x00000008, 0x2d800150,
1234 0x00000000, 0x00000000, 0x00000010, 0x205f0000, 0x00000008, 0x2c800000,
1235 0x00000008, 0x2d000000, 0x00000008, 0x2d800108, 0x00000008, 0x07000001,
1236 0x00000010, 0xb5de1c00, 0x00000010, 0x2c620002, 0x00000018, 0x8000000a,
1237 0x0000000b, 0x2fdf0002, 0x00000000, 0x2c070000, 0x0000000c, 0x1f800001,
1238 0x00000010, 0x91de0000, 0x00000018, 0x8000ff11, 0x00000008, 0x2c8000b0,
1239 0x00000008, 0x2d000008, 0x00000010, 0x91d40000, 0x00000008, 0x2d800108,
1240 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, 0x00000010, 0x91de0000,
1241 0x00000000, 0x2adf0000, 0x00000008, 0x2a00000a, 0x00000018, 0x8000ff07,
1242 0x00000000, 0x82265600, 0x0000000f, 0x47220008, 0x00000009, 0x070e000f,
1243 0x00000008, 0x070e0008, 0x00000008, 0x02800001, 0x00000007, 0x02851c00,
1244 0x00000008, 0x82850001, 0x00000000, 0x02840a00, 0x00000007, 0x42851c00,
1245 0x00000003, 0xc3aa5200, 0x00000000, 0x03b10e00, 0x00000010, 0x001f0000,
1246 0x0000000f, 0x0f280007, 0x00000007, 0x4b071c00, 0x00000000, 0x00000000,
1247 0x0000000f, 0x0a960003, 0x00000000, 0x0a955c00, 0x00000000, 0x4a005a00,
1248 0x00000000, 0x0c960a00, 0x00000009, 0x0c99ffff, 0x00000008, 0x0d00ffff,
1249 0x00000010, 0xb1963202, 0x00000008, 0x0f800005, 0x00000010, 0x00220020,
1250 0x00000000, 0x02a70000, 0x00000010, 0xb1850002, 0x00000008, 0x82850200,
1251 0x00000000, 0x02000000, 0x00000000, 0x03a60000, 0x00000018, 0x8000004e,
1252 0x00000000, 0x072b0000, 0x00000001, 0x878c1c00, 0x00000000, 0x870e1e00,
1253 0x00000000, 0x860c1e00, 0x00000000, 0x03061e00, 0x00000010, 0xb18e0003,
1254 0x00000018, 0x80000047, 0x00000018, 0x8000fffa, 0x00000010, 0x918c0003,
1255 0x00000010, 0xb1870002, 0x00000018, 0x80000043, 0x00000010, 0x91d40000,
1256 0x0000000c, 0x29800001, 0x00000000, 0x2a860000, 0x00000000, 0x230c0000,
1257 0x00000000, 0x2b070000, 0x00000010, 0xb187000e, 0x00000008, 0x2a000008,
1258 0x00000018, 0x8000003b, 0x00000010, 0x91d40000, 0x00000000, 0x28d18c00,
1259 0x00000000, 0x2a860000, 0x00000000, 0x230c0000, 0x00000000, 0x2b070000,
1260 0x00000018, 0x8000fff8, 0x00000010, 0x91d40000, 0x0000000c, 0x29800001,
1261 0x00000000, 0x2aab0000, 0x00000000, 0xa3265600, 0x00000000, 0x2b000000,
1262 0x0000000c, 0x1f800001, 0x00000008, 0x2a000008, 0x00000018, 0x8000fec8,
1263 0x00000010, 0x91d40000, 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001,
1264 0x00000008, 0x2a000009, 0x00000018, 0x8000fec3, 0x00000010, 0x91d40000,
1265 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, 0x00000000, 0x29420000,
1266 0x00000008, 0x2a000002, 0x00000018, 0x8000febd, 0x00000018, 0x8000febc,
1267 0x00000010, 0xb1bcb016, 0x0000000b, 0x2fdf0002, 0x00000000, 0x03d80000,
1268 0x00000000, 0x2c3c0000, 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008,
1269 0x00000010, 0x91d40000, 0x00000008, 0x2d800150, 0x00000000, 0x00000000,
1270 0x00000010, 0x205f0000, 0x00000008, 0x2c800000, 0x00000008, 0x2d000000,
1271 0x00000008, 0x2d800108, 0x00000008, 0x07000001, 0x00000010, 0xb5de1c00,
1272 0x00000010, 0x2c620002, 0x00000018, 0x8000000a, 0x0000000b, 0x2fdf0002,
1273 0x00000000, 0x2c070000, 0x0000000c, 0x1f800000, 0x00000010, 0x91de0000,
1274 0x00000018, 0x8000fea6, 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008,
1275 0x00000010, 0x91d40000, 0x00000008, 0x2d800108, 0x0000000c, 0x29800000,
1276 0x0000000c, 0x1f800000, 0x00000010, 0x91de0000, 0x00000000, 0x2adf0000,
1277 0x00000008, 0x2a000006, 0x00000018, 0x8000fe9c, 0x00000008, 0x03050004,
1278 0x00000006, 0x83040c00, 0x00000008, 0x02850200, 0x00000000, 0x86050c00,
1279 0x00000001, 0x860c0e00, 0x00000008, 0x02040004, 0x00000000, 0x02041800,
1280 0x00000000, 0x83871800, 0x00000018, 0x00020000 };
1281
1282static u32 bnx2_rv2p_proc2[] = {
1283 0x00000000, 0x2a000000, 0x00000010, 0xb1d40000, 0x00000008, 0x02540003,
1284 0x00000018, 0x00040000, 0x00000018, 0x8000000a, 0x00000018, 0x8000000a,
1285 0x00000018, 0x8000000e, 0x00000018, 0x80000056, 0x00000018, 0x800001b9,
1286 0x00000018, 0x800001e1, 0x00000018, 0x8000019b, 0x00000018, 0x800001f9,
1287 0x00000018, 0x8000019f, 0x00000018, 0x800001a6, 0x00000018, 0x80000000,
1288 0x0000000c, 0x29800001, 0x00000000, 0x2a000000, 0x0000000c, 0x29800000,
1289 0x00000010, 0x20530000, 0x00000018, 0x8000ffee, 0x0000000c, 0x29800001,
1290 0x00000010, 0x91de0000, 0x00000010, 0x001f0000, 0x00000000, 0x2f80aa00,
1291 0x00000000, 0x2a000000, 0x00000000, 0x0d610000, 0x00000000, 0x03620000,
1292 0x00000000, 0x2c400000, 0x00000000, 0x02638c00, 0x00000000, 0x26460000,
1293 0x00000010, 0x00420002, 0x00000008, 0x02040012, 0x00000010, 0xb9060836,
1294 0x00000000, 0x0f580000, 0x00000000, 0x0a640000, 0x00000000, 0x0ae50000,
1295 0x00000000, 0x0b660000, 0x00000000, 0x0c000000, 0x00000000, 0x0b800000,
1296 0x00000010, 0x00420009, 0x00000008, 0x0cc60012, 0x00000008, 0x0f800003,
1297 0x00000000, 0x00000000, 0x00000010, 0x009f0000, 0x00000008, 0x27110012,
1298 0x00000000, 0x66900000, 0x00000008, 0xa31b0012, 0x00000018, 0x80000008,
1299 0x00000000, 0x0cc60000, 0x00000008, 0x0f800003, 0x00000000, 0x00000000,
1300 0x00000010, 0x009f0000, 0x00000000, 0x27110000, 0x00000000, 0x66900000,
1301 0x00000000, 0x231b0000, 0x00000010, 0xb197320e, 0x00000000, 0x25960000,
1302 0x00000000, 0x021b0000, 0x00000010, 0x001f0000, 0x00000008, 0x0f800003,
1303 0x0000000c, 0x29800000, 0x00000010, 0x20530000, 0x00000000, 0x22c50800,
1304 0x00000010, 0x009f0000, 0x00000000, 0x27002200, 0x00000000, 0x26802000,
1305 0x00000000, 0x231b0000, 0x0000000c, 0x69520001, 0x00000018, 0x8000fff3,
1306 0x00000010, 0x01130002, 0x00000010, 0xb1980003, 0x00000010, 0x001f0000,
1307 0x00000008, 0x0f800004, 0x00000008, 0x22000003, 0x00000008, 0x2c80000c,
1308 0x00000008, 0x2d00000c, 0x00000010, 0x009f0000, 0x00000000, 0x25960000,
1309 0x0000000c, 0x29800000, 0x00000000, 0x32140000, 0x00000000, 0x32950000,
1310 0x00000000, 0x33160000, 0x00000000, 0x31e32e00, 0x00000008, 0x2d800010,
1311 0x00000010, 0x20530000, 0x00000018, 0x8000ffac, 0x00000000, 0x23000000,
1312 0x00000000, 0x25e60000, 0x00000008, 0x2200000b, 0x0000000c, 0x69520000,
1313 0x0000000c, 0x29800000, 0x00000010, 0x20530000, 0x00000018, 0x8000ffa5,
1314 0x0000000c, 0x29800001, 0x00000010, 0x91de0000, 0x00000000, 0x2fd50000,
1315 0x00000010, 0x001f0000, 0x00000000, 0x02700000, 0x00000000, 0x0d620000,
1316 0x00000000, 0xbb630800, 0x00000000, 0x2a000000, 0x00000009, 0x076000ff,
1317 0x0000000f, 0x2c0e0007, 0x00000008, 0x2c800000, 0x00000008, 0x2d000064,
1318 0x00000008, 0x2d80011c, 0x00000009, 0x06420002, 0x0000000c, 0x61420001,
1319 0x00000000, 0x0f400000, 0x00000000, 0x02d08c00, 0x00000000, 0x23000000,
1320 0x00000004, 0x826da000, 0x00000000, 0x8304a000, 0x00000000, 0x22c50c00,
1321 0x00000000, 0x03760000, 0x00000004, 0x83860a00, 0x00000000, 0x83870c00,
1322 0x00000010, 0x91de0000, 0x00000000, 0x037c0000, 0x00000000, 0x837b0c00,
1323 0x00000001, 0x83060e00, 0x00000000, 0x83870c00, 0x00000000, 0x82850e00,
1324 0x00000010, 0xb1860016, 0x0000000f, 0x47610018, 0x00000000, 0x068e0000,
1325 0x0000000f, 0x47670010, 0x0000000f, 0x47e20010, 0x00000000, 0x870e1e00,
1326 0x00000010, 0xb70e1a10, 0x00000010, 0x0ce7000e, 0x00000008, 0x22000009,
1327 0x00000000, 0x286d0000, 0x0000000f, 0x65680010, 0x00000003, 0xf66c9400,
1328 0x00000010, 0xb972a003, 0x0000000c, 0x73e70019, 0x0000000c, 0x21420004,
1329 0x00000018, 0x8000023f, 0x00000000, 0x37ed0000, 0x0000000c, 0x73e7001a,
1330 0x00000010, 0x20530000, 0x00000008, 0x22000008, 0x0000000c, 0x61420004,
1331 0x00000000, 0x02f60000, 0x00000004, 0x82840a00, 0x00000010, 0xb1840a2b,
1332 0x00000010, 0x2d67000a, 0x00000010, 0xb96d0804, 0x00000004, 0xb6ed0a00,
1333 0x00000000, 0x37ed0000, 0x00000018, 0x80000029, 0x0000000c, 0x61420000,
1334 0x00000000, 0x37040000, 0x00000000, 0x37850000, 0x0000000c, 0x33e7001a,
1335 0x00000018, 0x80000024, 0x00000010, 0xb96d0809, 0x00000004, 0xb6ed0a00,
1336 0x00000000, 0x036d0000, 0x00000004, 0xb76e0c00, 0x00000010, 0x91ee0c1f,
1337 0x0000000c, 0x73e7001a, 0x00000004, 0xb6ef0c00, 0x00000000, 0x37ed0000,
1338 0x00000018, 0x8000001b, 0x0000000c, 0x61420000, 0x00000010, 0xb7ee0a05,
1339 0x00000010, 0xb96f0815, 0x00000003, 0xb76e0800, 0x00000004, 0xb7ef0a00,
1340 0x00000018, 0x80000015, 0x00000010, 0x0ce7000c, 0x00000008, 0x22000009,
1341 0x00000000, 0x286d0000, 0x0000000f, 0x65680010, 0x00000003, 0xf66c9400,
1342 0x00000010, 0xb972a003, 0x0000000c, 0x73e70019, 0x0000000c, 0x21420004,
1343 0x00000018, 0x80000215, 0x00000010, 0x20530000, 0x00000008, 0x22000008,
1344 0x0000000c, 0x61420004, 0x00000000, 0x37040000, 0x00000000, 0x37850000,
1345 0x00000000, 0x036d0000, 0x00000003, 0xb8f10c00, 0x00000018, 0x80000004,
1346 0x00000000, 0x02840000, 0x00000002, 0x21421800, 0x0000000c, 0x61420000,
1347 0x00000000, 0x286d0000, 0x0000000f, 0x65ed0010, 0x00000009, 0x266dffff,
1348 0x00000000, 0x23000000, 0x00000010, 0xb1840a3d, 0x00000010, 0x01420002,
1349 0x00000004, 0xb8f10a00, 0x00000003, 0x83760a00, 0x00000010, 0xb8040c39,
1350 0x00000010, 0xb7e6080a, 0x00000000, 0x0a640000, 0x00000000, 0x0ae50000,
1351 0x00000009, 0x0c68ffff, 0x00000009, 0x0b67ffff, 0x00000000, 0x0be60000,
1352 0x00000000, 0x0c840000, 0x00000010, 0xb197320c, 0x00000008, 0x0f800002,
1353 0x00000018, 0x8000000a, 0x00000000, 0x0a6a0000, 0x00000000, 0x0aeb0000,
1354 0x00000000, 0x0c000000, 0x00000009, 0x0b6cffff, 0x00000000, 0x0be90000,
1355 0x00000000, 0x0c840000, 0x00000010, 0xb1973203, 0x00000008, 0x0f800002,
1356 0x00000018, 0x80000001, 0x00000010, 0x001f0000, 0x00000000, 0x0c860000,
1357 0x00000000, 0x06980000, 0x00000008, 0x0f800003, 0x00000000, 0x00000000,
1358 0x00000010, 0x009f0000, 0x00000010, 0xb1973210, 0x00000000, 0x231b0000,
1359 0x00000000, 0x02043600, 0x00000003, 0x8384a000, 0x0000000f, 0x65870010,
1360 0x00000009, 0x2607ffff, 0x00000000, 0x27111a00, 0x00000000, 0x66900000,
1361 0x0000000c, 0x29000000, 0x00000018, 0x800001de, 0x00000000, 0x06980000,
1362 0x00000010, 0x20530000, 0x00000000, 0x22c58c00, 0x00000010, 0x001f0000,
1363 0x00000008, 0x0f800003, 0x00000018, 0x8000fff0, 0x00000000, 0x02043600,
1364 0x00000000, 0x231b0000, 0x00000003, 0x8384a000, 0x0000000f, 0x65870010,
1365 0x00000009, 0x2607ffff, 0x00000000, 0x27111a00, 0x00000000, 0x66900000,
1366 0x0000000c, 0x29000000, 0x00000010, 0x91840a02, 0x00000002, 0x21421800,
1367 0x00000000, 0x32140000, 0x00000000, 0x32950000, 0x00000005, 0x73e72c00,
1368 0x00000005, 0x74683000, 0x00000000, 0x33170000, 0x00000018, 0x80000138,
1369 0x00000010, 0x91c60004, 0x00000008, 0x07000004, 0x00000010, 0xb1c41c02,
1370 0x00000010, 0x91840a04, 0x00000018, 0x800001c3, 0x00000010, 0x20530000,
1371 0x00000000, 0x22c58c00, 0x00000010, 0xb1840a8e, 0x0000000c, 0x21420006,
1372 0x00000010, 0x0ce7001a, 0x0000000f, 0x43680010, 0x00000000, 0x03f30c00,
1373 0x00000010, 0x91870850, 0x0000000f, 0x46ec0010, 0x00000010, 0xb68d0c4e,
1374 0x00000000, 0x838d0c00, 0x00000000, 0xa3050800, 0x00000001, 0xa3460e00,
1375 0x00000000, 0x02048c00, 0x00000010, 0x91840a02, 0x00000002, 0x21421800,
1376 0x00000010, 0x001f0000, 0x00000008, 0x22000008, 0x00000003, 0x8384a000,
1377 0x0000000f, 0x65870010, 0x00000009, 0x2607ffff, 0x00000000, 0x27750c00,
1378 0x00000000, 0x66f40000, 0x0000000c, 0x29000000, 0x00000018, 0x800001aa,
1379 0x00000000, 0x03068c00, 0x00000003, 0xf4680c00, 0x00000010, 0x20530000,
1380 0x00000000, 0x22c58c00, 0x00000018, 0x8000ffe5, 0x00000000, 0x39760000,
1381 0x00000000, 0x39840000, 0x0000000c, 0x33e70019, 0x00000010, 0x001f0000,
1382 0x00000000, 0x031e0000, 0x00000000, 0x0760fe00, 0x0000000f, 0x0f0e0007,
1383 0x00000000, 0x83850800, 0x00000000, 0x0a7d0000, 0x00000000, 0x0afe0000,
1384 0x00000000, 0x0b7f0000, 0x00000000, 0x0d7a0000, 0x00000000, 0x0c000000,
1385 0x00000000, 0x0bfc0000, 0x00000000, 0x0c970e00, 0x00000008, 0x0f800003,
1386 0x0000000f, 0x47670010, 0x00000008, 0x070e0001, 0x0000000b, 0xc38000ff,
1387 0x00000002, 0x43870000, 0x00000001, 0x33e70e00, 0x0000000f, 0x038e0010,
1388 0x00000002, 0x33e70e00, 0x00000000, 0x28f30000, 0x00000010, 0x009f0000,
1389 0x00000000, 0x02043600, 0x00000010, 0x91840a02, 0x00000002, 0x21421800,
1390 0x00000008, 0x22000006, 0x00000000, 0x231b0000, 0x00000000, 0x23ff0000,
1391 0x00000000, 0x241b0000, 0x00000003, 0x8384a000, 0x0000000f, 0x65870010,
1392 0x00000009, 0x2607ffff, 0x00000000, 0x27110000, 0x00000000, 0x26900000,
1393 0x0000000c, 0x29000000, 0x00000018, 0x8000017e, 0x00000003, 0xf4683600,
1394 0x00000000, 0x3a100000, 0x00000000, 0x3a910000, 0x00000003, 0xf66c2400,
1395 0x00000010, 0x001f0000, 0x00000010, 0xb1923604, 0x00000008, 0x0f800004,
1396 0x00000000, 0x00000000, 0x00000010, 0x009f0000, 0x00000000, 0x3e170000,
1397 0x00000000, 0x3e940000, 0x00000000, 0x3f150000, 0x00000000, 0x3f960000,
1398 0x00000010, 0x001f0000, 0x00000000, 0x0f060000, 0x00000010, 0x20530000,
1399 0x00000000, 0x22c53600, 0x00000018, 0x8000ffac, 0x00000010, 0x001f0000,
1400 0x00000000, 0x031e0000, 0x00000000, 0x83850800, 0x00000009, 0x076000ff,
1401 0x0000000f, 0x0f0e0007, 0x00000000, 0x0c000000, 0x00000000, 0x0a7d0000,
1402 0x00000000, 0x0afe0000, 0x00000000, 0x0b7f0000, 0x00000000, 0x0d7a0000,
1403 0x00000000, 0x0bfc0000, 0x00000000, 0x0c970e00, 0x00000008, 0x0f800003,
1404 0x0000000f, 0x47670010, 0x00000008, 0x070e0001, 0x0000000b, 0xc38000ff,
1405 0x00000002, 0x43870000, 0x00000001, 0x33e70e00, 0x0000000f, 0x038e0010,
1406 0x00000002, 0x33e70e00, 0x00000000, 0x39840000, 0x00000003, 0xb9720800,
1407 0x00000000, 0x28f30000, 0x0000000f, 0x65680010, 0x00000010, 0x009f0000,
1408 0x00000000, 0x02043600, 0x00000010, 0x91840a02, 0x00000002, 0x21421800,
1409 0x00000008, 0x22000007, 0x00000000, 0x231b0000, 0x00000000, 0x23ff0000,
1410 0x00000000, 0x241b0000, 0x00000003, 0x8384a000, 0x0000000f, 0x65870010,
1411 0x00000009, 0x2607ffff, 0x00000000, 0x27110000, 0x00000000, 0x26900000,
1412 0x0000000c, 0x29000000, 0x00000018, 0x80000145, 0x00000003, 0xf4683600,
1413 0x00000000, 0x3a100000, 0x00000000, 0x3a910000, 0x00000003, 0xf66c2400,
1414 0x00000010, 0x001f0000, 0x00000010, 0xb1923604, 0x00000008, 0x0f800004,
1415 0x00000000, 0x00000000, 0x00000010, 0x009f0000, 0x00000000, 0x3e170000,
1416 0x00000000, 0x3e940000, 0x00000000, 0x3f150000, 0x00000000, 0x3f960000,
1417 0x00000010, 0x001f0000, 0x00000000, 0x0f060000, 0x00000010, 0x20530000,
1418 0x00000000, 0x22c53600, 0x00000018, 0x8000ff73, 0x00000010, 0x0ce70005,
1419 0x00000008, 0x2c80000c, 0x00000008, 0x2d000070, 0x00000008, 0x2d800010,
1420 0x00000000, 0x00000000, 0x00000010, 0x205f0000, 0x00000018, 0x8000011d,
1421 0x00000000, 0x2c1e0000, 0x00000008, 0x2c8000b8, 0x00000008, 0x2d000010,
1422 0x00000008, 0x2d800048, 0x00000000, 0x00000000, 0x00000010, 0x91de0000,
1423 0x00000018, 0x8000fe5d, 0x0000000c, 0x29800001, 0x00000000, 0x2a000000,
1424 0x00000010, 0x001f0000, 0x00000000, 0x0f008000, 0x00000008, 0x0f800007,
1425 0x00000018, 0x80000006, 0x0000000c, 0x29800001, 0x00000000, 0x2a000000,
1426 0x00000010, 0x001f0000, 0x0000000f, 0x0f470007, 0x00000008, 0x0f800008,
1427 0x00000018, 0x80000119, 0x00000010, 0x20530000, 0x00000018, 0x8000fe4f,
1428 0x0000000c, 0x29800001, 0x00000010, 0x91de0000, 0x00000000, 0x2fd50000,
1429 0x00000000, 0x2a000000, 0x00000009, 0x0261ffff, 0x0000000d, 0x70e10001,
1430 0x00000018, 0x80000101, 0x00000000, 0x2c400000, 0x00000008, 0x2c8000c4,
1431 0x00000008, 0x2d00001c, 0x00000008, 0x2d800001, 0x00000005, 0x70e10800,
1432 0x00000010, 0x91de0000, 0x00000018, 0x8000fe41, 0x0000000c, 0x29800001,
1433 0x00000010, 0x91de0000, 0x00000000, 0x2fd50000, 0x00000010, 0x001f0000,
1434 0x00000000, 0x02700000, 0x00000000, 0x0d620000, 0x00000000, 0xbb630800,
1435 0x00000000, 0x2a000000, 0x00000000, 0x0f400000, 0x00000000, 0x2c400000,
1436 0x0000000c, 0x73e7001b, 0x00000010, 0x0ce7000e, 0x00000000, 0x286d0000,
1437 0x0000000f, 0x65ed0010, 0x00000009, 0x266dffff, 0x00000018, 0x80000069,
1438 0x00000008, 0x02000004, 0x00000010, 0x91c40803, 0x00000018, 0x800000f6,
1439 0x00000010, 0x20530000, 0x00000018, 0x800000e5, 0x00000008, 0x2c8000b8,
1440 0x00000008, 0x2d000010, 0x00000008, 0x2d800048, 0x00000018, 0x80000005,
1441 0x00000008, 0x2c8000c4, 0x00000008, 0x2d00001c, 0x00000008, 0x2d800001,
1442 0x00000000, 0x00000000, 0x00000010, 0x205f0000, 0x00000008, 0x2c800048,
1443 0x00000008, 0x2d000068, 0x00000008, 0x2d800104, 0x00000000, 0x00000000,
1444 0x00000010, 0x91de0000, 0x00000000, 0x27f60000, 0x00000010, 0xb87a9e04,
1445 0x00000008, 0x2200000d, 0x00000018, 0x800000e2, 0x00000010, 0x20530000,
1446 0x00000018, 0x8000fe18, 0x0000000c, 0x29800001, 0x00000010, 0x91de0000,
1447 0x00000000, 0x2fd50000, 0x00000010, 0x001f0000, 0x00000000, 0x02700000,
1448 0x00000000, 0x0d620000, 0x00000000, 0xbb630800, 0x00000000, 0x2a000000,
1449 0x00000010, 0x0e670011, 0x00000000, 0x286d0000, 0x0000000f, 0x65ed0010,
1450 0x00000009, 0x266dffff, 0x00000004, 0xb8f1a000, 0x00000000, 0x0f400000,
1451 0x0000000c, 0x73e7001c, 0x00000018, 0x80000040, 0x00000008, 0x02000004,
1452 0x00000010, 0x91c40802, 0x00000018, 0x800000cd, 0x00000000, 0x2c1e0000,
1453 0x00000008, 0x2c8000b8, 0x00000008, 0x2d000010, 0x00000008, 0x2d800048,
1454 0x00000010, 0x20530000, 0x00000010, 0x91de0000, 0x00000018, 0x8000fdfe,
1455 0x0000000c, 0x29800001, 0x00000000, 0x03550000, 0x00000000, 0x06460000,
1456 0x00000000, 0x03d60000, 0x00000000, 0x2a000000, 0x0000000f, 0x0f480007,
1457 0x00000010, 0xb18c0027, 0x0000000f, 0x47420008, 0x00000009, 0x070e000f,
1458 0x00000008, 0x070e0008, 0x00000010, 0x001f0000, 0x00000008, 0x09000001,
1459 0x00000007, 0x09121c00, 0x00000003, 0xcbca9200, 0x00000000, 0x0b97a200,
1460 0x00000007, 0x4b171c00, 0x0000000f, 0x0a960003, 0x00000000, 0x0a959c00,
1461 0x00000000, 0x4a009a00, 0x00000008, 0x82120001, 0x00000001, 0x0c170800,
1462 0x00000000, 0x02180000, 0x00000000, 0x0c971800, 0x00000008, 0x0d00ffff,
1463 0x00000008, 0x0f800006, 0x0000000c, 0x29000000, 0x00000008, 0x22000001,
1464 0x00000000, 0x22c50c00, 0x00000010, 0x009f0000, 0x00000010, 0xb197320b,
1465 0x00000000, 0x231b0000, 0x00000000, 0x27110800, 0x00000000, 0x66900000,
1466 0x00000018, 0x800000a4, 0x00000000, 0x02180000, 0x00000010, 0x20530000,
1467 0x00000000, 0x22c53600, 0x00000010, 0x001f0000, 0x00000008, 0x0f800006,
1468 0x00000018, 0x8000fff5, 0x00000010, 0x91870002, 0x00000008, 0x2200000a,
1469 0x00000000, 0x231b0000, 0x00000000, 0x27110800, 0x00000000, 0x66900000,
1470 0x00000018, 0x80000098, 0x00000008, 0x0200000a, 0x00000010, 0x91c40804,
1471 0x00000010, 0x02c20003, 0x00000010, 0x001f0000, 0x00000008, 0x0f800008,
1472 0x00000010, 0x20530000, 0x00000018, 0x8000fdc9, 0x00000000, 0x06820000,
1473 0x00000010, 0x001f0000, 0x00000010, 0x0ce70028, 0x00000000, 0x03720000,
1474 0x00000000, 0xa8760c00, 0x00000000, 0x0cf60000, 0x00000010, 0xb8723224,
1475 0x00000000, 0x03440000, 0x00000008, 0x22000010, 0x00000000, 0x03ca0000,
1476 0x0000000f, 0x65680010, 0x00000000, 0x0bcf0000, 0x00000000, 0x27f20000,
1477 0x00000010, 0xb7ef3203, 0x0000000c, 0x21420004, 0x0000000c, 0x73e70019,
1478 0x00000000, 0x07520000, 0x00000000, 0x29000000, 0x00000018, 0x8000007e,
1479 0x00000004, 0xb9723200, 0x00000010, 0x20530000, 0x00000000, 0x22060000,
1480 0x0000000c, 0x61420004, 0x00000000, 0x25070000, 0x00000000, 0x27970000,
1481 0x00000000, 0x290e0000, 0x00000010, 0x0ce70010, 0x00000010, 0xb873320f,
1482 0x0000000f, 0x436c0010, 0x00000000, 0x03f30c00, 0x00000000, 0x03f30000,
1483 0x00000000, 0x83990e00, 0x00000001, 0x83860e00, 0x00000000, 0x83060e00,
1484 0x00000003, 0xf66c0c00, 0x00000000, 0x39f30e00, 0x00000000, 0x3af50e00,
1485 0x00000000, 0x7a740000, 0x0000000f, 0x43680010, 0x00000001, 0x83860e00,
1486 0x00000000, 0x83060e00, 0x00000003, 0xf4680c00, 0x00000000, 0x286d0000,
1487 0x00000000, 0x03690000, 0x00000010, 0xb1f60c54, 0x00000000, 0x0a6a0000,
1488 0x00000000, 0x0aeb0000, 0x00000009, 0x0b6cffff, 0x00000000, 0x0c000000,
1489 0x00000000, 0x0be90000, 0x00000003, 0x8cf6a000, 0x0000000c, 0x09800002,
1490 0x00000010, 0x009f0000, 0x00000010, 0xb8173209, 0x00000000, 0x35140000,
1491 0x00000000, 0x35950000, 0x00000005, 0x766c2c00, 0x00000000, 0x34970000,
1492 0x00000004, 0xb8f12e00, 0x00000010, 0x001f0000, 0x00000008, 0x0f800004,
1493 0x00000018, 0x8000fff7, 0x00000000, 0x03e90000, 0x00000010, 0xb8f6a01a,
1494 0x00000010, 0x20130019, 0x00000010, 0xb1f10e18, 0x00000000, 0x83973200,
1495 0x00000000, 0x38700e00, 0x00000000, 0xbb760e00, 0x00000000, 0x37d00000,
1496 0x0000000c, 0x73e7001a, 0x00000003, 0xb8f1a000, 0x00000000, 0x32140000,
1497 0x00000000, 0x32950000, 0x00000005, 0x73e72c00, 0x00000000, 0x33190000,
1498 0x00000005, 0x74680000, 0x00000010, 0x0ce7000d, 0x00000008, 0x22000009,
1499 0x00000000, 0x07520000, 0x00000000, 0x29000000, 0x0000000c, 0x73e70019,
1500 0x0000000f, 0x65680010, 0x0000000c, 0x21420004, 0x00000018, 0x8000003c,
1501 0x00000010, 0x20530000, 0x0000000c, 0x61420004, 0x00000000, 0x290e0000,
1502 0x00000018, 0x80000002, 0x00000010, 0x91973206, 0x00000000, 0x35140000,
1503 0x00000000, 0x35950000, 0x00000005, 0x766c2c00, 0x00000000, 0x34990000,
1504 0x00000004, 0xb8f13200, 0x00000000, 0x83690c00, 0x00000010, 0xb1860013,
1505 0x00000000, 0x28e90000, 0x00000008, 0x22000004, 0x00000000, 0x23ec0000,
1506 0x00000000, 0x03690000, 0x00000010, 0xb8660c07, 0x00000009, 0x036cffff,
1507 0x00000000, 0x326a0000, 0x00000000, 0x32eb0000, 0x00000005, 0x73e70c00,
1508 0x00000000, 0x33690000, 0x00000005, 0x74680000, 0x0000000c, 0x73e7001c,
1509 0x00000000, 0x03690000, 0x00000010, 0xb1f60c12, 0x00000010, 0xb1d00c11,
1510 0x0000000c, 0x21420005, 0x0000000c, 0x33e7001c, 0x00000018, 0x8000000e,
1511 0x00000010, 0x2e67000d, 0x00000000, 0x03690000, 0x00000010, 0xb1f60c0b,
1512 0x00000010, 0xb1d00c0a, 0x00000000, 0x03440000, 0x00000008, 0x2200000c,
1513 0x00000000, 0x07520000, 0x00000000, 0x29000000, 0x00000018, 0x80000015,
1514 0x0000000c, 0x33e7001c, 0x00000010, 0x20530000, 0x00000000, 0x22060000,
1515 0x00000000, 0x290e0000, 0x00000018, 0x000d0000, 0x00000000, 0x06820000,
1516 0x00000010, 0x2de7000d, 0x00000010, 0x0ce7000c, 0x00000000, 0x27f20000,
1517 0x00000010, 0xb96d9e0a, 0x00000000, 0xa86d9e00, 0x00000009, 0x0361ffff,
1518 0x00000010, 0xb7500c07, 0x00000008, 0x2200000f, 0x0000000f, 0x65680010,
1519 0x00000000, 0x29000000, 0x00000018, 0x80000004, 0x0000000c, 0x33e7001b,
1520 0x00000010, 0x20530000, 0x00000018, 0x000d0000, 0x00000000, 0x2b820000,
1521 0x00000010, 0x20d2002f, 0x00000010, 0x0052002e, 0x00000009, 0x054e0007,
1522 0x00000010, 0xb18a002c, 0x00000000, 0x050a8c00, 0x00000008, 0x850a0008,
1523 0x00000010, 0x918a0029, 0x00000003, 0xc5008800, 0x00000008, 0xa3460001,
1524 0x00000010, 0xb1c60007, 0x00000008, 0x22000001, 0x0000000c, 0x29800000,
1525 0x00000010, 0x20530000, 0x00000000, 0x274e8c00, 0x00000000, 0x66cd0000,
1526 0x00000000, 0x22c58c00, 0x00000008, 0x22000014, 0x00000003, 0x22c58e00,
1527 0x00000003, 0x23c58e00, 0x00000003, 0x22c58e00, 0x00000003, 0x26cd9e00,
1528 0x00000003, 0x27cd9e00, 0x00000003, 0x26cd9e00, 0x00000003, 0x274ea000,
1529 0x00000003, 0x284ea000, 0x00000003, 0x274ea000, 0x0000000c, 0x69520000,
1530 0x0000000c, 0x29800000, 0x00000010, 0x20530000, 0x00000003, 0x22c58e00,
1531 0x00000003, 0x23c58e00, 0x00000003, 0x22c58e00, 0x00000003, 0x26cd9e00,
1532 0x00000003, 0x27cd9e00, 0x00000003, 0x26cd9e00, 0x00000003, 0x274ea000,
1533 0x00000003, 0x284ea000, 0x00000003, 0x274ea000, 0x00000000, 0xa2c58c00,
1534 0x00000000, 0xa74e8c00, 0x00000000, 0xe6cd0000, 0x0000000f, 0x620a0010,
1535 0x00000008, 0x23460001, 0x0000000c, 0x29800000, 0x00000010, 0x20530000,
1536 0x0000000c, 0x29520000, 0x00000018, 0x80000002, 0x0000000c, 0x29800000,
1537 0x00000018, 0x00570000 };
1538
1539static int bnx2_TPAT_b06FwReleaseMajor = 0x0;
1540static int bnx2_TPAT_b06FwReleaseMinor = 0x0;
1541static int bnx2_TPAT_b06FwReleaseFix = 0x0;
1542static u32 bnx2_TPAT_b06FwStartAddr = 0x08000858;
1543static u32 bnx2_TPAT_b06FwTextAddr = 0x08000800;
1544static int bnx2_TPAT_b06FwTextLen = 0x1314;
1545static u32 bnx2_TPAT_b06FwDataAddr = 0x08001b40;
1546static int bnx2_TPAT_b06FwDataLen = 0x0;
1547static u32 bnx2_TPAT_b06FwRodataAddr = 0x00000000;
1548static int bnx2_TPAT_b06FwRodataLen = 0x0;
1549static u32 bnx2_TPAT_b06FwBssAddr = 0x08001b90;
1550static int bnx2_TPAT_b06FwBssLen = 0x80;
1551static u32 bnx2_TPAT_b06FwSbssAddr = 0x08001b40;
1552static int bnx2_TPAT_b06FwSbssLen = 0x48;
1553
1554static u32 bnx2_TPAT_b06FwText[(0x1314/4) + 1] = {
1555 0x0a000216, 0x00000000, 0x00000000, 0x0000000d, 0x74706174, 0x20302e36,
1556 0x2e390000, 0x00060901, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1557 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1558 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x10000003,
1559 0x00000000, 0x0000000d, 0x0000000d, 0x3c020800, 0x24421b40, 0x3c030800,
1560 0x24631c10, 0xac400000, 0x0043202b, 0x1480fffd, 0x24420004, 0x3c1d0800,
1561 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100858, 0x3c1c0800, 0x279c1b40,
1562 0x0e00051f, 0x00000000, 0x0000000d, 0x8f820024, 0x27bdffe8, 0xafbf0014,
1563 0x10400004, 0xafb00010, 0x0000000d, 0x00000000, 0x2400015f, 0x8f82001c,
1564 0x8c450008, 0x24030800, 0xaf430178, 0x97430104, 0x3c020008, 0xaf420140,
1565 0x8f820034, 0x30420001, 0x10400006, 0x3070ffff, 0x24020002, 0x2603fffe,
1566 0xa7420146, 0x0a000246, 0xa7430148, 0xa7400146, 0x8f850034, 0x30a20020,
1567 0x0002102b, 0x00021023, 0x30460009, 0x30a30c00, 0x24020400, 0x14620002,
1568 0x34c40001, 0x34c40005, 0xa744014a, 0x3c020800, 0x8c440820, 0x3c030048,
1569 0x24020002, 0x00832025, 0x30a30006, 0x1062000d, 0x2c620003, 0x50400005,
1570 0x24020004, 0x10600012, 0x3c020001, 0x0a000271, 0x00000000, 0x10620007,
1571 0x24020006, 0x1462000f, 0x3c020111, 0x0a000269, 0x00821025, 0x0a000268,
1572 0x3c020101, 0x3c020011, 0x00821025, 0x24030001, 0xaf421000, 0xaf830030,
1573 0x0a000271, 0x00000000, 0x00821025, 0xaf421000, 0xaf800030, 0x00000000,
1574 0x00000000, 0x00000000, 0x00000000, 0x8f830030, 0x1060003f, 0x3c048000,
1575 0x8f421000, 0x00441024, 0x1040fffd, 0x00000000, 0x10600039, 0x00000000,
1576 0x8f421000, 0x3c030020, 0x00431024, 0x10400034, 0x00000000, 0x97421014,
1577 0x14400031, 0x00000000, 0x97421008, 0x8f84001c, 0x24420006, 0x00024082,
1578 0x00081880, 0x00643821, 0x8ce50000, 0x30430003, 0x30420001, 0x10400004,
1579 0x00000000, 0x0000000d, 0x0a0002b0, 0x00081080, 0x5460000f, 0x30a5ffff,
1580 0x3c06ffff, 0x00a62824, 0x0005182b, 0x00a61026, 0x0002102b, 0x00621824,
1581 0x10600004, 0x00000000, 0x0000000d, 0x00000000, 0x240001fc, 0x8ce20000,
1582 0x0a0002af, 0x00462825, 0x0005182b, 0x38a2ffff, 0x0002102b, 0x00621824,
1583 0x10600004, 0x00000000, 0x0000000d, 0x00000000, 0x24000206, 0x8ce20000,
1584 0x3445ffff, 0x00081080, 0x00441021, 0x3c030800, 0xac450000, 0x8c620840,
1585 0x24420001, 0xac620840, 0x8f820008, 0x10400003, 0x00000000, 0x0e000660,
1586 0x00000000, 0x8f840028, 0x02002821, 0x24820008, 0x30421fff, 0x24434000,
1587 0x0343d821, 0x30a30007, 0xaf840018, 0xaf820028, 0xaf420084, 0x10600002,
1588 0x24a20007, 0x3045fff8, 0x8f820044, 0x8f840004, 0x00451821, 0xaf82002c,
1589 0x0064102b, 0xaf830044, 0x14400002, 0x00641023, 0xaf820044, 0x8f840044,
1590 0x34028000, 0x8fbf0014, 0x8fb00010, 0x00821021, 0x03421821, 0x3c021000,
1591 0xaf83001c, 0xaf440080, 0xaf420178, 0x03e00008, 0x27bd0018, 0x8f820024,
1592 0x27bdffe8, 0xafbf0014, 0x10400004, 0xafb00010, 0x0000000d, 0x00000000,
1593 0x24000249, 0x8f85001c, 0x24020001, 0xaf820024, 0x8ca70008, 0xa3800023,
1594 0x8f620004, 0x3c100800, 0x26041b90, 0x00021402, 0xa3820010, 0x304600ff,
1595 0x24c60005, 0x0e00064a, 0x00063082, 0x8f640004, 0x8f430108, 0x3c021000,
1596 0x00621824, 0xa7840020, 0x10600008, 0x00000000, 0x97420104, 0x93830023,
1597 0x2442ffec, 0x34630002, 0xa3830023, 0x0a000304, 0x3045ffff, 0x97420104,
1598 0x2442fff0, 0x3045ffff, 0x8f620004, 0x3042ffff, 0x2c420013, 0x14400004,
1599 0x00000000, 0x93820023, 0x34420001, 0xa3820023, 0x93830023, 0x24020001,
1600 0x10620009, 0x28620002, 0x14400014, 0x24020002, 0x10620012, 0x24020003,
1601 0x1062000a, 0x00000000, 0x0a000325, 0x00000000, 0x8f82001c, 0x8c43000c,
1602 0x3c04ffff, 0x00641824, 0x00651825, 0x0a000325, 0xac43000c, 0x8f82001c,
1603 0x8c430010, 0x3c04ffff, 0x00641824, 0x00651825, 0xac430010, 0x8f620004,
1604 0x3042ffff, 0x24420002, 0x00021083, 0xa3820038, 0x304500ff, 0x8f82001c,
1605 0x3c04ffff, 0x00052880, 0x00a22821, 0x8ca70000, 0x97820020, 0x97430104,
1606 0x00e42024, 0x24420002, 0x00621823, 0x00833825, 0xaca70000, 0x93840038,
1607 0x26061b90, 0x00041080, 0x00461021, 0x90430000, 0x3063000f, 0x00832021,
1608 0xa3840022, 0x308200ff, 0x3c04fff6, 0x24420003, 0x00021080, 0x00461021,
1609 0x8c450000, 0x93830022, 0x8f82001c, 0x3484ffff, 0x00a43824, 0x00031880,
1610 0x00621821, 0xaf850000, 0xac67000c, 0x93820022, 0x93830022, 0x8f84001c,
1611 0x24420003, 0x00021080, 0x00461021, 0x24630004, 0x00031880, 0xac470000,
1612 0x93820022, 0x00661821, 0x94670002, 0x00021080, 0x00441021, 0xac670000,
1613 0x24030010, 0xac470010, 0xa7430140, 0x24030002, 0xa7400142, 0xa7400144,
1614 0xa7430146, 0x97420104, 0x8f840034, 0x24030001, 0x2442fffe, 0x30840006,
1615 0xa7420148, 0x24020002, 0xa743014a, 0x1082000d, 0x2c820003, 0x10400005,
1616 0x24020004, 0x10800011, 0x3c020009, 0x0a000383, 0x00000000, 0x10820007,
1617 0x24020006, 0x1482000d, 0x3c020119, 0x0a00037d, 0x24030001, 0x0a00037c,
1618 0x3c020109, 0x3c020019, 0x24030001, 0xaf421000, 0xaf830030, 0x0a000383,
1619 0x00000000, 0xaf421000, 0xaf800030, 0x00000000, 0x00000000, 0x00000000,
1620 0x00000000, 0x93820010, 0x24030008, 0x8f840030, 0x24420002, 0x30420007,
1621 0x00621823, 0x30630007, 0xaf83000c, 0x10800005, 0x3c038000, 0x8f421000,
1622 0x00431024, 0x1040fffd, 0x00000000, 0x8f820028, 0xaf820018, 0x24420010,
1623 0x30421fff, 0xaf820028, 0xaf420084, 0x97430104, 0x24424000, 0x0342d821,
1624 0x3063ffff, 0x30620007, 0x10400002, 0x24620007, 0x3043fff8, 0x8f820044,
1625 0x8f840004, 0x00431821, 0xaf82002c, 0x0064102b, 0xaf830044, 0x14400002,
1626 0x00641023, 0xaf820044, 0x8f840044, 0x34028000, 0x8fbf0014, 0x8fb00010,
1627 0x00821021, 0x03421821, 0x3c021000, 0xaf83001c, 0xaf440080, 0xaf420178,
1628 0x03e00008, 0x27bd0018, 0x8f820024, 0x27bdffe8, 0xafbf0014, 0x14400004,
1629 0xafb00010, 0x0000000d, 0x00000000, 0x240002db, 0x8f620004, 0x04410009,
1630 0x3c050800, 0x93820022, 0x8f830000, 0x24a41b90, 0xaf800024, 0x24420003,
1631 0x00021080, 0x00441021, 0xac430000, 0x93820038, 0x24a51b90, 0x93860010,
1632 0x3c040001, 0x27700008, 0x24420001, 0x00021080, 0x00451021, 0x8c430000,
1633 0x24c60005, 0x00063082, 0x00641821, 0x02002021, 0x0e00064a, 0xac430000,
1634 0x93840022, 0x3c057fff, 0x8f620004, 0x00042080, 0x00902021, 0x8c830004,
1635 0x34a5ffff, 0x00451024, 0x00621821, 0xac830004, 0x93850038, 0x3c07ffff,
1636 0x93840010, 0x00052880, 0x00b02821, 0x8ca30000, 0x97420104, 0x97860020,
1637 0x00671824, 0x00441021, 0x00461023, 0x3042ffff, 0x00621825, 0xaca30000,
1638 0x93830023, 0x24020001, 0x10620009, 0x28620002, 0x1440001a, 0x24020002,
1639 0x10620018, 0x24020003, 0x1062000d, 0x00000000, 0x0a000411, 0x00000000,
1640 0x93820010, 0x97430104, 0x8e04000c, 0x00621821, 0x2463fff2, 0x3063ffff,
1641 0x00872024, 0x00832025, 0x0a000411, 0xae04000c, 0x93820010, 0x97430104,
1642 0x8e040010, 0x00621821, 0x2463ffee, 0x3063ffff, 0x00872024, 0x00832025,
1643 0xae040010, 0x9783000e, 0x8f840034, 0x2402000a, 0xa7420140, 0xa7430142,
1644 0x93820010, 0xa7420144, 0xa7400146, 0x97430104, 0x30840006, 0x24020001,
1645 0xa7430148, 0xa742014a, 0x24020002, 0x1082000d, 0x2c820003, 0x10400005,
1646 0x24020004, 0x10800011, 0x3c020041, 0x0a000437, 0x00000000, 0x10820007,
1647 0x24020006, 0x1482000d, 0x3c020151, 0x0a000431, 0x24030001, 0x0a000430,
1648 0x3c020141, 0x3c020051, 0x24030001, 0xaf421000, 0xaf830030, 0x0a000437,
1649 0x00000000, 0xaf421000, 0xaf800030, 0x00000000, 0x00000000, 0x00000000,
1650 0x00000000, 0x8f820030, 0x93840010, 0x8f850028, 0x10400005, 0x3c038000,
1651 0x8f421000, 0x00431024, 0x1040fffd, 0x00000000, 0x2483000a, 0x30620007,
1652 0x10400002, 0x24620007, 0x304303f8, 0x00a31021, 0x30421fff, 0xaf850018,
1653 0xaf820028, 0xaf420084, 0x97430104, 0x24424000, 0x0342d821, 0x3063ffff,
1654 0x30620007, 0x10400002, 0x24620007, 0x3043fff8, 0x8f820044, 0x8f840004,
1655 0x00431821, 0xaf82002c, 0x0064102b, 0xaf830044, 0x14400002, 0x00641023,
1656 0xaf820044, 0x8f840044, 0x34028000, 0x8fbf0014, 0x8fb00010, 0x00821021,
1657 0x03421821, 0x3c021000, 0xaf83001c, 0xaf440080, 0xaf420178, 0x03e00008,
1658 0x27bd0018, 0x3c026000, 0x8c444448, 0x3c030800, 0xac64082c, 0x8f620000,
1659 0x97430104, 0x3c048000, 0x3046ffff, 0x3067ffff, 0x8f420178, 0x00441024,
1660 0x1440fffd, 0x2402000a, 0x30c30007, 0xa7420140, 0x24020008, 0x00431023,
1661 0x30420007, 0x24c3fffe, 0xa7420142, 0xa7430144, 0xa7400146, 0xa7470148,
1662 0x8f420108, 0x3c036000, 0x8f850034, 0x30420020, 0x0002102b, 0x00021023,
1663 0x30420009, 0x34420001, 0xa742014a, 0x8c644448, 0x3c020800, 0x30a50006,
1664 0xac440830, 0x24020002, 0x10a2000d, 0x2ca20003, 0x10400005, 0x24020004,
1665 0x10a00011, 0x3c020041, 0x0a0004a8, 0x00000000, 0x10a20007, 0x24020006,
1666 0x14a2000d, 0x3c020151, 0x0a0004a2, 0x24030001, 0x0a0004a1, 0x3c020141,
1667 0x3c020051, 0x24030001, 0xaf421000, 0xaf830030, 0x0a0004a8, 0x00000000,
1668 0xaf421000, 0xaf800030, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1669 0x8f820030, 0x24c30008, 0x10400006, 0x30e6ffff, 0x3c048000, 0x8f421000,
1670 0x00441024, 0x1040fffd, 0x00000000, 0x3c026000, 0x8c444448, 0x3065ffff,
1671 0x3c020800, 0x30a30007, 0x10600003, 0xac440834, 0x24a20007, 0x3045fff8,
1672 0x8f840028, 0x00851021, 0x30421fff, 0x24434000, 0x0343d821, 0x30c30007,
1673 0xaf840018, 0xaf820028, 0xaf420084, 0x10600002, 0x24c20007, 0x3046fff8,
1674 0x8f820044, 0x8f840004, 0x00461821, 0xaf82002c, 0x0064102b, 0xaf830044,
1675 0x14400002, 0x00641023, 0xaf820044, 0x8f840044, 0x34028000, 0x3c030800,
1676 0x8c650844, 0x00821021, 0x03421821, 0xaf83001c, 0xaf440080, 0x10a00006,
1677 0x2402000e, 0x93830043, 0x14620004, 0x3c021000, 0x2402043f, 0xa7420148,
1678 0x3c021000, 0x3c036000, 0xaf420178, 0x8c644448, 0x3c020800, 0x03e00008,
1679 0xac440838, 0x8f820034, 0x30424000, 0x10400005, 0x24020800, 0x0000000d,
1680 0x00000000, 0x24000405, 0x24020800, 0xaf420178, 0x97440104, 0x3c030008,
1681 0xaf430140, 0x8f820034, 0x30420001, 0x10400006, 0x3085ffff, 0x24020002,
1682 0x24a3fffe, 0xa7420146, 0x0a0004ff, 0xa7430148, 0xa7400146, 0x8f840028,
1683 0x2402000d, 0xa742014a, 0x24830008, 0x30631fff, 0x24624000, 0x0342d821,
1684 0x30a20007, 0xaf840018, 0xaf830028, 0xaf430084, 0x10400002, 0x24a20007,
1685 0x3045fff8, 0x8f820044, 0x8f840004, 0x00451821, 0xaf82002c, 0x0064102b,
1686 0xaf830044, 0x14400002, 0x00641023, 0xaf820044, 0x8f840044, 0x34028000,
1687 0x00821021, 0x03421821, 0x3c021000, 0xaf83001c, 0xaf440080, 0x03e00008,
1688 0xaf420178, 0x27bdffe8, 0x3c046008, 0xafbf0014, 0xafb00010, 0x8c825000,
1689 0x3c1a8000, 0x2403ff7f, 0x375b4000, 0x00431024, 0x3442380c, 0xac825000,
1690 0x8f430008, 0x3c100800, 0x37428000, 0x34630001, 0xaf430008, 0xaf82001c,
1691 0x3c02601c, 0xaf800028, 0xaf400080, 0xaf400084, 0x8c450008, 0x3c036000,
1692 0x8c620808, 0x3c040800, 0x3c030080, 0xac830820, 0x3042fff0, 0x38420010,
1693 0x2c420001, 0xaf850004, 0xaf820008, 0x0e00062f, 0x00000000, 0x8f420000,
1694 0x30420001, 0x1040fffb, 0x00000000, 0x8f440108, 0x30822000, 0xaf840034,
1695 0x10400004, 0x8e02083c, 0x24420001, 0x0a00059d, 0xae02083c, 0x30820200,
1696 0x10400027, 0x00000000, 0x97420104, 0x1040001c, 0x30824000, 0x14400005,
1697 0x00000000, 0x0e00022d, 0x00000000, 0x0a000592, 0x00000000, 0x8f620008,
1698 0x8f630000, 0x24020030, 0x00031e02, 0x306300f0, 0x10620007, 0x28620031,
1699 0x14400031, 0x24020040, 0x10620007, 0x00000000, 0x0a000592, 0x00000000,
1700 0x0e0002dd, 0x00000000, 0x0a000592, 0x00000000, 0x0e0003b8, 0x00000000,
1701 0x0a000592, 0x00000000, 0x30820040, 0x1440002d, 0x00000000, 0x0000000d,
1702 0x00000000, 0x240004a6, 0x0a00059d, 0x00000000, 0x8f430100, 0x24020d00,
1703 0x1462000f, 0x30820006, 0x97420104, 0x10400005, 0x30820040, 0x0e0004e9,
1704 0x00000000, 0x0a000592, 0x00000000, 0x1440001b, 0x00000000, 0x0000000d,
1705 0x00000000, 0x240004b8, 0x0a00059d, 0x00000000, 0x1040000e, 0x30821000,
1706 0x10400005, 0x00000000, 0x0e00065d, 0x00000000, 0x0a000592, 0x00000000,
1707 0x0e00046b, 0x00000000, 0x8f820040, 0x24420001, 0xaf820040, 0x0a00059d,
1708 0x00000000, 0x30820040, 0x14400004, 0x00000000, 0x0000000d, 0x00000000,
1709 0x240004cf, 0x8f420138, 0x3c034000, 0x00431025, 0xaf420138, 0x0a00053f,
1710 0x00000000, 0x3c046008, 0x8c835000, 0x3c1a8000, 0x2402ff7f, 0x375b4000,
1711 0x00621824, 0x3463380c, 0xac835000, 0x8f420008, 0x3c056000, 0x3c03601c,
1712 0x34420001, 0xaf420008, 0x37428000, 0xaf800028, 0xaf82001c, 0xaf400080,
1713 0xaf400084, 0x8c660008, 0x8ca20808, 0x3c040800, 0x3c030080, 0xac830820,
1714 0x3042fff0, 0x38420010, 0x2c420001, 0xaf860004, 0xaf820008, 0x03e00008,
1715 0x00000000, 0x3084ffff, 0x30820007, 0x10400002, 0x24820007, 0x3044fff8,
1716 0x8f820028, 0x00441821, 0x30631fff, 0x24644000, 0x0344d821, 0xaf820018,
1717 0xaf830028, 0x03e00008, 0xaf430084, 0x3084ffff, 0x30820007, 0x10400002,
1718 0x24820007, 0x3044fff8, 0x8f820044, 0x8f830004, 0x00442021, 0xaf82002c,
1719 0x0083102b, 0xaf840044, 0x14400002, 0x00831023, 0xaf820044, 0x8f820044,
1720 0x34038000, 0x00431821, 0x03432021, 0xaf84001c, 0x03e00008, 0xaf420080,
1721 0x8f830034, 0x24020002, 0x30630006, 0x1062000d, 0x2c620003, 0x50400005,
1722 0x24020004, 0x10600012, 0x3c020001, 0x0a000601, 0x00000000, 0x10620007,
1723 0x24020006, 0x1462000f, 0x3c020111, 0x0a0005f9, 0x00821025, 0x0a0005f8,
1724 0x3c020101, 0x3c020011, 0x00821025, 0x24030001, 0xaf421000, 0xaf830030,
1725 0x0a000601, 0x00000000, 0x00821025, 0xaf421000, 0xaf800030, 0x00000000,
1726 0x00000000, 0x00000000, 0x03e00008, 0x00000000, 0x8f820030, 0x10400005,
1727 0x3c038000, 0x8f421000, 0x00431024, 0x1040fffd, 0x00000000, 0x03e00008,
1728 0x00000000, 0x8f820034, 0x27bdffe8, 0x30424000, 0x14400005, 0xafbf0010,
1729 0x0e00022d, 0x00000000, 0x0a00062d, 0x8fbf0010, 0x8f620008, 0x8f630000,
1730 0x24020030, 0x00031e02, 0x306300f0, 0x10620008, 0x28620031, 0x1440000d,
1731 0x8fbf0010, 0x24020040, 0x10620007, 0x00000000, 0x0a00062d, 0x00000000,
1732 0x0e0002dd, 0x00000000, 0x0a00062d, 0x8fbf0010, 0x0e0003b8, 0x00000000,
1733 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x8f84003c, 0x1080000f, 0x3c026000,
1734 0x8c430c3c, 0x30630fff, 0xaf830014, 0x14600011, 0x3082000f, 0x10400005,
1735 0x308200f0, 0x10400003, 0x30820f00, 0x14400006, 0x00000000, 0x0000000d,
1736 0x00000000, 0x2400050e, 0x03e00008, 0x00000000, 0x0000000d, 0x00000000,
1737 0x24000513, 0x03e00008, 0x00000000, 0xaf83003c, 0x03e00008, 0x00000000,
1738 0x10c00007, 0x00000000, 0x8ca20000, 0x24c6ffff, 0x24a50004, 0xac820000,
1739 0x14c0fffb, 0x24840004, 0x03e00008, 0x00000000, 0x0a000659, 0x00a01021,
1740 0xac860000, 0x24840004, 0x00a01021, 0x1440fffc, 0x24a5ffff, 0x03e00008,
1741 0x00000000, 0x0000000d, 0x03e00008, 0x00000000, 0x3c040800, 0x8c82084c,
1742 0x54400007, 0xac80084c, 0x8f820034, 0x24030400, 0x30420c00, 0x1443005b,
1743 0x00000000, 0xac80084c, 0x0000000d, 0x00000000, 0x2400003c, 0x3c026000,
1744 0x8c444448, 0x3c030800, 0xac640850, 0x24000043, 0x97420104, 0x3045ffff,
1745 0x000530c2, 0x24a2007f, 0x000239c2, 0x2400004e, 0x3c046020, 0x24030020,
1746 0xac830000, 0x8c820000, 0x30420020, 0x10400005, 0x3c036020, 0x8c620000,
1747 0x30420020, 0x1440fffd, 0x00000000, 0x3c026020, 0x8c430010, 0x24040001,
1748 0x0087102b, 0x30ea007f, 0x24abfffe, 0x10400010, 0x00034240, 0x3c056020,
1749 0x24090020, 0xaca90000, 0x8ca20000, 0x30420020, 0x10400006, 0x24840001,
1750 0x3c036020, 0x8c620000, 0x30420020, 0x1440fffd, 0x00000000, 0x0087102b,
1751 0x1440fff4, 0x00000000, 0x8f85001c, 0x3c026020, 0x8c430010, 0x3c046020,
1752 0x34848000, 0x006a1825, 0x01034025, 0x2400006b, 0x10c0000b, 0x00000000,
1753 0x8ca30000, 0x24a50004, 0x8ca20000, 0x24a50004, 0x24c6ffff, 0xac820000,
1754 0x24840004, 0xac830000, 0x14c0fff7, 0x24840004, 0x24000077, 0x3c020007,
1755 0x34427700, 0x3c036000, 0xac6223c8, 0xac6b23cc, 0xac6823e4, 0x24000086,
1756 0x3c046000, 0x3c038000, 0x8c8223f8, 0x00431024, 0x1440fffd, 0x3c021000,
1757 0x3c056000, 0x24030019, 0xaca223f8, 0xa743014a, 0x8ca44448, 0x3c020800,
1758 0xac440854, 0x03e00008, 0x00000000, 0x00000000 };
1759
1760static u32 bnx2_TPAT_b06FwData[(0x0/4) + 1] = { 0x00000000 };
1761static u32 bnx2_TPAT_b06FwRodata[(0x0/4) + 1] = { 0x00000000 };
1762static u32 bnx2_TPAT_b06FwBss[(0x80/4) + 1] = { 0x00000000 };
1763static u32 bnx2_TPAT_b06FwSbss[(0x48/4) + 1] = { 0x00000000 };
1764
1765static int bnx2_TXP_b06FwReleaseMajor = 0x0;
1766static int bnx2_TXP_b06FwReleaseMinor = 0x0;
1767static int bnx2_TXP_b06FwReleaseFix = 0x0;
1768static u32 bnx2_TXP_b06FwStartAddr = 0x08002090;
1769static u32 bnx2_TXP_b06FwTextAddr = 0x08000000;
1770static int bnx2_TXP_b06FwTextLen = 0x3ffc;
1771static u32 bnx2_TXP_b06FwDataAddr = 0x08004020;
1772static int bnx2_TXP_b06FwDataLen = 0x0;
1773static u32 bnx2_TXP_b06FwRodataAddr = 0x00000000;
1774static int bnx2_TXP_b06FwRodataLen = 0x0;
1775static u32 bnx2_TXP_b06FwBssAddr = 0x08004060;
1776static int bnx2_TXP_b06FwBssLen = 0x194;
1777static u32 bnx2_TXP_b06FwSbssAddr = 0x08004020;
1778static int bnx2_TXP_b06FwSbssLen = 0x34;
1779static u32 bnx2_TXP_b06FwText[(0x3ffc/4) + 1] = {
1780 0x0a000824, 0x00000000, 0x00000000, 0x0000000d, 0x74787020, 0x302e362e,
1781 0x39000000, 0x00060900, 0x0000000a, 0x000003e8, 0x0000ea60, 0x00000000,
1782 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1783 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1784 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1785 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1786 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1787 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1788 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1789 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1790 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1791 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1792 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1793 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1794 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1795 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1796 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1797 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1798 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1799 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1800 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1801 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1802 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1803 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1804 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1805 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1806 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1807 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1808 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1809 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1810 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1811 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1812 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1813 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1814 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1815 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1816 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1817 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1818 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1819 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1820 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1821 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1822 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1823 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1824 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1825 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1826 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1827 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1828 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1829 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1830 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1831 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1832 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1833 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1834 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1835 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1836 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1837 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1838 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1839 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1840 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1841 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1842 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1843 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1844 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1845 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1846 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1847 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1848 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1849 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1850 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1851 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1852 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1853 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1854 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1855 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1856 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1857 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1858 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1859 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1860 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1861 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1862 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1863 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1864 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1865 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1866 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1867 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1868 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1869 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1870 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1871 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1872 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1873 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1874 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1875 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1876 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1877 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1878 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1879 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1880 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1881 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1882 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1883 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1884 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1885 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1886 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1887 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1888 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1889 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1890 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1891 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1892 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1893 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1894 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1895 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1896 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1897 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1898 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1899 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1900 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1901 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1902 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1903 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1904 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1905 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1906 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1907 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1908 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1909 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1910 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1911 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1912 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1913 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1914 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1915 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1916 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1917 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1918 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1919 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1920 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1921 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1922 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1923 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1924 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1925 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1926 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1927 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1928 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1929 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1930 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1931 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1932 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1933 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1934 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1935 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1936 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1937 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1938 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1939 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1940 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1941 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1942 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1943 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1944 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1945 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1946 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1947 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1948 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1949 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1950 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1951 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1952 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1953 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1954 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1955 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1956 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1957 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1958 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1959 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1960 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1961 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1962 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1963 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1964 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1965 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1966 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1967 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1968 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1969 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1970 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1971 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1972 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1973 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1974 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1975 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1976 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1977 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1978 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1979 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1980 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1981 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1982 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1983 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1984 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1985 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1986 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1987 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1988 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1989 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1990 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1991 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1992 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1993 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1994 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1995 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1996 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1997 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1998 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1999 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2000 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2001 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2002 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2003 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2004 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2005 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2006 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2007 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2008 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2009 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2010 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2011 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2012 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2013 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2014 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2015 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2016 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2017 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2018 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2019 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2020 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2021 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2022 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2023 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2024 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2025 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2026 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2027 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2028 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2029 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2030 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2031 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2032 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2033 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2034 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2035 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2036 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2037 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2038 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2039 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2040 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2041 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2042 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2043 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2044 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2045 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2046 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2047 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2048 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2049 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2050 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2051 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2052 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2053 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2054 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2055 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2056 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2057 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2058 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2059 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2060 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2061 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2062 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2063 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2064 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2065 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2066 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2067 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2068 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2069 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2070 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2071 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2072 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2073 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2074 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2075 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2076 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2077 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2078 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2079 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2080 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2081 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2082 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2083 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2084 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2085 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2086 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2087 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2088 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2089 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2090 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2091 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2092 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2093 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2094 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2095 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2096 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2097 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2098 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2099 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2100 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2101 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2102 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2103 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2104 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2105 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2106 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2107 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2108 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2109 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2110 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2111 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2112 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2113 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2114 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2115 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2116 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2117 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2118 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2119 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2120 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2121 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2122 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2123 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2124 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2125 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2126 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2127 0x00000000, 0x00000000, 0x00000000, 0x10000003, 0x00000000, 0x0000000d,
2128 0x0000000d, 0x3c020800, 0x24424020, 0x3c030800, 0x246341f4, 0xac400000,
2129 0x0043202b, 0x1480fffd, 0x24420004, 0x3c1d0800, 0x37bd7ffc, 0x03a0f021,
2130 0x3c100800, 0x26102090, 0x3c1c0800, 0x279c4020, 0x0e000a0e, 0x00000000,
2131 0x0000000d, 0x8f840014, 0x27bdffe8, 0xafb00010, 0x8f460104, 0x8f830008,
2132 0x8c8500ac, 0xaf430080, 0x948200a8, 0xa7420e10, 0x948300aa, 0xa7430e12,
2133 0x8c8200ac, 0xaf420e18, 0x97430e10, 0xa7430e14, 0x97420e12, 0xa7420e16,
2134 0x8f430e18, 0x00005021, 0x00c53023, 0x10c001a3, 0xaf430e1c, 0x240f0800,
2135 0x3c0e1000, 0x2419fff8, 0x24100010, 0x3c188100, 0x93620008, 0x10400009,
2136 0x00000000, 0x97620010, 0x00c2102b, 0x14400005, 0x00000000, 0x97620010,
2137 0x3042ffff, 0x0a000862, 0xaf420e00, 0xaf460e00, 0x8f420000, 0x30420008,
2138 0x1040fffd, 0x00000000, 0x97420e08, 0x8f450e04, 0x3044ffff, 0x30820001,
2139 0x14400005, 0x00000000, 0x14a00005, 0x3083a040, 0x0a0009e6, 0x00000000,
2140 0x0000000d, 0x3083a040, 0x24020040, 0x14620049, 0x3082a000, 0x8f87000c,
2141 0x30880036, 0x30890008, 0xaf4f0178, 0x00e01821, 0x9742008a, 0x00431023,
2142 0x2442ffff, 0x30421fff, 0x2c420008, 0x1440fffa, 0x00000000, 0x8f830018,
2143 0x00a05021, 0x00c53023, 0x24e24000, 0x03422821, 0x306b00ff, 0x24630001,
2144 0xaf830018, 0x93840012, 0x000b1400, 0x3c030100, 0x00431025, 0xaca20000,
2145 0x8f820018, 0x30840007, 0x00042240, 0x34870001, 0x00e83825, 0x1120000f,
2146 0xaca20004, 0x97430e0a, 0x8f84000c, 0x00ee3825, 0x2402000e, 0x00781825,
2147 0xaf430160, 0x25430006, 0x24840008, 0x30841fff, 0xa742015a, 0xa7430158,
2148 0xaf84000c, 0x0a0008a9, 0x00000000, 0x8f83000c, 0x25420002, 0xa7420158,
2149 0x24630008, 0x30631fff, 0xaf83000c, 0x54c0000c, 0x8f420e14, 0x97420e10,
2150 0x97430e12, 0x8f840014, 0x00021400, 0x00621825, 0xac8300a8, 0x8f850014,
2151 0x8f420e18, 0x34e70040, 0xaca200ac, 0x8f420e14, 0x8f430e1c, 0xaf420144,
2152 0xaf430148, 0xa34b0152, 0xaf470154, 0x0a0009f1, 0xaf4e0178, 0x10400128,
2153 0x00000000, 0x97620010, 0x00a2102b, 0x10400003, 0x30820040, 0x10400122,
2154 0x00000000, 0xafa60008, 0xa7840010, 0xaf850004, 0x93620008, 0x1440005e,
2155 0x27ac0008, 0xaf60000c, 0x97820010, 0x30424000, 0x10400002, 0x2403000e,
2156 0x24030016, 0xa363000a, 0x24034007, 0xaf630014, 0x93820012, 0x8f630014,
2157 0x30420007, 0x00021240, 0x00621825, 0xaf630014, 0x97820010, 0x8f630014,
2158 0x30420010, 0x00621825, 0xaf630014, 0x97820010, 0x30420008, 0x5040000e,
2159 0x00002821, 0x8f620014, 0x004e1025, 0xaf620014, 0x97430e0a, 0x2402000e,
2160 0x00781825, 0xaf630004, 0xa3620002, 0x9363000a, 0x3405fffc, 0x24630004,
2161 0x0a0008f2, 0xa363000a, 0xaf600004, 0xa3600002, 0x97820010, 0x9363000a,
2162 0x30421f00, 0x00021182, 0x24420028, 0x00621821, 0xa3630009, 0x97420e0c,
2163 0xa7620010, 0x93630009, 0x24020008, 0x24630002, 0x30630007, 0x00431023,
2164 0x30420007, 0xa362000b, 0x93640009, 0x97620010, 0x8f890004, 0x97830010,
2165 0x00441021, 0x00a21021, 0x30630040, 0x10600006, 0x3045ffff, 0x15250005,
2166 0x0125102b, 0x3c068000, 0x0a000925, 0x00005821, 0x0125102b, 0x144000c8,
2167 0x00005021, 0x97420e14, 0xa7420e10, 0x97430e16, 0xa7430e12, 0x8f420e1c,
2168 0xaf420e18, 0xaf450e00, 0x8f420000, 0x30420008, 0x1040fffd, 0x00000000,
2169 0x97420e08, 0x00a04821, 0xa7820010, 0x8f430e04, 0x00003021, 0x240b0001,
2170 0xaf830004, 0x97620010, 0x0a000936, 0x304dffff, 0x8f890004, 0x97820010,
2171 0x30420040, 0x10400004, 0x01206821, 0x3c068000, 0x0a000936, 0x00005821,
2172 0x97630010, 0x8f820004, 0x144300a7, 0x00005021, 0x00003021, 0x240b0001,
2173 0x8d820000, 0x00491023, 0x1440000d, 0xad820000, 0x8f620014, 0x34420040,
2174 0xaf620014, 0x97430e10, 0x97420e12, 0x8f840014, 0x00031c00, 0x00431025,
2175 0xac8200a8, 0x8f830014, 0x8f420e18, 0xac6200ac, 0x93620008, 0x1440003f,
2176 0x00000000, 0x25260002, 0x8f84000c, 0x9743008a, 0x3063ffff, 0xafa30000,
2177 0x8fa20000, 0x00441023, 0x2442ffff, 0x30421fff, 0x2c420010, 0x1440fff7,
2178 0x00000000, 0x8f82000c, 0x8f830018, 0x00021082, 0x00021080, 0x24424000,
2179 0x03422821, 0x00605021, 0x24630001, 0x314200ff, 0x00021400, 0xaf830018,
2180 0x3c033200, 0x00431025, 0xaca20000, 0x93630009, 0x9362000a, 0x00031c00,
2181 0x00431025, 0xaca20004, 0x8f830018, 0xaca30008, 0x97820010, 0x30420008,
2182 0x10400002, 0x00c04021, 0x25280006, 0x97430e14, 0x93640002, 0x8f450e1c,
2183 0x8f660004, 0x8f670014, 0xaf4f0178, 0x3063ffff, 0xa7430144, 0x97420e16,
2184 0xa7420146, 0xaf450148, 0xa34a0152, 0x8f82000c, 0x308400ff, 0xa744015a,
2185 0xaf460160, 0xa7480158, 0xaf470154, 0xaf4e0178, 0x00501021, 0x30421fff,
2186 0xaf82000c, 0x0a0009c5, 0x8d820000, 0x93620009, 0x9363000b, 0x8f85000c,
2187 0x2463000a, 0x00435021, 0x25440007, 0x00992024, 0x9743008a, 0x3063ffff,
2188 0xafa30000, 0x8fa20000, 0x00451023, 0x2442ffff, 0x30421fff, 0x0044102b,
2189 0x1440fff7, 0x00000000, 0x8f82000c, 0x8f840018, 0x00021082, 0x00021080,
2190 0x24424000, 0x03422821, 0x00804021, 0x24840001, 0xaf840018, 0x93630009,
2191 0x310200ff, 0x00022400, 0x3c024100, 0x24630002, 0x00621825, 0x00832025,
2192 0xaca40000, 0x8f62000c, 0x00461025, 0xaca20004, 0x97430e14, 0x93640002,
2193 0x8f450e1c, 0x8f660004, 0x8f670014, 0xaf4f0178, 0x3063ffff, 0xa7430144,
2194 0x97420e16, 0x308400ff, 0xa7420146, 0xaf450148, 0xa3480152, 0x8f83000c,
2195 0x25420007, 0x00591024, 0xa744015a, 0xaf460160, 0xa7490158, 0xaf470154,
2196 0xaf4e0178, 0x00621821, 0x30631fff, 0xaf83000c, 0x8d820000, 0x14400005,
2197 0x00000000, 0x8f620014, 0x2403ffbf, 0x00431024, 0xaf620014, 0x8f62000c,
2198 0x004d1021, 0xaf62000c, 0x93630008, 0x14600008, 0x00000000, 0x11600006,
2199 0x00000000, 0x8f630014, 0x3c02efff, 0x3442fffe, 0x00621824, 0xaf630014,
2200 0xa36b0008, 0x01205021, 0x15400016, 0x8fa60008, 0x97420e14, 0x97430e16,
2201 0x8f850014, 0x00021400, 0x00621825, 0xaca300a8, 0x8f840014, 0x8f420e1c,
2202 0x0a0009f3, 0xac8200ac, 0x97420e14, 0x97430e16, 0x8f840014, 0x00021400,
2203 0x00621825, 0xac8300a8, 0x8f850014, 0x8f420e1c, 0x00005021, 0x0a0009f3,
2204 0xaca200ac, 0x14c0fe64, 0x00000000, 0x55400018, 0x8fb00010, 0x3c038000,
2205 0x8f420178, 0x00431024, 0x1440fffd, 0x00000000, 0x97430e14, 0x8f440e1c,
2206 0x24020800, 0xaf420178, 0x3063ffff, 0xa7430144, 0x97420e16, 0x3c031000,
2207 0xa7420146, 0x24020240, 0xaf440148, 0xa3400152, 0xa740015a, 0xaf400160,
2208 0xa7400158, 0xaf420154, 0xaf430178, 0x8fb00010, 0x03e00008, 0x27bd0018,
2209 0x27bdffd8, 0x3c1a8000, 0x3c0420ff, 0x3484fffd, 0x3c020008, 0x03421821,
2210 0xafbf0020, 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0xaf830014,
2211 0xaf440e00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2212 0x3c0200ff, 0x3442fffd, 0x3c046004, 0xaf420e00, 0x8c835000, 0x24130d00,
2213 0x3c120800, 0x3c114000, 0x2402ff7f, 0x00621824, 0x3463380c, 0x24020009,
2214 0xac835000, 0xaf420008, 0xaf800018, 0xaf80000c, 0x0e000fa1, 0x00000000,
2215 0x0e000a96, 0x00000000, 0x3c020800, 0x24504080, 0x8f420000, 0x30420001,
2216 0x1040fffd, 0x00000000, 0x8f440100, 0xaf840008, 0xaf440020, 0x93430108,
2217 0xa3830012, 0x93820012, 0x30420001, 0x10400008, 0x00000000, 0x93820012,
2218 0x30420006, 0x00021100, 0x0e00083b, 0x0050d821, 0x0a000a52, 0x00000000,
2219 0x14930005, 0x00000000, 0x0e00083b, 0x265b4100, 0x0a000a52, 0x00000000,
2220 0x0e000ba3, 0x00000000, 0xaf510138, 0x0a000a36, 0x00000000, 0x27bdfff8,
2221 0x3084ffff, 0x24820007, 0x3044fff8, 0x8f85000c, 0x9743008a, 0x3063ffff,
2222 0xafa30000, 0x8fa20000, 0x00451023, 0x2442ffff, 0x30421fff, 0x0044102b,
2223 0x1440fff7, 0x00000000, 0x8f82000c, 0x00021082, 0x00021080, 0x24424000,
2224 0x03421021, 0x03e00008, 0x27bd0008, 0x3084ffff, 0x8f82000c, 0x24840007,
2225 0x3084fff8, 0x00441021, 0x30421fff, 0xaf82000c, 0x03e00008, 0x00000000,
2226 0x27bdffe8, 0x3c1a8000, 0x3c0420ff, 0x3484fffd, 0x3c020008, 0x03421821,
2227 0xafbf0010, 0xaf830014, 0xaf440e00, 0x00000000, 0x00000000, 0x00000000,
2228 0x00000000, 0x00000000, 0x3c0200ff, 0x3442fffd, 0x3c046004, 0xaf420e00,
2229 0x8c825000, 0x2403ff7f, 0x00431024, 0x3442380c, 0x24030009, 0xac825000,
2230 0xaf430008, 0xaf800018, 0xaf80000c, 0x0e000fa1, 0x00000000, 0x0e000a96,
2231 0x00000000, 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x27bdffe8, 0x3c02000a,
2232 0x03421821, 0x3c040800, 0x24844120, 0x24050018, 0xafbf0010, 0xaf830024,
2233 0x0e000fad, 0x00003021, 0x3c050800, 0x3c020800, 0x24423d60, 0xaca24180,
2234 0x24a54180, 0x3c020800, 0x24423e18, 0x3c030800, 0x24633e2c, 0x3c040800,
2235 0xaca20004, 0x3c020800, 0x24423d68, 0xaca30008, 0xac824190, 0x24844190,
2236 0x3c020800, 0x24423da4, 0x3c070800, 0x24e73de4, 0x3c060800, 0x24c63e40,
2237 0x3c050800, 0x24a52b28, 0x3c030800, 0xac820004, 0x3c020800, 0x24423e48,
2238 0xac870008, 0xac86000c, 0xac850010, 0xac6241b0, 0x246341b0, 0x8fbf0010,
2239 0x3c020800, 0x24423e60, 0xac620004, 0xac670008, 0xac66000c, 0xac650010,
2240 0x03e00008, 0x27bd0018, 0x27bdffc8, 0x3c020800, 0x24424120, 0xafbf0030,
2241 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x90470021, 0x8c510008,
2242 0x8c45001c, 0x8f900020, 0x3c060800, 0x3c038000, 0x8f420178, 0x00431024,
2243 0x1440fffd, 0x8cc2414c, 0x24c3414c, 0x2473ffd4, 0xaf420144, 0x8e620030,
2244 0x30b22000, 0xaf420148, 0x3c021000, 0xaf50014c, 0xa3470152, 0xa7510158,
2245 0xaf450154, 0xaf420178, 0x12400004, 0x3c030800, 0x8c620030, 0x24420001,
2246 0xac620030, 0x93420109, 0x9344010a, 0x00111c00, 0xafa30018, 0x00071a00,
2247 0xafa50014, 0x8cc5414c, 0x00021600, 0x00042400, 0x00441025, 0x00431025,
2248 0xafa20010, 0x8f440100, 0x8e660030, 0x0e000fe1, 0x02003821, 0x1640000e,
2249 0x8fbf0030, 0x8f820000, 0x8e630030, 0x8c44017c, 0x02031823, 0x00711823,
2250 0x00641823, 0x2c630002, 0x14600006, 0x8fb3002c, 0x0000000d, 0x00000000,
2251 0x240000ca, 0x8fbf0030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
2252 0x03e00008, 0x27bd0038, 0x974309da, 0x00804021, 0xad030000, 0x8f4209dc,
2253 0xad020004, 0x8f4309e0, 0xad030008, 0x934409d9, 0x24020001, 0x30840003,
2254 0x1082001f, 0x30a900ff, 0x28820002, 0x10400005, 0x24020002, 0x10800009,
2255 0x3c0a0800, 0x0a000b64, 0x93420934, 0x1082000b, 0x24020003, 0x10820026,
2256 0x3c0a0800, 0x0a000b64, 0x93420934, 0x974209e4, 0x00021400, 0x34420800,
2257 0xad02000c, 0x0a000b63, 0x25080010, 0x974209e4, 0x00021400, 0x34428100,
2258 0xad02000c, 0x974309e8, 0x3c0a0800, 0x00031c00, 0x34630800, 0xad030010,
2259 0x0a000b63, 0x25080014, 0x974409e4, 0x3c050800, 0x24a24120, 0x94430018,
2260 0x94460010, 0x9447000c, 0x00a05021, 0x24020800, 0xad000010, 0xad020014,
2261 0x00042400, 0x00661821, 0x00671823, 0x2463fff2, 0x00832025, 0xad04000c,
2262 0x0a000b63, 0x25080018, 0x974209e4, 0x3c050800, 0x00021400, 0x34428100,
2263 0xad02000c, 0x974409e8, 0x24a24120, 0x94430018, 0x94460010, 0x9447000c,
2264 0x00a05021, 0x24020800, 0xad000014, 0xad020018, 0x00042400, 0x00661821,
2265 0x00671823, 0x2463ffee, 0x00832025, 0xad040010, 0x2508001c, 0x93420934,
2266 0x93450921, 0x3c074000, 0x25444120, 0x94830014, 0x94860010, 0x00021082,
2267 0x00021600, 0x00052c00, 0x00a72825, 0x00451025, 0x00661821, 0x00431025,
2268 0xad020000, 0x97830028, 0x974209ea, 0x00621821, 0x00031c00, 0xad030004,
2269 0x97820028, 0x24420001, 0x30427fff, 0xa7820028, 0x93430920, 0x3c020006,
2270 0x00031e00, 0x00621825, 0xad030008, 0x8f42092c, 0xad02000c, 0x8f430930,
2271 0xad030010, 0x8f440938, 0x25080014, 0xad040000, 0x8f820020, 0x11200004,
2272 0xad020004, 0x8f420940, 0x0a000b8d, 0x2442ffff, 0x8f420940, 0xad020008,
2273 0x8f440948, 0x8f420940, 0x93430936, 0x00822823, 0x00652806, 0x3402ffff,
2274 0x0045102b, 0x54400001, 0x3405ffff, 0x93420937, 0x25444120, 0x90830020,
2275 0xad000010, 0x00021700, 0x34630010, 0x00031c00, 0x00431025, 0x00451025,
2276 0xad02000c, 0x03e00008, 0x25020014, 0x27bdffb0, 0x3c020008, 0x03421821,
2277 0xafbf004c, 0xafbe0048, 0xafb70044, 0xafb60040, 0xafb5003c, 0xafb40038,
2278 0xafb30034, 0xafb20030, 0xafb1002c, 0xafb00028, 0xaf830000, 0x24020040,
2279 0xaf420814, 0xaf400810, 0x8f420944, 0x8f430950, 0x8f440954, 0x8f45095c,
2280 0xaf820030, 0xaf830020, 0xaf84001c, 0xaf85002c, 0x93430900, 0x24020020,
2281 0x10620005, 0x24020030, 0x10620022, 0x3c030800, 0x0a000bf1, 0x8c62002c,
2282 0x24020088, 0xaf420818, 0x3c020800, 0x24424180, 0xafa20020, 0x93430109,
2283 0x3c020800, 0x10600009, 0x24574190, 0x3c026000, 0x24030100, 0xac43081c,
2284 0x3c030001, 0xac43081c, 0x0000000d, 0x00000000, 0x2400031d, 0x9342010a,
2285 0x30420080, 0x1440001c, 0x00000000, 0x3c026000, 0x24030100, 0xac43081c,
2286 0x3c030001, 0xac43081c, 0x0000000d, 0x00000000, 0x24000324, 0x0a000bf4,
2287 0x00000000, 0x93430109, 0x3063007f, 0x00031140, 0x000318c0, 0x00431021,
2288 0x24430088, 0xaf430818, 0x0000000d, 0x3c020800, 0x244241d0, 0x3c030800,
2289 0x247741e0, 0x0a000bf4, 0xafa20020, 0x24420001, 0x0a000f4c, 0xac62002c,
2290 0x8f840000, 0x8f850020, 0x24020800, 0xaf420178, 0x8f4209a4, 0x8c83017c,
2291 0x00a21023, 0x00431023, 0x2c420002, 0x14400004, 0x00000000, 0x0000000d,
2292 0x00000000, 0x24000349, 0x8f420104, 0x8f430988, 0x00431023, 0x58400005,
2293 0x8f4209a0, 0x0000000d, 0x00000000, 0x2400034d, 0x8f4209a0, 0x3c100800,
2294 0xae02414c, 0x8f4309a4, 0x2604414c, 0x2491ffd4, 0xae230030, 0x8f420104,
2295 0xae250024, 0x00431023, 0xac82ffd4, 0x8fa30020, 0x8c620000, 0x0040f809,
2296 0x0200b021, 0x00409021, 0x32440010, 0x32420002, 0x10400007, 0xafa40024,
2297 0x8e22001c, 0x32500040, 0x2403ffbf, 0x00431024, 0x0a000f13, 0xae22001c,
2298 0x32420020, 0x10400002, 0x3c020800, 0x245741b0, 0x32420001, 0x14400007,
2299 0x00000000, 0x8f820008, 0xaf420080, 0x8ec3414c, 0xaf430e10, 0x8e220030,
2300 0xaf420e18, 0x9343010b, 0x93420905, 0x30420008, 0x1040003c, 0x307400ff,
2301 0x8f820000, 0x8c430074, 0x0460000a, 0x00000000, 0x3c026000, 0x24030100,
2302 0xac43081c, 0x3c030001, 0xac43081c, 0x0000000d, 0x00000000, 0x24000384,
2303 0x8f820000, 0x9044007b, 0x9343010a, 0x14830027, 0x32500040, 0x24072000,
2304 0x3c090800, 0x3c038000, 0x8f420178, 0x00431024, 0x1440fffd, 0x8ec2414c,
2305 0x26c4414c, 0x2484ffd4, 0xaf420144, 0x8c820030, 0x3c030100, 0xaf420148,
2306 0x24020047, 0xaf43014c, 0x00001821, 0xa3420152, 0x3c021000, 0xa7430158,
2307 0xaf470154, 0xaf420178, 0x8ec5414c, 0x8d230030, 0x8c860030, 0x24630001,
2308 0xad230030, 0x93420109, 0x9343010a, 0xafa70014, 0xafa00018, 0x00021600,
2309 0x00031c00, 0x00431025, 0x34424700, 0xafa20010, 0x8f440100, 0x0e000fe1,
2310 0x3c070100, 0x3c030800, 0x24624120, 0x0a000d01, 0x8c43001c, 0x32820002,
2311 0x10400047, 0x3c039000, 0x34630001, 0x8f820008, 0x32500040, 0x3c048000,
2312 0x00431025, 0xaf420020, 0x8f420020, 0x00441024, 0x1440fffd, 0x00000000,
2313 0x8f830000, 0x90620005, 0x3c058000, 0x34420008, 0xa0620005, 0x8f860000,
2314 0x34a50001, 0x8f840008, 0x8cc20074, 0x3c038000, 0x00852025, 0x00431025,
2315 0xacc20074, 0xaf440020, 0x90c3007b, 0x9342010a, 0x14620028, 0x3c040800,
2316 0x24072000, 0x3c090800, 0x3c038000, 0x8f420178, 0x00431024, 0x1440fffd,
2317 0x8ec2414c, 0x26c4414c, 0x2484ffd4, 0xaf420144, 0x8c820030, 0x3c030100,
2318 0xaf420148, 0x24020046, 0xaf43014c, 0x00001821, 0xa3420152, 0x3c021000,
2319 0xa7430158, 0xaf470154, 0xaf420178, 0x8ec5414c, 0x8d230030, 0x8c860030,
2320 0x24630001, 0xad230030, 0x93420109, 0x9343010a, 0xafa70014, 0xafa00018,
2321 0x00021600, 0x00031c00, 0x00431025, 0x34424600, 0xafa20010, 0x8f440100,
2322 0x0e000fe1, 0x3c070100, 0x3c040800, 0x24824120, 0x0a000d01, 0x8c43001c,
2323 0x93420108, 0x30420010, 0x50400050, 0x9343093f, 0x8f860000, 0x90c3007f,
2324 0x90c2007e, 0x90c40080, 0x306800ff, 0x00021600, 0x00081c00, 0x00431025,
2325 0x00042200, 0x90c3007a, 0x90c5000a, 0x00441025, 0x11050028, 0x00623825,
2326 0xa0c8000a, 0x24086000, 0x3c090800, 0x3c038000, 0x8f420178, 0x00431024,
2327 0x1440fffd, 0x8ec2414c, 0x26c4414c, 0x2484ffd4, 0xaf420144, 0x8c820030,
2328 0x00001821, 0xaf420148, 0x24020052, 0xaf47014c, 0xa3420152, 0x3c021000,
2329 0xa7430158, 0xaf480154, 0xaf420178, 0x8ec5414c, 0x8d230030, 0x8c860030,
2330 0x24630001, 0xad230030, 0x93420109, 0x9343010a, 0xafa80014, 0xafa00018,
2331 0x00021600, 0x00031c00, 0x00431025, 0x34425200, 0xafa20010, 0x0e000fe1,
2332 0x8f440100, 0x0a000cfb, 0x00000000, 0x3c026000, 0x24030100, 0xac43081c,
2333 0x3c030001, 0xac43081c, 0x0000000d, 0x00000000, 0x240003cd, 0x16800009,
2334 0x3c040800, 0x3c030800, 0x24624120, 0x8c43001c, 0x32500040, 0x2404ffbf,
2335 0x00641824, 0x0a000f13, 0xac43001c, 0x8c824120, 0x10400005, 0x3c030800,
2336 0x8c620034, 0xac804120, 0x24420001, 0xac620034, 0x9343093f, 0x24020012,
2337 0x1462000f, 0x329e0038, 0x17c0000c, 0x3c030800, 0x8f830000, 0x8c62004c,
2338 0xac62005c, 0x3c020800, 0x24444120, 0x8c82001c, 0x32500040, 0x2403ffbf,
2339 0x00431024, 0x0a000f13, 0xac82001c, 0xac604120, 0x97420908, 0x000211c0,
2340 0xaf420024, 0x97420908, 0x3c030080, 0x34630003, 0x000211c0, 0xaf42080c,
2341 0xaf43081c, 0x974209ec, 0x8f4309a4, 0xa7820028, 0x3c020800, 0x24444120,
2342 0xac830028, 0x93420937, 0x93430934, 0x00021080, 0x00621821, 0xa4830014,
2343 0x934209d8, 0x00621821, 0xa4830016, 0x934209d8, 0x93430934, 0x00809821,
2344 0x00431021, 0x24420010, 0xa4820012, 0x0000a821, 0x24020006, 0x13c00003,
2345 0xae62001c, 0x0a000d82, 0x24120008, 0x8f420958, 0x8f830020, 0x8f84002c,
2346 0x00431023, 0x00832023, 0x04800003, 0xae620004, 0x04410003, 0x0082102b,
2347 0x0a000d4e, 0xae600004, 0x54400001, 0xae640004, 0x8ee20000, 0x0040f809,
2348 0x00000000, 0x00409021, 0x32420001, 0x5440001e, 0x8ee20004, 0x8e630008,
2349 0x1060002b, 0x3c02c000, 0x00621025, 0xaf420e00, 0x8f420000, 0x30420008,
2350 0x1040fffd, 0x00000000, 0x97420e08, 0xa7820010, 0x8f430e04, 0x8e620008,
2351 0xaf830004, 0x8f840004, 0x0044102b, 0x1040000b, 0x24150001, 0x24020100,
2352 0x3c016000, 0xac22081c, 0x3c020001, 0x3c016000, 0xac22081c, 0x0000000d,
2353 0x00000000, 0x24000449, 0x24150001, 0x8ee20004, 0x0040f809, 0x00000000,
2354 0x02429025, 0x32420002, 0x5040001d, 0x8f470940, 0x12a00006, 0x8ec2414c,
2355 0x8f830000, 0xac6200a8, 0x8f840000, 0x8e620030, 0xac8200ac, 0x32420004,
2356 0x50400013, 0x8f470940, 0x3c020800, 0x3283007d, 0x106000fe, 0x245741b0,
2357 0x32820001, 0x50400006, 0x36520002, 0x8f830030, 0x8f420940, 0x106200f7,
2358 0x00000000, 0x36520002, 0x24020008, 0xa660000c, 0xa662000e, 0xae600008,
2359 0xa2600020, 0x8f470940, 0x3c030800, 0x24684120, 0x8d020028, 0x8d050008,
2360 0x9504000c, 0x9506000a, 0x95030022, 0x00451021, 0x00862021, 0x00641821,
2361 0xaf870030, 0xad020028, 0x32820030, 0x10400006, 0xa5030010, 0x91020020,
2362 0x32910040, 0x34420004, 0x0a000dd4, 0xa1020020, 0x93420923, 0x30420040,
2363 0x10400029, 0x32910040, 0x8f830000, 0x8f840020, 0x8c620084, 0x00441023,
2364 0x0442000a, 0x3c039000, 0x95020010, 0x8c630084, 0x00821021, 0x00621823,
2365 0x1c600004, 0x3c039000, 0x91020020, 0x34420001, 0xa1020020, 0x34630001,
2366 0x8f820008, 0x32910040, 0x3c048000, 0x00431025, 0xaf420020, 0x8f420020,
2367 0x00441024, 0x1440fffd, 0x00000000, 0x8f840000, 0x9083003f, 0x2402000a,
2368 0x10620005, 0x2402000c, 0x9083003f, 0x24020008, 0x14620002, 0x24020014,
2369 0xa082003f, 0x8f830008, 0x3c028000, 0x34420001, 0x00621825, 0xaf430020,
2370 0x3c040800, 0x24904120, 0x9602000c, 0x96030016, 0x9604000e, 0x00431021,
2371 0x00442021, 0x24840002, 0x3084ffff, 0x0e000a55, 0xa6020018, 0x8f850018,
2372 0x00a01821, 0xa2030021, 0x8ee60008, 0x00402021, 0x24a50001, 0xaf850018,
2373 0x00c0f809, 0x00000000, 0x00402021, 0x0e000b12, 0x02202821, 0x8ee3000c,
2374 0x0060f809, 0x00402021, 0x96040018, 0x9602000e, 0x00822021, 0x24840002,
2375 0x0e000a6b, 0x3084ffff, 0x3c030800, 0x8c624120, 0x8e030008, 0x3c040800,
2376 0x00431023, 0x14400012, 0xac824120, 0x54600006, 0x8e02001c, 0x3243004a,
2377 0x24020002, 0x14620005, 0x00000000, 0x8e02001c, 0x34420040, 0x0a000e0b,
2378 0xae02001c, 0x52a00006, 0x36520002, 0x8e02002c, 0xaf420e10, 0x8e030030,
2379 0xaf430e18, 0x36520002, 0x52a00008, 0x96670010, 0x8f830000, 0x8f420e10,
2380 0xac6200a8, 0x8f840000, 0x8f420e18, 0xac8200ac, 0x96670010, 0x92680020,
2381 0x24020040, 0xaf420814, 0x8f830020, 0x8f82001c, 0x00671821, 0x00621023,
2382 0xaf830020, 0x58400005, 0x8f42095c, 0x8f820000, 0xaf83001c, 0xac430054,
2383 0x8f42095c, 0x31030008, 0xaf82002c, 0x1060001a, 0x00000000, 0x8f840000,
2384 0x90820120, 0x90830121, 0x304600ff, 0x00c31823, 0x30630007, 0x24020007,
2385 0x1062000e, 0x00000000, 0x90820122, 0x304200fe, 0xa0820122, 0x8f850000,
2386 0x00061880, 0x8f840020, 0x24a20100, 0x00431021, 0x24c30001, 0x30630007,
2387 0xac440000, 0x0a000e40, 0xa0a30120, 0x90820122, 0x34420001, 0xa0820122,
2388 0x14e00003, 0x31020001, 0x10400031, 0x32510002, 0x8f820000, 0x8c43000c,
2389 0x30630001, 0x1060002c, 0x32510002, 0x3c029000, 0x8f830008, 0x34420001,
2390 0x3c048000, 0x00621825, 0xaf430020, 0x8f420020, 0x00441024, 0x1440fffd,
2391 0x00000000, 0x8f870000, 0x8ce2000c, 0x30420001, 0x10400018, 0x00000000,
2392 0x94e2006a, 0x00022880, 0x50a00001, 0x24050001, 0x94e30068, 0x90e40081,
2393 0x3c020800, 0x8c460024, 0x00652821, 0x00852804, 0x00c5102b, 0x54400001,
2394 0x00a03021, 0x3c020800, 0x8c440028, 0x00c4182b, 0x54600001, 0x00c02021,
2395 0x8f430074, 0x2402fffe, 0x00822824, 0x00a31821, 0xace3000c, 0x8f830008,
2396 0x3c028000, 0x34420001, 0x00621825, 0xaf430020, 0x8f830020, 0x3c020800,
2397 0x24504120, 0xae030024, 0x8ee20010, 0x0040f809, 0x00000000, 0x12a00005,
2398 0x00000000, 0x8f420e10, 0xae02002c, 0x8f430e18, 0xae030030, 0x1220feba,
2399 0x0000a821, 0x8f870024, 0x97860028, 0x8f830000, 0x8f820030, 0x8f840020,
2400 0x8f85001c, 0x32500040, 0xa4e6002c, 0xac620044, 0x32420008, 0xac640050,
2401 0xac650054, 0x1040007a, 0x32820020, 0x10400027, 0x32910010, 0x24072000,
2402 0x3c090800, 0x3c038000, 0x8f420178, 0x00431024, 0x1440fffd, 0x8ec2414c,
2403 0x26c4414c, 0x2484ffd4, 0xaf420144, 0x8c820030, 0x3c030400, 0xaf420148,
2404 0x24020041, 0xaf43014c, 0x00001821, 0xa3420152, 0x3c021000, 0xa7430158,
2405 0xaf470154, 0xaf420178, 0x8ec5414c, 0x8d230030, 0x8c860030, 0x24630001,
2406 0xad230030, 0x93420109, 0x9343010a, 0xafa70014, 0xafa00018, 0x00021600,
2407 0x00031c00, 0x00431025, 0x34424100, 0xafa20010, 0x8f440100, 0x0e000fe1,
2408 0x3c070400, 0x12200028, 0x24072000, 0x3c090800, 0x3c038000, 0x8f420178,
2409 0x00431024, 0x1440fffd, 0x8ec2414c, 0x26c4414c, 0x2484ffd4, 0xaf420144,
2410 0x8c820030, 0x3c030300, 0xaf420148, 0x2402004e, 0xaf43014c, 0x00001821,
2411 0xa3420152, 0x3c021000, 0xa7430158, 0xaf470154, 0xaf420178, 0x8ec5414c,
2412 0x8d230030, 0x8c860030, 0x24630001, 0xad230030, 0x93420109, 0x9343010a,
2413 0xafa70014, 0xafa00018, 0x00021600, 0x00031c00, 0x00431025, 0x34424e00,
2414 0xafa20010, 0x8f440100, 0x0e000fe1, 0x3c070300, 0x0a000f0b, 0x8fa30024,
2415 0x32820008, 0x10400026, 0x3c090800, 0x24072000, 0x3c038000, 0x8f420178,
2416 0x00431024, 0x1440fffd, 0x8ec2414c, 0x26c4414c, 0x2484ffd4, 0xaf420144,
2417 0x8c820030, 0x3c030200, 0xaf420148, 0x2402004b, 0xaf43014c, 0x00001821,
2418 0xa3420152, 0x3c021000, 0xa7430158, 0xaf470154, 0xaf420178, 0x8ec5414c,
2419 0x8d230030, 0x8c860030, 0x24630001, 0xad230030, 0x93420109, 0x9343010a,
2420 0xafa70014, 0xafa00018, 0x00021600, 0x00031c00, 0x00431025, 0x34424b00,
2421 0xafa20010, 0x8f440100, 0x0e000fe1, 0x3c070200, 0x8fa30024, 0x14600004,
2422 0x8fa40020, 0x32420010, 0x10400004, 0x00000000, 0x8c820004, 0x0040f809,
2423 0x00000000, 0x12000006, 0x8fa30020, 0x8c620008, 0x0040f809, 0x00000000,
2424 0x0a000f4d, 0x8fbf004c, 0x3c030800, 0x8c62413c, 0x30420040, 0x1440002f,
2425 0x8fbf004c, 0x24040040, 0x8f910020, 0x3c038000, 0x8f420178, 0x00431024,
2426 0x1440fffd, 0x8ec2414c, 0x26d0414c, 0x2610ffd4, 0xaf420144, 0x8e020030,
2427 0x00001821, 0xaf420148, 0x24020049, 0xaf51014c, 0xa3420152, 0x3c021000,
2428 0xa7430158, 0xaf440154, 0xaf420178, 0x8ec5414c, 0x8e060030, 0x93420109,
2429 0x9343010a, 0xafa40014, 0xafa00018, 0x00021600, 0x00031c00, 0x00431025,
2430 0x34424900, 0xafa20010, 0x8f440100, 0x0e000fe1, 0x02203821, 0x8f830000,
2431 0x8e020030, 0x8c64017c, 0x02221023, 0x00441023, 0x2c420002, 0x14400005,
2432 0x8fbf004c, 0x0000000d, 0x00000000, 0x240000ca, 0x8fbf004c, 0x8fbe0048,
2433 0x8fb70044, 0x8fb60040, 0x8fb5003c, 0x8fb40038, 0x8fb30034, 0x8fb20030,
2434 0x8fb1002c, 0x8fb00028, 0x03e00008, 0x27bd0050, 0x03e00008, 0x00001021,
2435 0x3c030800, 0x24654120, 0x8ca40004, 0x8c634120, 0x0064102b, 0x54400001,
2436 0x00602021, 0x9743093c, 0x0083102b, 0x54400001, 0x00801821, 0x00001021,
2437 0xaca30008, 0x03e00008, 0xa4a00022, 0x8f850004, 0x97840010, 0x3c030800,
2438 0x24634120, 0x24020008, 0xa462000e, 0x8f820004, 0xa460000c, 0x000420c2,
2439 0x30840008, 0x2c420001, 0x00021023, 0x30420006, 0xac650008, 0x03e00008,
2440 0xa0640020, 0x3c020800, 0x24424120, 0x90450021, 0x94430018, 0x3c021100,
2441 0xac800004, 0x00052c00, 0x24630002, 0x00621825, 0x00a32825, 0x24820008,
2442 0x03e00008, 0xac850000, 0x0000000d, 0x00000000, 0x2400016f, 0x03e00008,
2443 0x00000000, 0x0000000d, 0x00000000, 0x2400017b, 0x03e00008, 0x00000000,
2444 0x03e00008, 0x00000000, 0x3c020800, 0x24424120, 0xac400008, 0xa4400022,
2445 0x03e00008, 0x24020001, 0x3c020800, 0x24424120, 0x24030008, 0xac400008,
2446 0xa440000c, 0xa443000e, 0xa0400020, 0x03e00008, 0x24020004, 0x03e00008,
2447 0x00001021, 0x10c00007, 0x00000000, 0x8ca20000, 0x24c6ffff, 0x24a50004,
2448 0xac820000, 0x14c0fffb, 0x24840004, 0x03e00008, 0x00000000, 0x0a000fb2,
2449 0x00a01021, 0xac860000, 0x24840004, 0x00a01021, 0x1440fffc, 0x24a5ffff,
2450 0x03e00008, 0x00000000, 0x3c0a0800, 0x8d490068, 0x3c050800, 0x24a51090,
2451 0x00093140, 0x00c51021, 0xac440000, 0x8f440e04, 0x00a61021, 0xac440004,
2452 0x97430e08, 0x97420e0c, 0x00a62021, 0x00031c00, 0x00431025, 0xac820008,
2453 0x8f430e10, 0x00801021, 0xac43000c, 0x8f440e14, 0xac440010, 0x8f430e18,
2454 0x3c0800ff, 0xac430014, 0x8f470e1c, 0x3508ffff, 0x25290001, 0xac470018,
2455 0x3c070800, 0x8ce3006c, 0x9344010a, 0x3c026000, 0x24630001, 0xace3006c,
2456 0x8c434448, 0x3129007f, 0x00a62821, 0xad490068, 0x00042600, 0x00681824,
2457 0x00832025, 0x03e00008, 0xaca4001c, 0x8fac0010, 0x8fad0014, 0x8fae0018,
2458 0x3c0b0800, 0x8d6a0060, 0x3c080800, 0x25080078, 0x000a4940, 0x01281021,
2459 0x01091821, 0xac440000, 0x00601021, 0xac650004, 0xac460008, 0xac67000c,
2460 0xac4c0010, 0xac6d0014, 0x3c036000, 0xac4e0018, 0x8c654448, 0x3c040800,
2461 0x8c820064, 0x254a0001, 0x314a007f, 0x01094021, 0xad6a0060, 0x24420001,
2462 0xac820064, 0x03e00008, 0xad05001c, 0x00000000 };
2463
2464static u32 bnx2_TXP_b06FwData[(0x0/4) + 1] = { 0x00000000 };
2465static u32 bnx2_TXP_b06FwRodata[(0x0/4) + 1] = { 0x00000000 };
2466static u32 bnx2_TXP_b06FwBss[(0x194/4) + 1] = { 0x00000000 };
2467static u32 bnx2_TXP_b06FwSbss[(0x34/4) + 1] = { 0x00000000 };
2468
diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c
index 770e28f98fd5..269a5e407349 100644
--- a/drivers/net/bonding/bond_main.c
+++ b/drivers/net/bonding/bond_main.c
@@ -3037,7 +3037,7 @@ static void bond_activebackup_arp_mon(struct net_device *bond_dev)
3037 bond_set_slave_inactive_flags(bond->current_arp_slave); 3037 bond_set_slave_inactive_flags(bond->current_arp_slave);
3038 3038
3039 /* search for next candidate */ 3039 /* search for next candidate */
3040 bond_for_each_slave_from(bond, slave, i, bond->current_arp_slave) { 3040 bond_for_each_slave_from(bond, slave, i, bond->current_arp_slave->next) {
3041 if (IS_UP(slave->dev)) { 3041 if (IS_UP(slave->dev)) {
3042 slave->link = BOND_LINK_BACK; 3042 slave->link = BOND_LINK_BACK;
3043 bond_set_slave_active_flags(slave); 3043 bond_set_slave_active_flags(slave);
diff --git a/drivers/net/dm9000.c b/drivers/net/dm9000.c
new file mode 100644
index 000000000000..f4ba0ffb8637
--- /dev/null
+++ b/drivers/net/dm9000.c
@@ -0,0 +1,1219 @@
1/*
2 * dm9000.c: Version 1.2 03/18/2003
3 *
4 * A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
5 * Copyright (C) 1997 Sten Wang
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
18 *
19 * V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match
20 * 06/22/2001 Support DM9801 progrmming
21 * E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
22 * E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
23 * R17 = (R17 & 0xfff0) | NF + 3
24 * E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
25 * R17 = (R17 & 0xfff0) | NF
26 *
27 * v1.00 modify by simon 2001.9.5
28 * change for kernel 2.4.x
29 *
30 * v1.1 11/09/2001 fix force mode bug
31 *
32 * v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>:
33 * Fixed phy reset.
34 * Added tx/rx 32 bit mode.
35 * Cleaned up for kernel merge.
36 *
37 * 03/03/2004 Sascha Hauer <s.hauer@pengutronix.de>
38 * Port to 2.6 kernel
39 *
40 * 24-Sep-2004 Ben Dooks <ben@simtec.co.uk>
41 * Cleanup of code to remove ifdefs
42 * Allowed platform device data to influence access width
43 * Reformatting areas of code
44 *
45 * 17-Mar-2005 Sascha Hauer <s.hauer@pengutronix.de>
46 * * removed 2.4 style module parameters
47 * * removed removed unused stat counter and fixed
48 * net_device_stats
49 * * introduced tx_timeout function
50 * * reworked locking
51 */
52
53#include <linux/module.h>
54#include <linux/ioport.h>
55#include <linux/netdevice.h>
56#include <linux/etherdevice.h>
57#include <linux/init.h>
58#include <linux/skbuff.h>
59#include <linux/version.h>
60#include <linux/spinlock.h>
61#include <linux/crc32.h>
62#include <linux/mii.h>
63#include <linux/dm9000.h>
64#include <linux/delay.h>
65
66#include <asm/delay.h>
67#include <asm/irq.h>
68#include <asm/io.h>
69
70#include "dm9000.h"
71
72/* Board/System/Debug information/definition ---------------- */
73
74#define DM9000_PHY 0x40 /* PHY address 0x01 */
75
76#define TRUE 1
77#define FALSE 0
78
79#define CARDNAME "dm9000"
80#define PFX CARDNAME ": "
81
82#define DM9000_TIMER_WUT jiffies+(HZ*2) /* timer wakeup time : 2 second */
83
84#define DM9000_DEBUG 0
85
86#if DM9000_DEBUG > 2
87#define PRINTK3(args...) printk(CARDNAME ": " args)
88#else
89#define PRINTK3(args...) do { } while(0)
90#endif
91
92#if DM9000_DEBUG > 1
93#define PRINTK2(args...) printk(CARDNAME ": " args)
94#else
95#define PRINTK2(args...) do { } while(0)
96#endif
97
98#if DM9000_DEBUG > 0
99#define PRINTK1(args...) printk(CARDNAME ": " args)
100#define PRINTK(args...) printk(CARDNAME ": " args)
101#else
102#define PRINTK1(args...) do { } while(0)
103#define PRINTK(args...) printk(KERN_DEBUG args)
104#endif
105
106/*
107 * Transmit timeout, default 5 seconds.
108 */
109static int watchdog = 5000;
110module_param(watchdog, int, 0400);
111MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
112
113/* Structure/enum declaration ------------------------------- */
114typedef struct board_info {
115
116 void __iomem *io_addr; /* Register I/O base address */
117 void __iomem *io_data; /* Data I/O address */
118 u16 irq; /* IRQ */
119
120 u16 tx_pkt_cnt;
121 u16 queue_pkt_len;
122 u16 queue_start_addr;
123 u16 dbug_cnt;
124 u8 io_mode; /* 0:word, 2:byte */
125 u8 phy_addr;
126
127 void (*inblk)(void __iomem *port, void *data, int length);
128 void (*outblk)(void __iomem *port, void *data, int length);
129 void (*dumpblk)(void __iomem *port, int length);
130
131 struct resource *addr_res; /* resources found */
132 struct resource *data_res;
133 struct resource *addr_req; /* resources requested */
134 struct resource *data_req;
135 struct resource *irq_res;
136
137 struct timer_list timer;
138 struct net_device_stats stats;
139 unsigned char srom[128];
140 spinlock_t lock;
141
142 struct mii_if_info mii;
143 u32 msg_enable;
144} board_info_t;
145
146/* function declaration ------------------------------------- */
147static int dm9000_probe(struct device *);
148static int dm9000_open(struct net_device *);
149static int dm9000_start_xmit(struct sk_buff *, struct net_device *);
150static int dm9000_stop(struct net_device *);
151static int dm9000_do_ioctl(struct net_device *, struct ifreq *, int);
152
153
154static void dm9000_timer(unsigned long);
155static void dm9000_init_dm9000(struct net_device *);
156
157static struct net_device_stats *dm9000_get_stats(struct net_device *);
158
159static irqreturn_t dm9000_interrupt(int, void *, struct pt_regs *);
160
161static int dm9000_phy_read(struct net_device *dev, int phyaddr_unsused, int reg);
162static void dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg,
163 int value);
164static u16 read_srom_word(board_info_t *, int);
165static void dm9000_rx(struct net_device *);
166static void dm9000_hash_table(struct net_device *);
167
168//#define DM9000_PROGRAM_EEPROM
169#ifdef DM9000_PROGRAM_EEPROM
170static void program_eeprom(board_info_t * db);
171#endif
172/* DM9000 network board routine ---------------------------- */
173
174static void
175dm9000_reset(board_info_t * db)
176{
177 PRINTK1("dm9000x: resetting\n");
178 /* RESET device */
179 writeb(DM9000_NCR, db->io_addr);
180 udelay(200);
181 writeb(NCR_RST, db->io_data);
182 udelay(200);
183}
184
185/*
186 * Read a byte from I/O port
187 */
188static u8
189ior(board_info_t * db, int reg)
190{
191 writeb(reg, db->io_addr);
192 return readb(db->io_data);
193}
194
195/*
196 * Write a byte to I/O port
197 */
198
199static void
200iow(board_info_t * db, int reg, int value)
201{
202 writeb(reg, db->io_addr);
203 writeb(value, db->io_data);
204}
205
206/* routines for sending block to chip */
207
208static void dm9000_outblk_8bit(void __iomem *reg, void *data, int count)
209{
210 writesb(reg, data, count);
211}
212
213static void dm9000_outblk_16bit(void __iomem *reg, void *data, int count)
214{
215 writesw(reg, data, (count+1) >> 1);
216}
217
218static void dm9000_outblk_32bit(void __iomem *reg, void *data, int count)
219{
220 writesl(reg, data, (count+3) >> 2);
221}
222
223/* input block from chip to memory */
224
225static void dm9000_inblk_8bit(void __iomem *reg, void *data, int count)
226{
227 readsb(reg, data, count+1);
228}
229
230
231static void dm9000_inblk_16bit(void __iomem *reg, void *data, int count)
232{
233 readsw(reg, data, (count+1) >> 1);
234}
235
236static void dm9000_inblk_32bit(void __iomem *reg, void *data, int count)
237{
238 readsl(reg, data, (count+3) >> 2);
239}
240
241/* dump block from chip to null */
242
243static void dm9000_dumpblk_8bit(void __iomem *reg, int count)
244{
245 int i;
246 int tmp;
247
248 for (i = 0; i < count; i++)
249 tmp = readb(reg);
250}
251
252static void dm9000_dumpblk_16bit(void __iomem *reg, int count)
253{
254 int i;
255 int tmp;
256
257 count = (count + 1) >> 1;
258
259 for (i = 0; i < count; i++)
260 tmp = readw(reg);
261}
262
263static void dm9000_dumpblk_32bit(void __iomem *reg, int count)
264{
265 int i;
266 int tmp;
267
268 count = (count + 3) >> 2;
269
270 for (i = 0; i < count; i++)
271 tmp = readl(reg);
272}
273
274/* dm9000_set_io
275 *
276 * select the specified set of io routines to use with the
277 * device
278 */
279
280static void dm9000_set_io(struct board_info *db, int byte_width)
281{
282 /* use the size of the data resource to work out what IO
283 * routines we want to use
284 */
285
286 switch (byte_width) {
287 case 1:
288 db->dumpblk = dm9000_dumpblk_8bit;
289 db->outblk = dm9000_outblk_8bit;
290 db->inblk = dm9000_inblk_8bit;
291 break;
292
293 case 2:
294 db->dumpblk = dm9000_dumpblk_16bit;
295 db->outblk = dm9000_outblk_16bit;
296 db->inblk = dm9000_inblk_16bit;
297 break;
298
299 case 3:
300 printk(KERN_ERR PFX ": 3 byte IO, falling back to 16bit\n");
301 db->dumpblk = dm9000_dumpblk_16bit;
302 db->outblk = dm9000_outblk_16bit;
303 db->inblk = dm9000_inblk_16bit;
304 break;
305
306 case 4:
307 default:
308 db->dumpblk = dm9000_dumpblk_32bit;
309 db->outblk = dm9000_outblk_32bit;
310 db->inblk = dm9000_inblk_32bit;
311 break;
312 }
313}
314
315
316/* Our watchdog timed out. Called by the networking layer */
317static void dm9000_timeout(struct net_device *dev)
318{
319 board_info_t *db = (board_info_t *) dev->priv;
320 u8 reg_save;
321 unsigned long flags;
322
323 /* Save previous register address */
324 reg_save = readb(db->io_addr);
325 spin_lock_irqsave(db->lock,flags);
326
327 netif_stop_queue(dev);
328 dm9000_reset(db);
329 dm9000_init_dm9000(dev);
330 /* We can accept TX packets again */
331 dev->trans_start = jiffies;
332 netif_wake_queue(dev);
333
334 /* Restore previous register address */
335 writeb(reg_save, db->io_addr);
336 spin_unlock_irqrestore(db->lock,flags);
337}
338
339
340/* dm9000_release_board
341 *
342 * release a board, and any mapped resources
343 */
344
345static void
346dm9000_release_board(struct platform_device *pdev, struct board_info *db)
347{
348 if (db->data_res == NULL) {
349 if (db->addr_res != NULL)
350 release_mem_region((unsigned long)db->io_addr, 4);
351 return;
352 }
353
354 /* unmap our resources */
355
356 iounmap(db->io_addr);
357 iounmap(db->io_data);
358
359 /* release the resources */
360
361 if (db->data_req != NULL) {
362 release_resource(db->data_req);
363 kfree(db->data_req);
364 }
365
366 if (db->addr_res != NULL) {
367 release_resource(db->data_req);
368 kfree(db->addr_req);
369 }
370}
371
372#define res_size(_r) (((_r)->end - (_r)->start) + 1)
373
374/*
375 * Search DM9000 board, allocate space and register it
376 */
377static int
378dm9000_probe(struct device *dev)
379{
380 struct platform_device *pdev = to_platform_device(dev);
381 struct dm9000_plat_data *pdata = pdev->dev.platform_data;
382 struct board_info *db; /* Point a board information structure */
383 struct net_device *ndev;
384 unsigned long base;
385 int ret = 0;
386 int iosize;
387 int i;
388 u32 id_val;
389
390 printk(KERN_INFO "%s Ethernet Driver\n", CARDNAME);
391
392 /* Init network device */
393 ndev = alloc_etherdev(sizeof (struct board_info));
394 if (!ndev) {
395 printk("%s: could not allocate device.\n", CARDNAME);
396 return -ENOMEM;
397 }
398
399 SET_MODULE_OWNER(ndev);
400 SET_NETDEV_DEV(ndev, dev);
401
402 PRINTK2("dm9000_probe()");
403
404 /* setup board info structure */
405 db = (struct board_info *) ndev->priv;
406 memset(db, 0, sizeof (*db));
407
408 if (pdev->num_resources < 2) {
409 ret = -ENODEV;
410 goto out;
411 }
412
413 switch (pdev->num_resources) {
414 case 2:
415 base = pdev->resource[0].start;
416
417 if (!request_mem_region(base, 4, ndev->name)) {
418 ret = -EBUSY;
419 goto out;
420 }
421
422 ndev->base_addr = base;
423 ndev->irq = pdev->resource[1].start;
424 db->io_addr = (void *)base;
425 db->io_data = (void *)(base + 4);
426
427 break;
428
429 case 3:
430 db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
431 db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
432 db->irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
433
434 if (db->addr_res == NULL || db->data_res == NULL) {
435 printk(KERN_ERR PFX "insufficient resources\n");
436 ret = -ENOENT;
437 goto out;
438 }
439
440 i = res_size(db->addr_res);
441 db->addr_req = request_mem_region(db->addr_res->start, i,
442 pdev->name);
443
444 if (db->addr_req == NULL) {
445 printk(KERN_ERR PFX "cannot claim address reg area\n");
446 ret = -EIO;
447 goto out;
448 }
449
450 db->io_addr = ioremap(db->addr_res->start, i);
451
452 if (db->io_addr == NULL) {
453 printk(KERN_ERR "failed to ioremap address reg\n");
454 ret = -EINVAL;
455 goto out;
456 }
457
458 iosize = res_size(db->data_res);
459 db->data_req = request_mem_region(db->data_res->start, iosize,
460 pdev->name);
461
462 if (db->data_req == NULL) {
463 printk(KERN_ERR PFX "cannot claim data reg area\n");
464 ret = -EIO;
465 goto out;
466 }
467
468 db->io_data = ioremap(db->data_res->start, iosize);
469
470 if (db->io_data == NULL) {
471 printk(KERN_ERR "failed to ioremap data reg\n");
472 ret = -EINVAL;
473 goto out;
474 }
475
476 /* fill in parameters for net-dev structure */
477
478 ndev->base_addr = (unsigned long)db->io_addr;
479 ndev->irq = db->irq_res->start;
480
481 /* ensure at least we have a default set of IO routines */
482 dm9000_set_io(db, iosize);
483
484 }
485
486 /* check to see if anything is being over-ridden */
487 if (pdata != NULL) {
488 /* check to see if the driver wants to over-ride the
489 * default IO width */
490
491 if (pdata->flags & DM9000_PLATF_8BITONLY)
492 dm9000_set_io(db, 1);
493
494 if (pdata->flags & DM9000_PLATF_16BITONLY)
495 dm9000_set_io(db, 2);
496
497 if (pdata->flags & DM9000_PLATF_32BITONLY)
498 dm9000_set_io(db, 4);
499
500 /* check to see if there are any IO routine
501 * over-rides */
502
503 if (pdata->inblk != NULL)
504 db->inblk = pdata->inblk;
505
506 if (pdata->outblk != NULL)
507 db->outblk = pdata->outblk;
508
509 if (pdata->dumpblk != NULL)
510 db->dumpblk = pdata->dumpblk;
511 }
512
513 dm9000_reset(db);
514
515 /* try two times, DM9000 sometimes gets the first read wrong */
516 for (i = 0; i < 2; i++) {
517 id_val = ior(db, DM9000_VIDL);
518 id_val |= (u32)ior(db, DM9000_VIDH) << 8;
519 id_val |= (u32)ior(db, DM9000_PIDL) << 16;
520 id_val |= (u32)ior(db, DM9000_PIDH) << 24;
521
522 if (id_val == DM9000_ID)
523 break;
524 printk("%s: read wrong id 0x%08x\n", CARDNAME, id_val);
525 }
526
527 if (id_val != DM9000_ID) {
528 printk("%s: wrong id: 0x%08x\n", CARDNAME, id_val);
529 goto release;
530 }
531
532 /* from this point we assume that we have found a DM9000 */
533
534 /* driver system function */
535 ether_setup(ndev);
536
537 ndev->open = &dm9000_open;
538 ndev->hard_start_xmit = &dm9000_start_xmit;
539 ndev->tx_timeout = &dm9000_timeout;
540 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
541 ndev->stop = &dm9000_stop;
542 ndev->get_stats = &dm9000_get_stats;
543 ndev->set_multicast_list = &dm9000_hash_table;
544 ndev->do_ioctl = &dm9000_do_ioctl;
545
546#ifdef DM9000_PROGRAM_EEPROM
547 program_eeprom(db);
548#endif
549 db->msg_enable = NETIF_MSG_LINK;
550 db->mii.phy_id_mask = 0x1f;
551 db->mii.reg_num_mask = 0x1f;
552 db->mii.force_media = 0;
553 db->mii.full_duplex = 0;
554 db->mii.dev = ndev;
555 db->mii.mdio_read = dm9000_phy_read;
556 db->mii.mdio_write = dm9000_phy_write;
557
558 /* Read SROM content */
559 for (i = 0; i < 64; i++)
560 ((u16 *) db->srom)[i] = read_srom_word(db, i);
561
562 /* Set Node Address */
563 for (i = 0; i < 6; i++)
564 ndev->dev_addr[i] = db->srom[i];
565
566 if (!is_valid_ether_addr(ndev->dev_addr))
567 printk("%s: Invalid ethernet MAC address. Please "
568 "set using ifconfig\n", ndev->name);
569
570 dev_set_drvdata(dev, ndev);
571 ret = register_netdev(ndev);
572
573 if (ret == 0) {
574 printk("%s: dm9000 at %p,%p IRQ %d MAC: ",
575 ndev->name, db->io_addr, db->io_data, ndev->irq);
576 for (i = 0; i < 5; i++)
577 printk("%02x:", ndev->dev_addr[i]);
578 printk("%02x\n", ndev->dev_addr[5]);
579 }
580 return 0;
581
582 release:
583 out:
584 printk("%s: not found (%d).\n", CARDNAME, ret);
585
586 dm9000_release_board(pdev, db);
587 kfree(ndev);
588
589 return ret;
590}
591
592/*
593 * Open the interface.
594 * The interface is opened whenever "ifconfig" actives it.
595 */
596static int
597dm9000_open(struct net_device *dev)
598{
599 board_info_t *db = (board_info_t *) dev->priv;
600
601 PRINTK2("entering dm9000_open\n");
602
603 if (request_irq(dev->irq, &dm9000_interrupt, SA_SHIRQ, dev->name, dev))
604 return -EAGAIN;
605
606 /* Initialize DM9000 board */
607 dm9000_reset(db);
608 dm9000_init_dm9000(dev);
609
610 /* Init driver variable */
611 db->dbug_cnt = 0;
612
613 /* set and active a timer process */
614 init_timer(&db->timer);
615 db->timer.expires = DM9000_TIMER_WUT * 2;
616 db->timer.data = (unsigned long) dev;
617 db->timer.function = &dm9000_timer;
618 add_timer(&db->timer);
619
620 mii_check_media(&db->mii, netif_msg_link(db), 1);
621 netif_start_queue(dev);
622
623 return 0;
624}
625
626/*
627 * Initilize dm9000 board
628 */
629static void
630dm9000_init_dm9000(struct net_device *dev)
631{
632 board_info_t *db = (board_info_t *) dev->priv;
633
634 PRINTK1("entering %s\n",__FUNCTION__);
635
636 /* I/O mode */
637 db->io_mode = ior(db, DM9000_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */
638
639 /* GPIO0 on pre-activate PHY */
640 iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */
641 iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */
642 iow(db, DM9000_GPR, 0); /* Enable PHY */
643
644 /* Program operating register */
645 iow(db, DM9000_TCR, 0); /* TX Polling clear */
646 iow(db, DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */
647 iow(db, DM9000_FCR, 0xff); /* Flow Control */
648 iow(db, DM9000_SMCR, 0); /* Special Mode */
649 /* clear TX status */
650 iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
651 iow(db, DM9000_ISR, ISR_CLR_STATUS); /* Clear interrupt status */
652
653 /* Set address filter table */
654 dm9000_hash_table(dev);
655
656 /* Activate DM9000 */
657 iow(db, DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
658 /* Enable TX/RX interrupt mask */
659 iow(db, DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM);
660
661 /* Init Driver variable */
662 db->tx_pkt_cnt = 0;
663 db->queue_pkt_len = 0;
664 dev->trans_start = 0;
665 spin_lock_init(&db->lock);
666}
667
668/*
669 * Hardware start transmission.
670 * Send a packet to media from the upper layer.
671 */
672static int
673dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev)
674{
675 board_info_t *db = (board_info_t *) dev->priv;
676
677 PRINTK3("dm9000_start_xmit\n");
678
679 if (db->tx_pkt_cnt > 1)
680 return 1;
681
682 netif_stop_queue(dev);
683
684 /* Disable all interrupts */
685 iow(db, DM9000_IMR, IMR_PAR);
686
687 /* Move data to DM9000 TX RAM */
688 writeb(DM9000_MWCMD, db->io_addr);
689
690 (db->outblk)(db->io_data, skb->data, skb->len);
691 db->stats.tx_bytes += skb->len;
692
693 /* TX control: First packet immediately send, second packet queue */
694 if (db->tx_pkt_cnt == 0) {
695
696 /* First Packet */
697 db->tx_pkt_cnt++;
698
699 /* Set TX length to DM9000 */
700 iow(db, DM9000_TXPLL, skb->len & 0xff);
701 iow(db, DM9000_TXPLH, (skb->len >> 8) & 0xff);
702
703 /* Issue TX polling command */
704 iow(db, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
705
706 dev->trans_start = jiffies; /* save the time stamp */
707
708 } else {
709 /* Second packet */
710 db->tx_pkt_cnt++;
711 db->queue_pkt_len = skb->len;
712 }
713
714 /* free this SKB */
715 dev_kfree_skb(skb);
716
717 /* Re-enable resource check */
718 if (db->tx_pkt_cnt == 1)
719 netif_wake_queue(dev);
720
721 /* Re-enable interrupt */
722 iow(db, DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM);
723
724 return 0;
725}
726
727static void
728dm9000_shutdown(struct net_device *dev)
729{
730 board_info_t *db = (board_info_t *) dev->priv;
731
732 /* RESET device */
733 dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */
734 iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */
735 iow(db, DM9000_IMR, IMR_PAR); /* Disable all interrupt */
736 iow(db, DM9000_RCR, 0x00); /* Disable RX */
737}
738
739/*
740 * Stop the interface.
741 * The interface is stopped when it is brought.
742 */
743static int
744dm9000_stop(struct net_device *ndev)
745{
746 board_info_t *db = (board_info_t *) ndev->priv;
747
748 PRINTK1("entering %s\n",__FUNCTION__);
749
750 /* deleted timer */
751 del_timer(&db->timer);
752
753 netif_stop_queue(ndev);
754 netif_carrier_off(ndev);
755
756 /* free interrupt */
757 free_irq(ndev->irq, ndev);
758
759 dm9000_shutdown(ndev);
760
761 return 0;
762}
763
764/*
765 * DM9000 interrupt handler
766 * receive the packet to upper layer, free the transmitted packet
767 */
768
769void
770dm9000_tx_done(struct net_device *dev, board_info_t * db)
771{
772 int tx_status = ior(db, DM9000_NSR); /* Got TX status */
773
774 if (tx_status & (NSR_TX2END | NSR_TX1END)) {
775 /* One packet sent complete */
776 db->tx_pkt_cnt--;
777 db->stats.tx_packets++;
778
779 /* Queue packet check & send */
780 if (db->tx_pkt_cnt > 0) {
781 iow(db, DM9000_TXPLL, db->queue_pkt_len & 0xff);
782 iow(db, DM9000_TXPLH, (db->queue_pkt_len >> 8) & 0xff);
783 iow(db, DM9000_TCR, TCR_TXREQ);
784 dev->trans_start = jiffies;
785 }
786 netif_wake_queue(dev);
787 }
788}
789
790static irqreturn_t
791dm9000_interrupt(int irq, void *dev_id, struct pt_regs *regs)
792{
793 struct net_device *dev = dev_id;
794 board_info_t *db;
795 int int_status;
796 u8 reg_save;
797
798 PRINTK3("entering %s\n",__FUNCTION__);
799
800 if (!dev) {
801 PRINTK1("dm9000_interrupt() without DEVICE arg\n");
802 return IRQ_HANDLED;
803 }
804
805 /* A real interrupt coming */
806 db = (board_info_t *) dev->priv;
807 spin_lock(&db->lock);
808
809 /* Save previous register address */
810 reg_save = readb(db->io_addr);
811
812 /* Disable all interrupts */
813 iow(db, DM9000_IMR, IMR_PAR);
814
815 /* Got DM9000 interrupt status */
816 int_status = ior(db, DM9000_ISR); /* Got ISR */
817 iow(db, DM9000_ISR, int_status); /* Clear ISR status */
818
819 /* Received the coming packet */
820 if (int_status & ISR_PRS)
821 dm9000_rx(dev);
822
823 /* Trnasmit Interrupt check */
824 if (int_status & ISR_PTS)
825 dm9000_tx_done(dev, db);
826
827 /* Re-enable interrupt mask */
828 iow(db, DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM);
829
830 /* Restore previous register address */
831 writeb(reg_save, db->io_addr);
832
833 spin_unlock(&db->lock);
834
835 return IRQ_HANDLED;
836}
837
838/*
839 * Get statistics from driver.
840 */
841static struct net_device_stats *
842dm9000_get_stats(struct net_device *dev)
843{
844 board_info_t *db = (board_info_t *) dev->priv;
845 return &db->stats;
846}
847
848/*
849 * Process the upper socket ioctl command
850 */
851static int
852dm9000_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
853{
854 PRINTK1("entering %s\n",__FUNCTION__);
855 return 0;
856}
857
858/*
859 * A periodic timer routine
860 * Dynamic media sense, allocated Rx buffer...
861 */
862static void
863dm9000_timer(unsigned long data)
864{
865 struct net_device *dev = (struct net_device *) data;
866 board_info_t *db = (board_info_t *) dev->priv;
867 u8 reg_save;
868 unsigned long flags;
869
870 PRINTK3("dm9000_timer()\n");
871
872 spin_lock_irqsave(db->lock,flags);
873 /* Save previous register address */
874 reg_save = readb(db->io_addr);
875
876 mii_check_media(&db->mii, netif_msg_link(db), 0);
877
878 /* Restore previous register address */
879 writeb(reg_save, db->io_addr);
880 spin_unlock_irqrestore(db->lock,flags);
881
882 /* Set timer again */
883 db->timer.expires = DM9000_TIMER_WUT;
884 add_timer(&db->timer);
885}
886
887struct dm9000_rxhdr {
888 u16 RxStatus;
889 u16 RxLen;
890} __attribute__((__packed__));
891
892/*
893 * Received a packet and pass to upper layer
894 */
895static void
896dm9000_rx(struct net_device *dev)
897{
898 board_info_t *db = (board_info_t *) dev->priv;
899 struct dm9000_rxhdr rxhdr;
900 struct sk_buff *skb;
901 u8 rxbyte, *rdptr;
902 int GoodPacket;
903 int RxLen;
904
905 /* Check packet ready or not */
906 do {
907 ior(db, DM9000_MRCMDX); /* Dummy read */
908
909 /* Get most updated data */
910 rxbyte = readb(db->io_data);
911
912 /* Status check: this byte must be 0 or 1 */
913 if (rxbyte > DM9000_PKT_RDY) {
914 printk("status check failed: %d\n", rxbyte);
915 iow(db, DM9000_RCR, 0x00); /* Stop Device */
916 iow(db, DM9000_ISR, IMR_PAR); /* Stop INT request */
917 return;
918 }
919
920 if (rxbyte != DM9000_PKT_RDY)
921 return;
922
923 /* A packet ready now & Get status/length */
924 GoodPacket = TRUE;
925 writeb(DM9000_MRCMD, db->io_addr);
926
927 (db->inblk)(db->io_data, &rxhdr, sizeof(rxhdr));
928
929 RxLen = rxhdr.RxLen;
930
931 /* Packet Status check */
932 if (RxLen < 0x40) {
933 GoodPacket = FALSE;
934 PRINTK1("Bad Packet received (runt)\n");
935 }
936
937 if (RxLen > DM9000_PKT_MAX) {
938 PRINTK1("RST: RX Len:%x\n", RxLen);
939 }
940
941 if (rxhdr.RxStatus & 0xbf00) {
942 GoodPacket = FALSE;
943 if (rxhdr.RxStatus & 0x100) {
944 PRINTK1("fifo error\n");
945 db->stats.rx_fifo_errors++;
946 }
947 if (rxhdr.RxStatus & 0x200) {
948 PRINTK1("crc error\n");
949 db->stats.rx_crc_errors++;
950 }
951 if (rxhdr.RxStatus & 0x8000) {
952 PRINTK1("length error\n");
953 db->stats.rx_length_errors++;
954 }
955 }
956
957 /* Move data from DM9000 */
958 if (GoodPacket
959 && ((skb = dev_alloc_skb(RxLen + 4)) != NULL)) {
960 skb->dev = dev;
961 skb_reserve(skb, 2);
962 rdptr = (u8 *) skb_put(skb, RxLen - 4);
963
964 /* Read received packet from RX SRAM */
965
966 (db->inblk)(db->io_data, rdptr, RxLen);
967 db->stats.rx_bytes += RxLen;
968
969 /* Pass to upper layer */
970 skb->protocol = eth_type_trans(skb, dev);
971 netif_rx(skb);
972 db->stats.rx_packets++;
973
974 } else {
975 /* need to dump the packet's data */
976
977 (db->dumpblk)(db->io_data, RxLen);
978 }
979 } while (rxbyte == DM9000_PKT_RDY);
980}
981
982/*
983 * Read a word data from SROM
984 */
985static u16
986read_srom_word(board_info_t * db, int offset)
987{
988 iow(db, DM9000_EPAR, offset);
989 iow(db, DM9000_EPCR, EPCR_ERPRR);
990 mdelay(8); /* according to the datasheet 200us should be enough,
991 but it doesn't work */
992 iow(db, DM9000_EPCR, 0x0);
993 return (ior(db, DM9000_EPDRL) + (ior(db, DM9000_EPDRH) << 8));
994}
995
996#ifdef DM9000_PROGRAM_EEPROM
997/*
998 * Write a word data to SROM
999 */
1000static void
1001write_srom_word(board_info_t * db, int offset, u16 val)
1002{
1003 iow(db, DM9000_EPAR, offset);
1004 iow(db, DM9000_EPDRH, ((val >> 8) & 0xff));
1005 iow(db, DM9000_EPDRL, (val & 0xff));
1006 iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW);
1007 mdelay(8); /* same shit */
1008 iow(db, DM9000_EPCR, 0);
1009}
1010
1011/*
1012 * Only for development:
1013 * Here we write static data to the eeprom in case
1014 * we don't have valid content on a new board
1015 */
1016static void
1017program_eeprom(board_info_t * db)
1018{
1019 u16 eeprom[] = { 0x0c00, 0x007f, 0x1300, /* MAC Address */
1020 0x0000, /* Autoload: accept nothing */
1021 0x0a46, 0x9000, /* Vendor / Product ID */
1022 0x0000, /* pin control */
1023 0x0000,
1024 }; /* Wake-up mode control */
1025 int i;
1026 for (i = 0; i < 8; i++)
1027 write_srom_word(db, i, eeprom[i]);
1028}
1029#endif
1030
1031
1032/*
1033 * Calculate the CRC valude of the Rx packet
1034 * flag = 1 : return the reverse CRC (for the received packet CRC)
1035 * 0 : return the normal CRC (for Hash Table index)
1036 */
1037
1038static unsigned long
1039cal_CRC(unsigned char *Data, unsigned int Len, u8 flag)
1040{
1041
1042 u32 crc = ether_crc_le(Len, Data);
1043
1044 if (flag)
1045 return ~crc;
1046
1047 return crc;
1048}
1049
1050/*
1051 * Set DM9000 multicast address
1052 */
1053static void
1054dm9000_hash_table(struct net_device *dev)
1055{
1056 board_info_t *db = (board_info_t *) dev->priv;
1057 struct dev_mc_list *mcptr = dev->mc_list;
1058 int mc_cnt = dev->mc_count;
1059 u32 hash_val;
1060 u16 i, oft, hash_table[4];
1061 unsigned long flags;
1062
1063 PRINTK2("dm9000_hash_table()\n");
1064
1065 spin_lock_irqsave(&db->lock,flags);
1066
1067 for (i = 0, oft = 0x10; i < 6; i++, oft++)
1068 iow(db, oft, dev->dev_addr[i]);
1069
1070 /* Clear Hash Table */
1071 for (i = 0; i < 4; i++)
1072 hash_table[i] = 0x0;
1073
1074 /* broadcast address */
1075 hash_table[3] = 0x8000;
1076
1077 /* the multicast address in Hash Table : 64 bits */
1078 for (i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1079 hash_val = cal_CRC((char *) mcptr->dmi_addr, 6, 0) & 0x3f;
1080 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1081 }
1082
1083 /* Write the hash table to MAC MD table */
1084 for (i = 0, oft = 0x16; i < 4; i++) {
1085 iow(db, oft++, hash_table[i] & 0xff);
1086 iow(db, oft++, (hash_table[i] >> 8) & 0xff);
1087 }
1088
1089 spin_unlock_irqrestore(&db->lock,flags);
1090}
1091
1092
1093/*
1094 * Read a word from phyxcer
1095 */
1096static int
1097dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg)
1098{
1099 board_info_t *db = (board_info_t *) dev->priv;
1100 unsigned long flags;
1101 int ret;
1102
1103 spin_lock_irqsave(&db->lock,flags);
1104 /* Fill the phyxcer register into REG_0C */
1105 iow(db, DM9000_EPAR, DM9000_PHY | reg);
1106
1107 iow(db, DM9000_EPCR, 0xc); /* Issue phyxcer read command */
1108 udelay(100); /* Wait read complete */
1109 iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */
1110
1111 /* The read data keeps on REG_0D & REG_0E */
1112 ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL);
1113
1114 spin_unlock_irqrestore(&db->lock,flags);
1115
1116 return ret;
1117}
1118
1119/*
1120 * Write a word to phyxcer
1121 */
1122static void
1123dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg, int value)
1124{
1125 board_info_t *db = (board_info_t *) dev->priv;
1126 unsigned long flags;
1127
1128 spin_lock_irqsave(&db->lock,flags);
1129
1130 /* Fill the phyxcer register into REG_0C */
1131 iow(db, DM9000_EPAR, DM9000_PHY | reg);
1132
1133 /* Fill the written data into REG_0D & REG_0E */
1134 iow(db, DM9000_EPDRL, (value & 0xff));
1135 iow(db, DM9000_EPDRH, ((value >> 8) & 0xff));
1136
1137 iow(db, DM9000_EPCR, 0xa); /* Issue phyxcer write command */
1138 udelay(500); /* Wait write complete */
1139 iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */
1140
1141 spin_unlock_irqrestore(&db->lock,flags);
1142}
1143
1144static int
1145dm9000_drv_suspend(struct device *dev, u32 state, u32 level)
1146{
1147 struct net_device *ndev = dev_get_drvdata(dev);
1148
1149 if (ndev && level == SUSPEND_DISABLE) {
1150 if (netif_running(ndev)) {
1151 netif_device_detach(ndev);
1152 dm9000_shutdown(ndev);
1153 }
1154 }
1155 return 0;
1156}
1157
1158static int
1159dm9000_drv_resume(struct device *dev, u32 level)
1160{
1161 struct net_device *ndev = dev_get_drvdata(dev);
1162 board_info_t *db = (board_info_t *) ndev->priv;
1163
1164 if (ndev && level == RESUME_ENABLE) {
1165
1166 if (netif_running(ndev)) {
1167 dm9000_reset(db);
1168 dm9000_init_dm9000(ndev);
1169
1170 netif_device_attach(ndev);
1171 }
1172 }
1173 return 0;
1174}
1175
1176static int
1177dm9000_drv_remove(struct device *dev)
1178{
1179 struct platform_device *pdev = to_platform_device(dev);
1180 struct net_device *ndev = dev_get_drvdata(dev);
1181
1182 dev_set_drvdata(dev, NULL);
1183
1184 unregister_netdev(ndev);
1185 dm9000_release_board(pdev, (board_info_t *) ndev->priv);
1186 kfree(ndev); /* free device structure */
1187
1188 PRINTK1("clean_module() exit\n");
1189
1190 return 0;
1191}
1192
1193static struct device_driver dm9000_driver = {
1194 .name = "dm9000",
1195 .bus = &platform_bus_type,
1196 .probe = dm9000_probe,
1197 .remove = dm9000_drv_remove,
1198 .suspend = dm9000_drv_suspend,
1199 .resume = dm9000_drv_resume,
1200};
1201
1202static int __init
1203dm9000_init(void)
1204{
1205 return driver_register(&dm9000_driver); /* search board and register */
1206}
1207
1208static void __exit
1209dm9000_cleanup(void)
1210{
1211 driver_unregister(&dm9000_driver);
1212}
1213
1214module_init(dm9000_init);
1215module_exit(dm9000_cleanup);
1216
1217MODULE_AUTHOR("Sascha Hauer, Ben Dooks");
1218MODULE_DESCRIPTION("Davicom DM9000 network driver");
1219MODULE_LICENSE("GPL");
diff --git a/drivers/net/dm9000.h b/drivers/net/dm9000.h
new file mode 100644
index 000000000000..82cad360bafc
--- /dev/null
+++ b/drivers/net/dm9000.h
@@ -0,0 +1,135 @@
1/*
2 * dm9000 Ethernet
3 */
4
5#ifndef _DM9000X_H_
6#define _DM9000X_H_
7
8#define DM9000_ID 0x90000A46
9
10/* although the registers are 16 bit, they are 32-bit aligned.
11 */
12
13#define DM9000_NCR 0x00
14#define DM9000_NSR 0x01
15#define DM9000_TCR 0x02
16#define DM9000_TSR1 0x03
17#define DM9000_TSR2 0x04
18#define DM9000_RCR 0x05
19#define DM9000_RSR 0x06
20#define DM9000_ROCR 0x07
21#define DM9000_BPTR 0x08
22#define DM9000_FCTR 0x09
23#define DM9000_FCR 0x0A
24#define DM9000_EPCR 0x0B
25#define DM9000_EPAR 0x0C
26#define DM9000_EPDRL 0x0D
27#define DM9000_EPDRH 0x0E
28#define DM9000_WCR 0x0F
29
30#define DM9000_PAR 0x10
31#define DM9000_MAR 0x16
32
33#define DM9000_GPCR 0x1e
34#define DM9000_GPR 0x1f
35#define DM9000_TRPAL 0x22
36#define DM9000_TRPAH 0x23
37#define DM9000_RWPAL 0x24
38#define DM9000_RWPAH 0x25
39
40#define DM9000_VIDL 0x28
41#define DM9000_VIDH 0x29
42#define DM9000_PIDL 0x2A
43#define DM9000_PIDH 0x2B
44
45#define DM9000_CHIPR 0x2C
46#define DM9000_SMCR 0x2F
47
48#define DM9000_MRCMDX 0xF0
49#define DM9000_MRCMD 0xF2
50#define DM9000_MRRL 0xF4
51#define DM9000_MRRH 0xF5
52#define DM9000_MWCMDX 0xF6
53#define DM9000_MWCMD 0xF8
54#define DM9000_MWRL 0xFA
55#define DM9000_MWRH 0xFB
56#define DM9000_TXPLL 0xFC
57#define DM9000_TXPLH 0xFD
58#define DM9000_ISR 0xFE
59#define DM9000_IMR 0xFF
60
61#define NCR_EXT_PHY (1<<7)
62#define NCR_WAKEEN (1<<6)
63#define NCR_FCOL (1<<4)
64#define NCR_FDX (1<<3)
65#define NCR_LBK (3<<1)
66#define NCR_RST (1<<0)
67
68#define NSR_SPEED (1<<7)
69#define NSR_LINKST (1<<6)
70#define NSR_WAKEST (1<<5)
71#define NSR_TX2END (1<<3)
72#define NSR_TX1END (1<<2)
73#define NSR_RXOV (1<<1)
74
75#define TCR_TJDIS (1<<6)
76#define TCR_EXCECM (1<<5)
77#define TCR_PAD_DIS2 (1<<4)
78#define TCR_CRC_DIS2 (1<<3)
79#define TCR_PAD_DIS1 (1<<2)
80#define TCR_CRC_DIS1 (1<<1)
81#define TCR_TXREQ (1<<0)
82
83#define TSR_TJTO (1<<7)
84#define TSR_LC (1<<6)
85#define TSR_NC (1<<5)
86#define TSR_LCOL (1<<4)
87#define TSR_COL (1<<3)
88#define TSR_EC (1<<2)
89
90#define RCR_WTDIS (1<<6)
91#define RCR_DIS_LONG (1<<5)
92#define RCR_DIS_CRC (1<<4)
93#define RCR_ALL (1<<3)
94#define RCR_RUNT (1<<2)
95#define RCR_PRMSC (1<<1)
96#define RCR_RXEN (1<<0)
97
98#define RSR_RF (1<<7)
99#define RSR_MF (1<<6)
100#define RSR_LCS (1<<5)
101#define RSR_RWTO (1<<4)
102#define RSR_PLE (1<<3)
103#define RSR_AE (1<<2)
104#define RSR_CE (1<<1)
105#define RSR_FOE (1<<0)
106
107#define FCTR_HWOT(ot) (( ot & 0xf ) << 4 )
108#define FCTR_LWOT(ot) ( ot & 0xf )
109
110#define IMR_PAR (1<<7)
111#define IMR_ROOM (1<<3)
112#define IMR_ROM (1<<2)
113#define IMR_PTM (1<<1)
114#define IMR_PRM (1<<0)
115
116#define ISR_ROOS (1<<3)
117#define ISR_ROS (1<<2)
118#define ISR_PTS (1<<1)
119#define ISR_PRS (1<<0)
120#define ISR_CLR_STATUS (ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS)
121
122#define EPCR_REEP (1<<5)
123#define EPCR_WEP (1<<4)
124#define EPCR_EPOS (1<<3)
125#define EPCR_ERPRR (1<<2)
126#define EPCR_ERPRW (1<<1)
127#define EPCR_ERRE (1<<0)
128
129#define GPCR_GEP_CNTL (1<<0)
130
131#define DM9000_PKT_RDY 0x01 /* Packet ready to receive */
132#define DM9000_PKT_MAX 1536 /* Received packet max size */
133
134#endif /* _DM9000X_H_ */
135
diff --git a/drivers/net/e100.c b/drivers/net/e100.c
index 1b68dd5a49b6..4a47df5a9ff9 100644
--- a/drivers/net/e100.c
+++ b/drivers/net/e100.c
@@ -155,9 +155,9 @@
155 155
156#define DRV_NAME "e100" 156#define DRV_NAME "e100"
157#define DRV_EXT "-NAPI" 157#define DRV_EXT "-NAPI"
158#define DRV_VERSION "3.3.6-k2"DRV_EXT 158#define DRV_VERSION "3.4.8-k2"DRV_EXT
159#define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver" 159#define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
160#define DRV_COPYRIGHT "Copyright(c) 1999-2004 Intel Corporation" 160#define DRV_COPYRIGHT "Copyright(c) 1999-2005 Intel Corporation"
161#define PFX DRV_NAME ": " 161#define PFX DRV_NAME ": "
162 162
163#define E100_WATCHDOG_PERIOD (2 * HZ) 163#define E100_WATCHDOG_PERIOD (2 * HZ)
@@ -210,11 +210,17 @@ static struct pci_device_id e100_id_table[] = {
210 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6), 210 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
211 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6), 211 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
212 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6), 212 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
213 INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),
214 INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),
215 INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),
216 INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),
217 INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),
213 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0), 218 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
214 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0), 219 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
215 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2), 220 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
216 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2), 221 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
217 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2), 222 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
223 INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),
218 { 0, } 224 { 0, }
219}; 225};
220MODULE_DEVICE_TABLE(pci, e100_id_table); 226MODULE_DEVICE_TABLE(pci, e100_id_table);
@@ -269,6 +275,12 @@ enum scb_status {
269 rus_mask = 0x3C, 275 rus_mask = 0x3C,
270}; 276};
271 277
278enum ru_state {
279 RU_SUSPENDED = 0,
280 RU_RUNNING = 1,
281 RU_UNINITIALIZED = -1,
282};
283
272enum scb_stat_ack { 284enum scb_stat_ack {
273 stat_ack_not_ours = 0x00, 285 stat_ack_not_ours = 0x00,
274 stat_ack_sw_gen = 0x04, 286 stat_ack_sw_gen = 0x04,
@@ -510,7 +522,7 @@ struct nic {
510 struct rx *rx_to_use; 522 struct rx *rx_to_use;
511 struct rx *rx_to_clean; 523 struct rx *rx_to_clean;
512 struct rfd blank_rfd; 524 struct rfd blank_rfd;
513 int ru_running; 525 enum ru_state ru_running;
514 526
515 spinlock_t cb_lock ____cacheline_aligned; 527 spinlock_t cb_lock ____cacheline_aligned;
516 spinlock_t cmd_lock; 528 spinlock_t cmd_lock;
@@ -539,6 +551,7 @@ struct nic {
539 struct timer_list watchdog; 551 struct timer_list watchdog;
540 struct timer_list blink_timer; 552 struct timer_list blink_timer;
541 struct mii_if_info mii; 553 struct mii_if_info mii;
554 struct work_struct tx_timeout_task;
542 enum loopback loopback; 555 enum loopback loopback;
543 556
544 struct mem *mem; 557 struct mem *mem;
@@ -770,7 +783,7 @@ static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
770 return 0; 783 return 0;
771} 784}
772 785
773#define E100_WAIT_SCB_TIMEOUT 40 786#define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */
774static inline int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr) 787static inline int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
775{ 788{
776 unsigned long flags; 789 unsigned long flags;
@@ -840,6 +853,10 @@ static inline int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
840 * because the controller is too busy, so 853 * because the controller is too busy, so
841 * let's just queue the command and try again 854 * let's just queue the command and try again
842 * when another command is scheduled. */ 855 * when another command is scheduled. */
856 if(err == -ENOSPC) {
857 //request a reset
858 schedule_work(&nic->tx_timeout_task);
859 }
843 break; 860 break;
844 } else { 861 } else {
845 nic->cuc_cmd = cuc_resume; 862 nic->cuc_cmd = cuc_resume;
@@ -884,7 +901,7 @@ static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
884 901
885static void e100_get_defaults(struct nic *nic) 902static void e100_get_defaults(struct nic *nic)
886{ 903{
887 struct param_range rfds = { .min = 64, .max = 256, .count = 64 }; 904 struct param_range rfds = { .min = 16, .max = 256, .count = 64 };
888 struct param_range cbs = { .min = 64, .max = 256, .count = 64 }; 905 struct param_range cbs = { .min = 64, .max = 256, .count = 64 };
889 906
890 pci_read_config_byte(nic->pdev, PCI_REVISION_ID, &nic->rev_id); 907 pci_read_config_byte(nic->pdev, PCI_REVISION_ID, &nic->rev_id);
@@ -899,8 +916,9 @@ static void e100_get_defaults(struct nic *nic)
899 /* Quadwords to DMA into FIFO before starting frame transmit */ 916 /* Quadwords to DMA into FIFO before starting frame transmit */
900 nic->tx_threshold = 0xE0; 917 nic->tx_threshold = 0xE0;
901 918
902 nic->tx_command = cpu_to_le16(cb_tx | cb_i | cb_tx_sf | 919 /* no interrupt for every tx completion, delay = 256us if not 557*/
903 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : 0)); 920 nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |
921 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));
904 922
905 /* Template for a freshly allocated RFD */ 923 /* Template for a freshly allocated RFD */
906 nic->blank_rfd.command = cpu_to_le16(cb_el); 924 nic->blank_rfd.command = cpu_to_le16(cb_el);
@@ -964,7 +982,8 @@ static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
964 if(nic->flags & multicast_all) 982 if(nic->flags & multicast_all)
965 config->multicast_all = 0x1; /* 1=accept, 0=no */ 983 config->multicast_all = 0x1; /* 1=accept, 0=no */
966 984
967 if(!(nic->flags & wol_magic)) 985 /* disable WoL when up */
986 if(netif_running(nic->netdev) || !(nic->flags & wol_magic))
968 config->magic_packet_disable = 0x1; /* 1=off, 0=on */ 987 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
969 988
970 if(nic->mac >= mac_82558_D101_A4) { 989 if(nic->mac >= mac_82558_D101_A4) {
@@ -1203,7 +1222,9 @@ static void e100_update_stats(struct nic *nic)
1203 } 1222 }
1204 } 1223 }
1205 1224
1206 e100_exec_cmd(nic, cuc_dump_reset, 0); 1225
1226 if(e100_exec_cmd(nic, cuc_dump_reset, 0))
1227 DPRINTK(TX_ERR, DEBUG, "exec cuc_dump_reset failed\n");
1207} 1228}
1208 1229
1209static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex) 1230static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
@@ -1279,12 +1300,15 @@ static inline void e100_xmit_prepare(struct nic *nic, struct cb *cb,
1279 struct sk_buff *skb) 1300 struct sk_buff *skb)
1280{ 1301{
1281 cb->command = nic->tx_command; 1302 cb->command = nic->tx_command;
1303 /* interrupt every 16 packets regardless of delay */
1304 if((nic->cbs_avail & ~15) == nic->cbs_avail) cb->command |= cb_i;
1282 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd); 1305 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1283 cb->u.tcb.tcb_byte_count = 0; 1306 cb->u.tcb.tcb_byte_count = 0;
1284 cb->u.tcb.threshold = nic->tx_threshold; 1307 cb->u.tcb.threshold = nic->tx_threshold;
1285 cb->u.tcb.tbd_count = 1; 1308 cb->u.tcb.tbd_count = 1;
1286 cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev, 1309 cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
1287 skb->data, skb->len, PCI_DMA_TODEVICE)); 1310 skb->data, skb->len, PCI_DMA_TODEVICE));
1311 // check for mapping failure?
1288 cb->u.tcb.tbd.size = cpu_to_le16(skb->len); 1312 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1289} 1313}
1290 1314
@@ -1297,7 +1321,8 @@ static int e100_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1297 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang. 1321 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1298 Issue a NOP command followed by a 1us delay before 1322 Issue a NOP command followed by a 1us delay before
1299 issuing the Tx command. */ 1323 issuing the Tx command. */
1300 e100_exec_cmd(nic, cuc_nop, 0); 1324 if(e100_exec_cmd(nic, cuc_nop, 0))
1325 DPRINTK(TX_ERR, DEBUG, "exec cuc_nop failed\n");
1301 udelay(1); 1326 udelay(1);
1302 } 1327 }
1303 1328
@@ -1415,12 +1440,18 @@ static int e100_alloc_cbs(struct nic *nic)
1415 return 0; 1440 return 0;
1416} 1441}
1417 1442
1418static inline void e100_start_receiver(struct nic *nic) 1443static inline void e100_start_receiver(struct nic *nic, struct rx *rx)
1419{ 1444{
1445 if(!nic->rxs) return;
1446 if(RU_SUSPENDED != nic->ru_running) return;
1447
1448 /* handle init time starts */
1449 if(!rx) rx = nic->rxs;
1450
1420 /* (Re)start RU if suspended or idle and RFA is non-NULL */ 1451 /* (Re)start RU if suspended or idle and RFA is non-NULL */
1421 if(!nic->ru_running && nic->rx_to_clean->skb) { 1452 if(rx->skb) {
1422 e100_exec_cmd(nic, ruc_start, nic->rx_to_clean->dma_addr); 1453 e100_exec_cmd(nic, ruc_start, rx->dma_addr);
1423 nic->ru_running = 1; 1454 nic->ru_running = RU_RUNNING;
1424 } 1455 }
1425} 1456}
1426 1457
@@ -1437,6 +1468,13 @@ static inline int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1437 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data, 1468 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1438 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL); 1469 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1439 1470
1471 if(pci_dma_mapping_error(rx->dma_addr)) {
1472 dev_kfree_skb_any(rx->skb);
1473 rx->skb = 0;
1474 rx->dma_addr = 0;
1475 return -ENOMEM;
1476 }
1477
1440 /* Link the RFD to end of RFA by linking previous RFD to 1478 /* Link the RFD to end of RFA by linking previous RFD to
1441 * this one, and clearing EL bit of previous. */ 1479 * this one, and clearing EL bit of previous. */
1442 if(rx->prev->skb) { 1480 if(rx->prev->skb) {
@@ -1471,7 +1509,7 @@ static inline int e100_rx_indicate(struct nic *nic, struct rx *rx,
1471 1509
1472 /* If data isn't ready, nothing to indicate */ 1510 /* If data isn't ready, nothing to indicate */
1473 if(unlikely(!(rfd_status & cb_complete))) 1511 if(unlikely(!(rfd_status & cb_complete)))
1474 return -EAGAIN; 1512 return -ENODATA;
1475 1513
1476 /* Get actual data size */ 1514 /* Get actual data size */
1477 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF; 1515 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
@@ -1482,6 +1520,10 @@ static inline int e100_rx_indicate(struct nic *nic, struct rx *rx,
1482 pci_unmap_single(nic->pdev, rx->dma_addr, 1520 pci_unmap_single(nic->pdev, rx->dma_addr,
1483 RFD_BUF_LEN, PCI_DMA_FROMDEVICE); 1521 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
1484 1522
1523 /* this allows for a fast restart without re-enabling interrupts */
1524 if(le16_to_cpu(rfd->command) & cb_el)
1525 nic->ru_running = RU_SUSPENDED;
1526
1485 /* Pull off the RFD and put the actual data (minus eth hdr) */ 1527 /* Pull off the RFD and put the actual data (minus eth hdr) */
1486 skb_reserve(skb, sizeof(struct rfd)); 1528 skb_reserve(skb, sizeof(struct rfd));
1487 skb_put(skb, actual_size); 1529 skb_put(skb, actual_size);
@@ -1514,20 +1556,45 @@ static inline void e100_rx_clean(struct nic *nic, unsigned int *work_done,
1514 unsigned int work_to_do) 1556 unsigned int work_to_do)
1515{ 1557{
1516 struct rx *rx; 1558 struct rx *rx;
1559 int restart_required = 0;
1560 struct rx *rx_to_start = NULL;
1561
1562 /* are we already rnr? then pay attention!!! this ensures that
1563 * the state machine progression never allows a start with a
1564 * partially cleaned list, avoiding a race between hardware
1565 * and rx_to_clean when in NAPI mode */
1566 if(RU_SUSPENDED == nic->ru_running)
1567 restart_required = 1;
1517 1568
1518 /* Indicate newly arrived packets */ 1569 /* Indicate newly arrived packets */
1519 for(rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) { 1570 for(rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
1520 if(e100_rx_indicate(nic, rx, work_done, work_to_do)) 1571 int err = e100_rx_indicate(nic, rx, work_done, work_to_do);
1572 if(-EAGAIN == err) {
1573 /* hit quota so have more work to do, restart once
1574 * cleanup is complete */
1575 restart_required = 0;
1576 break;
1577 } else if(-ENODATA == err)
1521 break; /* No more to clean */ 1578 break; /* No more to clean */
1522 } 1579 }
1523 1580
1581 /* save our starting point as the place we'll restart the receiver */
1582 if(restart_required)
1583 rx_to_start = nic->rx_to_clean;
1584
1524 /* Alloc new skbs to refill list */ 1585 /* Alloc new skbs to refill list */
1525 for(rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) { 1586 for(rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
1526 if(unlikely(e100_rx_alloc_skb(nic, rx))) 1587 if(unlikely(e100_rx_alloc_skb(nic, rx)))
1527 break; /* Better luck next time (see watchdog) */ 1588 break; /* Better luck next time (see watchdog) */
1528 } 1589 }
1529 1590
1530 e100_start_receiver(nic); 1591 if(restart_required) {
1592 // ack the rnr?
1593 writeb(stat_ack_rnr, &nic->csr->scb.stat_ack);
1594 e100_start_receiver(nic, rx_to_start);
1595 if(work_done)
1596 (*work_done)++;
1597 }
1531} 1598}
1532 1599
1533static void e100_rx_clean_list(struct nic *nic) 1600static void e100_rx_clean_list(struct nic *nic)
@@ -1535,6 +1602,8 @@ static void e100_rx_clean_list(struct nic *nic)
1535 struct rx *rx; 1602 struct rx *rx;
1536 unsigned int i, count = nic->params.rfds.count; 1603 unsigned int i, count = nic->params.rfds.count;
1537 1604
1605 nic->ru_running = RU_UNINITIALIZED;
1606
1538 if(nic->rxs) { 1607 if(nic->rxs) {
1539 for(rx = nic->rxs, i = 0; i < count; rx++, i++) { 1608 for(rx = nic->rxs, i = 0; i < count; rx++, i++) {
1540 if(rx->skb) { 1609 if(rx->skb) {
@@ -1548,7 +1617,6 @@ static void e100_rx_clean_list(struct nic *nic)
1548 } 1617 }
1549 1618
1550 nic->rx_to_use = nic->rx_to_clean = NULL; 1619 nic->rx_to_use = nic->rx_to_clean = NULL;
1551 nic->ru_running = 0;
1552} 1620}
1553 1621
1554static int e100_rx_alloc_list(struct nic *nic) 1622static int e100_rx_alloc_list(struct nic *nic)
@@ -1557,6 +1625,7 @@ static int e100_rx_alloc_list(struct nic *nic)
1557 unsigned int i, count = nic->params.rfds.count; 1625 unsigned int i, count = nic->params.rfds.count;
1558 1626
1559 nic->rx_to_use = nic->rx_to_clean = NULL; 1627 nic->rx_to_use = nic->rx_to_clean = NULL;
1628 nic->ru_running = RU_UNINITIALIZED;
1560 1629
1561 if(!(nic->rxs = kmalloc(sizeof(struct rx) * count, GFP_ATOMIC))) 1630 if(!(nic->rxs = kmalloc(sizeof(struct rx) * count, GFP_ATOMIC)))
1562 return -ENOMEM; 1631 return -ENOMEM;
@@ -1572,6 +1641,7 @@ static int e100_rx_alloc_list(struct nic *nic)
1572 } 1641 }
1573 1642
1574 nic->rx_to_use = nic->rx_to_clean = nic->rxs; 1643 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
1644 nic->ru_running = RU_SUSPENDED;
1575 1645
1576 return 0; 1646 return 0;
1577} 1647}
@@ -1593,7 +1663,7 @@ static irqreturn_t e100_intr(int irq, void *dev_id, struct pt_regs *regs)
1593 1663
1594 /* We hit Receive No Resource (RNR); restart RU after cleaning */ 1664 /* We hit Receive No Resource (RNR); restart RU after cleaning */
1595 if(stat_ack & stat_ack_rnr) 1665 if(stat_ack & stat_ack_rnr)
1596 nic->ru_running = 0; 1666 nic->ru_running = RU_SUSPENDED;
1597 1667
1598 e100_disable_irq(nic); 1668 e100_disable_irq(nic);
1599 netif_rx_schedule(netdev); 1669 netif_rx_schedule(netdev);
@@ -1663,6 +1733,7 @@ static int e100_change_mtu(struct net_device *netdev, int new_mtu)
1663 return 0; 1733 return 0;
1664} 1734}
1665 1735
1736#ifdef CONFIG_PM
1666static int e100_asf(struct nic *nic) 1737static int e100_asf(struct nic *nic)
1667{ 1738{
1668 /* ASF can be enabled from eeprom */ 1739 /* ASF can be enabled from eeprom */
@@ -1671,6 +1742,7 @@ static int e100_asf(struct nic *nic)
1671 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) && 1742 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
1672 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE)); 1743 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE));
1673} 1744}
1745#endif
1674 1746
1675static int e100_up(struct nic *nic) 1747static int e100_up(struct nic *nic)
1676{ 1748{
@@ -1683,13 +1755,16 @@ static int e100_up(struct nic *nic)
1683 if((err = e100_hw_init(nic))) 1755 if((err = e100_hw_init(nic)))
1684 goto err_clean_cbs; 1756 goto err_clean_cbs;
1685 e100_set_multicast_list(nic->netdev); 1757 e100_set_multicast_list(nic->netdev);
1686 e100_start_receiver(nic); 1758 e100_start_receiver(nic, 0);
1687 mod_timer(&nic->watchdog, jiffies); 1759 mod_timer(&nic->watchdog, jiffies);
1688 if((err = request_irq(nic->pdev->irq, e100_intr, SA_SHIRQ, 1760 if((err = request_irq(nic->pdev->irq, e100_intr, SA_SHIRQ,
1689 nic->netdev->name, nic->netdev))) 1761 nic->netdev->name, nic->netdev)))
1690 goto err_no_irq; 1762 goto err_no_irq;
1691 e100_enable_irq(nic);
1692 netif_wake_queue(nic->netdev); 1763 netif_wake_queue(nic->netdev);
1764 netif_poll_enable(nic->netdev);
1765 /* enable ints _after_ enabling poll, preventing a race between
1766 * disable ints+schedule */
1767 e100_enable_irq(nic);
1693 return 0; 1768 return 0;
1694 1769
1695err_no_irq: 1770err_no_irq:
@@ -1703,11 +1778,13 @@ err_rx_clean_list:
1703 1778
1704static void e100_down(struct nic *nic) 1779static void e100_down(struct nic *nic)
1705{ 1780{
1781 /* wait here for poll to complete */
1782 netif_poll_disable(nic->netdev);
1783 netif_stop_queue(nic->netdev);
1706 e100_hw_reset(nic); 1784 e100_hw_reset(nic);
1707 free_irq(nic->pdev->irq, nic->netdev); 1785 free_irq(nic->pdev->irq, nic->netdev);
1708 del_timer_sync(&nic->watchdog); 1786 del_timer_sync(&nic->watchdog);
1709 netif_carrier_off(nic->netdev); 1787 netif_carrier_off(nic->netdev);
1710 netif_stop_queue(nic->netdev);
1711 e100_clean_cbs(nic); 1788 e100_clean_cbs(nic);
1712 e100_rx_clean_list(nic); 1789 e100_rx_clean_list(nic);
1713} 1790}
@@ -1716,6 +1793,15 @@ static void e100_tx_timeout(struct net_device *netdev)
1716{ 1793{
1717 struct nic *nic = netdev_priv(netdev); 1794 struct nic *nic = netdev_priv(netdev);
1718 1795
1796 /* Reset outside of interrupt context, to avoid request_irq
1797 * in interrupt context */
1798 schedule_work(&nic->tx_timeout_task);
1799}
1800
1801static void e100_tx_timeout_task(struct net_device *netdev)
1802{
1803 struct nic *nic = netdev_priv(netdev);
1804
1719 DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n", 1805 DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n",
1720 readb(&nic->csr->scb.status)); 1806 readb(&nic->csr->scb.status));
1721 e100_down(netdev_priv(netdev)); 1807 e100_down(netdev_priv(netdev));
@@ -1749,7 +1835,7 @@ static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
1749 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 1835 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
1750 BMCR_LOOPBACK); 1836 BMCR_LOOPBACK);
1751 1837
1752 e100_start_receiver(nic); 1838 e100_start_receiver(nic, 0);
1753 1839
1754 if(!(skb = dev_alloc_skb(ETH_DATA_LEN))) { 1840 if(!(skb = dev_alloc_skb(ETH_DATA_LEN))) {
1755 err = -ENOMEM; 1841 err = -ENOMEM;
@@ -1869,7 +1955,6 @@ static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1869 else 1955 else
1870 nic->flags &= ~wol_magic; 1956 nic->flags &= ~wol_magic;
1871 1957
1872 pci_enable_wake(nic->pdev, 0, nic->flags & (wol_magic | e100_asf(nic)));
1873 e100_exec_cb(nic, NULL, e100_configure); 1958 e100_exec_cb(nic, NULL, e100_configure);
1874 1959
1875 return 0; 1960 return 0;
@@ -2223,6 +2308,7 @@ static int __devinit e100_probe(struct pci_dev *pdev,
2223 2308
2224 e100_get_defaults(nic); 2309 e100_get_defaults(nic);
2225 2310
2311 /* locks must be initialized before calling hw_reset */
2226 spin_lock_init(&nic->cb_lock); 2312 spin_lock_init(&nic->cb_lock);
2227 spin_lock_init(&nic->cmd_lock); 2313 spin_lock_init(&nic->cmd_lock);
2228 2314
@@ -2240,6 +2326,9 @@ static int __devinit e100_probe(struct pci_dev *pdev,
2240 nic->blink_timer.function = e100_blink_led; 2326 nic->blink_timer.function = e100_blink_led;
2241 nic->blink_timer.data = (unsigned long)nic; 2327 nic->blink_timer.data = (unsigned long)nic;
2242 2328
2329 INIT_WORK(&nic->tx_timeout_task,
2330 (void (*)(void *))e100_tx_timeout_task, netdev);
2331
2243 if((err = e100_alloc(nic))) { 2332 if((err = e100_alloc(nic))) {
2244 DPRINTK(PROBE, ERR, "Cannot alloc driver memory, aborting.\n"); 2333 DPRINTK(PROBE, ERR, "Cannot alloc driver memory, aborting.\n");
2245 goto err_out_iounmap; 2334 goto err_out_iounmap;
@@ -2263,7 +2352,8 @@ static int __devinit e100_probe(struct pci_dev *pdev,
2263 (nic->eeprom[eeprom_id] & eeprom_id_wol)) 2352 (nic->eeprom[eeprom_id] & eeprom_id_wol))
2264 nic->flags |= wol_magic; 2353 nic->flags |= wol_magic;
2265 2354
2266 pci_enable_wake(pdev, 0, nic->flags & (wol_magic | e100_asf(nic))); 2355 /* ack any pending wake events, disable PME */
2356 pci_enable_wake(pdev, 0, 0);
2267 2357
2268 strcpy(netdev->name, "eth%d"); 2358 strcpy(netdev->name, "eth%d");
2269 if((err = register_netdev(netdev))) { 2359 if((err = register_netdev(netdev))) {
@@ -2335,7 +2425,10 @@ static int e100_resume(struct pci_dev *pdev)
2335 2425
2336 pci_set_power_state(pdev, PCI_D0); 2426 pci_set_power_state(pdev, PCI_D0);
2337 pci_restore_state(pdev); 2427 pci_restore_state(pdev);
2338 e100_hw_init(nic); 2428 /* ack any pending wake events, disable PME */
2429 pci_enable_wake(pdev, 0, 0);
2430 if(e100_hw_init(nic))
2431 DPRINTK(HW, ERR, "e100_hw_init failed\n");
2339 2432
2340 netif_device_attach(netdev); 2433 netif_device_attach(netdev);
2341 if(netif_running(netdev)) 2434 if(netif_running(netdev))
@@ -2345,6 +2438,21 @@ static int e100_resume(struct pci_dev *pdev)
2345} 2438}
2346#endif 2439#endif
2347 2440
2441
2442static void e100_shutdown(struct device *dev)
2443{
2444 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
2445 struct net_device *netdev = pci_get_drvdata(pdev);
2446 struct nic *nic = netdev_priv(netdev);
2447
2448#ifdef CONFIG_PM
2449 pci_enable_wake(pdev, 0, nic->flags & (wol_magic | e100_asf(nic)));
2450#else
2451 pci_enable_wake(pdev, 0, nic->flags & (wol_magic));
2452#endif
2453}
2454
2455
2348static struct pci_driver e100_driver = { 2456static struct pci_driver e100_driver = {
2349 .name = DRV_NAME, 2457 .name = DRV_NAME,
2350 .id_table = e100_id_table, 2458 .id_table = e100_id_table,
@@ -2354,6 +2462,11 @@ static struct pci_driver e100_driver = {
2354 .suspend = e100_suspend, 2462 .suspend = e100_suspend,
2355 .resume = e100_resume, 2463 .resume = e100_resume,
2356#endif 2464#endif
2465
2466 .driver = {
2467 .shutdown = e100_shutdown,
2468 }
2469
2357}; 2470};
2358 2471
2359static int __init e100_init_module(void) 2472static int __init e100_init_module(void)
diff --git a/drivers/net/e1000/e1000.h b/drivers/net/e1000/e1000.h
index 148930d4e9bd..af1e82c5b808 100644
--- a/drivers/net/e1000/e1000.h
+++ b/drivers/net/e1000/e1000.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 3
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved. 4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free 7 under the terms of the GNU General Public License as published by the Free
@@ -112,6 +112,8 @@ struct e1000_adapter;
112#define E1000_MAX_82544_RXD 4096 112#define E1000_MAX_82544_RXD 4096
113 113
114/* Supported Rx Buffer Sizes */ 114/* Supported Rx Buffer Sizes */
115#define E1000_RXBUFFER_128 128 /* Used for packet split */
116#define E1000_RXBUFFER_256 256 /* Used for packet split */
115#define E1000_RXBUFFER_2048 2048 117#define E1000_RXBUFFER_2048 2048
116#define E1000_RXBUFFER_4096 4096 118#define E1000_RXBUFFER_4096 4096
117#define E1000_RXBUFFER_8192 8192 119#define E1000_RXBUFFER_8192 8192
@@ -137,15 +139,19 @@ struct e1000_adapter;
137/* How many Rx Buffers do we bundle into one write to the hardware ? */ 139/* How many Rx Buffers do we bundle into one write to the hardware ? */
138#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 140#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
139 141
140#define AUTO_ALL_MODES 0 142#define AUTO_ALL_MODES 0
141#define E1000_EEPROM_82544_APM 0x0004 143#define E1000_EEPROM_82544_APM 0x0400
142#define E1000_EEPROM_APME 0x0400 144#define E1000_EEPROM_APME 0x0400
143 145
144#ifndef E1000_MASTER_SLAVE 146#ifndef E1000_MASTER_SLAVE
145/* Switch to override PHY master/slave setting */ 147/* Switch to override PHY master/slave setting */
146#define E1000_MASTER_SLAVE e1000_ms_hw_default 148#define E1000_MASTER_SLAVE e1000_ms_hw_default
147#endif 149#endif
148 150
151#define E1000_MNG_VLAN_NONE -1
152/* Number of packet split data buffers (not including the header buffer) */
153#define PS_PAGE_BUFFERS MAX_PS_BUFFERS-1
154
149/* only works for sizes that are powers of 2 */ 155/* only works for sizes that are powers of 2 */
150#define E1000_ROUNDUP(i, size) ((i) = (((i) + (size) - 1) & ~((size) - 1))) 156#define E1000_ROUNDUP(i, size) ((i) = (((i) + (size) - 1) & ~((size) - 1)))
151 157
@@ -159,6 +165,9 @@ struct e1000_buffer {
159 uint16_t next_to_watch; 165 uint16_t next_to_watch;
160}; 166};
161 167
168struct e1000_ps_page { struct page *ps_page[MAX_PS_BUFFERS]; };
169struct e1000_ps_page_dma { uint64_t ps_page_dma[MAX_PS_BUFFERS]; };
170
162struct e1000_desc_ring { 171struct e1000_desc_ring {
163 /* pointer to the descriptor ring memory */ 172 /* pointer to the descriptor ring memory */
164 void *desc; 173 void *desc;
@@ -174,12 +183,19 @@ struct e1000_desc_ring {
174 unsigned int next_to_clean; 183 unsigned int next_to_clean;
175 /* array of buffer information structs */ 184 /* array of buffer information structs */
176 struct e1000_buffer *buffer_info; 185 struct e1000_buffer *buffer_info;
186 /* arrays of page information for packet split */
187 struct e1000_ps_page *ps_page;
188 struct e1000_ps_page_dma *ps_page_dma;
177}; 189};
178 190
179#define E1000_DESC_UNUSED(R) \ 191#define E1000_DESC_UNUSED(R) \
180 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 192 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
181 (R)->next_to_clean - (R)->next_to_use - 1) 193 (R)->next_to_clean - (R)->next_to_use - 1)
182 194
195#define E1000_RX_DESC_PS(R, i) \
196 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
197#define E1000_RX_DESC_EXT(R, i) \
198 (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
183#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) 199#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
184#define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc) 200#define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc)
185#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc) 201#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
@@ -192,6 +208,7 @@ struct e1000_adapter {
192 struct timer_list watchdog_timer; 208 struct timer_list watchdog_timer;
193 struct timer_list phy_info_timer; 209 struct timer_list phy_info_timer;
194 struct vlan_group *vlgrp; 210 struct vlan_group *vlgrp;
211 uint16_t mng_vlan_id;
195 uint32_t bd_number; 212 uint32_t bd_number;
196 uint32_t rx_buffer_len; 213 uint32_t rx_buffer_len;
197 uint32_t part_num; 214 uint32_t part_num;
@@ -228,14 +245,23 @@ struct e1000_adapter {
228 boolean_t detect_tx_hung; 245 boolean_t detect_tx_hung;
229 246
230 /* RX */ 247 /* RX */
248#ifdef CONFIG_E1000_NAPI
249 boolean_t (*clean_rx) (struct e1000_adapter *adapter, int *work_done,
250 int work_to_do);
251#else
252 boolean_t (*clean_rx) (struct e1000_adapter *adapter);
253#endif
254 void (*alloc_rx_buf) (struct e1000_adapter *adapter);
231 struct e1000_desc_ring rx_ring; 255 struct e1000_desc_ring rx_ring;
232 uint64_t hw_csum_err; 256 uint64_t hw_csum_err;
233 uint64_t hw_csum_good; 257 uint64_t hw_csum_good;
234 uint32_t rx_int_delay; 258 uint32_t rx_int_delay;
235 uint32_t rx_abs_int_delay; 259 uint32_t rx_abs_int_delay;
236 boolean_t rx_csum; 260 boolean_t rx_csum;
261 boolean_t rx_ps;
237 uint32_t gorcl; 262 uint32_t gorcl;
238 uint64_t gorcl_old; 263 uint64_t gorcl_old;
264 uint16_t rx_ps_bsize0;
239 265
240 /* Interrupt Throttle Rate */ 266 /* Interrupt Throttle Rate */
241 uint32_t itr; 267 uint32_t itr;
@@ -257,5 +283,8 @@ struct e1000_adapter {
257 283
258 284
259 int msg_enable; 285 int msg_enable;
286#ifdef CONFIG_PCI_MSI
287 boolean_t have_msi;
288#endif
260}; 289};
261#endif /* _E1000_H_ */ 290#endif /* _E1000_H_ */
diff --git a/drivers/net/e1000/e1000_ethtool.c b/drivers/net/e1000/e1000_ethtool.c
index 0a2ca7c73a41..237247f74df4 100644
--- a/drivers/net/e1000/e1000_ethtool.c
+++ b/drivers/net/e1000/e1000_ethtool.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 3
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved. 4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free 7 under the terms of the GNU General Public License as published by the Free
@@ -69,6 +69,7 @@ static const struct e1000_stats e1000_gstrings_stats[] = {
69 { "rx_crc_errors", E1000_STAT(net_stats.rx_crc_errors) }, 69 { "rx_crc_errors", E1000_STAT(net_stats.rx_crc_errors) },
70 { "rx_frame_errors", E1000_STAT(net_stats.rx_frame_errors) }, 70 { "rx_frame_errors", E1000_STAT(net_stats.rx_frame_errors) },
71 { "rx_fifo_errors", E1000_STAT(net_stats.rx_fifo_errors) }, 71 { "rx_fifo_errors", E1000_STAT(net_stats.rx_fifo_errors) },
72 { "rx_no_buffer_count", E1000_STAT(stats.rnbc) },
72 { "rx_missed_errors", E1000_STAT(net_stats.rx_missed_errors) }, 73 { "rx_missed_errors", E1000_STAT(net_stats.rx_missed_errors) },
73 { "tx_aborted_errors", E1000_STAT(net_stats.tx_aborted_errors) }, 74 { "tx_aborted_errors", E1000_STAT(net_stats.tx_aborted_errors) },
74 { "tx_carrier_errors", E1000_STAT(net_stats.tx_carrier_errors) }, 75 { "tx_carrier_errors", E1000_STAT(net_stats.tx_carrier_errors) },
@@ -593,7 +594,7 @@ e1000_set_ringparam(struct net_device *netdev,
593 tx_old = adapter->tx_ring; 594 tx_old = adapter->tx_ring;
594 rx_old = adapter->rx_ring; 595 rx_old = adapter->rx_ring;
595 596
596 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 597 if((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
597 return -EINVAL; 598 return -EINVAL;
598 599
599 if(netif_running(adapter->netdev)) 600 if(netif_running(adapter->netdev))
@@ -784,8 +785,8 @@ e1000_intr_test(struct e1000_adapter *adapter, uint64_t *data)
784 /* Hook up test interrupt handler just for this test */ 785 /* Hook up test interrupt handler just for this test */
785 if(!request_irq(irq, &e1000_test_intr, 0, netdev->name, netdev)) { 786 if(!request_irq(irq, &e1000_test_intr, 0, netdev->name, netdev)) {
786 shared_int = FALSE; 787 shared_int = FALSE;
787 } else if(request_irq(irq, &e1000_test_intr, SA_SHIRQ, 788 } else if(request_irq(irq, &e1000_test_intr, SA_SHIRQ,
788 netdev->name, netdev)){ 789 netdev->name, netdev)){
789 *data = 1; 790 *data = 1;
790 return -1; 791 return -1;
791 } 792 }
@@ -842,10 +843,8 @@ e1000_intr_test(struct e1000_adapter *adapter, uint64_t *data)
842 * test failed. 843 * test failed.
843 */ 844 */
844 adapter->test_icr = 0; 845 adapter->test_icr = 0;
845 E1000_WRITE_REG(&adapter->hw, IMC, 846 E1000_WRITE_REG(&adapter->hw, IMC, ~mask & 0x00007FFF);
846 (~mask & 0x00007FFF)); 847 E1000_WRITE_REG(&adapter->hw, ICS, ~mask & 0x00007FFF);
847 E1000_WRITE_REG(&adapter->hw, ICS,
848 (~mask & 0x00007FFF));
849 msec_delay(10); 848 msec_delay(10);
850 849
851 if(adapter->test_icr) { 850 if(adapter->test_icr) {
@@ -919,7 +918,8 @@ e1000_setup_desc_rings(struct e1000_adapter *adapter)
919 918
920 /* Setup Tx descriptor ring and Tx buffers */ 919 /* Setup Tx descriptor ring and Tx buffers */
921 920
922 txdr->count = 80; 921 if(!txdr->count)
922 txdr->count = E1000_DEFAULT_TXD;
923 923
924 size = txdr->count * sizeof(struct e1000_buffer); 924 size = txdr->count * sizeof(struct e1000_buffer);
925 if(!(txdr->buffer_info = kmalloc(size, GFP_KERNEL))) { 925 if(!(txdr->buffer_info = kmalloc(size, GFP_KERNEL))) {
@@ -974,7 +974,8 @@ e1000_setup_desc_rings(struct e1000_adapter *adapter)
974 974
975 /* Setup Rx descriptor ring and Rx buffers */ 975 /* Setup Rx descriptor ring and Rx buffers */
976 976
977 rxdr->count = 80; 977 if(!rxdr->count)
978 rxdr->count = E1000_DEFAULT_RXD;
978 979
979 size = rxdr->count * sizeof(struct e1000_buffer); 980 size = rxdr->count * sizeof(struct e1000_buffer);
980 if(!(rxdr->buffer_info = kmalloc(size, GFP_KERNEL))) { 981 if(!(rxdr->buffer_info = kmalloc(size, GFP_KERNEL))) {
@@ -1008,7 +1009,7 @@ e1000_setup_desc_rings(struct e1000_adapter *adapter)
1008 struct e1000_rx_desc *rx_desc = E1000_RX_DESC(*rxdr, i); 1009 struct e1000_rx_desc *rx_desc = E1000_RX_DESC(*rxdr, i);
1009 struct sk_buff *skb; 1010 struct sk_buff *skb;
1010 1011
1011 if(!(skb = alloc_skb(E1000_RXBUFFER_2048 + NET_IP_ALIGN, 1012 if(!(skb = alloc_skb(E1000_RXBUFFER_2048 + NET_IP_ALIGN,
1012 GFP_KERNEL))) { 1013 GFP_KERNEL))) {
1013 ret_val = 6; 1014 ret_val = 6;
1014 goto err_nomem; 1015 goto err_nomem;
@@ -1310,31 +1311,62 @@ e1000_run_loopback_test(struct e1000_adapter *adapter)
1310 struct e1000_desc_ring *txdr = &adapter->test_tx_ring; 1311 struct e1000_desc_ring *txdr = &adapter->test_tx_ring;
1311 struct e1000_desc_ring *rxdr = &adapter->test_rx_ring; 1312 struct e1000_desc_ring *rxdr = &adapter->test_rx_ring;
1312 struct pci_dev *pdev = adapter->pdev; 1313 struct pci_dev *pdev = adapter->pdev;
1313 int i, ret_val; 1314 int i, j, k, l, lc, good_cnt, ret_val=0;
1315 unsigned long time;
1314 1316
1315 E1000_WRITE_REG(&adapter->hw, RDT, rxdr->count - 1); 1317 E1000_WRITE_REG(&adapter->hw, RDT, rxdr->count - 1);
1316 1318
1317 for(i = 0; i < 64; i++) { 1319 /* Calculate the loop count based on the largest descriptor ring
1318 e1000_create_lbtest_frame(txdr->buffer_info[i].skb, 1024); 1320 * The idea is to wrap the largest ring a number of times using 64
1319 pci_dma_sync_single_for_device(pdev, txdr->buffer_info[i].dma, 1321 * send/receive pairs during each loop
1320 txdr->buffer_info[i].length, 1322 */
1321 PCI_DMA_TODEVICE);
1322 }
1323 E1000_WRITE_REG(&adapter->hw, TDT, i);
1324
1325 msec_delay(200);
1326
1327 i = 0;
1328 do {
1329 pci_dma_sync_single_for_cpu(pdev, rxdr->buffer_info[i].dma,
1330 rxdr->buffer_info[i].length,
1331 PCI_DMA_FROMDEVICE);
1332
1333 ret_val = e1000_check_lbtest_frame(rxdr->buffer_info[i].skb,
1334 1024);
1335 i++;
1336 } while (ret_val != 0 && i < 64);
1337 1323
1324 if(rxdr->count <= txdr->count)
1325 lc = ((txdr->count / 64) * 2) + 1;
1326 else
1327 lc = ((rxdr->count / 64) * 2) + 1;
1328
1329 k = l = 0;
1330 for(j = 0; j <= lc; j++) { /* loop count loop */
1331 for(i = 0; i < 64; i++) { /* send the packets */
1332 e1000_create_lbtest_frame(txdr->buffer_info[i].skb,
1333 1024);
1334 pci_dma_sync_single_for_device(pdev,
1335 txdr->buffer_info[k].dma,
1336 txdr->buffer_info[k].length,
1337 PCI_DMA_TODEVICE);
1338 if(unlikely(++k == txdr->count)) k = 0;
1339 }
1340 E1000_WRITE_REG(&adapter->hw, TDT, k);
1341 msec_delay(200);
1342 time = jiffies; /* set the start time for the receive */
1343 good_cnt = 0;
1344 do { /* receive the sent packets */
1345 pci_dma_sync_single_for_cpu(pdev,
1346 rxdr->buffer_info[l].dma,
1347 rxdr->buffer_info[l].length,
1348 PCI_DMA_FROMDEVICE);
1349
1350 ret_val = e1000_check_lbtest_frame(
1351 rxdr->buffer_info[l].skb,
1352 1024);
1353 if(!ret_val)
1354 good_cnt++;
1355 if(unlikely(++l == rxdr->count)) l = 0;
1356 /* time + 20 msecs (200 msecs on 2.4) is more than
1357 * enough time to complete the receives, if it's
1358 * exceeded, break and error off
1359 */
1360 } while (good_cnt < 64 && jiffies < (time + 20));
1361 if(good_cnt != 64) {
1362 ret_val = 13; /* ret_val is the same as mis-compare */
1363 break;
1364 }
1365 if(jiffies >= (time + 2)) {
1366 ret_val = 14; /* error code for time out error */
1367 break;
1368 }
1369 } /* end loop count loop */
1338 return ret_val; 1370 return ret_val;
1339} 1371}
1340 1372
@@ -1354,13 +1386,12 @@ static int
1354e1000_link_test(struct e1000_adapter *adapter, uint64_t *data) 1386e1000_link_test(struct e1000_adapter *adapter, uint64_t *data)
1355{ 1387{
1356 *data = 0; 1388 *data = 0;
1357
1358 if (adapter->hw.media_type == e1000_media_type_internal_serdes) { 1389 if (adapter->hw.media_type == e1000_media_type_internal_serdes) {
1359 int i = 0; 1390 int i = 0;
1360 adapter->hw.serdes_link_down = TRUE; 1391 adapter->hw.serdes_link_down = TRUE;
1361 1392
1362 /* on some blade server designs link establishment */ 1393 /* On some blade server designs, link establishment
1363 /* could take as long as 2-3 minutes. */ 1394 * could take as long as 2-3 minutes */
1364 do { 1395 do {
1365 e1000_check_for_link(&adapter->hw); 1396 e1000_check_for_link(&adapter->hw);
1366 if (adapter->hw.serdes_link_down == FALSE) 1397 if (adapter->hw.serdes_link_down == FALSE)
@@ -1368,9 +1399,11 @@ e1000_link_test(struct e1000_adapter *adapter, uint64_t *data)
1368 msec_delay(20); 1399 msec_delay(20);
1369 } while (i++ < 3750); 1400 } while (i++ < 3750);
1370 1401
1371 *data = 1; 1402 *data = 1;
1372 } else { 1403 } else {
1373 e1000_check_for_link(&adapter->hw); 1404 e1000_check_for_link(&adapter->hw);
1405 if(adapter->hw.autoneg) /* if auto_neg is set wait for it */
1406 msec_delay(4000);
1374 1407
1375 if(!(E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU)) { 1408 if(!(E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU)) {
1376 *data = 1; 1409 *data = 1;
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index 786a9b935659..723589b28be5 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 3
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved. 4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free 7 under the terms of the GNU General Public License as published by the Free
@@ -63,10 +63,11 @@ static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
63static int32_t e1000_acquire_eeprom(struct e1000_hw *hw); 63static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
64static void e1000_release_eeprom(struct e1000_hw *hw); 64static void e1000_release_eeprom(struct e1000_hw *hw);
65static void e1000_standby_eeprom(struct e1000_hw *hw); 65static void e1000_standby_eeprom(struct e1000_hw *hw);
66static int32_t e1000_id_led_init(struct e1000_hw * hw);
67static int32_t e1000_set_vco_speed(struct e1000_hw *hw); 66static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
68static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw); 67static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
69static int32_t e1000_set_phy_mode(struct e1000_hw *hw); 68static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
69static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);
70static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);
70 71
71/* IGP cable length table */ 72/* IGP cable length table */
72static const 73static const
@@ -80,6 +81,17 @@ uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
80 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 81 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
81 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; 82 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
82 83
84static const
85uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
86 { 8, 13, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43,
87 22, 24, 27, 30, 32, 35, 37, 40, 42, 44, 47, 49, 51, 54, 56, 58,
88 32, 35, 38, 41, 44, 47, 50, 53, 55, 58, 61, 63, 66, 69, 71, 74,
89 43, 47, 51, 54, 58, 61, 64, 67, 71, 74, 77, 80, 82, 85, 88, 90,
90 57, 62, 66, 70, 74, 77, 81, 85, 88, 91, 94, 97, 100, 103, 106, 108,
91 73, 78, 82, 87, 91, 95, 98, 102, 105, 109, 112, 114, 117, 119, 122, 124,
92 91, 96, 101, 105, 109, 113, 116, 119, 122, 125, 127, 128, 128, 128, 128, 128,
93 108, 113, 117, 121, 124, 127, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128};
94
83 95
84/****************************************************************************** 96/******************************************************************************
85 * Set the phy type member in the hw struct. 97 * Set the phy type member in the hw struct.
@@ -91,10 +103,14 @@ e1000_set_phy_type(struct e1000_hw *hw)
91{ 103{
92 DEBUGFUNC("e1000_set_phy_type"); 104 DEBUGFUNC("e1000_set_phy_type");
93 105
106 if(hw->mac_type == e1000_undefined)
107 return -E1000_ERR_PHY_TYPE;
108
94 switch(hw->phy_id) { 109 switch(hw->phy_id) {
95 case M88E1000_E_PHY_ID: 110 case M88E1000_E_PHY_ID:
96 case M88E1000_I_PHY_ID: 111 case M88E1000_I_PHY_ID:
97 case M88E1011_I_PHY_ID: 112 case M88E1011_I_PHY_ID:
113 case M88E1111_I_PHY_ID:
98 hw->phy_type = e1000_phy_m88; 114 hw->phy_type = e1000_phy_m88;
99 break; 115 break;
100 case IGP01E1000_I_PHY_ID: 116 case IGP01E1000_I_PHY_ID:
@@ -128,7 +144,6 @@ e1000_phy_init_script(struct e1000_hw *hw)
128 144
129 DEBUGFUNC("e1000_phy_init_script"); 145 DEBUGFUNC("e1000_phy_init_script");
130 146
131
132 if(hw->phy_init_script) { 147 if(hw->phy_init_script) {
133 msec_delay(20); 148 msec_delay(20);
134 149
@@ -271,6 +286,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
271 case E1000_DEV_ID_82546GB_FIBER: 286 case E1000_DEV_ID_82546GB_FIBER:
272 case E1000_DEV_ID_82546GB_SERDES: 287 case E1000_DEV_ID_82546GB_SERDES:
273 case E1000_DEV_ID_82546GB_PCIE: 288 case E1000_DEV_ID_82546GB_PCIE:
289 case E1000_DEV_ID_82546GB_QUAD_COPPER:
274 hw->mac_type = e1000_82546_rev_3; 290 hw->mac_type = e1000_82546_rev_3;
275 break; 291 break;
276 case E1000_DEV_ID_82541EI: 292 case E1000_DEV_ID_82541EI:
@@ -289,12 +305,19 @@ e1000_set_mac_type(struct e1000_hw *hw)
289 case E1000_DEV_ID_82547GI: 305 case E1000_DEV_ID_82547GI:
290 hw->mac_type = e1000_82547_rev_2; 306 hw->mac_type = e1000_82547_rev_2;
291 break; 307 break;
308 case E1000_DEV_ID_82573E:
309 case E1000_DEV_ID_82573E_IAMT:
310 hw->mac_type = e1000_82573;
311 break;
292 default: 312 default:
293 /* Should never have loaded on this device */ 313 /* Should never have loaded on this device */
294 return -E1000_ERR_MAC_TYPE; 314 return -E1000_ERR_MAC_TYPE;
295 } 315 }
296 316
297 switch(hw->mac_type) { 317 switch(hw->mac_type) {
318 case e1000_82573:
319 hw->eeprom_semaphore_present = TRUE;
320 /* fall through */
298 case e1000_82541: 321 case e1000_82541:
299 case e1000_82547: 322 case e1000_82547:
300 case e1000_82541_rev_2: 323 case e1000_82541_rev_2:
@@ -360,6 +383,9 @@ e1000_reset_hw(struct e1000_hw *hw)
360 uint32_t icr; 383 uint32_t icr;
361 uint32_t manc; 384 uint32_t manc;
362 uint32_t led_ctrl; 385 uint32_t led_ctrl;
386 uint32_t timeout;
387 uint32_t extcnf_ctrl;
388 int32_t ret_val;
363 389
364 DEBUGFUNC("e1000_reset_hw"); 390 DEBUGFUNC("e1000_reset_hw");
365 391
@@ -369,6 +395,15 @@ e1000_reset_hw(struct e1000_hw *hw)
369 e1000_pci_clear_mwi(hw); 395 e1000_pci_clear_mwi(hw);
370 } 396 }
371 397
398 if(hw->bus_type == e1000_bus_type_pci_express) {
399 /* Prevent the PCI-E bus from sticking if there is no TLP connection
400 * on the last TLP read/write transaction when MAC is reset.
401 */
402 if(e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
403 DEBUGOUT("PCI-E Master disable polling has failed.\n");
404 }
405 }
406
372 /* Clear interrupt mask to stop board from generating interrupts */ 407 /* Clear interrupt mask to stop board from generating interrupts */
373 DEBUGOUT("Masking off all interrupts\n"); 408 DEBUGOUT("Masking off all interrupts\n");
374 E1000_WRITE_REG(hw, IMC, 0xffffffff); 409 E1000_WRITE_REG(hw, IMC, 0xffffffff);
@@ -393,10 +428,32 @@ e1000_reset_hw(struct e1000_hw *hw)
393 428
394 /* Must reset the PHY before resetting the MAC */ 429 /* Must reset the PHY before resetting the MAC */
395 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 430 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
396 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); 431 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
397 msec_delay(5); 432 msec_delay(5);
398 } 433 }
399 434
435 /* Must acquire the MDIO ownership before MAC reset.
436 * Ownership defaults to firmware after a reset. */
437 if(hw->mac_type == e1000_82573) {
438 timeout = 10;
439
440 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
441 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
442
443 do {
444 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
445 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
446
447 if(extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
448 break;
449 else
450 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
451
452 msec_delay(2);
453 timeout--;
454 } while(timeout);
455 }
456
400 /* Issue a global reset to the MAC. This will reset the chip's 457 /* Issue a global reset to the MAC. This will reset the chip's
401 * transmit, receive, DMA, and link units. It will not effect 458 * transmit, receive, DMA, and link units. It will not effect
402 * the current PCI configuration. The global reset bit is self- 459 * the current PCI configuration. The global reset bit is self-
@@ -450,6 +507,18 @@ e1000_reset_hw(struct e1000_hw *hw)
450 /* Wait for EEPROM reload */ 507 /* Wait for EEPROM reload */
451 msec_delay(20); 508 msec_delay(20);
452 break; 509 break;
510 case e1000_82573:
511 udelay(10);
512 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
513 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
514 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
515 E1000_WRITE_FLUSH(hw);
516 /* fall through */
517 ret_val = e1000_get_auto_rd_done(hw);
518 if(ret_val)
519 /* We don't want to continue accessing MAC registers. */
520 return ret_val;
521 break;
453 default: 522 default:
454 /* Wait for EEPROM reload (it happens automatically) */ 523 /* Wait for EEPROM reload (it happens automatically) */
455 msec_delay(5); 524 msec_delay(5);
@@ -457,7 +526,7 @@ e1000_reset_hw(struct e1000_hw *hw)
457 } 526 }
458 527
459 /* Disable HW ARPs on ASF enabled adapters */ 528 /* Disable HW ARPs on ASF enabled adapters */
460 if(hw->mac_type >= e1000_82540) { 529 if(hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
461 manc = E1000_READ_REG(hw, MANC); 530 manc = E1000_READ_REG(hw, MANC);
462 manc &= ~(E1000_MANC_ARP_EN); 531 manc &= ~(E1000_MANC_ARP_EN);
463 E1000_WRITE_REG(hw, MANC, manc); 532 E1000_WRITE_REG(hw, MANC, manc);
@@ -510,6 +579,8 @@ e1000_init_hw(struct e1000_hw *hw)
510 uint16_t pcix_stat_hi_word; 579 uint16_t pcix_stat_hi_word;
511 uint16_t cmd_mmrbc; 580 uint16_t cmd_mmrbc;
512 uint16_t stat_mmrbc; 581 uint16_t stat_mmrbc;
582 uint32_t mta_size;
583
513 DEBUGFUNC("e1000_init_hw"); 584 DEBUGFUNC("e1000_init_hw");
514 585
515 /* Initialize Identification LED */ 586 /* Initialize Identification LED */
@@ -524,8 +595,8 @@ e1000_init_hw(struct e1000_hw *hw)
524 595
525 /* Disabling VLAN filtering. */ 596 /* Disabling VLAN filtering. */
526 DEBUGOUT("Initializing the IEEE VLAN\n"); 597 DEBUGOUT("Initializing the IEEE VLAN\n");
527 E1000_WRITE_REG(hw, VET, 0); 598 if (hw->mac_type < e1000_82545_rev_3)
528 599 E1000_WRITE_REG(hw, VET, 0);
529 e1000_clear_vfta(hw); 600 e1000_clear_vfta(hw);
530 601
531 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 602 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
@@ -553,14 +624,16 @@ e1000_init_hw(struct e1000_hw *hw)
553 624
554 /* Zero out the Multicast HASH table */ 625 /* Zero out the Multicast HASH table */
555 DEBUGOUT("Zeroing the MTA\n"); 626 DEBUGOUT("Zeroing the MTA\n");
556 for(i = 0; i < E1000_MC_TBL_SIZE; i++) 627 mta_size = E1000_MC_TBL_SIZE;
628 for(i = 0; i < mta_size; i++)
557 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 629 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
558 630
559 /* Set the PCI priority bit correctly in the CTRL register. This 631 /* Set the PCI priority bit correctly in the CTRL register. This
560 * determines if the adapter gives priority to receives, or if it 632 * determines if the adapter gives priority to receives, or if it
561 * gives equal priority to transmits and receives. 633 * gives equal priority to transmits and receives. Valid only on
634 * 82542 and 82543 silicon.
562 */ 635 */
563 if(hw->dma_fairness) { 636 if(hw->dma_fairness && hw->mac_type <= e1000_82543) {
564 ctrl = E1000_READ_REG(hw, CTRL); 637 ctrl = E1000_READ_REG(hw, CTRL);
565 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 638 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
566 } 639 }
@@ -598,9 +671,21 @@ e1000_init_hw(struct e1000_hw *hw)
598 if(hw->mac_type > e1000_82544) { 671 if(hw->mac_type > e1000_82544) {
599 ctrl = E1000_READ_REG(hw, TXDCTL); 672 ctrl = E1000_READ_REG(hw, TXDCTL);
600 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 673 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
674 switch (hw->mac_type) {
675 default:
676 break;
677 case e1000_82573:
678 ctrl |= E1000_TXDCTL_COUNT_DESC;
679 break;
680 }
601 E1000_WRITE_REG(hw, TXDCTL, ctrl); 681 E1000_WRITE_REG(hw, TXDCTL, ctrl);
602 } 682 }
603 683
684 if (hw->mac_type == e1000_82573) {
685 e1000_enable_tx_pkt_filtering(hw);
686 }
687
688
604 /* Clear all of the statistics registers (clear on read). It is 689 /* Clear all of the statistics registers (clear on read). It is
605 * important that we do this after we have tried to establish link 690 * important that we do this after we have tried to establish link
606 * because the symbol error count will increment wildly if there 691 * because the symbol error count will increment wildly if there
@@ -679,7 +764,7 @@ e1000_setup_link(struct e1000_hw *hw)
679 * control setting, then the variable hw->fc will 764 * control setting, then the variable hw->fc will
680 * be initialized based on a value in the EEPROM. 765 * be initialized based on a value in the EEPROM.
681 */ 766 */
682 if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) { 767 if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data)) {
683 DEBUGOUT("EEPROM Read Error\n"); 768 DEBUGOUT("EEPROM Read Error\n");
684 return -E1000_ERR_EEPROM; 769 return -E1000_ERR_EEPROM;
685 } 770 }
@@ -736,6 +821,7 @@ e1000_setup_link(struct e1000_hw *hw)
736 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 821 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
737 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 822 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
738 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 823 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
824
739 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 825 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
740 826
741 /* Set the flow control receive threshold registers. Normally, 827 /* Set the flow control receive threshold registers. Normally,
@@ -906,20 +992,18 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
906} 992}
907 993
908/****************************************************************************** 994/******************************************************************************
909* Detects which PHY is present and the speed and duplex 995* Make sure we have a valid PHY and change PHY mode before link setup.
910* 996*
911* hw - Struct containing variables accessed by shared code 997* hw - Struct containing variables accessed by shared code
912******************************************************************************/ 998******************************************************************************/
913static int32_t 999static int32_t
914e1000_setup_copper_link(struct e1000_hw *hw) 1000e1000_copper_link_preconfig(struct e1000_hw *hw)
915{ 1001{
916 uint32_t ctrl; 1002 uint32_t ctrl;
917 uint32_t led_ctrl;
918 int32_t ret_val; 1003 int32_t ret_val;
919 uint16_t i;
920 uint16_t phy_data; 1004 uint16_t phy_data;
921 1005
922 DEBUGFUNC("e1000_setup_copper_link"); 1006 DEBUGFUNC("e1000_copper_link_preconfig");
923 1007
924 ctrl = E1000_READ_REG(hw, CTRL); 1008 ctrl = E1000_READ_REG(hw, CTRL);
925 /* With 82543, we need to force speed and duplex on the MAC equal to what 1009 /* With 82543, we need to force speed and duplex on the MAC equal to what
@@ -933,7 +1017,9 @@ e1000_setup_copper_link(struct e1000_hw *hw)
933 } else { 1017 } else {
934 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); 1018 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
935 E1000_WRITE_REG(hw, CTRL, ctrl); 1019 E1000_WRITE_REG(hw, CTRL, ctrl);
936 e1000_phy_hw_reset(hw); 1020 ret_val = e1000_phy_hw_reset(hw);
1021 if(ret_val)
1022 return ret_val;
937 } 1023 }
938 1024
939 /* Make sure we have a valid PHY */ 1025 /* Make sure we have a valid PHY */
@@ -961,274 +1047,398 @@ e1000_setup_copper_link(struct e1000_hw *hw)
961 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) 1047 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
962 hw->phy_reset_disable = FALSE; 1048 hw->phy_reset_disable = FALSE;
963 1049
964 if(!hw->phy_reset_disable) { 1050 return E1000_SUCCESS;
965 if (hw->phy_type == e1000_phy_igp) { 1051}
966 1052
967 ret_val = e1000_phy_reset(hw);
968 if(ret_val) {
969 DEBUGOUT("Error Resetting the PHY\n");
970 return ret_val;
971 }
972 1053
973 /* Wait 10ms for MAC to configure PHY from eeprom settings */ 1054/********************************************************************
974 msec_delay(15); 1055* Copper link setup for e1000_phy_igp series.
1056*
1057* hw - Struct containing variables accessed by shared code
1058*********************************************************************/
1059static int32_t
1060e1000_copper_link_igp_setup(struct e1000_hw *hw)
1061{
1062 uint32_t led_ctrl;
1063 int32_t ret_val;
1064 uint16_t phy_data;
975 1065
976 /* Configure activity LED after PHY reset */ 1066 DEBUGFUNC("e1000_copper_link_igp_setup");
977 led_ctrl = E1000_READ_REG(hw, LEDCTL);
978 led_ctrl &= IGP_ACTIVITY_LED_MASK;
979 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
980 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
981 1067
982 /* disable lplu d3 during driver init */ 1068 if (hw->phy_reset_disable)
983 ret_val = e1000_set_d3_lplu_state(hw, FALSE); 1069 return E1000_SUCCESS;
984 if(ret_val) { 1070
985 DEBUGOUT("Error Disabling LPLU D3\n"); 1071 ret_val = e1000_phy_reset(hw);
986 return ret_val; 1072 if (ret_val) {
987 } 1073 DEBUGOUT("Error Resetting the PHY\n");
1074 return ret_val;
1075 }
988 1076
989 /* Configure mdi-mdix settings */ 1077 /* Wait 10ms for MAC to configure PHY from eeprom settings */
990 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 1078 msec_delay(15);
991 &phy_data);
992 if(ret_val)
993 return ret_val;
994 1079
995 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 1080 /* Configure activity LED after PHY reset */
996 hw->dsp_config_state = e1000_dsp_config_disabled; 1081 led_ctrl = E1000_READ_REG(hw, LEDCTL);
997 /* Force MDI for earlier revs of the IGP PHY */ 1082 led_ctrl &= IGP_ACTIVITY_LED_MASK;
998 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | 1083 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
999 IGP01E1000_PSCR_FORCE_MDI_MDIX); 1084 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1000 hw->mdix = 1;
1001 1085
1002 } else { 1086 /* disable lplu d3 during driver init */
1003 hw->dsp_config_state = e1000_dsp_config_enabled; 1087 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
1004 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1088 if (ret_val) {
1005 1089 DEBUGOUT("Error Disabling LPLU D3\n");
1006 switch (hw->mdix) { 1090 return ret_val;
1007 case 1: 1091 }
1008 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1009 break;
1010 case 2:
1011 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1012 break;
1013 case 0:
1014 default:
1015 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1016 break;
1017 }
1018 }
1019 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1020 phy_data);
1021 if(ret_val)
1022 return ret_val;
1023 1092
1024 /* set auto-master slave resolution settings */ 1093 /* disable lplu d0 during driver init */
1025 if(hw->autoneg) { 1094 ret_val = e1000_set_d0_lplu_state(hw, FALSE);
1026 e1000_ms_type phy_ms_setting = hw->master_slave; 1095 if (ret_val) {
1096 DEBUGOUT("Error Disabling LPLU D0\n");
1097 return ret_val;
1098 }
1099 /* Configure mdi-mdix settings */
1100 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1101 if (ret_val)
1102 return ret_val;
1027 1103
1028 if(hw->ffe_config_state == e1000_ffe_config_active) 1104 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1029 hw->ffe_config_state = e1000_ffe_config_enabled; 1105 hw->dsp_config_state = e1000_dsp_config_disabled;
1106 /* Force MDI for earlier revs of the IGP PHY */
1107 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1108 hw->mdix = 1;
1030 1109
1031 if(hw->dsp_config_state == e1000_dsp_config_activated) 1110 } else {
1032 hw->dsp_config_state = e1000_dsp_config_enabled; 1111 hw->dsp_config_state = e1000_dsp_config_enabled;
1112 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1033 1113
1034 /* when autonegotiation advertisment is only 1000Mbps then we 1114 switch (hw->mdix) {
1035 * should disable SmartSpeed and enable Auto MasterSlave 1115 case 1:
1036 * resolution as hardware default. */ 1116 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1037 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) { 1117 break;
1038 /* Disable SmartSpeed */ 1118 case 2:
1039 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1119 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1040 &phy_data); 1120 break;
1041 if(ret_val) 1121 case 0:
1042 return ret_val; 1122 default:
1043 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1123 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1044 ret_val = e1000_write_phy_reg(hw, 1124 break;
1045 IGP01E1000_PHY_PORT_CONFIG, 1125 }
1046 phy_data); 1126 }
1047 if(ret_val) 1127 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1048 return ret_val; 1128 if(ret_val)
1049 /* Set auto Master/Slave resolution process */ 1129 return ret_val;
1050 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1051 if(ret_val)
1052 return ret_val;
1053 phy_data &= ~CR_1000T_MS_ENABLE;
1054 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1055 if(ret_val)
1056 return ret_val;
1057 }
1058 1130
1059 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 1131 /* set auto-master slave resolution settings */
1060 if(ret_val) 1132 if(hw->autoneg) {
1061 return ret_val; 1133 e1000_ms_type phy_ms_setting = hw->master_slave;
1062 1134
1063 /* load defaults for future use */ 1135 if(hw->ffe_config_state == e1000_ffe_config_active)
1064 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 1136 hw->ffe_config_state = e1000_ffe_config_enabled;
1065 ((phy_data & CR_1000T_MS_VALUE) ? 1137
1066 e1000_ms_force_master : 1138 if(hw->dsp_config_state == e1000_dsp_config_activated)
1067 e1000_ms_force_slave) : 1139 hw->dsp_config_state = e1000_dsp_config_enabled;
1068 e1000_ms_auto; 1140
1069 1141 /* when autonegotiation advertisment is only 1000Mbps then we
1070 switch (phy_ms_setting) { 1142 * should disable SmartSpeed and enable Auto MasterSlave
1071 case e1000_ms_force_master: 1143 * resolution as hardware default. */
1072 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 1144 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1073 break; 1145 /* Disable SmartSpeed */
1074 case e1000_ms_force_slave: 1146 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
1075 phy_data |= CR_1000T_MS_ENABLE; 1147 if(ret_val)
1076 phy_data &= ~(CR_1000T_MS_VALUE); 1148 return ret_val;
1077 break; 1149 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1078 case e1000_ms_auto: 1150 ret_val = e1000_write_phy_reg(hw,
1079 phy_data &= ~CR_1000T_MS_ENABLE; 1151 IGP01E1000_PHY_PORT_CONFIG,
1080 default: 1152 phy_data);
1081 break; 1153 if(ret_val)
1082 } 1154 return ret_val;
1083 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 1155 /* Set auto Master/Slave resolution process */
1084 if(ret_val) 1156 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1085 return ret_val; 1157 if(ret_val)
1086 } 1158 return ret_val;
1087 } else { 1159 phy_data &= ~CR_1000T_MS_ENABLE;
1088 /* Enable CRS on TX. This must be set for half-duplex operation. */ 1160 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1089 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1090 &phy_data);
1091 if(ret_val) 1161 if(ret_val)
1092 return ret_val; 1162 return ret_val;
1163 }
1093 1164
1094 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1165 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1166 if(ret_val)
1167 return ret_val;
1095 1168
1096 /* Options: 1169 /* load defaults for future use */
1097 * MDI/MDI-X = 0 (default) 1170 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1098 * 0 - Auto for all speeds 1171 ((phy_data & CR_1000T_MS_VALUE) ?
1099 * 1 - MDI mode 1172 e1000_ms_force_master :
1100 * 2 - MDI-X mode 1173 e1000_ms_force_slave) :
1101 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1174 e1000_ms_auto;
1102 */
1103 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1104 1175
1105 switch (hw->mdix) { 1176 switch (phy_ms_setting) {
1106 case 1: 1177 case e1000_ms_force_master:
1107 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1178 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1108 break; 1179 break;
1109 case 2: 1180 case e1000_ms_force_slave:
1110 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1181 phy_data |= CR_1000T_MS_ENABLE;
1111 break; 1182 phy_data &= ~(CR_1000T_MS_VALUE);
1112 case 3: 1183 break;
1113 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1184 case e1000_ms_auto:
1114 break; 1185 phy_data &= ~CR_1000T_MS_ENABLE;
1115 case 0:
1116 default: 1186 default:
1117 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1187 break;
1118 break; 1188 }
1119 } 1189 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1190 if(ret_val)
1191 return ret_val;
1192 }
1120 1193
1121 /* Options: 1194 return E1000_SUCCESS;
1122 * disable_polarity_correction = 0 (default) 1195}
1123 * Automatic Correction for Reversed Cable Polarity
1124 * 0 - Disabled
1125 * 1 - Enabled
1126 */
1127 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1128 if(hw->disable_polarity_correction == 1)
1129 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1130 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1131 phy_data);
1132 if(ret_val)
1133 return ret_val;
1134 1196
1135 /* Force TX_CLK in the Extended PHY Specific Control Register
1136 * to 25MHz clock.
1137 */
1138 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1139 &phy_data);
1140 if(ret_val)
1141 return ret_val;
1142 1197
1143 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1198/********************************************************************
1199* Copper link setup for e1000_phy_m88 series.
1200*
1201* hw - Struct containing variables accessed by shared code
1202*********************************************************************/
1203static int32_t
1204e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1205{
1206 int32_t ret_val;
1207 uint16_t phy_data;
1208
1209 DEBUGFUNC("e1000_copper_link_mgp_setup");
1210
1211 if(hw->phy_reset_disable)
1212 return E1000_SUCCESS;
1213
1214 /* Enable CRS on TX. This must be set for half-duplex operation. */
1215 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1216 if(ret_val)
1217 return ret_val;
1218
1219 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1220
1221 /* Options:
1222 * MDI/MDI-X = 0 (default)
1223 * 0 - Auto for all speeds
1224 * 1 - MDI mode
1225 * 2 - MDI-X mode
1226 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1227 */
1228 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1229
1230 switch (hw->mdix) {
1231 case 1:
1232 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1233 break;
1234 case 2:
1235 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1236 break;
1237 case 3:
1238 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1239 break;
1240 case 0:
1241 default:
1242 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1243 break;
1244 }
1245
1246 /* Options:
1247 * disable_polarity_correction = 0 (default)
1248 * Automatic Correction for Reversed Cable Polarity
1249 * 0 - Disabled
1250 * 1 - Enabled
1251 */
1252 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1253 if(hw->disable_polarity_correction == 1)
1254 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1255 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1256 if(ret_val)
1257 return ret_val;
1144 1258
1145 if (hw->phy_revision < M88E1011_I_REV_4) { 1259 /* Force TX_CLK in the Extended PHY Specific Control Register
1146 /* Configure Master and Slave downshift values */ 1260 * to 25MHz clock.
1147 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1261 */
1262 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1263 if(ret_val)
1264 return ret_val;
1265
1266 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1267
1268 if (hw->phy_revision < M88E1011_I_REV_4) {
1269 /* Configure Master and Slave downshift values */
1270 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1148 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1271 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1149 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1272 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1150 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1273 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1151 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1274 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1152 phy_data); 1275 if(ret_val)
1153 if(ret_val) 1276 return ret_val;
1154 return ret_val; 1277 }
1155 }
1156 1278
1157 /* SW Reset the PHY so all changes take effect */ 1279 /* SW Reset the PHY so all changes take effect */
1158 ret_val = e1000_phy_reset(hw); 1280 ret_val = e1000_phy_reset(hw);
1159 if(ret_val) { 1281 if(ret_val) {
1160 DEBUGOUT("Error Resetting the PHY\n"); 1282 DEBUGOUT("Error Resetting the PHY\n");
1161 return ret_val; 1283 return ret_val;
1162 } 1284 }
1285
1286 return E1000_SUCCESS;
1287}
1288
1289/********************************************************************
1290* Setup auto-negotiation and flow control advertisements,
1291* and then perform auto-negotiation.
1292*
1293* hw - Struct containing variables accessed by shared code
1294*********************************************************************/
1295static int32_t
1296e1000_copper_link_autoneg(struct e1000_hw *hw)
1297{
1298 int32_t ret_val;
1299 uint16_t phy_data;
1300
1301 DEBUGFUNC("e1000_copper_link_autoneg");
1302
1303 /* Perform some bounds checking on the hw->autoneg_advertised
1304 * parameter. If this variable is zero, then set it to the default.
1305 */
1306 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1307
1308 /* If autoneg_advertised is zero, we assume it was not defaulted
1309 * by the calling code so we set to advertise full capability.
1310 */
1311 if(hw->autoneg_advertised == 0)
1312 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1313
1314 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1315 ret_val = e1000_phy_setup_autoneg(hw);
1316 if(ret_val) {
1317 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1318 return ret_val;
1319 }
1320 DEBUGOUT("Restarting Auto-Neg\n");
1321
1322 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1323 * the Auto Neg Restart bit in the PHY control register.
1324 */
1325 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1326 if(ret_val)
1327 return ret_val;
1328
1329 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1330 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1331 if(ret_val)
1332 return ret_val;
1333
1334 /* Does the user want to wait for Auto-Neg to complete here, or
1335 * check at a later time (for example, callback routine).
1336 */
1337 if(hw->wait_autoneg_complete) {
1338 ret_val = e1000_wait_autoneg(hw);
1339 if(ret_val) {
1340 DEBUGOUT("Error while waiting for autoneg to complete\n");
1341 return ret_val;
1163 } 1342 }
1343 }
1164 1344
1165 /* Options: 1345 hw->get_link_status = TRUE;
1166 * autoneg = 1 (default)
1167 * PHY will advertise value(s) parsed from
1168 * autoneg_advertised and fc
1169 * autoneg = 0
1170 * PHY will be set to 10H, 10F, 100H, or 100F
1171 * depending on value parsed from forced_speed_duplex.
1172 */
1173 1346
1174 /* Is autoneg enabled? This is enabled by default or by software 1347 return E1000_SUCCESS;
1175 * override. If so, call e1000_phy_setup_autoneg routine to parse the 1348}
1176 * autoneg_advertised and fc options. If autoneg is NOT enabled, then
1177 * the user should have provided a speed/duplex override. If so, then
1178 * call e1000_phy_force_speed_duplex to parse and set this up.
1179 */
1180 if(hw->autoneg) {
1181 /* Perform some bounds checking on the hw->autoneg_advertised
1182 * parameter. If this variable is zero, then set it to the default.
1183 */
1184 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1185 1349
1186 /* If autoneg_advertised is zero, we assume it was not defaulted
1187 * by the calling code so we set to advertise full capability.
1188 */
1189 if(hw->autoneg_advertised == 0)
1190 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1191 1350
1192 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1351/******************************************************************************
1193 ret_val = e1000_phy_setup_autoneg(hw); 1352* Config the MAC and the PHY after link is up.
1194 if(ret_val) { 1353* 1) Set up the MAC to the current PHY speed/duplex
1195 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1354* if we are on 82543. If we
1196 return ret_val; 1355* are on newer silicon, we only need to configure
1197 } 1356* collision distance in the Transmit Control Register.
1198 DEBUGOUT("Restarting Auto-Neg\n"); 1357* 2) Set up flow control on the MAC to that established with
1358* the link partner.
1359* 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1360*
1361* hw - Struct containing variables accessed by shared code
1362******************************************************************************/
1363static int32_t
1364e1000_copper_link_postconfig(struct e1000_hw *hw)
1365{
1366 int32_t ret_val;
1367 DEBUGFUNC("e1000_copper_link_postconfig");
1368
1369 if(hw->mac_type >= e1000_82544) {
1370 e1000_config_collision_dist(hw);
1371 } else {
1372 ret_val = e1000_config_mac_to_phy(hw);
1373 if(ret_val) {
1374 DEBUGOUT("Error configuring MAC to PHY settings\n");
1375 return ret_val;
1376 }
1377 }
1378 ret_val = e1000_config_fc_after_link_up(hw);
1379 if(ret_val) {
1380 DEBUGOUT("Error Configuring Flow Control\n");
1381 return ret_val;
1382 }
1199 1383
1200 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1384 /* Config DSP to improve Giga link quality */
1201 * the Auto Neg Restart bit in the PHY control register. 1385 if(hw->phy_type == e1000_phy_igp) {
1202 */ 1386 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1203 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 1387 if(ret_val) {
1204 if(ret_val) 1388 DEBUGOUT("Error Configuring DSP after link up\n");
1205 return ret_val; 1389 return ret_val;
1390 }
1391 }
1392
1393 return E1000_SUCCESS;
1394}
1206 1395
1207 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1396/******************************************************************************
1208 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 1397* Detects which PHY is present and setup the speed and duplex
1209 if(ret_val) 1398*
1210 return ret_val; 1399* hw - Struct containing variables accessed by shared code
1400******************************************************************************/
1401static int32_t
1402e1000_setup_copper_link(struct e1000_hw *hw)
1403{
1404 int32_t ret_val;
1405 uint16_t i;
1406 uint16_t phy_data;
1211 1407
1212 /* Does the user want to wait for Auto-Neg to complete here, or 1408 DEBUGFUNC("e1000_setup_copper_link");
1213 * check at a later time (for example, callback routine). 1409
1214 */ 1410 /* Check if it is a valid PHY and set PHY mode if necessary. */
1215 if(hw->wait_autoneg_complete) { 1411 ret_val = e1000_copper_link_preconfig(hw);
1216 ret_val = e1000_wait_autoneg(hw); 1412 if(ret_val)
1217 if(ret_val) { 1413 return ret_val;
1218 DEBUGOUT("Error while waiting for autoneg to complete\n"); 1414
1219 return ret_val; 1415 if (hw->phy_type == e1000_phy_igp ||
1220 } 1416 hw->phy_type == e1000_phy_igp_2) {
1221 } 1417 ret_val = e1000_copper_link_igp_setup(hw);
1222 hw->get_link_status = TRUE; 1418 if(ret_val)
1223 } else { 1419 return ret_val;
1224 DEBUGOUT("Forcing speed and duplex\n"); 1420 } else if (hw->phy_type == e1000_phy_m88) {
1225 ret_val = e1000_phy_force_speed_duplex(hw); 1421 ret_val = e1000_copper_link_mgp_setup(hw);
1226 if(ret_val) { 1422 if(ret_val)
1227 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1423 return ret_val;
1228 return ret_val; 1424 }
1229 } 1425
1426 if(hw->autoneg) {
1427 /* Setup autoneg and flow control advertisement
1428 * and perform autonegotiation */
1429 ret_val = e1000_copper_link_autoneg(hw);
1430 if(ret_val)
1431 return ret_val;
1432 } else {
1433 /* PHY will be set to 10H, 10F, 100H,or 100F
1434 * depending on value from forced_speed_duplex. */
1435 DEBUGOUT("Forcing speed and duplex\n");
1436 ret_val = e1000_phy_force_speed_duplex(hw);
1437 if(ret_val) {
1438 DEBUGOUT("Error Forcing Speed and Duplex\n");
1439 return ret_val;
1230 } 1440 }
1231 } /* !hw->phy_reset_disable */ 1441 }
1232 1442
1233 /* Check link status. Wait up to 100 microseconds for link to become 1443 /* Check link status. Wait up to 100 microseconds for link to become
1234 * valid. 1444 * valid.
@@ -1242,37 +1452,11 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1242 return ret_val; 1452 return ret_val;
1243 1453
1244 if(phy_data & MII_SR_LINK_STATUS) { 1454 if(phy_data & MII_SR_LINK_STATUS) {
1245 /* We have link, so we need to finish the config process: 1455 /* Config the MAC and PHY after link is up */
1246 * 1) Set up the MAC to the current PHY speed/duplex 1456 ret_val = e1000_copper_link_postconfig(hw);
1247 * if we are on 82543. If we 1457 if(ret_val)
1248 * are on newer silicon, we only need to configure
1249 * collision distance in the Transmit Control Register.
1250 * 2) Set up flow control on the MAC to that established with
1251 * the link partner.
1252 */
1253 if(hw->mac_type >= e1000_82544) {
1254 e1000_config_collision_dist(hw);
1255 } else {
1256 ret_val = e1000_config_mac_to_phy(hw);
1257 if(ret_val) {
1258 DEBUGOUT("Error configuring MAC to PHY settings\n");
1259 return ret_val;
1260 }
1261 }
1262 ret_val = e1000_config_fc_after_link_up(hw);
1263 if(ret_val) {
1264 DEBUGOUT("Error Configuring Flow Control\n");
1265 return ret_val; 1458 return ret_val;
1266 } 1459
1267 DEBUGOUT("Valid link established!!!\n");
1268
1269 if(hw->phy_type == e1000_phy_igp) {
1270 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1271 if(ret_val) {
1272 DEBUGOUT("Error Configuring DSP after link up\n");
1273 return ret_val;
1274 }
1275 }
1276 DEBUGOUT("Valid link established!!!\n"); 1460 DEBUGOUT("Valid link established!!!\n");
1277 return E1000_SUCCESS; 1461 return E1000_SUCCESS;
1278 } 1462 }
@@ -1302,10 +1486,10 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
1302 if(ret_val) 1486 if(ret_val)
1303 return ret_val; 1487 return ret_val;
1304 1488
1305 /* Read the MII 1000Base-T Control Register (Address 9). */ 1489 /* Read the MII 1000Base-T Control Register (Address 9). */
1306 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); 1490 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1307 if(ret_val) 1491 if(ret_val)
1308 return ret_val; 1492 return ret_val;
1309 1493
1310 /* Need to parse both autoneg_advertised and fc and set up 1494 /* Need to parse both autoneg_advertised and fc and set up
1311 * the appropriate PHY registers. First we will parse for 1495 * the appropriate PHY registers. First we will parse for
@@ -1417,7 +1601,7 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
1417 1601
1418 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1602 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1419 1603
1420 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); 1604 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1421 if(ret_val) 1605 if(ret_val)
1422 return ret_val; 1606 return ret_val;
1423 1607
@@ -1678,6 +1862,11 @@ e1000_config_mac_to_phy(struct e1000_hw *hw)
1678 1862
1679 DEBUGFUNC("e1000_config_mac_to_phy"); 1863 DEBUGFUNC("e1000_config_mac_to_phy");
1680 1864
1865 /* 82544 or newer MAC, Auto Speed Detection takes care of
1866 * MAC speed/duplex configuration.*/
1867 if (hw->mac_type >= e1000_82544)
1868 return E1000_SUCCESS;
1869
1681 /* Read the Device Control Register and set the bits to Force Speed 1870 /* Read the Device Control Register and set the bits to Force Speed
1682 * and Duplex. 1871 * and Duplex.
1683 */ 1872 */
@@ -1688,45 +1877,25 @@ e1000_config_mac_to_phy(struct e1000_hw *hw)
1688 /* Set up duplex in the Device Control and Transmit Control 1877 /* Set up duplex in the Device Control and Transmit Control
1689 * registers depending on negotiated values. 1878 * registers depending on negotiated values.
1690 */ 1879 */
1691 if (hw->phy_type == e1000_phy_igp) { 1880 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1692 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, 1881 if(ret_val)
1693 &phy_data); 1882 return ret_val;
1694 if(ret_val)
1695 return ret_val;
1696
1697 if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
1698 else ctrl &= ~E1000_CTRL_FD;
1699
1700 e1000_config_collision_dist(hw);
1701 1883
1702 /* Set up speed in the Device Control register depending on 1884 if(phy_data & M88E1000_PSSR_DPLX)
1703 * negotiated values. 1885 ctrl |= E1000_CTRL_FD;
1704 */ 1886 else
1705 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 1887 ctrl &= ~E1000_CTRL_FD;
1706 IGP01E1000_PSSR_SPEED_1000MBPS)
1707 ctrl |= E1000_CTRL_SPD_1000;
1708 else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1709 IGP01E1000_PSSR_SPEED_100MBPS)
1710 ctrl |= E1000_CTRL_SPD_100;
1711 } else {
1712 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1713 &phy_data);
1714 if(ret_val)
1715 return ret_val;
1716 1888
1717 if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD; 1889 e1000_config_collision_dist(hw);
1718 else ctrl &= ~E1000_CTRL_FD;
1719 1890
1720 e1000_config_collision_dist(hw); 1891 /* Set up speed in the Device Control register depending on
1892 * negotiated values.
1893 */
1894 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1895 ctrl |= E1000_CTRL_SPD_1000;
1896 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1897 ctrl |= E1000_CTRL_SPD_100;
1721 1898
1722 /* Set up speed in the Device Control register depending on
1723 * negotiated values.
1724 */
1725 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1726 ctrl |= E1000_CTRL_SPD_1000;
1727 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1728 ctrl |= E1000_CTRL_SPD_100;
1729 }
1730 /* Write the configured values back to the Device Control Reg. */ 1899 /* Write the configured values back to the Device Control Reg. */
1731 E1000_WRITE_REG(hw, CTRL, ctrl); 1900 E1000_WRITE_REG(hw, CTRL, ctrl);
1732 return E1000_SUCCESS; 1901 return E1000_SUCCESS;
@@ -2494,8 +2663,8 @@ e1000_read_phy_reg(struct e1000_hw *hw,
2494 2663
2495 DEBUGFUNC("e1000_read_phy_reg"); 2664 DEBUGFUNC("e1000_read_phy_reg");
2496 2665
2497 2666 if((hw->phy_type == e1000_phy_igp ||
2498 if(hw->phy_type == e1000_phy_igp && 2667 hw->phy_type == e1000_phy_igp_2) &&
2499 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 2668 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2500 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 2669 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2501 (uint16_t)reg_addr); 2670 (uint16_t)reg_addr);
@@ -2600,8 +2769,8 @@ e1000_write_phy_reg(struct e1000_hw *hw,
2600 2769
2601 DEBUGFUNC("e1000_write_phy_reg"); 2770 DEBUGFUNC("e1000_write_phy_reg");
2602 2771
2603 2772 if((hw->phy_type == e1000_phy_igp ||
2604 if(hw->phy_type == e1000_phy_igp && 2773 hw->phy_type == e1000_phy_igp_2) &&
2605 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 2774 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2606 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 2775 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2607 (uint16_t)reg_addr); 2776 (uint16_t)reg_addr);
@@ -2679,19 +2848,27 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw,
2679 return E1000_SUCCESS; 2848 return E1000_SUCCESS;
2680} 2849}
2681 2850
2851
2682/****************************************************************************** 2852/******************************************************************************
2683* Returns the PHY to the power-on reset state 2853* Returns the PHY to the power-on reset state
2684* 2854*
2685* hw - Struct containing variables accessed by shared code 2855* hw - Struct containing variables accessed by shared code
2686******************************************************************************/ 2856******************************************************************************/
2687void 2857int32_t
2688e1000_phy_hw_reset(struct e1000_hw *hw) 2858e1000_phy_hw_reset(struct e1000_hw *hw)
2689{ 2859{
2690 uint32_t ctrl, ctrl_ext; 2860 uint32_t ctrl, ctrl_ext;
2691 uint32_t led_ctrl; 2861 uint32_t led_ctrl;
2862 int32_t ret_val;
2692 2863
2693 DEBUGFUNC("e1000_phy_hw_reset"); 2864 DEBUGFUNC("e1000_phy_hw_reset");
2694 2865
2866 /* In the case of the phy reset being blocked, it's not an error, we
2867 * simply return success without performing the reset. */
2868 ret_val = e1000_check_phy_reset_block(hw);
2869 if (ret_val)
2870 return E1000_SUCCESS;
2871
2695 DEBUGOUT("Resetting Phy...\n"); 2872 DEBUGOUT("Resetting Phy...\n");
2696 2873
2697 if(hw->mac_type > e1000_82543) { 2874 if(hw->mac_type > e1000_82543) {
@@ -2727,6 +2904,11 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
2727 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 2904 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2728 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 2905 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2729 } 2906 }
2907
2908 /* Wait for FW to finish PHY configuration. */
2909 ret_val = e1000_get_phy_cfg_done(hw);
2910
2911 return ret_val;
2730} 2912}
2731 2913
2732/****************************************************************************** 2914/******************************************************************************
@@ -2744,7 +2926,19 @@ e1000_phy_reset(struct e1000_hw *hw)
2744 2926
2745 DEBUGFUNC("e1000_phy_reset"); 2927 DEBUGFUNC("e1000_phy_reset");
2746 2928
2747 if(hw->mac_type != e1000_82541_rev_2) { 2929 /* In the case of the phy reset being blocked, it's not an error, we
2930 * simply return success without performing the reset. */
2931 ret_val = e1000_check_phy_reset_block(hw);
2932 if (ret_val)
2933 return E1000_SUCCESS;
2934
2935 switch (hw->mac_type) {
2936 case e1000_82541_rev_2:
2937 ret_val = e1000_phy_hw_reset(hw);
2938 if(ret_val)
2939 return ret_val;
2940 break;
2941 default:
2748 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 2942 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2749 if(ret_val) 2943 if(ret_val)
2750 return ret_val; 2944 return ret_val;
@@ -2755,9 +2949,10 @@ e1000_phy_reset(struct e1000_hw *hw)
2755 return ret_val; 2949 return ret_val;
2756 2950
2757 udelay(1); 2951 udelay(1);
2758 } else e1000_phy_hw_reset(hw); 2952 break;
2953 }
2759 2954
2760 if(hw->phy_type == e1000_phy_igp) 2955 if(hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
2761 e1000_phy_init_script(hw); 2956 e1000_phy_init_script(hw);
2762 2957
2763 return E1000_SUCCESS; 2958 return E1000_SUCCESS;
@@ -2811,6 +3006,9 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
2811 case e1000_82547_rev_2: 3006 case e1000_82547_rev_2:
2812 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE; 3007 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
2813 break; 3008 break;
3009 case e1000_82573:
3010 if(hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
3011 break;
2814 default: 3012 default:
2815 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); 3013 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
2816 return -E1000_ERR_CONFIG; 3014 return -E1000_ERR_CONFIG;
@@ -2866,7 +3064,7 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
2866 3064
2867 /* The downshift status is checked only once, after link is established, 3065 /* The downshift status is checked only once, after link is established,
2868 * and it stored in the hw->speed_downgraded parameter. */ 3066 * and it stored in the hw->speed_downgraded parameter. */
2869 phy_info->downshift = hw->speed_downgraded; 3067 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
2870 3068
2871 /* IGP01E1000 does not need to support it. */ 3069 /* IGP01E1000 does not need to support it. */
2872 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; 3070 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
@@ -2905,7 +3103,7 @@ e1000_phy_igp_get_info(struct e1000_hw *hw,
2905 if(ret_val) 3103 if(ret_val)
2906 return ret_val; 3104 return ret_val;
2907 3105
2908 /* transalte to old method */ 3106 /* Translate to old method */
2909 average = (max_length + min_length) / 2; 3107 average = (max_length + min_length) / 2;
2910 3108
2911 if(average <= e1000_igp_cable_length_50) 3109 if(average <= e1000_igp_cable_length_50)
@@ -2940,7 +3138,7 @@ e1000_phy_m88_get_info(struct e1000_hw *hw,
2940 3138
2941 /* The downshift status is checked only once, after link is established, 3139 /* The downshift status is checked only once, after link is established,
2942 * and it stored in the hw->speed_downgraded parameter. */ 3140 * and it stored in the hw->speed_downgraded parameter. */
2943 phy_info->downshift = hw->speed_downgraded; 3141 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
2944 3142
2945 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 3143 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2946 if(ret_val) 3144 if(ret_val)
@@ -3029,7 +3227,8 @@ e1000_phy_get_info(struct e1000_hw *hw,
3029 return -E1000_ERR_CONFIG; 3227 return -E1000_ERR_CONFIG;
3030 } 3228 }
3031 3229
3032 if(hw->phy_type == e1000_phy_igp) 3230 if(hw->phy_type == e1000_phy_igp ||
3231 hw->phy_type == e1000_phy_igp_2)
3033 return e1000_phy_igp_get_info(hw, phy_info); 3232 return e1000_phy_igp_get_info(hw, phy_info);
3034 else 3233 else
3035 return e1000_phy_m88_get_info(hw, phy_info); 3234 return e1000_phy_m88_get_info(hw, phy_info);
@@ -3055,11 +3254,12 @@ e1000_validate_mdi_setting(struct e1000_hw *hw)
3055 * 3254 *
3056 * hw - Struct containing variables accessed by shared code 3255 * hw - Struct containing variables accessed by shared code
3057 *****************************************************************************/ 3256 *****************************************************************************/
3058void 3257int32_t
3059e1000_init_eeprom_params(struct e1000_hw *hw) 3258e1000_init_eeprom_params(struct e1000_hw *hw)
3060{ 3259{
3061 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3260 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3062 uint32_t eecd = E1000_READ_REG(hw, EECD); 3261 uint32_t eecd = E1000_READ_REG(hw, EECD);
3262 int32_t ret_val = E1000_SUCCESS;
3063 uint16_t eeprom_size; 3263 uint16_t eeprom_size;
3064 3264
3065 DEBUGFUNC("e1000_init_eeprom_params"); 3265 DEBUGFUNC("e1000_init_eeprom_params");
@@ -3074,6 +3274,8 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
3074 eeprom->opcode_bits = 3; 3274 eeprom->opcode_bits = 3;
3075 eeprom->address_bits = 6; 3275 eeprom->address_bits = 6;
3076 eeprom->delay_usec = 50; 3276 eeprom->delay_usec = 50;
3277 eeprom->use_eerd = FALSE;
3278 eeprom->use_eewr = FALSE;
3077 break; 3279 break;
3078 case e1000_82540: 3280 case e1000_82540:
3079 case e1000_82545: 3281 case e1000_82545:
@@ -3090,6 +3292,8 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
3090 eeprom->word_size = 64; 3292 eeprom->word_size = 64;
3091 eeprom->address_bits = 6; 3293 eeprom->address_bits = 6;
3092 } 3294 }
3295 eeprom->use_eerd = FALSE;
3296 eeprom->use_eewr = FALSE;
3093 break; 3297 break;
3094 case e1000_82541: 3298 case e1000_82541:
3095 case e1000_82541_rev_2: 3299 case e1000_82541_rev_2:
@@ -3118,42 +3322,60 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
3118 eeprom->address_bits = 6; 3322 eeprom->address_bits = 6;
3119 } 3323 }
3120 } 3324 }
3325 eeprom->use_eerd = FALSE;
3326 eeprom->use_eewr = FALSE;
3327 break;
3328 case e1000_82573:
3329 eeprom->type = e1000_eeprom_spi;
3330 eeprom->opcode_bits = 8;
3331 eeprom->delay_usec = 1;
3332 if (eecd & E1000_EECD_ADDR_BITS) {
3333 eeprom->page_size = 32;
3334 eeprom->address_bits = 16;
3335 } else {
3336 eeprom->page_size = 8;
3337 eeprom->address_bits = 8;
3338 }
3339 eeprom->use_eerd = TRUE;
3340 eeprom->use_eewr = TRUE;
3341 if(e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
3342 eeprom->type = e1000_eeprom_flash;
3343 eeprom->word_size = 2048;
3344
3345 /* Ensure that the Autonomous FLASH update bit is cleared due to
3346 * Flash update issue on parts which use a FLASH for NVM. */
3347 eecd &= ~E1000_EECD_AUPDEN;
3348 E1000_WRITE_REG(hw, EECD, eecd);
3349 }
3121 break; 3350 break;
3122 default: 3351 default:
3123 break; 3352 break;
3124 } 3353 }
3125 3354
3126 if (eeprom->type == e1000_eeprom_spi) { 3355 if (eeprom->type == e1000_eeprom_spi) {
3127 eeprom->word_size = 64; 3356 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
3128 if (e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) { 3357 * 32KB (incremented by powers of 2).
3129 eeprom_size &= EEPROM_SIZE_MASK; 3358 */
3130 3359 if(hw->mac_type <= e1000_82547_rev_2) {
3131 switch (eeprom_size) { 3360 /* Set to default value for initial eeprom read. */
3132 case EEPROM_SIZE_16KB: 3361 eeprom->word_size = 64;
3133 eeprom->word_size = 8192; 3362 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
3134 break; 3363 if(ret_val)
3135 case EEPROM_SIZE_8KB: 3364 return ret_val;
3136 eeprom->word_size = 4096; 3365 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
3137 break; 3366 /* 256B eeprom size was not supported in earlier hardware, so we
3138 case EEPROM_SIZE_4KB: 3367 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
3139 eeprom->word_size = 2048; 3368 * is never the result used in the shifting logic below. */
3140 break; 3369 if(eeprom_size)
3141 case EEPROM_SIZE_2KB: 3370 eeprom_size++;
3142 eeprom->word_size = 1024; 3371 } else {
3143 break; 3372 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
3144 case EEPROM_SIZE_1KB: 3373 E1000_EECD_SIZE_EX_SHIFT);
3145 eeprom->word_size = 512;
3146 break;
3147 case EEPROM_SIZE_512B:
3148 eeprom->word_size = 256;
3149 break;
3150 case EEPROM_SIZE_128B:
3151 default:
3152 eeprom->word_size = 64;
3153 break;
3154 }
3155 } 3374 }
3375
3376 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
3156 } 3377 }
3378 return ret_val;
3157} 3379}
3158 3380
3159/****************************************************************************** 3381/******************************************************************************
@@ -3306,8 +3528,12 @@ e1000_acquire_eeprom(struct e1000_hw *hw)
3306 3528
3307 DEBUGFUNC("e1000_acquire_eeprom"); 3529 DEBUGFUNC("e1000_acquire_eeprom");
3308 3530
3531 if(e1000_get_hw_eeprom_semaphore(hw))
3532 return -E1000_ERR_EEPROM;
3533
3309 eecd = E1000_READ_REG(hw, EECD); 3534 eecd = E1000_READ_REG(hw, EECD);
3310 3535
3536 if (hw->mac_type != e1000_82573) {
3311 /* Request EEPROM Access */ 3537 /* Request EEPROM Access */
3312 if(hw->mac_type > e1000_82544) { 3538 if(hw->mac_type > e1000_82544) {
3313 eecd |= E1000_EECD_REQ; 3539 eecd |= E1000_EECD_REQ;
@@ -3326,6 +3552,7 @@ e1000_acquire_eeprom(struct e1000_hw *hw)
3326 return -E1000_ERR_EEPROM; 3552 return -E1000_ERR_EEPROM;
3327 } 3553 }
3328 } 3554 }
3555 }
3329 3556
3330 /* Setup EEPROM for Read/Write */ 3557 /* Setup EEPROM for Read/Write */
3331 3558
@@ -3443,6 +3670,8 @@ e1000_release_eeprom(struct e1000_hw *hw)
3443 eecd &= ~E1000_EECD_REQ; 3670 eecd &= ~E1000_EECD_REQ;
3444 E1000_WRITE_REG(hw, EECD, eecd); 3671 E1000_WRITE_REG(hw, EECD, eecd);
3445 } 3672 }
3673
3674 e1000_put_hw_eeprom_semaphore(hw);
3446} 3675}
3447 3676
3448/****************************************************************************** 3677/******************************************************************************
@@ -3504,8 +3733,10 @@ e1000_read_eeprom(struct e1000_hw *hw,
3504{ 3733{
3505 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3734 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3506 uint32_t i = 0; 3735 uint32_t i = 0;
3736 int32_t ret_val;
3507 3737
3508 DEBUGFUNC("e1000_read_eeprom"); 3738 DEBUGFUNC("e1000_read_eeprom");
3739
3509 /* A check for invalid values: offset too large, too many words, and not 3740 /* A check for invalid values: offset too large, too many words, and not
3510 * enough words. 3741 * enough words.
3511 */ 3742 */
@@ -3515,9 +3746,23 @@ e1000_read_eeprom(struct e1000_hw *hw,
3515 return -E1000_ERR_EEPROM; 3746 return -E1000_ERR_EEPROM;
3516 } 3747 }
3517 3748
3518 /* Prepare the EEPROM for reading */ 3749 /* FLASH reads without acquiring the semaphore are safe in 82573-based
3519 if(e1000_acquire_eeprom(hw) != E1000_SUCCESS) 3750 * controllers.
3520 return -E1000_ERR_EEPROM; 3751 */
3752 if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) ||
3753 (hw->mac_type != e1000_82573)) {
3754 /* Prepare the EEPROM for reading */
3755 if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3756 return -E1000_ERR_EEPROM;
3757 }
3758
3759 if(eeprom->use_eerd == TRUE) {
3760 ret_val = e1000_read_eeprom_eerd(hw, offset, words, data);
3761 if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) ||
3762 (hw->mac_type != e1000_82573))
3763 e1000_release_eeprom(hw);
3764 return ret_val;
3765 }
3521 3766
3522 if(eeprom->type == e1000_eeprom_spi) { 3767 if(eeprom->type == e1000_eeprom_spi) {
3523 uint16_t word_in; 3768 uint16_t word_in;
@@ -3569,6 +3814,132 @@ e1000_read_eeprom(struct e1000_hw *hw,
3569} 3814}
3570 3815
3571/****************************************************************************** 3816/******************************************************************************
3817 * Reads a 16 bit word from the EEPROM using the EERD register.
3818 *
3819 * hw - Struct containing variables accessed by shared code
3820 * offset - offset of word in the EEPROM to read
3821 * data - word read from the EEPROM
3822 * words - number of words to read
3823 *****************************************************************************/
3824int32_t
3825e1000_read_eeprom_eerd(struct e1000_hw *hw,
3826 uint16_t offset,
3827 uint16_t words,
3828 uint16_t *data)
3829{
3830 uint32_t i, eerd = 0;
3831 int32_t error = 0;
3832
3833 for (i = 0; i < words; i++) {
3834 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
3835 E1000_EEPROM_RW_REG_START;
3836
3837 E1000_WRITE_REG(hw, EERD, eerd);
3838 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
3839
3840 if(error) {
3841 break;
3842 }
3843 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
3844
3845 }
3846
3847 return error;
3848}
3849
3850/******************************************************************************
3851 * Writes a 16 bit word from the EEPROM using the EEWR register.
3852 *
3853 * hw - Struct containing variables accessed by shared code
3854 * offset - offset of word in the EEPROM to read
3855 * data - word read from the EEPROM
3856 * words - number of words to read
3857 *****************************************************************************/
3858int32_t
3859e1000_write_eeprom_eewr(struct e1000_hw *hw,
3860 uint16_t offset,
3861 uint16_t words,
3862 uint16_t *data)
3863{
3864 uint32_t register_value = 0;
3865 uint32_t i = 0;
3866 int32_t error = 0;
3867
3868 for (i = 0; i < words; i++) {
3869 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
3870 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
3871 E1000_EEPROM_RW_REG_START;
3872
3873 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
3874 if(error) {
3875 break;
3876 }
3877
3878 E1000_WRITE_REG(hw, EEWR, register_value);
3879
3880 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
3881
3882 if(error) {
3883 break;
3884 }
3885 }
3886
3887 return error;
3888}
3889
3890/******************************************************************************
3891 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
3892 *
3893 * hw - Struct containing variables accessed by shared code
3894 *****************************************************************************/
3895int32_t
3896e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
3897{
3898 uint32_t attempts = 100000;
3899 uint32_t i, reg = 0;
3900 int32_t done = E1000_ERR_EEPROM;
3901
3902 for(i = 0; i < attempts; i++) {
3903 if(eerd == E1000_EEPROM_POLL_READ)
3904 reg = E1000_READ_REG(hw, EERD);
3905 else
3906 reg = E1000_READ_REG(hw, EEWR);
3907
3908 if(reg & E1000_EEPROM_RW_REG_DONE) {
3909 done = E1000_SUCCESS;
3910 break;
3911 }
3912 udelay(5);
3913 }
3914
3915 return done;
3916}
3917
3918/***************************************************************************
3919* Description: Determines if the onboard NVM is FLASH or EEPROM.
3920*
3921* hw - Struct containing variables accessed by shared code
3922****************************************************************************/
3923boolean_t
3924e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
3925{
3926 uint32_t eecd = 0;
3927
3928 if(hw->mac_type == e1000_82573) {
3929 eecd = E1000_READ_REG(hw, EECD);
3930
3931 /* Isolate bits 15 & 16 */
3932 eecd = ((eecd >> 15) & 0x03);
3933
3934 /* If both bits are set, device is Flash type */
3935 if(eecd == 0x03) {
3936 return FALSE;
3937 }
3938 }
3939 return TRUE;
3940}
3941
3942/******************************************************************************
3572 * Verifies that the EEPROM has a valid checksum 3943 * Verifies that the EEPROM has a valid checksum
3573 * 3944 *
3574 * hw - Struct containing variables accessed by shared code 3945 * hw - Struct containing variables accessed by shared code
@@ -3585,6 +3956,25 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
3585 3956
3586 DEBUGFUNC("e1000_validate_eeprom_checksum"); 3957 DEBUGFUNC("e1000_validate_eeprom_checksum");
3587 3958
3959 if ((hw->mac_type == e1000_82573) &&
3960 (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) {
3961 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
3962 * 10h-12h. Checksum may need to be fixed. */
3963 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
3964 if ((eeprom_data & 0x10) == 0) {
3965 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
3966 * has already been fixed. If the checksum is still wrong and this
3967 * bit is a 1, we need to return bad checksum. Otherwise, we need
3968 * to set this bit to a 1 and update the checksum. */
3969 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
3970 if ((eeprom_data & 0x8000) == 0) {
3971 eeprom_data |= 0x8000;
3972 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
3973 e1000_update_eeprom_checksum(hw);
3974 }
3975 }
3976 }
3977
3588 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 3978 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3589 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 3979 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3590 DEBUGOUT("EEPROM Read Error\n"); 3980 DEBUGOUT("EEPROM Read Error\n");
@@ -3628,6 +4018,8 @@ e1000_update_eeprom_checksum(struct e1000_hw *hw)
3628 if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 4018 if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
3629 DEBUGOUT("EEPROM Write Error\n"); 4019 DEBUGOUT("EEPROM Write Error\n");
3630 return -E1000_ERR_EEPROM; 4020 return -E1000_ERR_EEPROM;
4021 } else if (hw->eeprom.type == e1000_eeprom_flash) {
4022 e1000_commit_shadow_ram(hw);
3631 } 4023 }
3632 return E1000_SUCCESS; 4024 return E1000_SUCCESS;
3633} 4025}
@@ -3663,6 +4055,10 @@ e1000_write_eeprom(struct e1000_hw *hw,
3663 return -E1000_ERR_EEPROM; 4055 return -E1000_ERR_EEPROM;
3664 } 4056 }
3665 4057
4058 /* 82573 reads only through eerd */
4059 if(eeprom->use_eewr == TRUE)
4060 return e1000_write_eeprom_eewr(hw, offset, words, data);
4061
3666 /* Prepare the EEPROM for writing */ 4062 /* Prepare the EEPROM for writing */
3667 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 4063 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3668 return -E1000_ERR_EEPROM; 4064 return -E1000_ERR_EEPROM;
@@ -3833,6 +4229,65 @@ e1000_write_eeprom_microwire(struct e1000_hw *hw,
3833} 4229}
3834 4230
3835/****************************************************************************** 4231/******************************************************************************
4232 * Flushes the cached eeprom to NVM. This is done by saving the modified values
4233 * in the eeprom cache and the non modified values in the currently active bank
4234 * to the new bank.
4235 *
4236 * hw - Struct containing variables accessed by shared code
4237 * offset - offset of word in the EEPROM to read
4238 * data - word read from the EEPROM
4239 * words - number of words to read
4240 *****************************************************************************/
4241int32_t
4242e1000_commit_shadow_ram(struct e1000_hw *hw)
4243{
4244 uint32_t attempts = 100000;
4245 uint32_t eecd = 0;
4246 uint32_t flop = 0;
4247 uint32_t i = 0;
4248 int32_t error = E1000_SUCCESS;
4249
4250 /* The flop register will be used to determine if flash type is STM */
4251 flop = E1000_READ_REG(hw, FLOP);
4252
4253 if (hw->mac_type == e1000_82573) {
4254 for (i=0; i < attempts; i++) {
4255 eecd = E1000_READ_REG(hw, EECD);
4256 if ((eecd & E1000_EECD_FLUPD) == 0) {
4257 break;
4258 }
4259 udelay(5);
4260 }
4261
4262 if (i == attempts) {
4263 return -E1000_ERR_EEPROM;
4264 }
4265
4266 /* If STM opcode located in bits 15:8 of flop, reset firmware */
4267 if ((flop & 0xFF00) == E1000_STM_OPCODE) {
4268 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
4269 }
4270
4271 /* Perform the flash update */
4272 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
4273
4274 for (i=0; i < attempts; i++) {
4275 eecd = E1000_READ_REG(hw, EECD);
4276 if ((eecd & E1000_EECD_FLUPD) == 0) {
4277 break;
4278 }
4279 udelay(5);
4280 }
4281
4282 if (i == attempts) {
4283 return -E1000_ERR_EEPROM;
4284 }
4285 }
4286
4287 return error;
4288}
4289
4290/******************************************************************************
3836 * Reads the adapter's part number from the EEPROM 4291 * Reads the adapter's part number from the EEPROM
3837 * 4292 *
3838 * hw - Struct containing variables accessed by shared code 4293 * hw - Struct containing variables accessed by shared code
@@ -3911,6 +4366,7 @@ void
3911e1000_init_rx_addrs(struct e1000_hw *hw) 4366e1000_init_rx_addrs(struct e1000_hw *hw)
3912{ 4367{
3913 uint32_t i; 4368 uint32_t i;
4369 uint32_t rar_num;
3914 4370
3915 DEBUGFUNC("e1000_init_rx_addrs"); 4371 DEBUGFUNC("e1000_init_rx_addrs");
3916 4372
@@ -3919,9 +4375,10 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
3919 4375
3920 e1000_rar_set(hw, hw->mac_addr, 0); 4376 e1000_rar_set(hw, hw->mac_addr, 0);
3921 4377
4378 rar_num = E1000_RAR_ENTRIES;
3922 /* Zero out the other 15 receive addresses. */ 4379 /* Zero out the other 15 receive addresses. */
3923 DEBUGOUT("Clearing RAR[1-15]\n"); 4380 DEBUGOUT("Clearing RAR[1-15]\n");
3924 for(i = 1; i < E1000_RAR_ENTRIES; i++) { 4381 for(i = 1; i < rar_num; i++) {
3925 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 4382 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3926 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 4383 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3927 } 4384 }
@@ -3950,7 +4407,9 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
3950{ 4407{
3951 uint32_t hash_value; 4408 uint32_t hash_value;
3952 uint32_t i; 4409 uint32_t i;
3953 4410 uint32_t num_rar_entry;
4411 uint32_t num_mta_entry;
4412
3954 DEBUGFUNC("e1000_mc_addr_list_update"); 4413 DEBUGFUNC("e1000_mc_addr_list_update");
3955 4414
3956 /* Set the new number of MC addresses that we are being requested to use. */ 4415 /* Set the new number of MC addresses that we are being requested to use. */
@@ -3958,14 +4417,16 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
3958 4417
3959 /* Clear RAR[1-15] */ 4418 /* Clear RAR[1-15] */
3960 DEBUGOUT(" Clearing RAR[1-15]\n"); 4419 DEBUGOUT(" Clearing RAR[1-15]\n");
3961 for(i = rar_used_count; i < E1000_RAR_ENTRIES; i++) { 4420 num_rar_entry = E1000_RAR_ENTRIES;
4421 for(i = rar_used_count; i < num_rar_entry; i++) {
3962 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 4422 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3963 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 4423 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3964 } 4424 }
3965 4425
3966 /* Clear the MTA */ 4426 /* Clear the MTA */
3967 DEBUGOUT(" Clearing MTA\n"); 4427 DEBUGOUT(" Clearing MTA\n");
3968 for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++) { 4428 num_mta_entry = E1000_NUM_MTA_REGISTERS;
4429 for(i = 0; i < num_mta_entry; i++) {
3969 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 4430 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
3970 } 4431 }
3971 4432
@@ -3989,7 +4450,7 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
3989 /* Place this multicast address in the RAR if there is room, * 4450 /* Place this multicast address in the RAR if there is room, *
3990 * else put it in the MTA 4451 * else put it in the MTA
3991 */ 4452 */
3992 if(rar_used_count < E1000_RAR_ENTRIES) { 4453 if (rar_used_count < num_rar_entry) {
3993 e1000_rar_set(hw, 4454 e1000_rar_set(hw,
3994 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)), 4455 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
3995 rar_used_count); 4456 rar_used_count);
@@ -4040,6 +4501,7 @@ e1000_hash_mc_addr(struct e1000_hw *hw,
4040 } 4501 }
4041 4502
4042 hash_value &= 0xFFF; 4503 hash_value &= 0xFFF;
4504
4043 return hash_value; 4505 return hash_value;
4044} 4506}
4045 4507
@@ -4144,12 +4606,33 @@ void
4144e1000_clear_vfta(struct e1000_hw *hw) 4606e1000_clear_vfta(struct e1000_hw *hw)
4145{ 4607{
4146 uint32_t offset; 4608 uint32_t offset;
4147 4609 uint32_t vfta_value = 0;
4148 for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) 4610 uint32_t vfta_offset = 0;
4149 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 4611 uint32_t vfta_bit_in_reg = 0;
4612
4613 if (hw->mac_type == e1000_82573) {
4614 if (hw->mng_cookie.vlan_id != 0) {
4615 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
4616 * ID. The following operations determine which 32b entry
4617 * (i.e. offset) into the array we want to set the VLAN ID
4618 * (i.e. bit) of the manageability unit. */
4619 vfta_offset = (hw->mng_cookie.vlan_id >>
4620 E1000_VFTA_ENTRY_SHIFT) &
4621 E1000_VFTA_ENTRY_MASK;
4622 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
4623 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
4624 }
4625 }
4626 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
4627 /* If the offset we want to clear is the same offset of the
4628 * manageability VLAN ID, then clear all bits except that of the
4629 * manageability unit */
4630 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
4631 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
4632 }
4150} 4633}
4151 4634
4152static int32_t 4635int32_t
4153e1000_id_led_init(struct e1000_hw * hw) 4636e1000_id_led_init(struct e1000_hw * hw)
4154{ 4637{
4155 uint32_t ledctl; 4638 uint32_t ledctl;
@@ -4480,6 +4963,19 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
4480 temp = E1000_READ_REG(hw, MGTPRC); 4963 temp = E1000_READ_REG(hw, MGTPRC);
4481 temp = E1000_READ_REG(hw, MGTPDC); 4964 temp = E1000_READ_REG(hw, MGTPDC);
4482 temp = E1000_READ_REG(hw, MGTPTC); 4965 temp = E1000_READ_REG(hw, MGTPTC);
4966
4967 if(hw->mac_type <= e1000_82547_rev_2) return;
4968
4969 temp = E1000_READ_REG(hw, IAC);
4970 temp = E1000_READ_REG(hw, ICRXOC);
4971 temp = E1000_READ_REG(hw, ICRXPTC);
4972 temp = E1000_READ_REG(hw, ICRXATC);
4973 temp = E1000_READ_REG(hw, ICTXPTC);
4974 temp = E1000_READ_REG(hw, ICTXATC);
4975 temp = E1000_READ_REG(hw, ICTXQEC);
4976 temp = E1000_READ_REG(hw, ICTXQMTC);
4977 temp = E1000_READ_REG(hw, ICRXDMTC);
4978
4483} 4979}
4484 4980
4485/****************************************************************************** 4981/******************************************************************************
@@ -4646,6 +5142,11 @@ e1000_get_bus_info(struct e1000_hw *hw)
4646 hw->bus_speed = e1000_bus_speed_unknown; 5142 hw->bus_speed = e1000_bus_speed_unknown;
4647 hw->bus_width = e1000_bus_width_unknown; 5143 hw->bus_width = e1000_bus_width_unknown;
4648 break; 5144 break;
5145 case e1000_82573:
5146 hw->bus_type = e1000_bus_type_pci_express;
5147 hw->bus_speed = e1000_bus_speed_2500;
5148 hw->bus_width = e1000_bus_width_pciex_4;
5149 break;
4649 default: 5150 default:
4650 status = E1000_READ_REG(hw, STATUS); 5151 status = E1000_READ_REG(hw, STATUS);
4651 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 5152 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
@@ -4749,6 +5250,7 @@ e1000_get_cable_length(struct e1000_hw *hw,
4749 5250
4750 /* Use old method for Phy older than IGP */ 5251 /* Use old method for Phy older than IGP */
4751 if(hw->phy_type == e1000_phy_m88) { 5252 if(hw->phy_type == e1000_phy_m88) {
5253
4752 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 5254 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4753 &phy_data); 5255 &phy_data);
4754 if(ret_val) 5256 if(ret_val)
@@ -4865,7 +5367,8 @@ e1000_check_polarity(struct e1000_hw *hw,
4865 return ret_val; 5367 return ret_val;
4866 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >> 5368 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
4867 M88E1000_PSSR_REV_POLARITY_SHIFT; 5369 M88E1000_PSSR_REV_POLARITY_SHIFT;
4868 } else if(hw->phy_type == e1000_phy_igp) { 5370 } else if(hw->phy_type == e1000_phy_igp ||
5371 hw->phy_type == e1000_phy_igp_2) {
4869 /* Read the Status register to check the speed */ 5372 /* Read the Status register to check the speed */
4870 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, 5373 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
4871 &phy_data); 5374 &phy_data);
@@ -4917,7 +5420,8 @@ e1000_check_downshift(struct e1000_hw *hw)
4917 5420
4918 DEBUGFUNC("e1000_check_downshift"); 5421 DEBUGFUNC("e1000_check_downshift");
4919 5422
4920 if(hw->phy_type == e1000_phy_igp) { 5423 if(hw->phy_type == e1000_phy_igp ||
5424 hw->phy_type == e1000_phy_igp_2) {
4921 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 5425 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
4922 &phy_data); 5426 &phy_data);
4923 if(ret_val) 5427 if(ret_val)
@@ -4933,6 +5437,7 @@ e1000_check_downshift(struct e1000_hw *hw)
4933 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 5437 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
4934 M88E1000_PSSR_DOWNSHIFT_SHIFT; 5438 M88E1000_PSSR_DOWNSHIFT_SHIFT;
4935 } 5439 }
5440
4936 return E1000_SUCCESS; 5441 return E1000_SUCCESS;
4937} 5442}
4938 5443
@@ -5047,7 +5552,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
5047 if(ret_val) 5552 if(ret_val)
5048 return ret_val; 5553 return ret_val;
5049 5554
5050 msec_delay(20); 5555 msec_delay_irq(20);
5051 5556
5052 ret_val = e1000_write_phy_reg(hw, 0x0000, 5557 ret_val = e1000_write_phy_reg(hw, 0x0000,
5053 IGP01E1000_IEEE_FORCE_GIGA); 5558 IGP01E1000_IEEE_FORCE_GIGA);
@@ -5071,7 +5576,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
5071 if(ret_val) 5576 if(ret_val)
5072 return ret_val; 5577 return ret_val;
5073 5578
5074 msec_delay(20); 5579 msec_delay_irq(20);
5075 5580
5076 /* Now enable the transmitter */ 5581 /* Now enable the transmitter */
5077 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 5582 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
@@ -5096,7 +5601,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
5096 if(ret_val) 5601 if(ret_val)
5097 return ret_val; 5602 return ret_val;
5098 5603
5099 msec_delay(20); 5604 msec_delay_irq(20);
5100 5605
5101 ret_val = e1000_write_phy_reg(hw, 0x0000, 5606 ret_val = e1000_write_phy_reg(hw, 0x0000,
5102 IGP01E1000_IEEE_FORCE_GIGA); 5607 IGP01E1000_IEEE_FORCE_GIGA);
@@ -5112,7 +5617,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
5112 if(ret_val) 5617 if(ret_val)
5113 return ret_val; 5618 return ret_val;
5114 5619
5115 msec_delay(20); 5620 msec_delay_irq(20);
5116 5621
5117 /* Now enable the transmitter */ 5622 /* Now enable the transmitter */
5118 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 5623 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
@@ -5187,22 +5692,36 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
5187 uint16_t phy_data; 5692 uint16_t phy_data;
5188 DEBUGFUNC("e1000_set_d3_lplu_state"); 5693 DEBUGFUNC("e1000_set_d3_lplu_state");
5189 5694
5190 if(!((hw->mac_type == e1000_82541_rev_2) || 5695 if(hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2)
5191 (hw->mac_type == e1000_82547_rev_2)))
5192 return E1000_SUCCESS; 5696 return E1000_SUCCESS;
5193 5697
5194 /* During driver activity LPLU should not be used or it will attain link 5698 /* During driver activity LPLU should not be used or it will attain link
5195 * from the lowest speeds starting from 10Mbps. The capability is used for 5699 * from the lowest speeds starting from 10Mbps. The capability is used for
5196 * Dx transitions and states */ 5700 * Dx transitions and states */
5197 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 5701 if(hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
5198 if(ret_val) 5702 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
5199 return ret_val;
5200
5201 if(!active) {
5202 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5203 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
5204 if(ret_val) 5703 if(ret_val)
5205 return ret_val; 5704 return ret_val;
5705 } else {
5706 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
5707 if(ret_val)
5708 return ret_val;
5709 }
5710
5711 if(!active) {
5712 if(hw->mac_type == e1000_82541_rev_2 ||
5713 hw->mac_type == e1000_82547_rev_2) {
5714 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5715 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
5716 if(ret_val)
5717 return ret_val;
5718 } else {
5719 phy_data &= ~IGP02E1000_PM_D3_LPLU;
5720 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
5721 phy_data);
5722 if (ret_val)
5723 return ret_val;
5724 }
5206 5725
5207 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 5726 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5208 * Dx states where the power conservation is most important. During 5727 * Dx states where the power conservation is most important. During
@@ -5236,11 +5755,105 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
5236 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) || 5755 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
5237 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 5756 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
5238 5757
5239 phy_data |= IGP01E1000_GMII_FLEX_SPD; 5758 if(hw->mac_type == e1000_82541_rev_2 ||
5240 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); 5759 hw->mac_type == e1000_82547_rev_2) {
5760 phy_data |= IGP01E1000_GMII_FLEX_SPD;
5761 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
5762 if(ret_val)
5763 return ret_val;
5764 } else {
5765 phy_data |= IGP02E1000_PM_D3_LPLU;
5766 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
5767 phy_data);
5768 if (ret_val)
5769 return ret_val;
5770 }
5771
5772 /* When LPLU is enabled we should disable SmartSpeed */
5773 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
5774 if(ret_val)
5775 return ret_val;
5776
5777 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5778 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
5241 if(ret_val) 5779 if(ret_val)
5242 return ret_val; 5780 return ret_val;
5243 5781
5782 }
5783 return E1000_SUCCESS;
5784}
5785
5786/*****************************************************************************
5787 *
5788 * This function sets the lplu d0 state according to the active flag. When
5789 * activating lplu this function also disables smart speed and vise versa.
5790 * lplu will not be activated unless the device autonegotiation advertisment
5791 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5792 * hw: Struct containing variables accessed by shared code
5793 * active - true to enable lplu false to disable lplu.
5794 *
5795 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5796 * E1000_SUCCESS at any other case.
5797 *
5798 ****************************************************************************/
5799
5800int32_t
5801e1000_set_d0_lplu_state(struct e1000_hw *hw,
5802 boolean_t active)
5803{
5804 int32_t ret_val;
5805 uint16_t phy_data;
5806 DEBUGFUNC("e1000_set_d0_lplu_state");
5807
5808 if(hw->mac_type <= e1000_82547_rev_2)
5809 return E1000_SUCCESS;
5810
5811 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
5812 if(ret_val)
5813 return ret_val;
5814
5815 if (!active) {
5816 phy_data &= ~IGP02E1000_PM_D0_LPLU;
5817 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
5818 if (ret_val)
5819 return ret_val;
5820
5821 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5822 * Dx states where the power conservation is most important. During
5823 * driver activity we should enable SmartSpeed, so performance is
5824 * maintained. */
5825 if (hw->smart_speed == e1000_smart_speed_on) {
5826 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5827 &phy_data);
5828 if(ret_val)
5829 return ret_val;
5830
5831 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5832 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5833 phy_data);
5834 if(ret_val)
5835 return ret_val;
5836 } else if (hw->smart_speed == e1000_smart_speed_off) {
5837 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5838 &phy_data);
5839 if (ret_val)
5840 return ret_val;
5841
5842 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5843 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5844 phy_data);
5845 if(ret_val)
5846 return ret_val;
5847 }
5848
5849
5850 } else {
5851
5852 phy_data |= IGP02E1000_PM_D0_LPLU;
5853 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
5854 if (ret_val)
5855 return ret_val;
5856
5244 /* When LPLU is enabled we should disable SmartSpeed */ 5857 /* When LPLU is enabled we should disable SmartSpeed */
5245 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); 5858 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
5246 if(ret_val) 5859 if(ret_val)
@@ -5318,6 +5931,338 @@ e1000_set_vco_speed(struct e1000_hw *hw)
5318 return E1000_SUCCESS; 5931 return E1000_SUCCESS;
5319} 5932}
5320 5933
5934
5935/*****************************************************************************
5936 * This function reads the cookie from ARC ram.
5937 *
5938 * returns: - E1000_SUCCESS .
5939 ****************************************************************************/
5940int32_t
5941e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer)
5942{
5943 uint8_t i;
5944 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;
5945 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH;
5946
5947 length = (length >> 2);
5948 offset = (offset >> 2);
5949
5950 for (i = 0; i < length; i++) {
5951 *((uint32_t *) buffer + i) =
5952 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
5953 }
5954 return E1000_SUCCESS;
5955}
5956
5957
5958/*****************************************************************************
5959 * This function checks whether the HOST IF is enabled for command operaton
5960 * and also checks whether the previous command is completed.
5961 * It busy waits in case of previous command is not completed.
5962 *
5963 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
5964 * timeout
5965 * - E1000_SUCCESS for success.
5966 ****************************************************************************/
5967int32_t
5968e1000_mng_enable_host_if(struct e1000_hw * hw)
5969{
5970 uint32_t hicr;
5971 uint8_t i;
5972
5973 /* Check that the host interface is enabled. */
5974 hicr = E1000_READ_REG(hw, HICR);
5975 if ((hicr & E1000_HICR_EN) == 0) {
5976 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
5977 return -E1000_ERR_HOST_INTERFACE_COMMAND;
5978 }
5979 /* check the previous command is completed */
5980 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
5981 hicr = E1000_READ_REG(hw, HICR);
5982 if (!(hicr & E1000_HICR_C))
5983 break;
5984 msec_delay_irq(1);
5985 }
5986
5987 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
5988 DEBUGOUT("Previous command timeout failed .\n");
5989 return -E1000_ERR_HOST_INTERFACE_COMMAND;
5990 }
5991 return E1000_SUCCESS;
5992}
5993
5994/*****************************************************************************
5995 * This function writes the buffer content at the offset given on the host if.
5996 * It also does alignment considerations to do the writes in most efficient way.
5997 * Also fills up the sum of the buffer in *buffer parameter.
5998 *
5999 * returns - E1000_SUCCESS for success.
6000 ****************************************************************************/
6001int32_t
6002e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
6003 uint16_t length, uint16_t offset, uint8_t *sum)
6004{
6005 uint8_t *tmp;
6006 uint8_t *bufptr = buffer;
6007 uint32_t data;
6008 uint16_t remaining, i, j, prev_bytes;
6009
6010 /* sum = only sum of the data and it is not checksum */
6011
6012 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
6013 return -E1000_ERR_PARAM;
6014 }
6015
6016 tmp = (uint8_t *)&data;
6017 prev_bytes = offset & 0x3;
6018 offset &= 0xFFFC;
6019 offset >>= 2;
6020
6021 if (prev_bytes) {
6022 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
6023 for (j = prev_bytes; j < sizeof(uint32_t); j++) {
6024 *(tmp + j) = *bufptr++;
6025 *sum += *(tmp + j);
6026 }
6027 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
6028 length -= j - prev_bytes;
6029 offset++;
6030 }
6031
6032 remaining = length & 0x3;
6033 length -= remaining;
6034
6035 /* Calculate length in DWORDs */
6036 length >>= 2;
6037
6038 /* The device driver writes the relevant command block into the
6039 * ram area. */
6040 for (i = 0; i < length; i++) {
6041 for (j = 0; j < sizeof(uint32_t); j++) {
6042 *(tmp + j) = *bufptr++;
6043 *sum += *(tmp + j);
6044 }
6045
6046 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
6047 }
6048 if (remaining) {
6049 for (j = 0; j < sizeof(uint32_t); j++) {
6050 if (j < remaining)
6051 *(tmp + j) = *bufptr++;
6052 else
6053 *(tmp + j) = 0;
6054
6055 *sum += *(tmp + j);
6056 }
6057 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
6058 }
6059
6060 return E1000_SUCCESS;
6061}
6062
6063
6064/*****************************************************************************
6065 * This function writes the command header after does the checksum calculation.
6066 *
6067 * returns - E1000_SUCCESS for success.
6068 ****************************************************************************/
6069int32_t
6070e1000_mng_write_cmd_header(struct e1000_hw * hw,
6071 struct e1000_host_mng_command_header * hdr)
6072{
6073 uint16_t i;
6074 uint8_t sum;
6075 uint8_t *buffer;
6076
6077 /* Write the whole command header structure which includes sum of
6078 * the buffer */
6079
6080 uint16_t length = sizeof(struct e1000_host_mng_command_header);
6081
6082 sum = hdr->checksum;
6083 hdr->checksum = 0;
6084
6085 buffer = (uint8_t *) hdr;
6086 i = length;
6087 while(i--)
6088 sum += buffer[i];
6089
6090 hdr->checksum = 0 - sum;
6091
6092 length >>= 2;
6093 /* The device driver writes the relevant command block into the ram area. */
6094 for (i = 0; i < length; i++)
6095 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
6096
6097 return E1000_SUCCESS;
6098}
6099
6100
6101/*****************************************************************************
6102 * This function indicates to ARC that a new command is pending which completes
6103 * one write operation by the driver.
6104 *
6105 * returns - E1000_SUCCESS for success.
6106 ****************************************************************************/
6107int32_t
6108e1000_mng_write_commit(
6109 struct e1000_hw * hw)
6110{
6111 uint32_t hicr;
6112
6113 hicr = E1000_READ_REG(hw, HICR);
6114 /* Setting this bit tells the ARC that a new command is pending. */
6115 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C);
6116
6117 return E1000_SUCCESS;
6118}
6119
6120
6121/*****************************************************************************
6122 * This function checks the mode of the firmware.
6123 *
6124 * returns - TRUE when the mode is IAMT or FALSE.
6125 ****************************************************************************/
6126boolean_t
6127e1000_check_mng_mode(
6128 struct e1000_hw *hw)
6129{
6130 uint32_t fwsm;
6131
6132 fwsm = E1000_READ_REG(hw, FWSM);
6133
6134 if((fwsm & E1000_FWSM_MODE_MASK) ==
6135 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
6136 return TRUE;
6137
6138 return FALSE;
6139}
6140
6141
6142/*****************************************************************************
6143 * This function writes the dhcp info .
6144 ****************************************************************************/
6145int32_t
6146e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer,
6147 uint16_t length)
6148{
6149 int32_t ret_val;
6150 struct e1000_host_mng_command_header hdr;
6151
6152 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
6153 hdr.command_length = length;
6154 hdr.reserved1 = 0;
6155 hdr.reserved2 = 0;
6156 hdr.checksum = 0;
6157
6158 ret_val = e1000_mng_enable_host_if(hw);
6159 if (ret_val == E1000_SUCCESS) {
6160 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
6161 &(hdr.checksum));
6162 if (ret_val == E1000_SUCCESS) {
6163 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
6164 if (ret_val == E1000_SUCCESS)
6165 ret_val = e1000_mng_write_commit(hw);
6166 }
6167 }
6168 return ret_val;
6169}
6170
6171
6172/*****************************************************************************
6173 * This function calculates the checksum.
6174 *
6175 * returns - checksum of buffer contents.
6176 ****************************************************************************/
6177uint8_t
6178e1000_calculate_mng_checksum(char *buffer, uint32_t length)
6179{
6180 uint8_t sum = 0;
6181 uint32_t i;
6182
6183 if (!buffer)
6184 return 0;
6185
6186 for (i=0; i < length; i++)
6187 sum += buffer[i];
6188
6189 return (uint8_t) (0 - sum);
6190}
6191
6192/*****************************************************************************
6193 * This function checks whether tx pkt filtering needs to be enabled or not.
6194 *
6195 * returns - TRUE for packet filtering or FALSE.
6196 ****************************************************************************/
6197boolean_t
6198e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
6199{
6200 /* called in init as well as watchdog timer functions */
6201
6202 int32_t ret_val, checksum;
6203 boolean_t tx_filter = FALSE;
6204 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
6205 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
6206
6207 if (e1000_check_mng_mode(hw)) {
6208 ret_val = e1000_mng_enable_host_if(hw);
6209 if (ret_val == E1000_SUCCESS) {
6210 ret_val = e1000_host_if_read_cookie(hw, buffer);
6211 if (ret_val == E1000_SUCCESS) {
6212 checksum = hdr->checksum;
6213 hdr->checksum = 0;
6214 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
6215 checksum == e1000_calculate_mng_checksum((char *)buffer,
6216 E1000_MNG_DHCP_COOKIE_LENGTH)) {
6217 if (hdr->status &
6218 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
6219 tx_filter = TRUE;
6220 } else
6221 tx_filter = TRUE;
6222 } else
6223 tx_filter = TRUE;
6224 }
6225 }
6226
6227 hw->tx_pkt_filtering = tx_filter;
6228 return tx_filter;
6229}
6230
6231/******************************************************************************
6232 * Verifies the hardware needs to allow ARPs to be processed by the host
6233 *
6234 * hw - Struct containing variables accessed by shared code
6235 *
6236 * returns: - TRUE/FALSE
6237 *
6238 *****************************************************************************/
6239uint32_t
6240e1000_enable_mng_pass_thru(struct e1000_hw *hw)
6241{
6242 uint32_t manc;
6243 uint32_t fwsm, factps;
6244
6245 if (hw->asf_firmware_present) {
6246 manc = E1000_READ_REG(hw, MANC);
6247
6248 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
6249 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
6250 return FALSE;
6251 if (e1000_arc_subsystem_valid(hw) == TRUE) {
6252 fwsm = E1000_READ_REG(hw, FWSM);
6253 factps = E1000_READ_REG(hw, FACTPS);
6254
6255 if (((fwsm & E1000_FWSM_MODE_MASK) ==
6256 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) &&
6257 (factps & E1000_FACTPS_MNGCG))
6258 return TRUE;
6259 } else
6260 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
6261 return TRUE;
6262 }
6263 return FALSE;
6264}
6265
5321static int32_t 6266static int32_t
5322e1000_polarity_reversal_workaround(struct e1000_hw *hw) 6267e1000_polarity_reversal_workaround(struct e1000_hw *hw)
5323{ 6268{
@@ -5403,3 +6348,265 @@ e1000_polarity_reversal_workaround(struct e1000_hw *hw)
5403 return E1000_SUCCESS; 6348 return E1000_SUCCESS;
5404} 6349}
5405 6350
6351/***************************************************************************
6352 *
6353 * Disables PCI-Express master access.
6354 *
6355 * hw: Struct containing variables accessed by shared code
6356 *
6357 * returns: - none.
6358 *
6359 ***************************************************************************/
6360void
6361e1000_set_pci_express_master_disable(struct e1000_hw *hw)
6362{
6363 uint32_t ctrl;
6364
6365 DEBUGFUNC("e1000_set_pci_express_master_disable");
6366
6367 if (hw->bus_type != e1000_bus_type_pci_express)
6368 return;
6369
6370 ctrl = E1000_READ_REG(hw, CTRL);
6371 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
6372 E1000_WRITE_REG(hw, CTRL, ctrl);
6373}
6374
6375/***************************************************************************
6376 *
6377 * Enables PCI-Express master access.
6378 *
6379 * hw: Struct containing variables accessed by shared code
6380 *
6381 * returns: - none.
6382 *
6383 ***************************************************************************/
6384void
6385e1000_enable_pciex_master(struct e1000_hw *hw)
6386{
6387 uint32_t ctrl;
6388
6389 DEBUGFUNC("e1000_enable_pciex_master");
6390
6391 if (hw->bus_type != e1000_bus_type_pci_express)
6392 return;
6393
6394 ctrl = E1000_READ_REG(hw, CTRL);
6395 ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE;
6396 E1000_WRITE_REG(hw, CTRL, ctrl);
6397}
6398
6399/*******************************************************************************
6400 *
6401 * Disables PCI-Express master access and verifies there are no pending requests
6402 *
6403 * hw: Struct containing variables accessed by shared code
6404 *
6405 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
6406 * caused the master requests to be disabled.
6407 * E1000_SUCCESS master requests disabled.
6408 *
6409 ******************************************************************************/
6410int32_t
6411e1000_disable_pciex_master(struct e1000_hw *hw)
6412{
6413 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
6414
6415 DEBUGFUNC("e1000_disable_pciex_master");
6416
6417 if (hw->bus_type != e1000_bus_type_pci_express)
6418 return E1000_SUCCESS;
6419
6420 e1000_set_pci_express_master_disable(hw);
6421
6422 while(timeout) {
6423 if(!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
6424 break;
6425 else
6426 udelay(100);
6427 timeout--;
6428 }
6429
6430 if(!timeout) {
6431 DEBUGOUT("Master requests are pending.\n");
6432 return -E1000_ERR_MASTER_REQUESTS_PENDING;
6433 }
6434
6435 return E1000_SUCCESS;
6436}
6437
6438/*******************************************************************************
6439 *
6440 * Check for EEPROM Auto Read bit done.
6441 *
6442 * hw: Struct containing variables accessed by shared code
6443 *
6444 * returns: - E1000_ERR_RESET if fail to reset MAC
6445 * E1000_SUCCESS at any other case.
6446 *
6447 ******************************************************************************/
6448int32_t
6449e1000_get_auto_rd_done(struct e1000_hw *hw)
6450{
6451 int32_t timeout = AUTO_READ_DONE_TIMEOUT;
6452
6453 DEBUGFUNC("e1000_get_auto_rd_done");
6454
6455 switch (hw->mac_type) {
6456 default:
6457 msec_delay(5);
6458 break;
6459 case e1000_82573:
6460 while(timeout) {
6461 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) break;
6462 else msec_delay(1);
6463 timeout--;
6464 }
6465
6466 if(!timeout) {
6467 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
6468 return -E1000_ERR_RESET;
6469 }
6470 break;
6471 }
6472
6473 return E1000_SUCCESS;
6474}
6475
6476/***************************************************************************
6477 * Checks if the PHY configuration is done
6478 *
6479 * hw: Struct containing variables accessed by shared code
6480 *
6481 * returns: - E1000_ERR_RESET if fail to reset MAC
6482 * E1000_SUCCESS at any other case.
6483 *
6484 ***************************************************************************/
6485int32_t
6486e1000_get_phy_cfg_done(struct e1000_hw *hw)
6487{
6488 DEBUGFUNC("e1000_get_phy_cfg_done");
6489
6490 /* Simply wait for 10ms */
6491 msec_delay(10);
6492
6493 return E1000_SUCCESS;
6494}
6495
6496/***************************************************************************
6497 *
6498 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
6499 * adapter or Eeprom access.
6500 *
6501 * hw: Struct containing variables accessed by shared code
6502 *
6503 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
6504 * E1000_SUCCESS at any other case.
6505 *
6506 ***************************************************************************/
6507int32_t
6508e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
6509{
6510 int32_t timeout;
6511 uint32_t swsm;
6512
6513 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
6514
6515 if(!hw->eeprom_semaphore_present)
6516 return E1000_SUCCESS;
6517
6518
6519 /* Get the FW semaphore. */
6520 timeout = hw->eeprom.word_size + 1;
6521 while(timeout) {
6522 swsm = E1000_READ_REG(hw, SWSM);
6523 swsm |= E1000_SWSM_SWESMBI;
6524 E1000_WRITE_REG(hw, SWSM, swsm);
6525 /* if we managed to set the bit we got the semaphore. */
6526 swsm = E1000_READ_REG(hw, SWSM);
6527 if(swsm & E1000_SWSM_SWESMBI)
6528 break;
6529
6530 udelay(50);
6531 timeout--;
6532 }
6533
6534 if(!timeout) {
6535 /* Release semaphores */
6536 e1000_put_hw_eeprom_semaphore(hw);
6537 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
6538 return -E1000_ERR_EEPROM;
6539 }
6540
6541 return E1000_SUCCESS;
6542}
6543
6544/***************************************************************************
6545 * This function clears HW semaphore bits.
6546 *
6547 * hw: Struct containing variables accessed by shared code
6548 *
6549 * returns: - None.
6550 *
6551 ***************************************************************************/
6552void
6553e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
6554{
6555 uint32_t swsm;
6556
6557 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
6558
6559 if(!hw->eeprom_semaphore_present)
6560 return;
6561
6562 swsm = E1000_READ_REG(hw, SWSM);
6563 /* Release both semaphores. */
6564 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
6565 E1000_WRITE_REG(hw, SWSM, swsm);
6566}
6567
6568/******************************************************************************
6569 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
6570 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
6571 * the caller to figure out how to deal with it.
6572 *
6573 * hw - Struct containing variables accessed by shared code
6574 *
6575 * returns: - E1000_BLK_PHY_RESET
6576 * E1000_SUCCESS
6577 *
6578 *****************************************************************************/
6579int32_t
6580e1000_check_phy_reset_block(struct e1000_hw *hw)
6581{
6582 uint32_t manc = 0;
6583 if(hw->mac_type > e1000_82547_rev_2)
6584 manc = E1000_READ_REG(hw, MANC);
6585 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
6586 E1000_BLK_PHY_RESET : E1000_SUCCESS;
6587}
6588
6589uint8_t
6590e1000_arc_subsystem_valid(struct e1000_hw *hw)
6591{
6592 uint32_t fwsm;
6593
6594 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
6595 * may not be provided a DMA clock when no manageability features are
6596 * enabled. We do not want to perform any reads/writes to these registers
6597 * if this is the case. We read FWSM to determine the manageability mode.
6598 */
6599 switch (hw->mac_type) {
6600 case e1000_82573:
6601 fwsm = E1000_READ_REG(hw, FWSM);
6602 if((fwsm & E1000_FWSM_MODE_MASK) != 0)
6603 return TRUE;
6604 break;
6605 default:
6606 break;
6607 }
6608 return FALSE;
6609}
6610
6611
6612
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h
index f397e637a3c5..a0263ee96c6b 100644
--- a/drivers/net/e1000/e1000_hw.h
+++ b/drivers/net/e1000/e1000_hw.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 3
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved. 4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free 7 under the terms of the GNU General Public License as published by the Free
@@ -57,6 +57,7 @@ typedef enum {
57 e1000_82541_rev_2, 57 e1000_82541_rev_2,
58 e1000_82547, 58 e1000_82547,
59 e1000_82547_rev_2, 59 e1000_82547_rev_2,
60 e1000_82573,
60 e1000_num_macs 61 e1000_num_macs
61} e1000_mac_type; 62} e1000_mac_type;
62 63
@@ -64,6 +65,7 @@ typedef enum {
64 e1000_eeprom_uninitialized = 0, 65 e1000_eeprom_uninitialized = 0,
65 e1000_eeprom_spi, 66 e1000_eeprom_spi,
66 e1000_eeprom_microwire, 67 e1000_eeprom_microwire,
68 e1000_eeprom_flash,
67 e1000_num_eeprom_types 69 e1000_num_eeprom_types
68} e1000_eeprom_type; 70} e1000_eeprom_type;
69 71
@@ -96,6 +98,7 @@ typedef enum {
96 e1000_bus_type_unknown = 0, 98 e1000_bus_type_unknown = 0,
97 e1000_bus_type_pci, 99 e1000_bus_type_pci,
98 e1000_bus_type_pcix, 100 e1000_bus_type_pcix,
101 e1000_bus_type_pci_express,
99 e1000_bus_type_reserved 102 e1000_bus_type_reserved
100} e1000_bus_type; 103} e1000_bus_type;
101 104
@@ -107,6 +110,7 @@ typedef enum {
107 e1000_bus_speed_100, 110 e1000_bus_speed_100,
108 e1000_bus_speed_120, 111 e1000_bus_speed_120,
109 e1000_bus_speed_133, 112 e1000_bus_speed_133,
113 e1000_bus_speed_2500,
110 e1000_bus_speed_reserved 114 e1000_bus_speed_reserved
111} e1000_bus_speed; 115} e1000_bus_speed;
112 116
@@ -115,6 +119,8 @@ typedef enum {
115 e1000_bus_width_unknown = 0, 119 e1000_bus_width_unknown = 0,
116 e1000_bus_width_32, 120 e1000_bus_width_32,
117 e1000_bus_width_64, 121 e1000_bus_width_64,
122 e1000_bus_width_pciex_1,
123 e1000_bus_width_pciex_4,
118 e1000_bus_width_reserved 124 e1000_bus_width_reserved
119} e1000_bus_width; 125} e1000_bus_width;
120 126
@@ -196,6 +202,7 @@ typedef enum {
196typedef enum { 202typedef enum {
197 e1000_phy_m88 = 0, 203 e1000_phy_m88 = 0,
198 e1000_phy_igp, 204 e1000_phy_igp,
205 e1000_phy_igp_2,
199 e1000_phy_undefined = 0xFF 206 e1000_phy_undefined = 0xFF
200} e1000_phy_type; 207} e1000_phy_type;
201 208
@@ -242,8 +249,19 @@ struct e1000_eeprom_info {
242 uint16_t address_bits; 249 uint16_t address_bits;
243 uint16_t delay_usec; 250 uint16_t delay_usec;
244 uint16_t page_size; 251 uint16_t page_size;
252 boolean_t use_eerd;
253 boolean_t use_eewr;
245}; 254};
246 255
256/* Flex ASF Information */
257#define E1000_HOST_IF_MAX_SIZE 2048
258
259typedef enum {
260 e1000_byte_align = 0,
261 e1000_word_align = 1,
262 e1000_dword_align = 2
263} e1000_align_type;
264
247 265
248 266
249/* Error Codes */ 267/* Error Codes */
@@ -254,11 +272,16 @@ struct e1000_eeprom_info {
254#define E1000_ERR_PARAM 4 272#define E1000_ERR_PARAM 4
255#define E1000_ERR_MAC_TYPE 5 273#define E1000_ERR_MAC_TYPE 5
256#define E1000_ERR_PHY_TYPE 6 274#define E1000_ERR_PHY_TYPE 6
275#define E1000_ERR_RESET 9
276#define E1000_ERR_MASTER_REQUESTS_PENDING 10
277#define E1000_ERR_HOST_INTERFACE_COMMAND 11
278#define E1000_BLK_PHY_RESET 12
257 279
258/* Function prototypes */ 280/* Function prototypes */
259/* Initialization */ 281/* Initialization */
260int32_t e1000_reset_hw(struct e1000_hw *hw); 282int32_t e1000_reset_hw(struct e1000_hw *hw);
261int32_t e1000_init_hw(struct e1000_hw *hw); 283int32_t e1000_init_hw(struct e1000_hw *hw);
284int32_t e1000_id_led_init(struct e1000_hw * hw);
262int32_t e1000_set_mac_type(struct e1000_hw *hw); 285int32_t e1000_set_mac_type(struct e1000_hw *hw);
263void e1000_set_media_type(struct e1000_hw *hw); 286void e1000_set_media_type(struct e1000_hw *hw);
264 287
@@ -275,7 +298,7 @@ int32_t e1000_force_mac_fc(struct e1000_hw *hw);
275/* PHY */ 298/* PHY */
276int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data); 299int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
277int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data); 300int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
278void e1000_phy_hw_reset(struct e1000_hw *hw); 301int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
279int32_t e1000_phy_reset(struct e1000_hw *hw); 302int32_t e1000_phy_reset(struct e1000_hw *hw);
280int32_t e1000_detect_gig_phy(struct e1000_hw *hw); 303int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
281int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); 304int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
@@ -287,13 +310,86 @@ int32_t e1000_check_downshift(struct e1000_hw *hw);
287int32_t e1000_validate_mdi_setting(struct e1000_hw *hw); 310int32_t e1000_validate_mdi_setting(struct e1000_hw *hw);
288 311
289/* EEPROM Functions */ 312/* EEPROM Functions */
290void e1000_init_eeprom_params(struct e1000_hw *hw); 313int32_t e1000_init_eeprom_params(struct e1000_hw *hw);
314boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
315int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
316int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
317int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
318
319/* MNG HOST IF functions */
320uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw);
321
322#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
323#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */
324
325#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */
326#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */
327#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */
328#define E1000_MNG_IAMT_MODE 0x3
329#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */
330
331#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */
332#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2 /* DHCP parsing enabled */
333#define E1000_VFTA_ENTRY_SHIFT 0x5
334#define E1000_VFTA_ENTRY_MASK 0x7F
335#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
336
337struct e1000_host_mng_command_header {
338 uint8_t command_id;
339 uint8_t checksum;
340 uint16_t reserved1;
341 uint16_t reserved2;
342 uint16_t command_length;
343};
344
345struct e1000_host_mng_command_info {
346 struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
347 uint8_t command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658*/
348};
349#ifdef __BIG_ENDIAN
350struct e1000_host_mng_dhcp_cookie{
351 uint32_t signature;
352 uint16_t vlan_id;
353 uint8_t reserved0;
354 uint8_t status;
355 uint32_t reserved1;
356 uint8_t checksum;
357 uint8_t reserved3;
358 uint16_t reserved2;
359};
360#else
361struct e1000_host_mng_dhcp_cookie{
362 uint32_t signature;
363 uint8_t status;
364 uint8_t reserved0;
365 uint16_t vlan_id;
366 uint32_t reserved1;
367 uint16_t reserved2;
368 uint8_t reserved3;
369 uint8_t checksum;
370};
371#endif
372
373int32_t e1000_mng_write_dhcp_info(struct e1000_hw *hw, uint8_t *buffer,
374 uint16_t length);
375boolean_t e1000_check_mng_mode(struct e1000_hw *hw);
376boolean_t e1000_enable_tx_pkt_filtering(struct e1000_hw *hw);
377int32_t e1000_mng_enable_host_if(struct e1000_hw *hw);
378int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer,
379 uint16_t length, uint16_t offset, uint8_t *sum);
380int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw,
381 struct e1000_host_mng_command_header* hdr);
382
383int32_t e1000_mng_write_commit(struct e1000_hw *hw);
384
291int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); 385int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
292int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw); 386int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw);
293int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw); 387int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw);
294int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); 388int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
295int32_t e1000_read_part_num(struct e1000_hw *hw, uint32_t * part_num); 389int32_t e1000_read_part_num(struct e1000_hw *hw, uint32_t * part_num);
296int32_t e1000_read_mac_addr(struct e1000_hw * hw); 390int32_t e1000_read_mac_addr(struct e1000_hw * hw);
391int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
392void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
297 393
298/* Filters (multicast, vlan, receive) */ 394/* Filters (multicast, vlan, receive) */
299void e1000_init_rx_addrs(struct e1000_hw *hw); 395void e1000_init_rx_addrs(struct e1000_hw *hw);
@@ -313,7 +409,6 @@ int32_t e1000_led_off(struct e1000_hw *hw);
313/* Adaptive IFS Functions */ 409/* Adaptive IFS Functions */
314 410
315/* Everything else */ 411/* Everything else */
316uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw);
317void e1000_clear_hw_cntrs(struct e1000_hw *hw); 412void e1000_clear_hw_cntrs(struct e1000_hw *hw);
318void e1000_reset_adaptive(struct e1000_hw *hw); 413void e1000_reset_adaptive(struct e1000_hw *hw);
319void e1000_update_adaptive(struct e1000_hw *hw); 414void e1000_update_adaptive(struct e1000_hw *hw);
@@ -330,6 +425,19 @@ void e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value);
330void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value); 425void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
331int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up); 426int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up);
332int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active); 427int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
428int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
429void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
430void e1000_enable_pciex_master(struct e1000_hw *hw);
431int32_t e1000_disable_pciex_master(struct e1000_hw *hw);
432int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
433int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
434int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
435void e1000_release_software_semaphore(struct e1000_hw *hw);
436int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
437int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
438void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
439int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
440uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
333 441
334#define E1000_READ_REG_IO(a, reg) \ 442#define E1000_READ_REG_IO(a, reg) \
335 e1000_read_reg_io((a), E1000_##reg) 443 e1000_read_reg_io((a), E1000_##reg)
@@ -369,6 +477,10 @@ int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
369#define E1000_DEV_ID_82546GB_SERDES 0x107B 477#define E1000_DEV_ID_82546GB_SERDES 0x107B
370#define E1000_DEV_ID_82546GB_PCIE 0x108A 478#define E1000_DEV_ID_82546GB_PCIE 0x108A
371#define E1000_DEV_ID_82547EI 0x1019 479#define E1000_DEV_ID_82547EI 0x1019
480#define E1000_DEV_ID_82573E 0x108B
481#define E1000_DEV_ID_82573E_IAMT 0x108C
482
483#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
372 484
373#define NODE_ADDRESS_SIZE 6 485#define NODE_ADDRESS_SIZE 6
374#define ETH_LENGTH_OF_ADDRESS 6 486#define ETH_LENGTH_OF_ADDRESS 6
@@ -381,6 +493,7 @@ int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
381#define E1000_REVISION_0 0 493#define E1000_REVISION_0 0
382#define E1000_REVISION_1 1 494#define E1000_REVISION_1 1
383#define E1000_REVISION_2 2 495#define E1000_REVISION_2 2
496#define E1000_REVISION_3 3
384 497
385#define SPEED_10 10 498#define SPEED_10 10
386#define SPEED_100 100 499#define SPEED_100 100
@@ -437,6 +550,7 @@ int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
437 E1000_IMS_RXSEQ | \ 550 E1000_IMS_RXSEQ | \
438 E1000_IMS_LSC) 551 E1000_IMS_LSC)
439 552
553
440/* Number of high/low register pairs in the RAR. The RAR (Receive Address 554/* Number of high/low register pairs in the RAR. The RAR (Receive Address
441 * Registers) holds the directed and multicast addresses that we monitor. We 555 * Registers) holds the directed and multicast addresses that we monitor. We
442 * reserve one of these spots for our directed address, allowing us room for 556 * reserve one of these spots for our directed address, allowing us room for
@@ -457,14 +571,74 @@ struct e1000_rx_desc {
457 uint16_t special; 571 uint16_t special;
458}; 572};
459 573
574/* Receive Descriptor - Extended */
575union e1000_rx_desc_extended {
576 struct {
577 uint64_t buffer_addr;
578 uint64_t reserved;
579 } read;
580 struct {
581 struct {
582 uint32_t mrq; /* Multiple Rx Queues */
583 union {
584 uint32_t rss; /* RSS Hash */
585 struct {
586 uint16_t ip_id; /* IP id */
587 uint16_t csum; /* Packet Checksum */
588 } csum_ip;
589 } hi_dword;
590 } lower;
591 struct {
592 uint32_t status_error; /* ext status/error */
593 uint16_t length;
594 uint16_t vlan; /* VLAN tag */
595 } upper;
596 } wb; /* writeback */
597};
598
599#define MAX_PS_BUFFERS 4
600/* Receive Descriptor - Packet Split */
601union e1000_rx_desc_packet_split {
602 struct {
603 /* one buffer for protocol header(s), three data buffers */
604 uint64_t buffer_addr[MAX_PS_BUFFERS];
605 } read;
606 struct {
607 struct {
608 uint32_t mrq; /* Multiple Rx Queues */
609 union {
610 uint32_t rss; /* RSS Hash */
611 struct {
612 uint16_t ip_id; /* IP id */
613 uint16_t csum; /* Packet Checksum */
614 } csum_ip;
615 } hi_dword;
616 } lower;
617 struct {
618 uint32_t status_error; /* ext status/error */
619 uint16_t length0; /* length of buffer 0 */
620 uint16_t vlan; /* VLAN tag */
621 } middle;
622 struct {
623 uint16_t header_status;
624 uint16_t length[3]; /* length of buffers 1-3 */
625 } upper;
626 uint64_t reserved;
627 } wb; /* writeback */
628};
629
460/* Receive Decriptor bit definitions */ 630/* Receive Decriptor bit definitions */
461#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 631#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
462#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 632#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
463#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 633#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
464#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 634#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
635#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */
465#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 636#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
466#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 637#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
467#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 638#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
639#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
640#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
641#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
468#define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 642#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
469#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 643#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
470#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 644#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
@@ -474,9 +648,20 @@ struct e1000_rx_desc {
474#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 648#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
475#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 649#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
476#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 650#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
477#define E1000_RXD_SPC_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */ 651#define E1000_RXD_SPC_PRI_SHIFT 13
478#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ 652#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
479#define E1000_RXD_SPC_CFI_SHIFT 0x000C /* CFI is bit 12 */ 653#define E1000_RXD_SPC_CFI_SHIFT 12
654
655#define E1000_RXDEXT_STATERR_CE 0x01000000
656#define E1000_RXDEXT_STATERR_SE 0x02000000
657#define E1000_RXDEXT_STATERR_SEQ 0x04000000
658#define E1000_RXDEXT_STATERR_CXE 0x10000000
659#define E1000_RXDEXT_STATERR_TCPE 0x20000000
660#define E1000_RXDEXT_STATERR_IPE 0x40000000
661#define E1000_RXDEXT_STATERR_RXE 0x80000000
662
663#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
664#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
480 665
481/* mask to determine if packets should be dropped due to frame errors */ 666/* mask to determine if packets should be dropped due to frame errors */
482#define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 667#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
@@ -486,6 +671,15 @@ struct e1000_rx_desc {
486 E1000_RXD_ERR_CXE | \ 671 E1000_RXD_ERR_CXE | \
487 E1000_RXD_ERR_RXE) 672 E1000_RXD_ERR_RXE)
488 673
674
675/* Same mask, but for extended and packet split descriptors */
676#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
677 E1000_RXDEXT_STATERR_CE | \
678 E1000_RXDEXT_STATERR_SE | \
679 E1000_RXDEXT_STATERR_SEQ | \
680 E1000_RXDEXT_STATERR_CXE | \
681 E1000_RXDEXT_STATERR_RXE)
682
489/* Transmit Descriptor */ 683/* Transmit Descriptor */
490struct e1000_tx_desc { 684struct e1000_tx_desc {
491 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 685 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
@@ -667,6 +861,7 @@ struct e1000_ffvt_entry {
667#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ 861#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
668#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ 862#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
669#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ 863#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
864#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
670#define E1000_RCTL 0x00100 /* RX Control - RW */ 865#define E1000_RCTL 0x00100 /* RX Control - RW */
671#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ 866#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
672#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ 867#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
@@ -676,9 +871,23 @@ struct e1000_ffvt_entry {
676#define E1000_TBT 0x00448 /* TX Burst Timer - RW */ 871#define E1000_TBT 0x00448 /* TX Burst Timer - RW */
677#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ 872#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
678#define E1000_LEDCTL 0x00E00 /* LED Control - RW */ 873#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
874#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
875#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
679#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ 876#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
877#define E1000_PBS 0x01008 /* Packet Buffer Size */
878#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
879#define E1000_FLASH_UPDATES 1000
880#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
881#define E1000_FLASHT 0x01028 /* FLASH Timer Register */
882#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
883#define E1000_FLSWCTL 0x01030 /* FLASH control register */
884#define E1000_FLSWDATA 0x01034 /* FLASH data register */
885#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
886#define E1000_FLOP 0x0103C /* FLASH Opcode Register */
887#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
680#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ 888#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
681#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ 889#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
890#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
682#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */ 891#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
683#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */ 892#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
684#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */ 893#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
@@ -688,6 +897,7 @@ struct e1000_ffvt_entry {
688#define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */ 897#define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */
689#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ 898#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
690#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ 899#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
900#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
691#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ 901#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
692#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ 902#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
693#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ 903#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
@@ -703,6 +913,14 @@ struct e1000_ffvt_entry {
703#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ 913#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
704#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ 914#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
705#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ 915#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
916#define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */
917#define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */
918#define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */
919#define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */
920#define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */
921#define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */
922#define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */
923#define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */
706#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ 924#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
707#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ 925#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
708#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ 926#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
@@ -761,7 +979,17 @@ struct e1000_ffvt_entry {
761#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ 979#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
762#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ 980#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
763#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ 981#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
982#define E1000_IAC 0x4100 /* Interrupt Assertion Count */
983#define E1000_ICRXPTC 0x4104 /* Interrupt Cause Rx Packet Timer Expire Count */
984#define E1000_ICRXATC 0x4108 /* Interrupt Cause Rx Absolute Timer Expire Count */
985#define E1000_ICTXPTC 0x410C /* Interrupt Cause Tx Packet Timer Expire Count */
986#define E1000_ICTXATC 0x4110 /* Interrupt Cause Tx Absolute Timer Expire Count */
987#define E1000_ICTXQEC 0x4118 /* Interrupt Cause Tx Queue Empty Count */
988#define E1000_ICTXQMTC 0x411C /* Interrupt Cause Tx Queue Minimum Threshold Count */
989#define E1000_ICRXDMTC 0x4120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */
990#define E1000_ICRXOC 0x4124 /* Interrupt Cause Receiver Overrun Count */
764#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ 991#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
992#define E1000_RFCTL 0x05008 /* Receive Filter Control*/
765#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ 993#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
766#define E1000_RA 0x05400 /* Receive Address - RW Array */ 994#define E1000_RA 0x05400 /* Receive Address - RW Array */
767#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ 995#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
@@ -779,6 +1007,16 @@ struct e1000_ffvt_entry {
779#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ 1007#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
780#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ 1008#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
781 1009
1010#define E1000_GCR 0x05B00 /* PCI-Ex Control */
1011#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
1012#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
1013#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
1014#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
1015#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
1016#define E1000_SWSM 0x05B50 /* SW Semaphore */
1017#define E1000_FWSM 0x05B54 /* FW Semaphore */
1018#define E1000_FFLT_DBG 0x05F04 /* Debug Register */
1019#define E1000_HICR 0x08F00 /* Host Inteface Control */
782/* Register Set (82542) 1020/* Register Set (82542)
783 * 1021 *
784 * Some of the 82542 registers are located at different offsets than they are 1022 * Some of the 82542 registers are located at different offsets than they are
@@ -829,6 +1067,18 @@ struct e1000_ffvt_entry {
829#define E1000_82542_VFTA 0x00600 1067#define E1000_82542_VFTA 0x00600
830#define E1000_82542_LEDCTL E1000_LEDCTL 1068#define E1000_82542_LEDCTL E1000_LEDCTL
831#define E1000_82542_PBA E1000_PBA 1069#define E1000_82542_PBA E1000_PBA
1070#define E1000_82542_PBS E1000_PBS
1071#define E1000_82542_EEMNGCTL E1000_EEMNGCTL
1072#define E1000_82542_EEARBC E1000_EEARBC
1073#define E1000_82542_FLASHT E1000_FLASHT
1074#define E1000_82542_EEWR E1000_EEWR
1075#define E1000_82542_FLSWCTL E1000_FLSWCTL
1076#define E1000_82542_FLSWDATA E1000_FLSWDATA
1077#define E1000_82542_FLSWCNT E1000_FLSWCNT
1078#define E1000_82542_FLOP E1000_FLOP
1079#define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL
1080#define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE
1081#define E1000_82542_ERT E1000_ERT
832#define E1000_82542_RXDCTL E1000_RXDCTL 1082#define E1000_82542_RXDCTL E1000_RXDCTL
833#define E1000_82542_RADV E1000_RADV 1083#define E1000_82542_RADV E1000_RADV
834#define E1000_82542_RSRPD E1000_RSRPD 1084#define E1000_82542_RSRPD E1000_RSRPD
@@ -913,6 +1163,38 @@ struct e1000_ffvt_entry {
913#define E1000_82542_FFMT E1000_FFMT 1163#define E1000_82542_FFMT E1000_FFMT
914#define E1000_82542_FFVT E1000_FFVT 1164#define E1000_82542_FFVT E1000_FFVT
915#define E1000_82542_HOST_IF E1000_HOST_IF 1165#define E1000_82542_HOST_IF E1000_HOST_IF
1166#define E1000_82542_IAM E1000_IAM
1167#define E1000_82542_EEMNGCTL E1000_EEMNGCTL
1168#define E1000_82542_PSRCTL E1000_PSRCTL
1169#define E1000_82542_RAID E1000_RAID
1170#define E1000_82542_TARC0 E1000_TARC0
1171#define E1000_82542_TDBAL1 E1000_TDBAL1
1172#define E1000_82542_TDBAH1 E1000_TDBAH1
1173#define E1000_82542_TDLEN1 E1000_TDLEN1
1174#define E1000_82542_TDH1 E1000_TDH1
1175#define E1000_82542_TDT1 E1000_TDT1
1176#define E1000_82542_TXDCTL1 E1000_TXDCTL1
1177#define E1000_82542_TARC1 E1000_TARC1
1178#define E1000_82542_RFCTL E1000_RFCTL
1179#define E1000_82542_GCR E1000_GCR
1180#define E1000_82542_GSCL_1 E1000_GSCL_1
1181#define E1000_82542_GSCL_2 E1000_GSCL_2
1182#define E1000_82542_GSCL_3 E1000_GSCL_3
1183#define E1000_82542_GSCL_4 E1000_GSCL_4
1184#define E1000_82542_FACTPS E1000_FACTPS
1185#define E1000_82542_SWSM E1000_SWSM
1186#define E1000_82542_FWSM E1000_FWSM
1187#define E1000_82542_FFLT_DBG E1000_FFLT_DBG
1188#define E1000_82542_IAC E1000_IAC
1189#define E1000_82542_ICRXPTC E1000_ICRXPTC
1190#define E1000_82542_ICRXATC E1000_ICRXATC
1191#define E1000_82542_ICTXPTC E1000_ICTXPTC
1192#define E1000_82542_ICTXATC E1000_ICTXATC
1193#define E1000_82542_ICTXQEC E1000_ICTXQEC
1194#define E1000_82542_ICTXQMTC E1000_ICTXQMTC
1195#define E1000_82542_ICRXDMTC E1000_ICRXDMTC
1196#define E1000_82542_ICRXOC E1000_ICRXOC
1197#define E1000_82542_HICR E1000_HICR
916 1198
917/* Statistics counters collected by the MAC */ 1199/* Statistics counters collected by the MAC */
918struct e1000_hw_stats { 1200struct e1000_hw_stats {
@@ -974,11 +1256,21 @@ struct e1000_hw_stats {
974 uint64_t bptc; 1256 uint64_t bptc;
975 uint64_t tsctc; 1257 uint64_t tsctc;
976 uint64_t tsctfc; 1258 uint64_t tsctfc;
1259 uint64_t iac;
1260 uint64_t icrxptc;
1261 uint64_t icrxatc;
1262 uint64_t ictxptc;
1263 uint64_t ictxatc;
1264 uint64_t ictxqec;
1265 uint64_t ictxqmtc;
1266 uint64_t icrxdmtc;
1267 uint64_t icrxoc;
977}; 1268};
978 1269
979/* Structure containing variables used by the shared code (e1000_hw.c) */ 1270/* Structure containing variables used by the shared code (e1000_hw.c) */
980struct e1000_hw { 1271struct e1000_hw {
981 uint8_t __iomem *hw_addr; 1272 uint8_t *hw_addr;
1273 uint8_t *flash_address;
982 e1000_mac_type mac_type; 1274 e1000_mac_type mac_type;
983 e1000_phy_type phy_type; 1275 e1000_phy_type phy_type;
984 uint32_t phy_init_script; 1276 uint32_t phy_init_script;
@@ -993,6 +1285,7 @@ struct e1000_hw {
993 e1000_ms_type original_master_slave; 1285 e1000_ms_type original_master_slave;
994 e1000_ffe_config ffe_config_state; 1286 e1000_ffe_config ffe_config_state;
995 uint32_t asf_firmware_present; 1287 uint32_t asf_firmware_present;
1288 uint32_t eeprom_semaphore_present;
996 unsigned long io_base; 1289 unsigned long io_base;
997 uint32_t phy_id; 1290 uint32_t phy_id;
998 uint32_t phy_revision; 1291 uint32_t phy_revision;
@@ -1009,6 +1302,8 @@ struct e1000_hw {
1009 uint32_t ledctl_default; 1302 uint32_t ledctl_default;
1010 uint32_t ledctl_mode1; 1303 uint32_t ledctl_mode1;
1011 uint32_t ledctl_mode2; 1304 uint32_t ledctl_mode2;
1305 boolean_t tx_pkt_filtering;
1306 struct e1000_host_mng_dhcp_cookie mng_cookie;
1012 uint16_t phy_spd_default; 1307 uint16_t phy_spd_default;
1013 uint16_t autoneg_advertised; 1308 uint16_t autoneg_advertised;
1014 uint16_t pci_cmd_word; 1309 uint16_t pci_cmd_word;
@@ -1047,16 +1342,24 @@ struct e1000_hw {
1047 boolean_t adaptive_ifs; 1342 boolean_t adaptive_ifs;
1048 boolean_t ifs_params_forced; 1343 boolean_t ifs_params_forced;
1049 boolean_t in_ifs_mode; 1344 boolean_t in_ifs_mode;
1345 boolean_t mng_reg_access_disabled;
1050}; 1346};
1051 1347
1052 1348
1053#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ 1349#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
1054#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ 1350#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
1351#define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */
1352#define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1353#define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */
1354#define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1355#define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */
1356#define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */
1055/* Register Bit Masks */ 1357/* Register Bit Masks */
1056/* Device Control */ 1358/* Device Control */
1057#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 1359#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
1058#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ 1360#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
1059#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ 1361#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
1362#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
1060#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 1363#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
1061#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ 1364#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
1062#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ 1365#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
@@ -1070,6 +1373,7 @@ struct e1000_hw {
1070#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ 1373#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
1071#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 1374#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
1072#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 1375#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
1376#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */
1073#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 1377#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
1074#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 1378#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
1075#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ 1379#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
@@ -1089,6 +1393,7 @@ struct e1000_hw {
1089#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 1393#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
1090#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 1394#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
1091#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 1395#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
1396#define E1000_STATUS_FUNC_SHIFT 2
1092#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ 1397#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
1093#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 1398#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
1094#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 1399#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
@@ -1098,6 +1403,8 @@ struct e1000_hw {
1098#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 1403#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
1099#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 1404#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
1100#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ 1405#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
1406#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */
1407#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
1101#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ 1408#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
1102#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ 1409#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
1103#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ 1410#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
@@ -1128,6 +1435,18 @@ struct e1000_hw {
1128#ifndef E1000_EEPROM_GRANT_ATTEMPTS 1435#ifndef E1000_EEPROM_GRANT_ATTEMPTS
1129#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ 1436#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1130#endif 1437#endif
1438#define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */
1439#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */
1440#define E1000_EECD_SIZE_EX_SHIFT 11
1441#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
1442#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
1443#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
1444#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1445#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
1446#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
1447#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
1448#define E1000_STM_OPCODE 0xDB00
1449#define E1000_HICR_FW_RESET 0xC0
1131 1450
1132/* EEPROM Read */ 1451/* EEPROM Read */
1133#define E1000_EERD_START 0x00000001 /* Start Read */ 1452#define E1000_EERD_START 0x00000001 /* Start Read */
@@ -1171,6 +1490,8 @@ struct e1000_hw {
1171#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 1490#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
1172#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 1491#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
1173#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 1492#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
1493#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
1494#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
1174 1495
1175/* MDI Control */ 1496/* MDI Control */
1176#define E1000_MDIC_DATA_MASK 0x0000FFFF 1497#define E1000_MDIC_DATA_MASK 0x0000FFFF
@@ -1187,14 +1508,17 @@ struct e1000_hw {
1187/* LED Control */ 1508/* LED Control */
1188#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 1509#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
1189#define E1000_LEDCTL_LED0_MODE_SHIFT 0 1510#define E1000_LEDCTL_LED0_MODE_SHIFT 0
1511#define E1000_LEDCTL_LED0_BLINK_RATE 0x0000020
1190#define E1000_LEDCTL_LED0_IVRT 0x00000040 1512#define E1000_LEDCTL_LED0_IVRT 0x00000040
1191#define E1000_LEDCTL_LED0_BLINK 0x00000080 1513#define E1000_LEDCTL_LED0_BLINK 0x00000080
1192#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 1514#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
1193#define E1000_LEDCTL_LED1_MODE_SHIFT 8 1515#define E1000_LEDCTL_LED1_MODE_SHIFT 8
1516#define E1000_LEDCTL_LED1_BLINK_RATE 0x0002000
1194#define E1000_LEDCTL_LED1_IVRT 0x00004000 1517#define E1000_LEDCTL_LED1_IVRT 0x00004000
1195#define E1000_LEDCTL_LED1_BLINK 0x00008000 1518#define E1000_LEDCTL_LED1_BLINK 0x00008000
1196#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 1519#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
1197#define E1000_LEDCTL_LED2_MODE_SHIFT 16 1520#define E1000_LEDCTL_LED2_MODE_SHIFT 16
1521#define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000
1198#define E1000_LEDCTL_LED2_IVRT 0x00400000 1522#define E1000_LEDCTL_LED2_IVRT 0x00400000
1199#define E1000_LEDCTL_LED2_BLINK 0x00800000 1523#define E1000_LEDCTL_LED2_BLINK 0x00800000
1200#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 1524#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
@@ -1238,6 +1562,10 @@ struct e1000_hw {
1238#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 1562#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
1239#define E1000_ICR_TXD_LOW 0x00008000 1563#define E1000_ICR_TXD_LOW 0x00008000
1240#define E1000_ICR_SRPD 0x00010000 1564#define E1000_ICR_SRPD 0x00010000
1565#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
1566#define E1000_ICR_MNG 0x00040000 /* Manageability event */
1567#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */
1568#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */
1241 1569
1242/* Interrupt Cause Set */ 1570/* Interrupt Cause Set */
1243#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1571#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
@@ -1255,6 +1583,9 @@ struct e1000_hw {
1255#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1583#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1256#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW 1584#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
1257#define E1000_ICS_SRPD E1000_ICR_SRPD 1585#define E1000_ICS_SRPD E1000_ICR_SRPD
1586#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */
1587#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */
1588#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */
1258 1589
1259/* Interrupt Mask Set */ 1590/* Interrupt Mask Set */
1260#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1591#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
@@ -1272,6 +1603,9 @@ struct e1000_hw {
1272#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1603#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1273#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW 1604#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
1274#define E1000_IMS_SRPD E1000_ICR_SRPD 1605#define E1000_IMS_SRPD E1000_ICR_SRPD
1606#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */
1607#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */
1608#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */
1275 1609
1276/* Interrupt Mask Clear */ 1610/* Interrupt Mask Clear */
1277#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1611#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
@@ -1289,6 +1623,9 @@ struct e1000_hw {
1289#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1623#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1290#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW 1624#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
1291#define E1000_IMC_SRPD E1000_ICR_SRPD 1625#define E1000_IMC_SRPD E1000_ICR_SRPD
1626#define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */
1627#define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */
1628#define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */
1292 1629
1293/* Receive Control */ 1630/* Receive Control */
1294#define E1000_RCTL_RST 0x00000001 /* Software reset */ 1631#define E1000_RCTL_RST 0x00000001 /* Software reset */
@@ -1301,6 +1638,8 @@ struct e1000_hw {
1301#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 1638#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
1302#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ 1639#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
1303#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 1640#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
1641#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
1642#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
1304#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ 1643#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
1305#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ 1644#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
1306#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ 1645#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
@@ -1327,6 +1666,34 @@ struct e1000_hw {
1327#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 1666#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
1328#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 1667#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
1329#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 1668#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
1669#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
1670#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
1671
1672/* Use byte values for the following shift parameters
1673 * Usage:
1674 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
1675 * E1000_PSRCTL_BSIZE0_MASK) |
1676 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
1677 * E1000_PSRCTL_BSIZE1_MASK) |
1678 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
1679 * E1000_PSRCTL_BSIZE2_MASK) |
1680 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
1681 * E1000_PSRCTL_BSIZE3_MASK))
1682 * where value0 = [128..16256], default=256
1683 * value1 = [1024..64512], default=4096
1684 * value2 = [0..64512], default=4096
1685 * value3 = [0..64512], default=0
1686 */
1687
1688#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
1689#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
1690#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
1691#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
1692
1693#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
1694#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
1695#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
1696#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
1330 1697
1331/* Receive Descriptor */ 1698/* Receive Descriptor */
1332#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */ 1699#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
@@ -1341,6 +1708,23 @@ struct e1000_hw {
1341#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 1708#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
1342#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 1709#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
1343 1710
1711/* Header split receive */
1712#define E1000_RFCTL_ISCSI_DIS 0x00000001
1713#define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E
1714#define E1000_RFCTL_ISCSI_DWC_SHIFT 1
1715#define E1000_RFCTL_NFSW_DIS 0x00000040
1716#define E1000_RFCTL_NFSR_DIS 0x00000080
1717#define E1000_RFCTL_NFS_VER_MASK 0x00000300
1718#define E1000_RFCTL_NFS_VER_SHIFT 8
1719#define E1000_RFCTL_IPV6_DIS 0x00000400
1720#define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800
1721#define E1000_RFCTL_ACK_DIS 0x00001000
1722#define E1000_RFCTL_ACKD_DIS 0x00002000
1723#define E1000_RFCTL_IPFRSP_DIS 0x00004000
1724#define E1000_RFCTL_EXTEN 0x00008000
1725#define E1000_RFCTL_IPV6_EX_DIS 0x00010000
1726#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
1727
1344/* Receive Descriptor Control */ 1728/* Receive Descriptor Control */
1345#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */ 1729#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
1346#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */ 1730#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
@@ -1354,6 +1738,8 @@ struct e1000_hw {
1354#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 1738#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
1355#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ 1739#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
1356#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 1740#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
1741#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
1742 still to be processed. */
1357 1743
1358/* Transmit Configuration Word */ 1744/* Transmit Configuration Word */
1359#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 1745#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
@@ -1387,12 +1773,16 @@ struct e1000_hw {
1387#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ 1773#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
1388#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 1774#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
1389#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ 1775#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
1776#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
1390 1777
1391/* Receive Checksum Control */ 1778/* Receive Checksum Control */
1392#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ 1779#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
1393#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 1780#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
1394#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 1781#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
1395#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ 1782#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
1783#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
1784#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
1785
1396 1786
1397/* Definitions for power management and wakeup registers */ 1787/* Definitions for power management and wakeup registers */
1398/* Wake Up Control */ 1788/* Wake Up Control */
@@ -1411,6 +1801,7 @@ struct e1000_hw {
1411#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 1801#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
1412#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 1802#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
1413#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ 1803#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
1804#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
1414#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 1805#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
1415#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ 1806#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
1416#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ 1807#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
@@ -1446,13 +1837,19 @@ struct e1000_hw {
1446#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 1837#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
1447#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery 1838#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
1448 * Filtering */ 1839 * Filtering */
1840#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
1449#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ 1841#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
1450#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 1842#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
1451#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ 1843#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
1844#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
1452#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address 1845#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address
1453 * filtering */ 1846 * filtering */
1454#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host 1847#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host
1455 * memory */ 1848 * memory */
1849#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address
1850 * filtering */
1851#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */
1852#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
1456#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ 1853#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
1457#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ 1854#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
1458#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ 1855#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
@@ -1463,11 +1860,97 @@ struct e1000_hw {
1463#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ 1860#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
1464#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ 1861#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
1465 1862
1863/* SW Semaphore Register */
1864#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
1865#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
1866#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
1867#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
1868
1869/* FW Semaphore Register */
1870#define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */
1871#define E1000_FWSM_MODE_SHIFT 1
1872#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */
1873
1874/* FFLT Debug Register */
1875#define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */
1876
1877typedef enum {
1878 e1000_mng_mode_none = 0,
1879 e1000_mng_mode_asf,
1880 e1000_mng_mode_pt,
1881 e1000_mng_mode_ipmi,
1882 e1000_mng_mode_host_interface_only
1883} e1000_mng_mode;
1884
1885/* Host Inteface Control Register */
1886#define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */
1887#define E1000_HICR_C 0x00000002 /* Driver sets this bit when done
1888 * to put command in RAM */
1889#define E1000_HICR_SV 0x00000004 /* Status Validity */
1890#define E1000_HICR_FWR 0x00000080 /* FW reset. Set by the Host */
1891
1892/* Host Interface Command Interface - Address range 0x8800-0x8EFF */
1893#define E1000_HI_MAX_DATA_LENGTH 252 /* Host Interface data length */
1894#define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */
1895#define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */
1896#define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */
1897
1898struct e1000_host_command_header {
1899 uint8_t command_id;
1900 uint8_t command_length;
1901 uint8_t command_options; /* I/F bits for command, status for return */
1902 uint8_t checksum;
1903};
1904struct e1000_host_command_info {
1905 struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
1906 uint8_t command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */
1907};
1908
1909/* Host SMB register #0 */
1910#define E1000_HSMC0R_CLKIN 0x00000001 /* SMB Clock in */
1911#define E1000_HSMC0R_DATAIN 0x00000002 /* SMB Data in */
1912#define E1000_HSMC0R_DATAOUT 0x00000004 /* SMB Data out */
1913#define E1000_HSMC0R_CLKOUT 0x00000008 /* SMB Clock out */
1914
1915/* Host SMB register #1 */
1916#define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN
1917#define E1000_HSMC1R_DATAIN E1000_HSMC0R_DATAIN
1918#define E1000_HSMC1R_DATAOUT E1000_HSMC0R_DATAOUT
1919#define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT
1920
1921/* FW Status Register */
1922#define E1000_FWSTS_FWS_MASK 0x000000FF /* FW Status */
1923
1466/* Wake Up Packet Length */ 1924/* Wake Up Packet Length */
1467#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ 1925#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
1468 1926
1469#define E1000_MDALIGN 4096 1927#define E1000_MDALIGN 4096
1470 1928
1929#define E1000_GCR_BEM32 0x00400000
1930/* Function Active and Power State to MNG */
1931#define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003
1932#define E1000_FACTPS_LAN0_VALID 0x00000004
1933#define E1000_FACTPS_FUNC0_AUX_EN 0x00000008
1934#define E1000_FACTPS_FUNC1_POWER_STATE_MASK 0x000000C0
1935#define E1000_FACTPS_FUNC1_POWER_STATE_SHIFT 6
1936#define E1000_FACTPS_LAN1_VALID 0x00000100
1937#define E1000_FACTPS_FUNC1_AUX_EN 0x00000200
1938#define E1000_FACTPS_FUNC2_POWER_STATE_MASK 0x00003000
1939#define E1000_FACTPS_FUNC2_POWER_STATE_SHIFT 12
1940#define E1000_FACTPS_IDE_ENABLE 0x00004000
1941#define E1000_FACTPS_FUNC2_AUX_EN 0x00008000
1942#define E1000_FACTPS_FUNC3_POWER_STATE_MASK 0x000C0000
1943#define E1000_FACTPS_FUNC3_POWER_STATE_SHIFT 18
1944#define E1000_FACTPS_SP_ENABLE 0x00100000
1945#define E1000_FACTPS_FUNC3_AUX_EN 0x00200000
1946#define E1000_FACTPS_FUNC4_POWER_STATE_MASK 0x03000000
1947#define E1000_FACTPS_FUNC4_POWER_STATE_SHIFT 24
1948#define E1000_FACTPS_IPMI_ENABLE 0x04000000
1949#define E1000_FACTPS_FUNC4_AUX_EN 0x08000000
1950#define E1000_FACTPS_MNGCG 0x20000000
1951#define E1000_FACTPS_LAN_FUNC_SEL 0x40000000
1952#define E1000_FACTPS_PM_STATE_CHANGED 0x80000000
1953
1471/* EEPROM Commands - Microwire */ 1954/* EEPROM Commands - Microwire */
1472#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */ 1955#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
1473#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */ 1956#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
@@ -1477,22 +1960,20 @@ struct e1000_hw {
1477 1960
1478/* EEPROM Commands - SPI */ 1961/* EEPROM Commands - SPI */
1479#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 1962#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
1480#define EEPROM_READ_OPCODE_SPI 0x3 /* EEPROM read opcode */ 1963#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
1481#define EEPROM_WRITE_OPCODE_SPI 0x2 /* EEPROM write opcode */ 1964#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
1482#define EEPROM_A8_OPCODE_SPI 0x8 /* opcode bit-3 = address bit-8 */ 1965#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1483#define EEPROM_WREN_OPCODE_SPI 0x6 /* EEPROM set Write Enable latch */ 1966#define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */
1484#define EEPROM_WRDI_OPCODE_SPI 0x4 /* EEPROM reset Write Enable latch */ 1967#define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */
1485#define EEPROM_RDSR_OPCODE_SPI 0x5 /* EEPROM read Status register */ 1968#define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */
1486#define EEPROM_WRSR_OPCODE_SPI 0x1 /* EEPROM write Status register */ 1969#define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */
1970#define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
1971#define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
1972#define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
1487 1973
1488/* EEPROM Size definitions */ 1974/* EEPROM Size definitions */
1489#define EEPROM_SIZE_16KB 0x1800 1975#define EEPROM_WORD_SIZE_SHIFT 6
1490#define EEPROM_SIZE_8KB 0x1400 1976#define EEPROM_SIZE_SHIFT 10
1491#define EEPROM_SIZE_4KB 0x1000
1492#define EEPROM_SIZE_2KB 0x0C00
1493#define EEPROM_SIZE_1KB 0x0800
1494#define EEPROM_SIZE_512B 0x0400
1495#define EEPROM_SIZE_128B 0x0000
1496#define EEPROM_SIZE_MASK 0x1C00 1977#define EEPROM_SIZE_MASK 0x1C00
1497 1978
1498/* EEPROM Word Offsets */ 1979/* EEPROM Word Offsets */
@@ -1606,7 +2087,22 @@ struct e1000_hw {
1606#define IFS_MIN 40 2087#define IFS_MIN 40
1607#define IFS_RATIO 4 2088#define IFS_RATIO 4
1608 2089
2090/* Extended Configuration Control and Size */
2091#define E1000_EXTCNF_CTRL_PCIE_WRITE_ENABLE 0x00000001
2092#define E1000_EXTCNF_CTRL_PHY_WRITE_ENABLE 0x00000002
2093#define E1000_EXTCNF_CTRL_D_UD_ENABLE 0x00000004
2094#define E1000_EXTCNF_CTRL_D_UD_LATENCY 0x00000008
2095#define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010
2096#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
2097#define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040
2098#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x1FFF0000
2099
2100#define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF
2101#define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00
2102#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000
2103
1609/* PBA constants */ 2104/* PBA constants */
2105#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */
1610#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ 2106#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
1611#define E1000_PBA_22K 0x0016 2107#define E1000_PBA_22K 0x0016
1612#define E1000_PBA_24K 0x0018 2108#define E1000_PBA_24K 0x0018
@@ -1663,6 +2159,13 @@ struct e1000_hw {
1663/* Number of milliseconds we wait for auto-negotiation to complete */ 2159/* Number of milliseconds we wait for auto-negotiation to complete */
1664#define LINK_UP_TIMEOUT 500 2160#define LINK_UP_TIMEOUT 500
1665 2161
2162/* Number of 100 microseconds we wait for PCI Express master disable */
2163#define MASTER_DISABLE_TIMEOUT 800
2164/* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */
2165#define AUTO_READ_DONE_TIMEOUT 10
2166/* Number of milliseconds we wait for PHY configuration done after MAC reset */
2167#define PHY_CFG_TIMEOUT 40
2168
1666#define E1000_TX_BUFFER_SIZE ((uint32_t)1514) 2169#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
1667 2170
1668/* The carrier extension symbol, as received by the NIC. */ 2171/* The carrier extension symbol, as received by the NIC. */
@@ -1763,6 +2266,7 @@ struct e1000_hw {
1763#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */ 2266#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
1764#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */ 2267#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
1765#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */ 2268#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
2269#define IGP02E1000_PHY_POWER_MGMT 0x19
1766#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */ 2270#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
1767 2271
1768/* IGP01E1000 AGC Registers - stores the cable length values*/ 2272/* IGP01E1000 AGC Registers - stores the cable length values*/
@@ -1771,12 +2275,20 @@ struct e1000_hw {
1771#define IGP01E1000_PHY_AGC_C 0x1472 2275#define IGP01E1000_PHY_AGC_C 0x1472
1772#define IGP01E1000_PHY_AGC_D 0x1872 2276#define IGP01E1000_PHY_AGC_D 0x1872
1773 2277
2278/* IGP02E1000 AGC Registers for cable length values */
2279#define IGP02E1000_PHY_AGC_A 0x11B1
2280#define IGP02E1000_PHY_AGC_B 0x12B1
2281#define IGP02E1000_PHY_AGC_C 0x14B1
2282#define IGP02E1000_PHY_AGC_D 0x18B1
2283
1774/* IGP01E1000 DSP Reset Register */ 2284/* IGP01E1000 DSP Reset Register */
1775#define IGP01E1000_PHY_DSP_RESET 0x1F33 2285#define IGP01E1000_PHY_DSP_RESET 0x1F33
1776#define IGP01E1000_PHY_DSP_SET 0x1F71 2286#define IGP01E1000_PHY_DSP_SET 0x1F71
1777#define IGP01E1000_PHY_DSP_FFE 0x1F35 2287#define IGP01E1000_PHY_DSP_FFE 0x1F35
1778 2288
1779#define IGP01E1000_PHY_CHANNEL_NUM 4 2289#define IGP01E1000_PHY_CHANNEL_NUM 4
2290#define IGP02E1000_PHY_CHANNEL_NUM 4
2291
1780#define IGP01E1000_PHY_AGC_PARAM_A 0x1171 2292#define IGP01E1000_PHY_AGC_PARAM_A 0x1171
1781#define IGP01E1000_PHY_AGC_PARAM_B 0x1271 2293#define IGP01E1000_PHY_AGC_PARAM_B 0x1271
1782#define IGP01E1000_PHY_AGC_PARAM_C 0x1471 2294#define IGP01E1000_PHY_AGC_PARAM_C 0x1471
@@ -2060,20 +2572,30 @@ struct e1000_hw {
2060#define IGP01E1000_MSE_CHANNEL_B 0x0F00 2572#define IGP01E1000_MSE_CHANNEL_B 0x0F00
2061#define IGP01E1000_MSE_CHANNEL_A 0xF000 2573#define IGP01E1000_MSE_CHANNEL_A 0xF000
2062 2574
2575#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
2576#define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */
2577#define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in D0a mode */
2578
2063/* IGP01E1000 DSP reset macros */ 2579/* IGP01E1000 DSP reset macros */
2064#define DSP_RESET_ENABLE 0x0 2580#define DSP_RESET_ENABLE 0x0
2065#define DSP_RESET_DISABLE 0x2 2581#define DSP_RESET_DISABLE 0x2
2066#define E1000_MAX_DSP_RESETS 10 2582#define E1000_MAX_DSP_RESETS 10
2067 2583
2068/* IGP01E1000 AGC Registers */ 2584/* IGP01E1000 & IGP02E1000 AGC Registers */
2069 2585
2070#define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */ 2586#define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */
2587#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */
2588
2589/* IGP02E1000 AGC Register Length 9-bit mask */
2590#define IGP02E1000_AGC_LENGTH_MASK 0x7F
2071 2591
2072/* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */ 2592/* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */
2073#define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128 2593#define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128
2594#define IGP02E1000_AGC_LENGTH_TABLE_SIZE 128
2074 2595
2075/* The precision of the length is +/- 10 meters */ 2596/* The precision error of the cable length is +/- 10 meters */
2076#define IGP01E1000_AGC_RANGE 10 2597#define IGP01E1000_AGC_RANGE 10
2598#define IGP02E1000_AGC_RANGE 10
2077 2599
2078/* IGP01E1000 PCS Initialization register */ 2600/* IGP01E1000 PCS Initialization register */
2079/* bits 3:6 in the PCS registers stores the channels polarity */ 2601/* bits 3:6 in the PCS registers stores the channels polarity */
@@ -2113,6 +2635,8 @@ struct e1000_hw {
2113#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID 2635#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
2114#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID 2636#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
2115#define M88E1011_I_REV_4 0x04 2637#define M88E1011_I_REV_4 0x04
2638#define M88E1111_I_PHY_ID 0x01410CC0
2639#define L1LXT971A_PHY_ID 0x001378E0
2116 2640
2117/* Miscellaneous PHY bit definitions. */ 2641/* Miscellaneous PHY bit definitions. */
2118#define PHY_PREAMBLE 0xFFFFFFFF 2642#define PHY_PREAMBLE 0xFFFFFFFF
diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c
index 82549a6fcfb3..137226d98d47 100644
--- a/drivers/net/e1000/e1000_main.c
+++ b/drivers/net/e1000/e1000_main.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 3
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved. 4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free 7 under the terms of the GNU General Public License as published by the Free
@@ -29,33 +29,9 @@
29#include "e1000.h" 29#include "e1000.h"
30 30
31/* Change Log 31/* Change Log
32 * 5.3.12 6/7/04 32 * 6.0.44+ 2/15/05
33 * - kcompat NETIF_MSG for older kernels (2.4.9) <sean.p.mcdermott@intel.com> 33 * o applied Anton's patch to resolve tx hang in hardware
34 * - if_mii support and associated kcompat for older kernels 34 * o Applied Andrew Mortons patch - e1000 stops working after resume
35 * - More errlogging support from Jon Mason <jonmason@us.ibm.com>
36 * - Fix TSO issues on PPC64 machines -- Jon Mason <jonmason@us.ibm.com>
37 *
38 * 5.7.1 12/16/04
39 * - Resurrect 82547EI/GI related fix in e1000_intr to avoid deadlocks. This
40 * fix was removed as it caused system instability. The suspected cause of
41 * this is the called to e1000_irq_disable in e1000_intr. Inlined the
42 * required piece of e1000_irq_disable into e1000_intr - Anton Blanchard
43 * 5.7.0 12/10/04
44 * - include fix to the condition that determines when to quit NAPI - Robert Olsson
45 * - use netif_poll_{disable/enable} to synchronize between NAPI and i/f up/down
46 * 5.6.5 11/01/04
47 * - Enabling NETIF_F_SG without checksum offload is illegal -
48 John Mason <jdmason@us.ibm.com>
49 * 5.6.3 10/26/04
50 * - Remove redundant initialization - Jamal Hadi
51 * - Reset buffer_info->dma in tx resource cleanup logic
52 * 5.6.2 10/12/04
53 * - Avoid filling tx_ring completely - shemminger@osdl.org
54 * - Replace schedule_timeout() with msleep()/msleep_interruptible() -
55 * nacc@us.ibm.com
56 * - Sparse cleanup - shemminger@osdl.org
57 * - Fix tx resource cleanup logic
58 * - LLTX support - ak@suse.de and hadi@cyberus.ca
59 */ 35 */
60 36
61char e1000_driver_name[] = "e1000"; 37char e1000_driver_name[] = "e1000";
@@ -65,7 +41,7 @@ char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
65#else 41#else
66#define DRIVERNAPI "-NAPI" 42#define DRIVERNAPI "-NAPI"
67#endif 43#endif
68#define DRV_VERSION "5.7.6-k2"DRIVERNAPI 44#define DRV_VERSION "6.0.54-k2"DRIVERNAPI
69char e1000_driver_version[] = DRV_VERSION; 45char e1000_driver_version[] = DRV_VERSION;
70char e1000_copyright[] = "Copyright (c) 1999-2004 Intel Corporation."; 46char e1000_copyright[] = "Copyright (c) 1999-2004 Intel Corporation.";
71 47
@@ -96,6 +72,7 @@ static struct pci_device_id e1000_pci_tbl[] = {
96 INTEL_E1000_ETHERNET_DEVICE(0x1017), 72 INTEL_E1000_ETHERNET_DEVICE(0x1017),
97 INTEL_E1000_ETHERNET_DEVICE(0x1018), 73 INTEL_E1000_ETHERNET_DEVICE(0x1018),
98 INTEL_E1000_ETHERNET_DEVICE(0x1019), 74 INTEL_E1000_ETHERNET_DEVICE(0x1019),
75 INTEL_E1000_ETHERNET_DEVICE(0x101A),
99 INTEL_E1000_ETHERNET_DEVICE(0x101D), 76 INTEL_E1000_ETHERNET_DEVICE(0x101D),
100 INTEL_E1000_ETHERNET_DEVICE(0x101E), 77 INTEL_E1000_ETHERNET_DEVICE(0x101E),
101 INTEL_E1000_ETHERNET_DEVICE(0x1026), 78 INTEL_E1000_ETHERNET_DEVICE(0x1026),
@@ -110,6 +87,9 @@ static struct pci_device_id e1000_pci_tbl[] = {
110 INTEL_E1000_ETHERNET_DEVICE(0x107B), 87 INTEL_E1000_ETHERNET_DEVICE(0x107B),
111 INTEL_E1000_ETHERNET_DEVICE(0x107C), 88 INTEL_E1000_ETHERNET_DEVICE(0x107C),
112 INTEL_E1000_ETHERNET_DEVICE(0x108A), 89 INTEL_E1000_ETHERNET_DEVICE(0x108A),
90 INTEL_E1000_ETHERNET_DEVICE(0x108B),
91 INTEL_E1000_ETHERNET_DEVICE(0x108C),
92 INTEL_E1000_ETHERNET_DEVICE(0x1099),
113 /* required last entry */ 93 /* required last entry */
114 {0,} 94 {0,}
115}; 95};
@@ -155,10 +135,14 @@ static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter);
155static int e1000_clean(struct net_device *netdev, int *budget); 135static int e1000_clean(struct net_device *netdev, int *budget);
156static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter, 136static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
157 int *work_done, int work_to_do); 137 int *work_done, int work_to_do);
138static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
139 int *work_done, int work_to_do);
158#else 140#else
159static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter); 141static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter);
142static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter);
160#endif 143#endif
161static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter); 144static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter);
145static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter);
162static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd); 146static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
163static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, 147static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
164 int cmd); 148 int cmd);
@@ -286,7 +270,29 @@ e1000_irq_enable(struct e1000_adapter *adapter)
286 E1000_WRITE_FLUSH(&adapter->hw); 270 E1000_WRITE_FLUSH(&adapter->hw);
287 } 271 }
288} 272}
289 273void
274e1000_update_mng_vlan(struct e1000_adapter *adapter)
275{
276 struct net_device *netdev = adapter->netdev;
277 uint16_t vid = adapter->hw.mng_cookie.vlan_id;
278 uint16_t old_vid = adapter->mng_vlan_id;
279 if(adapter->vlgrp) {
280 if(!adapter->vlgrp->vlan_devices[vid]) {
281 if(adapter->hw.mng_cookie.status &
282 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) {
283 e1000_vlan_rx_add_vid(netdev, vid);
284 adapter->mng_vlan_id = vid;
285 } else
286 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
287
288 if((old_vid != (uint16_t)E1000_MNG_VLAN_NONE) &&
289 (vid != old_vid) &&
290 !adapter->vlgrp->vlan_devices[old_vid])
291 e1000_vlan_rx_kill_vid(netdev, old_vid);
292 }
293 }
294}
295
290int 296int
291e1000_up(struct e1000_adapter *adapter) 297e1000_up(struct e1000_adapter *adapter)
292{ 298{
@@ -310,19 +316,33 @@ e1000_up(struct e1000_adapter *adapter)
310 e1000_configure_tx(adapter); 316 e1000_configure_tx(adapter);
311 e1000_setup_rctl(adapter); 317 e1000_setup_rctl(adapter);
312 e1000_configure_rx(adapter); 318 e1000_configure_rx(adapter);
313 e1000_alloc_rx_buffers(adapter); 319 adapter->alloc_rx_buf(adapter);
314 320
321#ifdef CONFIG_PCI_MSI
322 if(adapter->hw.mac_type > e1000_82547_rev_2) {
323 adapter->have_msi = TRUE;
324 if((err = pci_enable_msi(adapter->pdev))) {
325 DPRINTK(PROBE, ERR,
326 "Unable to allocate MSI interrupt Error: %d\n", err);
327 adapter->have_msi = FALSE;
328 }
329 }
330#endif
315 if((err = request_irq(adapter->pdev->irq, &e1000_intr, 331 if((err = request_irq(adapter->pdev->irq, &e1000_intr,
316 SA_SHIRQ | SA_SAMPLE_RANDOM, 332 SA_SHIRQ | SA_SAMPLE_RANDOM,
317 netdev->name, netdev))) 333 netdev->name, netdev))) {
334 DPRINTK(PROBE, ERR,
335 "Unable to allocate interrupt Error: %d\n", err);
318 return err; 336 return err;
337 }
319 338
320 mod_timer(&adapter->watchdog_timer, jiffies); 339 mod_timer(&adapter->watchdog_timer, jiffies);
321 e1000_irq_enable(adapter);
322 340
323#ifdef CONFIG_E1000_NAPI 341#ifdef CONFIG_E1000_NAPI
324 netif_poll_enable(netdev); 342 netif_poll_enable(netdev);
325#endif 343#endif
344 e1000_irq_enable(adapter);
345
326 return 0; 346 return 0;
327} 347}
328 348
@@ -333,6 +353,11 @@ e1000_down(struct e1000_adapter *adapter)
333 353
334 e1000_irq_disable(adapter); 354 e1000_irq_disable(adapter);
335 free_irq(adapter->pdev->irq, netdev); 355 free_irq(adapter->pdev->irq, netdev);
356#ifdef CONFIG_PCI_MSI
357 if(adapter->hw.mac_type > e1000_82547_rev_2 &&
358 adapter->have_msi == TRUE)
359 pci_disable_msi(adapter->pdev);
360#endif
336 del_timer_sync(&adapter->tx_fifo_stall_timer); 361 del_timer_sync(&adapter->tx_fifo_stall_timer);
337 del_timer_sync(&adapter->watchdog_timer); 362 del_timer_sync(&adapter->watchdog_timer);
338 del_timer_sync(&adapter->phy_info_timer); 363 del_timer_sync(&adapter->phy_info_timer);
@@ -350,62 +375,93 @@ e1000_down(struct e1000_adapter *adapter)
350 e1000_clean_rx_ring(adapter); 375 e1000_clean_rx_ring(adapter);
351 376
352 /* If WoL is not enabled 377 /* If WoL is not enabled
378 * and management mode is not IAMT
353 * Power down the PHY so no link is implied when interface is down */ 379 * Power down the PHY so no link is implied when interface is down */
354 if(!adapter->wol && adapter->hw.media_type == e1000_media_type_copper) { 380 if(!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
381 adapter->hw.media_type == e1000_media_type_copper &&
382 !e1000_check_mng_mode(&adapter->hw) &&
383 !(E1000_READ_REG(&adapter->hw, MANC) & E1000_MANC_SMBUS_EN)) {
355 uint16_t mii_reg; 384 uint16_t mii_reg;
356 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg); 385 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
357 mii_reg |= MII_CR_POWER_DOWN; 386 mii_reg |= MII_CR_POWER_DOWN;
358 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg); 387 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
388 mdelay(1);
359 } 389 }
360} 390}
361 391
362void 392void
363e1000_reset(struct e1000_adapter *adapter) 393e1000_reset(struct e1000_adapter *adapter)
364{ 394{
365 uint32_t pba; 395 struct net_device *netdev = adapter->netdev;
396 uint32_t pba, manc;
397 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF;
398 uint16_t fc_low_water_mark = E1000_FC_LOW_DIFF;
366 399
367 /* Repartition Pba for greater than 9k mtu 400 /* Repartition Pba for greater than 9k mtu
368 * To take effect CTRL.RST is required. 401 * To take effect CTRL.RST is required.
369 */ 402 */
370 403
371 if(adapter->hw.mac_type < e1000_82547) { 404 switch (adapter->hw.mac_type) {
372 if(adapter->rx_buffer_len > E1000_RXBUFFER_8192) 405 case e1000_82547:
373 pba = E1000_PBA_40K; 406 case e1000_82547_rev_2:
374 else 407 pba = E1000_PBA_30K;
375 pba = E1000_PBA_48K; 408 break;
376 } else { 409 case e1000_82573:
377 if(adapter->rx_buffer_len > E1000_RXBUFFER_8192) 410 pba = E1000_PBA_12K;
378 pba = E1000_PBA_22K; 411 break;
379 else 412 default:
380 pba = E1000_PBA_30K; 413 pba = E1000_PBA_48K;
414 break;
415 }
416
417 if((adapter->hw.mac_type != e1000_82573) &&
418 (adapter->rx_buffer_len > E1000_RXBUFFER_8192)) {
419 pba -= 8; /* allocate more FIFO for Tx */
420 /* send an XOFF when there is enough space in the
421 * Rx FIFO to hold one extra full size Rx packet
422 */
423 fc_high_water_mark = netdev->mtu + ENET_HEADER_SIZE +
424 ETHERNET_FCS_SIZE + 1;
425 fc_low_water_mark = fc_high_water_mark + 8;
426 }
427
428
429 if(adapter->hw.mac_type == e1000_82547) {
381 adapter->tx_fifo_head = 0; 430 adapter->tx_fifo_head = 0;
382 adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT; 431 adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT;
383 adapter->tx_fifo_size = 432 adapter->tx_fifo_size =
384 (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT; 433 (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT;
385 atomic_set(&adapter->tx_fifo_stall, 0); 434 atomic_set(&adapter->tx_fifo_stall, 0);
386 } 435 }
436
387 E1000_WRITE_REG(&adapter->hw, PBA, pba); 437 E1000_WRITE_REG(&adapter->hw, PBA, pba);
388 438
389 /* flow control settings */ 439 /* flow control settings */
390 adapter->hw.fc_high_water = (pba << E1000_PBA_BYTES_SHIFT) - 440 adapter->hw.fc_high_water = (pba << E1000_PBA_BYTES_SHIFT) -
391 E1000_FC_HIGH_DIFF; 441 fc_high_water_mark;
392 adapter->hw.fc_low_water = (pba << E1000_PBA_BYTES_SHIFT) - 442 adapter->hw.fc_low_water = (pba << E1000_PBA_BYTES_SHIFT) -
393 E1000_FC_LOW_DIFF; 443 fc_low_water_mark;
394 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME; 444 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
395 adapter->hw.fc_send_xon = 1; 445 adapter->hw.fc_send_xon = 1;
396 adapter->hw.fc = adapter->hw.original_fc; 446 adapter->hw.fc = adapter->hw.original_fc;
397 447
448 /* Allow time for pending master requests to run */
398 e1000_reset_hw(&adapter->hw); 449 e1000_reset_hw(&adapter->hw);
399 if(adapter->hw.mac_type >= e1000_82544) 450 if(adapter->hw.mac_type >= e1000_82544)
400 E1000_WRITE_REG(&adapter->hw, WUC, 0); 451 E1000_WRITE_REG(&adapter->hw, WUC, 0);
401 if(e1000_init_hw(&adapter->hw)) 452 if(e1000_init_hw(&adapter->hw))
402 DPRINTK(PROBE, ERR, "Hardware Error\n"); 453 DPRINTK(PROBE, ERR, "Hardware Error\n");
403 454 e1000_update_mng_vlan(adapter);
404 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 455 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
405 E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE); 456 E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE);
406 457
407 e1000_reset_adaptive(&adapter->hw); 458 e1000_reset_adaptive(&adapter->hw);
408 e1000_phy_get_info(&adapter->hw, &adapter->phy_info); 459 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
460 if (adapter->en_mng_pt) {
461 manc = E1000_READ_REG(&adapter->hw, MANC);
462 manc |= (E1000_MANC_ARP_EN | E1000_MANC_EN_MNG2HOST);
463 E1000_WRITE_REG(&adapter->hw, MANC, manc);
464 }
409} 465}
410 466
411/** 467/**
@@ -426,15 +482,13 @@ e1000_probe(struct pci_dev *pdev,
426{ 482{
427 struct net_device *netdev; 483 struct net_device *netdev;
428 struct e1000_adapter *adapter; 484 struct e1000_adapter *adapter;
485 unsigned long mmio_start, mmio_len;
486 uint32_t swsm;
487
429 static int cards_found = 0; 488 static int cards_found = 0;
430 unsigned long mmio_start; 489 int i, err, pci_using_dac;
431 int mmio_len;
432 int pci_using_dac;
433 int i;
434 int err;
435 uint16_t eeprom_data; 490 uint16_t eeprom_data;
436 uint16_t eeprom_apme_mask = E1000_EEPROM_APME; 491 uint16_t eeprom_apme_mask = E1000_EEPROM_APME;
437
438 if((err = pci_enable_device(pdev))) 492 if((err = pci_enable_device(pdev)))
439 return err; 493 return err;
440 494
@@ -521,6 +575,9 @@ e1000_probe(struct pci_dev *pdev,
521 if((err = e1000_sw_init(adapter))) 575 if((err = e1000_sw_init(adapter)))
522 goto err_sw_init; 576 goto err_sw_init;
523 577
578 if((err = e1000_check_phy_reset_block(&adapter->hw)))
579 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
580
524 if(adapter->hw.mac_type >= e1000_82543) { 581 if(adapter->hw.mac_type >= e1000_82543) {
525 netdev->features = NETIF_F_SG | 582 netdev->features = NETIF_F_SG |
526 NETIF_F_HW_CSUM | 583 NETIF_F_HW_CSUM |
@@ -533,6 +590,11 @@ e1000_probe(struct pci_dev *pdev,
533 if((adapter->hw.mac_type >= e1000_82544) && 590 if((adapter->hw.mac_type >= e1000_82544) &&
534 (adapter->hw.mac_type != e1000_82547)) 591 (adapter->hw.mac_type != e1000_82547))
535 netdev->features |= NETIF_F_TSO; 592 netdev->features |= NETIF_F_TSO;
593
594#ifdef NETIF_F_TSO_IPV6
595 if(adapter->hw.mac_type > e1000_82547_rev_2)
596 netdev->features |= NETIF_F_TSO_IPV6;
597#endif
536#endif 598#endif
537 if(pci_using_dac) 599 if(pci_using_dac)
538 netdev->features |= NETIF_F_HIGHDMA; 600 netdev->features |= NETIF_F_HIGHDMA;
@@ -540,6 +602,8 @@ e1000_probe(struct pci_dev *pdev,
540 /* hard_start_xmit is safe against parallel locking */ 602 /* hard_start_xmit is safe against parallel locking */
541 netdev->features |= NETIF_F_LLTX; 603 netdev->features |= NETIF_F_LLTX;
542 604
605 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw);
606
543 /* before reading the EEPROM, reset the controller to 607 /* before reading the EEPROM, reset the controller to
544 * put the device in a known good starting state */ 608 * put the device in a known good starting state */
545 609
@@ -555,7 +619,7 @@ e1000_probe(struct pci_dev *pdev,
555 619
556 /* copy the MAC address out of the EEPROM */ 620 /* copy the MAC address out of the EEPROM */
557 621
558 if (e1000_read_mac_addr(&adapter->hw)) 622 if(e1000_read_mac_addr(&adapter->hw))
559 DPRINTK(PROBE, ERR, "EEPROM Read Error\n"); 623 DPRINTK(PROBE, ERR, "EEPROM Read Error\n");
560 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len); 624 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
561 625
@@ -629,6 +693,17 @@ e1000_probe(struct pci_dev *pdev,
629 /* reset the hardware with the new settings */ 693 /* reset the hardware with the new settings */
630 e1000_reset(adapter); 694 e1000_reset(adapter);
631 695
696 /* Let firmware know the driver has taken over */
697 switch(adapter->hw.mac_type) {
698 case e1000_82573:
699 swsm = E1000_READ_REG(&adapter->hw, SWSM);
700 E1000_WRITE_REG(&adapter->hw, SWSM,
701 swsm | E1000_SWSM_DRV_LOAD);
702 break;
703 default:
704 break;
705 }
706
632 strcpy(netdev->name, "eth%d"); 707 strcpy(netdev->name, "eth%d");
633 if((err = register_netdev(netdev))) 708 if((err = register_netdev(netdev)))
634 goto err_register; 709 goto err_register;
@@ -664,7 +739,7 @@ e1000_remove(struct pci_dev *pdev)
664{ 739{
665 struct net_device *netdev = pci_get_drvdata(pdev); 740 struct net_device *netdev = pci_get_drvdata(pdev);
666 struct e1000_adapter *adapter = netdev->priv; 741 struct e1000_adapter *adapter = netdev->priv;
667 uint32_t manc; 742 uint32_t manc, swsm;
668 743
669 flush_scheduled_work(); 744 flush_scheduled_work();
670 745
@@ -677,9 +752,21 @@ e1000_remove(struct pci_dev *pdev)
677 } 752 }
678 } 753 }
679 754
755 switch(adapter->hw.mac_type) {
756 case e1000_82573:
757 swsm = E1000_READ_REG(&adapter->hw, SWSM);
758 E1000_WRITE_REG(&adapter->hw, SWSM,
759 swsm & ~E1000_SWSM_DRV_LOAD);
760 break;
761
762 default:
763 break;
764 }
765
680 unregister_netdev(netdev); 766 unregister_netdev(netdev);
681 767
682 e1000_phy_hw_reset(&adapter->hw); 768 if(!e1000_check_phy_reset_block(&adapter->hw))
769 e1000_phy_hw_reset(&adapter->hw);
683 770
684 iounmap(adapter->hw.hw_addr); 771 iounmap(adapter->hw.hw_addr);
685 pci_release_regions(pdev); 772 pci_release_regions(pdev);
@@ -717,6 +804,7 @@ e1000_sw_init(struct e1000_adapter *adapter)
717 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word); 804 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
718 805
719 adapter->rx_buffer_len = E1000_RXBUFFER_2048; 806 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
807 adapter->rx_ps_bsize0 = E1000_RXBUFFER_256;
720 hw->max_frame_size = netdev->mtu + 808 hw->max_frame_size = netdev->mtu +
721 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE; 809 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
722 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE; 810 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
@@ -730,7 +818,10 @@ e1000_sw_init(struct e1000_adapter *adapter)
730 818
731 /* initialize eeprom parameters */ 819 /* initialize eeprom parameters */
732 820
733 e1000_init_eeprom_params(hw); 821 if(e1000_init_eeprom_params(hw)) {
822 E1000_ERR("EEPROM initialization failed\n");
823 return -EIO;
824 }
734 825
735 switch(hw->mac_type) { 826 switch(hw->mac_type) {
736 default: 827 default:
@@ -795,6 +886,11 @@ e1000_open(struct net_device *netdev)
795 886
796 if((err = e1000_up(adapter))) 887 if((err = e1000_up(adapter)))
797 goto err_up; 888 goto err_up;
889 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
890 if((adapter->hw.mng_cookie.status &
891 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
892 e1000_update_mng_vlan(adapter);
893 }
798 894
799 return E1000_SUCCESS; 895 return E1000_SUCCESS;
800 896
@@ -830,14 +926,18 @@ e1000_close(struct net_device *netdev)
830 e1000_free_tx_resources(adapter); 926 e1000_free_tx_resources(adapter);
831 e1000_free_rx_resources(adapter); 927 e1000_free_rx_resources(adapter);
832 928
929 if((adapter->hw.mng_cookie.status &
930 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
931 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
932 }
833 return 0; 933 return 0;
834} 934}
835 935
836/** 936/**
837 * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary 937 * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary
838 * @adapter: address of board private structure 938 * @adapter: address of board private structure
839 * @begin: address of beginning of memory 939 * @start: address of beginning of memory
840 * @end: address of end of memory 940 * @len: length of memory
841 **/ 941 **/
842static inline boolean_t 942static inline boolean_t
843e1000_check_64k_bound(struct e1000_adapter *adapter, 943e1000_check_64k_bound(struct e1000_adapter *adapter,
@@ -846,12 +946,10 @@ e1000_check_64k_bound(struct e1000_adapter *adapter,
846 unsigned long begin = (unsigned long) start; 946 unsigned long begin = (unsigned long) start;
847 unsigned long end = begin + len; 947 unsigned long end = begin + len;
848 948
849 /* first rev 82545 and 82546 need to not allow any memory 949 /* First rev 82545 and 82546 need to not allow any memory
850 * write location to cross a 64k boundary due to errata 23 */ 950 * write location to cross 64k boundary due to errata 23 */
851 if (adapter->hw.mac_type == e1000_82545 || 951 if (adapter->hw.mac_type == e1000_82545 ||
852 adapter->hw.mac_type == e1000_82546 ) { 952 adapter->hw.mac_type == e1000_82546) {
853
854 /* check buffer doesn't cross 64kB */
855 return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE; 953 return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE;
856 } 954 }
857 955
@@ -875,8 +973,8 @@ e1000_setup_tx_resources(struct e1000_adapter *adapter)
875 size = sizeof(struct e1000_buffer) * txdr->count; 973 size = sizeof(struct e1000_buffer) * txdr->count;
876 txdr->buffer_info = vmalloc(size); 974 txdr->buffer_info = vmalloc(size);
877 if(!txdr->buffer_info) { 975 if(!txdr->buffer_info) {
878 DPRINTK(PROBE, ERR, 976 DPRINTK(PROBE, ERR,
879 "Unable to Allocate Memory for the Transmit descriptor ring\n"); 977 "Unable to allocate memory for the transmit descriptor ring\n");
880 return -ENOMEM; 978 return -ENOMEM;
881 } 979 }
882 memset(txdr->buffer_info, 0, size); 980 memset(txdr->buffer_info, 0, size);
@@ -889,38 +987,38 @@ e1000_setup_tx_resources(struct e1000_adapter *adapter)
889 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma); 987 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
890 if(!txdr->desc) { 988 if(!txdr->desc) {
891setup_tx_desc_die: 989setup_tx_desc_die:
892 DPRINTK(PROBE, ERR,
893 "Unable to Allocate Memory for the Transmit descriptor ring\n");
894 vfree(txdr->buffer_info); 990 vfree(txdr->buffer_info);
991 DPRINTK(PROBE, ERR,
992 "Unable to allocate memory for the transmit descriptor ring\n");
895 return -ENOMEM; 993 return -ENOMEM;
896 } 994 }
897 995
898 /* fix for errata 23, cant cross 64kB boundary */ 996 /* Fix for errata 23, can't cross 64kB boundary */
899 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) { 997 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
900 void *olddesc = txdr->desc; 998 void *olddesc = txdr->desc;
901 dma_addr_t olddma = txdr->dma; 999 dma_addr_t olddma = txdr->dma;
902 DPRINTK(TX_ERR,ERR,"txdr align check failed: %u bytes at %p\n", 1000 DPRINTK(TX_ERR, ERR, "txdr align check failed: %u bytes "
903 txdr->size, txdr->desc); 1001 "at %p\n", txdr->size, txdr->desc);
904 /* try again, without freeing the previous */ 1002 /* Try again, without freeing the previous */
905 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma); 1003 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
906 /* failed allocation, critial failure */
907 if(!txdr->desc) { 1004 if(!txdr->desc) {
1005 /* Failed allocation, critical failure */
908 pci_free_consistent(pdev, txdr->size, olddesc, olddma); 1006 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
909 goto setup_tx_desc_die; 1007 goto setup_tx_desc_die;
910 } 1008 }
911 1009
912 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) { 1010 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
913 /* give up */ 1011 /* give up */
914 pci_free_consistent(pdev, txdr->size, 1012 pci_free_consistent(pdev, txdr->size, txdr->desc,
915 txdr->desc, txdr->dma); 1013 txdr->dma);
916 pci_free_consistent(pdev, txdr->size, olddesc, olddma); 1014 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
917 DPRINTK(PROBE, ERR, 1015 DPRINTK(PROBE, ERR,
918 "Unable to Allocate aligned Memory for the Transmit" 1016 "Unable to allocate aligned memory "
919 " descriptor ring\n"); 1017 "for the transmit descriptor ring\n");
920 vfree(txdr->buffer_info); 1018 vfree(txdr->buffer_info);
921 return -ENOMEM; 1019 return -ENOMEM;
922 } else { 1020 } else {
923 /* free old, move on with the new one since its okay */ 1021 /* Free old allocation, new allocation was successful */
924 pci_free_consistent(pdev, txdr->size, olddesc, olddma); 1022 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
925 } 1023 }
926 } 1024 }
@@ -1022,59 +1120,88 @@ e1000_setup_rx_resources(struct e1000_adapter *adapter)
1022{ 1120{
1023 struct e1000_desc_ring *rxdr = &adapter->rx_ring; 1121 struct e1000_desc_ring *rxdr = &adapter->rx_ring;
1024 struct pci_dev *pdev = adapter->pdev; 1122 struct pci_dev *pdev = adapter->pdev;
1025 int size; 1123 int size, desc_len;
1026 1124
1027 size = sizeof(struct e1000_buffer) * rxdr->count; 1125 size = sizeof(struct e1000_buffer) * rxdr->count;
1028 rxdr->buffer_info = vmalloc(size); 1126 rxdr->buffer_info = vmalloc(size);
1029 if(!rxdr->buffer_info) { 1127 if(!rxdr->buffer_info) {
1030 DPRINTK(PROBE, ERR, 1128 DPRINTK(PROBE, ERR,
1031 "Unable to Allocate Memory for the Recieve descriptor ring\n"); 1129 "Unable to allocate memory for the receive descriptor ring\n");
1032 return -ENOMEM; 1130 return -ENOMEM;
1033 } 1131 }
1034 memset(rxdr->buffer_info, 0, size); 1132 memset(rxdr->buffer_info, 0, size);
1035 1133
1134 size = sizeof(struct e1000_ps_page) * rxdr->count;
1135 rxdr->ps_page = kmalloc(size, GFP_KERNEL);
1136 if(!rxdr->ps_page) {
1137 vfree(rxdr->buffer_info);
1138 DPRINTK(PROBE, ERR,
1139 "Unable to allocate memory for the receive descriptor ring\n");
1140 return -ENOMEM;
1141 }
1142 memset(rxdr->ps_page, 0, size);
1143
1144 size = sizeof(struct e1000_ps_page_dma) * rxdr->count;
1145 rxdr->ps_page_dma = kmalloc(size, GFP_KERNEL);
1146 if(!rxdr->ps_page_dma) {
1147 vfree(rxdr->buffer_info);
1148 kfree(rxdr->ps_page);
1149 DPRINTK(PROBE, ERR,
1150 "Unable to allocate memory for the receive descriptor ring\n");
1151 return -ENOMEM;
1152 }
1153 memset(rxdr->ps_page_dma, 0, size);
1154
1155 if(adapter->hw.mac_type <= e1000_82547_rev_2)
1156 desc_len = sizeof(struct e1000_rx_desc);
1157 else
1158 desc_len = sizeof(union e1000_rx_desc_packet_split);
1159
1036 /* Round up to nearest 4K */ 1160 /* Round up to nearest 4K */
1037 1161
1038 rxdr->size = rxdr->count * sizeof(struct e1000_rx_desc); 1162 rxdr->size = rxdr->count * desc_len;
1039 E1000_ROUNDUP(rxdr->size, 4096); 1163 E1000_ROUNDUP(rxdr->size, 4096);
1040 1164
1041 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma); 1165 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
1042 1166
1043 if(!rxdr->desc) { 1167 if(!rxdr->desc) {
1044setup_rx_desc_die: 1168setup_rx_desc_die:
1045 DPRINTK(PROBE, ERR,
1046 "Unble to Allocate Memory for the Recieve descriptor ring\n");
1047 vfree(rxdr->buffer_info); 1169 vfree(rxdr->buffer_info);
1170 kfree(rxdr->ps_page);
1171 kfree(rxdr->ps_page_dma);
1172 DPRINTK(PROBE, ERR,
1173 "Unable to allocate memory for the receive descriptor ring\n");
1048 return -ENOMEM; 1174 return -ENOMEM;
1049 } 1175 }
1050 1176
1051 /* fix for errata 23, cant cross 64kB boundary */ 1177 /* Fix for errata 23, can't cross 64kB boundary */
1052 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) { 1178 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1053 void *olddesc = rxdr->desc; 1179 void *olddesc = rxdr->desc;
1054 dma_addr_t olddma = rxdr->dma; 1180 dma_addr_t olddma = rxdr->dma;
1055 DPRINTK(RX_ERR,ERR, 1181 DPRINTK(RX_ERR, ERR, "rxdr align check failed: %u bytes "
1056 "rxdr align check failed: %u bytes at %p\n", 1182 "at %p\n", rxdr->size, rxdr->desc);
1057 rxdr->size, rxdr->desc); 1183 /* Try again, without freeing the previous */
1058 /* try again, without freeing the previous */
1059 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma); 1184 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
1060 /* failed allocation, critial failure */
1061 if(!rxdr->desc) { 1185 if(!rxdr->desc) {
1186 /* Failed allocation, critical failure */
1062 pci_free_consistent(pdev, rxdr->size, olddesc, olddma); 1187 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
1063 goto setup_rx_desc_die; 1188 goto setup_rx_desc_die;
1064 } 1189 }
1065 1190
1066 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) { 1191 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1067 /* give up */ 1192 /* give up */
1068 pci_free_consistent(pdev, rxdr->size, 1193 pci_free_consistent(pdev, rxdr->size, rxdr->desc,
1069 rxdr->desc, rxdr->dma); 1194 rxdr->dma);
1070 pci_free_consistent(pdev, rxdr->size, olddesc, olddma); 1195 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
1071 DPRINTK(PROBE, ERR, 1196 DPRINTK(PROBE, ERR,
1072 "Unable to Allocate aligned Memory for the" 1197 "Unable to allocate aligned memory "
1073 " Receive descriptor ring\n"); 1198 "for the receive descriptor ring\n");
1074 vfree(rxdr->buffer_info); 1199 vfree(rxdr->buffer_info);
1200 kfree(rxdr->ps_page);
1201 kfree(rxdr->ps_page_dma);
1075 return -ENOMEM; 1202 return -ENOMEM;
1076 } else { 1203 } else {
1077 /* free old, move on with the new one since its okay */ 1204 /* Free old allocation, new allocation was successful */
1078 pci_free_consistent(pdev, rxdr->size, olddesc, olddma); 1205 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
1079 } 1206 }
1080 } 1207 }
@@ -1087,14 +1214,15 @@ setup_rx_desc_die:
1087} 1214}
1088 1215
1089/** 1216/**
1090 * e1000_setup_rctl - configure the receive control register 1217 * e1000_setup_rctl - configure the receive control registers
1091 * @adapter: Board private structure 1218 * @adapter: Board private structure
1092 **/ 1219 **/
1093 1220
1094static void 1221static void
1095e1000_setup_rctl(struct e1000_adapter *adapter) 1222e1000_setup_rctl(struct e1000_adapter *adapter)
1096{ 1223{
1097 uint32_t rctl; 1224 uint32_t rctl, rfctl;
1225 uint32_t psrctl = 0;
1098 1226
1099 rctl = E1000_READ_REG(&adapter->hw, RCTL); 1227 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1100 1228
@@ -1109,24 +1237,69 @@ e1000_setup_rctl(struct e1000_adapter *adapter)
1109 else 1237 else
1110 rctl &= ~E1000_RCTL_SBP; 1238 rctl &= ~E1000_RCTL_SBP;
1111 1239
1240 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1241 rctl &= ~E1000_RCTL_LPE;
1242 else
1243 rctl |= E1000_RCTL_LPE;
1244
1112 /* Setup buffer sizes */ 1245 /* Setup buffer sizes */
1113 rctl &= ~(E1000_RCTL_SZ_4096); 1246 if(adapter->hw.mac_type == e1000_82573) {
1114 rctl |= (E1000_RCTL_BSEX | E1000_RCTL_LPE); 1247 /* We can now specify buffers in 1K increments.
1115 switch (adapter->rx_buffer_len) { 1248 * BSIZE and BSEX are ignored in this case. */
1116 case E1000_RXBUFFER_2048: 1249 rctl |= adapter->rx_buffer_len << 0x11;
1117 default: 1250 } else {
1118 rctl |= E1000_RCTL_SZ_2048; 1251 rctl &= ~E1000_RCTL_SZ_4096;
1119 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE); 1252 rctl |= E1000_RCTL_BSEX;
1120 break; 1253 switch (adapter->rx_buffer_len) {
1121 case E1000_RXBUFFER_4096: 1254 case E1000_RXBUFFER_2048:
1122 rctl |= E1000_RCTL_SZ_4096; 1255 default:
1123 break; 1256 rctl |= E1000_RCTL_SZ_2048;
1124 case E1000_RXBUFFER_8192: 1257 rctl &= ~E1000_RCTL_BSEX;
1125 rctl |= E1000_RCTL_SZ_8192; 1258 break;
1126 break; 1259 case E1000_RXBUFFER_4096:
1127 case E1000_RXBUFFER_16384: 1260 rctl |= E1000_RCTL_SZ_4096;
1128 rctl |= E1000_RCTL_SZ_16384; 1261 break;
1129 break; 1262 case E1000_RXBUFFER_8192:
1263 rctl |= E1000_RCTL_SZ_8192;
1264 break;
1265 case E1000_RXBUFFER_16384:
1266 rctl |= E1000_RCTL_SZ_16384;
1267 break;
1268 }
1269 }
1270
1271#ifdef CONFIG_E1000_PACKET_SPLIT
1272 /* 82571 and greater support packet-split where the protocol
1273 * header is placed in skb->data and the packet data is
1274 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1275 * In the case of a non-split, skb->data is linearly filled,
1276 * followed by the page buffers. Therefore, skb->data is
1277 * sized to hold the largest protocol header.
1278 */
1279 adapter->rx_ps = (adapter->hw.mac_type > e1000_82547_rev_2)
1280 && (adapter->netdev->mtu
1281 < ((3 * PAGE_SIZE) + adapter->rx_ps_bsize0));
1282#endif
1283 if(adapter->rx_ps) {
1284 /* Configure extra packet-split registers */
1285 rfctl = E1000_READ_REG(&adapter->hw, RFCTL);
1286 rfctl |= E1000_RFCTL_EXTEN;
1287 /* disable IPv6 packet split support */
1288 rfctl |= E1000_RFCTL_IPV6_DIS;
1289 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl);
1290
1291 rctl |= E1000_RCTL_DTYP_PS | E1000_RCTL_SECRC;
1292
1293 psrctl |= adapter->rx_ps_bsize0 >>
1294 E1000_PSRCTL_BSIZE0_SHIFT;
1295 psrctl |= PAGE_SIZE >>
1296 E1000_PSRCTL_BSIZE1_SHIFT;
1297 psrctl |= PAGE_SIZE <<
1298 E1000_PSRCTL_BSIZE2_SHIFT;
1299 psrctl |= PAGE_SIZE <<
1300 E1000_PSRCTL_BSIZE3_SHIFT;
1301
1302 E1000_WRITE_REG(&adapter->hw, PSRCTL, psrctl);
1130 } 1303 }
1131 1304
1132 E1000_WRITE_REG(&adapter->hw, RCTL, rctl); 1305 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
@@ -1143,9 +1316,18 @@ static void
1143e1000_configure_rx(struct e1000_adapter *adapter) 1316e1000_configure_rx(struct e1000_adapter *adapter)
1144{ 1317{
1145 uint64_t rdba = adapter->rx_ring.dma; 1318 uint64_t rdba = adapter->rx_ring.dma;
1146 uint32_t rdlen = adapter->rx_ring.count * sizeof(struct e1000_rx_desc); 1319 uint32_t rdlen, rctl, rxcsum;
1147 uint32_t rctl; 1320
1148 uint32_t rxcsum; 1321 if(adapter->rx_ps) {
1322 rdlen = adapter->rx_ring.count *
1323 sizeof(union e1000_rx_desc_packet_split);
1324 adapter->clean_rx = e1000_clean_rx_irq_ps;
1325 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
1326 } else {
1327 rdlen = adapter->rx_ring.count * sizeof(struct e1000_rx_desc);
1328 adapter->clean_rx = e1000_clean_rx_irq;
1329 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
1330 }
1149 1331
1150 /* disable receives while setting up the descriptors */ 1332 /* disable receives while setting up the descriptors */
1151 rctl = E1000_READ_REG(&adapter->hw, RCTL); 1333 rctl = E1000_READ_REG(&adapter->hw, RCTL);
@@ -1172,13 +1354,27 @@ e1000_configure_rx(struct e1000_adapter *adapter)
1172 E1000_WRITE_REG(&adapter->hw, RDT, 0); 1354 E1000_WRITE_REG(&adapter->hw, RDT, 0);
1173 1355
1174 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 1356 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
1175 if((adapter->hw.mac_type >= e1000_82543) && 1357 if(adapter->hw.mac_type >= e1000_82543) {
1176 (adapter->rx_csum == TRUE)) {
1177 rxcsum = E1000_READ_REG(&adapter->hw, RXCSUM); 1358 rxcsum = E1000_READ_REG(&adapter->hw, RXCSUM);
1178 rxcsum |= E1000_RXCSUM_TUOFL; 1359 if(adapter->rx_csum == TRUE) {
1360 rxcsum |= E1000_RXCSUM_TUOFL;
1361
1362 /* Enable 82573 IPv4 payload checksum for UDP fragments
1363 * Must be used in conjunction with packet-split. */
1364 if((adapter->hw.mac_type > e1000_82547_rev_2) &&
1365 (adapter->rx_ps)) {
1366 rxcsum |= E1000_RXCSUM_IPPCSE;
1367 }
1368 } else {
1369 rxcsum &= ~E1000_RXCSUM_TUOFL;
1370 /* don't need to clear IPPCSE as it defaults to 0 */
1371 }
1179 E1000_WRITE_REG(&adapter->hw, RXCSUM, rxcsum); 1372 E1000_WRITE_REG(&adapter->hw, RXCSUM, rxcsum);
1180 } 1373 }
1181 1374
1375 if (adapter->hw.mac_type == e1000_82573)
1376 E1000_WRITE_REG(&adapter->hw, ERT, 0x0100);
1377
1182 /* Enable Receives */ 1378 /* Enable Receives */
1183 E1000_WRITE_REG(&adapter->hw, RCTL, rctl); 1379 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1184} 1380}
@@ -1210,13 +1406,11 @@ static inline void
1210e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter, 1406e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter,
1211 struct e1000_buffer *buffer_info) 1407 struct e1000_buffer *buffer_info)
1212{ 1408{
1213 struct pci_dev *pdev = adapter->pdev;
1214
1215 if(buffer_info->dma) { 1409 if(buffer_info->dma) {
1216 pci_unmap_page(pdev, 1410 pci_unmap_page(adapter->pdev,
1217 buffer_info->dma, 1411 buffer_info->dma,
1218 buffer_info->length, 1412 buffer_info->length,
1219 PCI_DMA_TODEVICE); 1413 PCI_DMA_TODEVICE);
1220 buffer_info->dma = 0; 1414 buffer_info->dma = 0;
1221 } 1415 }
1222 if(buffer_info->skb) { 1416 if(buffer_info->skb) {
@@ -1241,7 +1435,7 @@ e1000_clean_tx_ring(struct e1000_adapter *adapter)
1241 /* Free all the Tx ring sk_buffs */ 1435 /* Free all the Tx ring sk_buffs */
1242 1436
1243 if (likely(adapter->previous_buffer_info.skb != NULL)) { 1437 if (likely(adapter->previous_buffer_info.skb != NULL)) {
1244 e1000_unmap_and_free_tx_resource(adapter, 1438 e1000_unmap_and_free_tx_resource(adapter,
1245 &adapter->previous_buffer_info); 1439 &adapter->previous_buffer_info);
1246 } 1440 }
1247 1441
@@ -1281,6 +1475,10 @@ e1000_free_rx_resources(struct e1000_adapter *adapter)
1281 1475
1282 vfree(rx_ring->buffer_info); 1476 vfree(rx_ring->buffer_info);
1283 rx_ring->buffer_info = NULL; 1477 rx_ring->buffer_info = NULL;
1478 kfree(rx_ring->ps_page);
1479 rx_ring->ps_page = NULL;
1480 kfree(rx_ring->ps_page_dma);
1481 rx_ring->ps_page_dma = NULL;
1284 1482
1285 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); 1483 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1286 1484
@@ -1297,16 +1495,19 @@ e1000_clean_rx_ring(struct e1000_adapter *adapter)
1297{ 1495{
1298 struct e1000_desc_ring *rx_ring = &adapter->rx_ring; 1496 struct e1000_desc_ring *rx_ring = &adapter->rx_ring;
1299 struct e1000_buffer *buffer_info; 1497 struct e1000_buffer *buffer_info;
1498 struct e1000_ps_page *ps_page;
1499 struct e1000_ps_page_dma *ps_page_dma;
1300 struct pci_dev *pdev = adapter->pdev; 1500 struct pci_dev *pdev = adapter->pdev;
1301 unsigned long size; 1501 unsigned long size;
1302 unsigned int i; 1502 unsigned int i, j;
1303 1503
1304 /* Free all the Rx ring sk_buffs */ 1504 /* Free all the Rx ring sk_buffs */
1305 1505
1306 for(i = 0; i < rx_ring->count; i++) { 1506 for(i = 0; i < rx_ring->count; i++) {
1307 buffer_info = &rx_ring->buffer_info[i]; 1507 buffer_info = &rx_ring->buffer_info[i];
1308 if(buffer_info->skb) { 1508 if(buffer_info->skb) {
1309 1509 ps_page = &rx_ring->ps_page[i];
1510 ps_page_dma = &rx_ring->ps_page_dma[i];
1310 pci_unmap_single(pdev, 1511 pci_unmap_single(pdev,
1311 buffer_info->dma, 1512 buffer_info->dma,
1312 buffer_info->length, 1513 buffer_info->length,
@@ -1314,11 +1515,25 @@ e1000_clean_rx_ring(struct e1000_adapter *adapter)
1314 1515
1315 dev_kfree_skb(buffer_info->skb); 1516 dev_kfree_skb(buffer_info->skb);
1316 buffer_info->skb = NULL; 1517 buffer_info->skb = NULL;
1518
1519 for(j = 0; j < PS_PAGE_BUFFERS; j++) {
1520 if(!ps_page->ps_page[j]) break;
1521 pci_unmap_single(pdev,
1522 ps_page_dma->ps_page_dma[j],
1523 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1524 ps_page_dma->ps_page_dma[j] = 0;
1525 put_page(ps_page->ps_page[j]);
1526 ps_page->ps_page[j] = NULL;
1527 }
1317 } 1528 }
1318 } 1529 }
1319 1530
1320 size = sizeof(struct e1000_buffer) * rx_ring->count; 1531 size = sizeof(struct e1000_buffer) * rx_ring->count;
1321 memset(rx_ring->buffer_info, 0, size); 1532 memset(rx_ring->buffer_info, 0, size);
1533 size = sizeof(struct e1000_ps_page) * rx_ring->count;
1534 memset(rx_ring->ps_page, 0, size);
1535 size = sizeof(struct e1000_ps_page_dma) * rx_ring->count;
1536 memset(rx_ring->ps_page_dma, 0, size);
1322 1537
1323 /* Zero out the descriptor ring */ 1538 /* Zero out the descriptor ring */
1324 1539
@@ -1422,15 +1637,15 @@ e1000_set_multi(struct net_device *netdev)
1422 struct e1000_adapter *adapter = netdev->priv; 1637 struct e1000_adapter *adapter = netdev->priv;
1423 struct e1000_hw *hw = &adapter->hw; 1638 struct e1000_hw *hw = &adapter->hw;
1424 struct dev_mc_list *mc_ptr; 1639 struct dev_mc_list *mc_ptr;
1640 unsigned long flags;
1425 uint32_t rctl; 1641 uint32_t rctl;
1426 uint32_t hash_value; 1642 uint32_t hash_value;
1427 int i; 1643 int i;
1428 unsigned long flags;
1429
1430 /* Check for Promiscuous and All Multicast modes */
1431 1644
1432 spin_lock_irqsave(&adapter->tx_lock, flags); 1645 spin_lock_irqsave(&adapter->tx_lock, flags);
1433 1646
1647 /* Check for Promiscuous and All Multicast modes */
1648
1434 rctl = E1000_READ_REG(hw, RCTL); 1649 rctl = E1000_READ_REG(hw, RCTL);
1435 1650
1436 if(netdev->flags & IFF_PROMISC) { 1651 if(netdev->flags & IFF_PROMISC) {
@@ -1556,6 +1771,11 @@ e1000_watchdog_task(struct e1000_adapter *adapter)
1556 uint32_t link; 1771 uint32_t link;
1557 1772
1558 e1000_check_for_link(&adapter->hw); 1773 e1000_check_for_link(&adapter->hw);
1774 if (adapter->hw.mac_type == e1000_82573) {
1775 e1000_enable_tx_pkt_filtering(&adapter->hw);
1776 if(adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
1777 e1000_update_mng_vlan(adapter);
1778 }
1559 1779
1560 if((adapter->hw.media_type == e1000_media_type_internal_serdes) && 1780 if((adapter->hw.media_type == e1000_media_type_internal_serdes) &&
1561 !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE)) 1781 !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE))
@@ -1632,7 +1852,7 @@ e1000_watchdog_task(struct e1000_adapter *adapter)
1632 /* Cause software interrupt to ensure rx ring is cleaned */ 1852 /* Cause software interrupt to ensure rx ring is cleaned */
1633 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0); 1853 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
1634 1854
1635 /* Force detection of hung controller every watchdog period*/ 1855 /* Force detection of hung controller every watchdog period */
1636 adapter->detect_tx_hung = TRUE; 1856 adapter->detect_tx_hung = TRUE;
1637 1857
1638 /* Reset the timer */ 1858 /* Reset the timer */
@@ -1642,6 +1862,7 @@ e1000_watchdog_task(struct e1000_adapter *adapter)
1642#define E1000_TX_FLAGS_CSUM 0x00000001 1862#define E1000_TX_FLAGS_CSUM 0x00000001
1643#define E1000_TX_FLAGS_VLAN 0x00000002 1863#define E1000_TX_FLAGS_VLAN 0x00000002
1644#define E1000_TX_FLAGS_TSO 0x00000004 1864#define E1000_TX_FLAGS_TSO 0x00000004
1865#define E1000_TX_FLAGS_IPV4 0x00000008
1645#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000 1866#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
1646#define E1000_TX_FLAGS_VLAN_SHIFT 16 1867#define E1000_TX_FLAGS_VLAN_SHIFT 16
1647 1868
@@ -1652,7 +1873,7 @@ e1000_tso(struct e1000_adapter *adapter, struct sk_buff *skb)
1652 struct e1000_context_desc *context_desc; 1873 struct e1000_context_desc *context_desc;
1653 unsigned int i; 1874 unsigned int i;
1654 uint32_t cmd_length = 0; 1875 uint32_t cmd_length = 0;
1655 uint16_t ipcse, tucse, mss; 1876 uint16_t ipcse = 0, tucse, mss;
1656 uint8_t ipcss, ipcso, tucss, tucso, hdr_len; 1877 uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
1657 int err; 1878 int err;
1658 1879
@@ -1665,23 +1886,37 @@ e1000_tso(struct e1000_adapter *adapter, struct sk_buff *skb)
1665 1886
1666 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2)); 1887 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
1667 mss = skb_shinfo(skb)->tso_size; 1888 mss = skb_shinfo(skb)->tso_size;
1668 skb->nh.iph->tot_len = 0; 1889 if(skb->protocol == ntohs(ETH_P_IP)) {
1669 skb->nh.iph->check = 0; 1890 skb->nh.iph->tot_len = 0;
1670 skb->h.th->check = ~csum_tcpudp_magic(skb->nh.iph->saddr, 1891 skb->nh.iph->check = 0;
1671 skb->nh.iph->daddr, 1892 skb->h.th->check =
1672 0, 1893 ~csum_tcpudp_magic(skb->nh.iph->saddr,
1673 IPPROTO_TCP, 1894 skb->nh.iph->daddr,
1674 0); 1895 0,
1896 IPPROTO_TCP,
1897 0);
1898 cmd_length = E1000_TXD_CMD_IP;
1899 ipcse = skb->h.raw - skb->data - 1;
1900#ifdef NETIF_F_TSO_IPV6
1901 } else if(skb->protocol == ntohs(ETH_P_IPV6)) {
1902 skb->nh.ipv6h->payload_len = 0;
1903 skb->h.th->check =
1904 ~csum_ipv6_magic(&skb->nh.ipv6h->saddr,
1905 &skb->nh.ipv6h->daddr,
1906 0,
1907 IPPROTO_TCP,
1908 0);
1909 ipcse = 0;
1910#endif
1911 }
1675 ipcss = skb->nh.raw - skb->data; 1912 ipcss = skb->nh.raw - skb->data;
1676 ipcso = (void *)&(skb->nh.iph->check) - (void *)skb->data; 1913 ipcso = (void *)&(skb->nh.iph->check) - (void *)skb->data;
1677 ipcse = skb->h.raw - skb->data - 1;
1678 tucss = skb->h.raw - skb->data; 1914 tucss = skb->h.raw - skb->data;
1679 tucso = (void *)&(skb->h.th->check) - (void *)skb->data; 1915 tucso = (void *)&(skb->h.th->check) - (void *)skb->data;
1680 tucse = 0; 1916 tucse = 0;
1681 1917
1682 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE | 1918 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
1683 E1000_TXD_CMD_IP | E1000_TXD_CMD_TCP | 1919 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
1684 (skb->len - (hdr_len)));
1685 1920
1686 i = adapter->tx_ring.next_to_use; 1921 i = adapter->tx_ring.next_to_use;
1687 context_desc = E1000_CONTEXT_DESC(adapter->tx_ring, i); 1922 context_desc = E1000_CONTEXT_DESC(adapter->tx_ring, i);
@@ -1760,6 +1995,15 @@ e1000_tx_map(struct e1000_adapter *adapter, struct sk_buff *skb,
1760 if(unlikely(mss && !nr_frags && size == len && size > 8)) 1995 if(unlikely(mss && !nr_frags && size == len && size > 8))
1761 size -= 4; 1996 size -= 4;
1762#endif 1997#endif
1998 /* work-around for errata 10 and it applies
1999 * to all controllers in PCI-X mode
2000 * The fix is to make sure that the first descriptor of a
2001 * packet is smaller than 2048 - 16 - 16 (or 2016) bytes
2002 */
2003 if(unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
2004 (size > 2015) && count == 0))
2005 size = 2015;
2006
1763 /* Workaround for potential 82544 hang in PCI-X. Avoid 2007 /* Workaround for potential 82544 hang in PCI-X. Avoid
1764 * terminating buffers within evenly-aligned dwords. */ 2008 * terminating buffers within evenly-aligned dwords. */
1765 if(unlikely(adapter->pcix_82544 && 2009 if(unlikely(adapter->pcix_82544 &&
@@ -1840,7 +2084,10 @@ e1000_tx_queue(struct e1000_adapter *adapter, int count, int tx_flags)
1840 if(likely(tx_flags & E1000_TX_FLAGS_TSO)) { 2084 if(likely(tx_flags & E1000_TX_FLAGS_TSO)) {
1841 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D | 2085 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
1842 E1000_TXD_CMD_TSE; 2086 E1000_TXD_CMD_TSE;
1843 txd_upper |= (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8; 2087 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2088
2089 if(likely(tx_flags & E1000_TX_FLAGS_IPV4))
2090 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
1844 } 2091 }
1845 2092
1846 if(likely(tx_flags & E1000_TX_FLAGS_CSUM)) { 2093 if(likely(tx_flags & E1000_TX_FLAGS_CSUM)) {
@@ -1915,6 +2162,53 @@ no_fifo_stall_required:
1915 return 0; 2162 return 0;
1916} 2163}
1917 2164
2165#define MINIMUM_DHCP_PACKET_SIZE 282
2166static inline int
2167e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb)
2168{
2169 struct e1000_hw *hw = &adapter->hw;
2170 uint16_t length, offset;
2171 if(vlan_tx_tag_present(skb)) {
2172 if(!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
2173 ( adapter->hw.mng_cookie.status &
2174 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) )
2175 return 0;
2176 }
2177 if(htons(ETH_P_IP) == skb->protocol) {
2178 const struct iphdr *ip = skb->nh.iph;
2179 if(IPPROTO_UDP == ip->protocol) {
2180 struct udphdr *udp = (struct udphdr *)(skb->h.uh);
2181 if(ntohs(udp->dest) == 67) {
2182 offset = (uint8_t *)udp + 8 - skb->data;
2183 length = skb->len - offset;
2184
2185 return e1000_mng_write_dhcp_info(hw,
2186 (uint8_t *)udp + 8, length);
2187 }
2188 }
2189 } else if((skb->len > MINIMUM_DHCP_PACKET_SIZE) && (!skb->protocol)) {
2190 struct ethhdr *eth = (struct ethhdr *) skb->data;
2191 if((htons(ETH_P_IP) == eth->h_proto)) {
2192 const struct iphdr *ip =
2193 (struct iphdr *)((uint8_t *)skb->data+14);
2194 if(IPPROTO_UDP == ip->protocol) {
2195 struct udphdr *udp =
2196 (struct udphdr *)((uint8_t *)ip +
2197 (ip->ihl << 2));
2198 if(ntohs(udp->dest) == 67) {
2199 offset = (uint8_t *)udp + 8 - skb->data;
2200 length = skb->len - offset;
2201
2202 return e1000_mng_write_dhcp_info(hw,
2203 (uint8_t *)udp + 8,
2204 length);
2205 }
2206 }
2207 }
2208 }
2209 return 0;
2210}
2211
1918#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 ) 2212#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
1919static int 2213static int
1920e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev) 2214e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
@@ -1939,7 +2233,7 @@ e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1939 2233
1940#ifdef NETIF_F_TSO 2234#ifdef NETIF_F_TSO
1941 mss = skb_shinfo(skb)->tso_size; 2235 mss = skb_shinfo(skb)->tso_size;
1942 /* The controller does a simple calculation to 2236 /* The controller does a simple calculation to
1943 * make sure there is enough room in the FIFO before 2237 * make sure there is enough room in the FIFO before
1944 * initiating the DMA for each buffer. The calc is: 2238 * initiating the DMA for each buffer. The calc is:
1945 * 4 = ceil(buffer len/mss). To make sure we don't 2239 * 4 = ceil(buffer len/mss). To make sure we don't
@@ -1952,7 +2246,7 @@ e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1952 2246
1953 if((mss) || (skb->ip_summed == CHECKSUM_HW)) 2247 if((mss) || (skb->ip_summed == CHECKSUM_HW))
1954 count++; 2248 count++;
1955 count++; /* for sentinel desc */ 2249 count++;
1956#else 2250#else
1957 if(skb->ip_summed == CHECKSUM_HW) 2251 if(skb->ip_summed == CHECKSUM_HW)
1958 count++; 2252 count++;
@@ -1962,6 +2256,13 @@ e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1962 if(adapter->pcix_82544) 2256 if(adapter->pcix_82544)
1963 count++; 2257 count++;
1964 2258
2259 /* work-around for errata 10 and it applies to all controllers
2260 * in PCI-X mode, so add one more descriptor to the count
2261 */
2262 if(unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
2263 (len > 2015)))
2264 count++;
2265
1965 nr_frags = skb_shinfo(skb)->nr_frags; 2266 nr_frags = skb_shinfo(skb)->nr_frags;
1966 for(f = 0; f < nr_frags; f++) 2267 for(f = 0; f < nr_frags; f++)
1967 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size, 2268 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
@@ -1975,6 +2276,9 @@ e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1975 local_irq_restore(flags); 2276 local_irq_restore(flags);
1976 return NETDEV_TX_LOCKED; 2277 return NETDEV_TX_LOCKED;
1977 } 2278 }
2279 if(adapter->hw.tx_pkt_filtering && (adapter->hw.mac_type == e1000_82573) )
2280 e1000_transfer_dhcp_info(adapter, skb);
2281
1978 2282
1979 /* need: count + 2 desc gap to keep tail from touching 2283 /* need: count + 2 desc gap to keep tail from touching
1980 * head, otherwise try next time */ 2284 * head, otherwise try next time */
@@ -2003,6 +2307,7 @@ e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2003 tso = e1000_tso(adapter, skb); 2307 tso = e1000_tso(adapter, skb);
2004 if (tso < 0) { 2308 if (tso < 0) {
2005 dev_kfree_skb_any(skb); 2309 dev_kfree_skb_any(skb);
2310 spin_unlock_irqrestore(&adapter->tx_lock, flags);
2006 return NETDEV_TX_OK; 2311 return NETDEV_TX_OK;
2007 } 2312 }
2008 2313
@@ -2011,6 +2316,12 @@ e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2011 else if(likely(e1000_tx_csum(adapter, skb))) 2316 else if(likely(e1000_tx_csum(adapter, skb)))
2012 tx_flags |= E1000_TX_FLAGS_CSUM; 2317 tx_flags |= E1000_TX_FLAGS_CSUM;
2013 2318
2319 /* Old method was to assume IPv4 packet by default if TSO was enabled.
2320 * 82573 hardware supports TSO capabilities for IPv6 as well...
2321 * no longer assume, we must. */
2322 if(likely(skb->protocol == ntohs(ETH_P_IP)))
2323 tx_flags |= E1000_TX_FLAGS_IPV4;
2324
2014 e1000_tx_queue(adapter, 2325 e1000_tx_queue(adapter,
2015 e1000_tx_map(adapter, skb, first, max_per_txd, nr_frags, mss), 2326 e1000_tx_map(adapter, skb, first, max_per_txd, nr_frags, mss),
2016 tx_flags); 2327 tx_flags);
@@ -2077,7 +2388,6 @@ static int
2077e1000_change_mtu(struct net_device *netdev, int new_mtu) 2388e1000_change_mtu(struct net_device *netdev, int new_mtu)
2078{ 2389{
2079 struct e1000_adapter *adapter = netdev->priv; 2390 struct e1000_adapter *adapter = netdev->priv;
2080 int old_mtu = adapter->rx_buffer_len;
2081 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE; 2391 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
2082 2392
2083 if((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) || 2393 if((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
@@ -2086,29 +2396,45 @@ e1000_change_mtu(struct net_device *netdev, int new_mtu)
2086 return -EINVAL; 2396 return -EINVAL;
2087 } 2397 }
2088 2398
2089 if(max_frame <= MAXIMUM_ETHERNET_FRAME_SIZE) { 2399#define MAX_STD_JUMBO_FRAME_SIZE 9216
2090 adapter->rx_buffer_len = E1000_RXBUFFER_2048; 2400 /* might want this to be bigger enum check... */
2091 2401 if (adapter->hw.mac_type == e1000_82573 &&
2092 } else if(adapter->hw.mac_type < e1000_82543) { 2402 max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
2093 DPRINTK(PROBE, ERR, "Jumbo Frames not supported on 82542\n"); 2403 DPRINTK(PROBE, ERR, "Jumbo Frames not supported "
2404 "on 82573\n");
2094 return -EINVAL; 2405 return -EINVAL;
2406 }
2095 2407
2096 } else if(max_frame <= E1000_RXBUFFER_4096) { 2408 if(adapter->hw.mac_type > e1000_82547_rev_2) {
2097 adapter->rx_buffer_len = E1000_RXBUFFER_4096; 2409 adapter->rx_buffer_len = max_frame;
2098 2410 E1000_ROUNDUP(adapter->rx_buffer_len, 1024);
2099 } else if(max_frame <= E1000_RXBUFFER_8192) {
2100 adapter->rx_buffer_len = E1000_RXBUFFER_8192;
2101
2102 } else { 2411 } else {
2103 adapter->rx_buffer_len = E1000_RXBUFFER_16384; 2412 if(unlikely((adapter->hw.mac_type < e1000_82543) &&
2413 (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE))) {
2414 DPRINTK(PROBE, ERR, "Jumbo Frames not supported "
2415 "on 82542\n");
2416 return -EINVAL;
2417
2418 } else {
2419 if(max_frame <= E1000_RXBUFFER_2048) {
2420 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
2421 } else if(max_frame <= E1000_RXBUFFER_4096) {
2422 adapter->rx_buffer_len = E1000_RXBUFFER_4096;
2423 } else if(max_frame <= E1000_RXBUFFER_8192) {
2424 adapter->rx_buffer_len = E1000_RXBUFFER_8192;
2425 } else if(max_frame <= E1000_RXBUFFER_16384) {
2426 adapter->rx_buffer_len = E1000_RXBUFFER_16384;
2427 }
2428 }
2104 } 2429 }
2105 2430
2106 if(old_mtu != adapter->rx_buffer_len && netif_running(netdev)) { 2431 netdev->mtu = new_mtu;
2432
2433 if(netif_running(netdev)) {
2107 e1000_down(adapter); 2434 e1000_down(adapter);
2108 e1000_up(adapter); 2435 e1000_up(adapter);
2109 } 2436 }
2110 2437
2111 netdev->mtu = new_mtu;
2112 adapter->hw.max_frame_size = max_frame; 2438 adapter->hw.max_frame_size = max_frame;
2113 2439
2114 return 0; 2440 return 0;
@@ -2199,6 +2525,17 @@ e1000_update_stats(struct e1000_adapter *adapter)
2199 adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC); 2525 adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC);
2200 adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC); 2526 adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC);
2201 } 2527 }
2528 if(hw->mac_type > e1000_82547_rev_2) {
2529 adapter->stats.iac += E1000_READ_REG(hw, IAC);
2530 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
2531 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
2532 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
2533 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
2534 adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC);
2535 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
2536 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
2537 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
2538 }
2202 2539
2203 /* Fill out the OS statistics structure */ 2540 /* Fill out the OS statistics structure */
2204 2541
@@ -2213,9 +2550,9 @@ e1000_update_stats(struct e1000_adapter *adapter)
2213 2550
2214 adapter->net_stats.rx_errors = adapter->stats.rxerrc + 2551 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
2215 adapter->stats.crcerrs + adapter->stats.algnerrc + 2552 adapter->stats.crcerrs + adapter->stats.algnerrc +
2216 adapter->stats.rlec + adapter->stats.rnbc + 2553 adapter->stats.rlec + adapter->stats.mpc +
2217 adapter->stats.mpc + adapter->stats.cexterr; 2554 adapter->stats.cexterr;
2218 adapter->net_stats.rx_dropped = adapter->stats.rnbc; 2555 adapter->net_stats.rx_dropped = adapter->stats.mpc;
2219 adapter->net_stats.rx_length_errors = adapter->stats.rlec; 2556 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
2220 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs; 2557 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
2221 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc; 2558 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
@@ -2300,11 +2637,11 @@ e1000_intr(int irq, void *data, struct pt_regs *regs)
2300 */ 2637 */
2301 if(hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2){ 2638 if(hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2){
2302 atomic_inc(&adapter->irq_sem); 2639 atomic_inc(&adapter->irq_sem);
2303 E1000_WRITE_REG(&adapter->hw, IMC, ~0); 2640 E1000_WRITE_REG(hw, IMC, ~0);
2304 } 2641 }
2305 2642
2306 for(i = 0; i < E1000_MAX_INTR; i++) 2643 for(i = 0; i < E1000_MAX_INTR; i++)
2307 if(unlikely(!e1000_clean_rx_irq(adapter) & 2644 if(unlikely(!adapter->clean_rx(adapter) &
2308 !e1000_clean_tx_irq(adapter))) 2645 !e1000_clean_tx_irq(adapter)))
2309 break; 2646 break;
2310 2647
@@ -2328,16 +2665,15 @@ e1000_clean(struct net_device *netdev, int *budget)
2328 int work_to_do = min(*budget, netdev->quota); 2665 int work_to_do = min(*budget, netdev->quota);
2329 int tx_cleaned; 2666 int tx_cleaned;
2330 int work_done = 0; 2667 int work_done = 0;
2331 2668
2332 tx_cleaned = e1000_clean_tx_irq(adapter); 2669 tx_cleaned = e1000_clean_tx_irq(adapter);
2333 e1000_clean_rx_irq(adapter, &work_done, work_to_do); 2670 adapter->clean_rx(adapter, &work_done, work_to_do);
2334 2671
2335 *budget -= work_done; 2672 *budget -= work_done;
2336 netdev->quota -= work_done; 2673 netdev->quota -= work_done;
2337 2674
2338 /* if no Tx and not enough Rx work done, exit the polling mode */ 2675 /* If no Tx and no Rx work done, exit the polling mode */
2339 if((!tx_cleaned && (work_done < work_to_do)) || 2676 if ((!tx_cleaned && (work_done == 0)) || !netif_running(netdev)) {
2340 !netif_running(netdev)) {
2341 netif_rx_complete(netdev); 2677 netif_rx_complete(netdev);
2342 e1000_irq_enable(adapter); 2678 e1000_irq_enable(adapter);
2343 return 0; 2679 return 0;
@@ -2367,11 +2703,10 @@ e1000_clean_tx_irq(struct e1000_adapter *adapter)
2367 eop_desc = E1000_TX_DESC(*tx_ring, eop); 2703 eop_desc = E1000_TX_DESC(*tx_ring, eop);
2368 2704
2369 while(eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) { 2705 while(eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
2370 /* pre-mature writeback of Tx descriptors */ 2706 /* Premature writeback of Tx descriptors clear (free buffers
2371 /* clear (free buffers and unmap pci_mapping) */ 2707 * and unmap pci_mapping) previous_buffer_info */
2372 /* previous_buffer_info */
2373 if (likely(adapter->previous_buffer_info.skb != NULL)) { 2708 if (likely(adapter->previous_buffer_info.skb != NULL)) {
2374 e1000_unmap_and_free_tx_resource(adapter, 2709 e1000_unmap_and_free_tx_resource(adapter,
2375 &adapter->previous_buffer_info); 2710 &adapter->previous_buffer_info);
2376 } 2711 }
2377 2712
@@ -2380,26 +2715,30 @@ e1000_clean_tx_irq(struct e1000_adapter *adapter)
2380 buffer_info = &tx_ring->buffer_info[i]; 2715 buffer_info = &tx_ring->buffer_info[i];
2381 cleaned = (i == eop); 2716 cleaned = (i == eop);
2382 2717
2383 /* pre-mature writeback of Tx descriptors */ 2718#ifdef NETIF_F_TSO
2384 /* save the cleaning of the this for the */ 2719 if (!(netdev->features & NETIF_F_TSO)) {
2385 /* next iteration */ 2720#endif
2386 if (cleaned) { 2721 e1000_unmap_and_free_tx_resource(adapter,
2387 memcpy(&adapter->previous_buffer_info, 2722 buffer_info);
2388 buffer_info, 2723#ifdef NETIF_F_TSO
2389 sizeof(struct e1000_buffer));
2390 memset(buffer_info,
2391 0,
2392 sizeof(struct e1000_buffer));
2393 } else { 2724 } else {
2394 e1000_unmap_and_free_tx_resource(adapter, 2725 if (cleaned) {
2395 buffer_info); 2726 memcpy(&adapter->previous_buffer_info,
2727 buffer_info,
2728 sizeof(struct e1000_buffer));
2729 memset(buffer_info, 0,
2730 sizeof(struct e1000_buffer));
2731 } else {
2732 e1000_unmap_and_free_tx_resource(
2733 adapter, buffer_info);
2734 }
2396 } 2735 }
2736#endif
2397 2737
2398 tx_desc->buffer_addr = 0; 2738 tx_desc->buffer_addr = 0;
2399 tx_desc->lower.data = 0; 2739 tx_desc->lower.data = 0;
2400 tx_desc->upper.data = 0; 2740 tx_desc->upper.data = 0;
2401 2741
2402 cleaned = (i == eop);
2403 if(unlikely(++i == tx_ring->count)) i = 0; 2742 if(unlikely(++i == tx_ring->count)) i = 0;
2404 } 2743 }
2405 2744
@@ -2416,57 +2755,107 @@ e1000_clean_tx_irq(struct e1000_adapter *adapter)
2416 netif_wake_queue(netdev); 2755 netif_wake_queue(netdev);
2417 2756
2418 spin_unlock(&adapter->tx_lock); 2757 spin_unlock(&adapter->tx_lock);
2419
2420 if(adapter->detect_tx_hung) { 2758 if(adapter->detect_tx_hung) {
2421 /* detect a transmit hang in hardware, this serializes the 2759
2760 /* Detect a transmit hang in hardware, this serializes the
2422 * check with the clearing of time_stamp and movement of i */ 2761 * check with the clearing of time_stamp and movement of i */
2423 adapter->detect_tx_hung = FALSE; 2762 adapter->detect_tx_hung = FALSE;
2424 if(tx_ring->buffer_info[i].dma && 2763 if (tx_ring->buffer_info[i].dma &&
2425 time_after(jiffies, tx_ring->buffer_info[i].time_stamp + HZ) && 2764 time_after(jiffies, tx_ring->buffer_info[i].time_stamp + HZ)
2426 !(E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_TXOFF)) 2765 && !(E1000_READ_REG(&adapter->hw, STATUS) &
2766 E1000_STATUS_TXOFF)) {
2767
2768 /* detected Tx unit hang */
2769 i = tx_ring->next_to_clean;
2770 eop = tx_ring->buffer_info[i].next_to_watch;
2771 eop_desc = E1000_TX_DESC(*tx_ring, eop);
2772 DPRINTK(TX_ERR, ERR, "Detected Tx Unit Hang\n"
2773 " TDH <%x>\n"
2774 " TDT <%x>\n"
2775 " next_to_use <%x>\n"
2776 " next_to_clean <%x>\n"
2777 "buffer_info[next_to_clean]\n"
2778 " dma <%llx>\n"
2779 " time_stamp <%lx>\n"
2780 " next_to_watch <%x>\n"
2781 " jiffies <%lx>\n"
2782 " next_to_watch.status <%x>\n",
2783 E1000_READ_REG(&adapter->hw, TDH),
2784 E1000_READ_REG(&adapter->hw, TDT),
2785 tx_ring->next_to_use,
2786 i,
2787 tx_ring->buffer_info[i].dma,
2788 tx_ring->buffer_info[i].time_stamp,
2789 eop,
2790 jiffies,
2791 eop_desc->upper.fields.status);
2427 netif_stop_queue(netdev); 2792 netif_stop_queue(netdev);
2793 }
2428 } 2794 }
2795#ifdef NETIF_F_TSO
2796
2797 if( unlikely(!(eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
2798 time_after(jiffies, adapter->previous_buffer_info.time_stamp + HZ)))
2799 e1000_unmap_and_free_tx_resource(
2800 adapter, &adapter->previous_buffer_info);
2429 2801
2802#endif
2430 return cleaned; 2803 return cleaned;
2431} 2804}
2432 2805
2433/** 2806/**
2434 * e1000_rx_checksum - Receive Checksum Offload for 82543 2807 * e1000_rx_checksum - Receive Checksum Offload for 82543
2435 * @adapter: board private structure 2808 * @adapter: board private structure
2436 * @rx_desc: receive descriptor 2809 * @status_err: receive descriptor status and error fields
2437 * @sk_buff: socket buffer with received data 2810 * @csum: receive descriptor csum field
2811 * @sk_buff: socket buffer with received data
2438 **/ 2812 **/
2439 2813
2440static inline void 2814static inline void
2441e1000_rx_checksum(struct e1000_adapter *adapter, 2815e1000_rx_checksum(struct e1000_adapter *adapter,
2442 struct e1000_rx_desc *rx_desc, 2816 uint32_t status_err, uint32_t csum,
2443 struct sk_buff *skb) 2817 struct sk_buff *skb)
2444{ 2818{
2819 uint16_t status = (uint16_t)status_err;
2820 uint8_t errors = (uint8_t)(status_err >> 24);
2821 skb->ip_summed = CHECKSUM_NONE;
2822
2445 /* 82543 or newer only */ 2823 /* 82543 or newer only */
2446 if(unlikely((adapter->hw.mac_type < e1000_82543) || 2824 if(unlikely(adapter->hw.mac_type < e1000_82543)) return;
2447 /* Ignore Checksum bit is set */ 2825 /* Ignore Checksum bit is set */
2448 (rx_desc->status & E1000_RXD_STAT_IXSM) || 2826 if(unlikely(status & E1000_RXD_STAT_IXSM)) return;
2449 /* TCP Checksum has not been calculated */ 2827 /* TCP/UDP checksum error bit is set */
2450 (!(rx_desc->status & E1000_RXD_STAT_TCPCS)))) { 2828 if(unlikely(errors & E1000_RXD_ERR_TCPE)) {
2451 skb->ip_summed = CHECKSUM_NONE;
2452 return;
2453 }
2454
2455 /* At this point we know the hardware did the TCP checksum */
2456 /* now look at the TCP checksum error bit */
2457 if(rx_desc->errors & E1000_RXD_ERR_TCPE) {
2458 /* let the stack verify checksum errors */ 2829 /* let the stack verify checksum errors */
2459 skb->ip_summed = CHECKSUM_NONE;
2460 adapter->hw_csum_err++; 2830 adapter->hw_csum_err++;
2831 return;
2832 }
2833 /* TCP/UDP Checksum has not been calculated */
2834 if(adapter->hw.mac_type <= e1000_82547_rev_2) {
2835 if(!(status & E1000_RXD_STAT_TCPCS))
2836 return;
2461 } else { 2837 } else {
2838 if(!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
2839 return;
2840 }
2841 /* It must be a TCP or UDP packet with a valid checksum */
2842 if (likely(status & E1000_RXD_STAT_TCPCS)) {
2462 /* TCP checksum is good */ 2843 /* TCP checksum is good */
2463 skb->ip_summed = CHECKSUM_UNNECESSARY; 2844 skb->ip_summed = CHECKSUM_UNNECESSARY;
2464 adapter->hw_csum_good++; 2845 } else if (adapter->hw.mac_type > e1000_82547_rev_2) {
2846 /* IP fragment with UDP payload */
2847 /* Hardware complements the payload checksum, so we undo it
2848 * and then put the value in host order for further stack use.
2849 */
2850 csum = ntohl(csum ^ 0xFFFF);
2851 skb->csum = csum;
2852 skb->ip_summed = CHECKSUM_HW;
2465 } 2853 }
2854 adapter->hw_csum_good++;
2466} 2855}
2467 2856
2468/** 2857/**
2469 * e1000_clean_rx_irq - Send received data up the network stack 2858 * e1000_clean_rx_irq - Send received data up the network stack; legacy
2470 * @adapter: board private structure 2859 * @adapter: board private structure
2471 **/ 2860 **/
2472 2861
@@ -2513,7 +2902,7 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter)
2513 if(unlikely(!(rx_desc->status & E1000_RXD_STAT_EOP))) { 2902 if(unlikely(!(rx_desc->status & E1000_RXD_STAT_EOP))) {
2514 /* All receives must fit into a single buffer */ 2903 /* All receives must fit into a single buffer */
2515 E1000_DBG("%s: Receive packet consumed multiple" 2904 E1000_DBG("%s: Receive packet consumed multiple"
2516 " buffers\n", netdev->name); 2905 " buffers\n", netdev->name);
2517 dev_kfree_skb_irq(skb); 2906 dev_kfree_skb_irq(skb);
2518 goto next_desc; 2907 goto next_desc;
2519 } 2908 }
@@ -2539,15 +2928,17 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter)
2539 skb_put(skb, length - ETHERNET_FCS_SIZE); 2928 skb_put(skb, length - ETHERNET_FCS_SIZE);
2540 2929
2541 /* Receive Checksum Offload */ 2930 /* Receive Checksum Offload */
2542 e1000_rx_checksum(adapter, rx_desc, skb); 2931 e1000_rx_checksum(adapter,
2543 2932 (uint32_t)(rx_desc->status) |
2933 ((uint32_t)(rx_desc->errors) << 24),
2934 rx_desc->csum, skb);
2544 skb->protocol = eth_type_trans(skb, netdev); 2935 skb->protocol = eth_type_trans(skb, netdev);
2545#ifdef CONFIG_E1000_NAPI 2936#ifdef CONFIG_E1000_NAPI
2546 if(unlikely(adapter->vlgrp && 2937 if(unlikely(adapter->vlgrp &&
2547 (rx_desc->status & E1000_RXD_STAT_VP))) { 2938 (rx_desc->status & E1000_RXD_STAT_VP))) {
2548 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, 2939 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
2549 le16_to_cpu(rx_desc->special) & 2940 le16_to_cpu(rx_desc->special) &
2550 E1000_RXD_SPC_VLAN_MASK); 2941 E1000_RXD_SPC_VLAN_MASK);
2551 } else { 2942 } else {
2552 netif_receive_skb(skb); 2943 netif_receive_skb(skb);
2553 } 2944 }
@@ -2570,16 +2961,142 @@ next_desc:
2570 2961
2571 rx_desc = E1000_RX_DESC(*rx_ring, i); 2962 rx_desc = E1000_RX_DESC(*rx_ring, i);
2572 } 2963 }
2573
2574 rx_ring->next_to_clean = i; 2964 rx_ring->next_to_clean = i;
2965 adapter->alloc_rx_buf(adapter);
2966
2967 return cleaned;
2968}
2969
2970/**
2971 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
2972 * @adapter: board private structure
2973 **/
2974
2975static boolean_t
2976#ifdef CONFIG_E1000_NAPI
2977e1000_clean_rx_irq_ps(struct e1000_adapter *adapter, int *work_done,
2978 int work_to_do)
2979#else
2980e1000_clean_rx_irq_ps(struct e1000_adapter *adapter)
2981#endif
2982{
2983 struct e1000_desc_ring *rx_ring = &adapter->rx_ring;
2984 union e1000_rx_desc_packet_split *rx_desc;
2985 struct net_device *netdev = adapter->netdev;
2986 struct pci_dev *pdev = adapter->pdev;
2987 struct e1000_buffer *buffer_info;
2988 struct e1000_ps_page *ps_page;
2989 struct e1000_ps_page_dma *ps_page_dma;
2990 struct sk_buff *skb;
2991 unsigned int i, j;
2992 uint32_t length, staterr;
2993 boolean_t cleaned = FALSE;
2994
2995 i = rx_ring->next_to_clean;
2996 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
2997 staterr = rx_desc->wb.middle.status_error;
2998
2999 while(staterr & E1000_RXD_STAT_DD) {
3000 buffer_info = &rx_ring->buffer_info[i];
3001 ps_page = &rx_ring->ps_page[i];
3002 ps_page_dma = &rx_ring->ps_page_dma[i];
3003#ifdef CONFIG_E1000_NAPI
3004 if(unlikely(*work_done >= work_to_do))
3005 break;
3006 (*work_done)++;
3007#endif
3008 cleaned = TRUE;
3009 pci_unmap_single(pdev, buffer_info->dma,
3010 buffer_info->length,
3011 PCI_DMA_FROMDEVICE);
3012
3013 skb = buffer_info->skb;
3014
3015 if(unlikely(!(staterr & E1000_RXD_STAT_EOP))) {
3016 E1000_DBG("%s: Packet Split buffers didn't pick up"
3017 " the full packet\n", netdev->name);
3018 dev_kfree_skb_irq(skb);
3019 goto next_desc;
3020 }
3021
3022 if(unlikely(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
3023 dev_kfree_skb_irq(skb);
3024 goto next_desc;
3025 }
3026
3027 length = le16_to_cpu(rx_desc->wb.middle.length0);
3028
3029 if(unlikely(!length)) {
3030 E1000_DBG("%s: Last part of the packet spanning"
3031 " multiple descriptors\n", netdev->name);
3032 dev_kfree_skb_irq(skb);
3033 goto next_desc;
3034 }
3035
3036 /* Good Receive */
3037 skb_put(skb, length);
3038
3039 for(j = 0; j < PS_PAGE_BUFFERS; j++) {
3040 if(!(length = le16_to_cpu(rx_desc->wb.upper.length[j])))
3041 break;
3042
3043 pci_unmap_page(pdev, ps_page_dma->ps_page_dma[j],
3044 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3045 ps_page_dma->ps_page_dma[j] = 0;
3046 skb_shinfo(skb)->frags[j].page =
3047 ps_page->ps_page[j];
3048 ps_page->ps_page[j] = NULL;
3049 skb_shinfo(skb)->frags[j].page_offset = 0;
3050 skb_shinfo(skb)->frags[j].size = length;
3051 skb_shinfo(skb)->nr_frags++;
3052 skb->len += length;
3053 skb->data_len += length;
3054 }
2575 3055
2576 e1000_alloc_rx_buffers(adapter); 3056 e1000_rx_checksum(adapter, staterr,
3057 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
3058 skb->protocol = eth_type_trans(skb, netdev);
3059
3060#ifdef HAVE_RX_ZERO_COPY
3061 if(likely(rx_desc->wb.upper.header_status &
3062 E1000_RXDPS_HDRSTAT_HDRSP))
3063 skb_shinfo(skb)->zero_copy = TRUE;
3064#endif
3065#ifdef CONFIG_E1000_NAPI
3066 if(unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
3067 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3068 le16_to_cpu(rx_desc->wb.middle.vlan &
3069 E1000_RXD_SPC_VLAN_MASK));
3070 } else {
3071 netif_receive_skb(skb);
3072 }
3073#else /* CONFIG_E1000_NAPI */
3074 if(unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
3075 vlan_hwaccel_rx(skb, adapter->vlgrp,
3076 le16_to_cpu(rx_desc->wb.middle.vlan &
3077 E1000_RXD_SPC_VLAN_MASK));
3078 } else {
3079 netif_rx(skb);
3080 }
3081#endif /* CONFIG_E1000_NAPI */
3082 netdev->last_rx = jiffies;
3083
3084next_desc:
3085 rx_desc->wb.middle.status_error &= ~0xFF;
3086 buffer_info->skb = NULL;
3087 if(unlikely(++i == rx_ring->count)) i = 0;
3088
3089 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
3090 staterr = rx_desc->wb.middle.status_error;
3091 }
3092 rx_ring->next_to_clean = i;
3093 adapter->alloc_rx_buf(adapter);
2577 3094
2578 return cleaned; 3095 return cleaned;
2579} 3096}
2580 3097
2581/** 3098/**
2582 * e1000_alloc_rx_buffers - Replace used receive buffers 3099 * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
2583 * @adapter: address of board private structure 3100 * @adapter: address of board private structure
2584 **/ 3101 **/
2585 3102
@@ -2592,43 +3109,43 @@ e1000_alloc_rx_buffers(struct e1000_adapter *adapter)
2592 struct e1000_rx_desc *rx_desc; 3109 struct e1000_rx_desc *rx_desc;
2593 struct e1000_buffer *buffer_info; 3110 struct e1000_buffer *buffer_info;
2594 struct sk_buff *skb; 3111 struct sk_buff *skb;
2595 unsigned int i, bufsz; 3112 unsigned int i;
3113 unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
2596 3114
2597 i = rx_ring->next_to_use; 3115 i = rx_ring->next_to_use;
2598 buffer_info = &rx_ring->buffer_info[i]; 3116 buffer_info = &rx_ring->buffer_info[i];
2599 3117
2600 while(!buffer_info->skb) { 3118 while(!buffer_info->skb) {
2601 bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
2602
2603 skb = dev_alloc_skb(bufsz); 3119 skb = dev_alloc_skb(bufsz);
3120
2604 if(unlikely(!skb)) { 3121 if(unlikely(!skb)) {
2605 /* Better luck next round */ 3122 /* Better luck next round */
2606 break; 3123 break;
2607 } 3124 }
2608 3125
2609 /* fix for errata 23, cant cross 64kB boundary */ 3126 /* Fix for errata 23, can't cross 64kB boundary */
2610 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) { 3127 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
2611 struct sk_buff *oldskb = skb; 3128 struct sk_buff *oldskb = skb;
2612 DPRINTK(RX_ERR,ERR, 3129 DPRINTK(RX_ERR, ERR, "skb align check failed: %u bytes "
2613 "skb align check failed: %u bytes at %p\n", 3130 "at %p\n", bufsz, skb->data);
2614 bufsz, skb->data); 3131 /* Try again, without freeing the previous */
2615 /* try again, without freeing the previous */
2616 skb = dev_alloc_skb(bufsz); 3132 skb = dev_alloc_skb(bufsz);
3133 /* Failed allocation, critical failure */
2617 if (!skb) { 3134 if (!skb) {
2618 dev_kfree_skb(oldskb); 3135 dev_kfree_skb(oldskb);
2619 break; 3136 break;
2620 } 3137 }
3138
2621 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) { 3139 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
2622 /* give up */ 3140 /* give up */
2623 dev_kfree_skb(skb); 3141 dev_kfree_skb(skb);
2624 dev_kfree_skb(oldskb); 3142 dev_kfree_skb(oldskb);
2625 break; /* while !buffer_info->skb */ 3143 break; /* while !buffer_info->skb */
2626 } else { 3144 } else {
2627 /* move on with the new one */ 3145 /* Use new allocation */
2628 dev_kfree_skb(oldskb); 3146 dev_kfree_skb(oldskb);
2629 } 3147 }
2630 } 3148 }
2631
2632 /* Make buffer alignment 2 beyond a 16 byte boundary 3149 /* Make buffer alignment 2 beyond a 16 byte boundary
2633 * this will result in a 16 byte aligned IP header after 3150 * this will result in a 16 byte aligned IP header after
2634 * the 14 byte MAC header is removed 3151 * the 14 byte MAC header is removed
@@ -2644,25 +3161,23 @@ e1000_alloc_rx_buffers(struct e1000_adapter *adapter)
2644 adapter->rx_buffer_len, 3161 adapter->rx_buffer_len,
2645 PCI_DMA_FROMDEVICE); 3162 PCI_DMA_FROMDEVICE);
2646 3163
2647 /* fix for errata 23, cant cross 64kB boundary */ 3164 /* Fix for errata 23, can't cross 64kB boundary */
2648 if(!e1000_check_64k_bound(adapter, 3165 if (!e1000_check_64k_bound(adapter,
2649 (void *)(unsigned long)buffer_info->dma, 3166 (void *)(unsigned long)buffer_info->dma,
2650 adapter->rx_buffer_len)) { 3167 adapter->rx_buffer_len)) {
2651 DPRINTK(RX_ERR,ERR, 3168 DPRINTK(RX_ERR, ERR,
2652 "dma align check failed: %u bytes at %ld\n", 3169 "dma align check failed: %u bytes at %p\n",
2653 adapter->rx_buffer_len, (unsigned long)buffer_info->dma); 3170 adapter->rx_buffer_len,
2654 3171 (void *)(unsigned long)buffer_info->dma);
2655 dev_kfree_skb(skb); 3172 dev_kfree_skb(skb);
2656 buffer_info->skb = NULL; 3173 buffer_info->skb = NULL;
2657 3174
2658 pci_unmap_single(pdev, 3175 pci_unmap_single(pdev, buffer_info->dma,
2659 buffer_info->dma,
2660 adapter->rx_buffer_len, 3176 adapter->rx_buffer_len,
2661 PCI_DMA_FROMDEVICE); 3177 PCI_DMA_FROMDEVICE);
2662 3178
2663 break; /* while !buffer_info->skb */ 3179 break; /* while !buffer_info->skb */
2664 } 3180 }
2665
2666 rx_desc = E1000_RX_DESC(*rx_ring, i); 3181 rx_desc = E1000_RX_DESC(*rx_ring, i);
2667 rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); 3182 rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
2668 3183
@@ -2672,7 +3187,6 @@ e1000_alloc_rx_buffers(struct e1000_adapter *adapter)
2672 * applicable for weak-ordered memory model archs, 3187 * applicable for weak-ordered memory model archs,
2673 * such as IA-64). */ 3188 * such as IA-64). */
2674 wmb(); 3189 wmb();
2675
2676 E1000_WRITE_REG(&adapter->hw, RDT, i); 3190 E1000_WRITE_REG(&adapter->hw, RDT, i);
2677 } 3191 }
2678 3192
@@ -2684,6 +3198,95 @@ e1000_alloc_rx_buffers(struct e1000_adapter *adapter)
2684} 3198}
2685 3199
2686/** 3200/**
3201 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
3202 * @adapter: address of board private structure
3203 **/
3204
3205static void
3206e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter)
3207{
3208 struct e1000_desc_ring *rx_ring = &adapter->rx_ring;
3209 struct net_device *netdev = adapter->netdev;
3210 struct pci_dev *pdev = adapter->pdev;
3211 union e1000_rx_desc_packet_split *rx_desc;
3212 struct e1000_buffer *buffer_info;
3213 struct e1000_ps_page *ps_page;
3214 struct e1000_ps_page_dma *ps_page_dma;
3215 struct sk_buff *skb;
3216 unsigned int i, j;
3217
3218 i = rx_ring->next_to_use;
3219 buffer_info = &rx_ring->buffer_info[i];
3220 ps_page = &rx_ring->ps_page[i];
3221 ps_page_dma = &rx_ring->ps_page_dma[i];
3222
3223 while(!buffer_info->skb) {
3224 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
3225
3226 for(j = 0; j < PS_PAGE_BUFFERS; j++) {
3227 if(unlikely(!ps_page->ps_page[j])) {
3228 ps_page->ps_page[j] =
3229 alloc_page(GFP_ATOMIC);
3230 if(unlikely(!ps_page->ps_page[j]))
3231 goto no_buffers;
3232 ps_page_dma->ps_page_dma[j] =
3233 pci_map_page(pdev,
3234 ps_page->ps_page[j],
3235 0, PAGE_SIZE,
3236 PCI_DMA_FROMDEVICE);
3237 }
3238 /* Refresh the desc even if buffer_addrs didn't
3239 * change because each write-back erases this info.
3240 */
3241 rx_desc->read.buffer_addr[j+1] =
3242 cpu_to_le64(ps_page_dma->ps_page_dma[j]);
3243 }
3244
3245 skb = dev_alloc_skb(adapter->rx_ps_bsize0 + NET_IP_ALIGN);
3246
3247 if(unlikely(!skb))
3248 break;
3249
3250 /* Make buffer alignment 2 beyond a 16 byte boundary
3251 * this will result in a 16 byte aligned IP header after
3252 * the 14 byte MAC header is removed
3253 */
3254 skb_reserve(skb, NET_IP_ALIGN);
3255
3256 skb->dev = netdev;
3257
3258 buffer_info->skb = skb;
3259 buffer_info->length = adapter->rx_ps_bsize0;
3260 buffer_info->dma = pci_map_single(pdev, skb->data,
3261 adapter->rx_ps_bsize0,
3262 PCI_DMA_FROMDEVICE);
3263
3264 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
3265
3266 if(unlikely((i & ~(E1000_RX_BUFFER_WRITE - 1)) == i)) {
3267 /* Force memory writes to complete before letting h/w
3268 * know there are new descriptors to fetch. (Only
3269 * applicable for weak-ordered memory model archs,
3270 * such as IA-64). */
3271 wmb();
3272 /* Hardware increments by 16 bytes, but packet split
3273 * descriptors are 32 bytes...so we increment tail
3274 * twice as much.
3275 */
3276 E1000_WRITE_REG(&adapter->hw, RDT, i<<1);
3277 }
3278
3279 if(unlikely(++i == rx_ring->count)) i = 0;
3280 buffer_info = &rx_ring->buffer_info[i];
3281 ps_page = &rx_ring->ps_page[i];
3282 ps_page_dma = &rx_ring->ps_page_dma[i];
3283 }
3284
3285no_buffers:
3286 rx_ring->next_to_use = i;
3287}
3288
3289/**
2687 * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers. 3290 * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers.
2688 * @adapter: 3291 * @adapter:
2689 **/ 3292 **/
@@ -2856,9 +3459,10 @@ void
2856e1000_pci_set_mwi(struct e1000_hw *hw) 3459e1000_pci_set_mwi(struct e1000_hw *hw)
2857{ 3460{
2858 struct e1000_adapter *adapter = hw->back; 3461 struct e1000_adapter *adapter = hw->back;
3462 int ret_val = pci_set_mwi(adapter->pdev);
2859 3463
2860 int ret; 3464 if(ret_val)
2861 ret = pci_set_mwi(adapter->pdev); 3465 DPRINTK(PROBE, ERR, "Error in setting MWI\n");
2862} 3466}
2863 3467
2864void 3468void
@@ -2917,6 +3521,7 @@ e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2917 rctl |= E1000_RCTL_VFE; 3521 rctl |= E1000_RCTL_VFE;
2918 rctl &= ~E1000_RCTL_CFIEN; 3522 rctl &= ~E1000_RCTL_CFIEN;
2919 E1000_WRITE_REG(&adapter->hw, RCTL, rctl); 3523 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
3524 e1000_update_mng_vlan(adapter);
2920 } else { 3525 } else {
2921 /* disable VLAN tag insert/strip */ 3526 /* disable VLAN tag insert/strip */
2922 ctrl = E1000_READ_REG(&adapter->hw, CTRL); 3527 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
@@ -2927,6 +3532,10 @@ e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2927 rctl = E1000_READ_REG(&adapter->hw, RCTL); 3532 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2928 rctl &= ~E1000_RCTL_VFE; 3533 rctl &= ~E1000_RCTL_VFE;
2929 E1000_WRITE_REG(&adapter->hw, RCTL, rctl); 3534 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
3535 if(adapter->mng_vlan_id != (uint16_t)E1000_MNG_VLAN_NONE) {
3536 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
3537 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
3538 }
2930 } 3539 }
2931 3540
2932 e1000_irq_enable(adapter); 3541 e1000_irq_enable(adapter);
@@ -2937,7 +3546,10 @@ e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
2937{ 3546{
2938 struct e1000_adapter *adapter = netdev->priv; 3547 struct e1000_adapter *adapter = netdev->priv;
2939 uint32_t vfta, index; 3548 uint32_t vfta, index;
2940 3549 if((adapter->hw.mng_cookie.status &
3550 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
3551 (vid == adapter->mng_vlan_id))
3552 return;
2941 /* add VID to filter table */ 3553 /* add VID to filter table */
2942 index = (vid >> 5) & 0x7F; 3554 index = (vid >> 5) & 0x7F;
2943 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index); 3555 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
@@ -2958,6 +3570,10 @@ e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid)
2958 3570
2959 e1000_irq_enable(adapter); 3571 e1000_irq_enable(adapter);
2960 3572
3573 if((adapter->hw.mng_cookie.status &
3574 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
3575 (vid == adapter->mng_vlan_id))
3576 return;
2961 /* remove VID from filter table */ 3577 /* remove VID from filter table */
2962 index = (vid >> 5) & 0x7F; 3578 index = (vid >> 5) & 0x7F;
2963 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index); 3579 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
@@ -3004,8 +3620,7 @@ e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx)
3004 break; 3620 break;
3005 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 3621 case SPEED_1000 + DUPLEX_HALF: /* not supported */
3006 default: 3622 default:
3007 DPRINTK(PROBE, ERR, 3623 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
3008 "Unsupported Speed/Duplexity configuration\n");
3009 return -EINVAL; 3624 return -EINVAL;
3010 } 3625 }
3011 return 0; 3626 return 0;
@@ -3033,7 +3648,7 @@ e1000_suspend(struct pci_dev *pdev, uint32_t state)
3033{ 3648{
3034 struct net_device *netdev = pci_get_drvdata(pdev); 3649 struct net_device *netdev = pci_get_drvdata(pdev);
3035 struct e1000_adapter *adapter = netdev->priv; 3650 struct e1000_adapter *adapter = netdev->priv;
3036 uint32_t ctrl, ctrl_ext, rctl, manc, status; 3651 uint32_t ctrl, ctrl_ext, rctl, manc, status, swsm;
3037 uint32_t wufc = adapter->wol; 3652 uint32_t wufc = adapter->wol;
3038 3653
3039 netif_device_detach(netdev); 3654 netif_device_detach(netdev);
@@ -3075,6 +3690,9 @@ e1000_suspend(struct pci_dev *pdev, uint32_t state)
3075 E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext); 3690 E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext);
3076 } 3691 }
3077 3692
3693 /* Allow time for pending master requests to run */
3694 e1000_disable_pciex_master(&adapter->hw);
3695
3078 E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN); 3696 E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN);
3079 E1000_WRITE_REG(&adapter->hw, WUFC, wufc); 3697 E1000_WRITE_REG(&adapter->hw, WUFC, wufc);
3080 pci_enable_wake(pdev, 3, 1); 3698 pci_enable_wake(pdev, 3, 1);
@@ -3099,6 +3717,16 @@ e1000_suspend(struct pci_dev *pdev, uint32_t state)
3099 } 3717 }
3100 } 3718 }
3101 3719
3720 switch(adapter->hw.mac_type) {
3721 case e1000_82573:
3722 swsm = E1000_READ_REG(&adapter->hw, SWSM);
3723 E1000_WRITE_REG(&adapter->hw, SWSM,
3724 swsm & ~E1000_SWSM_DRV_LOAD);
3725 break;
3726 default:
3727 break;
3728 }
3729
3102 pci_disable_device(pdev); 3730 pci_disable_device(pdev);
3103 3731
3104 state = (state > 0) ? 3 : 0; 3732 state = (state > 0) ? 3 : 0;
@@ -3113,13 +3741,12 @@ e1000_resume(struct pci_dev *pdev)
3113{ 3741{
3114 struct net_device *netdev = pci_get_drvdata(pdev); 3742 struct net_device *netdev = pci_get_drvdata(pdev);
3115 struct e1000_adapter *adapter = netdev->priv; 3743 struct e1000_adapter *adapter = netdev->priv;
3116 uint32_t manc, ret; 3744 uint32_t manc, ret, swsm;
3117 3745
3118 pci_set_power_state(pdev, 0); 3746 pci_set_power_state(pdev, 0);
3119 pci_restore_state(pdev); 3747 pci_restore_state(pdev);
3120 ret = pci_enable_device(pdev); 3748 ret = pci_enable_device(pdev);
3121 if (pdev->is_busmaster) 3749 pci_set_master(pdev);
3122 pci_set_master(pdev);
3123 3750
3124 pci_enable_wake(pdev, 3, 0); 3751 pci_enable_wake(pdev, 3, 0);
3125 pci_enable_wake(pdev, 4, 0); /* 4 == D3 cold */ 3752 pci_enable_wake(pdev, 4, 0); /* 4 == D3 cold */
@@ -3139,10 +3766,19 @@ e1000_resume(struct pci_dev *pdev)
3139 E1000_WRITE_REG(&adapter->hw, MANC, manc); 3766 E1000_WRITE_REG(&adapter->hw, MANC, manc);
3140 } 3767 }
3141 3768
3769 switch(adapter->hw.mac_type) {
3770 case e1000_82573:
3771 swsm = E1000_READ_REG(&adapter->hw, SWSM);
3772 E1000_WRITE_REG(&adapter->hw, SWSM,
3773 swsm | E1000_SWSM_DRV_LOAD);
3774 break;
3775 default:
3776 break;
3777 }
3778
3142 return 0; 3779 return 0;
3143} 3780}
3144#endif 3781#endif
3145
3146#ifdef CONFIG_NET_POLL_CONTROLLER 3782#ifdef CONFIG_NET_POLL_CONTROLLER
3147/* 3783/*
3148 * Polling 'interrupt' - used by things like netconsole to send skbs 3784 * Polling 'interrupt' - used by things like netconsole to send skbs
@@ -3150,7 +3786,7 @@ e1000_resume(struct pci_dev *pdev)
3150 * the interrupt routine is executing. 3786 * the interrupt routine is executing.
3151 */ 3787 */
3152static void 3788static void
3153e1000_netpoll (struct net_device *netdev) 3789e1000_netpoll(struct net_device *netdev)
3154{ 3790{
3155 struct e1000_adapter *adapter = netdev->priv; 3791 struct e1000_adapter *adapter = netdev->priv;
3156 disable_irq(adapter->pdev->irq); 3792 disable_irq(adapter->pdev->irq);
diff --git a/drivers/net/e1000/e1000_osdep.h b/drivers/net/e1000/e1000_osdep.h
index 970c656a517c..aac64de61437 100644
--- a/drivers/net/e1000/e1000_osdep.h
+++ b/drivers/net/e1000/e1000_osdep.h
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 3
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved. 4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free 7 under the terms of the GNU General Public License as published by the Free
@@ -42,7 +42,12 @@
42#include <linux/sched.h> 42#include <linux/sched.h>
43 43
44#ifndef msec_delay 44#ifndef msec_delay
45#define msec_delay(x) msleep(x) 45#define msec_delay(x) do { if(in_interrupt()) { \
46 /* Don't mdelay in interrupt context! */ \
47 BUG(); \
48 } else { \
49 msleep(x); \
50 } } while(0)
46 51
47/* Some workarounds require millisecond delays and are run during interrupt 52/* Some workarounds require millisecond delays and are run during interrupt
48 * context. Most notably, when establishing link, the phy may need tweaking 53 * context. Most notably, when establishing link, the phy may need tweaking
@@ -96,6 +101,29 @@ typedef enum {
96 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ 101 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
97 ((offset) << 2))) 102 ((offset) << 2)))
98 103
104#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
105#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
106
107#define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \
108 writew((value), ((a)->hw_addr + \
109 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
110 ((offset) << 1))))
111
112#define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \
113 readw((a)->hw_addr + \
114 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
115 ((offset) << 1)))
116
117#define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \
118 writeb((value), ((a)->hw_addr + \
119 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
120 (offset))))
121
122#define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \
123 readb((a)->hw_addr + \
124 (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
125 (offset)))
126
99#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS) 127#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS)
100 128
101#endif /* _E1000_OSDEP_H_ */ 129#endif /* _E1000_OSDEP_H_ */
diff --git a/drivers/net/e1000/e1000_param.c b/drivers/net/e1000/e1000_param.c
index e914d09fe6f9..676247f9f1cc 100644
--- a/drivers/net/e1000/e1000_param.c
+++ b/drivers/net/e1000/e1000_param.c
@@ -1,7 +1,7 @@
1/******************************************************************************* 1/*******************************************************************************
2 2
3 3
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved. 4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
5 5
6 This program is free software; you can redistribute it and/or modify it 6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free 7 under the terms of the GNU General Public License as published by the Free
@@ -478,7 +478,6 @@ e1000_check_options(struct e1000_adapter *adapter)
478 DPRINTK(PROBE, INFO, "%s set to dynamic mode\n", 478 DPRINTK(PROBE, INFO, "%s set to dynamic mode\n",
479 opt.name); 479 opt.name);
480 break; 480 break;
481 case -1:
482 default: 481 default:
483 e1000_validate_option(&adapter->itr, &opt, 482 e1000_validate_option(&adapter->itr, &opt,
484 adapter); 483 adapter);
diff --git a/drivers/net/fmv18x.c b/drivers/net/fmv18x.c
deleted file mode 100644
index 04c748523471..000000000000
--- a/drivers/net/fmv18x.c
+++ /dev/null
@@ -1,689 +0,0 @@
1/* fmv18x.c: A network device driver for the Fujitsu FMV-181/182/183/184.
2
3 Original: at1700.c (1993-94 by Donald Becker).
4 Copyright 1993 United States Government as represented by the
5 Director, National Security Agency.
6 The author may be reached as becker@scyld.com, or C/O
7 Scyld Computing Corporation
8 410 Severn Ave., Suite 210
9 Annapolis MD 21403
10
11 Modified by Yutaka TAMIYA (tamy@flab.fujitsu.co.jp)
12 Copyright 1994 Fujitsu Laboratories Ltd.
13 Special thanks to:
14 Masayoshi UTAKA (utaka@ace.yk.fujitsu.co.jp)
15 for testing this driver.
16 H. NEGISHI (agy, negishi@sun45.psd.cs.fujitsu.co.jp)
17 for suggestion of some program modification.
18 Masahiro SEKIGUCHI <seki@sysrap.cs.fujitsu.co.jp>
19 for suggestion of some program modification.
20 Kazutoshi MORIOKA (morioka@aurora.oaks.cs.fujitsu.co.jp)
21 for testing this driver.
22
23 This software may be used and distributed according to the terms
24 of the GNU General Public License, incorporated herein by reference.
25
26 This is a device driver for the Fujitsu FMV-181/182/183/184, which
27 is a straight-forward Fujitsu MB86965 implementation.
28
29 Sources:
30 at1700.c
31 The Fujitsu MB86965 datasheet.
32 The Fujitsu FMV-181/182 user's guide
33*/
34
35static const char version[] =
36 "fmv18x.c:v2.2.0 09/24/98 Yutaka TAMIYA (tamy@flab.fujitsu.co.jp)\n";
37
38#include <linux/module.h>
39#include <linux/kernel.h>
40#include <linux/types.h>
41#include <linux/fcntl.h>
42#include <linux/interrupt.h>
43#include <linux/ioport.h>
44#include <linux/in.h>
45#include <linux/slab.h>
46#include <linux/string.h>
47#include <linux/init.h>
48#include <linux/errno.h>
49#include <linux/spinlock.h>
50#include <linux/netdevice.h>
51#include <linux/etherdevice.h>
52#include <linux/skbuff.h>
53#include <linux/delay.h>
54#include <linux/bitops.h>
55
56#include <asm/system.h>
57#include <asm/io.h>
58#include <asm/dma.h>
59
60#define DRV_NAME "fmv18x"
61
62static unsigned fmv18x_probe_list[] __initdata = {
63 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x300, 0x340, 0
64};
65
66/* use 0 for production, 1 for verification, >2 for debug */
67#ifndef NET_DEBUG
68#define NET_DEBUG 1
69#endif
70static unsigned int net_debug = NET_DEBUG;
71
72typedef unsigned char uchar;
73
74/* Information that need to be kept for each board. */
75struct net_local {
76 struct net_device_stats stats;
77 long open_time; /* Useless example local info. */
78 uint tx_started:1; /* Number of packet on the Tx queue. */
79 uint tx_queue_ready:1; /* Tx queue is ready to be sent. */
80 uint rx_started:1; /* Packets are Rxing. */
81 uchar tx_queue; /* Number of packet on the Tx queue. */
82 ushort tx_queue_len; /* Current length of the Tx queue. */
83 spinlock_t lock;
84};
85
86
87/* Offsets from the base address. */
88#define STATUS 0
89#define TX_STATUS 0
90#define RX_STATUS 1
91#define TX_INTR 2 /* Bit-mapped interrupt enable registers. */
92#define RX_INTR 3
93#define TX_MODE 4
94#define RX_MODE 5
95#define CONFIG_0 6 /* Misc. configuration settings. */
96#define CONFIG_1 7
97/* Run-time register bank 2 definitions. */
98#define DATAPORT 8 /* Word-wide DMA or programmed-I/O dataport. */
99#define TX_START 10
100#define COL16CNTL 11 /* Controll Reg for 16 collisions */
101#define MODE13 13
102/* Fujitsu FMV-18x Card Configuration */
103#define FJ_STATUS0 0x10
104#define FJ_STATUS1 0x11
105#define FJ_CONFIG0 0x12
106#define FJ_CONFIG1 0x13
107#define FJ_MACADDR 0x14 /* 0x14 - 0x19 */
108#define FJ_BUFCNTL 0x1A
109#define FJ_BUFDATA 0x1C
110#define FMV18X_IO_EXTENT 32
111
112/* Index to functions, as function prototypes. */
113
114static int fmv18x_probe1(struct net_device *dev, short ioaddr);
115static int net_open(struct net_device *dev);
116static int net_send_packet(struct sk_buff *skb, struct net_device *dev);
117static irqreturn_t net_interrupt(int irq, void *dev_id, struct pt_regs *regs);
118static void net_rx(struct net_device *dev);
119static void net_timeout(struct net_device *dev);
120static int net_close(struct net_device *dev);
121static struct net_device_stats *net_get_stats(struct net_device *dev);
122static void set_multicast_list(struct net_device *dev);
123
124
125/* Check for a network adaptor of this type, and return '0' iff one exists.
126 If dev->base_addr == 0, probe all likely locations.
127 If dev->base_addr == 1, always return failure.
128 If dev->base_addr == 2, allocate space for the device and return success
129 (detachable devices only).
130 */
131
132static int io = 0x220;
133static int irq;
134
135struct net_device * __init fmv18x_probe(int unit)
136{
137 struct net_device *dev = alloc_etherdev(sizeof(struct net_local));
138 unsigned *port;
139 int err = 0;
140
141 if (!dev)
142 return ERR_PTR(-ENODEV);
143
144 if (unit >= 0) {
145 sprintf(dev->name, "eth%d", unit);
146 netdev_boot_setup_check(dev);
147 io = dev->base_addr;
148 irq = dev->irq;
149 }
150
151 SET_MODULE_OWNER(dev);
152
153 if (io > 0x1ff) { /* Check a single specified location. */
154 err = fmv18x_probe1(dev, io);
155 } else if (io != 0) { /* Don't probe at all. */
156 err = -ENXIO;
157 } else {
158 for (port = fmv18x_probe_list; *port; port++)
159 if (fmv18x_probe1(dev, *port) == 0)
160 break;
161 if (!*port)
162 err = -ENODEV;
163 }
164 if (err)
165 goto out;
166 err = register_netdev(dev);
167 if (err)
168 goto out1;
169 return dev;
170out1:
171 free_irq(dev->irq, dev);
172 release_region(dev->base_addr, FMV18X_IO_EXTENT);
173out:
174 free_netdev(dev);
175 return ERR_PTR(err);
176}
177
178/* The Fujitsu datasheet suggests that the NIC be probed for by checking its
179 "signature", the default bit pattern after a reset. This *doesn't* work --
180 there is no way to reset the bus interface without a complete power-cycle!
181
182 It turns out that ATI came to the same conclusion I did: the only thing
183 that can be done is checking a few bits and then diving right into MAC
184 address check. */
185
186static int __init fmv18x_probe1(struct net_device *dev, short ioaddr)
187{
188 char irqmap[4] = {3, 7, 10, 15};
189 char irqmap_pnp[8] = {3, 4, 5, 7, 9, 10, 11, 15};
190 unsigned int i, retval;
191 struct net_local *lp;
192
193 /* Resetting the chip doesn't reset the ISA interface, so don't bother.
194 That means we have to be careful with the register values we probe for.
195 */
196
197 if (!request_region(ioaddr, FMV18X_IO_EXTENT, DRV_NAME))
198 return -EBUSY;
199
200 dev->irq = irq;
201 dev->base_addr = ioaddr;
202
203 /* Check I/O address configuration and Fujitsu vendor code */
204 if (inb(ioaddr+FJ_MACADDR ) != 0x00
205 || inb(ioaddr+FJ_MACADDR+1) != 0x00
206 || inb(ioaddr+FJ_MACADDR+2) != 0x0e) {
207 retval = -ENODEV;
208 goto out;
209 }
210
211 /* Check PnP mode for FMV-183/184/183A/184A. */
212 /* This PnP routine is very poor. IO and IRQ should be known. */
213 if (inb(ioaddr + FJ_STATUS1) & 0x20) {
214 for (i = 0; i < 8; i++) {
215 if (dev->irq == irqmap_pnp[i])
216 break;
217 }
218 if (i == 8) {
219 retval = -ENODEV;
220 goto out;
221 }
222 } else {
223 if (fmv18x_probe_list[inb(ioaddr + FJ_CONFIG0) & 0x07] != ioaddr)
224 return -ENODEV;
225 dev->irq = irqmap[(inb(ioaddr + FJ_CONFIG0)>>6) & 0x03];
226 }
227
228 /* Snarf the interrupt vector now. */
229 retval = request_irq(dev->irq, &net_interrupt, 0, DRV_NAME, dev);
230 if (retval) {
231 printk ("FMV-18x found at %#3x, but it's unusable due to a conflict on"
232 "IRQ %d.\n", ioaddr, dev->irq);
233 goto out;
234 }
235
236 printk("%s: FMV-18x found at %#3x, IRQ %d, address ", dev->name,
237 ioaddr, dev->irq);
238
239 for(i = 0; i < 6; i++) {
240 unsigned char val = inb(ioaddr + FJ_MACADDR + i);
241 printk("%02x", val);
242 dev->dev_addr[i] = val;
243 }
244
245 /* "FJ_STATUS0" 12 bit 0x0400 means use regular 100 ohm 10baseT signals,
246 rather than 150 ohm shielded twisted pair compensation.
247 0x0000 == auto-sense the interface
248 0x0800 == use TP interface
249 0x1800 == use coax interface
250 */
251 {
252 const char *porttype[] = {"auto-sense", "10baseT", "auto-sense", "10base2/5"};
253 ushort setup_value = inb(ioaddr + FJ_STATUS0);
254
255 switch( setup_value & 0x07 ){
256 case 0x01 /* 10base5 */:
257 case 0x02 /* 10base2 */: dev->if_port = 0x18; break;
258 case 0x04 /* 10baseT */: dev->if_port = 0x08; break;
259 default /* auto-sense*/: dev->if_port = 0x00; break;
260 }
261 printk(" %s interface.\n", porttype[(dev->if_port>>3) & 3]);
262 }
263
264 /* Initialize LAN Controller and LAN Card */
265 outb(0xda, ioaddr + CONFIG_0); /* Initialize LAN Controller */
266 outb(0x00, ioaddr + CONFIG_1); /* Stand by mode */
267 outb(0x00, ioaddr + FJ_CONFIG1); /* Disable IRQ of LAN Card */
268 outb(0x00, ioaddr + FJ_BUFCNTL); /* Reset ? I'm not sure (TAMIYA) */
269
270 /* wait for a while */
271 udelay(200);
272
273 /* Set the station address in bank zero. */
274 outb(0x00, ioaddr + CONFIG_1);
275 for (i = 0; i < 6; i++)
276 outb(dev->dev_addr[i], ioaddr + 8 + i);
277
278 /* Switch to bank 1 and set the multicast table to accept none. */
279 outb(0x04, ioaddr + CONFIG_1);
280 for (i = 0; i < 8; i++)
281 outb(0x00, ioaddr + 8 + i);
282
283 /* Switch to bank 2 and lock our I/O address. */
284 outb(0x08, ioaddr + CONFIG_1);
285 outb(dev->if_port, ioaddr + MODE13);
286 outb(0x00, ioaddr + COL16CNTL);
287
288 if (net_debug)
289 printk(version);
290
291 /* Initialize the device structure. */
292 dev->priv = kmalloc(sizeof(struct net_local), GFP_KERNEL);
293 if (!dev->priv) {
294 retval = -ENOMEM;
295 goto out_irq;
296 }
297 memset(dev->priv, 0, sizeof(struct net_local));
298 lp = dev->priv;
299 spin_lock_init(&lp->lock);
300
301 dev->open = net_open;
302 dev->stop = net_close;
303 dev->hard_start_xmit = net_send_packet;
304 dev->tx_timeout = net_timeout;
305 dev->watchdog_timeo = HZ/10;
306 dev->get_stats = net_get_stats;
307 dev->set_multicast_list = set_multicast_list;
308 return 0;
309
310out_irq:
311 free_irq(dev->irq, dev);
312out:
313 release_region(ioaddr, FMV18X_IO_EXTENT);
314 return retval;
315}
316
317
318static int net_open(struct net_device *dev)
319{
320 struct net_local *lp = dev->priv;
321 int ioaddr = dev->base_addr;
322
323 /* Set the configuration register 0 to 32K 100ns. byte-wide memory,
324 16 bit bus access, and two 4K Tx, enable the Rx and Tx. */
325 outb(0x5a, ioaddr + CONFIG_0);
326
327 /* Powerup and switch to register bank 2 for the run-time registers. */
328 outb(0xe8, ioaddr + CONFIG_1);
329
330 lp->tx_started = 0;
331 lp->tx_queue_ready = 1;
332 lp->rx_started = 0;
333 lp->tx_queue = 0;
334 lp->tx_queue_len = 0;
335
336 /* Clear Tx and Rx Status */
337 outb(0xff, ioaddr + TX_STATUS);
338 outb(0xff, ioaddr + RX_STATUS);
339 lp->open_time = jiffies;
340
341 netif_start_queue(dev);
342
343 /* Enable the IRQ of the LAN Card */
344 outb(0x80, ioaddr + FJ_CONFIG1);
345
346 /* Enable both Tx and Rx interrupts */
347 outw(0x8182, ioaddr+TX_INTR);
348
349 return 0;
350}
351
352static void net_timeout(struct net_device *dev)
353{
354 struct net_local *lp = dev->priv;
355 int ioaddr = dev->base_addr;
356 unsigned long flags;
357
358
359 printk(KERN_WARNING "%s: transmit timed out with status %04x, %s?\n", dev->name,
360 htons(inw(ioaddr + TX_STATUS)),
361 inb(ioaddr + TX_STATUS) & 0x80
362 ? "IRQ conflict" : "network cable problem");
363 printk(KERN_WARNING "%s: timeout registers: %04x %04x %04x %04x %04x %04x %04x %04x.\n",
364 dev->name, htons(inw(ioaddr + 0)),
365 htons(inw(ioaddr + 2)), htons(inw(ioaddr + 4)),
366 htons(inw(ioaddr + 6)), htons(inw(ioaddr + 8)),
367 htons(inw(ioaddr +10)), htons(inw(ioaddr +12)),
368 htons(inw(ioaddr +14)));
369 printk(KERN_WARNING "eth card: %04x %04x\n",
370 htons(inw(ioaddr+FJ_STATUS0)),
371 htons(inw(ioaddr+FJ_CONFIG0)));
372 lp->stats.tx_errors++;
373 /* ToDo: We should try to restart the adaptor... */
374 spin_lock_irqsave(&lp->lock, flags);
375
376 /* Initialize LAN Controller and LAN Card */
377 outb(0xda, ioaddr + CONFIG_0); /* Initialize LAN Controller */
378 outb(0x00, ioaddr + CONFIG_1); /* Stand by mode */
379 outb(0x00, ioaddr + FJ_CONFIG1); /* Disable IRQ of LAN Card */
380 outb(0x00, ioaddr + FJ_BUFCNTL); /* Reset ? I'm not sure */
381 net_open(dev);
382 spin_unlock_irqrestore(&lp->lock, flags);
383
384 netif_wake_queue(dev);
385}
386
387static int net_send_packet(struct sk_buff *skb, struct net_device *dev)
388{
389 struct net_local *lp = dev->priv;
390 int ioaddr = dev->base_addr;
391 short length = skb->len;
392 unsigned char *buf;
393 unsigned long flags;
394
395 /* Block a transmit from overlapping. */
396
397 if (length > ETH_FRAME_LEN) {
398 if (net_debug)
399 printk("%s: Attempting to send a large packet (%d bytes).\n",
400 dev->name, length);
401 return 1;
402 }
403
404 if (length < ETH_ZLEN) {
405 skb = skb_padto(skb, ETH_ZLEN);
406 if (skb == NULL)
407 return 0;
408 length = ETH_ZLEN;
409 }
410 buf = skb->data;
411
412 if (net_debug > 4)
413 printk("%s: Transmitting a packet of length %lu.\n", dev->name,
414 (unsigned long)skb->len);
415 /* We may not start transmitting unless we finish transferring
416 a packet into the Tx queue. During executing the following
417 codes we possibly catch a Tx interrupt. Thus we flag off
418 tx_queue_ready, so that we prevent the interrupt routine
419 (net_interrupt) to start transmitting. */
420 spin_lock_irqsave(&lp->lock, flags);
421 lp->tx_queue_ready = 0;
422 {
423 outw(length, ioaddr + DATAPORT);
424 outsw(ioaddr + DATAPORT, buf, (length + 1) >> 1);
425 lp->tx_queue++;
426 lp->tx_queue_len += length + 2;
427 }
428 lp->tx_queue_ready = 1;
429 spin_unlock_irqrestore(&lp->lock, flags);
430
431 if (lp->tx_started == 0) {
432 /* If the Tx is idle, always trigger a transmit. */
433 outb(0x80 | lp->tx_queue, ioaddr + TX_START);
434 lp->tx_queue = 0;
435 lp->tx_queue_len = 0;
436 dev->trans_start = jiffies;
437 lp->tx_started = 1;
438 } else if (lp->tx_queue_len >= 4096 - 1502) /* No room for a packet */
439 netif_stop_queue(dev);
440
441 dev_kfree_skb(skb);
442 return 0;
443}
444
445/* The typical workload of the driver:
446 Handle the network interface interrupts. */
447static irqreturn_t
448net_interrupt(int irq, void *dev_id, struct pt_regs *regs)
449{
450 struct net_device *dev = dev_id;
451 struct net_local *lp;
452 int ioaddr, status;
453
454 ioaddr = dev->base_addr;
455 lp = dev->priv;
456 status = inw(ioaddr + TX_STATUS);
457 outw(status, ioaddr + TX_STATUS);
458
459 if (net_debug > 4)
460 printk("%s: Interrupt with status %04x.\n", dev->name, status);
461 if (lp->rx_started == 0 &&
462 (status & 0xff00 || (inb(ioaddr + RX_MODE) & 0x40) == 0)) {
463 /* Got a packet(s).
464 We cannot execute net_rx more than once at the same time for
465 the same device. During executing net_rx, we possibly catch a
466 Tx interrupt. Thus we flag on rx_started, so that we prevent
467 the interrupt routine (net_interrupt) to dive into net_rx
468 again. */
469 lp->rx_started = 1;
470 outb(0x00, ioaddr + RX_INTR); /* Disable RX intr. */
471 net_rx(dev);
472 outb(0x81, ioaddr + RX_INTR); /* Enable RX intr. */
473 lp->rx_started = 0;
474 }
475 if (status & 0x00ff) {
476 if (status & 0x02) {
477 /* More than 16 collisions occurred */
478 if (net_debug > 4)
479 printk("%s: 16 Collision occur during Txing.\n", dev->name);
480 /* Cancel sending a packet. */
481 outb(0x03, ioaddr + COL16CNTL);
482 lp->stats.collisions++;
483 }
484 if (status & 0x82) {
485 spin_lock(&lp->lock);
486 lp->stats.tx_packets++;
487 if (lp->tx_queue && lp->tx_queue_ready) {
488 outb(0x80 | lp->tx_queue, ioaddr + TX_START);
489 lp->tx_queue = 0;
490 lp->tx_queue_len = 0;
491 dev->trans_start = jiffies;
492 netif_wake_queue(dev); /* Inform upper layers. */
493 } else {
494 lp->tx_started = 0;
495 netif_wake_queue(dev); /* Inform upper layers. */
496 }
497 spin_unlock(&lp->lock);
498 }
499 }
500 return IRQ_RETVAL(status);
501}
502
503/* We have a good packet(s), get it/them out of the buffers. */
504static void net_rx(struct net_device *dev)
505{
506 struct net_local *lp = dev->priv;
507 int ioaddr = dev->base_addr;
508 int boguscount = 5;
509
510 while ((inb(ioaddr + RX_MODE) & 0x40) == 0) {
511 /* Clear PKT_RDY bit: by agy 19940922 */
512 /* outb(0x80, ioaddr + RX_STATUS); */
513 ushort status = inw(ioaddr + DATAPORT);
514
515 if (net_debug > 4)
516 printk("%s: Rxing packet mode %02x status %04x.\n",
517 dev->name, inb(ioaddr + RX_MODE), status);
518#ifndef final_version
519 if (status == 0) {
520 outb(0x05, ioaddr + 14);
521 break;
522 }
523#endif
524
525 if ((status & 0xF0) != 0x20) { /* There was an error. */
526 lp->stats.rx_errors++;
527 if (status & 0x08) lp->stats.rx_length_errors++;
528 if (status & 0x04) lp->stats.rx_frame_errors++;
529 if (status & 0x02) lp->stats.rx_crc_errors++;
530 if (status & 0x01) lp->stats.rx_over_errors++;
531 } else {
532 ushort pkt_len = inw(ioaddr + DATAPORT);
533 /* Malloc up new buffer. */
534 struct sk_buff *skb;
535
536 if (pkt_len > 1550) {
537 printk("%s: The FMV-18x claimed a very large packet, size %d.\n",
538 dev->name, pkt_len);
539 outb(0x05, ioaddr + 14);
540 lp->stats.rx_errors++;
541 break;
542 }
543 skb = dev_alloc_skb(pkt_len+3);
544 if (skb == NULL) {
545 printk("%s: Memory squeeze, dropping packet (len %d).\n",
546 dev->name, pkt_len);
547 outb(0x05, ioaddr + 14);
548 lp->stats.rx_dropped++;
549 break;
550 }
551 skb->dev = dev;
552 skb_reserve(skb,2);
553
554 insw(ioaddr + DATAPORT, skb_put(skb,pkt_len), (pkt_len + 1) >> 1);
555
556 if (net_debug > 5) {
557 int i;
558 printk("%s: Rxed packet of length %d: ", dev->name, pkt_len);
559 for (i = 0; i < 14; i++)
560 printk(" %02x", skb->data[i]);
561 printk(".\n");
562 }
563
564 skb->protocol=eth_type_trans(skb, dev);
565 netif_rx(skb);
566 dev->last_rx = jiffies;
567 lp->stats.rx_packets++;
568 lp->stats.rx_bytes += pkt_len;
569 }
570 if (--boguscount <= 0)
571 break;
572 }
573
574 /* If any worth-while packets have been received, dev_rint()
575 has done a mark_bh(NET_BH) for us and will work on them
576 when we get to the bottom-half routine. */
577 {
578 int i;
579 for (i = 0; i < 20; i++) {
580 if ((inb(ioaddr + RX_MODE) & 0x40) == 0x40)
581 break;
582 (void)inw(ioaddr + DATAPORT); /* dummy status read */
583 outb(0x05, ioaddr + 14);
584 }
585
586 if (net_debug > 5 && i > 0)
587 printk("%s: Exint Rx packet with mode %02x after %d ticks.\n",
588 dev->name, inb(ioaddr + RX_MODE), i);
589 }
590
591 return;
592}
593
594/* The inverse routine to net_open(). */
595static int net_close(struct net_device *dev)
596{
597 int ioaddr = dev->base_addr;
598
599 ((struct net_local *)dev->priv)->open_time = 0;
600
601 netif_stop_queue(dev);
602
603 /* Set configuration register 0 to disable Tx and Rx. */
604 outb(0xda, ioaddr + CONFIG_0);
605
606 /* Update the statistics -- ToDo. */
607
608 /* Power-down the chip. Green, green, green! */
609 outb(0x00, ioaddr + CONFIG_1);
610
611 /* Set the ethernet adaptor disable IRQ */
612 outb(0x00, ioaddr + FJ_CONFIG1);
613
614 return 0;
615}
616
617/* Get the current statistics. This may be called with the card open or
618 closed. */
619static struct net_device_stats *net_get_stats(struct net_device *dev)
620{
621 struct net_local *lp = dev->priv;
622 return &lp->stats;
623}
624
625/* Set or clear the multicast filter for this adaptor.
626 num_addrs == -1 Promiscuous mode, receive all packets
627 num_addrs == 0 Normal mode, clear multicast list
628 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
629 best-effort filtering.
630 */
631
632static void set_multicast_list(struct net_device *dev)
633{
634 short ioaddr = dev->base_addr;
635 if (dev->mc_count || dev->flags&(IFF_PROMISC|IFF_ALLMULTI))
636 {
637 /*
638 * We must make the kernel realise we had to move
639 * into promisc mode or we start all out war on
640 * the cable. - AC
641 */
642 dev->flags|=IFF_PROMISC;
643
644 outb(3, ioaddr + RX_MODE); /* Enable promiscuous mode */
645 }
646 else
647 outb(2, ioaddr + RX_MODE); /* Disable promiscuous, use normal mode */
648}
649
650#ifdef MODULE
651static struct net_device *dev_fmv18x;
652
653MODULE_PARM(io, "i");
654MODULE_PARM(irq, "i");
655MODULE_PARM(net_debug, "i");
656MODULE_PARM_DESC(io, "FMV-18X I/O address");
657MODULE_PARM_DESC(irq, "FMV-18X IRQ number");
658MODULE_PARM_DESC(net_debug, "FMV-18X debug level (0-1,5-6)");
659MODULE_LICENSE("GPL");
660
661int init_module(void)
662{
663 if (io == 0)
664 printk("fmv18x: You should not use auto-probing with insmod!\n");
665 dev_fmv18x = fmv18x_probe(-1);
666 if (IS_ERR(dev_fmv18x))
667 return PTR_ERR(dev_fmv18x);
668 return 0;
669}
670
671void
672cleanup_module(void)
673{
674 unregister_netdev(dev_fmv18x);
675 free_irq(dev_fmv18x->irq, dev_fmv18x);
676 release_region(dev_fmv18x->base_addr, FMV18X_IO_EXTENT);
677 free_netdev(dev_fmv18x);
678}
679#endif /* MODULE */
680
681/*
682 * Local variables:
683 * compile-command: "gcc -D__KERNEL__ -I/usr/src/linux/net/inet -Wall -Wstrict-prototypes -O6 -m486 -c fmv18x.c"
684 * version-control: t
685 * kept-new-versions: 5
686 * tab-width: 4
687 * c-indent-level: 4
688 * End:
689 */
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index cda48c5d72a9..4ebcd052e150 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -81,6 +81,7 @@
81 * cause DMA to kfree'd memory. 81 * cause DMA to kfree'd memory.
82 * 0.31: 14 Nov 2004: ethtool support for getting/setting link 82 * 0.31: 14 Nov 2004: ethtool support for getting/setting link
83 * capabilities. 83 * capabilities.
84 * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
84 * 85 *
85 * Known bugs: 86 * Known bugs:
86 * We suspect that on some hardware no TX done interrupts are generated. 87 * We suspect that on some hardware no TX done interrupts are generated.
@@ -92,7 +93,7 @@
92 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few 93 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
93 * superfluous timer interrupts from the nic. 94 * superfluous timer interrupts from the nic.
94 */ 95 */
95#define FORCEDETH_VERSION "0.31" 96#define FORCEDETH_VERSION "0.32"
96#define DRV_NAME "forcedeth" 97#define DRV_NAME "forcedeth"
97 98
98#include <linux/module.h> 99#include <linux/module.h>
@@ -109,6 +110,7 @@
109#include <linux/mii.h> 110#include <linux/mii.h>
110#include <linux/random.h> 111#include <linux/random.h>
111#include <linux/init.h> 112#include <linux/init.h>
113#include <linux/if_vlan.h>
112 114
113#include <asm/irq.h> 115#include <asm/irq.h>
114#include <asm/io.h> 116#include <asm/io.h>
@@ -1013,6 +1015,59 @@ static void nv_tx_timeout(struct net_device *dev)
1013 spin_unlock_irq(&np->lock); 1015 spin_unlock_irq(&np->lock);
1014} 1016}
1015 1017
1018/*
1019 * Called when the nic notices a mismatch between the actual data len on the
1020 * wire and the len indicated in the 802 header
1021 */
1022static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1023{
1024 int hdrlen; /* length of the 802 header */
1025 int protolen; /* length as stored in the proto field */
1026
1027 /* 1) calculate len according to header */
1028 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) {
1029 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1030 hdrlen = VLAN_HLEN;
1031 } else {
1032 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1033 hdrlen = ETH_HLEN;
1034 }
1035 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1036 dev->name, datalen, protolen, hdrlen);
1037 if (protolen > ETH_DATA_LEN)
1038 return datalen; /* Value in proto field not a len, no checks possible */
1039
1040 protolen += hdrlen;
1041 /* consistency checks: */
1042 if (datalen > ETH_ZLEN) {
1043 if (datalen >= protolen) {
1044 /* more data on wire than in 802 header, trim of
1045 * additional data.
1046 */
1047 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1048 dev->name, protolen);
1049 return protolen;
1050 } else {
1051 /* less data on wire than mentioned in header.
1052 * Discard the packet.
1053 */
1054 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1055 dev->name);
1056 return -1;
1057 }
1058 } else {
1059 /* short packet. Accept only if 802 values are also short */
1060 if (protolen > ETH_ZLEN) {
1061 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1062 dev->name);
1063 return -1;
1064 }
1065 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1066 dev->name, datalen);
1067 return datalen;
1068 }
1069}
1070
1016static void nv_rx_process(struct net_device *dev) 1071static void nv_rx_process(struct net_device *dev)
1017{ 1072{
1018 struct fe_priv *np = get_nvpriv(dev); 1073 struct fe_priv *np = get_nvpriv(dev);
@@ -1064,7 +1119,7 @@ static void nv_rx_process(struct net_device *dev)
1064 np->stats.rx_errors++; 1119 np->stats.rx_errors++;
1065 goto next_pkt; 1120 goto next_pkt;
1066 } 1121 }
1067 if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4)) { 1122 if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1068 np->stats.rx_errors++; 1123 np->stats.rx_errors++;
1069 goto next_pkt; 1124 goto next_pkt;
1070 } 1125 }
@@ -1078,22 +1133,24 @@ static void nv_rx_process(struct net_device *dev)
1078 np->stats.rx_errors++; 1133 np->stats.rx_errors++;
1079 goto next_pkt; 1134 goto next_pkt;
1080 } 1135 }
1081 if (Flags & NV_RX_ERROR) { 1136 if (Flags & NV_RX_ERROR4) {
1082 /* framing errors are soft errors, the rest is fatal. */ 1137 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1083 if (Flags & NV_RX_FRAMINGERR) { 1138 if (len < 0) {
1084 if (Flags & NV_RX_SUBSTRACT1) {
1085 len--;
1086 }
1087 } else {
1088 np->stats.rx_errors++; 1139 np->stats.rx_errors++;
1089 goto next_pkt; 1140 goto next_pkt;
1090 } 1141 }
1091 } 1142 }
1143 /* framing errors are soft errors. */
1144 if (Flags & NV_RX_FRAMINGERR) {
1145 if (Flags & NV_RX_SUBSTRACT1) {
1146 len--;
1147 }
1148 }
1092 } else { 1149 } else {
1093 if (!(Flags & NV_RX2_DESCRIPTORVALID)) 1150 if (!(Flags & NV_RX2_DESCRIPTORVALID))
1094 goto next_pkt; 1151 goto next_pkt;
1095 1152
1096 if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4)) { 1153 if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1097 np->stats.rx_errors++; 1154 np->stats.rx_errors++;
1098 goto next_pkt; 1155 goto next_pkt;
1099 } 1156 }
@@ -1107,17 +1164,19 @@ static void nv_rx_process(struct net_device *dev)
1107 np->stats.rx_errors++; 1164 np->stats.rx_errors++;
1108 goto next_pkt; 1165 goto next_pkt;
1109 } 1166 }
1110 if (Flags & NV_RX2_ERROR) { 1167 if (Flags & NV_RX2_ERROR4) {
1111 /* framing errors are soft errors, the rest is fatal. */ 1168 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1112 if (Flags & NV_RX2_FRAMINGERR) { 1169 if (len < 0) {
1113 if (Flags & NV_RX2_SUBSTRACT1) {
1114 len--;
1115 }
1116 } else {
1117 np->stats.rx_errors++; 1170 np->stats.rx_errors++;
1118 goto next_pkt; 1171 goto next_pkt;
1119 } 1172 }
1120 } 1173 }
1174 /* framing errors are soft errors */
1175 if (Flags & NV_RX2_FRAMINGERR) {
1176 if (Flags & NV_RX2_SUBSTRACT1) {
1177 len--;
1178 }
1179 }
1121 Flags &= NV_RX2_CHECKSUMMASK; 1180 Flags &= NV_RX2_CHECKSUMMASK;
1122 if (Flags == NV_RX2_CHECKSUMOK1 || 1181 if (Flags == NV_RX2_CHECKSUMOK1 ||
1123 Flags == NV_RX2_CHECKSUMOK2 || 1182 Flags == NV_RX2_CHECKSUMOK2 ||
@@ -1480,6 +1539,13 @@ static void nv_do_nic_poll(unsigned long data)
1480 enable_irq(dev->irq); 1539 enable_irq(dev->irq);
1481} 1540}
1482 1541
1542#ifdef CONFIG_NET_POLL_CONTROLLER
1543static void nv_poll_controller(struct net_device *dev)
1544{
1545 nv_do_nic_poll((unsigned long) dev);
1546}
1547#endif
1548
1483static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 1549static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1484{ 1550{
1485 struct fe_priv *np = get_nvpriv(dev); 1551 struct fe_priv *np = get_nvpriv(dev);
@@ -1962,6 +2028,9 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
1962 dev->get_stats = nv_get_stats; 2028 dev->get_stats = nv_get_stats;
1963 dev->change_mtu = nv_change_mtu; 2029 dev->change_mtu = nv_change_mtu;
1964 dev->set_multicast_list = nv_set_multicast; 2030 dev->set_multicast_list = nv_set_multicast;
2031#ifdef CONFIG_NET_POLL_CONTROLLER
2032 dev->poll_controller = nv_poll_controller;
2033#endif
1965 SET_ETHTOOL_OPS(dev, &ops); 2034 SET_ETHTOOL_OPS(dev, &ops);
1966 dev->tx_timeout = nv_tx_timeout; 2035 dev->tx_timeout = nv_tx_timeout;
1967 dev->watchdog_timeo = NV_WATCHDOG_TIMEO; 2036 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
diff --git a/drivers/net/hamradio/6pack.c b/drivers/net/hamradio/6pack.c
index 89454915b857..e44f8e9055ef 100644
--- a/drivers/net/hamradio/6pack.c
+++ b/drivers/net/hamradio/6pack.c
@@ -848,7 +848,7 @@ static void __exit sixpack_exit_driver(void)
848{ 848{
849 int ret; 849 int ret;
850 850
851 if ((ret = tty_register_ldisc(N_6PACK, NULL))) 851 if ((ret = tty_unregister_ldisc(N_6PACK)))
852 printk(msg_unregfail, ret); 852 printk(msg_unregfail, ret);
853} 853}
854 854
diff --git a/drivers/net/hamradio/baycom_epp.c b/drivers/net/hamradio/baycom_epp.c
index 1c563f905a59..a7f15d9f13e5 100644
--- a/drivers/net/hamradio/baycom_epp.c
+++ b/drivers/net/hamradio/baycom_epp.c
@@ -374,29 +374,6 @@ static inline void do_kiss_params(struct baycom_state *bc,
374} 374}
375 375
376/* --------------------------------------------------------------------- */ 376/* --------------------------------------------------------------------- */
377/*
378 * high performance HDLC encoder
379 * yes, it's ugly, but generates pretty good code
380 */
381
382#define ENCODEITERA(j) \
383({ \
384 if (!(notbitstream & (0x1f0 << j))) \
385 goto stuff##j; \
386 encodeend##j: ; \
387})
388
389#define ENCODEITERB(j) \
390({ \
391 stuff##j: \
392 bitstream &= ~(0x100 << j); \
393 bitbuf = (bitbuf & (((2 << j) << numbit) - 1)) | \
394 ((bitbuf & ~(((2 << j) << numbit) - 1)) << 1); \
395 numbit++; \
396 notbitstream = ~bitstream; \
397 goto encodeend##j; \
398})
399
400 377
401static void encode_hdlc(struct baycom_state *bc) 378static void encode_hdlc(struct baycom_state *bc)
402{ 379{
@@ -405,6 +382,7 @@ static void encode_hdlc(struct baycom_state *bc)
405 int pkt_len; 382 int pkt_len;
406 unsigned bitstream, notbitstream, bitbuf, numbit, crc; 383 unsigned bitstream, notbitstream, bitbuf, numbit, crc;
407 unsigned char crcarr[2]; 384 unsigned char crcarr[2];
385 int j;
408 386
409 if (bc->hdlctx.bufcnt > 0) 387 if (bc->hdlctx.bufcnt > 0)
410 return; 388 return;
@@ -429,24 +407,14 @@ static void encode_hdlc(struct baycom_state *bc)
429 pkt_len--; 407 pkt_len--;
430 if (!pkt_len) 408 if (!pkt_len)
431 bp = crcarr; 409 bp = crcarr;
432 ENCODEITERA(0); 410 for (j = 0; j < 8; j++)
433 ENCODEITERA(1); 411 if (unlikely(!(notbitstream & (0x1f0 << j)))) {
434 ENCODEITERA(2); 412 bitstream &= ~(0x100 << j);
435 ENCODEITERA(3); 413 bitbuf = (bitbuf & (((2 << j) << numbit) - 1)) |
436 ENCODEITERA(4); 414 ((bitbuf & ~(((2 << j) << numbit) - 1)) << 1);
437 ENCODEITERA(5); 415 numbit++;
438 ENCODEITERA(6); 416 notbitstream = ~bitstream;
439 ENCODEITERA(7); 417 }
440 goto enditer;
441 ENCODEITERB(0);
442 ENCODEITERB(1);
443 ENCODEITERB(2);
444 ENCODEITERB(3);
445 ENCODEITERB(4);
446 ENCODEITERB(5);
447 ENCODEITERB(6);
448 ENCODEITERB(7);
449 enditer:
450 numbit += 8; 418 numbit += 8;
451 while (numbit >= 8) { 419 while (numbit >= 8) {
452 *wp++ = bitbuf; 420 *wp++ = bitbuf;
@@ -610,37 +578,6 @@ static void do_rxpacket(struct net_device *dev)
610 bc->stats.rx_packets++; 578 bc->stats.rx_packets++;
611} 579}
612 580
613#define DECODEITERA(j) \
614({ \
615 if (!(notbitstream & (0x0fc << j))) /* flag or abort */ \
616 goto flgabrt##j; \
617 if ((bitstream & (0x1f8 << j)) == (0xf8 << j)) /* stuffed bit */ \
618 goto stuff##j; \
619 enditer##j: ; \
620})
621
622#define DECODEITERB(j) \
623({ \
624 flgabrt##j: \
625 if (!(notbitstream & (0x1fc << j))) { /* abort received */ \
626 state = 0; \
627 goto enditer##j; \
628 } \
629 if ((bitstream & (0x1fe << j)) != (0x0fc << j)) /* flag received */ \
630 goto enditer##j; \
631 if (state) \
632 do_rxpacket(dev); \
633 bc->hdlcrx.bufcnt = 0; \
634 bc->hdlcrx.bufptr = bc->hdlcrx.buf; \
635 state = 1; \
636 numbits = 7-j; \
637 goto enditer##j; \
638 stuff##j: \
639 numbits--; \
640 bitbuf = (bitbuf & ((~0xff) << j)) | ((bitbuf & ~((~0xff) << j)) << 1); \
641 goto enditer##j; \
642})
643
644static int receive(struct net_device *dev, int cnt) 581static int receive(struct net_device *dev, int cnt)
645{ 582{
646 struct baycom_state *bc = netdev_priv(dev); 583 struct baycom_state *bc = netdev_priv(dev);
@@ -649,6 +586,7 @@ static int receive(struct net_device *dev, int cnt)
649 unsigned char tmp[128]; 586 unsigned char tmp[128];
650 unsigned char *cp; 587 unsigned char *cp;
651 int cnt2, ret = 0; 588 int cnt2, ret = 0;
589 int j;
652 590
653 numbits = bc->hdlcrx.numbits; 591 numbits = bc->hdlcrx.numbits;
654 state = bc->hdlcrx.state; 592 state = bc->hdlcrx.state;
@@ -669,24 +607,32 @@ static int receive(struct net_device *dev, int cnt)
669 bitbuf |= (*cp) << 8; 607 bitbuf |= (*cp) << 8;
670 numbits += 8; 608 numbits += 8;
671 notbitstream = ~bitstream; 609 notbitstream = ~bitstream;
672 DECODEITERA(0); 610 for (j = 0; j < 8; j++) {
673 DECODEITERA(1); 611
674 DECODEITERA(2); 612 /* flag or abort */
675 DECODEITERA(3); 613 if (unlikely(!(notbitstream & (0x0fc << j)))) {
676 DECODEITERA(4); 614
677 DECODEITERA(5); 615 /* abort received */
678 DECODEITERA(6); 616 if (!(notbitstream & (0x1fc << j)))
679 DECODEITERA(7); 617 state = 0;
680 goto enddec; 618
681 DECODEITERB(0); 619 /* not flag received */
682 DECODEITERB(1); 620 else if (!(bitstream & (0x1fe << j)) != (0x0fc << j)) {
683 DECODEITERB(2); 621 if (state)
684 DECODEITERB(3); 622 do_rxpacket(dev);
685 DECODEITERB(4); 623 bc->hdlcrx.bufcnt = 0;
686 DECODEITERB(5); 624 bc->hdlcrx.bufptr = bc->hdlcrx.buf;
687 DECODEITERB(6); 625 state = 1;
688 DECODEITERB(7); 626 numbits = 7-j;
689 enddec: 627 }
628 }
629
630 /* stuffed bit */
631 else if (unlikely((bitstream & (0x1f8 << j)) == (0xf8 << j))) {
632 numbits--;
633 bitbuf = (bitbuf & ((~0xff) << j)) | ((bitbuf & ~((~0xff) << j)) << 1);
634 }
635 }
690 while (state && numbits >= 8) { 636 while (state && numbits >= 8) {
691 if (bc->hdlcrx.bufcnt >= TXBUFFER_SIZE) { 637 if (bc->hdlcrx.bufcnt >= TXBUFFER_SIZE) {
692 state = 0; 638 state = 0;
diff --git a/drivers/net/hamradio/mkiss.c b/drivers/net/hamradio/mkiss.c
index 62790511098f..3035422f5ad8 100644
--- a/drivers/net/hamradio/mkiss.c
+++ b/drivers/net/hamradio/mkiss.c
@@ -934,7 +934,7 @@ static void __exit mkiss_exit_driver(void)
934 kfree(ax25_ctrls); 934 kfree(ax25_ctrls);
935 ax25_ctrls = NULL; 935 ax25_ctrls = NULL;
936 936
937 if ((i = tty_register_ldisc(N_AX25, NULL))) 937 if ((i = tty_unregister_ldisc(N_AX25)))
938 printk(KERN_ERR "mkiss: can't unregister line discipline (err = %d)\n", i); 938 printk(KERN_ERR "mkiss: can't unregister line discipline (err = %d)\n", i);
939} 939}
940 940
diff --git a/drivers/net/ibm_emac/ibm_emac_core.c b/drivers/net/ibm_emac/ibm_emac_core.c
index ab44358ddbfc..6482d994d489 100644
--- a/drivers/net/ibm_emac/ibm_emac_core.c
+++ b/drivers/net/ibm_emac/ibm_emac_core.c
@@ -1595,7 +1595,7 @@ static struct ethtool_ops emac_ethtool_ops = {
1595static int emac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1595static int emac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1596{ 1596{
1597 struct ocp_enet_private *fep = dev->priv; 1597 struct ocp_enet_private *fep = dev->priv;
1598 uint *data = (uint *) & rq->ifr_ifru; 1598 uint16_t *data = (uint16_t *) & rq->ifr_ifru;
1599 1599
1600 switch (cmd) { 1600 switch (cmd) {
1601 case SIOCGMIIPHY: 1601 case SIOCGMIIPHY:
diff --git a/drivers/net/irda/Kconfig b/drivers/net/irda/Kconfig
index 1c553d7efdd9..ca5914091d3a 100644
--- a/drivers/net/irda/Kconfig
+++ b/drivers/net/irda/Kconfig
@@ -389,7 +389,7 @@ config VIA_FIR
389 help 389 help
390 Say Y here if you want to build support for the VIA VT8231 390 Say Y here if you want to build support for the VIA VT8231
391 and VIA VT1211 IrDA controllers, found on the motherboards using 391 and VIA VT1211 IrDA controllers, found on the motherboards using
392 those those VIA chipsets. To use this controller, you will need 392 those VIA chipsets. To use this controller, you will need
393 to plug a specific 5 pins FIR IrDA dongle in the specific 393 to plug a specific 5 pins FIR IrDA dongle in the specific
394 motherboard connector. The driver provides support for SIR, MIR 394 motherboard connector. The driver provides support for SIR, MIR
395 and FIR (4Mbps) speeds. 395 and FIR (4Mbps) speeds.
diff --git a/drivers/net/irda/irtty-sir.c b/drivers/net/irda/irtty-sir.c
index 7d23aa375908..b8d112348ba4 100644
--- a/drivers/net/irda/irtty-sir.c
+++ b/drivers/net/irda/irtty-sir.c
@@ -626,7 +626,7 @@ static void __exit irtty_sir_cleanup(void)
626{ 626{
627 int err; 627 int err;
628 628
629 if ((err = tty_register_ldisc(N_IRDA, NULL))) { 629 if ((err = tty_unregister_ldisc(N_IRDA))) {
630 IRDA_ERROR("%s(), can't unregister line discipline (err = %d)\n", 630 IRDA_ERROR("%s(), can't unregister line discipline (err = %d)\n",
631 __FUNCTION__, err); 631 __FUNCTION__, err);
632 } 632 }
diff --git a/drivers/net/irda/sir_kthread.c b/drivers/net/irda/sir_kthread.c
index 18cea1099530..c65054364bca 100644
--- a/drivers/net/irda/sir_kthread.c
+++ b/drivers/net/irda/sir_kthread.c
@@ -135,8 +135,7 @@ static int irda_thread(void *startup)
135 remove_wait_queue(&irda_rq_queue.kick, &wait); 135 remove_wait_queue(&irda_rq_queue.kick, &wait);
136 136
137 /* make swsusp happy with our thread */ 137 /* make swsusp happy with our thread */
138 if (current->flags & PF_FREEZE) 138 try_to_freeze();
139 refrigerator(PF_FREEZE);
140 139
141 run_irda_queue(); 140 run_irda_queue();
142 } 141 }
diff --git a/drivers/net/irda/stir4200.c b/drivers/net/irda/stir4200.c
index 66f488c13717..15f207323d97 100644
--- a/drivers/net/irda/stir4200.c
+++ b/drivers/net/irda/stir4200.c
@@ -763,7 +763,7 @@ static int stir_transmit_thread(void *arg)
763 { 763 {
764#ifdef CONFIG_PM 764#ifdef CONFIG_PM
765 /* if suspending, then power off and wait */ 765 /* if suspending, then power off and wait */
766 if (unlikely(current->flags & PF_FREEZE)) { 766 if (unlikely(freezing(current))) {
767 if (stir->receiving) 767 if (stir->receiving)
768 receive_stop(stir); 768 receive_stop(stir);
769 else 769 else
@@ -771,7 +771,7 @@ static int stir_transmit_thread(void *arg)
771 771
772 write_reg(stir, REG_CTRL1, CTRL1_TXPWD|CTRL1_RXPWD); 772 write_reg(stir, REG_CTRL1, CTRL1_TXPWD|CTRL1_RXPWD);
773 773
774 refrigerator(PF_FREEZE); 774 refrigerator();
775 775
776 if (change_speed(stir, stir->speed)) 776 if (change_speed(stir, stir->speed))
777 break; 777 break;
diff --git a/drivers/net/iseries_veth.c b/drivers/net/iseries_veth.c
index 855f8b2cf13b..55af32e9bf08 100644
--- a/drivers/net/iseries_veth.c
+++ b/drivers/net/iseries_veth.c
@@ -802,13 +802,14 @@ static void veth_tx_timeout(struct net_device *dev)
802 802
803 spin_lock_irqsave(&port->pending_gate, flags); 803 spin_lock_irqsave(&port->pending_gate, flags);
804 804
805 if (!port->pending_lpmask) {
806 spin_unlock_irqrestore(&port->pending_gate, flags);
807 return;
808 }
809
805 printk(KERN_WARNING "%s: Tx timeout! Resetting lp connections: %08x\n", 810 printk(KERN_WARNING "%s: Tx timeout! Resetting lp connections: %08x\n",
806 dev->name, port->pending_lpmask); 811 dev->name, port->pending_lpmask);
807 812
808 /* If we've timed out the queue must be stopped, which should
809 * only ever happen when there is a pending packet. */
810 WARN_ON(! port->pending_lpmask);
811
812 for (i = 0; i < HVMAXARCHITECTEDLPS; i++) { 813 for (i = 0; i < HVMAXARCHITECTEDLPS; i++) {
813 struct veth_lpar_connection *cnx = veth_cnx[i]; 814 struct veth_lpar_connection *cnx = veth_cnx[i];
814 815
@@ -924,7 +925,7 @@ static int veth_transmit_to_one(struct sk_buff *skb, HvLpIndex rlp,
924 925
925 spin_lock_irqsave(&cnx->lock, flags); 926 spin_lock_irqsave(&cnx->lock, flags);
926 927
927 if (! cnx->state & VETH_STATE_READY) 928 if (! (cnx->state & VETH_STATE_READY))
928 goto drop; 929 goto drop;
929 930
930 if ((skb->len - 14) > VETH_MAX_MTU) 931 if ((skb->len - 14) > VETH_MAX_MTU)
@@ -1023,6 +1024,8 @@ static int veth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1023 1024
1024 lpmask = veth_transmit_to_many(skb, lpmask, dev); 1025 lpmask = veth_transmit_to_many(skb, lpmask, dev);
1025 1026
1027 dev->trans_start = jiffies;
1028
1026 if (! lpmask) { 1029 if (! lpmask) {
1027 dev_kfree_skb(skb); 1030 dev_kfree_skb(skb);
1028 } else { 1031 } else {
@@ -1262,13 +1265,18 @@ static void veth_receive(struct veth_lpar_connection *cnx,
1262 1265
1263 vlan = skb->data[9]; 1266 vlan = skb->data[9];
1264 dev = veth_dev[vlan]; 1267 dev = veth_dev[vlan];
1265 if (! dev) 1268 if (! dev) {
1266 /* Some earlier versions of the driver sent 1269 /*
1267 broadcasts down all connections, even to 1270 * Some earlier versions of the driver sent
1268 lpars that weren't on the relevant vlan. 1271 * broadcasts down all connections, even to lpars
1269 So ignore packets belonging to a vlan we're 1272 * that weren't on the relevant vlan. So ignore
1270 not on. */ 1273 * packets belonging to a vlan we're not on.
1274 * We can also be here if we receive packets while
1275 * the driver is going down, because then dev is NULL.
1276 */
1277 dev_kfree_skb_irq(skb);
1271 continue; 1278 continue;
1279 }
1272 1280
1273 port = (struct veth_port *)dev->priv; 1281 port = (struct veth_port *)dev->priv;
1274 dest = *((u64 *) skb->data) & 0xFFFFFFFFFFFF0000; 1282 dest = *((u64 *) skb->data) & 0xFFFFFFFFFFFF0000;
@@ -1381,18 +1389,25 @@ void __exit veth_module_cleanup(void)
1381{ 1389{
1382 int i; 1390 int i;
1383 1391
1384 vio_unregister_driver(&veth_driver); 1392 /* Stop the queues first to stop any new packets being sent. */
1393 for (i = 0; i < HVMAXARCHITECTEDVIRTUALLANS; i++)
1394 if (veth_dev[i])
1395 netif_stop_queue(veth_dev[i]);
1385 1396
1397 /* Stop the connections before we unregister the driver. This
1398 * ensures there's no skbs lying around holding the device open. */
1386 for (i = 0; i < HVMAXARCHITECTEDLPS; ++i) 1399 for (i = 0; i < HVMAXARCHITECTEDLPS; ++i)
1387 veth_stop_connection(i); 1400 veth_stop_connection(i);
1388 1401
1389 HvLpEvent_unregisterHandler(HvLpEvent_Type_VirtualLan); 1402 HvLpEvent_unregisterHandler(HvLpEvent_Type_VirtualLan);
1390 1403
1391 /* Hypervisor callbacks may have scheduled more work while we 1404 /* Hypervisor callbacks may have scheduled more work while we
1392 * were destroying connections. Now that we've disconnected from 1405 * were stoping connections. Now that we've disconnected from
1393 * the hypervisor make sure everything's finished. */ 1406 * the hypervisor make sure everything's finished. */
1394 flush_scheduled_work(); 1407 flush_scheduled_work();
1395 1408
1409 vio_unregister_driver(&veth_driver);
1410
1396 for (i = 0; i < HVMAXARCHITECTEDLPS; ++i) 1411 for (i = 0; i < HVMAXARCHITECTEDLPS; ++i)
1397 veth_destroy_connection(i); 1412 veth_destroy_connection(i);
1398 1413
diff --git a/drivers/net/ixgb/ixgb.h b/drivers/net/ixgb/ixgb.h
index 26c4f15f7fc0..f8d3385c7842 100644
--- a/drivers/net/ixgb/ixgb.h
+++ b/drivers/net/ixgb/ixgb.h
@@ -110,7 +110,7 @@ struct ixgb_adapter;
110#define IXGB_TX_QUEUE_WAKE 16 110#define IXGB_TX_QUEUE_WAKE 16
111 111
112/* How many Rx Buffers do we bundle into one write to the hardware ? */ 112/* How many Rx Buffers do we bundle into one write to the hardware ? */
113#define IXGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 113#define IXGB_RX_BUFFER_WRITE 4 /* Must be power of 2 */
114 114
115/* only works for sizes that are powers of 2 */ 115/* only works for sizes that are powers of 2 */
116#define IXGB_ROUNDUP(i, size) ((i) = (((i) + (size) - 1) & ~((size) - 1))) 116#define IXGB_ROUNDUP(i, size) ((i) = (((i) + (size) - 1) & ~((size) - 1)))
diff --git a/drivers/net/ixgb/ixgb_ee.c b/drivers/net/ixgb/ixgb_ee.c
index 653e99f919ce..3aae110c5560 100644
--- a/drivers/net/ixgb/ixgb_ee.c
+++ b/drivers/net/ixgb/ixgb_ee.c
@@ -411,7 +411,7 @@ ixgb_write_eeprom(struct ixgb_hw *hw, uint16_t offset, uint16_t data)
411 ixgb_cleanup_eeprom(hw); 411 ixgb_cleanup_eeprom(hw);
412 412
413 /* clear the init_ctrl_reg_1 to signify that the cache is invalidated */ 413 /* clear the init_ctrl_reg_1 to signify that the cache is invalidated */
414 ee_map->init_ctrl_reg_1 = EEPROM_ICW1_SIGNATURE_CLEAR; 414 ee_map->init_ctrl_reg_1 = le16_to_cpu(EEPROM_ICW1_SIGNATURE_CLEAR);
415 415
416 return; 416 return;
417} 417}
@@ -483,7 +483,7 @@ ixgb_get_eeprom_data(struct ixgb_hw *hw)
483 DEBUGOUT("ixgb_ee: Checksum invalid.\n"); 483 DEBUGOUT("ixgb_ee: Checksum invalid.\n");
484 /* clear the init_ctrl_reg_1 to signify that the cache is 484 /* clear the init_ctrl_reg_1 to signify that the cache is
485 * invalidated */ 485 * invalidated */
486 ee_map->init_ctrl_reg_1 = EEPROM_ICW1_SIGNATURE_CLEAR; 486 ee_map->init_ctrl_reg_1 = le16_to_cpu(EEPROM_ICW1_SIGNATURE_CLEAR);
487 return (FALSE); 487 return (FALSE);
488 } 488 }
489 489
@@ -579,7 +579,7 @@ ixgb_get_ee_compatibility(struct ixgb_hw *hw)
579 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; 579 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
580 580
581 if(ixgb_check_and_get_eeprom_data(hw) == TRUE) 581 if(ixgb_check_and_get_eeprom_data(hw) == TRUE)
582 return(ee_map->compatibility); 582 return (le16_to_cpu(ee_map->compatibility));
583 583
584 return(0); 584 return(0);
585} 585}
@@ -616,7 +616,7 @@ ixgb_get_ee_init_ctrl_reg_1(struct ixgb_hw *hw)
616 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; 616 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
617 617
618 if(ixgb_check_and_get_eeprom_data(hw) == TRUE) 618 if(ixgb_check_and_get_eeprom_data(hw) == TRUE)
619 return(ee_map->init_ctrl_reg_1); 619 return (le16_to_cpu(ee_map->init_ctrl_reg_1));
620 620
621 return(0); 621 return(0);
622} 622}
@@ -635,7 +635,7 @@ ixgb_get_ee_init_ctrl_reg_2(struct ixgb_hw *hw)
635 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; 635 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
636 636
637 if(ixgb_check_and_get_eeprom_data(hw) == TRUE) 637 if(ixgb_check_and_get_eeprom_data(hw) == TRUE)
638 return(ee_map->init_ctrl_reg_2); 638 return (le16_to_cpu(ee_map->init_ctrl_reg_2));
639 639
640 return(0); 640 return(0);
641} 641}
@@ -654,7 +654,7 @@ ixgb_get_ee_subsystem_id(struct ixgb_hw *hw)
654 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; 654 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
655 655
656 if(ixgb_check_and_get_eeprom_data(hw) == TRUE) 656 if(ixgb_check_and_get_eeprom_data(hw) == TRUE)
657 return(ee_map->subsystem_id); 657 return (le16_to_cpu(ee_map->subsystem_id));
658 658
659 return(0); 659 return(0);
660} 660}
@@ -673,7 +673,7 @@ ixgb_get_ee_subvendor_id(struct ixgb_hw *hw)
673 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; 673 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
674 674
675 if(ixgb_check_and_get_eeprom_data(hw) == TRUE) 675 if(ixgb_check_and_get_eeprom_data(hw) == TRUE)
676 return(ee_map->subvendor_id); 676 return (le16_to_cpu(ee_map->subvendor_id));
677 677
678 return(0); 678 return(0);
679} 679}
@@ -692,7 +692,7 @@ ixgb_get_ee_device_id(struct ixgb_hw *hw)
692 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; 692 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
693 693
694 if(ixgb_check_and_get_eeprom_data(hw) == TRUE) 694 if(ixgb_check_and_get_eeprom_data(hw) == TRUE)
695 return(ee_map->device_id); 695 return (le16_to_cpu(ee_map->device_id));
696 696
697 return(0); 697 return(0);
698} 698}
@@ -711,7 +711,7 @@ ixgb_get_ee_vendor_id(struct ixgb_hw *hw)
711 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; 711 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
712 712
713 if(ixgb_check_and_get_eeprom_data(hw) == TRUE) 713 if(ixgb_check_and_get_eeprom_data(hw) == TRUE)
714 return(ee_map->vendor_id); 714 return (le16_to_cpu(ee_map->vendor_id));
715 715
716 return(0); 716 return(0);
717} 717}
@@ -730,7 +730,7 @@ ixgb_get_ee_swdpins_reg(struct ixgb_hw *hw)
730 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; 730 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
731 731
732 if(ixgb_check_and_get_eeprom_data(hw) == TRUE) 732 if(ixgb_check_and_get_eeprom_data(hw) == TRUE)
733 return(ee_map->swdpins_reg); 733 return (le16_to_cpu(ee_map->swdpins_reg));
734 734
735 return(0); 735 return(0);
736} 736}
@@ -749,7 +749,7 @@ ixgb_get_ee_d3_power(struct ixgb_hw *hw)
749 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; 749 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
750 750
751 if(ixgb_check_and_get_eeprom_data(hw) == TRUE) 751 if(ixgb_check_and_get_eeprom_data(hw) == TRUE)
752 return(ee_map->d3_power); 752 return (le16_to_cpu(ee_map->d3_power));
753 753
754 return(0); 754 return(0);
755} 755}
@@ -768,7 +768,7 @@ ixgb_get_ee_d0_power(struct ixgb_hw *hw)
768 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; 768 struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
769 769
770 if(ixgb_check_and_get_eeprom_data(hw) == TRUE) 770 if(ixgb_check_and_get_eeprom_data(hw) == TRUE)
771 return(ee_map->d0_power); 771 return (le16_to_cpu(ee_map->d0_power));
772 772
773 return(0); 773 return(0);
774} 774}
diff --git a/drivers/net/ixgb/ixgb_ethtool.c b/drivers/net/ixgb/ixgb_ethtool.c
index aea10e8aaa72..3fa113854eeb 100644
--- a/drivers/net/ixgb/ixgb_ethtool.c
+++ b/drivers/net/ixgb/ixgb_ethtool.c
@@ -252,7 +252,9 @@ ixgb_get_regs(struct net_device *netdev,
252 uint32_t *reg_start = reg; 252 uint32_t *reg_start = reg;
253 uint8_t i; 253 uint8_t i;
254 254
255 regs->version = (adapter->hw.device_id << 16) | adapter->hw.subsystem_id; 255 /* the 1 (one) below indicates an attempt at versioning, if the
256 * interface in ethtool or the driver this 1 should be incremented */
257 regs->version = (1<<24) | hw->revision_id << 16 | hw->device_id;
256 258
257 /* General Registers */ 259 /* General Registers */
258 *reg++ = IXGB_READ_REG(hw, CTRL0); /* 0 */ 260 *reg++ = IXGB_READ_REG(hw, CTRL0); /* 0 */
diff --git a/drivers/net/ixgb/ixgb_main.c b/drivers/net/ixgb/ixgb_main.c
index a6af9d9e3408..097b90ccf575 100644
--- a/drivers/net/ixgb/ixgb_main.c
+++ b/drivers/net/ixgb/ixgb_main.c
@@ -47,7 +47,8 @@ char ixgb_driver_string[] = "Intel(R) PRO/10GbE Network Driver";
47#else 47#else
48#define DRIVERNAPI "-NAPI" 48#define DRIVERNAPI "-NAPI"
49#endif 49#endif
50#define DRV_VERSION "1.0.90-k2"DRIVERNAPI 50
51#define DRV_VERSION "1.0.95-k2"DRIVERNAPI
51char ixgb_driver_version[] = DRV_VERSION; 52char ixgb_driver_version[] = DRV_VERSION;
52char ixgb_copyright[] = "Copyright (c) 1999-2005 Intel Corporation."; 53char ixgb_copyright[] = "Copyright (c) 1999-2005 Intel Corporation.";
53 54
@@ -104,6 +105,7 @@ static int ixgb_change_mtu(struct net_device *netdev, int new_mtu);
104static int ixgb_set_mac(struct net_device *netdev, void *p); 105static int ixgb_set_mac(struct net_device *netdev, void *p);
105static irqreturn_t ixgb_intr(int irq, void *data, struct pt_regs *regs); 106static irqreturn_t ixgb_intr(int irq, void *data, struct pt_regs *regs);
106static boolean_t ixgb_clean_tx_irq(struct ixgb_adapter *adapter); 107static boolean_t ixgb_clean_tx_irq(struct ixgb_adapter *adapter);
108
107#ifdef CONFIG_IXGB_NAPI 109#ifdef CONFIG_IXGB_NAPI
108static int ixgb_clean(struct net_device *netdev, int *budget); 110static int ixgb_clean(struct net_device *netdev, int *budget);
109static boolean_t ixgb_clean_rx_irq(struct ixgb_adapter *adapter, 111static boolean_t ixgb_clean_rx_irq(struct ixgb_adapter *adapter,
@@ -121,33 +123,20 @@ static void ixgb_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
121static void ixgb_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid); 123static void ixgb_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
122static void ixgb_restore_vlan(struct ixgb_adapter *adapter); 124static void ixgb_restore_vlan(struct ixgb_adapter *adapter);
123 125
124static int ixgb_notify_reboot(struct notifier_block *, unsigned long event,
125 void *ptr);
126static int ixgb_suspend(struct pci_dev *pdev, uint32_t state);
127
128#ifdef CONFIG_NET_POLL_CONTROLLER 126#ifdef CONFIG_NET_POLL_CONTROLLER
129/* for netdump / net console */ 127/* for netdump / net console */
130static void ixgb_netpoll(struct net_device *dev); 128static void ixgb_netpoll(struct net_device *dev);
131#endif 129#endif
132 130
133struct notifier_block ixgb_notifier_reboot = {
134 .notifier_call = ixgb_notify_reboot,
135 .next = NULL,
136 .priority = 0
137};
138
139/* Exported from other modules */ 131/* Exported from other modules */
140 132
141extern void ixgb_check_options(struct ixgb_adapter *adapter); 133extern void ixgb_check_options(struct ixgb_adapter *adapter);
142 134
143static struct pci_driver ixgb_driver = { 135static struct pci_driver ixgb_driver = {
144 .name = ixgb_driver_name, 136 .name = ixgb_driver_name,
145 .id_table = ixgb_pci_tbl, 137 .id_table = ixgb_pci_tbl,
146 .probe = ixgb_probe, 138 .probe = ixgb_probe,
147 .remove = __devexit_p(ixgb_remove), 139 .remove = __devexit_p(ixgb_remove),
148 /* Power Managment Hooks */
149 .suspend = NULL,
150 .resume = NULL
151}; 140};
152 141
153MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); 142MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
@@ -171,17 +160,12 @@ MODULE_VERSION(DRV_VERSION);
171static int __init 160static int __init
172ixgb_init_module(void) 161ixgb_init_module(void)
173{ 162{
174 int ret;
175 printk(KERN_INFO "%s - version %s\n", 163 printk(KERN_INFO "%s - version %s\n",
176 ixgb_driver_string, ixgb_driver_version); 164 ixgb_driver_string, ixgb_driver_version);
177 165
178 printk(KERN_INFO "%s\n", ixgb_copyright); 166 printk(KERN_INFO "%s\n", ixgb_copyright);
179 167
180 ret = pci_module_init(&ixgb_driver); 168 return pci_module_init(&ixgb_driver);
181 if(ret >= 0) {
182 register_reboot_notifier(&ixgb_notifier_reboot);
183 }
184 return ret;
185} 169}
186 170
187module_init(ixgb_init_module); 171module_init(ixgb_init_module);
@@ -196,7 +180,6 @@ module_init(ixgb_init_module);
196static void __exit 180static void __exit
197ixgb_exit_module(void) 181ixgb_exit_module(void)
198{ 182{
199 unregister_reboot_notifier(&ixgb_notifier_reboot);
200 pci_unregister_driver(&ixgb_driver); 183 pci_unregister_driver(&ixgb_driver);
201} 184}
202 185
@@ -226,8 +209,8 @@ ixgb_irq_enable(struct ixgb_adapter *adapter)
226{ 209{
227 if(atomic_dec_and_test(&adapter->irq_sem)) { 210 if(atomic_dec_and_test(&adapter->irq_sem)) {
228 IXGB_WRITE_REG(&adapter->hw, IMS, 211 IXGB_WRITE_REG(&adapter->hw, IMS,
229 IXGB_INT_RXT0 | IXGB_INT_RXDMT0 | IXGB_INT_TXDW | 212 IXGB_INT_RXT0 | IXGB_INT_RXDMT0 | IXGB_INT_TXDW |
230 IXGB_INT_RXO | IXGB_INT_LSC); 213 IXGB_INT_LSC);
231 IXGB_WRITE_FLUSH(&adapter->hw); 214 IXGB_WRITE_FLUSH(&adapter->hw);
232 } 215 }
233} 216}
@@ -1211,10 +1194,10 @@ ixgb_tso(struct ixgb_adapter *adapter, struct sk_buff *skb)
1211 | IXGB_CONTEXT_DESC_CMD_TSE 1194 | IXGB_CONTEXT_DESC_CMD_TSE
1212 | IXGB_CONTEXT_DESC_CMD_IP 1195 | IXGB_CONTEXT_DESC_CMD_IP
1213 | IXGB_CONTEXT_DESC_CMD_TCP 1196 | IXGB_CONTEXT_DESC_CMD_TCP
1214 | IXGB_CONTEXT_DESC_CMD_RS
1215 | IXGB_CONTEXT_DESC_CMD_IDE 1197 | IXGB_CONTEXT_DESC_CMD_IDE
1216 | (skb->len - (hdr_len))); 1198 | (skb->len - (hdr_len)));
1217 1199
1200
1218 if(++i == adapter->tx_ring.count) i = 0; 1201 if(++i == adapter->tx_ring.count) i = 0;
1219 adapter->tx_ring.next_to_use = i; 1202 adapter->tx_ring.next_to_use = i;
1220 1203
@@ -1249,8 +1232,7 @@ ixgb_tx_csum(struct ixgb_adapter *adapter, struct sk_buff *skb)
1249 context_desc->mss = 0; 1232 context_desc->mss = 0;
1250 context_desc->cmd_type_len = 1233 context_desc->cmd_type_len =
1251 cpu_to_le32(IXGB_CONTEXT_DESC_TYPE 1234 cpu_to_le32(IXGB_CONTEXT_DESC_TYPE
1252 | IXGB_TX_DESC_CMD_RS 1235 | IXGB_TX_DESC_CMD_IDE);
1253 | IXGB_TX_DESC_CMD_IDE);
1254 1236
1255 if(++i == adapter->tx_ring.count) i = 0; 1237 if(++i == adapter->tx_ring.count) i = 0;
1256 adapter->tx_ring.next_to_use = i; 1238 adapter->tx_ring.next_to_use = i;
@@ -1275,6 +1257,7 @@ ixgb_tx_map(struct ixgb_adapter *adapter, struct sk_buff *skb,
1275 1257
1276 unsigned int nr_frags = skb_shinfo(skb)->nr_frags; 1258 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
1277 unsigned int f; 1259 unsigned int f;
1260
1278 len -= skb->data_len; 1261 len -= skb->data_len;
1279 1262
1280 i = tx_ring->next_to_use; 1263 i = tx_ring->next_to_use;
@@ -1528,14 +1511,33 @@ ixgb_change_mtu(struct net_device *netdev, int new_mtu)
1528void 1511void
1529ixgb_update_stats(struct ixgb_adapter *adapter) 1512ixgb_update_stats(struct ixgb_adapter *adapter)
1530{ 1513{
1514 struct net_device *netdev = adapter->netdev;
1515
1516 if((netdev->flags & IFF_PROMISC) || (netdev->flags & IFF_ALLMULTI) ||
1517 (netdev->mc_count > IXGB_MAX_NUM_MULTICAST_ADDRESSES)) {
1518 u64 multi = IXGB_READ_REG(&adapter->hw, MPRCL);
1519 u32 bcast_l = IXGB_READ_REG(&adapter->hw, BPRCL);
1520 u32 bcast_h = IXGB_READ_REG(&adapter->hw, BPRCH);
1521 u64 bcast = ((u64)bcast_h << 32) | bcast_l;
1522
1523 multi |= ((u64)IXGB_READ_REG(&adapter->hw, MPRCH) << 32);
1524 /* fix up multicast stats by removing broadcasts */
1525 multi -= bcast;
1526
1527 adapter->stats.mprcl += (multi & 0xFFFFFFFF);
1528 adapter->stats.mprch += (multi >> 32);
1529 adapter->stats.bprcl += bcast_l;
1530 adapter->stats.bprch += bcast_h;
1531 } else {
1532 adapter->stats.mprcl += IXGB_READ_REG(&adapter->hw, MPRCL);
1533 adapter->stats.mprch += IXGB_READ_REG(&adapter->hw, MPRCH);
1534 adapter->stats.bprcl += IXGB_READ_REG(&adapter->hw, BPRCL);
1535 adapter->stats.bprch += IXGB_READ_REG(&adapter->hw, BPRCH);
1536 }
1531 adapter->stats.tprl += IXGB_READ_REG(&adapter->hw, TPRL); 1537 adapter->stats.tprl += IXGB_READ_REG(&adapter->hw, TPRL);
1532 adapter->stats.tprh += IXGB_READ_REG(&adapter->hw, TPRH); 1538 adapter->stats.tprh += IXGB_READ_REG(&adapter->hw, TPRH);
1533 adapter->stats.gprcl += IXGB_READ_REG(&adapter->hw, GPRCL); 1539 adapter->stats.gprcl += IXGB_READ_REG(&adapter->hw, GPRCL);
1534 adapter->stats.gprch += IXGB_READ_REG(&adapter->hw, GPRCH); 1540 adapter->stats.gprch += IXGB_READ_REG(&adapter->hw, GPRCH);
1535 adapter->stats.bprcl += IXGB_READ_REG(&adapter->hw, BPRCL);
1536 adapter->stats.bprch += IXGB_READ_REG(&adapter->hw, BPRCH);
1537 adapter->stats.mprcl += IXGB_READ_REG(&adapter->hw, MPRCL);
1538 adapter->stats.mprch += IXGB_READ_REG(&adapter->hw, MPRCH);
1539 adapter->stats.uprcl += IXGB_READ_REG(&adapter->hw, UPRCL); 1541 adapter->stats.uprcl += IXGB_READ_REG(&adapter->hw, UPRCL);
1540 adapter->stats.uprch += IXGB_READ_REG(&adapter->hw, UPRCH); 1542 adapter->stats.uprch += IXGB_READ_REG(&adapter->hw, UPRCH);
1541 adapter->stats.vprcl += IXGB_READ_REG(&adapter->hw, VPRCL); 1543 adapter->stats.vprcl += IXGB_READ_REG(&adapter->hw, VPRCL);
@@ -1825,7 +1827,6 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter)
1825 struct pci_dev *pdev = adapter->pdev; 1827 struct pci_dev *pdev = adapter->pdev;
1826 struct ixgb_rx_desc *rx_desc, *next_rxd; 1828 struct ixgb_rx_desc *rx_desc, *next_rxd;
1827 struct ixgb_buffer *buffer_info, *next_buffer, *next2_buffer; 1829 struct ixgb_buffer *buffer_info, *next_buffer, *next2_buffer;
1828 struct sk_buff *skb, *next_skb;
1829 uint32_t length; 1830 uint32_t length;
1830 unsigned int i, j; 1831 unsigned int i, j;
1831 boolean_t cleaned = FALSE; 1832 boolean_t cleaned = FALSE;
@@ -1835,6 +1836,8 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter)
1835 buffer_info = &rx_ring->buffer_info[i]; 1836 buffer_info = &rx_ring->buffer_info[i];
1836 1837
1837 while(rx_desc->status & IXGB_RX_DESC_STATUS_DD) { 1838 while(rx_desc->status & IXGB_RX_DESC_STATUS_DD) {
1839 struct sk_buff *skb, *next_skb;
1840 u8 status;
1838 1841
1839#ifdef CONFIG_IXGB_NAPI 1842#ifdef CONFIG_IXGB_NAPI
1840 if(*work_done >= work_to_do) 1843 if(*work_done >= work_to_do)
@@ -1842,7 +1845,9 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter)
1842 1845
1843 (*work_done)++; 1846 (*work_done)++;
1844#endif 1847#endif
1848 status = rx_desc->status;
1845 skb = buffer_info->skb; 1849 skb = buffer_info->skb;
1850
1846 prefetch(skb->data); 1851 prefetch(skb->data);
1847 1852
1848 if(++i == rx_ring->count) i = 0; 1853 if(++i == rx_ring->count) i = 0;
@@ -1857,7 +1862,6 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter)
1857 next_skb = next_buffer->skb; 1862 next_skb = next_buffer->skb;
1858 prefetch(next_skb); 1863 prefetch(next_skb);
1859 1864
1860
1861 cleaned = TRUE; 1865 cleaned = TRUE;
1862 1866
1863 pci_unmap_single(pdev, 1867 pci_unmap_single(pdev,
@@ -1867,7 +1871,7 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter)
1867 1871
1868 length = le16_to_cpu(rx_desc->length); 1872 length = le16_to_cpu(rx_desc->length);
1869 1873
1870 if(unlikely(!(rx_desc->status & IXGB_RX_DESC_STATUS_EOP))) { 1874 if(unlikely(!(status & IXGB_RX_DESC_STATUS_EOP))) {
1871 1875
1872 /* All receives must fit into a single buffer */ 1876 /* All receives must fit into a single buffer */
1873 1877
@@ -1875,12 +1879,7 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter)
1875 "length<%x>\n", length); 1879 "length<%x>\n", length);
1876 1880
1877 dev_kfree_skb_irq(skb); 1881 dev_kfree_skb_irq(skb);
1878 rx_desc->status = 0; 1882 goto rxdesc_done;
1879 buffer_info->skb = NULL;
1880
1881 rx_desc = next_rxd;
1882 buffer_info = next_buffer;
1883 continue;
1884 } 1883 }
1885 1884
1886 if (unlikely(rx_desc->errors 1885 if (unlikely(rx_desc->errors
@@ -1889,12 +1888,7 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter)
1889 IXGB_RX_DESC_ERRORS_RXE))) { 1888 IXGB_RX_DESC_ERRORS_RXE))) {
1890 1889
1891 dev_kfree_skb_irq(skb); 1890 dev_kfree_skb_irq(skb);
1892 rx_desc->status = 0; 1891 goto rxdesc_done;
1893 buffer_info->skb = NULL;
1894
1895 rx_desc = next_rxd;
1896 buffer_info = next_buffer;
1897 continue;
1898 } 1892 }
1899 1893
1900 /* Good Receive */ 1894 /* Good Receive */
@@ -1905,7 +1899,7 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter)
1905 1899
1906 skb->protocol = eth_type_trans(skb, netdev); 1900 skb->protocol = eth_type_trans(skb, netdev);
1907#ifdef CONFIG_IXGB_NAPI 1901#ifdef CONFIG_IXGB_NAPI
1908 if(adapter->vlgrp && (rx_desc->status & IXGB_RX_DESC_STATUS_VP)) { 1902 if(adapter->vlgrp && (status & IXGB_RX_DESC_STATUS_VP)) {
1909 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, 1903 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
1910 le16_to_cpu(rx_desc->special) & 1904 le16_to_cpu(rx_desc->special) &
1911 IXGB_RX_DESC_SPECIAL_VLAN_MASK); 1905 IXGB_RX_DESC_SPECIAL_VLAN_MASK);
@@ -1913,7 +1907,7 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter)
1913 netif_receive_skb(skb); 1907 netif_receive_skb(skb);
1914 } 1908 }
1915#else /* CONFIG_IXGB_NAPI */ 1909#else /* CONFIG_IXGB_NAPI */
1916 if(adapter->vlgrp && (rx_desc->status & IXGB_RX_DESC_STATUS_VP)) { 1910 if(adapter->vlgrp && (status & IXGB_RX_DESC_STATUS_VP)) {
1917 vlan_hwaccel_rx(skb, adapter->vlgrp, 1911 vlan_hwaccel_rx(skb, adapter->vlgrp,
1918 le16_to_cpu(rx_desc->special) & 1912 le16_to_cpu(rx_desc->special) &
1919 IXGB_RX_DESC_SPECIAL_VLAN_MASK); 1913 IXGB_RX_DESC_SPECIAL_VLAN_MASK);
@@ -1923,9 +1917,12 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter)
1923#endif /* CONFIG_IXGB_NAPI */ 1917#endif /* CONFIG_IXGB_NAPI */
1924 netdev->last_rx = jiffies; 1918 netdev->last_rx = jiffies;
1925 1919
1920rxdesc_done:
1921 /* clean up descriptor, might be written over by hw */
1926 rx_desc->status = 0; 1922 rx_desc->status = 0;
1927 buffer_info->skb = NULL; 1923 buffer_info->skb = NULL;
1928 1924
1925 /* use prefetched values */
1929 rx_desc = next_rxd; 1926 rx_desc = next_rxd;
1930 buffer_info = next_buffer; 1927 buffer_info = next_buffer;
1931 } 1928 }
@@ -1961,8 +1958,8 @@ ixgb_alloc_rx_buffers(struct ixgb_adapter *adapter)
1961 1958
1962 num_group_tail_writes = IXGB_RX_BUFFER_WRITE; 1959 num_group_tail_writes = IXGB_RX_BUFFER_WRITE;
1963 1960
1964 /* leave one descriptor unused */ 1961 /* leave three descriptors unused */
1965 while(--cleancount > 0) { 1962 while(--cleancount > 2) {
1966 rx_desc = IXGB_RX_DESC(*rx_ring, i); 1963 rx_desc = IXGB_RX_DESC(*rx_ring, i);
1967 1964
1968 skb = dev_alloc_skb(adapter->rx_buffer_len + NET_IP_ALIGN); 1965 skb = dev_alloc_skb(adapter->rx_buffer_len + NET_IP_ALIGN);
@@ -1989,6 +1986,10 @@ ixgb_alloc_rx_buffers(struct ixgb_adapter *adapter)
1989 PCI_DMA_FROMDEVICE); 1986 PCI_DMA_FROMDEVICE);
1990 1987
1991 rx_desc->buff_addr = cpu_to_le64(buffer_info->dma); 1988 rx_desc->buff_addr = cpu_to_le64(buffer_info->dma);
1989 /* guarantee DD bit not set now before h/w gets descriptor
1990 * this is the rest of the workaround for h/w double
1991 * writeback. */
1992 rx_desc->status = 0;
1992 1993
1993 if((i & ~(num_group_tail_writes- 1)) == i) { 1994 if((i & ~(num_group_tail_writes- 1)) == i) {
1994 /* Force memory writes to complete before letting h/w 1995 /* Force memory writes to complete before letting h/w
@@ -2101,54 +2102,6 @@ ixgb_restore_vlan(struct ixgb_adapter *adapter)
2101 } 2102 }
2102} 2103}
2103 2104
2104/**
2105 * ixgb_notify_reboot - handles OS notification of reboot event.
2106 * @param nb notifier block, unused
2107 * @param event Event being passed to driver to act upon
2108 * @param p A pointer to our net device
2109 **/
2110static int
2111ixgb_notify_reboot(struct notifier_block *nb, unsigned long event, void *p)
2112{
2113 struct pci_dev *pdev = NULL;
2114
2115 switch(event) {
2116 case SYS_DOWN:
2117 case SYS_HALT:
2118 case SYS_POWER_OFF:
2119 while ((pdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pdev))) {
2120 if (pci_dev_driver(pdev) == &ixgb_driver)
2121 ixgb_suspend(pdev, 3);
2122 }
2123 }
2124 return NOTIFY_DONE;
2125}
2126
2127/**
2128 * ixgb_suspend - driver suspend function called from notify.
2129 * @param pdev pci driver structure used for passing to
2130 * @param state power state to enter
2131 **/
2132static int
2133ixgb_suspend(struct pci_dev *pdev, uint32_t state)
2134{
2135 struct net_device *netdev = pci_get_drvdata(pdev);
2136 struct ixgb_adapter *adapter = netdev->priv;
2137
2138 netif_device_detach(netdev);
2139
2140 if(netif_running(netdev))
2141 ixgb_down(adapter, TRUE);
2142
2143 pci_save_state(pdev);
2144
2145 state = (state > 0) ? 3 : 0;
2146 pci_set_power_state(pdev, state);
2147 msec_delay(200);
2148
2149 return 0;
2150}
2151
2152#ifdef CONFIG_NET_POLL_CONTROLLER 2105#ifdef CONFIG_NET_POLL_CONTROLLER
2153/* 2106/*
2154 * Polling 'interrupt' - used by things like netconsole to send skbs 2107 * Polling 'interrupt' - used by things like netconsole to send skbs
@@ -2159,6 +2112,7 @@ ixgb_suspend(struct pci_dev *pdev, uint32_t state)
2159static void ixgb_netpoll(struct net_device *dev) 2112static void ixgb_netpoll(struct net_device *dev)
2160{ 2113{
2161 struct ixgb_adapter *adapter = dev->priv; 2114 struct ixgb_adapter *adapter = dev->priv;
2115
2162 disable_irq(adapter->pdev->irq); 2116 disable_irq(adapter->pdev->irq);
2163 ixgb_intr(adapter->pdev->irq, dev, NULL); 2117 ixgb_intr(adapter->pdev->irq, dev, NULL);
2164 enable_irq(adapter->pdev->irq); 2118 enable_irq(adapter->pdev->irq);
diff --git a/drivers/net/ixgb/ixgb_osdep.h b/drivers/net/ixgb/ixgb_osdep.h
index 9eba92891901..dba20481ee80 100644
--- a/drivers/net/ixgb/ixgb_osdep.h
+++ b/drivers/net/ixgb/ixgb_osdep.h
@@ -45,8 +45,7 @@
45 /* Don't mdelay in interrupt context! */ \ 45 /* Don't mdelay in interrupt context! */ \
46 BUG(); \ 46 BUG(); \
47 } else { \ 47 } else { \
48 set_current_state(TASK_UNINTERRUPTIBLE); \ 48 msleep(x); \
49 schedule_timeout((x * HZ)/1000 + 2); \
50 } } while(0) 49 } } while(0)
51#endif 50#endif
52 51
diff --git a/drivers/net/natsemi.c b/drivers/net/natsemi.c
index 223bdadd4c0d..babb59e146ea 100644
--- a/drivers/net/natsemi.c
+++ b/drivers/net/natsemi.c
@@ -2433,9 +2433,9 @@ static void __set_rx_mode(struct net_device *dev)
2433 rx_mode = RxFilterEnable | AcceptBroadcast 2433 rx_mode = RxFilterEnable | AcceptBroadcast
2434 | AcceptMulticast | AcceptMyPhys; 2434 | AcceptMulticast | AcceptMyPhys;
2435 for (i = 0; i < 64; i += 2) { 2435 for (i = 0; i < 64; i += 2) {
2436 writew(HASH_TABLE + i, ioaddr + RxFilterAddr); 2436 writel(HASH_TABLE + i, ioaddr + RxFilterAddr);
2437 writew((mc_filter[i+1]<<8) + mc_filter[i], 2437 writel((mc_filter[i + 1] << 8) + mc_filter[i],
2438 ioaddr + RxFilterData); 2438 ioaddr + RxFilterData);
2439 } 2439 }
2440 } 2440 }
2441 writel(rx_mode, ioaddr + RxFilterAddr); 2441 writel(rx_mode, ioaddr + RxFilterAddr);
diff --git a/drivers/net/ns83820.c b/drivers/net/ns83820.c
index 2fcc181a8624..c336b46bd332 100644
--- a/drivers/net/ns83820.c
+++ b/drivers/net/ns83820.c
@@ -1,4 +1,4 @@
1#define _VERSION "0.20" 1#define VERSION "0.22"
2/* ns83820.c by Benjamin LaHaise with contributions. 2/* ns83820.c by Benjamin LaHaise with contributions.
3 * 3 *
4 * Questions/comments/discussion to linux-ns83820@kvack.org. 4 * Questions/comments/discussion to linux-ns83820@kvack.org.
@@ -63,9 +63,11 @@
63 * - fix missed txok introduced during performance 63 * - fix missed txok introduced during performance
64 * tuning 64 * tuning
65 * 0.20 - fix stupid RFEN thinko. i am such a smurf. 65 * 0.20 - fix stupid RFEN thinko. i am such a smurf.
66 *
67 * 20040828 0.21 - add hardware vlan accleration 66 * 20040828 0.21 - add hardware vlan accleration
68 * by Neil Horman <nhorman@redhat.com> 67 * by Neil Horman <nhorman@redhat.com>
68 * 20050406 0.22 - improved DAC ifdefs from Andi Kleen
69 * - removal of dead code from Adrian Bunk
70 * - fix half duplex collision behaviour
69 * Driver Overview 71 * Driver Overview
70 * =============== 72 * ===============
71 * 73 *
@@ -129,18 +131,6 @@ static int lnksts = 0; /* CFG_LNKSTS bit polarity */
129#undef Dprintk 131#undef Dprintk
130#define Dprintk dprintk 132#define Dprintk dprintk
131 133
132#if defined(CONFIG_HIGHMEM64G) || defined(__ia64__)
133#define USE_64BIT_ADDR "+"
134#endif
135
136#if defined(USE_64BIT_ADDR)
137#define VERSION _VERSION USE_64BIT_ADDR
138#define TRY_DAC 1
139#else
140#define VERSION _VERSION
141#define TRY_DAC 0
142#endif
143
144/* tunables */ 134/* tunables */
145#define RX_BUF_SIZE 1500 /* 8192 */ 135#define RX_BUF_SIZE 1500 /* 8192 */
146#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) 136#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
@@ -386,22 +376,16 @@ static int lnksts = 0; /* CFG_LNKSTS bit polarity */
386#define LINK_DOWN 0x02 376#define LINK_DOWN 0x02
387#define LINK_UP 0x04 377#define LINK_UP 0x04
388 378
389#ifdef USE_64BIT_ADDR 379#define HW_ADDR_LEN sizeof(dma_addr_t)
390#define HW_ADDR_LEN 8
391#define desc_addr_set(desc, addr) \ 380#define desc_addr_set(desc, addr) \
392 do { \ 381 do { \
393 u64 __addr = (addr); \ 382 ((desc)[0] = cpu_to_le32(addr)); \
394 (desc)[0] = cpu_to_le32(__addr); \ 383 if (HW_ADDR_LEN == 8) \
395 (desc)[1] = cpu_to_le32(__addr >> 32); \ 384 (desc)[1] = cpu_to_le32(((u64)addr) >> 32); \
396 } while(0) 385 } while(0)
397#define desc_addr_get(desc) \ 386#define desc_addr_get(desc) \
398 (((u64)le32_to_cpu((desc)[1]) << 32) \ 387 (le32_to_cpu((desc)[0]) | \
399 | le32_to_cpu((desc)[0])) 388 (HW_ADDR_LEN == 8 ? ((dma_addr_t)le32_to_cpu((desc)[1]))<<32 : 0))
400#else
401#define HW_ADDR_LEN 4
402#define desc_addr_set(desc, addr) ((desc)[0] = cpu_to_le32(addr))
403#define desc_addr_get(desc) (le32_to_cpu((desc)[0]))
404#endif
405 389
406#define DESC_LINK 0 390#define DESC_LINK 0
407#define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4) 391#define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4)
@@ -727,11 +711,23 @@ static void fastcall phy_intr(struct net_device *ndev)
727 speed = ((cfg / CFG_SPDSTS0) & 3); 711 speed = ((cfg / CFG_SPDSTS0) & 3);
728 fullduplex = (cfg & CFG_DUPSTS); 712 fullduplex = (cfg & CFG_DUPSTS);
729 713
730 if (fullduplex) 714 if (fullduplex) {
731 new_cfg |= CFG_SB; 715 new_cfg |= CFG_SB;
716 writel(readl(dev->base + TXCFG)
717 | TXCFG_CSI | TXCFG_HBI,
718 dev->base + TXCFG);
719 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
720 dev->base + RXCFG);
721 } else {
722 writel(readl(dev->base + TXCFG)
723 & ~(TXCFG_CSI | TXCFG_HBI),
724 dev->base + TXCFG);
725 writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD),
726 dev->base + RXCFG);
727 }
732 728
733 if ((cfg & CFG_LNKSTS) && 729 if ((cfg & CFG_LNKSTS) &&
734 ((new_cfg ^ dev->CFG_cache) & CFG_MODE_1000)) { 730 ((new_cfg ^ dev->CFG_cache) != 0)) {
735 writel(new_cfg, dev->base + CFG); 731 writel(new_cfg, dev->base + CFG);
736 dev->CFG_cache = new_cfg; 732 dev->CFG_cache = new_cfg;
737 } 733 }
@@ -1189,7 +1185,6 @@ again:
1189 1185
1190 for (;;) { 1186 for (;;) {
1191 volatile u32 *desc = dev->tx_descs + (free_idx * DESC_SIZE); 1187 volatile u32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1192 u32 residue = 0;
1193 1188
1194 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len, 1189 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len,
1195 (unsigned long long)buf); 1190 (unsigned long long)buf);
@@ -1199,17 +1194,11 @@ again:
1199 desc_addr_set(desc + DESC_BUFPTR, buf); 1194 desc_addr_set(desc + DESC_BUFPTR, buf);
1200 desc[DESC_EXTSTS] = cpu_to_le32(extsts); 1195 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
1201 1196
1202 cmdsts = ((nr_frags|residue) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0); 1197 cmdsts = ((nr_frags) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0);
1203 cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN; 1198 cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN;
1204 cmdsts |= len; 1199 cmdsts |= len;
1205 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts); 1200 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
1206 1201
1207 if (residue) {
1208 buf += len;
1209 len = residue;
1210 continue;
1211 }
1212
1213 if (!nr_frags) 1202 if (!nr_frags)
1214 break; 1203 break;
1215 1204
@@ -1841,7 +1830,8 @@ static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_
1841 int using_dac = 0; 1830 int using_dac = 0;
1842 1831
1843 /* See if we can set the dma mask early on; failure is fatal. */ 1832 /* See if we can set the dma mask early on; failure is fatal. */
1844 if (TRY_DAC && !pci_set_dma_mask(pci_dev, 0xffffffffffffffffULL)) { 1833 if (sizeof(dma_addr_t) == 8 &&
1834 !pci_set_dma_mask(pci_dev, 0xffffffffffffffffULL)) {
1845 using_dac = 1; 1835 using_dac = 1;
1846 } else if (!pci_set_dma_mask(pci_dev, 0xffffffff)) { 1836 } else if (!pci_set_dma_mask(pci_dev, 0xffffffff)) {
1847 using_dac = 0; 1837 using_dac = 0;
@@ -1972,9 +1962,8 @@ static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_
1972 /* When compiled with 64 bit addressing, we must always enable 1962 /* When compiled with 64 bit addressing, we must always enable
1973 * the 64 bit descriptor format. 1963 * the 64 bit descriptor format.
1974 */ 1964 */
1975#ifdef USE_64BIT_ADDR 1965 if (sizeof(dma_addr_t) == 8)
1976 dev->CFG_cache |= CFG_M64ADDR; 1966 dev->CFG_cache |= CFG_M64ADDR;
1977#endif
1978 if (using_dac) 1967 if (using_dac)
1979 dev->CFG_cache |= CFG_T64ADDR; 1968 dev->CFG_cache |= CFG_T64ADDR;
1980 1969
diff --git a/drivers/net/pcmcia/3c574_cs.c b/drivers/net/pcmcia/3c574_cs.c
index 41e517114807..c6e8b25f9685 100644
--- a/drivers/net/pcmcia/3c574_cs.c
+++ b/drivers/net/pcmcia/3c574_cs.c
@@ -1274,6 +1274,9 @@ static int el3_close(struct net_device *dev)
1274 spin_lock_irqsave(&lp->window_lock, flags); 1274 spin_lock_irqsave(&lp->window_lock, flags);
1275 update_stats(dev); 1275 update_stats(dev);
1276 spin_unlock_irqrestore(&lp->window_lock, flags); 1276 spin_unlock_irqrestore(&lp->window_lock, flags);
1277
1278 /* force interrupts off */
1279 outw(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
1277 } 1280 }
1278 1281
1279 link->open--; 1282 link->open--;
diff --git a/drivers/net/pcmcia/pcnet_cs.c b/drivers/net/pcmcia/pcnet_cs.c
index b0126304ca08..181b6ed55003 100644
--- a/drivers/net/pcmcia/pcnet_cs.c
+++ b/drivers/net/pcmcia/pcnet_cs.c
@@ -1537,20 +1537,20 @@ static void shmem_get_8390_hdr(struct net_device *dev,
1537static void shmem_block_input(struct net_device *dev, int count, 1537static void shmem_block_input(struct net_device *dev, int count,
1538 struct sk_buff *skb, int ring_offset) 1538 struct sk_buff *skb, int ring_offset)
1539{ 1539{
1540 void __iomem *xfer_start = ei_status.mem + (TX_PAGES<<8) 1540 void __iomem *base = ei_status.mem;
1541 + ring_offset 1541 unsigned long offset = (TX_PAGES<<8) + ring_offset
1542 - (ei_status.rx_start_page << 8); 1542 - (ei_status.rx_start_page << 8);
1543 char *buf = skb->data; 1543 char *buf = skb->data;
1544 1544
1545 if (xfer_start + count > (void __iomem *)ei_status.rmem_end) { 1545 if (offset + count > ei_status.priv) {
1546 /* We must wrap the input move. */ 1546 /* We must wrap the input move. */
1547 int semi_count = (void __iomem *)ei_status.rmem_end - xfer_start; 1547 int semi_count = ei_status.priv - offset;
1548 copyin(buf, xfer_start, semi_count); 1548 copyin(buf, base + offset, semi_count);
1549 buf += semi_count; 1549 buf += semi_count;
1550 xfer_start = ei_status.mem + (TX_PAGES<<8); 1550 offset = TX_PAGES<<8;
1551 count -= semi_count; 1551 count -= semi_count;
1552 } 1552 }
1553 copyin(buf, xfer_start, count); 1553 copyin(buf, base + offset, count);
1554} 1554}
1555 1555
1556/*====================================================================*/ 1556/*====================================================================*/
@@ -1611,8 +1611,9 @@ static int setup_shmem_window(dev_link_t *link, int start_pg,
1611 } 1611 }
1612 1612
1613 ei_status.mem = info->base + offset; 1613 ei_status.mem = info->base + offset;
1614 ei_status.priv = req.Size;
1614 dev->mem_start = (u_long)ei_status.mem; 1615 dev->mem_start = (u_long)ei_status.mem;
1615 dev->mem_end = ei_status.rmem_end = (u_long)info->base + req.Size; 1616 dev->mem_end = dev->mem_start + req.Size;
1616 1617
1617 ei_status.tx_start_page = start_pg; 1618 ei_status.tx_start_page = start_pg;
1618 ei_status.rx_start_page = start_pg + TX_PAGES; 1619 ei_status.rx_start_page = start_pg + TX_PAGES;
diff --git a/drivers/net/pcnet32.c b/drivers/net/pcnet32.c
index 17947e6c8793..13f114876965 100644
--- a/drivers/net/pcnet32.c
+++ b/drivers/net/pcnet32.c
@@ -22,8 +22,8 @@
22 *************************************************************************/ 22 *************************************************************************/
23 23
24#define DRV_NAME "pcnet32" 24#define DRV_NAME "pcnet32"
25#define DRV_VERSION "1.30i" 25#define DRV_VERSION "1.30j"
26#define DRV_RELDATE "06.28.2004" 26#define DRV_RELDATE "29.04.2005"
27#define PFX DRV_NAME ": " 27#define PFX DRV_NAME ": "
28 28
29static const char *version = 29static const char *version =
@@ -256,6 +256,7 @@ static int homepna[MAX_UNITS];
256 * homepna for selecting HomePNA mode for PCNet/Home 79C978. 256 * homepna for selecting HomePNA mode for PCNet/Home 79C978.
257 * v1.30h 24 Jun 2004 Don Fry correctly select auto, speed, duplex in bcr32. 257 * v1.30h 24 Jun 2004 Don Fry correctly select auto, speed, duplex in bcr32.
258 * v1.30i 28 Jun 2004 Don Fry change to use module_param. 258 * v1.30i 28 Jun 2004 Don Fry change to use module_param.
259 * v1.30j 29 Apr 2005 Don Fry fix skb/map leak with loopback test.
259 */ 260 */
260 261
261 262
@@ -395,6 +396,7 @@ static void pcnet32_led_blink_callback(struct net_device *dev);
395static int pcnet32_get_regs_len(struct net_device *dev); 396static int pcnet32_get_regs_len(struct net_device *dev);
396static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs, 397static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
397 void *ptr); 398 void *ptr);
399static void pcnet32_purge_tx_ring(struct net_device *dev);
398 400
399enum pci_flags_bit { 401enum pci_flags_bit {
400 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4, 402 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
@@ -785,6 +787,7 @@ static int pcnet32_loopback_test(struct net_device *dev, uint64_t *data1)
785 } 787 }
786 788
787clean_up: 789clean_up:
790 pcnet32_purge_tx_ring(dev);
788 x = a->read_csr(ioaddr, 15) & 0xFFFF; 791 x = a->read_csr(ioaddr, 15) & 0xFFFF;
789 a->write_csr(ioaddr, 15, (x & ~0x0044)); /* reset bits 6 and 2 */ 792 a->write_csr(ioaddr, 15, (x & ~0x0044)); /* reset bits 6 and 2 */
790 793
diff --git a/drivers/net/ppp_async.c b/drivers/net/ppp_async.c
index 33b9d79b1aad..5e48b9ab3045 100644
--- a/drivers/net/ppp_async.c
+++ b/drivers/net/ppp_async.c
@@ -1025,7 +1025,7 @@ static void async_lcp_peek(struct asyncppp *ap, unsigned char *data,
1025 1025
1026static void __exit ppp_async_cleanup(void) 1026static void __exit ppp_async_cleanup(void)
1027{ 1027{
1028 if (tty_register_ldisc(N_PPP, NULL) != 0) 1028 if (tty_unregister_ldisc(N_PPP) != 0)
1029 printk(KERN_ERR "failed to unregister PPP line discipline\n"); 1029 printk(KERN_ERR "failed to unregister PPP line discipline\n");
1030} 1030}
1031 1031
diff --git a/drivers/net/ppp_generic.c b/drivers/net/ppp_generic.c
index 3b377f6cd4a0..ab726ab43798 100644
--- a/drivers/net/ppp_generic.c
+++ b/drivers/net/ppp_generic.c
@@ -273,7 +273,7 @@ static int ppp_connect_channel(struct channel *pch, int unit);
273static int ppp_disconnect_channel(struct channel *pch); 273static int ppp_disconnect_channel(struct channel *pch);
274static void ppp_destroy_channel(struct channel *pch); 274static void ppp_destroy_channel(struct channel *pch);
275 275
276static struct class_simple *ppp_class; 276static struct class *ppp_class;
277 277
278/* Translates a PPP protocol number to a NP index (NP == network protocol) */ 278/* Translates a PPP protocol number to a NP index (NP == network protocol) */
279static inline int proto_to_npindex(int proto) 279static inline int proto_to_npindex(int proto)
@@ -858,12 +858,12 @@ static int __init ppp_init(void)
858 printk(KERN_INFO "PPP generic driver version " PPP_VERSION "\n"); 858 printk(KERN_INFO "PPP generic driver version " PPP_VERSION "\n");
859 err = register_chrdev(PPP_MAJOR, "ppp", &ppp_device_fops); 859 err = register_chrdev(PPP_MAJOR, "ppp", &ppp_device_fops);
860 if (!err) { 860 if (!err) {
861 ppp_class = class_simple_create(THIS_MODULE, "ppp"); 861 ppp_class = class_create(THIS_MODULE, "ppp");
862 if (IS_ERR(ppp_class)) { 862 if (IS_ERR(ppp_class)) {
863 err = PTR_ERR(ppp_class); 863 err = PTR_ERR(ppp_class);
864 goto out_chrdev; 864 goto out_chrdev;
865 } 865 }
866 class_simple_device_add(ppp_class, MKDEV(PPP_MAJOR, 0), NULL, "ppp"); 866 class_device_create(ppp_class, MKDEV(PPP_MAJOR, 0), NULL, "ppp");
867 err = devfs_mk_cdev(MKDEV(PPP_MAJOR, 0), 867 err = devfs_mk_cdev(MKDEV(PPP_MAJOR, 0),
868 S_IFCHR|S_IRUSR|S_IWUSR, "ppp"); 868 S_IFCHR|S_IRUSR|S_IWUSR, "ppp");
869 if (err) 869 if (err)
@@ -876,8 +876,8 @@ out:
876 return err; 876 return err;
877 877
878out_class: 878out_class:
879 class_simple_device_remove(MKDEV(PPP_MAJOR,0)); 879 class_device_destroy(ppp_class, MKDEV(PPP_MAJOR,0));
880 class_simple_destroy(ppp_class); 880 class_destroy(ppp_class);
881out_chrdev: 881out_chrdev:
882 unregister_chrdev(PPP_MAJOR, "ppp"); 882 unregister_chrdev(PPP_MAJOR, "ppp");
883 goto out; 883 goto out;
@@ -1217,36 +1217,43 @@ ppp_push(struct ppp *ppp)
1217 */ 1217 */
1218static int ppp_mp_explode(struct ppp *ppp, struct sk_buff *skb) 1218static int ppp_mp_explode(struct ppp *ppp, struct sk_buff *skb)
1219{ 1219{
1220 int nch, len, fragsize; 1220 int len, fragsize;
1221 int i, bits, hdrlen, mtu; 1221 int i, bits, hdrlen, mtu;
1222 int flen, fnb; 1222 int flen;
1223 int navail, nfree;
1224 int nbigger;
1223 unsigned char *p, *q; 1225 unsigned char *p, *q;
1224 struct list_head *list; 1226 struct list_head *list;
1225 struct channel *pch; 1227 struct channel *pch;
1226 struct sk_buff *frag; 1228 struct sk_buff *frag;
1227 struct ppp_channel *chan; 1229 struct ppp_channel *chan;
1228 1230
1229 nch = 0; 1231 nfree = 0; /* # channels which have no packet already queued */
1232 navail = 0; /* total # of usable channels (not deregistered) */
1230 hdrlen = (ppp->flags & SC_MP_XSHORTSEQ)? MPHDRLEN_SSN: MPHDRLEN; 1233 hdrlen = (ppp->flags & SC_MP_XSHORTSEQ)? MPHDRLEN_SSN: MPHDRLEN;
1234 i = 0;
1231 list = &ppp->channels; 1235 list = &ppp->channels;
1232 while ((list = list->next) != &ppp->channels) { 1236 while ((list = list->next) != &ppp->channels) {
1233 pch = list_entry(list, struct channel, clist); 1237 pch = list_entry(list, struct channel, clist);
1234 nch += pch->avail = (skb_queue_len(&pch->file.xq) == 0); 1238 navail += pch->avail = (pch->chan != NULL);
1235 /* 1239 if (pch->avail) {
1236 * If a channel hasn't had a fragment yet, it has to get 1240 if (skb_queue_len(&pch->file.xq) == 0
1237 * one before we send any fragments on later channels. 1241 || !pch->had_frag) {
1238 * If it can't take a fragment now, don't give any 1242 pch->avail = 2;
1239 * to subsequent channels. 1243 ++nfree;
1240 */
1241 if (!pch->had_frag && !pch->avail) {
1242 while ((list = list->next) != &ppp->channels) {
1243 pch = list_entry(list, struct channel, clist);
1244 pch->avail = 0;
1245 } 1244 }
1246 break; 1245 if (!pch->had_frag && i < ppp->nxchan)
1246 ppp->nxchan = i;
1247 } 1247 }
1248 ++i;
1248 } 1249 }
1249 if (nch == 0) 1250
1251 /*
1252 * Don't start sending this packet unless at least half of
1253 * the channels are free. This gives much better TCP
1254 * performance if we have a lot of channels.
1255 */
1256 if (nfree == 0 || nfree < navail / 2)
1250 return 0; /* can't take now, leave it in xmit_pending */ 1257 return 0; /* can't take now, leave it in xmit_pending */
1251 1258
1252 /* Do protocol field compression (XXX this should be optional) */ 1259 /* Do protocol field compression (XXX this should be optional) */
@@ -1257,14 +1264,19 @@ static int ppp_mp_explode(struct ppp *ppp, struct sk_buff *skb)
1257 --len; 1264 --len;
1258 } 1265 }
1259 1266
1260 /* decide on fragment size */ 1267 /*
1268 * Decide on fragment size.
1269 * We create a fragment for each free channel regardless of
1270 * how small they are (i.e. even 0 length) in order to minimize
1271 * the time that it will take to detect when a channel drops
1272 * a fragment.
1273 */
1261 fragsize = len; 1274 fragsize = len;
1262 if (nch > 1) { 1275 if (nfree > 1)
1263 int maxch = ROUNDUP(len, MIN_FRAG_SIZE); 1276 fragsize = ROUNDUP(fragsize, nfree);
1264 if (nch > maxch) 1277 /* nbigger channels get fragsize bytes, the rest get fragsize-1,
1265 nch = maxch; 1278 except if nbigger==0, then they all get fragsize. */
1266 fragsize = ROUNDUP(fragsize, nch); 1279 nbigger = len % nfree;
1267 }
1268 1280
1269 /* skip to the channel after the one we last used 1281 /* skip to the channel after the one we last used
1270 and start at that one */ 1282 and start at that one */
@@ -1278,7 +1290,7 @@ static int ppp_mp_explode(struct ppp *ppp, struct sk_buff *skb)
1278 1290
1279 /* create a fragment for each channel */ 1291 /* create a fragment for each channel */
1280 bits = B; 1292 bits = B;
1281 do { 1293 while (nfree > 0 || len > 0) {
1282 list = list->next; 1294 list = list->next;
1283 if (list == &ppp->channels) { 1295 if (list == &ppp->channels) {
1284 i = 0; 1296 i = 0;
@@ -1289,61 +1301,92 @@ static int ppp_mp_explode(struct ppp *ppp, struct sk_buff *skb)
1289 if (!pch->avail) 1301 if (!pch->avail)
1290 continue; 1302 continue;
1291 1303
1304 /*
1305 * Skip this channel if it has a fragment pending already and
1306 * we haven't given a fragment to all of the free channels.
1307 */
1308 if (pch->avail == 1) {
1309 if (nfree > 0)
1310 continue;
1311 } else {
1312 --nfree;
1313 pch->avail = 1;
1314 }
1315
1292 /* check the channel's mtu and whether it is still attached. */ 1316 /* check the channel's mtu and whether it is still attached. */
1293 spin_lock_bh(&pch->downl); 1317 spin_lock_bh(&pch->downl);
1294 if (pch->chan == 0 || (mtu = pch->chan->mtu) < hdrlen) { 1318 if (pch->chan == NULL) {
1295 /* can't use this channel */ 1319 /* can't use this channel, it's being deregistered */
1296 spin_unlock_bh(&pch->downl); 1320 spin_unlock_bh(&pch->downl);
1297 pch->avail = 0; 1321 pch->avail = 0;
1298 if (--nch == 0) 1322 if (--navail == 0)
1299 break; 1323 break;
1300 continue; 1324 continue;
1301 } 1325 }
1302 1326
1303 /* 1327 /*
1304 * We have to create multiple fragments for this channel 1328 * Create a fragment for this channel of
1305 * if fragsize is greater than the channel's mtu. 1329 * min(max(mtu+2-hdrlen, 4), fragsize, len) bytes.
1330 * If mtu+2-hdrlen < 4, that is a ridiculously small
1331 * MTU, so we use mtu = 2 + hdrlen.
1306 */ 1332 */
1307 if (fragsize > len) 1333 if (fragsize > len)
1308 fragsize = len; 1334 fragsize = len;
1309 for (flen = fragsize; flen > 0; flen -= fnb) { 1335 flen = fragsize;
1310 fnb = flen; 1336 mtu = pch->chan->mtu + 2 - hdrlen;
1311 if (fnb > mtu + 2 - hdrlen) 1337 if (mtu < 4)
1312 fnb = mtu + 2 - hdrlen; 1338 mtu = 4;
1313 if (fnb >= len) 1339 if (flen > mtu)
1314 bits |= E; 1340 flen = mtu;
1315 frag = alloc_skb(fnb + hdrlen, GFP_ATOMIC); 1341 if (flen == len && nfree == 0)
1316 if (frag == 0) 1342 bits |= E;
1317 goto noskb; 1343 frag = alloc_skb(flen + hdrlen + (flen == 0), GFP_ATOMIC);
1318 q = skb_put(frag, fnb + hdrlen); 1344 if (frag == 0)
1319 /* make the MP header */ 1345 goto noskb;
1320 q[0] = PPP_MP >> 8; 1346 q = skb_put(frag, flen + hdrlen);
1321 q[1] = PPP_MP; 1347
1322 if (ppp->flags & SC_MP_XSHORTSEQ) { 1348 /* make the MP header */
1323 q[2] = bits + ((ppp->nxseq >> 8) & 0xf); 1349 q[0] = PPP_MP >> 8;
1324 q[3] = ppp->nxseq; 1350 q[1] = PPP_MP;
1325 } else { 1351 if (ppp->flags & SC_MP_XSHORTSEQ) {
1326 q[2] = bits; 1352 q[2] = bits + ((ppp->nxseq >> 8) & 0xf);
1327 q[3] = ppp->nxseq >> 16; 1353 q[3] = ppp->nxseq;
1328 q[4] = ppp->nxseq >> 8; 1354 } else {
1329 q[5] = ppp->nxseq; 1355 q[2] = bits;
1330 } 1356 q[3] = ppp->nxseq >> 16;
1331 1357 q[4] = ppp->nxseq >> 8;
1332 /* copy the data in */ 1358 q[5] = ppp->nxseq;
1333 memcpy(q + hdrlen, p, fnb);
1334
1335 /* try to send it down the channel */
1336 chan = pch->chan;
1337 if (!chan->ops->start_xmit(chan, frag))
1338 skb_queue_tail(&pch->file.xq, frag);
1339 pch->had_frag = 1;
1340 p += fnb;
1341 len -= fnb;
1342 ++ppp->nxseq;
1343 bits = 0;
1344 } 1359 }
1360
1361 /*
1362 * Copy the data in.
1363 * Unfortunately there is a bug in older versions of
1364 * the Linux PPP multilink reconstruction code where it
1365 * drops 0-length fragments. Therefore we make sure the
1366 * fragment has at least one byte of data. Any bytes
1367 * we add in this situation will end up as padding on the
1368 * end of the reconstructed packet.
1369 */
1370 if (flen == 0)
1371 *skb_put(frag, 1) = 0;
1372 else
1373 memcpy(q + hdrlen, p, flen);
1374
1375 /* try to send it down the channel */
1376 chan = pch->chan;
1377 if (skb_queue_len(&pch->file.xq)
1378 || !chan->ops->start_xmit(chan, frag))
1379 skb_queue_tail(&pch->file.xq, frag);
1380 pch->had_frag = 1;
1381 p += flen;
1382 len -= flen;
1383 ++ppp->nxseq;
1384 bits = 0;
1345 spin_unlock_bh(&pch->downl); 1385 spin_unlock_bh(&pch->downl);
1346 } while (len > 0); 1386
1387 if (--nbigger == 0 && fragsize > 0)
1388 --fragsize;
1389 }
1347 ppp->nxchan = i; 1390 ppp->nxchan = i;
1348 1391
1349 return 1; 1392 return 1;
@@ -1422,7 +1465,7 @@ ppp_input(struct ppp_channel *chan, struct sk_buff *skb)
1422 kfree_skb(skb); 1465 kfree_skb(skb);
1423 return; 1466 return;
1424 } 1467 }
1425 1468
1426 proto = PPP_PROTO(skb); 1469 proto = PPP_PROTO(skb);
1427 read_lock_bh(&pch->upl); 1470 read_lock_bh(&pch->upl);
1428 if (pch->ppp == 0 || proto >= 0xc000 || proto == PPP_CCPFRAG) { 1471 if (pch->ppp == 0 || proto >= 0xc000 || proto == PPP_CCPFRAG) {
@@ -1691,7 +1734,7 @@ ppp_receive_mp_frame(struct ppp *ppp, struct sk_buff *skb, struct channel *pch)
1691 struct list_head *l; 1734 struct list_head *l;
1692 int mphdrlen = (ppp->flags & SC_MP_SHORTSEQ)? MPHDRLEN_SSN: MPHDRLEN; 1735 int mphdrlen = (ppp->flags & SC_MP_SHORTSEQ)? MPHDRLEN_SSN: MPHDRLEN;
1693 1736
1694 if (!pskb_may_pull(skb, mphdrlen + 1) || ppp->mrru == 0) 1737 if (!pskb_may_pull(skb, mphdrlen) || ppp->mrru == 0)
1695 goto err; /* no good, throw it away */ 1738 goto err; /* no good, throw it away */
1696 1739
1697 /* Decode sequence number and begin/end bits */ 1740 /* Decode sequence number and begin/end bits */
@@ -2611,8 +2654,8 @@ static void __exit ppp_cleanup(void)
2611 if (unregister_chrdev(PPP_MAJOR, "ppp") != 0) 2654 if (unregister_chrdev(PPP_MAJOR, "ppp") != 0)
2612 printk(KERN_ERR "PPP: failed to unregister PPP device\n"); 2655 printk(KERN_ERR "PPP: failed to unregister PPP device\n");
2613 devfs_remove("ppp"); 2656 devfs_remove("ppp");
2614 class_simple_device_remove(MKDEV(PPP_MAJOR, 0)); 2657 class_device_destroy(ppp_class, MKDEV(PPP_MAJOR, 0));
2615 class_simple_destroy(ppp_class); 2658 class_destroy(ppp_class);
2616} 2659}
2617 2660
2618/* 2661/*
diff --git a/drivers/net/ppp_synctty.c b/drivers/net/ppp_synctty.c
index 7d0150b4c629..fd9f50180355 100644
--- a/drivers/net/ppp_synctty.c
+++ b/drivers/net/ppp_synctty.c
@@ -793,7 +793,7 @@ err:
793static void __exit 793static void __exit
794ppp_sync_cleanup(void) 794ppp_sync_cleanup(void)
795{ 795{
796 if (tty_register_ldisc(N_SYNC_PPP, NULL) != 0) 796 if (tty_unregister_ldisc(N_SYNC_PPP) != 0)
797 printk(KERN_ERR "failed to unregister Sync PPP line discipline\n"); 797 printk(KERN_ERR "failed to unregister Sync PPP line discipline\n");
798} 798}
799 799
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index c59507f8a76b..ce449fe90e6d 100644
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -69,7 +69,13 @@ VERSION 2.2LK <2005/01/25>
69#include <asm/io.h> 69#include <asm/io.h>
70#include <asm/irq.h> 70#include <asm/irq.h>
71 71
72#define RTL8169_VERSION "2.2LK" 72#ifdef CONFIG_R8169_NAPI
73#define NAPI_SUFFIX "-NAPI"
74#else
75#define NAPI_SUFFIX ""
76#endif
77
78#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
73#define MODULENAME "r8169" 79#define MODULENAME "r8169"
74#define PFX MODULENAME ": " 80#define PFX MODULENAME ": "
75 81
@@ -85,6 +91,10 @@ VERSION 2.2LK <2005/01/25>
85#define dprintk(fmt, args...) do {} while (0) 91#define dprintk(fmt, args...) do {} while (0)
86#endif /* RTL8169_DEBUG */ 92#endif /* RTL8169_DEBUG */
87 93
94#define R8169_MSG_DEFAULT \
95 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | NETIF_MSG_IFUP | \
96 NETIF_MSG_IFDOWN)
97
88#define TX_BUFFS_AVAIL(tp) \ 98#define TX_BUFFS_AVAIL(tp) \
89 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1) 99 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
90 100
@@ -174,8 +184,9 @@ const static struct {
174#undef _R 184#undef _R
175 185
176static struct pci_device_id rtl8169_pci_tbl[] = { 186static struct pci_device_id rtl8169_pci_tbl[] = {
177 {0x10ec, 0x8169, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 187 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), },
178 {0x1186, 0x4300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 188 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), },
189 { PCI_DEVICE(0x16ec, 0x0116), },
179 {0,}, 190 {0,},
180}; 191};
181 192
@@ -183,10 +194,15 @@ MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
183 194
184static int rx_copybreak = 200; 195static int rx_copybreak = 200;
185static int use_dac; 196static int use_dac;
197static struct {
198 u32 msg_enable;
199} debug = { -1 };
186 200
187enum RTL8169_registers { 201enum RTL8169_registers {
188 MAC0 = 0, /* Ethernet hardware address. */ 202 MAC0 = 0, /* Ethernet hardware address. */
189 MAR0 = 8, /* Multicast filter. */ 203 MAR0 = 8, /* Multicast filter. */
204 CounterAddrLow = 0x10,
205 CounterAddrHigh = 0x14,
190 TxDescStartAddrLow = 0x20, 206 TxDescStartAddrLow = 0x20,
191 TxDescStartAddrHigh = 0x24, 207 TxDescStartAddrHigh = 0x24,
192 TxHDescStartAddrLow = 0x28, 208 TxHDescStartAddrLow = 0x28,
@@ -328,6 +344,9 @@ enum RTL8169_register_content {
328 344
329 /* _TBICSRBit */ 345 /* _TBICSRBit */
330 TBILinkOK = 0x02000000, 346 TBILinkOK = 0x02000000,
347
348 /* DumpCounterCommand */
349 CounterDump = 0x8,
331}; 350};
332 351
333enum _DescStatusBit { 352enum _DescStatusBit {
@@ -385,6 +404,7 @@ struct rtl8169_private {
385 struct pci_dev *pci_dev; /* Index of PCI device */ 404 struct pci_dev *pci_dev; /* Index of PCI device */
386 struct net_device_stats stats; /* statistics of net device */ 405 struct net_device_stats stats; /* statistics of net device */
387 spinlock_t lock; /* spin lock flag */ 406 spinlock_t lock; /* spin lock flag */
407 u32 msg_enable;
388 int chipset; 408 int chipset;
389 int mac_version; 409 int mac_version;
390 int phy_version; 410 int phy_version;
@@ -415,12 +435,16 @@ struct rtl8169_private {
415 struct work_struct task; 435 struct work_struct task;
416}; 436};
417 437
418MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@oss.sgi.com>"); 438MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
419MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 439MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
420module_param_array(media, int, &num_media, 0); 440module_param_array(media, int, &num_media, 0);
441MODULE_PARM_DESC(media, "force phy operation. Deprecated by ethtool (8).");
421module_param(rx_copybreak, int, 0); 442module_param(rx_copybreak, int, 0);
443MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
422module_param(use_dac, int, 0); 444module_param(use_dac, int, 0);
423MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); 445MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
446module_param_named(debug, debug.msg_enable, int, 0);
447MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
424MODULE_LICENSE("GPL"); 448MODULE_LICENSE("GPL");
425MODULE_VERSION(RTL8169_VERSION); 449MODULE_VERSION(RTL8169_VERSION);
426 450
@@ -433,10 +457,10 @@ static void rtl8169_hw_start(struct net_device *dev);
433static int rtl8169_close(struct net_device *dev); 457static int rtl8169_close(struct net_device *dev);
434static void rtl8169_set_rx_mode(struct net_device *dev); 458static void rtl8169_set_rx_mode(struct net_device *dev);
435static void rtl8169_tx_timeout(struct net_device *dev); 459static void rtl8169_tx_timeout(struct net_device *dev);
436static struct net_device_stats *rtl8169_get_stats(struct net_device *netdev); 460static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
437static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *, 461static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
438 void __iomem *); 462 void __iomem *);
439static int rtl8169_change_mtu(struct net_device *netdev, int new_mtu); 463static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
440static void rtl8169_down(struct net_device *dev); 464static void rtl8169_down(struct net_device *dev);
441 465
442#ifdef CONFIG_R8169_NAPI 466#ifdef CONFIG_R8169_NAPI
@@ -543,9 +567,13 @@ static void rtl8169_check_link_status(struct net_device *dev,
543 spin_lock_irqsave(&tp->lock, flags); 567 spin_lock_irqsave(&tp->lock, flags);
544 if (tp->link_ok(ioaddr)) { 568 if (tp->link_ok(ioaddr)) {
545 netif_carrier_on(dev); 569 netif_carrier_on(dev);
546 printk(KERN_INFO PFX "%s: link up\n", dev->name); 570 if (netif_msg_ifup(tp))
547 } else 571 printk(KERN_INFO PFX "%s: link up\n", dev->name);
572 } else {
573 if (netif_msg_ifdown(tp))
574 printk(KERN_INFO PFX "%s: link down\n", dev->name);
548 netif_carrier_off(dev); 575 netif_carrier_off(dev);
576 }
549 spin_unlock_irqrestore(&tp->lock, flags); 577 spin_unlock_irqrestore(&tp->lock, flags);
550} 578}
551 579
@@ -569,7 +597,7 @@ static void rtl8169_link_option(int idx, u8 *autoneg, u16 *speed, u8 *duplex)
569 597
570 option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff; 598 option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff;
571 599
572 if ((option != 0xff) && !idx) 600 if ((option != 0xff) && !idx && netif_msg_drv(&debug))
573 printk(KERN_WARNING PFX "media option is deprecated.\n"); 601 printk(KERN_WARNING PFX "media option is deprecated.\n");
574 602
575 for (p = link_settings; p->media != 0xff; p++) { 603 for (p = link_settings; p->media != 0xff; p++) {
@@ -611,9 +639,11 @@ static int rtl8169_set_speed_tbi(struct net_device *dev,
611 } else if (autoneg == AUTONEG_ENABLE) 639 } else if (autoneg == AUTONEG_ENABLE)
612 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); 640 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
613 else { 641 else {
614 printk(KERN_WARNING PFX 642 if (netif_msg_link(tp)) {
615 "%s: incorrect speed setting refused in TBI mode\n", 643 printk(KERN_WARNING "%s: "
616 dev->name); 644 "incorrect speed setting refused in TBI mode\n",
645 dev->name);
646 }
617 ret = -EOPNOTSUPP; 647 ret = -EOPNOTSUPP;
618 } 648 }
619 649
@@ -871,12 +901,120 @@ static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
871 spin_unlock_irqrestore(&tp->lock, flags); 901 spin_unlock_irqrestore(&tp->lock, flags);
872} 902}
873 903
904static u32 rtl8169_get_msglevel(struct net_device *dev)
905{
906 struct rtl8169_private *tp = netdev_priv(dev);
907
908 return tp->msg_enable;
909}
910
911static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
912{
913 struct rtl8169_private *tp = netdev_priv(dev);
914
915 tp->msg_enable = value;
916}
917
918static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
919 "tx_packets",
920 "rx_packets",
921 "tx_errors",
922 "rx_errors",
923 "rx_missed",
924 "align_errors",
925 "tx_single_collisions",
926 "tx_multi_collisions",
927 "unicast",
928 "broadcast",
929 "multicast",
930 "tx_aborted",
931 "tx_underrun",
932};
933
934struct rtl8169_counters {
935 u64 tx_packets;
936 u64 rx_packets;
937 u64 tx_errors;
938 u32 rx_errors;
939 u16 rx_missed;
940 u16 align_errors;
941 u32 tx_one_collision;
942 u32 tx_multi_collision;
943 u64 rx_unicast;
944 u64 rx_broadcast;
945 u32 rx_multicast;
946 u16 tx_aborted;
947 u16 tx_underun;
948};
949
950static int rtl8169_get_stats_count(struct net_device *dev)
951{
952 return ARRAY_SIZE(rtl8169_gstrings);
953}
954
955static void rtl8169_get_ethtool_stats(struct net_device *dev,
956 struct ethtool_stats *stats, u64 *data)
957{
958 struct rtl8169_private *tp = netdev_priv(dev);
959 void __iomem *ioaddr = tp->mmio_addr;
960 struct rtl8169_counters *counters;
961 dma_addr_t paddr;
962 u32 cmd;
963
964 ASSERT_RTNL();
965
966 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
967 if (!counters)
968 return;
969
970 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
971 cmd = (u64)paddr & DMA_32BIT_MASK;
972 RTL_W32(CounterAddrLow, cmd);
973 RTL_W32(CounterAddrLow, cmd | CounterDump);
974
975 while (RTL_R32(CounterAddrLow) & CounterDump) {
976 if (msleep_interruptible(1))
977 break;
978 }
979
980 RTL_W32(CounterAddrLow, 0);
981 RTL_W32(CounterAddrHigh, 0);
982
983 data[0] = le64_to_cpu(counters->tx_packets);
984 data[1] = le64_to_cpu(counters->rx_packets);
985 data[2] = le64_to_cpu(counters->tx_errors);
986 data[3] = le32_to_cpu(counters->rx_errors);
987 data[4] = le16_to_cpu(counters->rx_missed);
988 data[5] = le16_to_cpu(counters->align_errors);
989 data[6] = le32_to_cpu(counters->tx_one_collision);
990 data[7] = le32_to_cpu(counters->tx_multi_collision);
991 data[8] = le64_to_cpu(counters->rx_unicast);
992 data[9] = le64_to_cpu(counters->rx_broadcast);
993 data[10] = le32_to_cpu(counters->rx_multicast);
994 data[11] = le16_to_cpu(counters->tx_aborted);
995 data[12] = le16_to_cpu(counters->tx_underun);
996
997 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
998}
999
1000static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1001{
1002 switch(stringset) {
1003 case ETH_SS_STATS:
1004 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1005 break;
1006 }
1007}
1008
1009
874static struct ethtool_ops rtl8169_ethtool_ops = { 1010static struct ethtool_ops rtl8169_ethtool_ops = {
875 .get_drvinfo = rtl8169_get_drvinfo, 1011 .get_drvinfo = rtl8169_get_drvinfo,
876 .get_regs_len = rtl8169_get_regs_len, 1012 .get_regs_len = rtl8169_get_regs_len,
877 .get_link = ethtool_op_get_link, 1013 .get_link = ethtool_op_get_link,
878 .get_settings = rtl8169_get_settings, 1014 .get_settings = rtl8169_get_settings,
879 .set_settings = rtl8169_set_settings, 1015 .set_settings = rtl8169_set_settings,
1016 .get_msglevel = rtl8169_get_msglevel,
1017 .set_msglevel = rtl8169_set_msglevel,
880 .get_rx_csum = rtl8169_get_rx_csum, 1018 .get_rx_csum = rtl8169_get_rx_csum,
881 .set_rx_csum = rtl8169_set_rx_csum, 1019 .set_rx_csum = rtl8169_set_rx_csum,
882 .get_tx_csum = ethtool_op_get_tx_csum, 1020 .get_tx_csum = ethtool_op_get_tx_csum,
@@ -886,6 +1024,9 @@ static struct ethtool_ops rtl8169_ethtool_ops = {
886 .get_tso = ethtool_op_get_tso, 1024 .get_tso = ethtool_op_get_tso,
887 .set_tso = ethtool_op_set_tso, 1025 .set_tso = ethtool_op_set_tso,
888 .get_regs = rtl8169_get_regs, 1026 .get_regs = rtl8169_get_regs,
1027 .get_strings = rtl8169_get_strings,
1028 .get_stats_count = rtl8169_get_stats_count,
1029 .get_ethtool_stats = rtl8169_get_ethtool_stats,
889}; 1030};
890 1031
891static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, int bitnum, 1032static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, int bitnum,
@@ -1091,7 +1232,8 @@ static void rtl8169_phy_timer(unsigned long __opaque)
1091 if (tp->link_ok(ioaddr)) 1232 if (tp->link_ok(ioaddr))
1092 goto out_unlock; 1233 goto out_unlock;
1093 1234
1094 printk(KERN_WARNING PFX "%s: PHY reset until link up\n", dev->name); 1235 if (netif_msg_link(tp))
1236 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1095 1237
1096 tp->phy_reset_enable(ioaddr); 1238 tp->phy_reset_enable(ioaddr);
1097 1239
@@ -1169,18 +1311,23 @@ rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
1169 /* dev zeroed in alloc_etherdev */ 1311 /* dev zeroed in alloc_etherdev */
1170 dev = alloc_etherdev(sizeof (*tp)); 1312 dev = alloc_etherdev(sizeof (*tp));
1171 if (dev == NULL) { 1313 if (dev == NULL) {
1172 printk(KERN_ERR PFX "unable to alloc new ethernet\n"); 1314 if (netif_msg_drv(&debug))
1315 printk(KERN_ERR PFX "unable to alloc new ethernet\n");
1173 goto err_out; 1316 goto err_out;
1174 } 1317 }
1175 1318
1176 SET_MODULE_OWNER(dev); 1319 SET_MODULE_OWNER(dev);
1177 SET_NETDEV_DEV(dev, &pdev->dev); 1320 SET_NETDEV_DEV(dev, &pdev->dev);
1178 tp = netdev_priv(dev); 1321 tp = netdev_priv(dev);
1322 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1179 1323
1180 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 1324 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1181 rc = pci_enable_device(pdev); 1325 rc = pci_enable_device(pdev);
1182 if (rc) { 1326 if (rc < 0) {
1183 printk(KERN_ERR PFX "%s: enable failure\n", pci_name(pdev)); 1327 if (netif_msg_probe(tp)) {
1328 printk(KERN_ERR PFX "%s: enable failure\n",
1329 pci_name(pdev));
1330 }
1184 goto err_out_free_dev; 1331 goto err_out_free_dev;
1185 } 1332 }
1186 1333
@@ -1196,29 +1343,39 @@ rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
1196 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command); 1343 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command);
1197 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK; 1344 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
1198 } else { 1345 } else {
1199 printk(KERN_ERR PFX 1346 if (netif_msg_probe(tp)) {
1200 "Cannot find PowerManagement capability, aborting.\n"); 1347 printk(KERN_ERR PFX
1348 "Cannot find PowerManagement capability. "
1349 "Aborting.\n");
1350 }
1201 goto err_out_mwi; 1351 goto err_out_mwi;
1202 } 1352 }
1203 1353
1204 /* make sure PCI base addr 1 is MMIO */ 1354 /* make sure PCI base addr 1 is MMIO */
1205 if (!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) { 1355 if (!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
1206 printk(KERN_ERR PFX 1356 if (netif_msg_probe(tp)) {
1207 "region #1 not an MMIO resource, aborting\n"); 1357 printk(KERN_ERR PFX
1358 "region #1 not an MMIO resource, aborting\n");
1359 }
1208 rc = -ENODEV; 1360 rc = -ENODEV;
1209 goto err_out_mwi; 1361 goto err_out_mwi;
1210 } 1362 }
1211 /* check for weird/broken PCI region reporting */ 1363 /* check for weird/broken PCI region reporting */
1212 if (pci_resource_len(pdev, 1) < R8169_REGS_SIZE) { 1364 if (pci_resource_len(pdev, 1) < R8169_REGS_SIZE) {
1213 printk(KERN_ERR PFX "Invalid PCI region size(s), aborting\n"); 1365 if (netif_msg_probe(tp)) {
1366 printk(KERN_ERR PFX
1367 "Invalid PCI region size(s), aborting\n");
1368 }
1214 rc = -ENODEV; 1369 rc = -ENODEV;
1215 goto err_out_mwi; 1370 goto err_out_mwi;
1216 } 1371 }
1217 1372
1218 rc = pci_request_regions(pdev, MODULENAME); 1373 rc = pci_request_regions(pdev, MODULENAME);
1219 if (rc) { 1374 if (rc < 0) {
1220 printk(KERN_ERR PFX "%s: could not request regions.\n", 1375 if (netif_msg_probe(tp)) {
1221 pci_name(pdev)); 1376 printk(KERN_ERR PFX "%s: could not request regions.\n",
1377 pci_name(pdev));
1378 }
1222 goto err_out_mwi; 1379 goto err_out_mwi;
1223 } 1380 }
1224 1381
@@ -1231,7 +1388,10 @@ rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
1231 } else { 1388 } else {
1232 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 1389 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1233 if (rc < 0) { 1390 if (rc < 0) {
1234 printk(KERN_ERR PFX "DMA configuration failed.\n"); 1391 if (netif_msg_probe(tp)) {
1392 printk(KERN_ERR PFX
1393 "DMA configuration failed.\n");
1394 }
1235 goto err_out_free_res; 1395 goto err_out_free_res;
1236 } 1396 }
1237 } 1397 }
@@ -1241,7 +1401,8 @@ rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
1241 /* ioremap MMIO region */ 1401 /* ioremap MMIO region */
1242 ioaddr = ioremap(pci_resource_start(pdev, 1), R8169_REGS_SIZE); 1402 ioaddr = ioremap(pci_resource_start(pdev, 1), R8169_REGS_SIZE);
1243 if (ioaddr == NULL) { 1403 if (ioaddr == NULL) {
1244 printk(KERN_ERR PFX "cannot remap MMIO, aborting\n"); 1404 if (netif_msg_probe(tp))
1405 printk(KERN_ERR PFX "cannot remap MMIO, aborting\n");
1245 rc = -EIO; 1406 rc = -EIO;
1246 goto err_out_free_res; 1407 goto err_out_free_res;
1247 } 1408 }
@@ -1272,9 +1433,11 @@ rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
1272 } 1433 }
1273 if (i < 0) { 1434 if (i < 0) {
1274 /* Unknown chip: assume array element #0, original RTL-8169 */ 1435 /* Unknown chip: assume array element #0, original RTL-8169 */
1275 printk(KERN_DEBUG PFX 1436 if (netif_msg_probe(tp)) {
1276 "PCI device %s: unknown chip version, assuming %s\n", 1437 printk(KERN_DEBUG PFX "PCI device %s: "
1277 pci_name(pdev), rtl_chip_info[0].name); 1438 "unknown chip version, assuming %s\n",
1439 pci_name(pdev), rtl_chip_info[0].name);
1440 }
1278 i++; 1441 i++;
1279 } 1442 }
1280 tp->chipset = i; 1443 tp->chipset = i;
@@ -1308,7 +1471,6 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1308 struct rtl8169_private *tp; 1471 struct rtl8169_private *tp;
1309 void __iomem *ioaddr = NULL; 1472 void __iomem *ioaddr = NULL;
1310 static int board_idx = -1; 1473 static int board_idx = -1;
1311 static int printed_version = 0;
1312 u8 autoneg, duplex; 1474 u8 autoneg, duplex;
1313 u16 speed; 1475 u16 speed;
1314 int i, rc; 1476 int i, rc;
@@ -1318,10 +1480,9 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1318 1480
1319 board_idx++; 1481 board_idx++;
1320 1482
1321 if (!printed_version) { 1483 if (netif_msg_drv(&debug)) {
1322 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", 1484 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1323 MODULENAME, RTL8169_VERSION); 1485 MODULENAME, RTL8169_VERSION);
1324 printed_version = 1;
1325 } 1486 }
1326 1487
1327 rc = rtl8169_init_board(pdev, &dev, &ioaddr); 1488 rc = rtl8169_init_board(pdev, &dev, &ioaddr);
@@ -1366,7 +1527,6 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1366#ifdef CONFIG_R8169_NAPI 1527#ifdef CONFIG_R8169_NAPI
1367 dev->poll = rtl8169_poll; 1528 dev->poll = rtl8169_poll;
1368 dev->weight = R8169_NAPI_WEIGHT; 1529 dev->weight = R8169_NAPI_WEIGHT;
1369 printk(KERN_INFO PFX "NAPI enabled\n");
1370#endif 1530#endif
1371 1531
1372#ifdef CONFIG_R8169_VLAN 1532#ifdef CONFIG_R8169_VLAN
@@ -1391,20 +1551,24 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1391 return rc; 1551 return rc;
1392 } 1552 }
1393 1553
1394 printk(KERN_DEBUG "%s: Identified chip type is '%s'.\n", dev->name, 1554 if (netif_msg_probe(tp)) {
1395 rtl_chip_info[tp->chipset].name); 1555 printk(KERN_DEBUG "%s: Identified chip type is '%s'.\n",
1556 dev->name, rtl_chip_info[tp->chipset].name);
1557 }
1396 1558
1397 pci_set_drvdata(pdev, dev); 1559 pci_set_drvdata(pdev, dev);
1398 1560
1399 printk(KERN_INFO "%s: %s at 0x%lx, " 1561 if (netif_msg_probe(tp)) {
1400 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, " 1562 printk(KERN_INFO "%s: %s at 0x%lx, "
1401 "IRQ %d\n", 1563 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1402 dev->name, 1564 "IRQ %d\n",
1403 rtl_chip_info[ent->driver_data].name, 1565 dev->name,
1404 dev->base_addr, 1566 rtl_chip_info[ent->driver_data].name,
1405 dev->dev_addr[0], dev->dev_addr[1], 1567 dev->base_addr,
1406 dev->dev_addr[2], dev->dev_addr[3], 1568 dev->dev_addr[0], dev->dev_addr[1],
1407 dev->dev_addr[4], dev->dev_addr[5], dev->irq); 1569 dev->dev_addr[2], dev->dev_addr[3],
1570 dev->dev_addr[4], dev->dev_addr[5], dev->irq);
1571 }
1408 1572
1409 rtl8169_hw_phy_config(dev); 1573 rtl8169_hw_phy_config(dev);
1410 1574
@@ -1427,7 +1591,7 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1427 1591
1428 rtl8169_set_speed(dev, autoneg, speed, duplex); 1592 rtl8169_set_speed(dev, autoneg, speed, duplex);
1429 1593
1430 if (RTL_R8(PHYstatus) & TBI_Enable) 1594 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1431 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name); 1595 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1432 1596
1433 return 0; 1597 return 0;
@@ -1585,8 +1749,8 @@ rtl8169_hw_start(struct net_device *dev)
1585 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 1749 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1586 RTL_W8(EarlyTxThres, EarlyTxThld); 1750 RTL_W8(EarlyTxThres, EarlyTxThld);
1587 1751
1588 /* For gigabit rtl8169, MTU + header + CRC + VLAN */ 1752 /* Low hurts. Let's disable the filtering. */
1589 RTL_W16(RxMaxSize, tp->rx_buf_sz); 1753 RTL_W16(RxMaxSize, 16383);
1590 1754
1591 /* Set Rx Config register */ 1755 /* Set Rx Config register */
1592 i = rtl8169_rx_config | 1756 i = rtl8169_rx_config |
@@ -1860,8 +2024,13 @@ static void rtl8169_reinit_task(void *_data)
1860 ret = rtl8169_open(dev); 2024 ret = rtl8169_open(dev);
1861 if (unlikely(ret < 0)) { 2025 if (unlikely(ret < 0)) {
1862 if (net_ratelimit()) { 2026 if (net_ratelimit()) {
1863 printk(PFX KERN_ERR "%s: reinit failure (status = %d)." 2027 struct rtl8169_private *tp = netdev_priv(dev);
1864 " Rescheduling.\n", dev->name, ret); 2028
2029 if (netif_msg_drv(tp)) {
2030 printk(PFX KERN_ERR
2031 "%s: reinit failure (status = %d)."
2032 " Rescheduling.\n", dev->name, ret);
2033 }
1865 } 2034 }
1866 rtl8169_schedule_work(dev, rtl8169_reinit_task); 2035 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1867 } 2036 }
@@ -1886,8 +2055,12 @@ static void rtl8169_reset_task(void *_data)
1886 netif_wake_queue(dev); 2055 netif_wake_queue(dev);
1887 } else { 2056 } else {
1888 if (net_ratelimit()) { 2057 if (net_ratelimit()) {
1889 printk(PFX KERN_EMERG "%s: Rx buffers shortage\n", 2058 struct rtl8169_private *tp = netdev_priv(dev);
1890 dev->name); 2059
2060 if (netif_msg_intr(tp)) {
2061 printk(PFX KERN_EMERG
2062 "%s: Rx buffers shortage\n", dev->name);
2063 }
1891 } 2064 }
1892 rtl8169_schedule_work(dev, rtl8169_reset_task); 2065 rtl8169_schedule_work(dev, rtl8169_reset_task);
1893 } 2066 }
@@ -1973,8 +2146,11 @@ static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
1973 int ret = 0; 2146 int ret = 0;
1974 2147
1975 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) { 2148 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
1976 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n", 2149 if (netif_msg_drv(tp)) {
1977 dev->name); 2150 printk(KERN_ERR
2151 "%s: BUG! Tx Ring full when queue awake!\n",
2152 dev->name);
2153 }
1978 goto err_stop; 2154 goto err_stop;
1979 } 2155 }
1980 2156
@@ -2049,8 +2225,11 @@ static void rtl8169_pcierr_interrupt(struct net_device *dev)
2049 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 2225 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2050 pci_read_config_word(pdev, PCI_STATUS, &pci_status); 2226 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2051 2227
2052 printk(KERN_ERR PFX "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n", 2228 if (netif_msg_intr(tp)) {
2053 dev->name, pci_cmd, pci_status); 2229 printk(KERN_ERR
2230 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2231 dev->name, pci_cmd, pci_status);
2232 }
2054 2233
2055 /* 2234 /*
2056 * The recovery sequence below admits a very elaborated explanation: 2235 * The recovery sequence below admits a very elaborated explanation:
@@ -2069,7 +2248,8 @@ static void rtl8169_pcierr_interrupt(struct net_device *dev)
2069 2248
2070 /* The infamous DAC f*ckup only happens at boot time */ 2249 /* The infamous DAC f*ckup only happens at boot time */
2071 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) { 2250 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2072 printk(KERN_INFO PFX "%s: disabling PCI DAC.\n", dev->name); 2251 if (netif_msg_intr(tp))
2252 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2073 tp->cp_cmd &= ~PCIDAC; 2253 tp->cp_cmd &= ~PCIDAC;
2074 RTL_W16(CPlusCmd, tp->cp_cmd); 2254 RTL_W16(CPlusCmd, tp->cp_cmd);
2075 dev->features &= ~NETIF_F_HIGHDMA; 2255 dev->features &= ~NETIF_F_HIGHDMA;
@@ -2127,6 +2307,11 @@ rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2127 } 2307 }
2128} 2308}
2129 2309
2310static inline int rtl8169_fragmented_frame(u32 status)
2311{
2312 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2313}
2314
2130static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc) 2315static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2131{ 2316{
2132 u32 opts1 = le32_to_cpu(desc->opts1); 2317 u32 opts1 = le32_to_cpu(desc->opts1);
@@ -2175,29 +2360,46 @@ rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2175 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; 2360 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2176 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota); 2361 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2177 2362
2178 while (rx_left > 0) { 2363 for (; rx_left > 0; rx_left--, cur_rx++) {
2179 unsigned int entry = cur_rx % NUM_RX_DESC; 2364 unsigned int entry = cur_rx % NUM_RX_DESC;
2365 struct RxDesc *desc = tp->RxDescArray + entry;
2180 u32 status; 2366 u32 status;
2181 2367
2182 rmb(); 2368 rmb();
2183 status = le32_to_cpu(tp->RxDescArray[entry].opts1); 2369 status = le32_to_cpu(desc->opts1);
2184 2370
2185 if (status & DescOwn) 2371 if (status & DescOwn)
2186 break; 2372 break;
2187 if (status & RxRES) { 2373 if (unlikely(status & RxRES)) {
2188 printk(KERN_INFO "%s: Rx ERROR!!!\n", dev->name); 2374 if (netif_msg_rx_err(tp)) {
2375 printk(KERN_INFO
2376 "%s: Rx ERROR. status = %08x\n",
2377 dev->name, status);
2378 }
2189 tp->stats.rx_errors++; 2379 tp->stats.rx_errors++;
2190 if (status & (RxRWT | RxRUNT)) 2380 if (status & (RxRWT | RxRUNT))
2191 tp->stats.rx_length_errors++; 2381 tp->stats.rx_length_errors++;
2192 if (status & RxCRC) 2382 if (status & RxCRC)
2193 tp->stats.rx_crc_errors++; 2383 tp->stats.rx_crc_errors++;
2384 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2194 } else { 2385 } else {
2195 struct RxDesc *desc = tp->RxDescArray + entry;
2196 struct sk_buff *skb = tp->Rx_skbuff[entry]; 2386 struct sk_buff *skb = tp->Rx_skbuff[entry];
2197 int pkt_size = (status & 0x00001FFF) - 4; 2387 int pkt_size = (status & 0x00001FFF) - 4;
2198 void (*pci_action)(struct pci_dev *, dma_addr_t, 2388 void (*pci_action)(struct pci_dev *, dma_addr_t,
2199 size_t, int) = pci_dma_sync_single_for_device; 2389 size_t, int) = pci_dma_sync_single_for_device;
2200 2390
2391 /*
2392 * The driver does not support incoming fragmented
2393 * frames. They are seen as a symptom of over-mtu
2394 * sized frames.
2395 */
2396 if (unlikely(rtl8169_fragmented_frame(status))) {
2397 tp->stats.rx_dropped++;
2398 tp->stats.rx_length_errors++;
2399 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2400 continue;
2401 }
2402
2201 rtl8169_rx_csum(skb, desc); 2403 rtl8169_rx_csum(skb, desc);
2202 2404
2203 pci_dma_sync_single_for_cpu(tp->pci_dev, 2405 pci_dma_sync_single_for_cpu(tp->pci_dev,
@@ -2224,16 +2426,13 @@ rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2224 tp->stats.rx_bytes += pkt_size; 2426 tp->stats.rx_bytes += pkt_size;
2225 tp->stats.rx_packets++; 2427 tp->stats.rx_packets++;
2226 } 2428 }
2227
2228 cur_rx++;
2229 rx_left--;
2230 } 2429 }
2231 2430
2232 count = cur_rx - tp->cur_rx; 2431 count = cur_rx - tp->cur_rx;
2233 tp->cur_rx = cur_rx; 2432 tp->cur_rx = cur_rx;
2234 2433
2235 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx); 2434 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
2236 if (!delta && count) 2435 if (!delta && count && netif_msg_intr(tp))
2237 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name); 2436 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2238 tp->dirty_rx += delta; 2437 tp->dirty_rx += delta;
2239 2438
@@ -2244,7 +2443,7 @@ rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2244 * after refill ? 2443 * after refill ?
2245 * - how do others driver handle this condition (Uh oh...). 2444 * - how do others driver handle this condition (Uh oh...).
2246 */ 2445 */
2247 if (tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) 2446 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
2248 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name); 2447 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2249 2448
2250 return count; 2449 return count;
@@ -2296,7 +2495,7 @@ rtl8169_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
2296 2495
2297 if (likely(netif_rx_schedule_prep(dev))) 2496 if (likely(netif_rx_schedule_prep(dev)))
2298 __netif_rx_schedule(dev); 2497 __netif_rx_schedule(dev);
2299 else { 2498 else if (netif_msg_intr(tp)) {
2300 printk(KERN_INFO "%s: interrupt %04x taken in poll\n", 2499 printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
2301 dev->name, status); 2500 dev->name, status);
2302 } 2501 }
@@ -2315,8 +2514,10 @@ rtl8169_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
2315 } while (boguscnt > 0); 2514 } while (boguscnt > 0);
2316 2515
2317 if (boguscnt <= 0) { 2516 if (boguscnt <= 0) {
2318 printk(KERN_WARNING "%s: Too much work at interrupt!\n", 2517 if (net_ratelimit() && netif_msg_intr(tp)) {
2319 dev->name); 2518 printk(KERN_WARNING
2519 "%s: Too much work at interrupt!\n", dev->name);
2520 }
2320 /* Clear all interrupt sources. */ 2521 /* Clear all interrupt sources. */
2321 RTL_W16(IntrStatus, 0xffff); 2522 RTL_W16(IntrStatus, 0xffff);
2322 } 2523 }
@@ -2439,8 +2640,10 @@ rtl8169_set_rx_mode(struct net_device *dev)
2439 2640
2440 if (dev->flags & IFF_PROMISC) { 2641 if (dev->flags & IFF_PROMISC) {
2441 /* Unconditionally log net taps. */ 2642 /* Unconditionally log net taps. */
2442 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", 2643 if (netif_msg_link(tp)) {
2443 dev->name); 2644 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2645 dev->name);
2646 }
2444 rx_mode = 2647 rx_mode =
2445 AcceptBroadcast | AcceptMulticast | AcceptMyPhys | 2648 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2446 AcceptAllPhys; 2649 AcceptAllPhys;
diff --git a/drivers/net/shaper.c b/drivers/net/shaper.c
index e68cf5fb4920..20edeb345792 100644
--- a/drivers/net/shaper.c
+++ b/drivers/net/shaper.c
@@ -100,35 +100,8 @@ static int sh_debug; /* Debug flag */
100 100
101#define SHAPER_BANNER "CymruNet Traffic Shaper BETA 0.04 for Linux 2.1\n" 101#define SHAPER_BANNER "CymruNet Traffic Shaper BETA 0.04 for Linux 2.1\n"
102 102
103/*
104 * Locking
105 */
106
107static int shaper_lock(struct shaper *sh)
108{
109 /*
110 * Lock in an interrupt must fail
111 */
112 while (test_and_set_bit(0, &sh->locked))
113 {
114 if (!in_interrupt())
115 sleep_on(&sh->wait_queue);
116 else
117 return 0;
118
119 }
120 return 1;
121}
122
123static void shaper_kick(struct shaper *sh); 103static void shaper_kick(struct shaper *sh);
124 104
125static void shaper_unlock(struct shaper *sh)
126{
127 clear_bit(0, &sh->locked);
128 wake_up(&sh->wait_queue);
129 shaper_kick(sh);
130}
131
132/* 105/*
133 * Compute clocks on a buffer 106 * Compute clocks on a buffer
134 */ 107 */
@@ -157,17 +130,15 @@ static void shaper_setspeed(struct shaper *shaper, int bitspersec)
157 * Throw a frame at a shaper. 130 * Throw a frame at a shaper.
158 */ 131 */
159 132
160static int shaper_qframe(struct shaper *shaper, struct sk_buff *skb) 133
134static int shaper_start_xmit(struct sk_buff *skb, struct net_device *dev)
161{ 135{
136 struct shaper *shaper = dev->priv;
162 struct sk_buff *ptr; 137 struct sk_buff *ptr;
163 138
164 /* 139 if (down_trylock(&shaper->sem))
165 * Get ready to work on this shaper. Lock may fail if its 140 return -1;
166 * an interrupt and locked. 141
167 */
168
169 if(!shaper_lock(shaper))
170 return -1;
171 ptr=shaper->sendq.prev; 142 ptr=shaper->sendq.prev;
172 143
173 /* 144 /*
@@ -260,7 +231,8 @@ static int shaper_qframe(struct shaper *shaper, struct sk_buff *skb)
260 dev_kfree_skb(ptr); 231 dev_kfree_skb(ptr);
261 shaper->stats.collisions++; 232 shaper->stats.collisions++;
262 } 233 }
263 shaper_unlock(shaper); 234 shaper_kick(shaper);
235 up(&shaper->sem);
264 return 0; 236 return 0;
265} 237}
266 238
@@ -297,8 +269,13 @@ static void shaper_queue_xmit(struct shaper *shaper, struct sk_buff *skb)
297 269
298static void shaper_timer(unsigned long data) 270static void shaper_timer(unsigned long data)
299{ 271{
300 struct shaper *sh=(struct shaper *)data; 272 struct shaper *shaper = (struct shaper *)data;
301 shaper_kick(sh); 273
274 if (!down_trylock(&shaper->sem)) {
275 shaper_kick(shaper);
276 up(&shaper->sem);
277 } else
278 mod_timer(&shaper->timer, jiffies);
302} 279}
303 280
304/* 281/*
@@ -311,19 +288,6 @@ static void shaper_kick(struct shaper *shaper)
311 struct sk_buff *skb; 288 struct sk_buff *skb;
312 289
313 /* 290 /*
314 * Shaper unlock will kick
315 */
316
317 if (test_and_set_bit(0, &shaper->locked))
318 {
319 if(sh_debug)
320 printk("Shaper locked.\n");
321 mod_timer(&shaper->timer, jiffies);
322 return;
323 }
324
325
326 /*
327 * Walk the list (may be empty) 291 * Walk the list (may be empty)
328 */ 292 */
329 293
@@ -364,8 +328,6 @@ static void shaper_kick(struct shaper *shaper)
364 328
365 if(skb!=NULL) 329 if(skb!=NULL)
366 mod_timer(&shaper->timer, SHAPERCB(skb)->shapeclock); 330 mod_timer(&shaper->timer, SHAPERCB(skb)->shapeclock);
367
368 clear_bit(0, &shaper->locked);
369} 331}
370 332
371 333
@@ -376,14 +338,12 @@ static void shaper_kick(struct shaper *shaper)
376static void shaper_flush(struct shaper *shaper) 338static void shaper_flush(struct shaper *shaper)
377{ 339{
378 struct sk_buff *skb; 340 struct sk_buff *skb;
379 if(!shaper_lock(shaper)) 341
380 { 342 down(&shaper->sem);
381 printk(KERN_ERR "shaper: shaper_flush() called by an irq!\n");
382 return;
383 }
384 while((skb=skb_dequeue(&shaper->sendq))!=NULL) 343 while((skb=skb_dequeue(&shaper->sendq))!=NULL)
385 dev_kfree_skb(skb); 344 dev_kfree_skb(skb);
386 shaper_unlock(shaper); 345 shaper_kick(shaper);
346 up(&shaper->sem);
387} 347}
388 348
389/* 349/*
@@ -426,13 +386,6 @@ static int shaper_close(struct net_device *dev)
426 * ARP and other resolutions and not before. 386 * ARP and other resolutions and not before.
427 */ 387 */
428 388
429
430static int shaper_start_xmit(struct sk_buff *skb, struct net_device *dev)
431{
432 struct shaper *sh=dev->priv;
433 return shaper_qframe(sh, skb);
434}
435
436static struct net_device_stats *shaper_get_stats(struct net_device *dev) 389static struct net_device_stats *shaper_get_stats(struct net_device *dev)
437{ 390{
438 struct shaper *sh=dev->priv; 391 struct shaper *sh=dev->priv;
@@ -623,7 +576,6 @@ static void shaper_init_priv(struct net_device *dev)
623 init_timer(&sh->timer); 576 init_timer(&sh->timer);
624 sh->timer.function=shaper_timer; 577 sh->timer.function=shaper_timer;
625 sh->timer.data=(unsigned long)sh; 578 sh->timer.data=(unsigned long)sh;
626 init_waitqueue_head(&sh->wait_queue);
627} 579}
628 580
629/* 581/*
diff --git a/drivers/net/sis900.c b/drivers/net/sis900.c
index 3e9d9aab0588..3107aed0fb51 100644
--- a/drivers/net/sis900.c
+++ b/drivers/net/sis900.c
@@ -162,6 +162,7 @@ struct sis900_private {
162 struct mii_phy * mii; 162 struct mii_phy * mii;
163 struct mii_phy * first_mii; /* record the first mii structure */ 163 struct mii_phy * first_mii; /* record the first mii structure */
164 unsigned int cur_phy; 164 unsigned int cur_phy;
165 struct mii_if_info mii_info;
165 166
166 struct timer_list timer; /* Link status detection timer. */ 167 struct timer_list timer; /* Link status detection timer. */
167 u8 autong_complete; /* 1: auto-negotiate complete */ 168 u8 autong_complete; /* 1: auto-negotiate complete */
@@ -203,7 +204,7 @@ static int sis900_open(struct net_device *net_dev);
203static int sis900_mii_probe (struct net_device * net_dev); 204static int sis900_mii_probe (struct net_device * net_dev);
204static void sis900_init_rxfilter (struct net_device * net_dev); 205static void sis900_init_rxfilter (struct net_device * net_dev);
205static u16 read_eeprom(long ioaddr, int location); 206static u16 read_eeprom(long ioaddr, int location);
206static u16 mdio_read(struct net_device *net_dev, int phy_id, int location); 207static int mdio_read(struct net_device *net_dev, int phy_id, int location);
207static void mdio_write(struct net_device *net_dev, int phy_id, int location, int val); 208static void mdio_write(struct net_device *net_dev, int phy_id, int location, int val);
208static void sis900_timer(unsigned long data); 209static void sis900_timer(unsigned long data);
209static void sis900_check_mode (struct net_device *net_dev, struct mii_phy *mii_phy); 210static void sis900_check_mode (struct net_device *net_dev, struct mii_phy *mii_phy);
@@ -478,7 +479,13 @@ static int __devinit sis900_probe(struct pci_dev *pci_dev,
478 sis_priv->msg_enable = sis900_debug; 479 sis_priv->msg_enable = sis900_debug;
479 else 480 else
480 sis_priv->msg_enable = SIS900_DEF_MSG; 481 sis_priv->msg_enable = SIS900_DEF_MSG;
481 482
483 sis_priv->mii_info.dev = net_dev;
484 sis_priv->mii_info.mdio_read = mdio_read;
485 sis_priv->mii_info.mdio_write = mdio_write;
486 sis_priv->mii_info.phy_id_mask = 0x1f;
487 sis_priv->mii_info.reg_num_mask = 0x1f;
488
482 /* Get Mac address according to the chip revision */ 489 /* Get Mac address according to the chip revision */
483 pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &(sis_priv->chipset_rev)); 490 pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &(sis_priv->chipset_rev));
484 if(netif_msg_probe(sis_priv)) 491 if(netif_msg_probe(sis_priv))
@@ -725,6 +732,8 @@ static u16 sis900_default_phy(struct net_device * net_dev)
725 pci_name(sis_priv->pci_dev), sis_priv->cur_phy); 732 pci_name(sis_priv->pci_dev), sis_priv->cur_phy);
726 } 733 }
727 734
735 sis_priv->mii_info.phy_id = sis_priv->cur_phy;
736
728 status = mdio_read(net_dev, sis_priv->cur_phy, MII_CONTROL); 737 status = mdio_read(net_dev, sis_priv->cur_phy, MII_CONTROL);
729 status &= (~MII_CNTL_ISOLATE); 738 status &= (~MII_CNTL_ISOLATE);
730 739
@@ -852,7 +861,7 @@ static void mdio_reset(long mdio_addr)
852 * Please see SiS7014 or ICS spec 861 * Please see SiS7014 or ICS spec
853 */ 862 */
854 863
855static u16 mdio_read(struct net_device *net_dev, int phy_id, int location) 864static int mdio_read(struct net_device *net_dev, int phy_id, int location)
856{ 865{
857 long mdio_addr = net_dev->base_addr + mear; 866 long mdio_addr = net_dev->base_addr + mear;
858 int mii_cmd = MIIread|(phy_id<<MIIpmdShift)|(location<<MIIregShift); 867 int mii_cmd = MIIread|(phy_id<<MIIpmdShift)|(location<<MIIregShift);
@@ -1966,10 +1975,47 @@ static void sis900_set_msglevel(struct net_device *net_dev, u32 value)
1966 sis_priv->msg_enable = value; 1975 sis_priv->msg_enable = value;
1967} 1976}
1968 1977
1978static u32 sis900_get_link(struct net_device *net_dev)
1979{
1980 struct sis900_private *sis_priv = net_dev->priv;
1981 return mii_link_ok(&sis_priv->mii_info);
1982}
1983
1984static int sis900_get_settings(struct net_device *net_dev,
1985 struct ethtool_cmd *cmd)
1986{
1987 struct sis900_private *sis_priv = net_dev->priv;
1988 spin_lock_irq(&sis_priv->lock);
1989 mii_ethtool_gset(&sis_priv->mii_info, cmd);
1990 spin_unlock_irq(&sis_priv->lock);
1991 return 0;
1992}
1993
1994static int sis900_set_settings(struct net_device *net_dev,
1995 struct ethtool_cmd *cmd)
1996{
1997 struct sis900_private *sis_priv = net_dev->priv;
1998 int rt;
1999 spin_lock_irq(&sis_priv->lock);
2000 rt = mii_ethtool_sset(&sis_priv->mii_info, cmd);
2001 spin_unlock_irq(&sis_priv->lock);
2002 return rt;
2003}
2004
2005static int sis900_nway_reset(struct net_device *net_dev)
2006{
2007 struct sis900_private *sis_priv = net_dev->priv;
2008 return mii_nway_restart(&sis_priv->mii_info);
2009}
2010
1969static struct ethtool_ops sis900_ethtool_ops = { 2011static struct ethtool_ops sis900_ethtool_ops = {
1970 .get_drvinfo = sis900_get_drvinfo, 2012 .get_drvinfo = sis900_get_drvinfo,
1971 .get_msglevel = sis900_get_msglevel, 2013 .get_msglevel = sis900_get_msglevel,
1972 .set_msglevel = sis900_set_msglevel, 2014 .set_msglevel = sis900_set_msglevel,
2015 .get_link = sis900_get_link,
2016 .get_settings = sis900_get_settings,
2017 .set_settings = sis900_set_settings,
2018 .nway_reset = sis900_nway_reset,
1973}; 2019};
1974 2020
1975/** 2021/**
diff --git a/drivers/net/sk98lin/skge.c b/drivers/net/sk98lin/skge.c
index 05b827f79f54..1ccb2989001c 100644
--- a/drivers/net/sk98lin/skge.c
+++ b/drivers/net/sk98lin/skge.c
@@ -4212,7 +4212,7 @@ SK_BOOL DualNet;
4212 Flags); 4212 Flags);
4213 4213
4214 SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST); 4214 SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST);
4215 pAC->dev[Param.Para32[0]]->flags &= ~IFF_RUNNING; 4215 netif_carrier_off(pAC->dev[Param.Para32[0]]);
4216 spin_unlock_irqrestore( 4216 spin_unlock_irqrestore(
4217 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock, 4217 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
4218 Flags); 4218 Flags);
@@ -4355,7 +4355,7 @@ SK_BOOL DualNet;
4355 } 4355 }
4356 4356
4357 /* Inform the world that link protocol is up. */ 4357 /* Inform the world that link protocol is up. */
4358 pAC->dev[Param.Para32[0]]->flags |= IFF_RUNNING; 4358 netif_carrier_on(pAC->dev[Param.Para32[0]]);
4359 4359
4360 break; 4360 break;
4361 case SK_DRV_NET_DOWN: /* SK_U32 Reason */ 4361 case SK_DRV_NET_DOWN: /* SK_U32 Reason */
@@ -4368,7 +4368,7 @@ SK_BOOL DualNet;
4368 } else { 4368 } else {
4369 DoPrintInterfaceChange = SK_TRUE; 4369 DoPrintInterfaceChange = SK_TRUE;
4370 } 4370 }
4371 pAC->dev[Param.Para32[1]]->flags &= ~IFF_RUNNING; 4371 netif_carrier_off(pAC->dev[Param.Para32[1]]);
4372 break; 4372 break;
4373 case SK_DRV_SWITCH_HARD: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */ 4373 case SK_DRV_SWITCH_HARD: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */
4374 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT, 4374 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
@@ -4961,7 +4961,6 @@ static int __devinit skge_probe_one(struct pci_dev *pdev,
4961#ifdef CONFIG_NET_POLL_CONTROLLER 4961#ifdef CONFIG_NET_POLL_CONTROLLER
4962 dev->poll_controller = &SkGePollController; 4962 dev->poll_controller = &SkGePollController;
4963#endif 4963#endif
4964 dev->flags &= ~IFF_RUNNING;
4965 SET_NETDEV_DEV(dev, &pdev->dev); 4964 SET_NETDEV_DEV(dev, &pdev->dev);
4966 SET_ETHTOOL_OPS(dev, &SkGeEthtoolOps); 4965 SET_ETHTOOL_OPS(dev, &SkGeEthtoolOps);
4967 4966
@@ -5035,7 +5034,6 @@ static int __devinit skge_probe_one(struct pci_dev *pdev,
5035 dev->set_mac_address = &SkGeSetMacAddr; 5034 dev->set_mac_address = &SkGeSetMacAddr;
5036 dev->do_ioctl = &SkGeIoctl; 5035 dev->do_ioctl = &SkGeIoctl;
5037 dev->change_mtu = &SkGeChangeMtu; 5036 dev->change_mtu = &SkGeChangeMtu;
5038 dev->flags &= ~IFF_RUNNING;
5039 SET_NETDEV_DEV(dev, &pdev->dev); 5037 SET_NETDEV_DEV(dev, &pdev->dev);
5040 SET_ETHTOOL_OPS(dev, &SkGeEthtoolOps); 5038 SET_ETHTOOL_OPS(dev, &SkGeEthtoolOps);
5041 5039
diff --git a/drivers/net/sk_g16.c b/drivers/net/sk_g16.c
deleted file mode 100644
index 134ae0e6495b..000000000000
--- a/drivers/net/sk_g16.c
+++ /dev/null
@@ -1,2066 +0,0 @@
1/*-
2 * Copyright (C) 1994 by PJD Weichmann & SWS Bern, Switzerland
3 *
4 * This software may be used and distributed according to the terms
5 * of the GNU General Public License, incorporated herein by reference.
6 *
7 * Module : sk_g16.c
8 *
9 * Version : $Revision: 1.1 $
10 *
11 * Author : Patrick J.D. Weichmann
12 *
13 * Date Created : 94/05/26
14 * Last Updated : $Date: 1994/06/30 16:25:15 $
15 *
16 * Description : Schneider & Koch G16 Ethernet Device Driver for
17 * Linux Kernel >= 1.1.22
18 * Update History :
19 * Paul Gortmaker, 03/97: Fix for v2.1.x to use read{b,w}
20 * write{b,w} and memcpy -> memcpy_{to,from}io
21 *
22 * Jeff Garzik, 06/2000, Modularize
23 *
24-*/
25
26static const char rcsid[] = "$Id: sk_g16.c,v 1.1 1994/06/30 16:25:15 root Exp $";
27
28/*
29 * The Schneider & Koch (SK) G16 Network device driver is based
30 * on the 'ni6510' driver from Michael Hipp which can be found at
31 * ftp://sunsite.unc.edu/pub/Linux/system/Network/drivers/nidrivers.tar.gz
32 *
33 * Sources: 1) ni6510.c by M. Hipp
34 * 2) depca.c by D.C. Davies
35 * 3) skeleton.c by D. Becker
36 * 4) Am7990 Local Area Network Controller for Ethernet (LANCE),
37 * AMD, Pub. #05698, June 1989
38 *
39 * Many Thanks for helping me to get things working to:
40 *
41 * A. Cox (A.Cox@swansea.ac.uk)
42 * M. Hipp (mhipp@student.uni-tuebingen.de)
43 * R. Bolz (Schneider & Koch, Germany)
44 *
45 * To Do:
46 * - Support of SK_G8 and other SK Network Cards.
47 * - Autoset memory mapped RAM. Check for free memory and then
48 * configure RAM correctly.
49 * - SK_close should really set card in to initial state.
50 * - Test if IRQ 3 is not switched off. Use autoirq() functionality.
51 * (as in /drivers/net/skeleton.c)
52 * - Implement Multicast addressing. At minimum something like
53 * in depca.c.
54 * - Redo the statistics part.
55 * - Try to find out if the board is in 8 Bit or 16 Bit slot.
56 * If in 8 Bit mode don't use IRQ 11.
57 * - (Try to make it slightly faster.)
58 * - Power management support
59 */
60
61#include <linux/module.h>
62#include <linux/kernel.h>
63#include <linux/fcntl.h>
64#include <linux/ioport.h>
65#include <linux/interrupt.h>
66#include <linux/slab.h>
67#include <linux/string.h>
68#include <linux/delay.h>
69#include <linux/errno.h>
70#include <linux/init.h>
71#include <linux/spinlock.h>
72#include <linux/netdevice.h>
73#include <linux/etherdevice.h>
74#include <linux/skbuff.h>
75#include <linux/bitops.h>
76
77#include <asm/system.h>
78#include <asm/io.h>
79
80#include "sk_g16.h"
81
82/*
83 * Schneider & Koch Card Definitions
84 * =================================
85 */
86
87#define SK_NAME "SK_G16"
88
89/*
90 * SK_G16 Configuration
91 * --------------------
92 */
93
94/*
95 * Abbreviations
96 * -------------
97 *
98 * RAM - used for the 16KB shared memory
99 * Boot_ROM, ROM - are used for referencing the BootEPROM
100 *
101 * SK_BOOT_ROM and SK_ADDR are symbolic constants used to configure
102 * the behaviour of the driver and the SK_G16.
103 *
104 * ! See sk_g16.install on how to install and configure the driver !
105 *
106 * SK_BOOT_ROM defines if the Boot_ROM should be switched off or not.
107 *
108 * SK_ADDR defines the address where the RAM will be mapped into the real
109 * host memory.
110 * valid addresses are from 0xa0000 to 0xfc000 in 16Kbyte steps.
111 */
112
113#define SK_BOOT_ROM 1 /* 1=BootROM on 0=off */
114
115#define SK_ADDR 0xcc000
116
117/*
118 * In POS3 are bits A14-A19 of the address bus. These bits can be set
119 * to choose the RAM address. That's why we only can choose the RAM address
120 * in 16KB steps.
121 */
122
123#define POS_ADDR (rom_addr>>14) /* Do not change this line */
124
125/*
126 * SK_G16 I/O PORT's + IRQ's + Boot_ROM locations
127 * ----------------------------------------------
128 */
129
130/*
131 * As nearly every card has also SK_G16 a specified I/O Port region and
132 * only a few possible IRQ's.
133 * In the Installation Guide from Schneider & Koch is listed a possible
134 * Interrupt IRQ2. IRQ2 is always IRQ9 in boards with two cascaded interrupt
135 * controllers. So we use in SK_IRQS IRQ9.
136 */
137
138/* Don't touch any of the following #defines. */
139
140#define SK_IO_PORTS { 0x100, 0x180, 0x208, 0x220, 0x288, 0x320, 0x328, 0x390, 0 }
141
142#define SK_IRQS { 3, 5, 9, 11, 0 }
143
144#define SK_BOOT_ROM_LOCATIONS { 0xc0000, 0xc4000, 0xc8000, 0xcc000, 0xd0000, 0xd4000, 0xd8000, 0xdc000, 0 }
145
146#define SK_BOOT_ROM_ID { 0x55, 0xaa, 0x10, 0x50, 0x06, 0x33 }
147
148/*
149 * SK_G16 POS REGISTERS
150 * --------------------
151 */
152
153/*
154 * SK_G16 has a Programmable Option Select (POS) Register.
155 * The POS is composed of 8 separate registers (POS0-7) which
156 * are I/O mapped on an address set by the W1 switch.
157 *
158 */
159
160#define SK_POS_SIZE 8 /* 8 I/O Ports are used by SK_G16 */
161
162#define SK_POS0 ioaddr /* Card-ID Low (R) */
163#define SK_POS1 ioaddr+1 /* Card-ID High (R) */
164#define SK_POS2 ioaddr+2 /* Card-Enable, Boot-ROM Disable (RW) */
165#define SK_POS3 ioaddr+3 /* Base address of RAM */
166#define SK_POS4 ioaddr+4 /* IRQ */
167
168/* POS5 - POS7 are unused */
169
170/*
171 * SK_G16 MAC PREFIX
172 * -----------------
173 */
174
175/*
176 * Scheider & Koch manufacturer code (00:00:a5).
177 * This must be checked, that we are sure it is a SK card.
178 */
179
180#define SK_MAC0 0x00
181#define SK_MAC1 0x00
182#define SK_MAC2 0x5a
183
184/*
185 * SK_G16 ID
186 * ---------
187 */
188
189/*
190 * If POS0,POS1 contain the following ID, then we know
191 * at which I/O Port Address we are.
192 */
193
194#define SK_IDLOW 0xfd
195#define SK_IDHIGH 0x6a
196
197
198/*
199 * LANCE POS Bit definitions
200 * -------------------------
201 */
202
203#define SK_ROM_RAM_ON (POS2_CARD)
204#define SK_ROM_RAM_OFF (POS2_EPROM)
205#define SK_ROM_ON (inb(SK_POS2) & POS2_CARD)
206#define SK_ROM_OFF (inb(SK_POS2) | POS2_EPROM)
207#define SK_RAM_ON (inb(SK_POS2) | POS2_CARD)
208#define SK_RAM_OFF (inb(SK_POS2) & POS2_EPROM)
209
210#define POS2_CARD 0x0001 /* 1 = SK_G16 on 0 = off */
211#define POS2_EPROM 0x0002 /* 1 = Boot EPROM off 0 = on */
212
213/*
214 * SK_G16 Memory mapped Registers
215 * ------------------------------
216 *
217 */
218
219#define SK_IOREG (&board->ioreg) /* LANCE data registers. */
220#define SK_PORT (&board->port) /* Control, Status register */
221#define SK_IOCOM (&board->iocom) /* I/O Command */
222
223/*
224 * SK_G16 Status/Control Register bits
225 * -----------------------------------
226 *
227 * (C) Controlreg (S) Statusreg
228 */
229
230/*
231 * Register transfer: 0 = no transfer
232 * 1 = transferring data between LANCE and I/O reg
233 */
234#define SK_IORUN 0x20
235
236/*
237 * LANCE interrupt: 0 = LANCE interrupt occurred
238 * 1 = no LANCE interrupt occurred
239 */
240#define SK_IRQ 0x10
241
242#define SK_RESET 0x08 /* Reset SK_CARD: 0 = RESET 1 = normal */
243#define SK_RW 0x02 /* 0 = write to 1 = read from */
244#define SK_ADR 0x01 /* 0 = REG DataPort 1 = RAP Reg addr port */
245
246
247#define SK_RREG SK_RW /* Transferdirection to read from lance */
248#define SK_WREG 0 /* Transferdirection to write to lance */
249#define SK_RAP SK_ADR /* Destination Register RAP */
250#define SK_RDATA 0 /* Destination Register REG DataPort */
251
252/*
253 * SK_G16 I/O Command
254 * ------------------
255 */
256
257/*
258 * Any bitcombination sets the internal I/O bit (transfer will start)
259 * when written to I/O Command
260 */
261
262#define SK_DOIO 0x80 /* Do Transfer */
263
264/*
265 * LANCE RAP (Register Address Port).
266 * ---------------------------------
267 */
268
269/*
270 * The LANCE internal registers are selected through the RAP.
271 * The Registers are:
272 *
273 * CSR0 - Status and Control flags
274 * CSR1 - Low order bits of initialize block (bits 15:00)
275 * CSR2 - High order bits of initialize block (bits 07:00, 15:08 are reserved)
276 * CSR3 - Allows redefinition of the Bus Master Interface.
277 * This register must be set to 0x0002, which means BSWAP = 0,
278 * ACON = 1, BCON = 0;
279 *
280 */
281
282#define CSR0 0x00
283#define CSR1 0x01
284#define CSR2 0x02
285#define CSR3 0x03
286
287/*
288 * General Definitions
289 * ===================
290 */
291
292/*
293 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
294 * We have 16KB RAM which can be accessed by the LANCE. In the
295 * memory are not only the buffers but also the ring descriptors and
296 * the initialize block.
297 * Don't change anything unless you really know what you do.
298 */
299
300#define LC_LOG_TX_BUFFERS 1 /* (2 == 2^^1) 2 Transmit buffers */
301#define LC_LOG_RX_BUFFERS 3 /* (8 == 2^^3) 8 Receive buffers */
302
303/* Descriptor ring sizes */
304
305#define TMDNUM (1 << (LC_LOG_TX_BUFFERS)) /* 2 Transmit descriptor rings */
306#define RMDNUM (1 << (LC_LOG_RX_BUFFERS)) /* 8 Receive Buffers */
307
308/* Define Mask for setting RMD, TMD length in the LANCE init_block */
309
310#define TMDNUMMASK (LC_LOG_TX_BUFFERS << 29)
311#define RMDNUMMASK (LC_LOG_RX_BUFFERS << 29)
312
313/*
314 * Data Buffer size is set to maximum packet length.
315 */
316
317#define PKT_BUF_SZ 1518
318
319/*
320 * The number of low I/O ports used by the ethercard.
321 */
322
323#define ETHERCARD_TOTAL_SIZE SK_POS_SIZE
324
325/*
326 * SK_DEBUG
327 *
328 * Here you can choose what level of debugging wanted.
329 *
330 * If SK_DEBUG and SK_DEBUG2 are undefined, then only the
331 * necessary messages will be printed.
332 *
333 * If SK_DEBUG is defined, there will be many debugging prints
334 * which can help to find some mistakes in configuration or even
335 * in the driver code.
336 *
337 * If SK_DEBUG2 is defined, many many messages will be printed
338 * which normally you don't need. I used this to check the interrupt
339 * routine.
340 *
341 * (If you define only SK_DEBUG2 then only the messages for
342 * checking interrupts will be printed!)
343 *
344 * Normal way of live is:
345 *
346 * For the whole thing get going let both symbolic constants
347 * undefined. If you face any problems and you know what's going
348 * on (you know something about the card and you can interpret some
349 * hex LANCE register output) then define SK_DEBUG
350 *
351 */
352
353#undef SK_DEBUG /* debugging */
354#undef SK_DEBUG2 /* debugging with more verbose report */
355
356#ifdef SK_DEBUG
357#define PRINTK(x) printk x
358#else
359#define PRINTK(x) /**/
360#endif
361
362#ifdef SK_DEBUG2
363#define PRINTK2(x) printk x
364#else
365#define PRINTK2(x) /**/
366#endif
367
368/*
369 * SK_G16 RAM
370 *
371 * The components are memory mapped and can be set in a region from
372 * 0x00000 through 0xfc000 in 16KB steps.
373 *
374 * The Network components are: dual ported RAM, Prom, I/O Reg, Status-,
375 * Controlregister and I/O Command.
376 *
377 * dual ported RAM: This is the only memory region which the LANCE chip
378 * has access to. From the Lance it is addressed from 0x0000 to
379 * 0x3fbf. The host accesses it normally.
380 *
381 * PROM: The PROM obtains the ETHERNET-MAC-Address. It is realised as a
382 * 8-Bit PROM, this means only the 16 even addresses are used of the
383 * 32 Byte Address region. Access to an odd address results in invalid
384 * data.
385 *
386 * LANCE I/O Reg: The I/O Reg is build of 4 single Registers, Low-Byte Write,
387 * Hi-Byte Write, Low-Byte Read, Hi-Byte Read.
388 * Transfer from or to the LANCE is always in 16Bit so Low and High
389 * registers are always relevant.
390 *
391 * The Data from the Readregister is not the data in the Writeregister!!
392 *
393 * Port: Status- and Controlregister.
394 * Two different registers which share the same address, Status is
395 * read-only, Control is write-only.
396 *
397 * I/O Command:
398 * Any bitcombination written in here starts the transmission between
399 * Host and LANCE.
400 */
401
402typedef struct
403{
404 unsigned char ram[0x3fc0]; /* 16KB dual ported ram */
405 unsigned char rom[0x0020]; /* 32Byte PROM containing 6Byte MAC */
406 unsigned char res1[0x0010]; /* reserved */
407 unsigned volatile short ioreg;/* LANCE I/O Register */
408 unsigned volatile char port; /* Statusregister and Controlregister */
409 unsigned char iocom; /* I/O Command Register */
410} SK_RAM;
411
412/* struct */
413
414/*
415 * This is the structure for the dual ported ram. We
416 * have exactly 16 320 Bytes. In here there must be:
417 *
418 * - Initialize Block (starting at a word boundary)
419 * - Receive and Transmit Descriptor Rings (quadword boundary)
420 * - Data Buffers (arbitrary boundary)
421 *
422 * This is because LANCE has on SK_G16 only access to the dual ported
423 * RAM and nowhere else.
424 */
425
426struct SK_ram
427{
428 struct init_block ib;
429 struct tmd tmde[TMDNUM];
430 struct rmd rmde[RMDNUM];
431 char tmdbuf[TMDNUM][PKT_BUF_SZ];
432 char rmdbuf[RMDNUM][PKT_BUF_SZ];
433};
434
435/*
436 * Structure where all necessary information is for ring buffer
437 * management and statistics.
438 */
439
440struct priv
441{
442 struct SK_ram *ram; /* dual ported ram structure */
443 struct rmd *rmdhead; /* start of receive ring descriptors */
444 struct tmd *tmdhead; /* start of transmit ring descriptors */
445 int rmdnum; /* actual used ring descriptor */
446 int tmdnum; /* actual transmit descriptor for transmitting data */
447 int tmdlast; /* last sent descriptor used for error handling, etc */
448 void *rmdbufs[RMDNUM]; /* pointer to the receive buffers */
449 void *tmdbufs[TMDNUM]; /* pointer to the transmit buffers */
450 struct net_device_stats stats; /* Device driver statistics */
451};
452
453/* global variable declaration */
454
455/* IRQ map used to reserve a IRQ (see SK_open()) */
456
457/* static variables */
458
459static SK_RAM *board; /* pointer to our memory mapped board components */
460static DEFINE_SPINLOCK(SK_lock);
461
462/* Macros */
463
464
465/* Function Prototypes */
466
467/*
468 * Device Driver functions
469 * -----------------------
470 * See for short explanation of each function its definitions header.
471 */
472
473static int SK_probe(struct net_device *dev, short ioaddr);
474
475static void SK_timeout(struct net_device *dev);
476static int SK_open(struct net_device *dev);
477static int SK_send_packet(struct sk_buff *skb, struct net_device *dev);
478static irqreturn_t SK_interrupt(int irq, void *dev_id, struct pt_regs * regs);
479static void SK_rxintr(struct net_device *dev);
480static void SK_txintr(struct net_device *dev);
481static int SK_close(struct net_device *dev);
482
483static struct net_device_stats *SK_get_stats(struct net_device *dev);
484
485unsigned int SK_rom_addr(void);
486
487static void set_multicast_list(struct net_device *dev);
488
489/*
490 * LANCE Functions
491 * ---------------
492 */
493
494static int SK_lance_init(struct net_device *dev, unsigned short mode);
495void SK_reset_board(void);
496void SK_set_RAP(int reg_number);
497int SK_read_reg(int reg_number);
498int SK_rread_reg(void);
499void SK_write_reg(int reg_number, int value);
500
501/*
502 * Debugging functions
503 * -------------------
504 */
505
506void SK_print_pos(struct net_device *dev, char *text);
507void SK_print_dev(struct net_device *dev, char *text);
508void SK_print_ram(struct net_device *dev);
509
510
511/*-
512 * Function : SK_init
513 * Author : Patrick J.D. Weichmann
514 * Date Created : 94/05/26
515 *
516 * Description : Check for a SK_G16 network adaptor and initialize it.
517 * This function gets called by dev_init which initializes
518 * all Network devices.
519 *
520 * Parameters : I : struct net_device *dev - structure preconfigured
521 * from Space.c
522 * Return Value : 0 = Driver Found and initialized
523 * Errors : ENODEV - no device found
524 * ENXIO - not probed
525 * Globals : None
526 * Update History :
527 * YY/MM/DD uid Description
528-*/
529
530static int io; /* 0 == probe */
531
532/*
533 * Check for a network adaptor of this type, and return '0' if one exists.
534 * If dev->base_addr == 0, probe all likely locations.
535 * If dev->base_addr == 1, always return failure.
536 */
537
538struct net_device * __init SK_init(int unit)
539{
540 int *port, ports[] = SK_IO_PORTS; /* SK_G16 supported ports */
541 static unsigned version_printed;
542 struct net_device *dev = alloc_etherdev(sizeof(struct priv));
543 int err = -ENODEV;
544
545 if (!dev)
546 return ERR_PTR(-ENOMEM);
547
548 if (unit >= 0) {
549 sprintf(dev->name, "eth%d", unit);
550 netdev_boot_setup_check(dev);
551 io = dev->base_addr;
552 }
553
554 if (version_printed++ == 0)
555 PRINTK(("%s: %s", SK_NAME, rcsid));
556
557 if (io > 0xff) { /* Check a single specified address */
558 err = -EBUSY;
559 /* Check if on specified address is a SK_G16 */
560 if (request_region(io, ETHERCARD_TOTAL_SIZE, "sk_g16")) {
561 err = SK_probe(dev, io);
562 if (!err)
563 goto got_it;
564 release_region(io, ETHERCARD_TOTAL_SIZE);
565 }
566 } else if (io > 0) { /* Don't probe at all */
567 err = -ENXIO;
568 } else {
569 /* Autoprobe base_addr */
570 for (port = &ports[0]; *port; port++) {
571 io = *port;
572
573 /* Check if I/O Port region is used by another board */
574 if (!request_region(io, ETHERCARD_TOTAL_SIZE, "sk_g16"))
575 continue; /* Try next Port address */
576
577 /* Check if at ioaddr is a SK_G16 */
578 if (SK_probe(dev, io) == 0)
579 goto got_it;
580
581 release_region(io, ETHERCARD_TOTAL_SIZE);
582 }
583 }
584err_out:
585 free_netdev(dev);
586 return ERR_PTR(err);
587
588got_it:
589 err = register_netdev(dev);
590 if (err) {
591 release_region(dev->base_addr, ETHERCARD_TOTAL_SIZE);
592 goto err_out;
593 }
594 return dev;
595
596} /* End of SK_init */
597
598
599MODULE_AUTHOR("Patrick J.D. Weichmann");
600MODULE_DESCRIPTION("Schneider & Koch G16 Ethernet Device Driver");
601MODULE_LICENSE("GPL");
602MODULE_PARM(io, "i");
603MODULE_PARM_DESC(io, "0 to probe common ports (unsafe), or the I/O base of the board");
604
605
606#ifdef MODULE
607
608static struct net_device *SK_dev;
609
610static int __init SK_init_module (void)
611{
612 SK_dev = SK_init(-1);
613 return IS_ERR(SK_dev) ? PTR_ERR(SK_dev) : 0;
614}
615
616static void __exit SK_cleanup_module (void)
617{
618 unregister_netdev(SK_dev);
619 release_region(SK_dev->base_addr, ETHERCARD_TOTAL_SIZE);
620 free_netdev(SK_dev);
621}
622
623module_init(SK_init_module);
624module_exit(SK_cleanup_module);
625#endif
626
627
628/*-
629 * Function : SK_probe
630 * Author : Patrick J.D. Weichmann
631 * Date Created : 94/05/26
632 *
633 * Description : This function is called by SK_init and
634 * does the main part of initialization.
635 *
636 * Parameters : I : struct net_device *dev - SK_G16 device structure
637 * I : short ioaddr - I/O Port address where POS is.
638 * Return Value : 0 = Initialization done
639 * Errors : ENODEV - No SK_G16 found
640 * -1 - Configuration problem
641 * Globals : board - pointer to SK_RAM
642 * Update History :
643 * YY/MM/DD uid Description
644 * 94/06/30 pwe SK_ADDR now checked and at the correct place
645-*/
646
647int __init SK_probe(struct net_device *dev, short ioaddr)
648{
649 int i,j; /* Counters */
650 int sk_addr_flag = 0; /* SK ADDR correct? 1 - no, 0 - yes */
651 unsigned int rom_addr; /* used to store RAM address used for POS_ADDR */
652
653 struct priv *p = netdev_priv(dev); /* SK_G16 private structure */
654
655 if (inb(SK_POS0) != SK_IDLOW || inb(SK_POS1) != SK_IDHIGH)
656 return -ENODEV;
657 dev->base_addr = ioaddr;
658
659 if (SK_ADDR & 0x3fff || SK_ADDR < 0xa0000)
660 {
661
662 sk_addr_flag = 1;
663
664 /*
665 * Now here we could use a routine which searches for a free
666 * place in the ram and set SK_ADDR if found. TODO.
667 */
668 }
669
670 if (SK_BOOT_ROM) /* Shall we keep Boot_ROM on ? */
671 {
672 PRINTK(("## %s: SK_BOOT_ROM is set.\n", SK_NAME));
673
674 rom_addr = SK_rom_addr();
675
676 if (rom_addr == 0) /* No Boot_ROM found */
677 {
678 if (sk_addr_flag) /* No or Invalid SK_ADDR is defined */
679 {
680 printk("%s: SK_ADDR %#08x is not valid. Check configuration.\n",
681 dev->name, SK_ADDR);
682 return -1;
683 }
684
685 rom_addr = SK_ADDR; /* assign predefined address */
686
687 PRINTK(("## %s: NO Bootrom found \n", SK_NAME));
688
689 outb(SK_ROM_RAM_OFF, SK_POS2); /* Boot_ROM + RAM off */
690 outb(POS_ADDR, SK_POS3); /* Set RAM address */
691 outb(SK_RAM_ON, SK_POS2); /* enable RAM */
692 }
693 else if (rom_addr == SK_ADDR)
694 {
695 printk("%s: RAM + ROM are set to the same address %#08x\n"
696 " Check configuration. Now switching off Boot_ROM\n",
697 SK_NAME, rom_addr);
698
699 outb(SK_ROM_RAM_OFF, SK_POS2); /* Boot_ROM + RAM off*/
700 outb(POS_ADDR, SK_POS3); /* Set RAM address */
701 outb(SK_RAM_ON, SK_POS2); /* enable RAM */
702 }
703 else
704 {
705 PRINTK(("## %s: Found ROM at %#08x\n", SK_NAME, rom_addr));
706 PRINTK(("## %s: Keeping Boot_ROM on\n", SK_NAME));
707
708 if (sk_addr_flag) /* No or Invalid SK_ADDR is defined */
709 {
710 printk("%s: SK_ADDR %#08x is not valid. Check configuration.\n",
711 dev->name, SK_ADDR);
712 return -1;
713 }
714
715 rom_addr = SK_ADDR;
716
717 outb(SK_ROM_RAM_OFF, SK_POS2); /* Boot_ROM + RAM off */
718 outb(POS_ADDR, SK_POS3); /* Set RAM address */
719 outb(SK_ROM_RAM_ON, SK_POS2); /* RAM on, BOOT_ROM on */
720 }
721 }
722 else /* Don't keep Boot_ROM */
723 {
724 PRINTK(("## %s: SK_BOOT_ROM is not set.\n", SK_NAME));
725
726 if (sk_addr_flag) /* No or Invalid SK_ADDR is defined */
727 {
728 printk("%s: SK_ADDR %#08x is not valid. Check configuration.\n",
729 dev->name, SK_ADDR);
730 return -1;
731 }
732
733 rom_addr = SK_rom_addr(); /* Try to find a Boot_ROM */
734
735 /* IF we find a Boot_ROM disable it */
736
737 outb(SK_ROM_RAM_OFF, SK_POS2); /* Boot_ROM + RAM off */
738
739 /* We found a Boot_ROM and it's gone. Set RAM address on
740 * Boot_ROM address.
741 */
742
743 if (rom_addr)
744 {
745 printk("%s: We found Boot_ROM at %#08x. Now setting RAM on"
746 "that address\n", SK_NAME, rom_addr);
747
748 outb(POS_ADDR, SK_POS3); /* Set RAM on Boot_ROM address */
749 }
750 else /* We did not find a Boot_ROM, use predefined SK_ADDR for ram */
751 {
752 if (sk_addr_flag) /* No or Invalid SK_ADDR is defined */
753 {
754 printk("%s: SK_ADDR %#08x is not valid. Check configuration.\n",
755 dev->name, SK_ADDR);
756 return -1;
757 }
758
759 rom_addr = SK_ADDR;
760
761 outb(POS_ADDR, SK_POS3); /* Set RAM address */
762 }
763 outb(SK_RAM_ON, SK_POS2); /* enable RAM */
764 }
765
766#ifdef SK_DEBUG
767 SK_print_pos(dev, "POS registers after ROM, RAM config");
768#endif
769
770 board = (SK_RAM *) isa_bus_to_virt(rom_addr);
771
772 /* Read in station address */
773 for (i = 0, j = 0; i < ETH_ALEN; i++, j+=2)
774 {
775 dev->dev_addr[i] = readb(board->rom+j);
776 }
777
778 /* Check for manufacturer code */
779 if (!(dev->dev_addr[0] == SK_MAC0 &&
780 dev->dev_addr[1] == SK_MAC1 &&
781 dev->dev_addr[2] == SK_MAC2) )
782 {
783 PRINTK(("## %s: We did not find SK_G16 at RAM location.\n",
784 SK_NAME));
785 return -ENODEV; /* NO SK_G16 found */
786 }
787
788 printk("%s: %s found at %#3x, HW addr: %#04x:%02x:%02x:%02x:%02x:%02x\n",
789 dev->name,
790 "Schneider & Koch Netcard",
791 (unsigned int) dev->base_addr,
792 dev->dev_addr[0],
793 dev->dev_addr[1],
794 dev->dev_addr[2],
795 dev->dev_addr[3],
796 dev->dev_addr[4],
797 dev->dev_addr[5]);
798
799 memset((char *) dev->priv, 0, sizeof(struct priv)); /* clear memory */
800
801 /* Assign our Device Driver functions */
802
803 dev->open = SK_open;
804 dev->stop = SK_close;
805 dev->hard_start_xmit = SK_send_packet;
806 dev->get_stats = SK_get_stats;
807 dev->set_multicast_list = set_multicast_list;
808 dev->tx_timeout = SK_timeout;
809 dev->watchdog_timeo = HZ/7;
810
811
812 dev->flags &= ~IFF_MULTICAST;
813
814 /* Initialize private structure */
815
816 p->ram = (struct SK_ram *) rom_addr; /* Set dual ported RAM addr */
817 p->tmdhead = &(p->ram)->tmde[0]; /* Set TMD head */
818 p->rmdhead = &(p->ram)->rmde[0]; /* Set RMD head */
819
820 /* Initialize buffer pointers */
821
822 for (i = 0; i < TMDNUM; i++)
823 {
824 p->tmdbufs[i] = &(p->ram)->tmdbuf[i];
825 }
826
827 for (i = 0; i < RMDNUM; i++)
828 {
829 p->rmdbufs[i] = &(p->ram)->rmdbuf[i];
830 }
831
832#ifdef SK_DEBUG
833 SK_print_pos(dev, "End of SK_probe");
834 SK_print_ram(dev);
835#endif
836 return 0; /* Initialization done */
837} /* End of SK_probe() */
838
839
840/*-
841 * Function : SK_open
842 * Author : Patrick J.D. Weichmann
843 * Date Created : 94/05/26
844 *
845 * Description : This function is called sometimes after booting
846 * when ifconfig program is run.
847 *
848 * This function requests an IRQ, sets the correct
849 * IRQ in the card. Then calls SK_lance_init() to
850 * init and start the LANCE chip. Then if everything is
851 * ok returns with 0 (OK), which means SK_G16 is now
852 * opened and operational.
853 *
854 * (Called by dev_open() /net/inet/dev.c)
855 *
856 * Parameters : I : struct net_device *dev - SK_G16 device structure
857 * Return Value : 0 - Device opened
858 * Errors : -EAGAIN - Open failed
859 * Side Effects : None
860 * Update History :
861 * YY/MM/DD uid Description
862-*/
863
864static int SK_open(struct net_device *dev)
865{
866 int i = 0;
867 int irqval = 0;
868 int ioaddr = dev->base_addr;
869
870 int irqtab[] = SK_IRQS;
871
872 struct priv *p = netdev_priv(dev);
873
874 PRINTK(("## %s: At beginning of SK_open(). CSR0: %#06x\n",
875 SK_NAME, SK_read_reg(CSR0)));
876
877 if (dev->irq == 0) /* Autoirq */
878 {
879 i = 0;
880
881 /*
882 * Check if one IRQ out of SK_IRQS is free and install
883 * interrupt handler.
884 * Most done by request_irq().
885 * irqval: 0 - interrupt handler installed for IRQ irqtab[i]
886 * -EBUSY - interrupt busy
887 * -EINVAL - irq > 15 or handler = NULL
888 */
889
890 do
891 {
892 irqval = request_irq(irqtab[i], &SK_interrupt, 0, "sk_g16", dev);
893 i++;
894 } while (irqval && irqtab[i]);
895
896 if (irqval) /* We tried every possible IRQ but no success */
897 {
898 printk("%s: unable to get an IRQ\n", dev->name);
899 return -EAGAIN;
900 }
901
902 dev->irq = irqtab[--i];
903
904 outb(i<<2, SK_POS4); /* Set Card on probed IRQ */
905
906 }
907 else if (dev->irq == 2) /* IRQ2 is always IRQ9 */
908 {
909 if (request_irq(9, &SK_interrupt, 0, "sk_g16", dev))
910 {
911 printk("%s: unable to get IRQ 9\n", dev->name);
912 return -EAGAIN;
913 }
914 dev->irq = 9;
915
916 /*
917 * Now we set card on IRQ2.
918 * This can be confusing, but remember that IRQ2 on the network
919 * card is in reality IRQ9
920 */
921 outb(0x08, SK_POS4); /* set card to IRQ2 */
922
923 }
924 else /* Check IRQ as defined in Space.c */
925 {
926 int i = 0;
927
928 /* check if IRQ free and valid. Then install Interrupt handler */
929
930 if (request_irq(dev->irq, &SK_interrupt, 0, "sk_g16", dev))
931 {
932 printk("%s: unable to get selected IRQ\n", dev->name);
933 return -EAGAIN;
934 }
935
936 switch(dev->irq)
937 {
938 case 3: i = 0;
939 break;
940 case 5: i = 1;
941 break;
942 case 2: i = 2;
943 break;
944 case 11:i = 3;
945 break;
946 default:
947 printk("%s: Preselected IRQ %d is invalid for %s boards",
948 dev->name,
949 dev->irq,
950 SK_NAME);
951 return -EAGAIN;
952 }
953
954 outb(i<<2, SK_POS4); /* Set IRQ on card */
955 }
956
957 printk("%s: Schneider & Koch G16 at %#3x, IRQ %d, shared mem at %#08x\n",
958 dev->name, (unsigned int)dev->base_addr,
959 (int) dev->irq, (unsigned int) p->ram);
960
961 if (!(i = SK_lance_init(dev, 0))) /* LANCE init OK? */
962 {
963 netif_start_queue(dev);
964
965#ifdef SK_DEBUG
966
967 /*
968 * This debug block tries to stop LANCE,
969 * reinit LANCE with transmitter and receiver disabled,
970 * then stop again and reinit with NORMAL_MODE
971 */
972
973 printk("## %s: After lance init. CSR0: %#06x\n",
974 SK_NAME, SK_read_reg(CSR0));
975 SK_write_reg(CSR0, CSR0_STOP);
976 printk("## %s: LANCE stopped. CSR0: %#06x\n",
977 SK_NAME, SK_read_reg(CSR0));
978 SK_lance_init(dev, MODE_DTX | MODE_DRX);
979 printk("## %s: Reinit with DTX + DRX off. CSR0: %#06x\n",
980 SK_NAME, SK_read_reg(CSR0));
981 SK_write_reg(CSR0, CSR0_STOP);
982 printk("## %s: LANCE stopped. CSR0: %#06x\n",
983 SK_NAME, SK_read_reg(CSR0));
984 SK_lance_init(dev, MODE_NORMAL);
985 printk("## %s: LANCE back to normal mode. CSR0: %#06x\n",
986 SK_NAME, SK_read_reg(CSR0));
987 SK_print_pos(dev, "POS regs before returning OK");
988
989#endif /* SK_DEBUG */
990
991 return 0; /* SK_open() is successful */
992 }
993 else /* LANCE init failed */
994 {
995
996 PRINTK(("## %s: LANCE init failed: CSR0: %#06x\n",
997 SK_NAME, SK_read_reg(CSR0)));
998
999 return -EAGAIN;
1000 }
1001
1002} /* End of SK_open() */
1003
1004
1005/*-
1006 * Function : SK_lance_init
1007 * Author : Patrick J.D. Weichmann
1008 * Date Created : 94/05/26
1009 *
1010 * Description : Reset LANCE chip, fill RMD, TMD structures with
1011 * start values and Start LANCE.
1012 *
1013 * Parameters : I : struct net_device *dev - SK_G16 device structure
1014 * I : int mode - put LANCE into "mode" see data-sheet for
1015 * more info.
1016 * Return Value : 0 - Init done
1017 * Errors : -1 - Init failed
1018 * Update History :
1019 * YY/MM/DD uid Description
1020-*/
1021
1022static int SK_lance_init(struct net_device *dev, unsigned short mode)
1023{
1024 int i;
1025 unsigned long flags;
1026 struct priv *p = netdev_priv(dev);
1027 struct tmd *tmdp;
1028 struct rmd *rmdp;
1029
1030 PRINTK(("## %s: At beginning of LANCE init. CSR0: %#06x\n",
1031 SK_NAME, SK_read_reg(CSR0)));
1032
1033 /* Reset LANCE */
1034 SK_reset_board();
1035
1036 /* Initialize TMD's with start values */
1037 p->tmdnum = 0; /* First descriptor for transmitting */
1038 p->tmdlast = 0; /* First descriptor for reading stats */
1039
1040 for (i = 0; i < TMDNUM; i++) /* Init all TMD's */
1041 {
1042 tmdp = p->tmdhead + i;
1043
1044 writel((unsigned long) p->tmdbufs[i], tmdp->u.buffer); /* assign buffer */
1045
1046 /* Mark TMD as start and end of packet */
1047 writeb(TX_STP | TX_ENP, &tmdp->u.s.status);
1048 }
1049
1050
1051 /* Initialize RMD's with start values */
1052
1053 p->rmdnum = 0; /* First RMD which will be used */
1054
1055 for (i = 0; i < RMDNUM; i++) /* Init all RMD's */
1056 {
1057 rmdp = p->rmdhead + i;
1058
1059
1060 writel((unsigned long) p->rmdbufs[i], rmdp->u.buffer); /* assign buffer */
1061
1062 /*
1063 * LANCE must be owner at beginning so that he can fill in
1064 * receiving packets, set status and release RMD
1065 */
1066
1067 writeb(RX_OWN, &rmdp->u.s.status);
1068
1069 writew(-PKT_BUF_SZ, &rmdp->blen); /* Buffer Size (two's complement) */
1070
1071 writeb(0, &rmdp->mlen); /* init message length */
1072
1073 }
1074
1075 /* Fill LANCE Initialize Block */
1076
1077 writew(mode, (&((p->ram)->ib.mode))); /* Set operation mode */
1078
1079 for (i = 0; i < ETH_ALEN; i++) /* Set physical address */
1080 {
1081 writeb(dev->dev_addr[i], (&((p->ram)->ib.paddr[i])));
1082 }
1083
1084 for (i = 0; i < 8; i++) /* Set multicast, logical address */
1085 {
1086 writeb(0, (&((p->ram)->ib.laddr[i]))); /* We do not use logical addressing */
1087 }
1088
1089 /* Set ring descriptor pointers and set number of descriptors */
1090
1091 writel((int)p->rmdhead | RMDNUMMASK, (&((p->ram)->ib.rdrp)));
1092 writel((int)p->tmdhead | TMDNUMMASK, (&((p->ram)->ib.tdrp)));
1093
1094 /* Prepare LANCE Control and Status Registers */
1095
1096 spin_lock_irqsave(&SK_lock, flags);
1097
1098 SK_write_reg(CSR3, CSR3_ACON); /* Ale Control !!!THIS MUST BE SET!!!! */
1099
1100 /*
1101 * LANCE addresses the RAM from 0x0000 to 0x3fbf and has no access to
1102 * PC Memory locations.
1103 *
1104 * In structure SK_ram is defined that the first thing in ram
1105 * is the initialization block. So his address is for LANCE always
1106 * 0x0000
1107 *
1108 * CSR1 contains low order bits 15:0 of initialization block address
1109 * CSR2 is built of:
1110 * 7:0 High order bits 23:16 of initialization block address
1111 * 15:8 reserved, must be 0
1112 */
1113
1114 /* Set initialization block address (must be on word boundary) */
1115 SK_write_reg(CSR1, 0); /* Set low order bits 15:0 */
1116 SK_write_reg(CSR2, 0); /* Set high order bits 23:16 */
1117
1118
1119 PRINTK(("## %s: After setting CSR1-3. CSR0: %#06x\n",
1120 SK_NAME, SK_read_reg(CSR0)));
1121
1122 /* Initialize LANCE */
1123
1124 /*
1125 * INIT = Initialize, when set, causes the LANCE to begin the
1126 * initialization procedure and access the Init Block.
1127 */
1128
1129 SK_write_reg(CSR0, CSR0_INIT);
1130
1131 spin_unlock_irqrestore(&SK_lock, flags);
1132
1133 /* Wait until LANCE finished initialization */
1134
1135 SK_set_RAP(CSR0); /* Register Address Pointer to CSR0 */
1136
1137 for (i = 0; (i < 100) && !(SK_rread_reg() & CSR0_IDON); i++)
1138 ; /* Wait until init done or go ahead if problems (i>=100) */
1139
1140 if (i >= 100) /* Something is wrong ! */
1141 {
1142 printk("%s: can't init am7990, status: %04x "
1143 "init_block: %#08x\n",
1144 dev->name, (int) SK_read_reg(CSR0),
1145 (unsigned int) &(p->ram)->ib);
1146
1147#ifdef SK_DEBUG
1148 SK_print_pos(dev, "LANCE INIT failed");
1149 SK_print_dev(dev,"Device Structure:");
1150#endif
1151
1152 return -1; /* LANCE init failed */
1153 }
1154
1155 PRINTK(("## %s: init done after %d ticks\n", SK_NAME, i));
1156
1157 /* Clear Initialize done, enable Interrupts, start LANCE */
1158
1159 SK_write_reg(CSR0, CSR0_IDON | CSR0_INEA | CSR0_STRT);
1160
1161 PRINTK(("## %s: LANCE started. CSR0: %#06x\n", SK_NAME,
1162 SK_read_reg(CSR0)));
1163
1164 return 0; /* LANCE is up and running */
1165
1166} /* End of SK_lance_init() */
1167
1168
1169
1170/*-
1171 * Function : SK_send_packet
1172 * Author : Patrick J.D. Weichmann
1173 * Date Created : 94/05/27
1174 *
1175 * Description : Writes an socket buffer into a transmit descriptor
1176 * and starts transmission.
1177 *
1178 * Parameters : I : struct sk_buff *skb - packet to transfer
1179 * I : struct net_device *dev - SK_G16 device structure
1180 * Return Value : 0 - OK
1181 * 1 - Could not transmit (dev_queue_xmit will queue it)
1182 * and try to sent it later
1183 * Globals : None
1184 * Side Effects : None
1185 * Update History :
1186 * YY/MM/DD uid Description
1187-*/
1188
1189static void SK_timeout(struct net_device *dev)
1190{
1191 printk(KERN_WARNING "%s: xmitter timed out, try to restart!\n", dev->name);
1192 SK_lance_init(dev, MODE_NORMAL); /* Reinit LANCE */
1193 netif_wake_queue(dev); /* Clear Transmitter flag */
1194 dev->trans_start = jiffies; /* Mark Start of transmission */
1195}
1196
1197static int SK_send_packet(struct sk_buff *skb, struct net_device *dev)
1198{
1199 struct priv *p = netdev_priv(dev);
1200 struct tmd *tmdp;
1201 static char pad[64];
1202
1203 PRINTK2(("## %s: SK_send_packet() called, CSR0 %#04x.\n",
1204 SK_NAME, SK_read_reg(CSR0)));
1205
1206
1207 /*
1208 * Block a timer-based transmit from overlapping.
1209 * This means check if we are already in.
1210 */
1211
1212 netif_stop_queue (dev);
1213
1214 {
1215
1216 /* Evaluate Packet length */
1217 short len = ETH_ZLEN < skb->len ? skb->len : ETH_ZLEN;
1218
1219 tmdp = p->tmdhead + p->tmdnum; /* Which descriptor for transmitting */
1220
1221 /* Fill in Transmit Message Descriptor */
1222
1223 /* Copy data into dual ported ram */
1224
1225 memcpy_toio((tmdp->u.buffer & 0x00ffffff), skb->data, skb->len);
1226 if (len != skb->len)
1227 memcpy_toio((tmdp->u.buffer & 0x00ffffff) + skb->len, pad, len-skb->len);
1228
1229 writew(-len, &tmdp->blen); /* set length to transmit */
1230
1231 /*
1232 * Packet start and end is always set because we use the maximum
1233 * packet length as buffer length.
1234 * Relinquish ownership to LANCE
1235 */
1236
1237 writeb(TX_OWN | TX_STP | TX_ENP, &tmdp->u.s.status);
1238
1239 /* Start Demand Transmission */
1240 SK_write_reg(CSR0, CSR0_TDMD | CSR0_INEA);
1241
1242 dev->trans_start = jiffies; /* Mark start of transmission */
1243
1244 /* Set pointer to next transmit buffer */
1245 p->tmdnum++;
1246 p->tmdnum &= TMDNUM-1;
1247
1248 /* Do we own the next transmit buffer ? */
1249 if (! (readb(&((p->tmdhead + p->tmdnum)->u.s.status)) & TX_OWN) )
1250 {
1251 /*
1252 * We own next buffer and are ready to transmit, so
1253 * clear busy flag
1254 */
1255 netif_start_queue(dev);
1256 }
1257
1258 p->stats.tx_bytes += skb->len;
1259
1260 }
1261
1262 dev_kfree_skb(skb);
1263 return 0;
1264} /* End of SK_send_packet */
1265
1266
1267/*-
1268 * Function : SK_interrupt
1269 * Author : Patrick J.D. Weichmann
1270 * Date Created : 94/05/27
1271 *
1272 * Description : SK_G16 interrupt handler which checks for LANCE
1273 * Errors, handles transmit and receive interrupts
1274 *
1275 * Parameters : I : int irq, void *dev_id, struct pt_regs * regs -
1276 * Return Value : None
1277 * Errors : None
1278 * Globals : None
1279 * Side Effects : None
1280 * Update History :
1281 * YY/MM/DD uid Description
1282-*/
1283
1284static irqreturn_t SK_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1285{
1286 int csr0;
1287 struct net_device *dev = dev_id;
1288 struct priv *p = netdev_priv(dev);
1289
1290
1291 PRINTK2(("## %s: SK_interrupt(). status: %#06x\n",
1292 SK_NAME, SK_read_reg(CSR0)));
1293
1294 if (dev == NULL)
1295 {
1296 printk("SK_interrupt(): IRQ %d for unknown device.\n", irq);
1297 }
1298
1299 spin_lock (&SK_lock);
1300
1301 csr0 = SK_read_reg(CSR0); /* store register for checking */
1302
1303 /*
1304 * Acknowledge all of the current interrupt sources, disable
1305 * Interrupts (INEA = 0)
1306 */
1307
1308 SK_write_reg(CSR0, csr0 & CSR0_CLRALL);
1309
1310 if (csr0 & CSR0_ERR) /* LANCE Error */
1311 {
1312 printk("%s: error: %04x\n", dev->name, csr0);
1313
1314 if (csr0 & CSR0_MISS) /* No place to store packet ? */
1315 {
1316 p->stats.rx_dropped++;
1317 }
1318 }
1319
1320 if (csr0 & CSR0_RINT) /* Receive Interrupt (packet arrived) */
1321 {
1322 SK_rxintr(dev);
1323 }
1324
1325 if (csr0 & CSR0_TINT) /* Transmit interrupt (packet sent) */
1326 {
1327 SK_txintr(dev);
1328 }
1329
1330 SK_write_reg(CSR0, CSR0_INEA); /* Enable Interrupts */
1331
1332 spin_unlock (&SK_lock);
1333 return IRQ_HANDLED;
1334} /* End of SK_interrupt() */
1335
1336
1337/*-
1338 * Function : SK_txintr
1339 * Author : Patrick J.D. Weichmann
1340 * Date Created : 94/05/27
1341 *
1342 * Description : After sending a packet we check status, update
1343 * statistics and relinquish ownership of transmit
1344 * descriptor ring.
1345 *
1346 * Parameters : I : struct net_device *dev - SK_G16 device structure
1347 * Return Value : None
1348 * Errors : None
1349 * Globals : None
1350 * Update History :
1351 * YY/MM/DD uid Description
1352-*/
1353
1354static void SK_txintr(struct net_device *dev)
1355{
1356 int tmdstat;
1357 struct tmd *tmdp;
1358 struct priv *p = netdev_priv(dev);
1359
1360
1361 PRINTK2(("## %s: SK_txintr() status: %#06x\n",
1362 SK_NAME, SK_read_reg(CSR0)));
1363
1364 tmdp = p->tmdhead + p->tmdlast; /* Which buffer we sent at last ? */
1365
1366 /* Set next buffer */
1367 p->tmdlast++;
1368 p->tmdlast &= TMDNUM-1;
1369
1370 tmdstat = readb(&tmdp->u.s.status);
1371
1372 /*
1373 * We check status of transmitted packet.
1374 * see LANCE data-sheet for error explanation
1375 */
1376 if (tmdstat & TX_ERR) /* Error occurred */
1377 {
1378 int stat2 = readw(&tmdp->status2);
1379
1380 printk("%s: TX error: %04x %04x\n", dev->name, tmdstat, stat2);
1381
1382 if (stat2 & TX_TDR) /* TDR problems? */
1383 {
1384 printk("%s: tdr-problems \n", dev->name);
1385 }
1386
1387 if (stat2 & TX_RTRY) /* Failed in 16 attempts to transmit ? */
1388 p->stats.tx_aborted_errors++;
1389 if (stat2 & TX_LCOL) /* Late collision ? */
1390 p->stats.tx_window_errors++;
1391 if (stat2 & TX_LCAR) /* Loss of Carrier ? */
1392 p->stats.tx_carrier_errors++;
1393 if (stat2 & TX_UFLO) /* Underflow error ? */
1394 {
1395 p->stats.tx_fifo_errors++;
1396
1397 /*
1398 * If UFLO error occurs it will turn transmitter of.
1399 * So we must reinit LANCE
1400 */
1401
1402 SK_lance_init(dev, MODE_NORMAL);
1403 }
1404
1405 p->stats.tx_errors++;
1406
1407 writew(0, &tmdp->status2); /* Clear error flags */
1408 }
1409 else if (tmdstat & TX_MORE) /* Collisions occurred ? */
1410 {
1411 /*
1412 * Here I have a problem.
1413 * I only know that there must be one or up to 15 collisions.
1414 * That's why TX_MORE is set, because after 16 attempts TX_RTRY
1415 * will be set which means couldn't send packet aborted transfer.
1416 *
1417 * First I did not have this in but then I thought at minimum
1418 * we see that something was not ok.
1419 * If anyone knows something better than this to handle this
1420 * please report it.
1421 */
1422
1423 p->stats.collisions++;
1424 }
1425 else /* Packet sent without any problems */
1426 {
1427 p->stats.tx_packets++;
1428 }
1429
1430 /*
1431 * We mark transmitter not busy anymore, because now we have a free
1432 * transmit descriptor which can be filled by SK_send_packet and
1433 * afterwards sent by the LANCE
1434 *
1435 * The function which do handle slow IRQ parts is do_bottom_half()
1436 * which runs at normal kernel priority, that means all interrupt are
1437 * enabled. (see kernel/irq.c)
1438 *
1439 * net_bh does something like this:
1440 * - check if already in net_bh
1441 * - try to transmit something from the send queue
1442 * - if something is in the receive queue send it up to higher
1443 * levels if it is a known protocol
1444 * - try to transmit something from the send queue
1445 */
1446
1447 netif_wake_queue(dev);
1448
1449} /* End of SK_txintr() */
1450
1451
1452/*-
1453 * Function : SK_rxintr
1454 * Author : Patrick J.D. Weichmann
1455 * Date Created : 94/05/27
1456 *
1457 * Description : Buffer sent, check for errors, relinquish ownership
1458 * of the receive message descriptor.
1459 *
1460 * Parameters : I : SK_G16 device structure
1461 * Return Value : None
1462 * Globals : None
1463 * Update History :
1464 * YY/MM/DD uid Description
1465-*/
1466
1467static void SK_rxintr(struct net_device *dev)
1468{
1469
1470 struct rmd *rmdp;
1471 int rmdstat;
1472 struct priv *p = netdev_priv(dev);
1473
1474 PRINTK2(("## %s: SK_rxintr(). CSR0: %#06x\n",
1475 SK_NAME, SK_read_reg(CSR0)));
1476
1477 rmdp = p->rmdhead + p->rmdnum;
1478
1479 /* As long as we own the next entry, check status and send
1480 * it up to higher layer
1481 */
1482
1483 while (!( (rmdstat = readb(&rmdp->u.s.status)) & RX_OWN))
1484 {
1485 /*
1486 * Start and end of packet must be set, because we use
1487 * the ethernet maximum packet length (1518) as buffer size.
1488 *
1489 * Because our buffers are at maximum OFLO and BUFF errors are
1490 * not to be concerned (see Data sheet)
1491 */
1492
1493 if ((rmdstat & (RX_STP | RX_ENP)) != (RX_STP | RX_ENP))
1494 {
1495 /* Start of a frame > 1518 Bytes ? */
1496
1497 if (rmdstat & RX_STP)
1498 {
1499 p->stats.rx_errors++; /* bad packet received */
1500 p->stats.rx_length_errors++; /* packet too long */
1501
1502 printk("%s: packet too long\n", dev->name);
1503 }
1504
1505 /*
1506 * All other packets will be ignored until a new frame with
1507 * start (RX_STP) set follows.
1508 *
1509 * What we do is just give descriptor free for new incoming
1510 * packets.
1511 */
1512
1513 writeb(RX_OWN, &rmdp->u.s.status); /* Relinquish ownership to LANCE */
1514
1515 }
1516 else if (rmdstat & RX_ERR) /* Receive Error ? */
1517 {
1518 printk("%s: RX error: %04x\n", dev->name, (int) rmdstat);
1519
1520 p->stats.rx_errors++;
1521
1522 if (rmdstat & RX_FRAM) p->stats.rx_frame_errors++;
1523 if (rmdstat & RX_CRC) p->stats.rx_crc_errors++;
1524
1525 writeb(RX_OWN, &rmdp->u.s.status); /* Relinquish ownership to LANCE */
1526
1527 }
1528 else /* We have a packet which can be queued for the upper layers */
1529 {
1530
1531 int len = readw(&rmdp->mlen) & 0x0fff; /* extract message length from receive buffer */
1532 struct sk_buff *skb;
1533
1534 skb = dev_alloc_skb(len+2); /* allocate socket buffer */
1535
1536 if (skb == NULL) /* Could not get mem ? */
1537 {
1538
1539 /*
1540 * Couldn't allocate sk_buffer so we give descriptor back
1541 * to Lance, update statistics and go ahead.
1542 */
1543
1544 writeb(RX_OWN, &rmdp->u.s.status); /* Relinquish ownership to LANCE */
1545 printk("%s: Couldn't allocate sk_buff, deferring packet.\n",
1546 dev->name);
1547 p->stats.rx_dropped++;
1548
1549 break; /* Jump out */
1550 }
1551
1552 /* Prepare sk_buff to queue for upper layers */
1553
1554 skb->dev = dev;
1555 skb_reserve(skb,2); /* Align IP header on 16 byte boundary */
1556
1557 /*
1558 * Copy data out of our receive descriptor into sk_buff.
1559 *
1560 * (rmdp->u.buffer & 0x00ffffff) -> get address of buffer and
1561 * ignore status fields)
1562 */
1563
1564 memcpy_fromio(skb_put(skb,len), (rmdp->u.buffer & 0x00ffffff), len);
1565
1566
1567 /*
1568 * Notify the upper protocol layers that there is another packet
1569 * to handle
1570 *
1571 * netif_rx() always succeeds. see /net/inet/dev.c for more.
1572 */
1573
1574 skb->protocol=eth_type_trans(skb,dev);
1575 netif_rx(skb); /* queue packet and mark it for processing */
1576
1577 /*
1578 * Packet is queued and marked for processing so we
1579 * free our descriptor and update statistics
1580 */
1581
1582 writeb(RX_OWN, &rmdp->u.s.status);
1583 dev->last_rx = jiffies;
1584 p->stats.rx_packets++;
1585 p->stats.rx_bytes += len;
1586
1587
1588 p->rmdnum++;
1589 p->rmdnum %= RMDNUM;
1590
1591 rmdp = p->rmdhead + p->rmdnum;
1592 }
1593 }
1594} /* End of SK_rxintr() */
1595
1596
1597/*-
1598 * Function : SK_close
1599 * Author : Patrick J.D. Weichmann
1600 * Date Created : 94/05/26
1601 *
1602 * Description : close gets called from dev_close() and should
1603 * deinstall the card (free_irq, mem etc).
1604 *
1605 * Parameters : I : struct net_device *dev - our device structure
1606 * Return Value : 0 - closed device driver
1607 * Errors : None
1608 * Globals : None
1609 * Update History :
1610 * YY/MM/DD uid Description
1611-*/
1612
1613/* I have tried to set BOOT_ROM on and RAM off but then, after a 'ifconfig
1614 * down' the system stops. So I don't shut set card to init state.
1615 */
1616
1617static int SK_close(struct net_device *dev)
1618{
1619
1620 PRINTK(("## %s: SK_close(). CSR0: %#06x\n",
1621 SK_NAME, SK_read_reg(CSR0)));
1622
1623 netif_stop_queue(dev); /* Transmitter busy */
1624
1625 printk("%s: Shutting %s down CSR0 %#06x\n", dev->name, SK_NAME,
1626 (int) SK_read_reg(CSR0));
1627
1628 SK_write_reg(CSR0, CSR0_STOP); /* STOP the LANCE */
1629
1630 free_irq(dev->irq, dev); /* Free IRQ */
1631
1632 return 0; /* always succeed */
1633
1634} /* End of SK_close() */
1635
1636
1637/*-
1638 * Function : SK_get_stats
1639 * Author : Patrick J.D. Weichmann
1640 * Date Created : 94/05/26
1641 *
1642 * Description : Return current status structure to upper layers.
1643 * It is called by sprintf_stats (dev.c).
1644 *
1645 * Parameters : I : struct net_device *dev - our device structure
1646 * Return Value : struct net_device_stats * - our current statistics
1647 * Errors : None
1648 * Side Effects : None
1649 * Update History :
1650 * YY/MM/DD uid Description
1651-*/
1652
1653static struct net_device_stats *SK_get_stats(struct net_device *dev)
1654{
1655
1656 struct priv *p = netdev_priv(dev);
1657
1658 PRINTK(("## %s: SK_get_stats(). CSR0: %#06x\n",
1659 SK_NAME, SK_read_reg(CSR0)));
1660
1661 return &p->stats; /* Return Device status */
1662
1663} /* End of SK_get_stats() */
1664
1665
1666/*-
1667 * Function : set_multicast_list
1668 * Author : Patrick J.D. Weichmann
1669 * Date Created : 94/05/26
1670 *
1671 * Description : This function gets called when a program performs
1672 * a SIOCSIFFLAGS call. Ifconfig does this if you call
1673 * 'ifconfig [-]allmulti' which enables or disables the
1674 * Promiscuous mode.
1675 * Promiscuous mode is when the Network card accepts all
1676 * packets, not only the packets which match our MAC
1677 * Address. It is useful for writing a network monitor,
1678 * but it is also a security problem. You have to remember
1679 * that all information on the net is not encrypted.
1680 *
1681 * Parameters : I : struct net_device *dev - SK_G16 device Structure
1682 * Return Value : None
1683 * Errors : None
1684 * Globals : None
1685 * Update History :
1686 * YY/MM/DD uid Description
1687 * 95/10/18 ACox New multicast calling scheme
1688-*/
1689
1690
1691/* Set or clear the multicast filter for SK_G16.
1692 */
1693
1694static void set_multicast_list(struct net_device *dev)
1695{
1696
1697 if (dev->flags&IFF_PROMISC)
1698 {
1699 /* Reinitialize LANCE with MODE_PROM set */
1700 SK_lance_init(dev, MODE_PROM);
1701 }
1702 else if (dev->mc_count==0 && !(dev->flags&IFF_ALLMULTI))
1703 {
1704 /* Reinitialize LANCE without MODE_PROM */
1705 SK_lance_init(dev, MODE_NORMAL);
1706 }
1707 else
1708 {
1709 /* Multicast with logical address filter on */
1710 /* Reinitialize LANCE without MODE_PROM */
1711 SK_lance_init(dev, MODE_NORMAL);
1712
1713 /* Not implemented yet. */
1714 }
1715} /* End of set_multicast_list() */
1716
1717
1718
1719/*-
1720 * Function : SK_rom_addr
1721 * Author : Patrick J.D. Weichmann
1722 * Date Created : 94/06/01
1723 *
1724 * Description : Try to find a Boot_ROM at all possible locations
1725 *
1726 * Parameters : None
1727 * Return Value : Address where Boot_ROM is
1728 * Errors : 0 - Did not find Boot_ROM
1729 * Globals : None
1730 * Update History :
1731 * YY/MM/DD uid Description
1732-*/
1733
1734unsigned int __init SK_rom_addr(void)
1735{
1736 int i,j;
1737 int rom_found = 0;
1738 unsigned int rom_location[] = SK_BOOT_ROM_LOCATIONS;
1739 unsigned char rom_id[] = SK_BOOT_ROM_ID;
1740 unsigned char test_byte;
1741
1742 /* Autodetect Boot_ROM */
1743 PRINTK(("## %s: Autodetection of Boot_ROM\n", SK_NAME));
1744
1745 for (i = 0; (rom_location[i] != 0) && (rom_found == 0); i++)
1746 {
1747
1748 PRINTK(("## Trying ROM location %#08x", rom_location[i]));
1749
1750 rom_found = 1;
1751 for (j = 0; j < 6; j++)
1752 {
1753 test_byte = readb(rom_location[i]+j);
1754 PRINTK((" %02x ", *test_byte));
1755
1756 if(test_byte != rom_id[j])
1757 {
1758 rom_found = 0;
1759 }
1760 }
1761 PRINTK(("\n"));
1762 }
1763
1764 if (rom_found == 1)
1765 {
1766 PRINTK(("## %s: Boot_ROM found at %#08x\n",
1767 SK_NAME, rom_location[(i-1)]));
1768
1769 return (rom_location[--i]);
1770 }
1771 else
1772 {
1773 PRINTK(("%s: No Boot_ROM found\n", SK_NAME));
1774 return 0;
1775 }
1776} /* End of SK_rom_addr() */
1777
1778
1779
1780/* LANCE access functions
1781 *
1782 * ! CSR1-3 can only be accessed when in CSR0 the STOP bit is set !
1783 */
1784
1785
1786/*-
1787 * Function : SK_reset_board
1788 *
1789 * Author : Patrick J.D. Weichmann
1790 *
1791 * Date Created : 94/05/25
1792 *
1793 * Description : This function resets SK_G16 and all components, but
1794 * POS registers are not changed
1795 *
1796 * Parameters : None
1797 * Return Value : None
1798 * Errors : None
1799 * Globals : SK_RAM *board - SK_RAM structure pointer
1800 *
1801 * Update History :
1802 * YY/MM/DD uid Description
1803-*/
1804
1805void SK_reset_board(void)
1806{
1807 writeb(0x00, SK_PORT); /* Reset active */
1808 mdelay(5); /* Delay min 5ms */
1809 writeb(SK_RESET, SK_PORT); /* Set back to normal operation */
1810
1811} /* End of SK_reset_board() */
1812
1813
1814/*-
1815 * Function : SK_set_RAP
1816 * Author : Patrick J.D. Weichmann
1817 * Date Created : 94/05/25
1818 *
1819 * Description : Set LANCE Register Address Port to register
1820 * for later data transfer.
1821 *
1822 * Parameters : I : reg_number - which CSR to read/write from/to
1823 * Return Value : None
1824 * Errors : None
1825 * Globals : SK_RAM *board - SK_RAM structure pointer
1826 * Update History :
1827 * YY/MM/DD uid Description
1828-*/
1829
1830void SK_set_RAP(int reg_number)
1831{
1832 writew(reg_number, SK_IOREG);
1833 writeb(SK_RESET | SK_RAP | SK_WREG, SK_PORT);
1834 writeb(SK_DOIO, SK_IOCOM);
1835
1836 while (readb(SK_PORT) & SK_IORUN)
1837 barrier();
1838} /* End of SK_set_RAP() */
1839
1840
1841/*-
1842 * Function : SK_read_reg
1843 * Author : Patrick J.D. Weichmann
1844 * Date Created : 94/05/25
1845 *
1846 * Description : Set RAP and read data from a LANCE CSR register
1847 *
1848 * Parameters : I : reg_number - which CSR to read from
1849 * Return Value : Register contents
1850 * Errors : None
1851 * Globals : SK_RAM *board - SK_RAM structure pointer
1852 * Update History :
1853 * YY/MM/DD uid Description
1854-*/
1855
1856int SK_read_reg(int reg_number)
1857{
1858 SK_set_RAP(reg_number);
1859
1860 writeb(SK_RESET | SK_RDATA | SK_RREG, SK_PORT);
1861 writeb(SK_DOIO, SK_IOCOM);
1862
1863 while (readb(SK_PORT) & SK_IORUN)
1864 barrier();
1865 return (readw(SK_IOREG));
1866
1867} /* End of SK_read_reg() */
1868
1869
1870/*-
1871 * Function : SK_rread_reg
1872 * Author : Patrick J.D. Weichmann
1873 * Date Created : 94/05/28
1874 *
1875 * Description : Read data from preseted register.
1876 * This function requires that you know which
1877 * Register is actually set. Be aware that CSR1-3
1878 * can only be accessed when in CSR0 STOP is set.
1879 *
1880 * Return Value : Register contents
1881 * Errors : None
1882 * Globals : SK_RAM *board - SK_RAM structure pointer
1883 * Update History :
1884 * YY/MM/DD uid Description
1885-*/
1886
1887int SK_rread_reg(void)
1888{
1889 writeb(SK_RESET | SK_RDATA | SK_RREG, SK_PORT);
1890
1891 writeb(SK_DOIO, SK_IOCOM);
1892
1893 while (readb(SK_PORT) & SK_IORUN)
1894 barrier();
1895 return (readw(SK_IOREG));
1896
1897} /* End of SK_rread_reg() */
1898
1899
1900/*-
1901 * Function : SK_write_reg
1902 * Author : Patrick J.D. Weichmann
1903 * Date Created : 94/05/25
1904 *
1905 * Description : This function sets the RAP then fills in the
1906 * LANCE I/O Reg and starts Transfer to LANCE.
1907 * It waits until transfer has ended which is max. 7 ms
1908 * and then it returns.
1909 *
1910 * Parameters : I : reg_number - which CSR to write to
1911 * I : value - what value to fill into register
1912 * Return Value : None
1913 * Errors : None
1914 * Globals : SK_RAM *board - SK_RAM structure pointer
1915 * Update History :
1916 * YY/MM/DD uid Description
1917-*/
1918
1919void SK_write_reg(int reg_number, int value)
1920{
1921 SK_set_RAP(reg_number);
1922
1923 writew(value, SK_IOREG);
1924 writeb(SK_RESET | SK_RDATA | SK_WREG, SK_PORT);
1925 writeb(SK_DOIO, SK_IOCOM);
1926
1927 while (readb(SK_PORT) & SK_IORUN)
1928 barrier();
1929} /* End of SK_write_reg */
1930
1931
1932
1933/*
1934 * Debugging functions
1935 * -------------------
1936 */
1937
1938/*-
1939 * Function : SK_print_pos
1940 * Author : Patrick J.D. Weichmann
1941 * Date Created : 94/05/25
1942 *
1943 * Description : This function prints out the 4 POS (Programmable
1944 * Option Select) Registers. Used mainly to debug operation.
1945 *
1946 * Parameters : I : struct net_device *dev - SK_G16 device structure
1947 * I : char * - Text which will be printed as title
1948 * Return Value : None
1949 * Errors : None
1950 * Update History :
1951 * YY/MM/DD uid Description
1952-*/
1953
1954void SK_print_pos(struct net_device *dev, char *text)
1955{
1956 int ioaddr = dev->base_addr;
1957
1958 unsigned char pos0 = inb(SK_POS0),
1959 pos1 = inb(SK_POS1),
1960 pos2 = inb(SK_POS2),
1961 pos3 = inb(SK_POS3),
1962 pos4 = inb(SK_POS4);
1963
1964
1965 printk("## %s: %s.\n"
1966 "## pos0=%#4x pos1=%#4x pos2=%#04x pos3=%#08x pos4=%#04x\n",
1967 SK_NAME, text, pos0, pos1, pos2, (pos3<<14), pos4);
1968
1969} /* End of SK_print_pos() */
1970
1971
1972
1973/*-
1974 * Function : SK_print_dev
1975 * Author : Patrick J.D. Weichmann
1976 * Date Created : 94/05/25
1977 *
1978 * Description : This function simply prints out the important fields
1979 * of the device structure.
1980 *
1981 * Parameters : I : struct net_device *dev - SK_G16 device structure
1982 * I : char *text - Title for printing
1983 * Return Value : None
1984 * Errors : None
1985 * Update History :
1986 * YY/MM/DD uid Description
1987-*/
1988
1989void SK_print_dev(struct net_device *dev, char *text)
1990{
1991 if (dev == NULL)
1992 {
1993 printk("## %s: Device Structure. %s\n", SK_NAME, text);
1994 printk("## DEVICE == NULL\n");
1995 }
1996 else
1997 {
1998 printk("## %s: Device Structure. %s\n", SK_NAME, text);
1999 printk("## Device Name: %s Base Address: %#06lx IRQ: %d\n",
2000 dev->name, dev->base_addr, dev->irq);
2001
2002 printk("## next device: %#08x init function: %#08x\n",
2003 (int) dev->next, (int) dev->init);
2004 }
2005
2006} /* End of SK_print_dev() */
2007
2008
2009
2010/*-
2011 * Function : SK_print_ram
2012 * Author : Patrick J.D. Weichmann
2013 * Date Created : 94/06/02
2014 *
2015 * Description : This function is used to check how are things set up
2016 * in the 16KB RAM. Also the pointers to the receive and
2017 * transmit descriptor rings and rx and tx buffers locations.
2018 * It contains a minor bug in printing, but has no effect to the values
2019 * only newlines are not correct.
2020 *
2021 * Parameters : I : struct net_device *dev - SK_G16 device structure
2022 * Return Value : None
2023 * Errors : None
2024 * Globals : None
2025 * Update History :
2026 * YY/MM/DD uid Description
2027-*/
2028
2029void __init SK_print_ram(struct net_device *dev)
2030{
2031
2032 int i;
2033 struct priv *p = netdev_priv(dev);
2034
2035 printk("## %s: RAM Details.\n"
2036 "## RAM at %#08x tmdhead: %#08x rmdhead: %#08x initblock: %#08x\n",
2037 SK_NAME,
2038 (unsigned int) p->ram,
2039 (unsigned int) p->tmdhead,
2040 (unsigned int) p->rmdhead,
2041 (unsigned int) &(p->ram)->ib);
2042
2043 printk("## ");
2044
2045 for(i = 0; i < TMDNUM; i++)
2046 {
2047 if (!(i % 3)) /* Every third line do a newline */
2048 {
2049 printk("\n## ");
2050 }
2051 printk("tmdbufs%d: %#08x ", (i+1), (int) p->tmdbufs[i]);
2052 }
2053 printk("## ");
2054
2055 for(i = 0; i < RMDNUM; i++)
2056 {
2057 if (!(i % 3)) /* Every third line do a newline */
2058 {
2059 printk("\n## ");
2060 }
2061 printk("rmdbufs%d: %#08x ", (i+1), (int) p->rmdbufs[i]);
2062 }
2063 printk("\n");
2064
2065} /* End of SK_print_ram() */
2066
diff --git a/drivers/net/sk_g16.h b/drivers/net/sk_g16.h
deleted file mode 100644
index 0a5dc0908a04..000000000000
--- a/drivers/net/sk_g16.h
+++ /dev/null
@@ -1,165 +0,0 @@
1/*-
2 *
3 * This software may be used and distributed according to the terms
4 * of the GNU General Public License, incorporated herein by reference.
5 *
6 * Module : sk_g16.h
7 * Version : $Revision$
8 *
9 * Author : M.Hipp (mhipp@student.uni-tuebingen.de)
10 * changes by : Patrick J.D. Weichmann
11 *
12 * Date Created : 94/05/25
13 *
14 * Description : In here are all necessary definitions of
15 * the am7990 (LANCE) chip used for writing a
16 * network device driver which uses this chip
17 *
18 * $Log$
19-*/
20
21#ifndef SK_G16_H
22
23#define SK_G16_H
24
25
26/*
27 * Control and Status Register 0 (CSR0) bit definitions
28 *
29 * (R=Readable) (W=Writeable) (S=Set on write) (C-Clear on write)
30 *
31 */
32
33#define CSR0_ERR 0x8000 /* Error summary (R) */
34#define CSR0_BABL 0x4000 /* Babble transmitter timeout error (RC) */
35#define CSR0_CERR 0x2000 /* Collision Error (RC) */
36#define CSR0_MISS 0x1000 /* Missed packet (RC) */
37#define CSR0_MERR 0x0800 /* Memory Error (RC) */
38#define CSR0_RINT 0x0400 /* Receiver Interrupt (RC) */
39#define CSR0_TINT 0x0200 /* Transmit Interrupt (RC) */
40#define CSR0_IDON 0x0100 /* Initialization Done (RC) */
41#define CSR0_INTR 0x0080 /* Interrupt Flag (R) */
42#define CSR0_INEA 0x0040 /* Interrupt Enable (RW) */
43#define CSR0_RXON 0x0020 /* Receiver on (R) */
44#define CSR0_TXON 0x0010 /* Transmitter on (R) */
45#define CSR0_TDMD 0x0008 /* Transmit Demand (RS) */
46#define CSR0_STOP 0x0004 /* Stop (RS) */
47#define CSR0_STRT 0x0002 /* Start (RS) */
48#define CSR0_INIT 0x0001 /* Initialize (RS) */
49
50#define CSR0_CLRALL 0x7f00 /* mask for all clearable bits */
51
52/*
53 * Control and Status Register 3 (CSR3) bit definitions
54 *
55 */
56
57#define CSR3_BSWAP 0x0004 /* Byte Swap (RW) */
58#define CSR3_ACON 0x0002 /* ALE Control (RW) */
59#define CSR3_BCON 0x0001 /* Byte Control (RW) */
60
61/*
62 * Initialization Block Mode operation Bit Definitions.
63 */
64
65#define MODE_PROM 0x8000 /* Promiscuous Mode */
66#define MODE_INTL 0x0040 /* Internal Loopback */
67#define MODE_DRTY 0x0020 /* Disable Retry */
68#define MODE_COLL 0x0010 /* Force Collision */
69#define MODE_DTCR 0x0008 /* Disable Transmit CRC) */
70#define MODE_LOOP 0x0004 /* Loopback */
71#define MODE_DTX 0x0002 /* Disable the Transmitter */
72#define MODE_DRX 0x0001 /* Disable the Receiver */
73
74#define MODE_NORMAL 0x0000 /* Normal operation mode */
75
76/*
77 * Receive message descriptor status bit definitions.
78 */
79
80#define RX_OWN 0x80 /* Owner bit 0 = host, 1 = lance */
81#define RX_ERR 0x40 /* Error Summary */
82#define RX_FRAM 0x20 /* Framing Error */
83#define RX_OFLO 0x10 /* Overflow Error */
84#define RX_CRC 0x08 /* CRC Error */
85#define RX_BUFF 0x04 /* Buffer Error */
86#define RX_STP 0x02 /* Start of Packet */
87#define RX_ENP 0x01 /* End of Packet */
88
89
90/*
91 * Transmit message descriptor status bit definitions.
92 */
93
94#define TX_OWN 0x80 /* Owner bit 0 = host, 1 = lance */
95#define TX_ERR 0x40 /* Error Summary */
96#define TX_MORE 0x10 /* More the 1 retry needed to Xmit */
97#define TX_ONE 0x08 /* One retry needed to Xmit */
98#define TX_DEF 0x04 /* Deferred */
99#define TX_STP 0x02 /* Start of Packet */
100#define TX_ENP 0x01 /* End of Packet */
101
102/*
103 * Transmit status (2) (valid if TX_ERR == 1)
104 */
105
106#define TX_BUFF 0x8000 /* Buffering error (no ENP) */
107#define TX_UFLO 0x4000 /* Underflow (late memory) */
108#define TX_LCOL 0x1000 /* Late collision */
109#define TX_LCAR 0x0400 /* Loss of Carrier */
110#define TX_RTRY 0x0200 /* Failed after 16 retransmissions */
111#define TX_TDR 0x003f /* Time-domain-reflectometer-value */
112
113
114/*
115 * Structures used for Communication with the LANCE
116 */
117
118/* LANCE Initialize Block */
119
120struct init_block
121{
122 unsigned short mode; /* Mode Register */
123 unsigned char paddr[6]; /* Physical Address (MAC) */
124 unsigned char laddr[8]; /* Logical Filter Address (not used) */
125 unsigned int rdrp; /* Receive Descriptor Ring pointer */
126 unsigned int tdrp; /* Transmit Descriptor Ring pointer */
127};
128
129
130/* Receive Message Descriptor Entry */
131
132struct rmd
133{
134 union
135 {
136 unsigned long buffer; /* Address of buffer */
137 struct
138 {
139 unsigned char unused[3];
140 unsigned volatile char status; /* Status Bits */
141 } s;
142 } u;
143 volatile short blen; /* Buffer Length (two's complement) */
144 unsigned short mlen; /* Message Byte Count */
145};
146
147
148/* Transmit Message Descriptor Entry */
149
150struct tmd
151{
152 union
153 {
154 unsigned long buffer; /* Address of buffer */
155 struct
156 {
157 unsigned char unused[3];
158 unsigned volatile char status; /* Status Bits */
159 } s;
160 } u;
161 unsigned short blen; /* Buffer Length (two's complement) */
162 unsigned volatile short status2; /* Error Status Bits */
163};
164
165#endif /* End of SK_G16_H */
diff --git a/drivers/net/skge.c b/drivers/net/skge.c
new file mode 100644
index 000000000000..30e8d589d167
--- /dev/null
+++ b/drivers/net/skge.c
@@ -0,0 +1,3386 @@
1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/config.h>
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/moduleparam.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/delay.h>
38#include <linux/crc32.h>
39#include <linux/dma-mapping.h>
40#include <asm/irq.h>
41
42#include "skge.h"
43
44#define DRV_NAME "skge"
45#define DRV_VERSION "0.6"
46#define PFX DRV_NAME " "
47
48#define DEFAULT_TX_RING_SIZE 128
49#define DEFAULT_RX_RING_SIZE 512
50#define MAX_TX_RING_SIZE 1024
51#define MAX_RX_RING_SIZE 4096
52#define PHY_RETRIES 1000
53#define ETH_JUMBO_MTU 9000
54#define TX_WATCHDOG (5 * HZ)
55#define NAPI_WEIGHT 64
56#define BLINK_HZ (HZ/4)
57#define LINK_POLL_HZ (HZ/10)
58
59MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
60MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
61MODULE_LICENSE("GPL");
62MODULE_VERSION(DRV_VERSION);
63
64static const u32 default_msg
65 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
66 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
67
68static int debug = -1; /* defaults above */
69module_param(debug, int, 0);
70MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
71
72static const struct pci_device_id skge_id_table[] = {
73 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940,
74 PCI_ANY_ID, PCI_ANY_ID },
75 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B,
76 PCI_ANY_ID, PCI_ANY_ID },
77 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE,
78 PCI_ANY_ID, PCI_ANY_ID },
79 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU,
80 PCI_ANY_ID, PCI_ANY_ID },
81 { PCI_VENDOR_ID_SYSKONNECT, 0x9E00, /* SK-9Exx */
82 PCI_ANY_ID, PCI_ANY_ID },
83 { PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T,
84 PCI_ANY_ID, PCI_ANY_ID },
85 { PCI_VENDOR_ID_MARVELL, 0x4320, /* Gigabit Ethernet Controller */
86 PCI_ANY_ID, PCI_ANY_ID },
87 { PCI_VENDOR_ID_MARVELL, 0x5005, /* Marvell (11ab), Belkin */
88 PCI_ANY_ID, PCI_ANY_ID },
89 { PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD,
90 PCI_ANY_ID, PCI_ANY_ID },
91 { PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1032,
92 PCI_ANY_ID, PCI_ANY_ID },
93 { PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064,
94 PCI_ANY_ID, PCI_ANY_ID },
95 { 0 }
96};
97MODULE_DEVICE_TABLE(pci, skge_id_table);
98
99static int skge_up(struct net_device *dev);
100static int skge_down(struct net_device *dev);
101static void skge_tx_clean(struct skge_port *skge);
102static void skge_xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
103static void skge_gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
104static void genesis_get_stats(struct skge_port *skge, u64 *data);
105static void yukon_get_stats(struct skge_port *skge, u64 *data);
106static void yukon_init(struct skge_hw *hw, int port);
107static void yukon_reset(struct skge_hw *hw, int port);
108static void genesis_mac_init(struct skge_hw *hw, int port);
109static void genesis_reset(struct skge_hw *hw, int port);
110
111static const int txqaddr[] = { Q_XA1, Q_XA2 };
112static const int rxqaddr[] = { Q_R1, Q_R2 };
113static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
114static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
115
116/* Don't need to look at whole 16K.
117 * last interesting register is descriptor poll timer.
118 */
119#define SKGE_REGS_LEN (29*128)
120
121static int skge_get_regs_len(struct net_device *dev)
122{
123 return SKGE_REGS_LEN;
124}
125
126/*
127 * Returns copy of control register region
128 * I/O region is divided into banks and certain regions are unreadable
129 */
130static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
131 void *p)
132{
133 const struct skge_port *skge = netdev_priv(dev);
134 unsigned long offs;
135 const void __iomem *io = skge->hw->regs;
136 static const unsigned long bankmap
137 = (1<<0) | (1<<2) | (1<<8) | (1<<9)
138 | (1<<12) | (1<<13) | (1<<14) | (1<<15) | (1<<16)
139 | (1<<17) | (1<<20) | (1<<21) | (1<<22) | (1<<23)
140 | (1<<24) | (1<<25) | (1<<26) | (1<<27) | (1<<28);
141
142 regs->version = 1;
143 for (offs = 0; offs < regs->len; offs += 128) {
144 u32 len = min_t(u32, 128, regs->len - offs);
145
146 if (bankmap & (1<<(offs/128)))
147 memcpy_fromio(p + offs, io + offs, len);
148 else
149 memset(p + offs, 0, len);
150 }
151}
152
153/* Wake on Lan only supported on Yukon chps with rev 1 or above */
154static int wol_supported(const struct skge_hw *hw)
155{
156 return !((hw->chip_id == CHIP_ID_GENESIS ||
157 (hw->chip_id == CHIP_ID_YUKON && chip_rev(hw) == 0)));
158}
159
160static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
161{
162 struct skge_port *skge = netdev_priv(dev);
163
164 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
165 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
166}
167
168static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
169{
170 struct skge_port *skge = netdev_priv(dev);
171 struct skge_hw *hw = skge->hw;
172
173 if(wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
174 return -EOPNOTSUPP;
175
176 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
177 return -EOPNOTSUPP;
178
179 skge->wol = wol->wolopts == WAKE_MAGIC;
180
181 if (skge->wol) {
182 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
183
184 skge_write16(hw, WOL_CTRL_STAT,
185 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
186 WOL_CTL_ENA_MAGIC_PKT_UNIT);
187 } else
188 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
189
190 return 0;
191}
192
193
194static int skge_get_settings(struct net_device *dev,
195 struct ethtool_cmd *ecmd)
196{
197 struct skge_port *skge = netdev_priv(dev);
198 struct skge_hw *hw = skge->hw;
199
200 ecmd->transceiver = XCVR_INTERNAL;
201
202 if (iscopper(hw)) {
203 if (hw->chip_id == CHIP_ID_GENESIS)
204 ecmd->supported = SUPPORTED_1000baseT_Full
205 | SUPPORTED_1000baseT_Half
206 | SUPPORTED_Autoneg | SUPPORTED_TP;
207 else {
208 ecmd->supported = SUPPORTED_10baseT_Half
209 | SUPPORTED_10baseT_Full
210 | SUPPORTED_100baseT_Half
211 | SUPPORTED_100baseT_Full
212 | SUPPORTED_1000baseT_Half
213 | SUPPORTED_1000baseT_Full
214 | SUPPORTED_Autoneg| SUPPORTED_TP;
215
216 if (hw->chip_id == CHIP_ID_YUKON)
217 ecmd->supported &= ~SUPPORTED_1000baseT_Half;
218
219 else if (hw->chip_id == CHIP_ID_YUKON_FE)
220 ecmd->supported &= ~(SUPPORTED_1000baseT_Half
221 | SUPPORTED_1000baseT_Full);
222 }
223
224 ecmd->port = PORT_TP;
225 ecmd->phy_address = hw->phy_addr;
226 } else {
227 ecmd->supported = SUPPORTED_1000baseT_Full
228 | SUPPORTED_FIBRE
229 | SUPPORTED_Autoneg;
230
231 ecmd->port = PORT_FIBRE;
232 }
233
234 ecmd->advertising = skge->advertising;
235 ecmd->autoneg = skge->autoneg;
236 ecmd->speed = skge->speed;
237 ecmd->duplex = skge->duplex;
238 return 0;
239}
240
241static u32 skge_modes(const struct skge_hw *hw)
242{
243 u32 modes = ADVERTISED_Autoneg
244 | ADVERTISED_1000baseT_Full | ADVERTISED_1000baseT_Half
245 | ADVERTISED_100baseT_Full | ADVERTISED_100baseT_Half
246 | ADVERTISED_10baseT_Full | ADVERTISED_10baseT_Half;
247
248 if (iscopper(hw)) {
249 modes |= ADVERTISED_TP;
250 switch(hw->chip_id) {
251 case CHIP_ID_GENESIS:
252 modes &= ~(ADVERTISED_100baseT_Full
253 | ADVERTISED_100baseT_Half
254 | ADVERTISED_10baseT_Full
255 | ADVERTISED_10baseT_Half);
256 break;
257
258 case CHIP_ID_YUKON:
259 modes &= ~ADVERTISED_1000baseT_Half;
260 break;
261
262 case CHIP_ID_YUKON_FE:
263 modes &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
264 break;
265 }
266 } else {
267 modes |= ADVERTISED_FIBRE;
268 modes &= ~ADVERTISED_1000baseT_Half;
269 }
270 return modes;
271}
272
273static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
274{
275 struct skge_port *skge = netdev_priv(dev);
276 const struct skge_hw *hw = skge->hw;
277
278 if (ecmd->autoneg == AUTONEG_ENABLE) {
279 if (ecmd->advertising & skge_modes(hw))
280 return -EINVAL;
281 } else {
282 switch(ecmd->speed) {
283 case SPEED_1000:
284 if (hw->chip_id == CHIP_ID_YUKON_FE)
285 return -EINVAL;
286 break;
287 case SPEED_100:
288 case SPEED_10:
289 if (iscopper(hw) || hw->chip_id == CHIP_ID_GENESIS)
290 return -EINVAL;
291 break;
292 default:
293 return -EINVAL;
294 }
295 }
296
297 skge->autoneg = ecmd->autoneg;
298 skge->speed = ecmd->speed;
299 skge->duplex = ecmd->duplex;
300 skge->advertising = ecmd->advertising;
301
302 if (netif_running(dev)) {
303 skge_down(dev);
304 skge_up(dev);
305 }
306 return (0);
307}
308
309static void skge_get_drvinfo(struct net_device *dev,
310 struct ethtool_drvinfo *info)
311{
312 struct skge_port *skge = netdev_priv(dev);
313
314 strcpy(info->driver, DRV_NAME);
315 strcpy(info->version, DRV_VERSION);
316 strcpy(info->fw_version, "N/A");
317 strcpy(info->bus_info, pci_name(skge->hw->pdev));
318}
319
320static const struct skge_stat {
321 char name[ETH_GSTRING_LEN];
322 u16 xmac_offset;
323 u16 gma_offset;
324} skge_stats[] = {
325 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
326 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
327
328 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
329 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
330 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
331 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
332 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
333 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
334 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
335 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
336
337 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
338 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
339 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
340 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
341 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
342 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
343
344 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
345 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
346 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
347 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
348 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
349};
350
351static int skge_get_stats_count(struct net_device *dev)
352{
353 return ARRAY_SIZE(skge_stats);
354}
355
356static void skge_get_ethtool_stats(struct net_device *dev,
357 struct ethtool_stats *stats, u64 *data)
358{
359 struct skge_port *skge = netdev_priv(dev);
360
361 if (skge->hw->chip_id == CHIP_ID_GENESIS)
362 genesis_get_stats(skge, data);
363 else
364 yukon_get_stats(skge, data);
365}
366
367/* Use hardware MIB variables for critical path statistics and
368 * transmit feedback not reported at interrupt.
369 * Other errors are accounted for in interrupt handler.
370 */
371static struct net_device_stats *skge_get_stats(struct net_device *dev)
372{
373 struct skge_port *skge = netdev_priv(dev);
374 u64 data[ARRAY_SIZE(skge_stats)];
375
376 if (skge->hw->chip_id == CHIP_ID_GENESIS)
377 genesis_get_stats(skge, data);
378 else
379 yukon_get_stats(skge, data);
380
381 skge->net_stats.tx_bytes = data[0];
382 skge->net_stats.rx_bytes = data[1];
383 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
384 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
385 skge->net_stats.multicast = data[5] + data[7];
386 skge->net_stats.collisions = data[10];
387 skge->net_stats.tx_aborted_errors = data[12];
388
389 return &skge->net_stats;
390}
391
392static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
393{
394 int i;
395
396 switch(stringset) {
397 case ETH_SS_STATS:
398 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
399 memcpy(data + i * ETH_GSTRING_LEN,
400 skge_stats[i].name, ETH_GSTRING_LEN);
401 break;
402 }
403}
404
405static void skge_get_ring_param(struct net_device *dev,
406 struct ethtool_ringparam *p)
407{
408 struct skge_port *skge = netdev_priv(dev);
409
410 p->rx_max_pending = MAX_RX_RING_SIZE;
411 p->tx_max_pending = MAX_TX_RING_SIZE;
412 p->rx_mini_max_pending = 0;
413 p->rx_jumbo_max_pending = 0;
414
415 p->rx_pending = skge->rx_ring.count;
416 p->tx_pending = skge->tx_ring.count;
417 p->rx_mini_pending = 0;
418 p->rx_jumbo_pending = 0;
419}
420
421static int skge_set_ring_param(struct net_device *dev,
422 struct ethtool_ringparam *p)
423{
424 struct skge_port *skge = netdev_priv(dev);
425
426 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
427 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
428 return -EINVAL;
429
430 skge->rx_ring.count = p->rx_pending;
431 skge->tx_ring.count = p->tx_pending;
432
433 if (netif_running(dev)) {
434 skge_down(dev);
435 skge_up(dev);
436 }
437
438 return 0;
439}
440
441static u32 skge_get_msglevel(struct net_device *netdev)
442{
443 struct skge_port *skge = netdev_priv(netdev);
444 return skge->msg_enable;
445}
446
447static void skge_set_msglevel(struct net_device *netdev, u32 value)
448{
449 struct skge_port *skge = netdev_priv(netdev);
450 skge->msg_enable = value;
451}
452
453static int skge_nway_reset(struct net_device *dev)
454{
455 struct skge_port *skge = netdev_priv(dev);
456 struct skge_hw *hw = skge->hw;
457 int port = skge->port;
458
459 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
460 return -EINVAL;
461
462 spin_lock_bh(&hw->phy_lock);
463 if (hw->chip_id == CHIP_ID_GENESIS) {
464 genesis_reset(hw, port);
465 genesis_mac_init(hw, port);
466 } else {
467 yukon_reset(hw, port);
468 yukon_init(hw, port);
469 }
470 spin_unlock_bh(&hw->phy_lock);
471 return 0;
472}
473
474static int skge_set_sg(struct net_device *dev, u32 data)
475{
476 struct skge_port *skge = netdev_priv(dev);
477 struct skge_hw *hw = skge->hw;
478
479 if (hw->chip_id == CHIP_ID_GENESIS && data)
480 return -EOPNOTSUPP;
481 return ethtool_op_set_sg(dev, data);
482}
483
484static int skge_set_tx_csum(struct net_device *dev, u32 data)
485{
486 struct skge_port *skge = netdev_priv(dev);
487 struct skge_hw *hw = skge->hw;
488
489 if (hw->chip_id == CHIP_ID_GENESIS && data)
490 return -EOPNOTSUPP;
491
492 return ethtool_op_set_tx_csum(dev, data);
493}
494
495static u32 skge_get_rx_csum(struct net_device *dev)
496{
497 struct skge_port *skge = netdev_priv(dev);
498
499 return skge->rx_csum;
500}
501
502/* Only Yukon supports checksum offload. */
503static int skge_set_rx_csum(struct net_device *dev, u32 data)
504{
505 struct skge_port *skge = netdev_priv(dev);
506
507 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
508 return -EOPNOTSUPP;
509
510 skge->rx_csum = data;
511 return 0;
512}
513
514/* Only Yukon II supports TSO (not implemented yet) */
515static int skge_set_tso(struct net_device *dev, u32 data)
516{
517 if (data)
518 return -EOPNOTSUPP;
519 return 0;
520}
521
522static void skge_get_pauseparam(struct net_device *dev,
523 struct ethtool_pauseparam *ecmd)
524{
525 struct skge_port *skge = netdev_priv(dev);
526
527 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
528 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
529 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
530 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
531
532 ecmd->autoneg = skge->autoneg;
533}
534
535static int skge_set_pauseparam(struct net_device *dev,
536 struct ethtool_pauseparam *ecmd)
537{
538 struct skge_port *skge = netdev_priv(dev);
539
540 skge->autoneg = ecmd->autoneg;
541 if (ecmd->rx_pause && ecmd->tx_pause)
542 skge->flow_control = FLOW_MODE_SYMMETRIC;
543 else if(ecmd->rx_pause && !ecmd->tx_pause)
544 skge->flow_control = FLOW_MODE_REM_SEND;
545 else if(!ecmd->rx_pause && ecmd->tx_pause)
546 skge->flow_control = FLOW_MODE_LOC_SEND;
547 else
548 skge->flow_control = FLOW_MODE_NONE;
549
550 if (netif_running(dev)) {
551 skge_down(dev);
552 skge_up(dev);
553 }
554 return 0;
555}
556
557/* Chip internal frequency for clock calculations */
558static inline u32 hwkhz(const struct skge_hw *hw)
559{
560 if (hw->chip_id == CHIP_ID_GENESIS)
561 return 53215; /* or: 53.125 MHz */
562 else if (hw->chip_id == CHIP_ID_YUKON_EC)
563 return 125000; /* or: 125.000 MHz */
564 else
565 return 78215; /* or: 78.125 MHz */
566}
567
568/* Chip hz to microseconds */
569static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
570{
571 return (ticks * 1000) / hwkhz(hw);
572}
573
574/* Microseconds to chip hz */
575static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
576{
577 return hwkhz(hw) * usec / 1000;
578}
579
580static int skge_get_coalesce(struct net_device *dev,
581 struct ethtool_coalesce *ecmd)
582{
583 struct skge_port *skge = netdev_priv(dev);
584 struct skge_hw *hw = skge->hw;
585 int port = skge->port;
586
587 ecmd->rx_coalesce_usecs = 0;
588 ecmd->tx_coalesce_usecs = 0;
589
590 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
591 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
592 u32 msk = skge_read32(hw, B2_IRQM_MSK);
593
594 if (msk & rxirqmask[port])
595 ecmd->rx_coalesce_usecs = delay;
596 if (msk & txirqmask[port])
597 ecmd->tx_coalesce_usecs = delay;
598 }
599
600 return 0;
601}
602
603/* Note: interrupt timer is per board, but can turn on/off per port */
604static int skge_set_coalesce(struct net_device *dev,
605 struct ethtool_coalesce *ecmd)
606{
607 struct skge_port *skge = netdev_priv(dev);
608 struct skge_hw *hw = skge->hw;
609 int port = skge->port;
610 u32 msk = skge_read32(hw, B2_IRQM_MSK);
611 u32 delay = 25;
612
613 if (ecmd->rx_coalesce_usecs == 0)
614 msk &= ~rxirqmask[port];
615 else if (ecmd->rx_coalesce_usecs < 25 ||
616 ecmd->rx_coalesce_usecs > 33333)
617 return -EINVAL;
618 else {
619 msk |= rxirqmask[port];
620 delay = ecmd->rx_coalesce_usecs;
621 }
622
623 if (ecmd->tx_coalesce_usecs == 0)
624 msk &= ~txirqmask[port];
625 else if (ecmd->tx_coalesce_usecs < 25 ||
626 ecmd->tx_coalesce_usecs > 33333)
627 return -EINVAL;
628 else {
629 msk |= txirqmask[port];
630 delay = min(delay, ecmd->rx_coalesce_usecs);
631 }
632
633 skge_write32(hw, B2_IRQM_MSK, msk);
634 if (msk == 0)
635 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
636 else {
637 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
638 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
639 }
640 return 0;
641}
642
643static void skge_led_on(struct skge_hw *hw, int port)
644{
645 if (hw->chip_id == CHIP_ID_GENESIS) {
646 skge_write8(hw, SKGEMAC_REG(port, LNK_LED_REG), LINKLED_ON);
647 skge_write8(hw, B0_LED, LED_STAT_ON);
648
649 skge_write8(hw, SKGEMAC_REG(port, RX_LED_TST), LED_T_ON);
650 skge_write32(hw, SKGEMAC_REG(port, RX_LED_VAL), 100);
651 skge_write8(hw, SKGEMAC_REG(port, RX_LED_CTRL), LED_START);
652
653 switch (hw->phy_type) {
654 case SK_PHY_BCOM:
655 skge_xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL,
656 PHY_B_PEC_LED_ON);
657 break;
658 case SK_PHY_LONE:
659 skge_xm_phy_write(hw, port, PHY_LONE_LED_CFG,
660 0x0800);
661 break;
662 default:
663 skge_write8(hw, SKGEMAC_REG(port, TX_LED_TST), LED_T_ON);
664 skge_write32(hw, SKGEMAC_REG(port, TX_LED_VAL), 100);
665 skge_write8(hw, SKGEMAC_REG(port, TX_LED_CTRL), LED_START);
666 }
667 } else {
668 skge_gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
669 skge_gm_phy_write(hw, port, PHY_MARV_LED_OVER,
670 PHY_M_LED_MO_DUP(MO_LED_ON) |
671 PHY_M_LED_MO_10(MO_LED_ON) |
672 PHY_M_LED_MO_100(MO_LED_ON) |
673 PHY_M_LED_MO_1000(MO_LED_ON) |
674 PHY_M_LED_MO_RX(MO_LED_ON));
675 }
676}
677
678static void skge_led_off(struct skge_hw *hw, int port)
679{
680 if (hw->chip_id == CHIP_ID_GENESIS) {
681 skge_write8(hw, SKGEMAC_REG(port, LNK_LED_REG), LINKLED_OFF);
682 skge_write8(hw, B0_LED, LED_STAT_OFF);
683
684 skge_write32(hw, SKGEMAC_REG(port, RX_LED_VAL), 0);
685 skge_write8(hw, SKGEMAC_REG(port, RX_LED_CTRL), LED_T_OFF);
686
687 switch (hw->phy_type) {
688 case SK_PHY_BCOM:
689 skge_xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL,
690 PHY_B_PEC_LED_OFF);
691 break;
692 case SK_PHY_LONE:
693 skge_xm_phy_write(hw, port, PHY_LONE_LED_CFG,
694 PHY_L_LC_LEDT);
695 break;
696 default:
697 skge_write32(hw, SKGEMAC_REG(port, TX_LED_VAL), 0);
698 skge_write8(hw, SKGEMAC_REG(port, TX_LED_CTRL), LED_T_OFF);
699 }
700 } else {
701 skge_gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
702 skge_gm_phy_write(hw, port, PHY_MARV_LED_OVER,
703 PHY_M_LED_MO_DUP(MO_LED_OFF) |
704 PHY_M_LED_MO_10(MO_LED_OFF) |
705 PHY_M_LED_MO_100(MO_LED_OFF) |
706 PHY_M_LED_MO_1000(MO_LED_OFF) |
707 PHY_M_LED_MO_RX(MO_LED_OFF));
708 }
709}
710
711static void skge_blink_timer(unsigned long data)
712{
713 struct skge_port *skge = (struct skge_port *) data;
714 struct skge_hw *hw = skge->hw;
715 unsigned long flags;
716
717 spin_lock_irqsave(&hw->phy_lock, flags);
718 if (skge->blink_on)
719 skge_led_on(hw, skge->port);
720 else
721 skge_led_off(hw, skge->port);
722 spin_unlock_irqrestore(&hw->phy_lock, flags);
723
724 skge->blink_on = !skge->blink_on;
725 mod_timer(&skge->led_blink, jiffies + BLINK_HZ);
726}
727
728/* blink LED's for finding board */
729static int skge_phys_id(struct net_device *dev, u32 data)
730{
731 struct skge_port *skge = netdev_priv(dev);
732
733 if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
734 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
735
736 /* start blinking */
737 skge->blink_on = 1;
738 mod_timer(&skge->led_blink, jiffies+1);
739
740 msleep_interruptible(data * 1000);
741 del_timer_sync(&skge->led_blink);
742
743 skge_led_off(skge->hw, skge->port);
744
745 return 0;
746}
747
748static struct ethtool_ops skge_ethtool_ops = {
749 .get_settings = skge_get_settings,
750 .set_settings = skge_set_settings,
751 .get_drvinfo = skge_get_drvinfo,
752 .get_regs_len = skge_get_regs_len,
753 .get_regs = skge_get_regs,
754 .get_wol = skge_get_wol,
755 .set_wol = skge_set_wol,
756 .get_msglevel = skge_get_msglevel,
757 .set_msglevel = skge_set_msglevel,
758 .nway_reset = skge_nway_reset,
759 .get_link = ethtool_op_get_link,
760 .get_ringparam = skge_get_ring_param,
761 .set_ringparam = skge_set_ring_param,
762 .get_pauseparam = skge_get_pauseparam,
763 .set_pauseparam = skge_set_pauseparam,
764 .get_coalesce = skge_get_coalesce,
765 .set_coalesce = skge_set_coalesce,
766 .get_tso = ethtool_op_get_tso,
767 .set_tso = skge_set_tso,
768 .get_sg = ethtool_op_get_sg,
769 .set_sg = skge_set_sg,
770 .get_tx_csum = ethtool_op_get_tx_csum,
771 .set_tx_csum = skge_set_tx_csum,
772 .get_rx_csum = skge_get_rx_csum,
773 .set_rx_csum = skge_set_rx_csum,
774 .get_strings = skge_get_strings,
775 .phys_id = skge_phys_id,
776 .get_stats_count = skge_get_stats_count,
777 .get_ethtool_stats = skge_get_ethtool_stats,
778};
779
780/*
781 * Allocate ring elements and chain them together
782 * One-to-one association of board descriptors with ring elements
783 */
784static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
785{
786 struct skge_tx_desc *d;
787 struct skge_element *e;
788 int i;
789
790 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
791 if (!ring->start)
792 return -ENOMEM;
793
794 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
795 e->desc = d;
796 if (i == ring->count - 1) {
797 e->next = ring->start;
798 d->next_offset = base;
799 } else {
800 e->next = e + 1;
801 d->next_offset = base + (i+1) * sizeof(*d);
802 }
803 }
804 ring->to_use = ring->to_clean = ring->start;
805
806 return 0;
807}
808
809/* Setup buffer for receiving */
810static inline int skge_rx_alloc(struct skge_port *skge,
811 struct skge_element *e)
812{
813 unsigned long bufsize = skge->netdev->mtu + ETH_HLEN; /* VLAN? */
814 struct skge_rx_desc *rd = e->desc;
815 struct sk_buff *skb;
816 u64 map;
817
818 skb = dev_alloc_skb(bufsize + NET_IP_ALIGN);
819 if (unlikely(!skb)) {
820 printk(KERN_DEBUG PFX "%s: out of memory for receive\n",
821 skge->netdev->name);
822 return -ENOMEM;
823 }
824
825 skb->dev = skge->netdev;
826 skb_reserve(skb, NET_IP_ALIGN);
827
828 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
829 PCI_DMA_FROMDEVICE);
830
831 rd->dma_lo = map;
832 rd->dma_hi = map >> 32;
833 e->skb = skb;
834 rd->csum1_start = ETH_HLEN;
835 rd->csum2_start = ETH_HLEN;
836 rd->csum1 = 0;
837 rd->csum2 = 0;
838
839 wmb();
840
841 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
842 pci_unmap_addr_set(e, mapaddr, map);
843 pci_unmap_len_set(e, maplen, bufsize);
844 return 0;
845}
846
847/* Free all unused buffers in receive ring, assumes receiver stopped */
848static void skge_rx_clean(struct skge_port *skge)
849{
850 struct skge_hw *hw = skge->hw;
851 struct skge_ring *ring = &skge->rx_ring;
852 struct skge_element *e;
853
854 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
855 struct skge_rx_desc *rd = e->desc;
856 rd->control = 0;
857
858 pci_unmap_single(hw->pdev,
859 pci_unmap_addr(e, mapaddr),
860 pci_unmap_len(e, maplen),
861 PCI_DMA_FROMDEVICE);
862 dev_kfree_skb(e->skb);
863 e->skb = NULL;
864 }
865 ring->to_clean = e;
866}
867
868/* Allocate buffers for receive ring
869 * For receive: to_use is refill location
870 * to_clean is next received frame.
871 *
872 * if (to_use == to_clean)
873 * then ring all frames in ring need buffers
874 * if (to_use->next == to_clean)
875 * then ring all frames in ring have buffers
876 */
877static int skge_rx_fill(struct skge_port *skge)
878{
879 struct skge_ring *ring = &skge->rx_ring;
880 struct skge_element *e;
881 int ret = 0;
882
883 for (e = ring->to_use; e->next != ring->to_clean; e = e->next) {
884 if (skge_rx_alloc(skge, e)) {
885 ret = 1;
886 break;
887 }
888
889 }
890 ring->to_use = e;
891
892 return ret;
893}
894
895static void skge_link_up(struct skge_port *skge)
896{
897 netif_carrier_on(skge->netdev);
898 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
899 netif_wake_queue(skge->netdev);
900
901 if (netif_msg_link(skge))
902 printk(KERN_INFO PFX
903 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
904 skge->netdev->name, skge->speed,
905 skge->duplex == DUPLEX_FULL ? "full" : "half",
906 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
907 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
908 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
909 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
910 "unknown");
911}
912
913static void skge_link_down(struct skge_port *skge)
914{
915 netif_carrier_off(skge->netdev);
916 netif_stop_queue(skge->netdev);
917
918 if (netif_msg_link(skge))
919 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
920}
921
922static u16 skge_xm_phy_read(struct skge_hw *hw, int port, u16 reg)
923{
924 int i;
925 u16 v;
926
927 skge_xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
928 v = skge_xm_read16(hw, port, XM_PHY_DATA);
929 if (hw->phy_type != SK_PHY_XMAC) {
930 for (i = 0; i < PHY_RETRIES; i++) {
931 udelay(1);
932 if (skge_xm_read16(hw, port, XM_MMU_CMD)
933 & XM_MMU_PHY_RDY)
934 goto ready;
935 }
936
937 printk(KERN_WARNING PFX "%s: phy read timed out\n",
938 hw->dev[port]->name);
939 return 0;
940 ready:
941 v = skge_xm_read16(hw, port, XM_PHY_DATA);
942 }
943
944 return v;
945}
946
947static void skge_xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
948{
949 int i;
950
951 skge_xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
952 for (i = 0; i < PHY_RETRIES; i++) {
953 if (!(skge_xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
954 goto ready;
955 cpu_relax();
956 }
957 printk(KERN_WARNING PFX "%s: phy write failed to come ready\n",
958 hw->dev[port]->name);
959
960
961 ready:
962 skge_xm_write16(hw, port, XM_PHY_DATA, val);
963 for (i = 0; i < PHY_RETRIES; i++) {
964 udelay(1);
965 if (!(skge_xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
966 return;
967 }
968 printk(KERN_WARNING PFX "%s: phy write timed out\n",
969 hw->dev[port]->name);
970}
971
972static void genesis_init(struct skge_hw *hw)
973{
974 /* set blink source counter */
975 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
976 skge_write8(hw, B2_BSC_CTRL, BSC_START);
977
978 /* configure mac arbiter */
979 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
980
981 /* configure mac arbiter timeout values */
982 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
983 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
984 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
985 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
986
987 skge_write8(hw, B3_MA_RCINI_RX1, 0);
988 skge_write8(hw, B3_MA_RCINI_RX2, 0);
989 skge_write8(hw, B3_MA_RCINI_TX1, 0);
990 skge_write8(hw, B3_MA_RCINI_TX2, 0);
991
992 /* configure packet arbiter timeout */
993 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
994 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
995 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
996 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
997 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
998}
999
1000static void genesis_reset(struct skge_hw *hw, int port)
1001{
1002 int i;
1003 u64 zero = 0;
1004
1005 /* reset the statistics module */
1006 skge_xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1007 skge_xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
1008 skge_xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1009 skge_xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1010 skge_xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1011
1012 /* disable all PHY IRQs */
1013 if (hw->phy_type == SK_PHY_BCOM)
1014 skge_xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1015
1016 skge_xm_outhash(hw, port, XM_HSM, (u8 *) &zero);
1017 for (i = 0; i < 15; i++)
1018 skge_xm_outaddr(hw, port, XM_EXM(i), (u8 *) &zero);
1019 skge_xm_outhash(hw, port, XM_SRC_CHK, (u8 *) &zero);
1020}
1021
1022
1023static void genesis_mac_init(struct skge_hw *hw, int port)
1024{
1025 struct skge_port *skge = netdev_priv(hw->dev[port]);
1026 int i;
1027 u32 r;
1028 u16 id1;
1029 u16 ctrl1, ctrl2, ctrl3, ctrl4, ctrl5;
1030
1031 /* magic workaround patterns for Broadcom */
1032 static const struct {
1033 u16 reg;
1034 u16 val;
1035 } A1hack[] = {
1036 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1037 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1038 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1039 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1040 }, C0hack[] = {
1041 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1042 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1043 };
1044
1045
1046 /* initialize Rx, Tx and Link LED */
1047 skge_write8(hw, SKGEMAC_REG(port, LNK_LED_REG), LINKLED_ON);
1048 skge_write8(hw, SKGEMAC_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
1049
1050 skge_write8(hw, SKGEMAC_REG(port, RX_LED_CTRL), LED_START);
1051 skge_write8(hw, SKGEMAC_REG(port, TX_LED_CTRL), LED_START);
1052
1053 /* Unreset the XMAC. */
1054 skge_write16(hw, SKGEMAC_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1055
1056 /*
1057 * Perform additional initialization for external PHYs,
1058 * namely for the 1000baseTX cards that use the XMAC's
1059 * GMII mode.
1060 */
1061 spin_lock_bh(&hw->phy_lock);
1062 if (hw->phy_type != SK_PHY_XMAC) {
1063 /* Take PHY out of reset. */
1064 r = skge_read32(hw, B2_GP_IO);
1065 if (port == 0)
1066 r |= GP_DIR_0|GP_IO_0;
1067 else
1068 r |= GP_DIR_2|GP_IO_2;
1069
1070 skge_write32(hw, B2_GP_IO, r);
1071 skge_read32(hw, B2_GP_IO);
1072
1073 /* Enable GMII mode on the XMAC. */
1074 skge_xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1075
1076 id1 = skge_xm_phy_read(hw, port, PHY_XMAC_ID1);
1077
1078 /* Optimize MDIO transfer by suppressing preamble. */
1079 skge_xm_write16(hw, port, XM_MMU_CMD,
1080 skge_xm_read16(hw, port, XM_MMU_CMD)
1081 | XM_MMU_NO_PRE);
1082
1083 if (id1 == PHY_BCOM_ID1_C0) {
1084 /*
1085 * Workaround BCOM Errata for the C0 type.
1086 * Write magic patterns to reserved registers.
1087 */
1088 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1089 skge_xm_phy_write(hw, port,
1090 C0hack[i].reg, C0hack[i].val);
1091
1092 } else if (id1 == PHY_BCOM_ID1_A1) {
1093 /*
1094 * Workaround BCOM Errata for the A1 type.
1095 * Write magic patterns to reserved registers.
1096 */
1097 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1098 skge_xm_phy_write(hw, port,
1099 A1hack[i].reg, A1hack[i].val);
1100 }
1101
1102 /*
1103 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1104 * Disable Power Management after reset.
1105 */
1106 r = skge_xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1107 skge_xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r | PHY_B_AC_DIS_PM);
1108 }
1109
1110 /* Dummy read */
1111 skge_xm_read16(hw, port, XM_ISRC);
1112
1113 r = skge_xm_read32(hw, port, XM_MODE);
1114 skge_xm_write32(hw, port, XM_MODE, r|XM_MD_CSA);
1115
1116 /* We don't need the FCS appended to the packet. */
1117 r = skge_xm_read16(hw, port, XM_RX_CMD);
1118 skge_xm_write16(hw, port, XM_RX_CMD, r | XM_RX_STRIP_FCS);
1119
1120 /* We want short frames padded to 60 bytes. */
1121 r = skge_xm_read16(hw, port, XM_TX_CMD);
1122 skge_xm_write16(hw, port, XM_TX_CMD, r | XM_TX_AUTO_PAD);
1123
1124 /*
1125 * Enable the reception of all error frames. This is is
1126 * a necessary evil due to the design of the XMAC. The
1127 * XMAC's receive FIFO is only 8K in size, however jumbo
1128 * frames can be up to 9000 bytes in length. When bad
1129 * frame filtering is enabled, the XMAC's RX FIFO operates
1130 * in 'store and forward' mode. For this to work, the
1131 * entire frame has to fit into the FIFO, but that means
1132 * that jumbo frames larger than 8192 bytes will be
1133 * truncated. Disabling all bad frame filtering causes
1134 * the RX FIFO to operate in streaming mode, in which
1135 * case the XMAC will start transfering frames out of the
1136 * RX FIFO as soon as the FIFO threshold is reached.
1137 */
1138 r = skge_xm_read32(hw, port, XM_MODE);
1139 skge_xm_write32(hw, port, XM_MODE,
1140 XM_MD_RX_CRCE|XM_MD_RX_LONG|XM_MD_RX_RUNT|
1141 XM_MD_RX_ERR|XM_MD_RX_IRLE);
1142
1143 skge_xm_outaddr(hw, port, XM_SA, hw->dev[port]->dev_addr);
1144 skge_xm_outaddr(hw, port, XM_EXM(0), hw->dev[port]->dev_addr);
1145
1146 /*
1147 * Bump up the transmit threshold. This helps hold off transmit
1148 * underruns when we're blasting traffic from both ports at once.
1149 */
1150 skge_xm_write16(hw, port, XM_TX_THR, 512);
1151
1152 /* Configure MAC arbiter */
1153 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1154
1155 /* configure timeout values */
1156 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1157 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1158 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1159 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1160
1161 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1162 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1163 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1164 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1165
1166 /* Configure Rx MAC FIFO */
1167 skge_write8(hw, SKGEMAC_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1168 skge_write16(hw, SKGEMAC_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1169 skge_write8(hw, SKGEMAC_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1170
1171 /* Configure Tx MAC FIFO */
1172 skge_write8(hw, SKGEMAC_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1173 skge_write16(hw, SKGEMAC_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1174 skge_write8(hw, SKGEMAC_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1175
1176 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1177 /* Enable frame flushing if jumbo frames used */
1178 skge_write16(hw, SKGEMAC_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1179 } else {
1180 /* enable timeout timers if normal frames */
1181 skge_write16(hw, B3_PA_CTRL,
1182 port == 0 ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1183 }
1184
1185
1186 r = skge_xm_read16(hw, port, XM_RX_CMD);
1187 if (hw->dev[port]->mtu > ETH_DATA_LEN)
1188 skge_xm_write16(hw, port, XM_RX_CMD, r | XM_RX_BIG_PK_OK);
1189 else
1190 skge_xm_write16(hw, port, XM_RX_CMD, r & ~(XM_RX_BIG_PK_OK));
1191
1192 switch (hw->phy_type) {
1193 case SK_PHY_XMAC:
1194 if (skge->autoneg == AUTONEG_ENABLE) {
1195 ctrl1 = PHY_X_AN_FD | PHY_X_AN_HD;
1196
1197 switch (skge->flow_control) {
1198 case FLOW_MODE_NONE:
1199 ctrl1 |= PHY_X_P_NO_PAUSE;
1200 break;
1201 case FLOW_MODE_LOC_SEND:
1202 ctrl1 |= PHY_X_P_ASYM_MD;
1203 break;
1204 case FLOW_MODE_SYMMETRIC:
1205 ctrl1 |= PHY_X_P_SYM_MD;
1206 break;
1207 case FLOW_MODE_REM_SEND:
1208 ctrl1 |= PHY_X_P_BOTH_MD;
1209 break;
1210 }
1211
1212 skge_xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl1);
1213 ctrl2 = PHY_CT_ANE | PHY_CT_RE_CFG;
1214 } else {
1215 ctrl2 = 0;
1216 if (skge->duplex == DUPLEX_FULL)
1217 ctrl2 |= PHY_CT_DUP_MD;
1218 }
1219
1220 skge_xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl2);
1221 break;
1222
1223 case SK_PHY_BCOM:
1224 ctrl1 = PHY_CT_SP1000;
1225 ctrl2 = 0;
1226 ctrl3 = PHY_SEL_TYPE;
1227 ctrl4 = PHY_B_PEC_EN_LTR;
1228 ctrl5 = PHY_B_AC_TX_TST;
1229
1230 if (skge->autoneg == AUTONEG_ENABLE) {
1231 /*
1232 * Workaround BCOM Errata #1 for the C5 type.
1233 * 1000Base-T Link Acquisition Failure in Slave Mode
1234 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1235 */
1236 ctrl2 |= PHY_B_1000C_RD;
1237 if (skge->advertising & ADVERTISED_1000baseT_Half)
1238 ctrl2 |= PHY_B_1000C_AHD;
1239 if (skge->advertising & ADVERTISED_1000baseT_Full)
1240 ctrl2 |= PHY_B_1000C_AFD;
1241
1242 /* Set Flow-control capabilities */
1243 switch (skge->flow_control) {
1244 case FLOW_MODE_NONE:
1245 ctrl3 |= PHY_B_P_NO_PAUSE;
1246 break;
1247 case FLOW_MODE_LOC_SEND:
1248 ctrl3 |= PHY_B_P_ASYM_MD;
1249 break;
1250 case FLOW_MODE_SYMMETRIC:
1251 ctrl3 |= PHY_B_P_SYM_MD;
1252 break;
1253 case FLOW_MODE_REM_SEND:
1254 ctrl3 |= PHY_B_P_BOTH_MD;
1255 break;
1256 }
1257
1258 /* Restart Auto-negotiation */
1259 ctrl1 |= PHY_CT_ANE | PHY_CT_RE_CFG;
1260 } else {
1261 if (skge->duplex == DUPLEX_FULL)
1262 ctrl1 |= PHY_CT_DUP_MD;
1263
1264 ctrl2 |= PHY_B_1000C_MSE; /* set it to Slave */
1265 }
1266
1267 skge_xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, ctrl2);
1268 skge_xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV, ctrl3);
1269
1270 if (skge->netdev->mtu > ETH_DATA_LEN) {
1271 ctrl4 |= PHY_B_PEC_HIGH_LA;
1272 ctrl5 |= PHY_B_AC_LONG_PACK;
1273
1274 skge_xm_phy_write(hw, port,PHY_BCOM_AUX_CTRL, ctrl5);
1275 }
1276
1277 skge_xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ctrl4);
1278 skge_xm_phy_write(hw, port, PHY_BCOM_CTRL, ctrl1);
1279 break;
1280 }
1281 spin_unlock_bh(&hw->phy_lock);
1282
1283 /* Clear MIB counters */
1284 skge_xm_write16(hw, port, XM_STAT_CMD,
1285 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1286 /* Clear two times according to Errata #3 */
1287 skge_xm_write16(hw, port, XM_STAT_CMD,
1288 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1289
1290 /* Start polling for link status */
1291 mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1292}
1293
1294static void genesis_stop(struct skge_port *skge)
1295{
1296 struct skge_hw *hw = skge->hw;
1297 int port = skge->port;
1298
1299 /* Clear Tx packet arbiter timeout IRQ */
1300 skge_write16(hw, B3_PA_CTRL,
1301 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1302
1303 /*
1304 * If the transfer stucks at the MAC the STOP command will not
1305 * terminate if we don't flush the XMAC's transmit FIFO !
1306 */
1307 skge_xm_write32(hw, port, XM_MODE,
1308 skge_xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1309
1310
1311 /* Reset the MAC */
1312 skge_write16(hw, SKGEMAC_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1313
1314 /* For external PHYs there must be special handling */
1315 if (hw->phy_type != SK_PHY_XMAC) {
1316 u32 reg = skge_read32(hw, B2_GP_IO);
1317
1318 if (port == 0) {
1319 reg |= GP_DIR_0;
1320 reg &= ~GP_IO_0;
1321 } else {
1322 reg |= GP_DIR_2;
1323 reg &= ~GP_IO_2;
1324 }
1325 skge_write32(hw, B2_GP_IO, reg);
1326 skge_read32(hw, B2_GP_IO);
1327 }
1328
1329 skge_xm_write16(hw, port, XM_MMU_CMD,
1330 skge_xm_read16(hw, port, XM_MMU_CMD)
1331 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1332
1333 skge_xm_read16(hw, port, XM_MMU_CMD);
1334}
1335
1336
1337static void genesis_get_stats(struct skge_port *skge, u64 *data)
1338{
1339 struct skge_hw *hw = skge->hw;
1340 int port = skge->port;
1341 int i;
1342 unsigned long timeout = jiffies + HZ;
1343
1344 skge_xm_write16(hw, port,
1345 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1346
1347 /* wait for update to complete */
1348 while (skge_xm_read16(hw, port, XM_STAT_CMD)
1349 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1350 if (time_after(jiffies, timeout))
1351 break;
1352 udelay(10);
1353 }
1354
1355 /* special case for 64 bit octet counter */
1356 data[0] = (u64) skge_xm_read32(hw, port, XM_TXO_OK_HI) << 32
1357 | skge_xm_read32(hw, port, XM_TXO_OK_LO);
1358 data[1] = (u64) skge_xm_read32(hw, port, XM_RXO_OK_HI) << 32
1359 | skge_xm_read32(hw, port, XM_RXO_OK_LO);
1360
1361 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1362 data[i] = skge_xm_read32(hw, port, skge_stats[i].xmac_offset);
1363}
1364
1365static void genesis_mac_intr(struct skge_hw *hw, int port)
1366{
1367 struct skge_port *skge = netdev_priv(hw->dev[port]);
1368 u16 status = skge_xm_read16(hw, port, XM_ISRC);
1369
1370 pr_debug("genesis_intr status %x\n", status);
1371 if (hw->phy_type == SK_PHY_XMAC) {
1372 /* LInk down, start polling for state change */
1373 if (status & XM_IS_INP_ASS) {
1374 skge_xm_write16(hw, port, XM_IMSK,
1375 skge_xm_read16(hw, port, XM_IMSK) | XM_IS_INP_ASS);
1376 mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1377 }
1378 else if (status & XM_IS_AND)
1379 mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1380 }
1381
1382 if (status & XM_IS_TXF_UR) {
1383 skge_xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1384 ++skge->net_stats.tx_fifo_errors;
1385 }
1386 if (status & XM_IS_RXF_OV) {
1387 skge_xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1388 ++skge->net_stats.rx_fifo_errors;
1389 }
1390}
1391
1392static void skge_gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1393{
1394 int i;
1395
1396 skge_gma_write16(hw, port, GM_SMI_DATA, val);
1397 skge_gma_write16(hw, port, GM_SMI_CTRL,
1398 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1399 for (i = 0; i < PHY_RETRIES; i++) {
1400 udelay(1);
1401
1402 if (!(skge_gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1403 break;
1404 }
1405}
1406
1407static u16 skge_gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1408{
1409 int i;
1410
1411 skge_gma_write16(hw, port, GM_SMI_CTRL,
1412 GM_SMI_CT_PHY_AD(hw->phy_addr)
1413 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1414
1415 for (i = 0; i < PHY_RETRIES; i++) {
1416 udelay(1);
1417 if (skge_gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1418 goto ready;
1419 }
1420
1421 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1422 hw->dev[port]->name);
1423 return 0;
1424 ready:
1425 return skge_gma_read16(hw, port, GM_SMI_DATA);
1426}
1427
1428static void genesis_link_down(struct skge_port *skge)
1429{
1430 struct skge_hw *hw = skge->hw;
1431 int port = skge->port;
1432
1433 pr_debug("genesis_link_down\n");
1434
1435 skge_xm_write16(hw, port, XM_MMU_CMD,
1436 skge_xm_read16(hw, port, XM_MMU_CMD)
1437 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1438
1439 /* dummy read to ensure writing */
1440 (void) skge_xm_read16(hw, port, XM_MMU_CMD);
1441
1442 skge_link_down(skge);
1443}
1444
1445static void genesis_link_up(struct skge_port *skge)
1446{
1447 struct skge_hw *hw = skge->hw;
1448 int port = skge->port;
1449 u16 cmd;
1450 u32 mode, msk;
1451
1452 pr_debug("genesis_link_up\n");
1453 cmd = skge_xm_read16(hw, port, XM_MMU_CMD);
1454
1455 /*
1456 * enabling pause frame reception is required for 1000BT
1457 * because the XMAC is not reset if the link is going down
1458 */
1459 if (skge->flow_control == FLOW_MODE_NONE ||
1460 skge->flow_control == FLOW_MODE_LOC_SEND)
1461 cmd |= XM_MMU_IGN_PF;
1462 else
1463 /* Enable Pause Frame Reception */
1464 cmd &= ~XM_MMU_IGN_PF;
1465
1466 skge_xm_write16(hw, port, XM_MMU_CMD, cmd);
1467
1468 mode = skge_xm_read32(hw, port, XM_MODE);
1469 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1470 skge->flow_control == FLOW_MODE_LOC_SEND) {
1471 /*
1472 * Configure Pause Frame Generation
1473 * Use internal and external Pause Frame Generation.
1474 * Sending pause frames is edge triggered.
1475 * Send a Pause frame with the maximum pause time if
1476 * internal oder external FIFO full condition occurs.
1477 * Send a zero pause time frame to re-start transmission.
1478 */
1479 /* XM_PAUSE_DA = '010000C28001' (default) */
1480 /* XM_MAC_PTIME = 0xffff (maximum) */
1481 /* remember this value is defined in big endian (!) */
1482 skge_xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1483
1484 mode |= XM_PAUSE_MODE;
1485 skge_write16(hw, SKGEMAC_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1486 } else {
1487 /*
1488 * disable pause frame generation is required for 1000BT
1489 * because the XMAC is not reset if the link is going down
1490 */
1491 /* Disable Pause Mode in Mode Register */
1492 mode &= ~XM_PAUSE_MODE;
1493
1494 skge_write16(hw, SKGEMAC_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1495 }
1496
1497 skge_xm_write32(hw, port, XM_MODE, mode);
1498
1499 msk = XM_DEF_MSK;
1500 if (hw->phy_type != SK_PHY_XMAC)
1501 msk |= XM_IS_INP_ASS; /* disable GP0 interrupt bit */
1502
1503 skge_xm_write16(hw, port, XM_IMSK, msk);
1504 skge_xm_read16(hw, port, XM_ISRC);
1505
1506 /* get MMU Command Reg. */
1507 cmd = skge_xm_read16(hw, port, XM_MMU_CMD);
1508 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1509 cmd |= XM_MMU_GMII_FD;
1510
1511 if (hw->phy_type == SK_PHY_BCOM) {
1512 /*
1513 * Workaround BCOM Errata (#10523) for all BCom Phys
1514 * Enable Power Management after link up
1515 */
1516 skge_xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1517 skge_xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1518 & ~PHY_B_AC_DIS_PM);
1519 skge_xm_phy_write(hw, port, PHY_BCOM_INT_MASK,
1520 PHY_B_DEF_MSK);
1521 }
1522
1523 /* enable Rx/Tx */
1524 skge_xm_write16(hw, port, XM_MMU_CMD,
1525 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1526 skge_link_up(skge);
1527}
1528
1529
1530static void genesis_bcom_intr(struct skge_port *skge)
1531{
1532 struct skge_hw *hw = skge->hw;
1533 int port = skge->port;
1534 u16 stat = skge_xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1535
1536 pr_debug("genesis_bcom intr stat=%x\n", stat);
1537
1538 /* Workaround BCom Errata:
1539 * enable and disable loopback mode if "NO HCD" occurs.
1540 */
1541 if (stat & PHY_B_IS_NO_HDCL) {
1542 u16 ctrl = skge_xm_phy_read(hw, port, PHY_BCOM_CTRL);
1543 skge_xm_phy_write(hw, port, PHY_BCOM_CTRL,
1544 ctrl | PHY_CT_LOOP);
1545 skge_xm_phy_write(hw, port, PHY_BCOM_CTRL,
1546 ctrl & ~PHY_CT_LOOP);
1547 }
1548
1549 stat = skge_xm_phy_read(hw, port, PHY_BCOM_STAT);
1550 if (stat & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) {
1551 u16 aux = skge_xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1552 if ( !(aux & PHY_B_AS_LS) && netif_carrier_ok(skge->netdev))
1553 genesis_link_down(skge);
1554
1555 else if (stat & PHY_B_IS_LST_CHANGE) {
1556 if (aux & PHY_B_AS_AN_C) {
1557 switch (aux & PHY_B_AS_AN_RES_MSK) {
1558 case PHY_B_RES_1000FD:
1559 skge->duplex = DUPLEX_FULL;
1560 break;
1561 case PHY_B_RES_1000HD:
1562 skge->duplex = DUPLEX_HALF;
1563 break;
1564 }
1565
1566 switch (aux & PHY_B_AS_PAUSE_MSK) {
1567 case PHY_B_AS_PAUSE_MSK:
1568 skge->flow_control = FLOW_MODE_SYMMETRIC;
1569 break;
1570 case PHY_B_AS_PRR:
1571 skge->flow_control = FLOW_MODE_REM_SEND;
1572 break;
1573 case PHY_B_AS_PRT:
1574 skge->flow_control = FLOW_MODE_LOC_SEND;
1575 break;
1576 default:
1577 skge->flow_control = FLOW_MODE_NONE;
1578 }
1579 skge->speed = SPEED_1000;
1580 }
1581 genesis_link_up(skge);
1582 }
1583 else
1584 mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1585 }
1586}
1587
1588/* Perodic poll of phy status to check for link transistion */
1589static void skge_link_timer(unsigned long __arg)
1590{
1591 struct skge_port *skge = (struct skge_port *) __arg;
1592 struct skge_hw *hw = skge->hw;
1593 int port = skge->port;
1594
1595 if (hw->chip_id != CHIP_ID_GENESIS || !netif_running(skge->netdev))
1596 return;
1597
1598 spin_lock_bh(&hw->phy_lock);
1599 if (hw->phy_type == SK_PHY_BCOM)
1600 genesis_bcom_intr(skge);
1601 else {
1602 int i;
1603 for (i = 0; i < 3; i++)
1604 if (skge_xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS)
1605 break;
1606
1607 if (i == 3)
1608 mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
1609 else
1610 genesis_link_up(skge);
1611 }
1612 spin_unlock_bh(&hw->phy_lock);
1613}
1614
1615/* Marvell Phy Initailization */
1616static void yukon_init(struct skge_hw *hw, int port)
1617{
1618 struct skge_port *skge = netdev_priv(hw->dev[port]);
1619 u16 ctrl, ct1000, adv;
1620 u16 ledctrl, ledover;
1621
1622 pr_debug("yukon_init\n");
1623 if (skge->autoneg == AUTONEG_ENABLE) {
1624 u16 ectrl = skge_gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1625
1626 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1627 PHY_M_EC_MAC_S_MSK);
1628 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1629
1630 /* on PHY 88E1111 there is a change for downshift control */
1631 if (hw->chip_id == CHIP_ID_YUKON_EC)
1632 ectrl |= PHY_M_EC_M_DSC_2(0) | PHY_M_EC_DOWN_S_ENA;
1633 else
1634 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1635
1636 skge_gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1637 }
1638
1639 ctrl = skge_gm_phy_read(hw, port, PHY_MARV_CTRL);
1640 if (skge->autoneg == AUTONEG_DISABLE)
1641 ctrl &= ~PHY_CT_ANE;
1642
1643 ctrl |= PHY_CT_RESET;
1644 skge_gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1645
1646 ctrl = 0;
1647 ct1000 = 0;
1648 adv = PHY_SEL_TYPE;
1649
1650 if (skge->autoneg == AUTONEG_ENABLE) {
1651 if (iscopper(hw)) {
1652 if (skge->advertising & ADVERTISED_1000baseT_Full)
1653 ct1000 |= PHY_M_1000C_AFD;
1654 if (skge->advertising & ADVERTISED_1000baseT_Half)
1655 ct1000 |= PHY_M_1000C_AHD;
1656 if (skge->advertising & ADVERTISED_100baseT_Full)
1657 adv |= PHY_M_AN_100_FD;
1658 if (skge->advertising & ADVERTISED_100baseT_Half)
1659 adv |= PHY_M_AN_100_HD;
1660 if (skge->advertising & ADVERTISED_10baseT_Full)
1661 adv |= PHY_M_AN_10_FD;
1662 if (skge->advertising & ADVERTISED_10baseT_Half)
1663 adv |= PHY_M_AN_10_HD;
1664
1665 /* Set Flow-control capabilities */
1666 switch (skge->flow_control) {
1667 case FLOW_MODE_NONE:
1668 adv |= PHY_B_P_NO_PAUSE;
1669 break;
1670 case FLOW_MODE_LOC_SEND:
1671 adv |= PHY_B_P_ASYM_MD;
1672 break;
1673 case FLOW_MODE_SYMMETRIC:
1674 adv |= PHY_B_P_SYM_MD;
1675 break;
1676 case FLOW_MODE_REM_SEND:
1677 adv |= PHY_B_P_BOTH_MD;
1678 break;
1679 }
1680 } else { /* special defines for FIBER (88E1011S only) */
1681 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1682
1683 /* Set Flow-control capabilities */
1684 switch (skge->flow_control) {
1685 case FLOW_MODE_NONE:
1686 adv |= PHY_M_P_NO_PAUSE_X;
1687 break;
1688 case FLOW_MODE_LOC_SEND:
1689 adv |= PHY_M_P_ASYM_MD_X;
1690 break;
1691 case FLOW_MODE_SYMMETRIC:
1692 adv |= PHY_M_P_SYM_MD_X;
1693 break;
1694 case FLOW_MODE_REM_SEND:
1695 adv |= PHY_M_P_BOTH_MD_X;
1696 break;
1697 }
1698 }
1699 /* Restart Auto-negotiation */
1700 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1701 } else {
1702 /* forced speed/duplex settings */
1703 ct1000 = PHY_M_1000C_MSE;
1704
1705 if (skge->duplex == DUPLEX_FULL)
1706 ctrl |= PHY_CT_DUP_MD;
1707
1708 switch (skge->speed) {
1709 case SPEED_1000:
1710 ctrl |= PHY_CT_SP1000;
1711 break;
1712 case SPEED_100:
1713 ctrl |= PHY_CT_SP100;
1714 break;
1715 }
1716
1717 ctrl |= PHY_CT_RESET;
1718 }
1719
1720 if (hw->chip_id != CHIP_ID_YUKON_FE)
1721 skge_gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1722
1723 skge_gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1724 skge_gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1725
1726 /* Setup Phy LED's */
1727 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
1728 ledover = 0;
1729
1730 if (hw->chip_id == CHIP_ID_YUKON_FE) {
1731 /* on 88E3082 these bits are at 11..9 (shifted left) */
1732 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
1733
1734 skge_gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR,
1735 ((skge_gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR)
1736
1737 & ~PHY_M_FELP_LED1_MSK)
1738 | PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL)));
1739 } else {
1740 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
1741 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
1742
1743 /* turn off the Rx LED (LED_RX) */
1744 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
1745 }
1746
1747 /* disable blink mode (LED_DUPLEX) on collisions */
1748 ctrl |= PHY_M_LEDC_DP_CTRL;
1749 skge_gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
1750
1751 if (skge->autoneg == AUTONEG_DISABLE || skge->speed == SPEED_100) {
1752 /* turn on 100 Mbps LED (LED_LINK100) */
1753 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
1754 }
1755
1756 if (ledover)
1757 skge_gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
1758
1759 /* Enable phy interrupt on autonegotiation complete (or link up) */
1760 if (skge->autoneg == AUTONEG_ENABLE)
1761 skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
1762 else
1763 skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1764}
1765
1766static void yukon_reset(struct skge_hw *hw, int port)
1767{
1768 skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1769 skge_gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1770 skge_gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1771 skge_gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1772 skge_gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1773
1774 skge_gma_write16(hw, port, GM_RX_CTRL,
1775 skge_gma_read16(hw, port, GM_RX_CTRL)
1776 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1777}
1778
1779static void yukon_mac_init(struct skge_hw *hw, int port)
1780{
1781 struct skge_port *skge = netdev_priv(hw->dev[port]);
1782 int i;
1783 u32 reg;
1784 const u8 *addr = hw->dev[port]->dev_addr;
1785
1786 /* WA code for COMA mode -- set PHY reset */
1787 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1788 chip_rev(hw) == CHIP_REV_YU_LITE_A3)
1789 skge_write32(hw, B2_GP_IO,
1790 (skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9));
1791
1792 /* hard reset */
1793 skge_write32(hw, SKGEMAC_REG(port, GPHY_CTRL), GPC_RST_SET);
1794 skge_write32(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_RST_SET);
1795
1796 /* WA code for COMA mode -- clear PHY reset */
1797 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1798 chip_rev(hw) == CHIP_REV_YU_LITE_A3)
1799 skge_write32(hw, B2_GP_IO,
1800 (skge_read32(hw, B2_GP_IO) | GP_DIR_9)
1801 & ~GP_IO_9);
1802
1803 /* Set hardware config mode */
1804 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1805 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1806 reg |= iscopper(hw) ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1807
1808 /* Clear GMC reset */
1809 skge_write32(hw, SKGEMAC_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1810 skge_write32(hw, SKGEMAC_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1811 skge_write32(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1812 if (skge->autoneg == AUTONEG_DISABLE) {
1813 reg = GM_GPCR_AU_ALL_DIS;
1814 skge_gma_write16(hw, port, GM_GP_CTRL,
1815 skge_gma_read16(hw, port, GM_GP_CTRL) | reg);
1816
1817 switch (skge->speed) {
1818 case SPEED_1000:
1819 reg |= GM_GPCR_SPEED_1000;
1820 /* fallthru */
1821 case SPEED_100:
1822 reg |= GM_GPCR_SPEED_100;
1823 }
1824
1825 if (skge->duplex == DUPLEX_FULL)
1826 reg |= GM_GPCR_DUP_FULL;
1827 } else
1828 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1829 switch (skge->flow_control) {
1830 case FLOW_MODE_NONE:
1831 skge_write32(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1832 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1833 break;
1834 case FLOW_MODE_LOC_SEND:
1835 /* disable Rx flow-control */
1836 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1837 }
1838
1839 skge_gma_write16(hw, port, GM_GP_CTRL, reg);
1840 skge_read16(hw, GMAC_IRQ_SRC);
1841
1842 spin_lock_bh(&hw->phy_lock);
1843 yukon_init(hw, port);
1844 spin_unlock_bh(&hw->phy_lock);
1845
1846 /* MIB clear */
1847 reg = skge_gma_read16(hw, port, GM_PHY_ADDR);
1848 skge_gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1849
1850 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
1851 skge_gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1852 skge_gma_write16(hw, port, GM_PHY_ADDR, reg);
1853
1854 /* transmit control */
1855 skge_gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1856
1857 /* receive control reg: unicast + multicast + no FCS */
1858 skge_gma_write16(hw, port, GM_RX_CTRL,
1859 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1860
1861 /* transmit flow control */
1862 skge_gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1863
1864 /* transmit parameter */
1865 skge_gma_write16(hw, port, GM_TX_PARAM,
1866 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1867 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1868 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1869
1870 /* serial mode register */
1871 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1872 if (hw->dev[port]->mtu > 1500)
1873 reg |= GM_SMOD_JUMBO_ENA;
1874
1875 skge_gma_write16(hw, port, GM_SERIAL_MODE, reg);
1876
1877 /* physical address: used for pause frames */
1878 skge_gm_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1879 /* virtual address for data */
1880 skge_gm_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1881
1882 /* enable interrupt mask for counter overflows */
1883 skge_gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1884 skge_gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1885 skge_gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1886
1887 /* Initialize Mac Fifo */
1888
1889 /* Configure Rx MAC FIFO */
1890 skge_write16(hw, SKGEMAC_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1891 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1892 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1893 chip_rev(hw) == CHIP_REV_YU_LITE_A3)
1894 reg &= ~GMF_RX_F_FL_ON;
1895 skge_write8(hw, SKGEMAC_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1896 skge_write16(hw, SKGEMAC_REG(port, RX_GMF_CTRL_T), reg);
1897 skge_write16(hw, SKGEMAC_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
1898
1899 /* Configure Tx MAC FIFO */
1900 skge_write8(hw, SKGEMAC_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1901 skge_write16(hw, SKGEMAC_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1902}
1903
1904static void yukon_stop(struct skge_port *skge)
1905{
1906 struct skge_hw *hw = skge->hw;
1907 int port = skge->port;
1908
1909 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1910 chip_rev(hw) == CHIP_REV_YU_LITE_A3) {
1911 skge_write32(hw, B2_GP_IO,
1912 skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9);
1913 }
1914
1915 skge_gma_write16(hw, port, GM_GP_CTRL,
1916 skge_gma_read16(hw, port, GM_GP_CTRL)
1917 & ~(GM_GPCR_RX_ENA|GM_GPCR_RX_ENA));
1918 skge_gma_read16(hw, port, GM_GP_CTRL);
1919
1920 /* set GPHY Control reset */
1921 skge_gma_write32(hw, port, GPHY_CTRL, GPC_RST_SET);
1922 skge_gma_write32(hw, port, GMAC_CTRL, GMC_RST_SET);
1923}
1924
1925static void yukon_get_stats(struct skge_port *skge, u64 *data)
1926{
1927 struct skge_hw *hw = skge->hw;
1928 int port = skge->port;
1929 int i;
1930
1931 data[0] = (u64) skge_gma_read32(hw, port, GM_TXO_OK_HI) << 32
1932 | skge_gma_read32(hw, port, GM_TXO_OK_LO);
1933 data[1] = (u64) skge_gma_read32(hw, port, GM_RXO_OK_HI) << 32
1934 | skge_gma_read32(hw, port, GM_RXO_OK_LO);
1935
1936 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1937 data[i] = skge_gma_read32(hw, port,
1938 skge_stats[i].gma_offset);
1939}
1940
1941static void yukon_mac_intr(struct skge_hw *hw, int port)
1942{
1943 struct skge_port *skge = netdev_priv(hw->dev[port]);
1944 u8 status = skge_read8(hw, SKGEMAC_REG(port, GMAC_IRQ_SRC));
1945
1946 pr_debug("yukon_intr status %x\n", status);
1947 if (status & GM_IS_RX_FF_OR) {
1948 ++skge->net_stats.rx_fifo_errors;
1949 skge_gma_write8(hw, port, RX_GMF_CTRL_T, GMF_CLI_RX_FO);
1950 }
1951 if (status & GM_IS_TX_FF_UR) {
1952 ++skge->net_stats.tx_fifo_errors;
1953 skge_gma_write8(hw, port, TX_GMF_CTRL_T, GMF_CLI_TX_FU);
1954 }
1955
1956}
1957
1958static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1959{
1960 if (hw->chip_id == CHIP_ID_YUKON_FE)
1961 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1962
1963 switch(aux & PHY_M_PS_SPEED_MSK) {
1964 case PHY_M_PS_SPEED_1000:
1965 return SPEED_1000;
1966 case PHY_M_PS_SPEED_100:
1967 return SPEED_100;
1968 default:
1969 return SPEED_10;
1970 }
1971}
1972
1973static void yukon_link_up(struct skge_port *skge)
1974{
1975 struct skge_hw *hw = skge->hw;
1976 int port = skge->port;
1977 u16 reg;
1978
1979 pr_debug("yukon_link_up\n");
1980
1981 /* Enable Transmit FIFO Underrun */
1982 skge_write8(hw, GMAC_IRQ_MSK, GMAC_DEF_MSK);
1983
1984 reg = skge_gma_read16(hw, port, GM_GP_CTRL);
1985 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1986 reg |= GM_GPCR_DUP_FULL;
1987
1988 /* enable Rx/Tx */
1989 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1990 skge_gma_write16(hw, port, GM_GP_CTRL, reg);
1991
1992 skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1993 skge_link_up(skge);
1994}
1995
1996static void yukon_link_down(struct skge_port *skge)
1997{
1998 struct skge_hw *hw = skge->hw;
1999 int port = skge->port;
2000
2001 pr_debug("yukon_link_down\n");
2002 skge_gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2003 skge_gm_phy_write(hw, port, GM_GP_CTRL,
2004 skge_gm_phy_read(hw, port, GM_GP_CTRL)
2005 & ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA));
2006
2007 if (hw->chip_id != CHIP_ID_YUKON_FE &&
2008 skge->flow_control == FLOW_MODE_REM_SEND) {
2009 /* restore Asymmetric Pause bit */
2010 skge_gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
2011 skge_gm_phy_read(hw, port,
2012 PHY_MARV_AUNE_ADV)
2013 | PHY_M_AN_ASP);
2014
2015 }
2016
2017 yukon_reset(hw, port);
2018 skge_link_down(skge);
2019
2020 yukon_init(hw, port);
2021}
2022
2023static void yukon_phy_intr(struct skge_port *skge)
2024{
2025 struct skge_hw *hw = skge->hw;
2026 int port = skge->port;
2027 const char *reason = NULL;
2028 u16 istatus, phystat;
2029
2030 istatus = skge_gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2031 phystat = skge_gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2032 pr_debug("yukon phy intr istat=%x phy_stat=%x\n", istatus, phystat);
2033
2034 if (istatus & PHY_M_IS_AN_COMPL) {
2035 if (skge_gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2036 & PHY_M_AN_RF) {
2037 reason = "remote fault";
2038 goto failed;
2039 }
2040
2041 if (!(hw->chip_id == CHIP_ID_YUKON_FE || hw->chip_id == CHIP_ID_YUKON_EC)
2042 && (skge_gm_phy_read(hw, port, PHY_MARV_1000T_STAT)
2043 & PHY_B_1000S_MSF)) {
2044 reason = "master/slave fault";
2045 goto failed;
2046 }
2047
2048 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2049 reason = "speed/duplex";
2050 goto failed;
2051 }
2052
2053 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2054 ? DUPLEX_FULL : DUPLEX_HALF;
2055 skge->speed = yukon_speed(hw, phystat);
2056
2057 /* Tx & Rx Pause Enabled bits are at 9..8 */
2058 if (hw->chip_id == CHIP_ID_YUKON_XL)
2059 phystat >>= 6;
2060
2061 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2062 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2063 case PHY_M_PS_PAUSE_MSK:
2064 skge->flow_control = FLOW_MODE_SYMMETRIC;
2065 break;
2066 case PHY_M_PS_RX_P_EN:
2067 skge->flow_control = FLOW_MODE_REM_SEND;
2068 break;
2069 case PHY_M_PS_TX_P_EN:
2070 skge->flow_control = FLOW_MODE_LOC_SEND;
2071 break;
2072 default:
2073 skge->flow_control = FLOW_MODE_NONE;
2074 }
2075
2076 if (skge->flow_control == FLOW_MODE_NONE ||
2077 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2078 skge_write8(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2079 else
2080 skge_write8(hw, SKGEMAC_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2081 yukon_link_up(skge);
2082 return;
2083 }
2084
2085 if (istatus & PHY_M_IS_LSP_CHANGE)
2086 skge->speed = yukon_speed(hw, phystat);
2087
2088 if (istatus & PHY_M_IS_DUP_CHANGE)
2089 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2090 if (istatus & PHY_M_IS_LST_CHANGE) {
2091 if (phystat & PHY_M_PS_LINK_UP)
2092 yukon_link_up(skge);
2093 else
2094 yukon_link_down(skge);
2095 }
2096 return;
2097 failed:
2098 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2099 skge->netdev->name, reason);
2100
2101 /* XXX restart autonegotiation? */
2102}
2103
2104static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2105{
2106 u32 end;
2107
2108 start /= 8;
2109 len /= 8;
2110 end = start + len - 1;
2111
2112 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2113 skge_write32(hw, RB_ADDR(q, RB_START), start);
2114 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2115 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2116 skge_write32(hw, RB_ADDR(q, RB_END), end);
2117
2118 if (q == Q_R1 || q == Q_R2) {
2119 /* Set thresholds on receive queue's */
2120 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2121 start + (2*len)/3);
2122 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2123 start + (len/3));
2124 } else {
2125 /* Enable store & forward on Tx queue's because
2126 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2127 */
2128 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2129 }
2130
2131 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2132}
2133
2134/* Setup Bus Memory Interface */
2135static void skge_qset(struct skge_port *skge, u16 q,
2136 const struct skge_element *e)
2137{
2138 struct skge_hw *hw = skge->hw;
2139 u32 watermark = 0x600;
2140 u64 base = skge->dma + (e->desc - skge->mem);
2141
2142 /* optimization to reduce window on 32bit/33mhz */
2143 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2144 watermark /= 2;
2145
2146 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2147 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2148 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2149 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2150}
2151
2152static int skge_up(struct net_device *dev)
2153{
2154 struct skge_port *skge = netdev_priv(dev);
2155 struct skge_hw *hw = skge->hw;
2156 int port = skge->port;
2157 u32 chunk, ram_addr;
2158 size_t rx_size, tx_size;
2159 int err;
2160
2161 if (netif_msg_ifup(skge))
2162 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2163
2164 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2165 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2166 skge->mem_size = tx_size + rx_size;
2167 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2168 if (!skge->mem)
2169 return -ENOMEM;
2170
2171 memset(skge->mem, 0, skge->mem_size);
2172
2173 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2174 goto free_pci_mem;
2175
2176 if (skge_rx_fill(skge))
2177 goto free_rx_ring;
2178
2179 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2180 skge->dma + rx_size)))
2181 goto free_rx_ring;
2182
2183 skge->tx_avail = skge->tx_ring.count - 1;
2184
2185 /* Initialze MAC */
2186 if (hw->chip_id == CHIP_ID_GENESIS)
2187 genesis_mac_init(hw, port);
2188 else
2189 yukon_mac_init(hw, port);
2190
2191 /* Configure RAMbuffers */
2192 chunk = hw->ram_size / (isdualport(hw) ? 4 : 2);
2193 ram_addr = hw->ram_offset + 2 * chunk * port;
2194
2195 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2196 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2197
2198 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2199 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2200 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2201
2202 /* Start receiver BMU */
2203 wmb();
2204 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2205
2206 pr_debug("skge_up completed\n");
2207 return 0;
2208
2209 free_rx_ring:
2210 skge_rx_clean(skge);
2211 kfree(skge->rx_ring.start);
2212 free_pci_mem:
2213 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2214
2215 return err;
2216}
2217
2218static int skge_down(struct net_device *dev)
2219{
2220 struct skge_port *skge = netdev_priv(dev);
2221 struct skge_hw *hw = skge->hw;
2222 int port = skge->port;
2223
2224 if (netif_msg_ifdown(skge))
2225 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2226
2227 netif_stop_queue(dev);
2228
2229 del_timer_sync(&skge->led_blink);
2230 del_timer_sync(&skge->link_check);
2231
2232 /* Stop transmitter */
2233 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2234 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2235 RB_RST_SET|RB_DIS_OP_MD);
2236
2237 if (hw->chip_id == CHIP_ID_GENESIS)
2238 genesis_stop(skge);
2239 else
2240 yukon_stop(skge);
2241
2242 /* Disable Force Sync bit and Enable Alloc bit */
2243 skge_write8(hw, SKGEMAC_REG(port, TXA_CTRL),
2244 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2245
2246 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2247 skge_write32(hw, SKGEMAC_REG(port, TXA_ITI_INI), 0L);
2248 skge_write32(hw, SKGEMAC_REG(port, TXA_LIM_INI), 0L);
2249
2250 /* Reset PCI FIFO */
2251 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2252 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2253
2254 /* Reset the RAM Buffer async Tx queue */
2255 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2256 /* stop receiver */
2257 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2258 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2259 RB_RST_SET|RB_DIS_OP_MD);
2260 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2261
2262 if (hw->chip_id == CHIP_ID_GENESIS) {
2263 skge_write8(hw, SKGEMAC_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2264 skge_write8(hw, SKGEMAC_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2265 skge_write8(hw, SKGEMAC_REG(port, TX_LED_CTRL), LED_STOP);
2266 skge_write8(hw, SKGEMAC_REG(port, RX_LED_CTRL), LED_STOP);
2267 } else {
2268 skge_write8(hw, SKGEMAC_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2269 skge_write8(hw, SKGEMAC_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2270 }
2271
2272 /* turn off led's */
2273 skge_write16(hw, B0_LED, LED_STAT_OFF);
2274
2275 skge_tx_clean(skge);
2276 skge_rx_clean(skge);
2277
2278 kfree(skge->rx_ring.start);
2279 kfree(skge->tx_ring.start);
2280 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2281 return 0;
2282}
2283
2284static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2285{
2286 struct skge_port *skge = netdev_priv(dev);
2287 struct skge_hw *hw = skge->hw;
2288 struct skge_ring *ring = &skge->tx_ring;
2289 struct skge_element *e;
2290 struct skge_tx_desc *td;
2291 int i;
2292 u32 control, len;
2293 u64 map;
2294 unsigned long flags;
2295
2296 skb = skb_padto(skb, ETH_ZLEN);
2297 if (!skb)
2298 return NETDEV_TX_OK;
2299
2300 local_irq_save(flags);
2301 if (!spin_trylock(&skge->tx_lock)) {
2302 /* Collision - tell upper layer to requeue */
2303 local_irq_restore(flags);
2304 return NETDEV_TX_LOCKED;
2305 }
2306
2307 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2308 netif_stop_queue(dev);
2309 spin_unlock_irqrestore(&skge->tx_lock, flags);
2310
2311 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2312 dev->name);
2313 return NETDEV_TX_BUSY;
2314 }
2315
2316 e = ring->to_use;
2317 td = e->desc;
2318 e->skb = skb;
2319 len = skb_headlen(skb);
2320 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2321 pci_unmap_addr_set(e, mapaddr, map);
2322 pci_unmap_len_set(e, maplen, len);
2323
2324 td->dma_lo = map;
2325 td->dma_hi = map >> 32;
2326
2327 if (skb->ip_summed == CHECKSUM_HW) {
2328 const struct iphdr *ip
2329 = (const struct iphdr *) (skb->data + ETH_HLEN);
2330 int offset = skb->h.raw - skb->data;
2331
2332 /* This seems backwards, but it is what the sk98lin
2333 * does. Looks like hardware is wrong?
2334 */
2335 if (ip->protocol == IPPROTO_UDP
2336 && chip_rev(hw) == 0 && hw->chip_id == CHIP_ID_YUKON)
2337 control = BMU_TCP_CHECK;
2338 else
2339 control = BMU_UDP_CHECK;
2340
2341 td->csum_offs = 0;
2342 td->csum_start = offset;
2343 td->csum_write = offset + skb->csum;
2344 } else
2345 control = BMU_CHECK;
2346
2347 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2348 control |= BMU_EOF| BMU_IRQ_EOF;
2349 else {
2350 struct skge_tx_desc *tf = td;
2351
2352 control |= BMU_STFWD;
2353 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2354 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2355
2356 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2357 frag->size, PCI_DMA_TODEVICE);
2358
2359 e = e->next;
2360 e->skb = NULL;
2361 tf = e->desc;
2362 tf->dma_lo = map;
2363 tf->dma_hi = (u64) map >> 32;
2364 pci_unmap_addr_set(e, mapaddr, map);
2365 pci_unmap_len_set(e, maplen, frag->size);
2366
2367 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2368 }
2369 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2370 }
2371 /* Make sure all the descriptors written */
2372 wmb();
2373 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2374 wmb();
2375
2376 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2377
2378 if (netif_msg_tx_queued(skge))
2379 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2380 dev->name, e - ring->start, skb->len);
2381
2382 ring->to_use = e->next;
2383 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2384 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2385 pr_debug("%s: transmit queue full\n", dev->name);
2386 netif_stop_queue(dev);
2387 }
2388
2389 dev->trans_start = jiffies;
2390 spin_unlock_irqrestore(&skge->tx_lock, flags);
2391
2392 return NETDEV_TX_OK;
2393}
2394
2395static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2396{
2397 if (e->skb) {
2398 pci_unmap_single(hw->pdev,
2399 pci_unmap_addr(e, mapaddr),
2400 pci_unmap_len(e, maplen),
2401 PCI_DMA_TODEVICE);
2402 dev_kfree_skb_any(e->skb);
2403 e->skb = NULL;
2404 } else {
2405 pci_unmap_page(hw->pdev,
2406 pci_unmap_addr(e, mapaddr),
2407 pci_unmap_len(e, maplen),
2408 PCI_DMA_TODEVICE);
2409 }
2410}
2411
2412static void skge_tx_clean(struct skge_port *skge)
2413{
2414 struct skge_ring *ring = &skge->tx_ring;
2415 struct skge_element *e;
2416 unsigned long flags;
2417
2418 spin_lock_irqsave(&skge->tx_lock, flags);
2419 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2420 ++skge->tx_avail;
2421 skge_tx_free(skge->hw, e);
2422 }
2423 ring->to_clean = e;
2424 spin_unlock_irqrestore(&skge->tx_lock, flags);
2425}
2426
2427static void skge_tx_timeout(struct net_device *dev)
2428{
2429 struct skge_port *skge = netdev_priv(dev);
2430
2431 if (netif_msg_timer(skge))
2432 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2433
2434 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2435 skge_tx_clean(skge);
2436}
2437
2438static int skge_change_mtu(struct net_device *dev, int new_mtu)
2439{
2440 int err = 0;
2441
2442 if(new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2443 return -EINVAL;
2444
2445 dev->mtu = new_mtu;
2446
2447 if (netif_running(dev)) {
2448 skge_down(dev);
2449 skge_up(dev);
2450 }
2451
2452 return err;
2453}
2454
2455static void genesis_set_multicast(struct net_device *dev)
2456{
2457 struct skge_port *skge = netdev_priv(dev);
2458 struct skge_hw *hw = skge->hw;
2459 int port = skge->port;
2460 int i, count = dev->mc_count;
2461 struct dev_mc_list *list = dev->mc_list;
2462 u32 mode;
2463 u8 filter[8];
2464
2465 mode = skge_xm_read32(hw, port, XM_MODE);
2466 mode |= XM_MD_ENA_HASH;
2467 if (dev->flags & IFF_PROMISC)
2468 mode |= XM_MD_ENA_PROM;
2469 else
2470 mode &= ~XM_MD_ENA_PROM;
2471
2472 if (dev->flags & IFF_ALLMULTI)
2473 memset(filter, 0xff, sizeof(filter));
2474 else {
2475 memset(filter, 0, sizeof(filter));
2476 for(i = 0; list && i < count; i++, list = list->next) {
2477 u32 crc = crc32_le(~0, list->dmi_addr, ETH_ALEN);
2478 u8 bit = 63 - (crc & 63);
2479
2480 filter[bit/8] |= 1 << (bit%8);
2481 }
2482 }
2483
2484 skge_xm_outhash(hw, port, XM_HSM, filter);
2485
2486 skge_xm_write32(hw, port, XM_MODE, mode);
2487}
2488
2489static void yukon_set_multicast(struct net_device *dev)
2490{
2491 struct skge_port *skge = netdev_priv(dev);
2492 struct skge_hw *hw = skge->hw;
2493 int port = skge->port;
2494 struct dev_mc_list *list = dev->mc_list;
2495 u16 reg;
2496 u8 filter[8];
2497
2498 memset(filter, 0, sizeof(filter));
2499
2500 reg = skge_gma_read16(hw, port, GM_RX_CTRL);
2501 reg |= GM_RXCR_UCF_ENA;
2502
2503 if (dev->flags & IFF_PROMISC) /* promiscious */
2504 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2505 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2506 memset(filter, 0xff, sizeof(filter));
2507 else if (dev->mc_count == 0) /* no multicast */
2508 reg &= ~GM_RXCR_MCF_ENA;
2509 else {
2510 int i;
2511 reg |= GM_RXCR_MCF_ENA;
2512
2513 for(i = 0; list && i < dev->mc_count; i++, list = list->next) {
2514 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2515 filter[bit/8] |= 1 << (bit%8);
2516 }
2517 }
2518
2519
2520 skge_gma_write16(hw, port, GM_MC_ADDR_H1,
2521 (u16)filter[0] | ((u16)filter[1] << 8));
2522 skge_gma_write16(hw, port, GM_MC_ADDR_H2,
2523 (u16)filter[2] | ((u16)filter[3] << 8));
2524 skge_gma_write16(hw, port, GM_MC_ADDR_H3,
2525 (u16)filter[4] | ((u16)filter[5] << 8));
2526 skge_gma_write16(hw, port, GM_MC_ADDR_H4,
2527 (u16)filter[6] | ((u16)filter[7] << 8));
2528
2529 skge_gma_write16(hw, port, GM_RX_CTRL, reg);
2530}
2531
2532static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2533{
2534 if (hw->chip_id == CHIP_ID_GENESIS)
2535 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2536 else
2537 return (status & GMR_FS_ANY_ERR) ||
2538 (status & GMR_FS_RX_OK) == 0;
2539}
2540
2541static void skge_rx_error(struct skge_port *skge, int slot,
2542 u32 control, u32 status)
2543{
2544 if (netif_msg_rx_err(skge))
2545 printk(KERN_DEBUG PFX "%s: rx err, slot %d control 0x%x status 0x%x\n",
2546 skge->netdev->name, slot, control, status);
2547
2548 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
2549 || (control & BMU_BBC) > skge->netdev->mtu + VLAN_ETH_HLEN)
2550 skge->net_stats.rx_length_errors++;
2551 else {
2552 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2553 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2554 skge->net_stats.rx_length_errors++;
2555 if (status & XMR_FS_FRA_ERR)
2556 skge->net_stats.rx_frame_errors++;
2557 if (status & XMR_FS_FCS_ERR)
2558 skge->net_stats.rx_crc_errors++;
2559 } else {
2560 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2561 skge->net_stats.rx_length_errors++;
2562 if (status & GMR_FS_FRAGMENT)
2563 skge->net_stats.rx_frame_errors++;
2564 if (status & GMR_FS_CRC_ERR)
2565 skge->net_stats.rx_crc_errors++;
2566 }
2567 }
2568}
2569
2570static int skge_poll(struct net_device *dev, int *budget)
2571{
2572 struct skge_port *skge = netdev_priv(dev);
2573 struct skge_hw *hw = skge->hw;
2574 struct skge_ring *ring = &skge->rx_ring;
2575 struct skge_element *e;
2576 unsigned int to_do = min(dev->quota, *budget);
2577 unsigned int work_done = 0;
2578 int done;
2579 static const u32 irqmask[] = { IS_PORT_1, IS_PORT_2 };
2580
2581 for (e = ring->to_clean; e != ring->to_use && work_done < to_do;
2582 e = e->next) {
2583 struct skge_rx_desc *rd = e->desc;
2584 struct sk_buff *skb = e->skb;
2585 u32 control, len, status;
2586
2587 rmb();
2588 control = rd->control;
2589 if (control & BMU_OWN)
2590 break;
2591
2592 len = control & BMU_BBC;
2593 e->skb = NULL;
2594
2595 pci_unmap_single(hw->pdev,
2596 pci_unmap_addr(e, mapaddr),
2597 pci_unmap_len(e, maplen),
2598 PCI_DMA_FROMDEVICE);
2599
2600 status = rd->status;
2601 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
2602 || len > dev->mtu + VLAN_ETH_HLEN
2603 || bad_phy_status(hw, status)) {
2604 skge_rx_error(skge, e - ring->start, control, status);
2605 dev_kfree_skb(skb);
2606 continue;
2607 }
2608
2609 if (netif_msg_rx_status(skge))
2610 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2611 dev->name, e - ring->start, rd->status, len);
2612
2613 skb_put(skb, len);
2614 skb->protocol = eth_type_trans(skb, dev);
2615
2616 if (skge->rx_csum) {
2617 skb->csum = le16_to_cpu(rd->csum2);
2618 skb->ip_summed = CHECKSUM_HW;
2619 }
2620
2621 dev->last_rx = jiffies;
2622 netif_receive_skb(skb);
2623
2624 ++work_done;
2625 }
2626 ring->to_clean = e;
2627
2628 *budget -= work_done;
2629 dev->quota -= work_done;
2630 done = work_done < to_do;
2631
2632 if (skge_rx_fill(skge))
2633 done = 0;
2634
2635 /* restart receiver */
2636 wmb();
2637 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
2638 CSR_START | CSR_IRQ_CL_F);
2639
2640 if (done) {
2641 local_irq_disable();
2642 hw->intr_mask |= irqmask[skge->port];
2643 /* Order is important since data can get interrupted */
2644 skge_write32(hw, B0_IMSK, hw->intr_mask);
2645 __netif_rx_complete(dev);
2646 local_irq_enable();
2647 }
2648
2649 return !done;
2650}
2651
2652static inline void skge_tx_intr(struct net_device *dev)
2653{
2654 struct skge_port *skge = netdev_priv(dev);
2655 struct skge_hw *hw = skge->hw;
2656 struct skge_ring *ring = &skge->tx_ring;
2657 struct skge_element *e;
2658
2659 spin_lock(&skge->tx_lock);
2660 for(e = ring->to_clean; e != ring->to_use; e = e->next) {
2661 struct skge_tx_desc *td = e->desc;
2662 u32 control;
2663
2664 rmb();
2665 control = td->control;
2666 if (control & BMU_OWN)
2667 break;
2668
2669 if (unlikely(netif_msg_tx_done(skge)))
2670 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
2671 dev->name, e - ring->start, td->status);
2672
2673 skge_tx_free(hw, e);
2674 e->skb = NULL;
2675 ++skge->tx_avail;
2676 }
2677 ring->to_clean = e;
2678 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2679
2680 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2681 netif_wake_queue(dev);
2682
2683 spin_unlock(&skge->tx_lock);
2684}
2685
2686static void skge_mac_parity(struct skge_hw *hw, int port)
2687{
2688 printk(KERN_ERR PFX "%s: mac data parity error\n",
2689 hw->dev[port] ? hw->dev[port]->name
2690 : (port == 0 ? "(port A)": "(port B"));
2691
2692 if (hw->chip_id == CHIP_ID_GENESIS)
2693 skge_write16(hw, SKGEMAC_REG(port, TX_MFF_CTRL1),
2694 MFF_CLR_PERR);
2695 else
2696 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2697 skge_write8(hw, SKGEMAC_REG(port, TX_GMF_CTRL_T),
2698 (hw->chip_id == CHIP_ID_YUKON && chip_rev(hw) == 0)
2699 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2700}
2701
2702static void skge_pci_clear(struct skge_hw *hw)
2703{
2704 u16 status;
2705
2706 status = skge_read16(hw, SKGEPCI_REG(PCI_STATUS));
2707 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2708 skge_write16(hw, SKGEPCI_REG(PCI_STATUS),
2709 status | PCI_STATUS_ERROR_BITS);
2710 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2711}
2712
2713static void skge_mac_intr(struct skge_hw *hw, int port)
2714{
2715 if (hw->chip_id == CHIP_ID_GENESIS)
2716 genesis_mac_intr(hw, port);
2717 else
2718 yukon_mac_intr(hw, port);
2719}
2720
2721/* Handle device specific framing and timeout interrupts */
2722static void skge_error_irq(struct skge_hw *hw)
2723{
2724 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2725
2726 if (hw->chip_id == CHIP_ID_GENESIS) {
2727 /* clear xmac errors */
2728 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
2729 skge_write16(hw, SKGEMAC_REG(0, RX_MFF_CTRL1), MFF_CLR_INSTAT);
2730 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
2731 skge_write16(hw, SKGEMAC_REG(0, RX_MFF_CTRL2), MFF_CLR_INSTAT);
2732 } else {
2733 /* Timestamp (unused) overflow */
2734 if (hwstatus & IS_IRQ_TIST_OV)
2735 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2736
2737 if (hwstatus & IS_IRQ_SENSOR) {
2738 /* no sensors on 32-bit Yukon */
2739 if (!(skge_read16(hw, B0_CTST) & CS_BUS_SLOT_SZ)) {
2740 printk(KERN_ERR PFX "ignoring bogus sensor interrups\n");
2741 skge_write32(hw, B0_HWE_IMSK,
2742 IS_ERR_MSK & ~IS_IRQ_SENSOR);
2743 } else
2744 printk(KERN_WARNING PFX "sensor interrupt\n");
2745 }
2746
2747
2748 }
2749
2750 if (hwstatus & IS_RAM_RD_PAR) {
2751 printk(KERN_ERR PFX "Ram read data parity error\n");
2752 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2753 }
2754
2755 if (hwstatus & IS_RAM_WR_PAR) {
2756 printk(KERN_ERR PFX "Ram write data parity error\n");
2757 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2758 }
2759
2760 if (hwstatus & IS_M1_PAR_ERR)
2761 skge_mac_parity(hw, 0);
2762
2763 if (hwstatus & IS_M2_PAR_ERR)
2764 skge_mac_parity(hw, 1);
2765
2766 if (hwstatus & IS_R1_PAR_ERR)
2767 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2768
2769 if (hwstatus & IS_R2_PAR_ERR)
2770 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2771
2772 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2773 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2774 hwstatus);
2775
2776 skge_pci_clear(hw);
2777
2778 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2779 if (hwstatus & IS_IRQ_STAT) {
2780 printk(KERN_WARNING PFX "IRQ status %x: still set ignoring hardware errors\n",
2781 hwstatus);
2782 hw->intr_mask &= ~IS_HW_ERR;
2783 }
2784 }
2785}
2786
2787/*
2788 * Interrrupt from PHY are handled in tasklet (soft irq)
2789 * because accessing phy registers requires spin wait which might
2790 * cause excess interrupt latency.
2791 */
2792static void skge_extirq(unsigned long data)
2793{
2794 struct skge_hw *hw = (struct skge_hw *) data;
2795 int port;
2796
2797 spin_lock(&hw->phy_lock);
2798 for (port = 0; port < 2; port++) {
2799 struct net_device *dev = hw->dev[port];
2800
2801 if (dev && netif_running(dev)) {
2802 struct skge_port *skge = netdev_priv(dev);
2803
2804 if (hw->chip_id != CHIP_ID_GENESIS)
2805 yukon_phy_intr(skge);
2806 else if (hw->phy_type == SK_PHY_BCOM)
2807 genesis_bcom_intr(skge);
2808 }
2809 }
2810 spin_unlock(&hw->phy_lock);
2811
2812 local_irq_disable();
2813 hw->intr_mask |= IS_EXT_REG;
2814 skge_write32(hw, B0_IMSK, hw->intr_mask);
2815 local_irq_enable();
2816}
2817
2818static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2819{
2820 struct skge_hw *hw = dev_id;
2821 u32 status = skge_read32(hw, B0_SP_ISRC);
2822
2823 if (status == 0 || status == ~0) /* hotplug or shared irq */
2824 return IRQ_NONE;
2825
2826 status &= hw->intr_mask;
2827
2828 if ((status & IS_R1_F) && netif_rx_schedule_prep(hw->dev[0])) {
2829 status &= ~IS_R1_F;
2830 hw->intr_mask &= ~IS_R1_F;
2831 skge_write32(hw, B0_IMSK, hw->intr_mask);
2832 __netif_rx_schedule(hw->dev[0]);
2833 }
2834
2835 if ((status & IS_R2_F) && netif_rx_schedule_prep(hw->dev[1])) {
2836 status &= ~IS_R2_F;
2837 hw->intr_mask &= ~IS_R2_F;
2838 skge_write32(hw, B0_IMSK, hw->intr_mask);
2839 __netif_rx_schedule(hw->dev[1]);
2840 }
2841
2842 if (status & IS_XA1_F)
2843 skge_tx_intr(hw->dev[0]);
2844
2845 if (status & IS_XA2_F)
2846 skge_tx_intr(hw->dev[1]);
2847
2848 if (status & IS_MAC1)
2849 skge_mac_intr(hw, 0);
2850
2851 if (status & IS_MAC2)
2852 skge_mac_intr(hw, 1);
2853
2854 if (status & IS_HW_ERR)
2855 skge_error_irq(hw);
2856
2857 if (status & IS_EXT_REG) {
2858 hw->intr_mask &= ~IS_EXT_REG;
2859 tasklet_schedule(&hw->ext_tasklet);
2860 }
2861
2862 if (status)
2863 skge_write32(hw, B0_IMSK, hw->intr_mask);
2864
2865 return IRQ_HANDLED;
2866}
2867
2868#ifdef CONFIG_NET_POLL_CONTROLLER
2869static void skge_netpoll(struct net_device *dev)
2870{
2871 struct skge_port *skge = netdev_priv(dev);
2872
2873 disable_irq(dev->irq);
2874 skge_intr(dev->irq, skge->hw, NULL);
2875 enable_irq(dev->irq);
2876}
2877#endif
2878
2879static int skge_set_mac_address(struct net_device *dev, void *p)
2880{
2881 struct skge_port *skge = netdev_priv(dev);
2882 struct sockaddr *addr = p;
2883 int err = 0;
2884
2885 if (!is_valid_ether_addr(addr->sa_data))
2886 return -EADDRNOTAVAIL;
2887
2888 skge_down(dev);
2889 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2890 memcpy_toio(skge->hw->regs + B2_MAC_1 + skge->port*8,
2891 dev->dev_addr, ETH_ALEN);
2892 memcpy_toio(skge->hw->regs + B2_MAC_2 + skge->port*8,
2893 dev->dev_addr, ETH_ALEN);
2894 if (dev->flags & IFF_UP)
2895 err = skge_up(dev);
2896 return err;
2897}
2898
2899static const struct {
2900 u8 id;
2901 const char *name;
2902} skge_chips[] = {
2903 { CHIP_ID_GENESIS, "Genesis" },
2904 { CHIP_ID_YUKON, "Yukon" },
2905 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2906 { CHIP_ID_YUKON_LP, "Yukon-LP"},
2907 { CHIP_ID_YUKON_XL, "Yukon-2 XL"},
2908 { CHIP_ID_YUKON_EC, "YUKON-2 EC"},
2909 { CHIP_ID_YUKON_FE, "YUKON-2 FE"},
2910};
2911
2912static const char *skge_board_name(const struct skge_hw *hw)
2913{
2914 int i;
2915 static char buf[16];
2916
2917 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2918 if (skge_chips[i].id == hw->chip_id)
2919 return skge_chips[i].name;
2920
2921 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2922 return buf;
2923}
2924
2925
2926/*
2927 * Setup the board data structure, but don't bring up
2928 * the port(s)
2929 */
2930static int skge_reset(struct skge_hw *hw)
2931{
2932 u16 ctst;
2933 u8 t8;
2934 int i, ports;
2935
2936 ctst = skge_read16(hw, B0_CTST);
2937
2938 /* do a SW reset */
2939 skge_write8(hw, B0_CTST, CS_RST_SET);
2940 skge_write8(hw, B0_CTST, CS_RST_CLR);
2941
2942 /* clear PCI errors, if any */
2943 skge_pci_clear(hw);
2944
2945 skge_write8(hw, B0_CTST, CS_MRST_CLR);
2946
2947 /* restore CLK_RUN bits (for Yukon-Lite) */
2948 skge_write16(hw, B0_CTST,
2949 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
2950
2951 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
2952 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
2953 hw->pmd_type = skge_read8(hw, B2_PMD_TYP);
2954
2955 switch(hw->chip_id) {
2956 case CHIP_ID_GENESIS:
2957 switch (hw->phy_type) {
2958 case SK_PHY_XMAC:
2959 hw->phy_addr = PHY_ADDR_XMAC;
2960 break;
2961 case SK_PHY_BCOM:
2962 hw->phy_addr = PHY_ADDR_BCOM;
2963 break;
2964 default:
2965 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
2966 pci_name(hw->pdev), hw->phy_type);
2967 return -EOPNOTSUPP;
2968 }
2969 break;
2970
2971 case CHIP_ID_YUKON:
2972 case CHIP_ID_YUKON_LITE:
2973 case CHIP_ID_YUKON_LP:
2974 if (hw->phy_type < SK_PHY_MARV_COPPER && hw->pmd_type != 'S')
2975 hw->phy_type = SK_PHY_MARV_COPPER;
2976
2977 hw->phy_addr = PHY_ADDR_MARV;
2978 if (!iscopper(hw))
2979 hw->phy_type = SK_PHY_MARV_FIBER;
2980
2981 break;
2982
2983 default:
2984 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2985 pci_name(hw->pdev), hw->chip_id);
2986 return -EOPNOTSUPP;
2987 }
2988
2989 hw->mac_cfg = skge_read8(hw, B2_MAC_CFG);
2990 ports = isdualport(hw) ? 2 : 1;
2991
2992 /* read the adapters RAM size */
2993 t8 = skge_read8(hw, B2_E_0);
2994 if (hw->chip_id == CHIP_ID_GENESIS) {
2995 if (t8 == 3) {
2996 /* special case: 4 x 64k x 36, offset = 0x80000 */
2997 hw->ram_size = 0x100000;
2998 hw->ram_offset = 0x80000;
2999 } else
3000 hw->ram_size = t8 * 512;
3001 }
3002 else if (t8 == 0)
3003 hw->ram_size = 0x20000;
3004 else
3005 hw->ram_size = t8 * 4096;
3006
3007 if (hw->chip_id == CHIP_ID_GENESIS)
3008 genesis_init(hw);
3009 else {
3010 /* switch power to VCC (WA for VAUX problem) */
3011 skge_write8(hw, B0_POWER_CTRL,
3012 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3013 for (i = 0; i < ports; i++) {
3014 skge_write16(hw, SKGEMAC_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3015 skge_write16(hw, SKGEMAC_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3016 }
3017 }
3018
3019 /* turn off hardware timer (unused) */
3020 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3021 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3022 skge_write8(hw, B0_LED, LED_STAT_ON);
3023
3024 /* enable the Tx Arbiters */
3025 for (i = 0; i < ports; i++)
3026 skge_write8(hw, SKGEMAC_REG(i, TXA_CTRL), TXA_ENA_ARB);
3027
3028 /* Initialize ram interface */
3029 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3030
3031 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3032 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3033 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3034 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3035 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3036 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3037 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3038 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3039 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3040 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3041 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3042 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3043
3044 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3045
3046 /* Set interrupt moderation for Transmit only
3047 * Receive interrupts avoided by NAPI
3048 */
3049 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3050 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3051 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3052
3053 hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1;
3054 if (isdualport(hw))
3055 hw->intr_mask |= IS_PORT_2;
3056 skge_write32(hw, B0_IMSK, hw->intr_mask);
3057
3058 if (hw->chip_id != CHIP_ID_GENESIS)
3059 skge_write8(hw, GMAC_IRQ_MSK, 0);
3060
3061 spin_lock_bh(&hw->phy_lock);
3062 for (i = 0; i < ports; i++) {
3063 if (hw->chip_id == CHIP_ID_GENESIS)
3064 genesis_reset(hw, i);
3065 else
3066 yukon_reset(hw, i);
3067 }
3068 spin_unlock_bh(&hw->phy_lock);
3069
3070 return 0;
3071}
3072
3073/* Initialize network device */
3074static struct net_device *skge_devinit(struct skge_hw *hw, int port)
3075{
3076 struct skge_port *skge;
3077 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3078
3079 if (!dev) {
3080 printk(KERN_ERR "skge etherdev alloc failed");
3081 return NULL;
3082 }
3083
3084 SET_MODULE_OWNER(dev);
3085 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3086 dev->open = skge_up;
3087 dev->stop = skge_down;
3088 dev->hard_start_xmit = skge_xmit_frame;
3089 dev->get_stats = skge_get_stats;
3090 if (hw->chip_id == CHIP_ID_GENESIS)
3091 dev->set_multicast_list = genesis_set_multicast;
3092 else
3093 dev->set_multicast_list = yukon_set_multicast;
3094
3095 dev->set_mac_address = skge_set_mac_address;
3096 dev->change_mtu = skge_change_mtu;
3097 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3098 dev->tx_timeout = skge_tx_timeout;
3099 dev->watchdog_timeo = TX_WATCHDOG;
3100 dev->poll = skge_poll;
3101 dev->weight = NAPI_WEIGHT;
3102#ifdef CONFIG_NET_POLL_CONTROLLER
3103 dev->poll_controller = skge_netpoll;
3104#endif
3105 dev->irq = hw->pdev->irq;
3106 dev->features = NETIF_F_LLTX;
3107
3108 skge = netdev_priv(dev);
3109 skge->netdev = dev;
3110 skge->hw = hw;
3111 skge->msg_enable = netif_msg_init(debug, default_msg);
3112 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3113 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3114
3115 /* Auto speed and flow control */
3116 skge->autoneg = AUTONEG_ENABLE;
3117 skge->flow_control = FLOW_MODE_SYMMETRIC;
3118 skge->duplex = -1;
3119 skge->speed = -1;
3120 skge->advertising = skge_modes(hw);
3121
3122 hw->dev[port] = dev;
3123
3124 skge->port = port;
3125
3126 spin_lock_init(&skge->tx_lock);
3127
3128 init_timer(&skge->link_check);
3129 skge->link_check.function = skge_link_timer;
3130 skge->link_check.data = (unsigned long) skge;
3131
3132 init_timer(&skge->led_blink);
3133 skge->led_blink.function = skge_blink_timer;
3134 skge->led_blink.data = (unsigned long) skge;
3135
3136 if (hw->chip_id != CHIP_ID_GENESIS) {
3137 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3138 skge->rx_csum = 1;
3139 }
3140
3141 /* read the mac address */
3142 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3143
3144 /* device is off until link detection */
3145 netif_carrier_off(dev);
3146 netif_stop_queue(dev);
3147
3148 return dev;
3149}
3150
3151static void __devinit skge_show_addr(struct net_device *dev)
3152{
3153 const struct skge_port *skge = netdev_priv(dev);
3154
3155 if (netif_msg_probe(skge))
3156 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3157 dev->name,
3158 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3159 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3160}
3161
3162static int __devinit skge_probe(struct pci_dev *pdev,
3163 const struct pci_device_id *ent)
3164{
3165 struct net_device *dev, *dev1;
3166 struct skge_hw *hw;
3167 int err, using_dac = 0;
3168
3169 if ((err = pci_enable_device(pdev))) {
3170 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3171 pci_name(pdev));
3172 goto err_out;
3173 }
3174
3175 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3176 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3177 pci_name(pdev));
3178 goto err_out_disable_pdev;
3179 }
3180
3181 pci_set_master(pdev);
3182
3183 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)))
3184 using_dac = 1;
3185 else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3186 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3187 pci_name(pdev));
3188 goto err_out_free_regions;
3189 }
3190
3191#ifdef __BIG_ENDIAN
3192 /* byte swap decriptors in hardware */
3193 {
3194 u32 reg;
3195
3196 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3197 reg |= PCI_REV_DESC;
3198 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3199 }
3200#endif
3201
3202 err = -ENOMEM;
3203 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3204 if (!hw) {
3205 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3206 pci_name(pdev));
3207 goto err_out_free_regions;
3208 }
3209
3210 memset(hw, 0, sizeof(*hw));
3211 hw->pdev = pdev;
3212 spin_lock_init(&hw->phy_lock);
3213 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3214
3215 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3216 if (!hw->regs) {
3217 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3218 pci_name(pdev));
3219 goto err_out_free_hw;
3220 }
3221
3222 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3223 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3224 pci_name(pdev), pdev->irq);
3225 goto err_out_iounmap;
3226 }
3227 pci_set_drvdata(pdev, hw);
3228
3229 err = skge_reset(hw);
3230 if (err)
3231 goto err_out_free_irq;
3232
3233 printk(KERN_INFO PFX "addr 0x%lx irq %d chip %s rev %d\n",
3234 pci_resource_start(pdev, 0), pdev->irq,
3235 skge_board_name(hw), chip_rev(hw));
3236
3237 if ((dev = skge_devinit(hw, 0)) == NULL)
3238 goto err_out_led_off;
3239
3240 if (using_dac)
3241 dev->features |= NETIF_F_HIGHDMA;
3242
3243 if ((err = register_netdev(dev))) {
3244 printk(KERN_ERR PFX "%s: cannot register net device\n",
3245 pci_name(pdev));
3246 goto err_out_free_netdev;
3247 }
3248
3249 skge_show_addr(dev);
3250
3251 if (isdualport(hw) && (dev1 = skge_devinit(hw, 1))) {
3252 if (using_dac)
3253 dev1->features |= NETIF_F_HIGHDMA;
3254
3255 if (register_netdev(dev1) == 0)
3256 skge_show_addr(dev1);
3257 else {
3258 /* Failure to register second port need not be fatal */
3259 printk(KERN_WARNING PFX "register of second port failed\n");
3260 hw->dev[1] = NULL;
3261 free_netdev(dev1);
3262 }
3263 }
3264
3265 return 0;
3266
3267err_out_free_netdev:
3268 free_netdev(dev);
3269err_out_led_off:
3270 skge_write16(hw, B0_LED, LED_STAT_OFF);
3271err_out_free_irq:
3272 free_irq(pdev->irq, hw);
3273err_out_iounmap:
3274 iounmap(hw->regs);
3275err_out_free_hw:
3276 kfree(hw);
3277err_out_free_regions:
3278 pci_release_regions(pdev);
3279err_out_disable_pdev:
3280 pci_disable_device(pdev);
3281 pci_set_drvdata(pdev, NULL);
3282err_out:
3283 return err;
3284}
3285
3286static void __devexit skge_remove(struct pci_dev *pdev)
3287{
3288 struct skge_hw *hw = pci_get_drvdata(pdev);
3289 struct net_device *dev0, *dev1;
3290
3291 if(!hw)
3292 return;
3293
3294 if ((dev1 = hw->dev[1]))
3295 unregister_netdev(dev1);
3296 dev0 = hw->dev[0];
3297 unregister_netdev(dev0);
3298
3299 tasklet_kill(&hw->ext_tasklet);
3300
3301 free_irq(pdev->irq, hw);
3302 pci_release_regions(pdev);
3303 pci_disable_device(pdev);
3304 if (dev1)
3305 free_netdev(dev1);
3306 free_netdev(dev0);
3307 skge_write16(hw, B0_LED, LED_STAT_OFF);
3308 iounmap(hw->regs);
3309 kfree(hw);
3310 pci_set_drvdata(pdev, NULL);
3311}
3312
3313#ifdef CONFIG_PM
3314static int skge_suspend(struct pci_dev *pdev, u32 state)
3315{
3316 struct skge_hw *hw = pci_get_drvdata(pdev);
3317 int i, wol = 0;
3318
3319 for(i = 0; i < 2; i++) {
3320 struct net_device *dev = hw->dev[i];
3321
3322 if (dev) {
3323 struct skge_port *skge = netdev_priv(dev);
3324 if (netif_running(dev)) {
3325 netif_carrier_off(dev);
3326 skge_down(dev);
3327 }
3328 netif_device_detach(dev);
3329 wol |= skge->wol;
3330 }
3331 }
3332
3333 pci_save_state(pdev);
3334 pci_enable_wake(pdev, state, wol);
3335 pci_disable_device(pdev);
3336 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3337
3338 return 0;
3339}
3340
3341static int skge_resume(struct pci_dev *pdev)
3342{
3343 struct skge_hw *hw = pci_get_drvdata(pdev);
3344 int i;
3345
3346 pci_set_power_state(pdev, PCI_D0);
3347 pci_restore_state(pdev);
3348 pci_enable_wake(pdev, PCI_D0, 0);
3349
3350 skge_reset(hw);
3351
3352 for(i = 0; i < 2; i++) {
3353 struct net_device *dev = hw->dev[i];
3354 if (dev) {
3355 netif_device_attach(dev);
3356 if(netif_running(dev))
3357 skge_up(dev);
3358 }
3359 }
3360 return 0;
3361}
3362#endif
3363
3364static struct pci_driver skge_driver = {
3365 .name = DRV_NAME,
3366 .id_table = skge_id_table,
3367 .probe = skge_probe,
3368 .remove = __devexit_p(skge_remove),
3369#ifdef CONFIG_PM
3370 .suspend = skge_suspend,
3371 .resume = skge_resume,
3372#endif
3373};
3374
3375static int __init skge_init_module(void)
3376{
3377 return pci_module_init(&skge_driver);
3378}
3379
3380static void __exit skge_cleanup_module(void)
3381{
3382 pci_unregister_driver(&skge_driver);
3383}
3384
3385module_init(skge_init_module);
3386module_exit(skge_cleanup_module);
diff --git a/drivers/net/skge.h b/drivers/net/skge.h
new file mode 100644
index 000000000000..36c62b68fab4
--- /dev/null
+++ b/drivers/net/skge.h
@@ -0,0 +1,3005 @@
1/*
2 * Definitions for the new Marvell Yukon / SysKonenct driver.
3 */
4#ifndef _SKGE_H
5#define _SKGE_H
6
7/* PCI config registers */
8#define PCI_DEV_REG1 0x40
9#define PCI_DEV_REG2 0x44
10#ifndef PCI_VPD
11#define PCI_VPD 0x50
12#endif
13
14/* PCI_OUR_REG_2 32 bit Our Register 2 */
15enum {
16 PCI_VPD_WR_THR = 0xff<<24, /* Bit 31..24: VPD Write Threshold */
17 PCI_DEV_SEL = 0x7f<<17, /* Bit 23..17: EEPROM Device Select */
18 PCI_VPD_ROM_SZ = 7 <<14, /* Bit 16..14: VPD ROM Size */
19 /* Bit 13..12: reserved */
20 PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */
21 PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */
22 PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
23};
24
25/* PCI_VPD_ADR_REG 16 bit VPD Address Register */
26enum {
27 PCI_VPD_FLAG = 1<<15, /* starts VPD rd/wr cycle */
28 PCI_VPD_ADR_MSK =0x7fffL, /* Bit 14.. 0: VPD Address Mask */
29 VPD_RES_ID = 0x82,
30 VPD_RES_READ = 0x90,
31 VPD_RES_WRITE = 0x81,
32 VPD_RES_END = 0x78,
33};
34
35
36#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
37 PCI_STATUS_SIG_SYSTEM_ERROR | \
38 PCI_STATUS_REC_MASTER_ABORT | \
39 PCI_STATUS_REC_TARGET_ABORT | \
40 PCI_STATUS_PARITY)
41
42
43enum csr_regs {
44 B0_RAP = 0x0000,
45 B0_CTST = 0x0004,
46 B0_LED = 0x0006,
47 B0_POWER_CTRL = 0x0007,
48 B0_ISRC = 0x0008,
49 B0_IMSK = 0x000c,
50 B0_HWE_ISRC = 0x0010,
51 B0_HWE_IMSK = 0x0014,
52 B0_SP_ISRC = 0x0018,
53 B0_XM1_IMSK = 0x0020,
54 B0_XM1_ISRC = 0x0028,
55 B0_XM1_PHY_ADDR = 0x0030,
56 B0_XM1_PHY_DATA = 0x0034,
57 B0_XM2_IMSK = 0x0040,
58 B0_XM2_ISRC = 0x0048,
59 B0_XM2_PHY_ADDR = 0x0050,
60 B0_XM2_PHY_DATA = 0x0054,
61 B0_R1_CSR = 0x0060,
62 B0_R2_CSR = 0x0064,
63 B0_XS1_CSR = 0x0068,
64 B0_XA1_CSR = 0x006c,
65 B0_XS2_CSR = 0x0070,
66 B0_XA2_CSR = 0x0074,
67
68 B2_MAC_1 = 0x0100,
69 B2_MAC_2 = 0x0108,
70 B2_MAC_3 = 0x0110,
71 B2_CONN_TYP = 0x0118,
72 B2_PMD_TYP = 0x0119,
73 B2_MAC_CFG = 0x011a,
74 B2_CHIP_ID = 0x011b,
75 B2_E_0 = 0x011c,
76 B2_E_1 = 0x011d,
77 B2_E_2 = 0x011e,
78 B2_E_3 = 0x011f,
79 B2_FAR = 0x0120,
80 B2_FDP = 0x0124,
81 B2_LD_CTRL = 0x0128,
82 B2_LD_TEST = 0x0129,
83 B2_TI_INI = 0x0130,
84 B2_TI_VAL = 0x0134,
85 B2_TI_CTRL = 0x0138,
86 B2_TI_TEST = 0x0139,
87 B2_IRQM_INI = 0x0140,
88 B2_IRQM_VAL = 0x0144,
89 B2_IRQM_CTRL = 0x0148,
90 B2_IRQM_TEST = 0x0149,
91 B2_IRQM_MSK = 0x014c,
92 B2_IRQM_HWE_MSK = 0x0150,
93 B2_TST_CTRL1 = 0x0158,
94 B2_TST_CTRL2 = 0x0159,
95 B2_GP_IO = 0x015c,
96 B2_I2C_CTRL = 0x0160,
97 B2_I2C_DATA = 0x0164,
98 B2_I2C_IRQ = 0x0168,
99 B2_I2C_SW = 0x016c,
100 B2_BSC_INI = 0x0170,
101 B2_BSC_VAL = 0x0174,
102 B2_BSC_CTRL = 0x0178,
103 B2_BSC_STAT = 0x0179,
104 B2_BSC_TST = 0x017a,
105
106 B3_RAM_ADDR = 0x0180,
107 B3_RAM_DATA_LO = 0x0184,
108 B3_RAM_DATA_HI = 0x0188,
109 B3_RI_WTO_R1 = 0x0190,
110 B3_RI_WTO_XA1 = 0x0191,
111 B3_RI_WTO_XS1 = 0x0192,
112 B3_RI_RTO_R1 = 0x0193,
113 B3_RI_RTO_XA1 = 0x0194,
114 B3_RI_RTO_XS1 = 0x0195,
115 B3_RI_WTO_R2 = 0x0196,
116 B3_RI_WTO_XA2 = 0x0197,
117 B3_RI_WTO_XS2 = 0x0198,
118 B3_RI_RTO_R2 = 0x0199,
119 B3_RI_RTO_XA2 = 0x019a,
120 B3_RI_RTO_XS2 = 0x019b,
121 B3_RI_TO_VAL = 0x019c,
122 B3_RI_CTRL = 0x01a0,
123 B3_RI_TEST = 0x01a2,
124 B3_MA_TOINI_RX1 = 0x01b0,
125 B3_MA_TOINI_RX2 = 0x01b1,
126 B3_MA_TOINI_TX1 = 0x01b2,
127 B3_MA_TOINI_TX2 = 0x01b3,
128 B3_MA_TOVAL_RX1 = 0x01b4,
129 B3_MA_TOVAL_RX2 = 0x01b5,
130 B3_MA_TOVAL_TX1 = 0x01b6,
131 B3_MA_TOVAL_TX2 = 0x01b7,
132 B3_MA_TO_CTRL = 0x01b8,
133 B3_MA_TO_TEST = 0x01ba,
134 B3_MA_RCINI_RX1 = 0x01c0,
135 B3_MA_RCINI_RX2 = 0x01c1,
136 B3_MA_RCINI_TX1 = 0x01c2,
137 B3_MA_RCINI_TX2 = 0x01c3,
138 B3_MA_RCVAL_RX1 = 0x01c4,
139 B3_MA_RCVAL_RX2 = 0x01c5,
140 B3_MA_RCVAL_TX1 = 0x01c6,
141 B3_MA_RCVAL_TX2 = 0x01c7,
142 B3_MA_RC_CTRL = 0x01c8,
143 B3_MA_RC_TEST = 0x01ca,
144 B3_PA_TOINI_RX1 = 0x01d0,
145 B3_PA_TOINI_RX2 = 0x01d4,
146 B3_PA_TOINI_TX1 = 0x01d8,
147 B3_PA_TOINI_TX2 = 0x01dc,
148 B3_PA_TOVAL_RX1 = 0x01e0,
149 B3_PA_TOVAL_RX2 = 0x01e4,
150 B3_PA_TOVAL_TX1 = 0x01e8,
151 B3_PA_TOVAL_TX2 = 0x01ec,
152 B3_PA_CTRL = 0x01f0,
153 B3_PA_TEST = 0x01f2,
154};
155
156/* B0_CTST 16 bit Control/Status register */
157enum {
158 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
159 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
160 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
161 CS_VAUX_AVAIL = 1<<10,/* VAUX available (YUKON only) */
162 CS_BUS_CLOCK = 1<<9, /* Bus Clock 0/1 = 33/66 MHz */
163 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
164 CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
165 CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
166 CS_STOP_DONE = 1<<5, /* Stop Master is finished */
167 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
168 CS_MRST_CLR = 1<<3, /* Clear Master reset */
169 CS_MRST_SET = 1<<2, /* Set Master reset */
170 CS_RST_CLR = 1<<1, /* Clear Software reset */
171 CS_RST_SET = 1, /* Set Software reset */
172
173/* B0_LED 8 Bit LED register */
174/* Bit 7.. 2: reserved */
175 LED_STAT_ON = 1<<1, /* Status LED on */
176 LED_STAT_OFF = 1, /* Status LED off */
177
178/* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
179 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
180 PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
181 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
182 PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
183 PC_VAUX_ON = 1<<3, /* Switch VAUX On */
184 PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
185 PC_VCC_ON = 1<<1, /* Switch VCC On */
186 PC_VCC_OFF = 1<<0, /* Switch VCC Off */
187};
188
189/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
190enum {
191 IS_ALL_MSK = 0xbffffffful, /* All Interrupt bits */
192 IS_HW_ERR = 1<<31, /* Interrupt HW Error */
193 /* Bit 30: reserved */
194 IS_PA_TO_RX1 = 1<<29, /* Packet Arb Timeout Rx1 */
195 IS_PA_TO_RX2 = 1<<28, /* Packet Arb Timeout Rx2 */
196 IS_PA_TO_TX1 = 1<<27, /* Packet Arb Timeout Tx1 */
197 IS_PA_TO_TX2 = 1<<26, /* Packet Arb Timeout Tx2 */
198 IS_I2C_READY = 1<<25, /* IRQ on end of I2C Tx */
199 IS_IRQ_SW = 1<<24, /* SW forced IRQ */
200 IS_EXT_REG = 1<<23, /* IRQ from LM80 or PHY (GENESIS only) */
201 /* IRQ from PHY (YUKON only) */
202 IS_TIMINT = 1<<22, /* IRQ from Timer */
203 IS_MAC1 = 1<<21, /* IRQ from MAC 1 */
204 IS_LNK_SYNC_M1 = 1<<20, /* Link Sync Cnt wrap MAC 1 */
205 IS_MAC2 = 1<<19, /* IRQ from MAC 2 */
206 IS_LNK_SYNC_M2 = 1<<18, /* Link Sync Cnt wrap MAC 2 */
207/* Receive Queue 1 */
208 IS_R1_B = 1<<17, /* Q_R1 End of Buffer */
209 IS_R1_F = 1<<16, /* Q_R1 End of Frame */
210 IS_R1_C = 1<<15, /* Q_R1 Encoding Error */
211/* Receive Queue 2 */
212 IS_R2_B = 1<<14, /* Q_R2 End of Buffer */
213 IS_R2_F = 1<<13, /* Q_R2 End of Frame */
214 IS_R2_C = 1<<12, /* Q_R2 Encoding Error */
215/* Synchronous Transmit Queue 1 */
216 IS_XS1_B = 1<<11, /* Q_XS1 End of Buffer */
217 IS_XS1_F = 1<<10, /* Q_XS1 End of Frame */
218 IS_XS1_C = 1<<9, /* Q_XS1 Encoding Error */
219/* Asynchronous Transmit Queue 1 */
220 IS_XA1_B = 1<<8, /* Q_XA1 End of Buffer */
221 IS_XA1_F = 1<<7, /* Q_XA1 End of Frame */
222 IS_XA1_C = 1<<6, /* Q_XA1 Encoding Error */
223/* Synchronous Transmit Queue 2 */
224 IS_XS2_B = 1<<5, /* Q_XS2 End of Buffer */
225 IS_XS2_F = 1<<4, /* Q_XS2 End of Frame */
226 IS_XS2_C = 1<<3, /* Q_XS2 Encoding Error */
227/* Asynchronous Transmit Queue 2 */
228 IS_XA2_B = 1<<2, /* Q_XA2 End of Buffer */
229 IS_XA2_F = 1<<1, /* Q_XA2 End of Frame */
230 IS_XA2_C = 1<<0, /* Q_XA2 Encoding Error */
231
232 IS_PORT_1 = IS_XA1_F| IS_R1_F| IS_MAC1,
233 IS_PORT_2 = IS_XA2_F| IS_R2_F| IS_MAC2,
234};
235
236
237/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
238enum {
239 IS_ERR_MSK = 0x00003fff,/* All Error bits */
240
241 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
242 IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
243 IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
244 IS_IRQ_STAT = 1<<10, /* IRQ status exception */
245 IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
246 IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
247 IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
248 IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
249 IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
250 IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
251 IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
252 IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
253 IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
254 IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
255};
256
257/* B2_TST_CTRL1 8 bit Test Control Register 1 */
258enum {
259 TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
260 TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
261 TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
262 TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
263 TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
264 TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
265 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
266 TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
267};
268
269/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
270enum {
271 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
272 /* Bit 3.. 2: reserved */
273 CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
274 CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
275};
276
277/* B2_CHIP_ID 8 bit Chip Identification Number */
278enum {
279 CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
280 CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
281 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
282 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
283 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
284 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
285 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
286
287 CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */
288 CHIP_REV_YU_LITE_A3 = 7, /* Chip Rev. for YUKON-Lite A3 */
289};
290
291/* B2_LD_TEST 8 bit EPROM loader test register */
292enum {
293 LD_T_ON = 1<<3, /* Loader Test mode on */
294 LD_T_OFF = 1<<2, /* Loader Test mode off */
295 LD_T_STEP = 1<<1, /* Decrement FPROM addr. Counter */
296 LD_START = 1<<0, /* Start loading FPROM */
297};
298
299/* B2_TI_CTRL 8 bit Timer control */
300/* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
301enum {
302 TIM_START = 1<<2, /* Start Timer */
303 TIM_STOP = 1<<1, /* Stop Timer */
304 TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
305};
306
307/* B2_TI_TEST 8 Bit Timer Test */
308/* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
309/* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
310enum {
311 TIM_T_ON = 1<<2, /* Test mode on */
312 TIM_T_OFF = 1<<1, /* Test mode off */
313 TIM_T_STEP = 1<<0, /* Test step */
314};
315
316/* B28_DPT_INI 32 bit Descriptor Poll Timer Init Val */
317/* B28_DPT_VAL 32 bit Descriptor Poll Timer Curr Val */
318/* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
319enum {
320 DPT_MSK = 0x00ffffffL, /* Bit 23.. 0: Desc Poll Timer Bits */
321
322 DPT_START = 1<<1, /* Start Descriptor Poll Timer */
323 DPT_STOP = 1<<0, /* Stop Descriptor Poll Timer */
324};
325
326/* B2_GP_IO 32 bit General Purpose I/O Register */
327enum {
328 GP_DIR_9 = 1<<25, /* IO_9 direct, 0=In/1=Out */
329 GP_DIR_8 = 1<<24, /* IO_8 direct, 0=In/1=Out */
330 GP_DIR_7 = 1<<23, /* IO_7 direct, 0=In/1=Out */
331 GP_DIR_6 = 1<<22, /* IO_6 direct, 0=In/1=Out */
332 GP_DIR_5 = 1<<21, /* IO_5 direct, 0=In/1=Out */
333 GP_DIR_4 = 1<<20, /* IO_4 direct, 0=In/1=Out */
334 GP_DIR_3 = 1<<19, /* IO_3 direct, 0=In/1=Out */
335 GP_DIR_2 = 1<<18, /* IO_2 direct, 0=In/1=Out */
336 GP_DIR_1 = 1<<17, /* IO_1 direct, 0=In/1=Out */
337 GP_DIR_0 = 1<<16, /* IO_0 direct, 0=In/1=Out */
338
339 GP_IO_9 = 1<<9, /* IO_9 pin */
340 GP_IO_8 = 1<<8, /* IO_8 pin */
341 GP_IO_7 = 1<<7, /* IO_7 pin */
342 GP_IO_6 = 1<<6, /* IO_6 pin */
343 GP_IO_5 = 1<<5, /* IO_5 pin */
344 GP_IO_4 = 1<<4, /* IO_4 pin */
345 GP_IO_3 = 1<<3, /* IO_3 pin */
346 GP_IO_2 = 1<<2, /* IO_2 pin */
347 GP_IO_1 = 1<<1, /* IO_1 pin */
348 GP_IO_0 = 1<<0, /* IO_0 pin */
349};
350
351/* Rx/Tx Path related Arbiter Test Registers */
352/* B3_MA_TO_TEST 16 bit MAC Arbiter Timeout Test Reg */
353/* B3_MA_RC_TEST 16 bit MAC Arbiter Recovery Test Reg */
354/* B3_PA_TEST 16 bit Packet Arbiter Test Register */
355/* Bit 15, 11, 7, and 3 are reserved in B3_PA_TEST */
356enum {
357 TX2_T_EV = 1<<15,/* TX2 Timeout/Recv Event occured */
358 TX2_T_ON = 1<<14,/* TX2 Timeout/Recv Timer Test On */
359 TX2_T_OFF = 1<<13,/* TX2 Timeout/Recv Timer Tst Off */
360 TX2_T_STEP = 1<<12,/* TX2 Timeout/Recv Timer Step */
361 TX1_T_EV = 1<<11,/* TX1 Timeout/Recv Event occured */
362 TX1_T_ON = 1<<10,/* TX1 Timeout/Recv Timer Test On */
363 TX1_T_OFF = 1<<9, /* TX1 Timeout/Recv Timer Tst Off */
364 TX1_T_STEP = 1<<8, /* TX1 Timeout/Recv Timer Step */
365 RX2_T_EV = 1<<7, /* RX2 Timeout/Recv Event occured */
366 RX2_T_ON = 1<<6, /* RX2 Timeout/Recv Timer Test On */
367 RX2_T_OFF = 1<<5, /* RX2 Timeout/Recv Timer Tst Off */
368 RX2_T_STEP = 1<<4, /* RX2 Timeout/Recv Timer Step */
369 RX1_T_EV = 1<<3, /* RX1 Timeout/Recv Event occured */
370 RX1_T_ON = 1<<2, /* RX1 Timeout/Recv Timer Test On */
371 RX1_T_OFF = 1<<1, /* RX1 Timeout/Recv Timer Tst Off */
372 RX1_T_STEP = 1<<0, /* RX1 Timeout/Recv Timer Step */
373};
374
375/* Descriptor Bit Definition */
376/* TxCtrl Transmit Buffer Control Field */
377/* RxCtrl Receive Buffer Control Field */
378enum {
379 BMU_OWN = 1<<31, /* OWN bit: 0=host/1=BMU */
380 BMU_STF = 1<<30, /* Start of Frame */
381 BMU_EOF = 1<<29, /* End of Frame */
382 BMU_IRQ_EOB = 1<<28, /* Req "End of Buffer" IRQ */
383 BMU_IRQ_EOF = 1<<27, /* Req "End of Frame" IRQ */
384 /* TxCtrl specific bits */
385 BMU_STFWD = 1<<26, /* (Tx) Store & Forward Frame */
386 BMU_NO_FCS = 1<<25, /* (Tx) Disable MAC FCS (CRC) generation */
387 BMU_SW = 1<<24, /* (Tx) 1 bit res. for SW use */
388 /* RxCtrl specific bits */
389 BMU_DEV_0 = 1<<26, /* (Rx) Transfer data to Dev0 */
390 BMU_STAT_VAL = 1<<25, /* (Rx) Rx Status Valid */
391 BMU_TIST_VAL = 1<<24, /* (Rx) Rx TimeStamp Valid */
392 /* Bit 23..16: BMU Check Opcodes */
393 BMU_CHECK = 0x55<<16, /* Default BMU check */
394 BMU_TCP_CHECK = 0x56<<16, /* Descr with TCP ext */
395 BMU_UDP_CHECK = 0x57<<16, /* Descr with UDP ext (YUKON only) */
396 BMU_BBC = 0xffffL, /* Bit 15.. 0: Buffer Byte Counter */
397};
398
399/* B2_BSC_CTRL 8 bit Blink Source Counter Control */
400enum {
401 BSC_START = 1<<1, /* Start Blink Source Counter */
402 BSC_STOP = 1<<0, /* Stop Blink Source Counter */
403};
404
405/* B2_BSC_STAT 8 bit Blink Source Counter Status */
406enum {
407 BSC_SRC = 1<<0, /* Blink Source, 0=Off / 1=On */
408};
409
410/* B2_BSC_TST 16 bit Blink Source Counter Test Reg */
411enum {
412 BSC_T_ON = 1<<2, /* Test mode on */
413 BSC_T_OFF = 1<<1, /* Test mode off */
414 BSC_T_STEP = 1<<0, /* Test step */
415};
416
417/* B3_RAM_ADDR 32 bit RAM Address, to read or write */
418 /* Bit 31..19: reserved */
419#define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
420/* RAM Interface Registers */
421
422/* B3_RI_CTRL 16 bit RAM Iface Control Register */
423enum {
424 RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
425 RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
426
427 RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
428 RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
429};
430
431/* B3_RI_TEST 8 bit RAM Iface Test Register */
432enum {
433 RI_T_EV = 1<<3, /* Timeout Event occured */
434 RI_T_ON = 1<<2, /* Timeout Timer Test On */
435 RI_T_OFF = 1<<1, /* Timeout Timer Test Off */
436 RI_T_STEP = 1<<0, /* Timeout Timer Step */
437};
438
439/* MAC Arbiter Registers */
440/* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */
441enum {
442 MA_FOE_ON = 1<<3, /* XMAC Fast Output Enable ON */
443 MA_FOE_OFF = 1<<2, /* XMAC Fast Output Enable OFF */
444 MA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
445 MA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
446
447};
448
449/* Timeout values */
450#define SK_MAC_TO_53 72 /* MAC arbiter timeout */
451#define SK_PKT_TO_53 0x2000 /* Packet arbiter timeout */
452#define SK_PKT_TO_MAX 0xffff /* Maximum value */
453#define SK_RI_TO_53 36 /* RAM interface timeout */
454
455
456/* B3_MA_RC_CTRL 16 bit MAC Arbiter Recovery Ctrl Reg */
457enum {
458 MA_ENA_REC_TX2 = 1<<7, /* Enable Recovery Timer TX2 */
459 MA_DIS_REC_TX2 = 1<<6, /* Disable Recovery Timer TX2 */
460 MA_ENA_REC_TX1 = 1<<5, /* Enable Recovery Timer TX1 */
461 MA_DIS_REC_TX1 = 1<<4, /* Disable Recovery Timer TX1 */
462 MA_ENA_REC_RX2 = 1<<3, /* Enable Recovery Timer RX2 */
463 MA_DIS_REC_RX2 = 1<<2, /* Disable Recovery Timer RX2 */
464 MA_ENA_REC_RX1 = 1<<1, /* Enable Recovery Timer RX1 */
465 MA_DIS_REC_RX1 = 1<<0, /* Disable Recovery Timer RX1 */
466};
467
468/* Packet Arbiter Registers */
469/* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */
470enum {
471 PA_CLR_TO_TX2 = 1<<13, /* Clear IRQ Packet Timeout TX2 */
472 PA_CLR_TO_TX1 = 1<<12, /* Clear IRQ Packet Timeout TX1 */
473 PA_CLR_TO_RX2 = 1<<11, /* Clear IRQ Packet Timeout RX2 */
474 PA_CLR_TO_RX1 = 1<<10, /* Clear IRQ Packet Timeout RX1 */
475 PA_ENA_TO_TX2 = 1<<9, /* Enable Timeout Timer TX2 */
476 PA_DIS_TO_TX2 = 1<<8, /* Disable Timeout Timer TX2 */
477 PA_ENA_TO_TX1 = 1<<7, /* Enable Timeout Timer TX1 */
478 PA_DIS_TO_TX1 = 1<<6, /* Disable Timeout Timer TX1 */
479 PA_ENA_TO_RX2 = 1<<5, /* Enable Timeout Timer RX2 */
480 PA_DIS_TO_RX2 = 1<<4, /* Disable Timeout Timer RX2 */
481 PA_ENA_TO_RX1 = 1<<3, /* Enable Timeout Timer RX1 */
482 PA_DIS_TO_RX1 = 1<<2, /* Disable Timeout Timer RX1 */
483 PA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
484 PA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
485};
486
487#define PA_ENA_TO_ALL (PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\
488 PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
489
490
491/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */
492/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
493/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
494/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
495/* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
496
497#define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
498
499/* TXA_CTRL 8 bit Tx Arbiter Control Register */
500enum {
501 TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
502 TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
503 TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
504 TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
505 TXA_START_RC = 1<<3, /* Start sync Rate Control */
506 TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
507 TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
508 TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
509};
510
511/*
512 * Bank 4 - 5
513 */
514/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */
515enum {
516 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
517 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
518 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
519 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
520 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
521 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
522 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
523};
524
525
526enum {
527 B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
528 B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
529 B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
530 B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
531 B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
532 B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
533 B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
534 B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
535 B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
536};
537
538/* Queue Register Offsets, use Q_ADDR() to access */
539enum {
540 B8_Q_REGS = 0x0400, /* base of Queue registers */
541 Q_D = 0x00, /* 8*32 bit Current Descriptor */
542 Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
543 Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
544 Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
545 Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
546 Q_BC = 0x30, /* 32 bit Current Byte Counter */
547 Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
548 Q_F = 0x38, /* 32 bit Flag Register */
549 Q_T1 = 0x3c, /* 32 bit Test Register 1 */
550 Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
551 Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
552 Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
553 Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
554 Q_T2 = 0x40, /* 32 bit Test Register 2 */
555 Q_T3 = 0x44, /* 32 bit Test Register 3 */
556
557/* Yukon-2 */
558 Q_DONE = 0x24, /* 16 bit Done Index (Yukon-2 only) */
559 Q_WM = 0x40, /* 16 bit FIFO Watermark */
560 Q_AL = 0x42, /* 8 bit FIFO Alignment */
561 Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
562 Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */
563 Q_RP = 0x48, /* 8 bit FIFO Read Pointer */
564 Q_RL = 0x4a, /* 8 bit FIFO Read Level */
565 Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */
566 Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */
567 Q_WL = 0x4e, /* 8 bit FIFO Write Level */
568 Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */
569};
570#define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
571
572/* RAM Buffer Register Offsets */
573enum {
574
575 RB_START = 0x00,/* 32 bit RAM Buffer Start Address */
576 RB_END = 0x04,/* 32 bit RAM Buffer End Address */
577 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
578 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
579 RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
580 RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
581 RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
582 RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
583 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
584 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
585 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
586 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
587 RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
588 RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
589};
590
591/* Receive and Transmit Queues */
592enum {
593 Q_R1 = 0x0000, /* Receive Queue 1 */
594 Q_R2 = 0x0080, /* Receive Queue 2 */
595 Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
596 Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
597 Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
598 Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
599};
600
601/* Different MAC Types */
602enum {
603 SK_MAC_XMAC = 0, /* Xaqti XMAC II */
604 SK_MAC_GMAC = 1, /* Marvell GMAC */
605};
606
607/* Different PHY Types */
608enum {
609 SK_PHY_XMAC = 0,/* integrated in XMAC II */
610 SK_PHY_BCOM = 1,/* Broadcom BCM5400 */
611 SK_PHY_LONE = 2,/* Level One LXT1000 [not supported]*/
612 SK_PHY_NAT = 3,/* National DP83891 [not supported] */
613 SK_PHY_MARV_COPPER= 4,/* Marvell 88E1011S */
614 SK_PHY_MARV_FIBER = 5,/* Marvell 88E1011S working on fiber */
615};
616
617/* PHY addresses (bits 12..8 of PHY address reg) */
618enum {
619 PHY_ADDR_XMAC = 0<<8,
620 PHY_ADDR_BCOM = 1<<8,
621 PHY_ADDR_LONE = 3<<8,
622 PHY_ADDR_NAT = 0<<8,
623/* GPHY address (bits 15..11 of SMI control reg) */
624 PHY_ADDR_MARV = 0,
625};
626
627#define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs))
628
629/* Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) */
630enum {
631 RX_MFF_EA = 0x0c00,/* 32 bit Receive MAC FIFO End Address */
632 RX_MFF_WP = 0x0c04,/* 32 bit Receive MAC FIFO Write Pointer */
633
634 RX_MFF_RP = 0x0c0c,/* 32 bit Receive MAC FIFO Read Pointer */
635 RX_MFF_PC = 0x0c10,/* 32 bit Receive MAC FIFO Packet Cnt */
636 RX_MFF_LEV = 0x0c14,/* 32 bit Receive MAC FIFO Level */
637 RX_MFF_CTRL1 = 0x0c18,/* 16 bit Receive MAC FIFO Control Reg 1*/
638 RX_MFF_STAT_TO = 0x0c1a,/* 8 bit Receive MAC Status Timeout */
639 RX_MFF_TIST_TO = 0x0c1b,/* 8 bit Receive MAC Time Stamp Timeout */
640 RX_MFF_CTRL2 = 0x0c1c,/* 8 bit Receive MAC FIFO Control Reg 2*/
641 RX_MFF_TST1 = 0x0c1d,/* 8 bit Receive MAC FIFO Test Reg 1 */
642 RX_MFF_TST2 = 0x0c1e,/* 8 bit Receive MAC FIFO Test Reg 2 */
643
644 RX_LED_INI = 0x0c20,/* 32 bit Receive LED Cnt Init Value */
645 RX_LED_VAL = 0x0c24,/* 32 bit Receive LED Cnt Current Value */
646 RX_LED_CTRL = 0x0c28,/* 8 bit Receive LED Cnt Control Reg */
647 RX_LED_TST = 0x0c29,/* 8 bit Receive LED Cnt Test Register */
648
649 LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
650 LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
651 LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
652 LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
653 LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
654};
655
656/* Receive and Transmit MAC FIFO Registers (GENESIS only) */
657/* RX_MFF_CTRL1 16 bit Receive MAC FIFO Control Reg 1 */
658enum {
659 MFF_ENA_RDY_PAT = 1<<13, /* Enable Ready Patch */
660 MFF_DIS_RDY_PAT = 1<<12, /* Disable Ready Patch */
661 MFF_ENA_TIM_PAT = 1<<11, /* Enable Timing Patch */
662 MFF_DIS_TIM_PAT = 1<<10, /* Disable Timing Patch */
663 MFF_ENA_ALM_FUL = 1<<9, /* Enable AlmostFull Sign */
664 MFF_DIS_ALM_FUL = 1<<8, /* Disable AlmostFull Sign */
665 MFF_ENA_PAUSE = 1<<7, /* Enable Pause Signaling */
666 MFF_DIS_PAUSE = 1<<6, /* Disable Pause Signaling */
667 MFF_ENA_FLUSH = 1<<5, /* Enable Frame Flushing */
668 MFF_DIS_FLUSH = 1<<4, /* Disable Frame Flushing */
669 MFF_ENA_TIST = 1<<3, /* Enable Time Stamp Gener */
670 MFF_DIS_TIST = 1<<2, /* Disable Time Stamp Gener */
671 MFF_CLR_INTIST = 1<<1, /* Clear IRQ No Time Stamp */
672 MFF_CLR_INSTAT = 1<<0, /* Clear IRQ No Status */
673#define MFF_RX_CTRL_DEF MFF_ENA_TIM_PAT
674};
675
676/* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */
677enum {
678 MFF_CLR_PERR = 1<<15, /* Clear Parity Error IRQ */
679 /* Bit 14: reserved */
680 MFF_ENA_PKT_REC = 1<<13, /* Enable Packet Recovery */
681 MFF_DIS_PKT_REC = 1<<12, /* Disable Packet Recovery */
682
683 MFF_ENA_W4E = 1<<7, /* Enable Wait for Empty */
684 MFF_DIS_W4E = 1<<6, /* Disable Wait for Empty */
685
686 MFF_ENA_LOOPB = 1<<3, /* Enable Loopback */
687 MFF_DIS_LOOPB = 1<<2, /* Disable Loopback */
688 MFF_CLR_MAC_RST = 1<<1, /* Clear XMAC Reset */
689 MFF_SET_MAC_RST = 1<<0, /* Set XMAC Reset */
690};
691
692#define MFF_TX_CTRL_DEF (MFF_ENA_PKT_REC | MFF_ENA_TIM_PAT | MFF_ENA_FLUSH)
693
694/* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */
695/* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */
696enum {
697 MFF_WSP_T_ON = 1<<6, /* Tx: Write Shadow Ptr TestOn */
698 MFF_WSP_T_OFF = 1<<5, /* Tx: Write Shadow Ptr TstOff */
699 MFF_WSP_INC = 1<<4, /* Tx: Write Shadow Ptr Increment */
700 MFF_PC_DEC = 1<<3, /* Packet Counter Decrement */
701 MFF_PC_T_ON = 1<<2, /* Packet Counter Test On */
702 MFF_PC_T_OFF = 1<<1, /* Packet Counter Test Off */
703 MFF_PC_INC = 1<<0, /* Packet Counter Increment */
704};
705
706/* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */
707/* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */
708enum {
709 MFF_WP_T_ON = 1<<6, /* Write Pointer Test On */
710 MFF_WP_T_OFF = 1<<5, /* Write Pointer Test Off */
711 MFF_WP_INC = 1<<4, /* Write Pointer Increm */
712
713 MFF_RP_T_ON = 1<<2, /* Read Pointer Test On */
714 MFF_RP_T_OFF = 1<<1, /* Read Pointer Test Off */
715 MFF_RP_DEC = 1<<0, /* Read Pointer Decrement */
716};
717
718/* RX_MFF_CTRL2 8 bit Receive MAC FIFO Control Reg 2 */
719/* TX_MFF_CTRL2 8 bit Transmit MAC FIFO Control Reg 2 */
720enum {
721 MFF_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
722 MFF_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
723 MFF_RST_CLR = 1<<1, /* Clear MAC FIFO Reset */
724 MFF_RST_SET = 1<<0, /* Set MAC FIFO Reset */
725};
726
727
728/* Link LED Counter Registers (GENESIS only) */
729
730/* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */
731/* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */
732/* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */
733enum {
734 LED_START = 1<<2, /* Start Timer */
735 LED_STOP = 1<<1, /* Stop Timer */
736 LED_STATE = 1<<0, /* Rx/Tx: LED State, 1=LED on */
737};
738
739/* RX_LED_TST 8 bit Receive LED Cnt Test Register */
740/* TX_LED_TST 8 bit Transmit LED Cnt Test Register */
741/* LNK_SYNC_TST 8 bit Link Sync Cnt Test Register */
742enum {
743 LED_T_ON = 1<<2, /* LED Counter Test mode On */
744 LED_T_OFF = 1<<1, /* LED Counter Test mode Off */
745 LED_T_STEP = 1<<0, /* LED Counter Step */
746};
747
748/* LNK_LED_REG 8 bit Link LED Register */
749enum {
750 LED_BLK_ON = 1<<5, /* Link LED Blinking On */
751 LED_BLK_OFF = 1<<4, /* Link LED Blinking Off */
752 LED_SYNC_ON = 1<<3, /* Use Sync Wire to switch LED */
753 LED_SYNC_OFF = 1<<2, /* Disable Sync Wire Input */
754 LED_ON = 1<<1, /* switch LED on */
755 LED_OFF = 1<<0, /* switch LED off */
756};
757
758/* Receive GMAC FIFO (YUKON and Yukon-2) */
759enum {
760 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
761 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
762 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
763 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
764 RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
765 RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
766
767 RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
768 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
769
770 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
771
772 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
773
774 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
775};
776
777
778/* TXA_TEST 8 bit Tx Arbiter Test Register */
779enum {
780 TXA_INT_T_ON = 1<<5, /* Tx Arb Interval Timer Test On */
781 TXA_INT_T_OFF = 1<<4, /* Tx Arb Interval Timer Test Off */
782 TXA_INT_T_STEP = 1<<3, /* Tx Arb Interval Timer Step */
783 TXA_LIM_T_ON = 1<<2, /* Tx Arb Limit Timer Test On */
784 TXA_LIM_T_OFF = 1<<1, /* Tx Arb Limit Timer Test Off */
785 TXA_LIM_T_STEP = 1<<0, /* Tx Arb Limit Timer Step */
786};
787
788/* TXA_STAT 8 bit Tx Arbiter Status Register */
789enum {
790 TXA_PRIO_XS = 1<<0, /* sync queue has prio to send */
791};
792
793
794/* Q_BC 32 bit Current Byte Counter */
795
796/* BMU Control Status Registers */
797/* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
798/* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
799/* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
800/* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
801/* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
802/* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
803/* Q_CSR 32 bit BMU Control/Status Register */
804
805enum {
806 CSR_SV_IDLE = 1<<24, /* BMU SM Idle */
807
808 CSR_DESC_CLR = 1<<21, /* Clear Reset for Descr */
809 CSR_DESC_SET = 1<<20, /* Set Reset for Descr */
810 CSR_FIFO_CLR = 1<<19, /* Clear Reset for FIFO */
811 CSR_FIFO_SET = 1<<18, /* Set Reset for FIFO */
812 CSR_HPI_RUN = 1<<17, /* Release HPI SM */
813 CSR_HPI_RST = 1<<16, /* Reset HPI SM to Idle */
814 CSR_SV_RUN = 1<<15, /* Release Supervisor SM */
815 CSR_SV_RST = 1<<14, /* Reset Supervisor SM */
816 CSR_DREAD_RUN = 1<<13, /* Release Descr Read SM */
817 CSR_DREAD_RST = 1<<12, /* Reset Descr Read SM */
818 CSR_DWRITE_RUN = 1<<11, /* Release Descr Write SM */
819 CSR_DWRITE_RST = 1<<10, /* Reset Descr Write SM */
820 CSR_TRANS_RUN = 1<<9, /* Release Transfer SM */
821 CSR_TRANS_RST = 1<<8, /* Reset Transfer SM */
822 CSR_ENA_POL = 1<<7, /* Enable Descr Polling */
823 CSR_DIS_POL = 1<<6, /* Disable Descr Polling */
824 CSR_STOP = 1<<5, /* Stop Rx/Tx Queue */
825 CSR_START = 1<<4, /* Start Rx/Tx Queue */
826 CSR_IRQ_CL_P = 1<<3, /* (Rx) Clear Parity IRQ */
827 CSR_IRQ_CL_B = 1<<2, /* Clear EOB IRQ */
828 CSR_IRQ_CL_F = 1<<1, /* Clear EOF IRQ */
829 CSR_IRQ_CL_C = 1<<0, /* Clear ERR IRQ */
830};
831
832#define CSR_SET_RESET (CSR_DESC_SET | CSR_FIFO_SET | CSR_HPI_RST |\
833 CSR_SV_RST | CSR_DREAD_RST | CSR_DWRITE_RST |\
834 CSR_TRANS_RST)
835#define CSR_CLR_RESET (CSR_DESC_CLR | CSR_FIFO_CLR | CSR_HPI_RUN |\
836 CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\
837 CSR_TRANS_RUN)
838
839/* Q_F 32 bit Flag Register */
840enum {
841 F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */
842 F_EMPTY = 1<<27, /* Tx FIFO: empty flag */
843 F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */
844 F_WM_REACHED = 1<<25, /* Watermark reached */
845
846 F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */
847 F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */
848};
849
850/* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
851/* RB_START 32 bit RAM Buffer Start Address */
852/* RB_END 32 bit RAM Buffer End Address */
853/* RB_WP 32 bit RAM Buffer Write Pointer */
854/* RB_RP 32 bit RAM Buffer Read Pointer */
855/* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
856/* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
857/* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
858/* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
859/* RB_PC 32 bit RAM Buffer Packet Counter */
860/* RB_LEV 32 bit RAM Buffer Level Register */
861
862#define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
863/* RB_TST2 8 bit RAM Buffer Test Register 2 */
864/* RB_TST1 8 bit RAM Buffer Test Register 1 */
865
866/* RB_CTRL 8 bit RAM Buffer Control Register */
867enum {
868 RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
869 RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
870 RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
871 RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
872 RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
873 RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
874};
875
876/* Transmit MAC FIFO and Transmit LED Registers (GENESIS only), */
877enum {
878 TX_MFF_EA = 0x0d00,/* 32 bit Transmit MAC FIFO End Address */
879 TX_MFF_WP = 0x0d04,/* 32 bit Transmit MAC FIFO WR Pointer */
880 TX_MFF_WSP = 0x0d08,/* 32 bit Transmit MAC FIFO WR Shadow Ptr */
881 TX_MFF_RP = 0x0d0c,/* 32 bit Transmit MAC FIFO RD Pointer */
882 TX_MFF_PC = 0x0d10,/* 32 bit Transmit MAC FIFO Packet Cnt */
883 TX_MFF_LEV = 0x0d14,/* 32 bit Transmit MAC FIFO Level */
884 TX_MFF_CTRL1 = 0x0d18,/* 16 bit Transmit MAC FIFO Ctrl Reg 1 */
885 TX_MFF_WAF = 0x0d1a,/* 8 bit Transmit MAC Wait after flush */
886
887 TX_MFF_CTRL2 = 0x0d1c,/* 8 bit Transmit MAC FIFO Ctrl Reg 2 */
888 TX_MFF_TST1 = 0x0d1d,/* 8 bit Transmit MAC FIFO Test Reg 1 */
889 TX_MFF_TST2 = 0x0d1e,/* 8 bit Transmit MAC FIFO Test Reg 2 */
890
891 TX_LED_INI = 0x0d20,/* 32 bit Transmit LED Cnt Init Value */
892 TX_LED_VAL = 0x0d24,/* 32 bit Transmit LED Cnt Current Val */
893 TX_LED_CTRL = 0x0d28,/* 8 bit Transmit LED Cnt Control Reg */
894 TX_LED_TST = 0x0d29,/* 8 bit Transmit LED Cnt Test Reg */
895};
896
897/* Counter and Timer constants, for a host clock of 62.5 MHz */
898#define SK_XMIT_DUR 0x002faf08UL /* 50 ms */
899#define SK_BLK_DUR 0x01dcd650UL /* 500 ms */
900
901#define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz */
902
903#define SK_DPOLL_MAX 0x00ffffffUL /* 268 ms at 62.5 MHz */
904 /* 215 ms at 78.12 MHz */
905
906#define SK_FACT_62 100 /* is given in percent */
907#define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */
908#define SK_FACT_78 125 /* on YUKON: 78.12 MHz */
909
910
911/* Transmit GMAC FIFO (YUKON only) */
912enum {
913 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
914 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
915 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
916
917 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
918 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
919 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
920
921 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
922 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
923 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
924
925 /* Descriptor Poll Timer Registers */
926 B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
927 B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
928 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
929
930 B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
931
932 /* Time Stamp Timer Registers (YUKON only) */
933 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
934 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
935 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
936};
937
938/* Status BMU Registers (Yukon-2 only)*/
939enum {
940 STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */
941 STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */
942 /* 0x0e85 - 0x0e86: reserved */
943 STAT_LIST_ADDR_LO = 0x0e88,/* 32 bit Status List Start Addr (low) */
944 STAT_LIST_ADDR_HI = 0x0e8c,/* 32 bit Status List Start Addr (high) */
945 STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
946 STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
947 STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
948 STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
949 STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
950 STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */
951
952/* FIFO Control/Status Registers (Yukon-2 only)*/
953 STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
954 STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
955 STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
956 STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */
957 STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
958 STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */
959 STAT_FIFO_ISR_WM = 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
960
961/* Level and ISR Timer Registers (Yukon-2 only)*/
962 STAT_LEV_TIMER_INI = 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
963 STAT_LEV_TIMER_CNT = 0x0eb4,/* 32 bit Level Timer Counter Reg */
964 STAT_LEV_TIMER_CTRL = 0x0eb8,/* 8 bit Level Timer Control Reg */
965 STAT_LEV_TIMER_TEST = 0x0eb9,/* 8 bit Level Timer Test Reg */
966 STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
967 STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
968 STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
969 STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
970 STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
971 STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
972 STAT_ISR_TIMER_CTRL = 0x0ed8,/* 8 bit ISR Timer Control Reg */
973 STAT_ISR_TIMER_TEST = 0x0ed9,/* 8 bit ISR Timer Test Reg */
974
975 ST_LAST_IDX_MASK = 0x007f,/* Last Index Mask */
976 ST_TXRP_IDX_MASK = 0x0fff,/* Tx Report Index Mask */
977 ST_TXTH_IDX_MASK = 0x0fff,/* Tx Threshold Index Mask */
978 ST_WM_IDX_MASK = 0x3f,/* FIFO Watermark Index Mask */
979};
980
981enum {
982 LINKLED_OFF = 0x01,
983 LINKLED_ON = 0x02,
984 LINKLED_LINKSYNC_OFF = 0x04,
985 LINKLED_LINKSYNC_ON = 0x08,
986 LINKLED_BLINK_OFF = 0x10,
987 LINKLED_BLINK_ON = 0x20,
988};
989
990/* GMAC and GPHY Control Registers (YUKON only) */
991enum {
992 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
993 GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
994 GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
995 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
996 GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
997
998/* Wake-up Frame Pattern Match Control Registers (YUKON only) */
999
1000 WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
1001
1002 WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
1003 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
1004 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
1005 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
1006 WOL_PATT_PME = 0x0f2a,/* 8 bit WOL PME Match Enable (Yukon-2) */
1007 WOL_PATT_ASFM = 0x0f2b,/* 8 bit WOL ASF Match Enable (Yukon-2) */
1008 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
1009
1010/* WOL Pattern Length Registers (YUKON only) */
1011
1012 WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
1013 WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
1014
1015/* WOL Pattern Counter Registers (YUKON only) */
1016
1017 WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
1018 WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
1019};
1020
1021enum {
1022 WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
1023 WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
1024};
1025
1026enum {
1027 BASE_XMAC_1 = 0x2000,/* XMAC 1 registers */
1028 BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
1029 BASE_XMAC_2 = 0x3000,/* XMAC 2 registers */
1030 BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
1031};
1032
1033/*
1034 * Receive Frame Status Encoding
1035 */
1036enum {
1037 XMR_FS_LEN = 0x3fff<<18, /* Bit 31..18: Rx Frame Length */
1038 XMR_FS_2L_VLAN = 1<<17, /* Bit 17: tagged wh 2Lev VLAN ID*/
1039 XMR_FS_1_VLAN = 1<<16, /* Bit 16: tagged wh 1ev VLAN ID*/
1040 XMR_FS_BC = 1<<15, /* Bit 15: Broadcast Frame */
1041 XMR_FS_MC = 1<<14, /* Bit 14: Multicast Frame */
1042 XMR_FS_UC = 1<<13, /* Bit 13: Unicast Frame */
1043
1044 XMR_FS_BURST = 1<<11, /* Bit 11: Burst Mode */
1045 XMR_FS_CEX_ERR = 1<<10, /* Bit 10: Carrier Ext. Error */
1046 XMR_FS_802_3 = 1<<9, /* Bit 9: 802.3 Frame */
1047 XMR_FS_COL_ERR = 1<<8, /* Bit 8: Collision Error */
1048 XMR_FS_CAR_ERR = 1<<7, /* Bit 7: Carrier Event Error */
1049 XMR_FS_LEN_ERR = 1<<6, /* Bit 6: In-Range Length Error */
1050 XMR_FS_FRA_ERR = 1<<5, /* Bit 5: Framing Error */
1051 XMR_FS_RUNT = 1<<4, /* Bit 4: Runt Frame */
1052 XMR_FS_LNG_ERR = 1<<3, /* Bit 3: Giant (Jumbo) Frame */
1053 XMR_FS_FCS_ERR = 1<<2, /* Bit 2: Frame Check Sequ Err */
1054 XMR_FS_ERR = 1<<1, /* Bit 1: Frame Error */
1055 XMR_FS_MCTRL = 1<<0, /* Bit 0: MAC Control Packet */
1056
1057/*
1058 * XMR_FS_ERR will be set if
1059 * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT,
1060 * XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR
1061 * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue
1062 * XMR_FS_ERR unless the corresponding bit in the Receive Command
1063 * Register is set.
1064 */
1065};
1066
1067/*
1068,* XMAC-PHY Registers, indirect addressed over the XMAC
1069 */
1070enum {
1071 PHY_XMAC_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
1072 PHY_XMAC_STAT = 0x01,/* 16 bit r/w PHY Status Register */
1073 PHY_XMAC_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
1074 PHY_XMAC_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
1075 PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1076 PHY_XMAC_AUNE_LP = 0x05,/* 16 bit r/o Link Partner Abi Reg */
1077 PHY_XMAC_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1078 PHY_XMAC_NEPG = 0x07,/* 16 bit r/w Next Page Register */
1079 PHY_XMAC_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
1080
1081 PHY_XMAC_EXT_STAT = 0x0f,/* 16 bit r/o Ext Status Register */
1082 PHY_XMAC_RES_ABI = 0x10,/* 16 bit r/o PHY Resolved Ability */
1083};
1084/*
1085 * Broadcom-PHY Registers, indirect addressed over XMAC
1086 */
1087enum {
1088 PHY_BCOM_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
1089 PHY_BCOM_STAT = 0x01,/* 16 bit r/o PHY Status Register */
1090 PHY_BCOM_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
1091 PHY_BCOM_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
1092 PHY_BCOM_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1093 PHY_BCOM_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
1094 PHY_BCOM_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1095 PHY_BCOM_NEPG = 0x07,/* 16 bit r/w Next Page Register */
1096 PHY_BCOM_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
1097 /* Broadcom-specific registers */
1098 PHY_BCOM_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1099 PHY_BCOM_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1100 PHY_BCOM_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
1101 PHY_BCOM_P_EXT_CTRL = 0x10,/* 16 bit r/w PHY Extended Ctrl Reg */
1102 PHY_BCOM_P_EXT_STAT = 0x11,/* 16 bit r/o PHY Extended Stat Reg */
1103 PHY_BCOM_RE_CTR = 0x12,/* 16 bit r/w Receive Error Counter */
1104 PHY_BCOM_FC_CTR = 0x13,/* 16 bit r/w False Carrier Sense Cnt */
1105 PHY_BCOM_RNO_CTR = 0x14,/* 16 bit r/w Receiver NOT_OK Cnt */
1106
1107 PHY_BCOM_AUX_CTRL = 0x18,/* 16 bit r/w Auxiliary Control Reg */
1108 PHY_BCOM_AUX_STAT = 0x19,/* 16 bit r/o Auxiliary Stat Summary */
1109 PHY_BCOM_INT_STAT = 0x1a,/* 16 bit r/o Interrupt Status Reg */
1110 PHY_BCOM_INT_MASK = 0x1b,/* 16 bit r/w Interrupt Mask Reg */
1111};
1112
1113/*
1114 * Marvel-PHY Registers, indirect addressed over GMAC
1115 */
1116enum {
1117 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
1118 PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
1119 PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
1120 PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
1121 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1122 PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
1123 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1124 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
1125 PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
1126 /* Marvel-specific registers */
1127 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1128 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1129 PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
1130 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
1131 PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
1132 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
1133 PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
1134 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
1135 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
1136 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
1137 PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
1138 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
1139 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
1140 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
1141 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
1142 PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
1143 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
1144 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
1145
1146/* for 10/100 Fast Ethernet PHY (88E3082 only) */
1147 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
1148 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
1149 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
1150 PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
1151 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
1152};
1153
1154/* Level One-PHY Registers, indirect addressed over XMAC */
1155enum {
1156 PHY_LONE_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
1157 PHY_LONE_STAT = 0x01,/* 16 bit r/o PHY Status Register */
1158 PHY_LONE_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
1159 PHY_LONE_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
1160 PHY_LONE_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1161 PHY_LONE_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
1162 PHY_LONE_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1163 PHY_LONE_NEPG = 0x07,/* 16 bit r/w Next Page Register */
1164 PHY_LONE_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
1165 /* Level One-specific registers */
1166 PHY_LONE_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1167 PHY_LONE_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1168 PHY_LONE_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
1169 PHY_LONE_PORT_CFG = 0x10,/* 16 bit r/w Port Configuration Reg*/
1170 PHY_LONE_Q_STAT = 0x11,/* 16 bit r/o Quick Status Reg */
1171 PHY_LONE_INT_ENAB = 0x12,/* 16 bit r/w Interrupt Enable Reg */
1172 PHY_LONE_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
1173 PHY_LONE_LED_CFG = 0x14,/* 16 bit r/w LED Configuration Reg */
1174 PHY_LONE_PORT_CTRL = 0x15,/* 16 bit r/w Port Control Reg */
1175 PHY_LONE_CIM = 0x16,/* 16 bit r/o CIM Reg */
1176};
1177
1178/* National-PHY Registers, indirect addressed over XMAC */
1179enum {
1180 PHY_NAT_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
1181 PHY_NAT_STAT = 0x01,/* 16 bit r/w PHY Status Register */
1182 PHY_NAT_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
1183 PHY_NAT_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
1184 PHY_NAT_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1185 PHY_NAT_AUNE_LP = 0x05,/* 16 bit r/o Link Partner Ability Reg */
1186 PHY_NAT_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1187 PHY_NAT_NEPG = 0x07,/* 16 bit r/w Next Page Register */
1188 PHY_NAT_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner Reg */
1189 /* National-specific registers */
1190 PHY_NAT_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1191 PHY_NAT_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1192 PHY_NAT_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Register */
1193 PHY_NAT_EXT_CTRL1 = 0x10,/* 16 bit r/o Extended Control Reg1 */
1194 PHY_NAT_Q_STAT1 = 0x11,/* 16 bit r/o Quick Status Reg1 */
1195 PHY_NAT_10B_OP = 0x12,/* 16 bit r/o 10Base-T Operations Reg */
1196 PHY_NAT_EXT_CTRL2 = 0x13,/* 16 bit r/o Extended Control Reg1 */
1197 PHY_NAT_Q_STAT2 = 0x14,/* 16 bit r/o Quick Status Reg2 */
1198
1199 PHY_NAT_PHY_ADDR = 0x19,/* 16 bit r/o PHY Address Register */
1200};
1201
1202enum {
1203 PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
1204 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
1205 PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
1206 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
1207 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
1208 PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
1209 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
1210 PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
1211 PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
1212 PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
1213};
1214
1215enum {
1216 PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
1217 PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
1218 PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
1219};
1220
1221enum {
1222 PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
1223
1224 PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
1225 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
1226 PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */
1227 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
1228 PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
1229 PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
1230 PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
1231};
1232
1233enum {
1234 PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
1235 PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
1236 PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
1237};
1238
1239/* different Broadcom PHY Ids */
1240enum {
1241 PHY_BCOM_ID1_A1 = 0x6041,
1242 PHY_BCOM_ID1_B2 = 0x6043,
1243 PHY_BCOM_ID1_C0 = 0x6044,
1244 PHY_BCOM_ID1_C5 = 0x6047,
1245};
1246
1247/* different Marvell PHY Ids */
1248enum {
1249 PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
1250 PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
1251 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1252 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
1253 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
1254};
1255
1256enum {
1257 PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
1258 PHY_X_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
1259 PHY_X_AN_RFB = 3<<12,/* Bit 13..12: Remote Fault Bits */
1260
1261 PHY_X_AN_PAUSE = 3<<7,/* Bit 8.. 7: Pause Bits */
1262 PHY_X_AN_HD = 1<<6, /* Bit 6: Half Duplex */
1263 PHY_X_AN_FD = 1<<5, /* Bit 5: Full Duplex */
1264};
1265
1266enum {
1267 PHY_B_AN_RF = 1<<13, /* Bit 13: Remote Fault */
1268
1269 PHY_B_AN_ASP = 1<<11, /* Bit 11: Asymmetric Pause */
1270 PHY_B_AN_PC = 1<<10, /* Bit 10: Pause Capable */
1271 PHY_B_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
1272};
1273
1274enum {
1275 PHY_L_AN_RF = 1<<13, /* Bit 13: Remote Fault */
1276 /* Bit 12: reserved */
1277 PHY_L_AN_ASP = 1<<11, /* Bit 11: Asymmetric Pause */
1278 PHY_L_AN_PC = 1<<10, /* Bit 10: Pause Capable */
1279
1280 PHY_L_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
1281};
1282
1283/* PHY_NAT_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement */
1284/* PHY_NAT_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
1285/* PHY_AN_NXT_PG (see XMAC) Bit 15: Request Next Page */
1286enum {
1287 PHY_N_AN_RF = 1<<13, /* Bit 13: Remote Fault */
1288
1289 PHY_N_AN_100F = 1<<11, /* Bit 11: 100Base-T2 FD Support */
1290 PHY_N_AN_100H = 1<<10, /* Bit 10: 100Base-T2 HD Support */
1291
1292 PHY_N_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
1293};
1294
1295/* field type definition for PHY_x_AN_SEL */
1296enum {
1297 PHY_SEL_TYPE = 1, /* 00001 = Ethernet */
1298};
1299
1300enum {
1301 PHY_ANE_LP_NP = 1<<3, /* Bit 3: Link Partner can Next Page */
1302 PHY_ANE_LOC_NP = 1<<2, /* Bit 2: Local PHY can Next Page */
1303 PHY_ANE_RX_PG = 1<<1, /* Bit 1: Page Received */
1304};
1305
1306enum {
1307 PHY_ANE_PAR_DF = 1<<4, /* Bit 4: Parallel Detection Fault */
1308
1309 PHY_ANE_LP_CAP = 1<<0, /* Bit 0: Link Partner Auto-Neg. Cap. */
1310};
1311
1312enum {
1313 PHY_NP_MORE = 1<<15, /* Bit 15: More, Next Pages to follow */
1314 PHY_NP_ACK1 = 1<<14, /* Bit 14: (ro) Ack1, for receiving a message */
1315 PHY_NP_MSG_VAL = 1<<13, /* Bit 13: Message Page valid */
1316 PHY_NP_ACK2 = 1<<12, /* Bit 12: Ack2, comply with msg content */
1317 PHY_NP_TOG = 1<<11, /* Bit 11: Toggle Bit, ensure sync */
1318 PHY_NP_MSG = 0x07ff, /* Bit 10..0: Message from/to Link Partner */
1319};
1320
1321enum {
1322 PHY_X_EX_FD = 1<<15, /* Bit 15: Device Supports Full Duplex */
1323 PHY_X_EX_HD = 1<<14, /* Bit 14: Device Supports Half Duplex */
1324};
1325
1326enum {
1327 PHY_X_RS_PAUSE = 3<<7,/* Bit 8..7: selected Pause Mode */
1328 PHY_X_RS_HD = 1<<6, /* Bit 6: Half Duplex Mode selected */
1329 PHY_X_RS_FD = 1<<5, /* Bit 5: Full Duplex Mode selected */
1330 PHY_X_RS_ABLMIS = 1<<4, /* Bit 4: duplex or pause cap mismatch */
1331 PHY_X_RS_PAUMIS = 1<<3, /* Bit 3: pause capability mismatch */
1332};
1333
1334/** Remote Fault Bits (PHY_X_AN_RFB) encoding */
1335enum {
1336 X_RFB_OK = 0<<12,/* Bit 13..12 No errors, Link OK */
1337 X_RFB_LF = 1<<12, /* Bit 13..12 Link Failure */
1338 X_RFB_OFF = 2<<12,/* Bit 13..12 Offline */
1339 X_RFB_AN_ERR = 3<<12,/* Bit 13..12 Auto-Negotiation Error */
1340};
1341
1342/* Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding */
1343enum {
1344 PHY_X_P_NO_PAUSE = 0<<7,/* Bit 8..7: no Pause Mode */
1345 PHY_X_P_SYM_MD = 1<<7, /* Bit 8..7: symmetric Pause Mode */
1346 PHY_X_P_ASYM_MD = 2<<7,/* Bit 8..7: asymmetric Pause Mode */
1347 PHY_X_P_BOTH_MD = 3<<7,/* Bit 8..7: both Pause Mode */
1348};
1349
1350
1351/* Broadcom-Specific */
1352/***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1353enum {
1354 PHY_B_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
1355 PHY_B_1000C_MSE = 1<<12, /* Bit 12: Master/Slave Enable */
1356 PHY_B_1000C_MSC = 1<<11, /* Bit 11: M/S Configuration */
1357 PHY_B_1000C_RD = 1<<10, /* Bit 10: Repeater/DTE */
1358 PHY_B_1000C_AFD = 1<<9, /* Bit 9: Advertise Full Duplex */
1359 PHY_B_1000C_AHD = 1<<8, /* Bit 8: Advertise Half Duplex */
1360};
1361
1362/***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1363/***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1364enum {
1365 PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
1366 PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
1367 PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
1368 PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
1369 PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
1370 PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
1371 /* Bit 9..8: reserved */
1372 PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
1373};
1374
1375/***** PHY_BCOM_EXT_STAT 16 bit r/o Extended Status Register *****/
1376enum {
1377 PHY_B_ES_X_FD_CAP = 1<<15, /* Bit 15: 1000Base-X FD capable */
1378 PHY_B_ES_X_HD_CAP = 1<<14, /* Bit 14: 1000Base-X HD capable */
1379 PHY_B_ES_T_FD_CAP = 1<<13, /* Bit 13: 1000Base-T FD capable */
1380 PHY_B_ES_T_HD_CAP = 1<<12, /* Bit 12: 1000Base-T HD capable */
1381};
1382
1383/***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/
1384enum {
1385 PHY_B_PEC_MAC_PHY = 1<<15, /* Bit 15: 10BIT/GMI-Interface */
1386 PHY_B_PEC_DIS_CROSS = 1<<14, /* Bit 14: Disable MDI Crossover */
1387 PHY_B_PEC_TX_DIS = 1<<13, /* Bit 13: Tx output Disabled */
1388 PHY_B_PEC_INT_DIS = 1<<12, /* Bit 12: Interrupts Disabled */
1389 PHY_B_PEC_F_INT = 1<<11, /* Bit 11: Force Interrupt */
1390 PHY_B_PEC_BY_45 = 1<<10, /* Bit 10: Bypass 4B5B-Decoder */
1391 PHY_B_PEC_BY_SCR = 1<<9, /* Bit 9: Bypass Scrambler */
1392 PHY_B_PEC_BY_MLT3 = 1<<8, /* Bit 8: Bypass MLT3 Encoder */
1393 PHY_B_PEC_BY_RXA = 1<<7, /* Bit 7: Bypass Rx Alignm. */
1394 PHY_B_PEC_RES_SCR = 1<<6, /* Bit 6: Reset Scrambler */
1395 PHY_B_PEC_EN_LTR = 1<<5, /* Bit 5: Ena LED Traffic Mode */
1396 PHY_B_PEC_LED_ON = 1<<4, /* Bit 4: Force LED's on */
1397 PHY_B_PEC_LED_OFF = 1<<3, /* Bit 3: Force LED's off */
1398 PHY_B_PEC_EX_IPG = 1<<2, /* Bit 2: Extend Tx IPG Mode */
1399 PHY_B_PEC_3_LED = 1<<1, /* Bit 1: Three Link LED mode */
1400 PHY_B_PEC_HIGH_LA = 1<<0, /* Bit 0: GMII FIFO Elasticy */
1401};
1402
1403/***** PHY_BCOM_P_EXT_STAT 16 bit r/o PHY Extended Status Reg *****/
1404enum {
1405 PHY_B_PES_CROSS_STAT = 1<<13, /* Bit 13: MDI Crossover Status */
1406 PHY_B_PES_INT_STAT = 1<<12, /* Bit 12: Interrupt Status */
1407 PHY_B_PES_RRS = 1<<11, /* Bit 11: Remote Receiver Stat. */
1408 PHY_B_PES_LRS = 1<<10, /* Bit 10: Local Receiver Stat. */
1409 PHY_B_PES_LOCKED = 1<<9, /* Bit 9: Locked */
1410 PHY_B_PES_LS = 1<<8, /* Bit 8: Link Status */
1411 PHY_B_PES_RF = 1<<7, /* Bit 7: Remote Fault */
1412 PHY_B_PES_CE_ER = 1<<6, /* Bit 6: Carrier Ext Error */
1413 PHY_B_PES_BAD_SSD = 1<<5, /* Bit 5: Bad SSD */
1414 PHY_B_PES_BAD_ESD = 1<<4, /* Bit 4: Bad ESD */
1415 PHY_B_PES_RX_ER = 1<<3, /* Bit 3: Receive Error */
1416 PHY_B_PES_TX_ER = 1<<2, /* Bit 2: Transmit Error */
1417 PHY_B_PES_LOCK_ER = 1<<1, /* Bit 1: Lock Error */
1418 PHY_B_PES_MLT3_ER = 1<<0, /* Bit 0: MLT3 code Error */
1419};
1420
1421/***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/
1422enum {
1423 PHY_B_FC_CTR = 0xff, /* Bit 7..0: False Carrier Counter */
1424
1425/***** PHY_BCOM_RNO_CTR 16 bit r/w Receive NOT_OK Counter *****/
1426 PHY_B_RC_LOC_MSK = 0xff00, /* Bit 15..8: Local Rx NOT_OK cnt */
1427 PHY_B_RC_REM_MSK = 0x00ff, /* Bit 7..0: Remote Rx NOT_OK cnt */
1428
1429/***** PHY_BCOM_AUX_CTRL 16 bit r/w Auxiliary Control Reg *****/
1430 PHY_B_AC_L_SQE = 1<<15, /* Bit 15: Low Squelch */
1431 PHY_B_AC_LONG_PACK = 1<<14, /* Bit 14: Rx Long Packets */
1432 PHY_B_AC_ER_CTRL = 3<<12,/* Bit 13..12: Edgerate Control */
1433 /* Bit 11: reserved */
1434 PHY_B_AC_TX_TST = 1<<10, /* Bit 10: Tx test bit, always 1 */
1435 /* Bit 9.. 8: reserved */
1436 PHY_B_AC_DIS_PRF = 1<<7, /* Bit 7: dis part resp filter */
1437 /* Bit 6: reserved */
1438 PHY_B_AC_DIS_PM = 1<<5, /* Bit 5: dis power management */
1439 /* Bit 4: reserved */
1440 PHY_B_AC_DIAG = 1<<3, /* Bit 3: Diagnostic Mode */
1441};
1442
1443/***** PHY_BCOM_AUX_STAT 16 bit r/o Auxiliary Status Reg *****/
1444enum {
1445 PHY_B_AS_AN_C = 1<<15, /* Bit 15: AutoNeg complete */
1446 PHY_B_AS_AN_CA = 1<<14, /* Bit 14: AN Complete Ack */
1447 PHY_B_AS_ANACK_D = 1<<13, /* Bit 13: AN Ack Detect */
1448 PHY_B_AS_ANAB_D = 1<<12, /* Bit 12: AN Ability Detect */
1449 PHY_B_AS_NPW = 1<<11, /* Bit 11: AN Next Page Wait */
1450 PHY_B_AS_AN_RES_MSK = 7<<8,/* Bit 10..8: AN HDC */
1451 PHY_B_AS_PDF = 1<<7, /* Bit 7: Parallel Detect. Fault */
1452 PHY_B_AS_RF = 1<<6, /* Bit 6: Remote Fault */
1453 PHY_B_AS_ANP_R = 1<<5, /* Bit 5: AN Page Received */
1454 PHY_B_AS_LP_ANAB = 1<<4, /* Bit 4: LP AN Ability */
1455 PHY_B_AS_LP_NPAB = 1<<3, /* Bit 3: LP Next Page Ability */
1456 PHY_B_AS_LS = 1<<2, /* Bit 2: Link Status */
1457 PHY_B_AS_PRR = 1<<1, /* Bit 1: Pause Resolution-Rx */
1458 PHY_B_AS_PRT = 1<<0, /* Bit 0: Pause Resolution-Tx */
1459};
1460#define PHY_B_AS_PAUSE_MSK (PHY_B_AS_PRR | PHY_B_AS_PRT)
1461
1462/***** PHY_BCOM_INT_STAT 16 bit r/o Interrupt Status Reg *****/
1463/***** PHY_BCOM_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
1464enum {
1465 PHY_B_IS_PSE = 1<<14, /* Bit 14: Pair Swap Error */
1466 PHY_B_IS_MDXI_SC = 1<<13, /* Bit 13: MDIX Status Change */
1467 PHY_B_IS_HCT = 1<<12, /* Bit 12: counter above 32k */
1468 PHY_B_IS_LCT = 1<<11, /* Bit 11: counter above 128 */
1469 PHY_B_IS_AN_PR = 1<<10, /* Bit 10: Page Received */
1470 PHY_B_IS_NO_HDCL = 1<<9, /* Bit 9: No HCD Link */
1471 PHY_B_IS_NO_HDC = 1<<8, /* Bit 8: No HCD */
1472 PHY_B_IS_NEG_USHDC = 1<<7, /* Bit 7: Negotiated Unsup. HCD */
1473 PHY_B_IS_SCR_S_ER = 1<<6, /* Bit 6: Scrambler Sync Error */
1474 PHY_B_IS_RRS_CHANGE = 1<<5, /* Bit 5: Remote Rx Stat Change */
1475 PHY_B_IS_LRS_CHANGE = 1<<4, /* Bit 4: Local Rx Stat Change */
1476 PHY_B_IS_DUP_CHANGE = 1<<3, /* Bit 3: Duplex Mode Change */
1477 PHY_B_IS_LSP_CHANGE = 1<<2, /* Bit 2: Link Speed Change */
1478 PHY_B_IS_LST_CHANGE = 1<<1, /* Bit 1: Link Status Changed */
1479 PHY_B_IS_CRC_ER = 1<<0, /* Bit 0: CRC Error */
1480};
1481#define PHY_B_DEF_MSK (~(PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1482
1483/* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */
1484enum {
1485 PHY_B_P_NO_PAUSE = 0<<10,/* Bit 11..10: no Pause Mode */
1486 PHY_B_P_SYM_MD = 1<<10, /* Bit 11..10: symmetric Pause Mode */
1487 PHY_B_P_ASYM_MD = 2<<10,/* Bit 11..10: asymmetric Pause Mode */
1488 PHY_B_P_BOTH_MD = 3<<10,/* Bit 11..10: both Pause Mode */
1489};
1490/*
1491 * Resolved Duplex mode and Capabilities (Aux Status Summary Reg)
1492 */
1493enum {
1494 PHY_B_RES_1000FD = 7<<8,/* Bit 10..8: 1000Base-T Full Dup. */
1495 PHY_B_RES_1000HD = 6<<8,/* Bit 10..8: 1000Base-T Half Dup. */
1496};
1497
1498/*
1499 * Level One-Specific
1500 */
1501/***** PHY_LONE_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1502enum {
1503 PHY_L_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
1504 PHY_L_1000C_MSE = 1<<12, /* Bit 12: Master/Slave Enable */
1505 PHY_L_1000C_MSC = 1<<11, /* Bit 11: M/S Configuration */
1506 PHY_L_1000C_RD = 1<<10, /* Bit 10: Repeater/DTE */
1507 PHY_L_1000C_AFD = 1<<9, /* Bit 9: Advertise Full Duplex */
1508 PHY_L_1000C_AHD = 1<<8, /* Bit 8: Advertise Half Duplex */
1509};
1510
1511/***** PHY_LONE_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1512enum {
1513 PHY_L_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
1514 PHY_L_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
1515 PHY_L_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
1516 PHY_L_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
1517 PHY_L_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
1518 PHY_L_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
1519
1520 PHY_L_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
1521
1522/***** PHY_LONE_EXT_STAT 16 bit r/o Extended Status Register *****/
1523 PHY_L_ES_X_FD_CAP = 1<<15, /* Bit 15: 1000Base-X FD capable */
1524 PHY_L_ES_X_HD_CAP = 1<<14, /* Bit 14: 1000Base-X HD capable */
1525 PHY_L_ES_T_FD_CAP = 1<<13, /* Bit 13: 1000Base-T FD capable */
1526 PHY_L_ES_T_HD_CAP = 1<<12, /* Bit 12: 1000Base-T HD capable */
1527};
1528
1529/***** PHY_LONE_PORT_CFG 16 bit r/w Port Configuration Reg *****/
1530enum {
1531 PHY_L_PC_REP_MODE = 1<<15, /* Bit 15: Repeater Mode */
1532
1533 PHY_L_PC_TX_DIS = 1<<13, /* Bit 13: Tx output Disabled */
1534 PHY_L_PC_BY_SCR = 1<<12, /* Bit 12: Bypass Scrambler */
1535 PHY_L_PC_BY_45 = 1<<11, /* Bit 11: Bypass 4B5B-Decoder */
1536 PHY_L_PC_JAB_DIS = 1<<10, /* Bit 10: Jabber Disabled */
1537 PHY_L_PC_SQE = 1<<9, /* Bit 9: Enable Heartbeat */
1538 PHY_L_PC_TP_LOOP = 1<<8, /* Bit 8: TP Loopback */
1539 PHY_L_PC_SSS = 1<<7, /* Bit 7: Smart Speed Selection */
1540 PHY_L_PC_FIFO_SIZE = 1<<6, /* Bit 6: FIFO Size */
1541 PHY_L_PC_PRE_EN = 1<<5, /* Bit 5: Preamble Enable */
1542 PHY_L_PC_CIM = 1<<4, /* Bit 4: Carrier Integrity Mon */
1543 PHY_L_PC_10_SER = 1<<3, /* Bit 3: Use Serial Output */
1544 PHY_L_PC_ANISOL = 1<<2, /* Bit 2: Unisolate Port */
1545 PHY_L_PC_TEN_BIT = 1<<1, /* Bit 1: 10bit iface mode on */
1546 PHY_L_PC_ALTCLOCK = 1<<0, /* Bit 0: (ro) ALTCLOCK Mode on */
1547};
1548
1549/***** PHY_LONE_Q_STAT 16 bit r/o Quick Status Reg *****/
1550enum {
1551 PHY_L_QS_D_RATE = 3<<14,/* Bit 15..14: Data Rate */
1552 PHY_L_QS_TX_STAT = 1<<13, /* Bit 13: Transmitting */
1553 PHY_L_QS_RX_STAT = 1<<12, /* Bit 12: Receiving */
1554 PHY_L_QS_COL_STAT = 1<<11, /* Bit 11: Collision */
1555 PHY_L_QS_L_STAT = 1<<10, /* Bit 10: Link is up */
1556 PHY_L_QS_DUP_MOD = 1<<9, /* Bit 9: Full/Half Duplex */
1557 PHY_L_QS_AN = 1<<8, /* Bit 8: AutoNeg is On */
1558 PHY_L_QS_AN_C = 1<<7, /* Bit 7: AN is Complete */
1559 PHY_L_QS_LLE = 7<<4,/* Bit 6..4: Line Length Estim. */
1560 PHY_L_QS_PAUSE = 1<<3, /* Bit 3: LP advertised Pause */
1561 PHY_L_QS_AS_PAUSE = 1<<2, /* Bit 2: LP adv. asym. Pause */
1562 PHY_L_QS_ISOLATE = 1<<1, /* Bit 1: CIM Isolated */
1563 PHY_L_QS_EVENT = 1<<0, /* Bit 0: Event has occurred */
1564};
1565
1566/***** PHY_LONE_INT_ENAB 16 bit r/w Interrupt Enable Reg *****/
1567/***** PHY_LONE_INT_STAT 16 bit r/o Interrupt Status Reg *****/
1568enum {
1569 PHY_L_IS_AN_F = 1<<13, /* Bit 13: Auto-Negotiation fault */
1570 PHY_L_IS_CROSS = 1<<11, /* Bit 11: Crossover used */
1571 PHY_L_IS_POL = 1<<10, /* Bit 10: Polarity correct. used */
1572 PHY_L_IS_SS = 1<<9, /* Bit 9: Smart Speed Downgrade */
1573 PHY_L_IS_CFULL = 1<<8, /* Bit 8: Counter Full */
1574 PHY_L_IS_AN_C = 1<<7, /* Bit 7: AutoNeg Complete */
1575 PHY_L_IS_SPEED = 1<<6, /* Bit 6: Speed Changed */
1576 PHY_L_IS_DUP = 1<<5, /* Bit 5: Duplex Changed */
1577 PHY_L_IS_LS = 1<<4, /* Bit 4: Link Status Changed */
1578 PHY_L_IS_ISOL = 1<<3, /* Bit 3: Isolate Occured */
1579 PHY_L_IS_MDINT = 1<<2, /* Bit 2: (ro) STAT: MII Int Pending */
1580 PHY_L_IS_INTEN = 1<<1, /* Bit 1: ENAB: Enable IRQs */
1581 PHY_L_IS_FORCE = 1<<0, /* Bit 0: ENAB: Force Interrupt */
1582};
1583
1584/* int. mask */
1585#define PHY_L_DEF_MSK (PHY_L_IS_LS | PHY_L_IS_ISOL | PHY_L_IS_INTEN)
1586
1587/***** PHY_LONE_LED_CFG 16 bit r/w LED Configuration Reg *****/
1588enum {
1589 PHY_L_LC_LEDC = 3<<14,/* Bit 15..14: Col/Blink/On/Off */
1590 PHY_L_LC_LEDR = 3<<12,/* Bit 13..12: Rx/Blink/On/Off */
1591 PHY_L_LC_LEDT = 3<<10,/* Bit 11..10: Tx/Blink/On/Off */
1592 PHY_L_LC_LEDG = 3<<8,/* Bit 9..8: Giga/Blink/On/Off */
1593 PHY_L_LC_LEDS = 3<<6,/* Bit 7..6: 10-100/Blink/On/Off */
1594 PHY_L_LC_LEDL = 3<<4,/* Bit 5..4: Link/Blink/On/Off */
1595 PHY_L_LC_LEDF = 3<<2,/* Bit 3..2: Duplex/Blink/On/Off */
1596 PHY_L_LC_PSTRECH= 1<<1, /* Bit 1: Strech LED Pulses */
1597 PHY_L_LC_FREQ = 1<<0, /* Bit 0: 30/100 ms */
1598};
1599
1600/***** PHY_LONE_PORT_CTRL 16 bit r/w Port Control Reg *****/
1601enum {
1602 PHY_L_PC_TX_TCLK = 1<<15, /* Bit 15: Enable TX_TCLK */
1603 PHY_L_PC_ALT_NP = 1<<13, /* Bit 14: Alternate Next Page */
1604 PHY_L_PC_GMII_ALT= 1<<12, /* Bit 13: Alternate GMII driver */
1605 PHY_L_PC_TEN_CRS = 1<<10, /* Bit 10: Extend CRS*/
1606};
1607
1608/***** PHY_LONE_CIM 16 bit r/o CIM Reg *****/
1609enum {
1610 PHY_L_CIM_ISOL = 0xff<<8,/* Bit 15..8: Isolate Count */
1611 PHY_L_CIM_FALSE_CAR = 0xff, /* Bit 7..0: False Carrier Count */
1612};
1613
1614/*
1615 * Pause Bits (PHY_L_AN_ASP and PHY_L_AN_PC) encoding
1616 */
1617enum {
1618 PHY_L_P_NO_PAUSE= 0<<10,/* Bit 11..10: no Pause Mode */
1619 PHY_L_P_SYM_MD = 1<<10, /* Bit 11..10: symmetric Pause Mode */
1620 PHY_L_P_ASYM_MD = 2<<10,/* Bit 11..10: asymmetric Pause Mode */
1621 PHY_L_P_BOTH_MD = 3<<10,/* Bit 11..10: both Pause Mode */
1622};
1623
1624/*
1625 * National-Specific
1626 */
1627/***** PHY_NAT_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1628enum {
1629 PHY_N_1000C_TEST= 7<<13,/* Bit 15..13: Test Modes */
1630 PHY_N_1000C_MSE = 1<<12, /* Bit 12: Master/Slave Enable */
1631 PHY_N_1000C_MSC = 1<<11, /* Bit 11: M/S Configuration */
1632 PHY_N_1000C_RD = 1<<10, /* Bit 10: Repeater/DTE */
1633 PHY_N_1000C_AFD = 1<<9, /* Bit 9: Advertise Full Duplex */
1634 PHY_N_1000C_AHD = 1<<8, /* Bit 8: Advertise Half Duplex */
1635 PHY_N_1000C_APC = 1<<7, /* Bit 7: Asymmetric Pause Cap. */};
1636
1637
1638/***** PHY_NAT_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1639enum {
1640 PHY_N_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
1641 PHY_N_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
1642 PHY_N_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
1643 PHY_N_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status*/
1644 PHY_N_1000S_LP_FD= 1<<11, /* Bit 11: Link Partner can FD */
1645 PHY_N_1000S_LP_HD= 1<<10, /* Bit 10: Link Partner can HD */
1646 PHY_N_1000C_LP_APC= 1<<9, /* Bit 9: LP Asym. Pause Cap. */
1647 PHY_N_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
1648};
1649
1650/***** PHY_NAT_EXT_STAT 16 bit r/o Extended Status Register *****/
1651enum {
1652 PHY_N_ES_X_FD_CAP= 1<<15, /* Bit 15: 1000Base-X FD capable */
1653 PHY_N_ES_X_HD_CAP= 1<<14, /* Bit 14: 1000Base-X HD capable */
1654 PHY_N_ES_T_FD_CAP= 1<<13, /* Bit 13: 1000Base-T FD capable */
1655 PHY_N_ES_T_HD_CAP= 1<<12, /* Bit 12: 1000Base-T HD capable */
1656};
1657
1658/** Marvell-Specific */
1659enum {
1660 PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
1661 PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
1662 PHY_M_AN_RF = 1<<13, /* Remote Fault */
1663
1664 PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
1665 PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
1666 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1667 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1668 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1669 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1670 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1671 PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
1672};
1673
1674/* special defines for FIBER (88E1011S only) */
1675enum {
1676 PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
1677 PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
1678 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1679 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1680};
1681
1682/* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
1683enum {
1684 PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
1685 PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
1686 PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
1687 PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
1688};
1689
1690/***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1691enum {
1692 PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
1693 PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
1694 PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
1695 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1696 PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
1697 PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
1698};
1699
1700/***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1701enum {
1702 PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
1703 PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
1704 PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
1705 PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
1706 PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
1707 PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
1708 PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
1709 PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
1710 PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
1711 PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
1712 PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
1713 PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
1714};
1715
1716enum {
1717 PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
1718 PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
1719};
1720
1721#define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK)
1722
1723enum {
1724 PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
1725 PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
1726 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
1727};
1728
1729/* for 10/100 Fast Ethernet PHY (88E3082 only) */
1730enum {
1731 PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
1732 PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
1733 PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
1734 PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
1735 PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
1736
1737 PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
1738 PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
1739
1740 PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
1741 PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
1742};
1743
1744/***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1745enum {
1746 PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
1747 PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
1748 PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
1749 PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
1750 PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
1751 PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
1752 PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
1753 PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
1754 PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
1755 PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
1756 PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
1757 PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
1758 PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
1759 PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
1760 PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
1761 PHY_M_PS_JABBER = 1<<0, /* Jabber */
1762};
1763
1764#define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1765
1766/* for 10/100 Fast Ethernet PHY (88E3082 only) */
1767enum {
1768 PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
1769 PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
1770};
1771
1772enum {
1773 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1774 PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
1775 PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
1776 PHY_M_IS_AN_PR = 1<<12, /* Page Received */
1777 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1778 PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
1779 PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
1780 PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
1781 PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
1782 PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
1783 PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
1784 PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
1785
1786 PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
1787 PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
1788 PHY_M_IS_JABBER = 1<<0, /* Jabber */
1789};
1790
1791#define PHY_M_DEF_MSK ( PHY_M_IS_AN_ERROR | PHY_M_IS_LSP_CHANGE | \
1792 PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR)
1793
1794/***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1795enum {
1796 PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
1797 PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
1798
1799 PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
1800 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
1801 /* (88E1011 only) */
1802 PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */
1803 /* (88E1011 only) */
1804 PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */
1805 /* (88E1111 only) */
1806 PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
1807 /* !!! Errata in spec. (1 = disable) */
1808 PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
1809 PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */
1810 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1811 PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
1812 PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
1813 PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
1814
1815#define PHY_M_EC_M_DSC(x) ((x)<<10) /* 00=1x; 01=2x; 10=3x; 11=4x */
1816#define PHY_M_EC_S_DSC(x) ((x)<<8) /* 00=dis; 01=1x; 10=2x; 11=3x */
1817#define PHY_M_EC_MAC_S(x) ((x)<<4) /* 01X=0; 110=2.5; 111=25 (MHz) */
1818
1819#define PHY_M_EC_M_DSC_2(x) ((x)<<9) /* 000=1x; 001=2x; 010=3x; 011=4x */
1820 /* 100=5x; 101=6x; 110=7x; 111=8x */
1821enum {
1822 MAC_TX_CLK_0_MHZ = 2,
1823 MAC_TX_CLK_2_5_MHZ = 6,
1824 MAC_TX_CLK_25_MHZ = 7,
1825};
1826
1827/***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1828enum {
1829 PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
1830 PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
1831 PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
1832 PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
1833 PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
1834 PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
1835 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
1836 /* (88E1111 only) */
1837};
1838
1839enum {
1840 PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */
1841 /* (88E1011 only) */
1842 PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
1843 PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
1844 PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
1845 PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
1846 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
1847};
1848
1849#define PHY_M_LED_PULS_DUR(x) ( ((x)<<12) & PHY_M_LEDC_PULS_MSK)
1850
1851enum {
1852 PULS_NO_STR = 0,/* no pulse stretching */
1853 PULS_21MS = 1,/* 21 ms to 42 ms */
1854 PULS_42MS = 2,/* 42 ms to 84 ms */
1855 PULS_84MS = 3,/* 84 ms to 170 ms */
1856 PULS_170MS = 4,/* 170 ms to 340 ms */
1857 PULS_340MS = 5,/* 340 ms to 670 ms */
1858 PULS_670MS = 6,/* 670 ms to 1.3 s */
1859 PULS_1300MS = 7,/* 1.3 s to 2.7 s */
1860};
1861
1862#define PHY_M_LED_BLINK_RT(x) ( ((x)<<8) & PHY_M_LEDC_BL_R_MSK)
1863
1864enum {
1865 BLINK_42MS = 0,/* 42 ms */
1866 BLINK_84MS = 1,/* 84 ms */
1867 BLINK_170MS = 2,/* 170 ms */
1868 BLINK_340MS = 3,/* 340 ms */
1869 BLINK_670MS = 4,/* 670 ms */
1870};
1871
1872/***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1873#define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */
1874 /* Bit 13..12: reserved */
1875#define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
1876#define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */
1877#define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */
1878#define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
1879#define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
1880#define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
1881
1882enum {
1883 MO_LED_NORM = 0,
1884 MO_LED_BLINK = 1,
1885 MO_LED_OFF = 2,
1886 MO_LED_ON = 3,
1887};
1888
1889/***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1890enum {
1891 PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */
1892 PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
1893 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
1894 PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
1895 PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */
1896};
1897
1898/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1899enum {
1900 PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
1901 PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */
1902 PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */
1903 PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
1904 PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
1905 PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */
1906 PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
1907 /* (88E1111 only) */
1908 /* Bit 9.. 4: reserved (88E1011 only) */
1909 PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
1910 PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
1911 PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
1912};
1913
1914/***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/
1915enum {
1916 PHY_M_CABD_ENA_TEST = 1<<15, /* Enable Test (Page 0) */
1917 PHY_M_CABD_DIS_WAIT = 1<<15, /* Disable Waiting Period (Page 1) */
1918 /* (88E1111 only) */
1919 PHY_M_CABD_STAT_MSK = 3<<13, /* Bit 14..13: Status Mask */
1920 PHY_M_CABD_AMPL_MSK = 0x1f<<8,/* Bit 12.. 8: Amplitude Mask */
1921 /* (88E1111 only) */
1922 PHY_M_CABD_DIST_MSK = 0xff, /* Bit 7.. 0: Distance Mask */
1923};
1924
1925/* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */
1926enum {
1927 CABD_STAT_NORMAL= 0,
1928 CABD_STAT_SHORT = 1,
1929 CABD_STAT_OPEN = 2,
1930 CABD_STAT_FAIL = 3,
1931};
1932
1933/* for 10/100 Fast Ethernet PHY (88E3082 only) */
1934/***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1935 /* Bit 15..12: reserved (used internally) */
1936enum {
1937 PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
1938 PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
1939 PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
1940};
1941
1942#define PHY_M_FELP_LED2_CTRL(x) ( ((x)<<8) & PHY_M_FELP_LED2_MSK)
1943#define PHY_M_FELP_LED1_CTRL(x) ( ((x)<<4) & PHY_M_FELP_LED1_MSK)
1944#define PHY_M_FELP_LED0_CTRL(x) ( ((x)<<0) & PHY_M_FELP_LED0_MSK)
1945
1946enum {
1947 LED_PAR_CTRL_COLX = 0x00,
1948 LED_PAR_CTRL_ERROR = 0x01,
1949 LED_PAR_CTRL_DUPLEX = 0x02,
1950 LED_PAR_CTRL_DP_COL = 0x03,
1951 LED_PAR_CTRL_SPEED = 0x04,
1952 LED_PAR_CTRL_LINK = 0x05,
1953 LED_PAR_CTRL_TX = 0x06,
1954 LED_PAR_CTRL_RX = 0x07,
1955 LED_PAR_CTRL_ACT = 0x08,
1956 LED_PAR_CTRL_LNK_RX = 0x09,
1957 LED_PAR_CTRL_LNK_AC = 0x0a,
1958 LED_PAR_CTRL_ACT_BL = 0x0b,
1959 LED_PAR_CTRL_TX_BL = 0x0c,
1960 LED_PAR_CTRL_RX_BL = 0x0d,
1961 LED_PAR_CTRL_COL_BL = 0x0e,
1962 LED_PAR_CTRL_INACT = 0x0f
1963};
1964
1965/*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1966enum {
1967 PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
1968 PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
1969 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1970};
1971
1972/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1973/***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
1974enum {
1975 PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
1976 PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
1977 PHY_M_MAC_MD_COPPER = 5,/* Copper only */
1978 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
1979};
1980#define PHY_M_MAC_MODE_SEL(x) ( ((x)<<7) & PHY_M_MAC_MD_MSK)
1981
1982/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1983enum {
1984 PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
1985 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1986 PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1987 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1988};
1989
1990#define PHY_M_LEDC_LOS_CTRL(x) ( ((x)<<12) & PHY_M_LEDC_LOS_MSK)
1991#define PHY_M_LEDC_INIT_CTRL(x) ( ((x)<<8) & PHY_M_LEDC_INIT_MSK)
1992#define PHY_M_LEDC_STA1_CTRL(x) ( ((x)<<4) & PHY_M_LEDC_STA1_MSK)
1993#define PHY_M_LEDC_STA0_CTRL(x) ( ((x)<<0) & PHY_M_LEDC_STA0_MSK)
1994
1995/* GMAC registers */
1996/* Port Registers */
1997enum {
1998 GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
1999 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
2000 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
2001 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
2002 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
2003 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
2004 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
2005/* Source Address Registers */
2006 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
2007 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
2008 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
2009 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
2010 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
2011 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
2012
2013/* Multicast Address Hash Registers */
2014 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
2015 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
2016 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
2017 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
2018
2019/* Interrupt Source Registers */
2020 GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
2021 GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
2022 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
2023
2024/* Interrupt Mask Registers */
2025 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
2026 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
2027 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
2028
2029/* Serial Management Interface (SMI) Registers */
2030 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
2031 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
2032 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
2033};
2034
2035/* MIB Counters */
2036#define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */
2037#define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */
2038
2039/*
2040 * MIB Counters base address definitions (low word) -
2041 * use offset 4 for access to high word (32 bit r/o)
2042 */
2043enum {
2044 GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
2045 GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
2046 GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
2047 GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
2048 GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
2049 /* GM_MIB_CNT_BASE + 40: reserved */
2050 GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
2051 GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
2052 GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
2053 GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
2054 GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
2055 GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
2056 GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
2057 GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */
2058 GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */
2059 GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */
2060 GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */
2061 GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */
2062 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */
2063 GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152, /* Rx Frame too Long Error */
2064 GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160, /* Rx Jabber Packet Frame */
2065 /* GM_MIB_CNT_BASE + 168: reserved */
2066 GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176, /* Rx FIFO overflow Event */
2067 /* GM_MIB_CNT_BASE + 184: reserved */
2068 GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192, /* Unicast Frames Xmitted OK */
2069 GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200, /* Broadcast Frames Xmitted OK */
2070 GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208, /* Pause MAC Ctrl Frames Xmitted */
2071 GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216, /* Multicast Frames Xmitted OK */
2072 GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224, /* Octets Transmitted OK Low */
2073 GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232, /* Octets Transmitted OK High */
2074 GM_TXF_64B = GM_MIB_CNT_BASE + 240, /* 64 Byte Tx Frame */
2075 GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */
2076 GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */
2077 GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */
2078 GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */
2079 GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */
2080 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */
2081
2082 GM_TXF_COL = GM_MIB_CNT_BASE + 304, /* Tx Collision */
2083 GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312, /* Tx Late Collision */
2084 GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320, /* Tx aborted due to Exces. Col. */
2085 GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328, /* Tx Multiple Collision */
2086 GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336, /* Tx Single Collision */
2087 GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344, /* Tx FIFO Underrun Event */
2088};
2089
2090/* GMAC Bit Definitions */
2091/* GM_GP_STAT 16 bit r/o General Purpose Status Register */
2092enum {
2093 GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
2094 GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
2095 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
2096 GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
2097 GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
2098 GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
2099 GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */
2100 GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */
2101
2102 GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
2103 GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
2104 GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
2105 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
2106 GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
2107};
2108
2109/* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
2110enum {
2111 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
2112 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
2113 GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
2114 GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
2115 GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
2116 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
2117 GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
2118 GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
2119 GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
2120 GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
2121 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
2122 GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
2123 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
2124 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
2125 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
2126};
2127
2128#define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
2129#define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
2130
2131/* GM_TX_CTRL 16 bit r/w Transmit Control Register */
2132enum {
2133 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
2134 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
2135 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
2136 GM_TXCR_COL_THR_MSK = 1<<10, /* Bit 12..10: Collision Threshold */
2137};
2138
2139#define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
2140#define TX_COL_DEF 0x04
2141
2142/* GM_RX_CTRL 16 bit r/w Receive Control Register */
2143enum {
2144 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
2145 GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
2146 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
2147 GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
2148};
2149
2150/* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
2151enum {
2152 GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
2153 GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
2154 GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
2155
2156 TX_JAM_LEN_DEF = 0x03,
2157 TX_JAM_IPG_DEF = 0x0b,
2158 TX_IPG_JAM_DEF = 0x1c,
2159};
2160
2161#define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
2162#define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
2163#define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
2164
2165
2166/* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
2167enum {
2168 GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
2169 GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
2170 GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
2171 GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
2172 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
2173};
2174
2175#define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
2176#define DATA_BLIND_DEF 0x04
2177
2178#define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
2179#define IPG_DATA_DEF 0x1e
2180
2181/* GM_SMI_CTRL 16 bit r/w SMI Control Register */
2182enum {
2183 GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */
2184 GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */
2185 GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
2186 GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
2187 GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
2188};
2189
2190#define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
2191#define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK)
2192
2193/* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
2194enum {
2195 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
2196 GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
2197};
2198
2199/* Receive Frame Status Encoding */
2200enum {
2201 GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
2202 GMR_FS_VLAN = 1<<13, /* Bit 13: VLAN Packet */
2203 GMR_FS_JABBER = 1<<12, /* Bit 12: Jabber Packet */
2204 GMR_FS_UN_SIZE = 1<<11, /* Bit 11: Undersize Packet */
2205 GMR_FS_MC = 1<<10, /* Bit 10: Multicast Packet */
2206 GMR_FS_BC = 1<<9, /* Bit 9: Broadcast Packet */
2207 GMR_FS_RX_OK = 1<<8, /* Bit 8: Receive OK (Good Packet) */
2208 GMR_FS_GOOD_FC = 1<<7, /* Bit 7: Good Flow-Control Packet */
2209 GMR_FS_BAD_FC = 1<<6, /* Bit 6: Bad Flow-Control Packet */
2210 GMR_FS_MII_ERR = 1<<5, /* Bit 5: MII Error */
2211 GMR_FS_LONG_ERR = 1<<4, /* Bit 4: Too Long Packet */
2212 GMR_FS_FRAGMENT = 1<<3, /* Bit 3: Fragment */
2213
2214 GMR_FS_CRC_ERR = 1<<1, /* Bit 1: CRC Error */
2215 GMR_FS_RX_FF_OV = 1<<0, /* Bit 0: Rx FIFO Overflow */
2216
2217/*
2218 * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
2219 */
2220 GMR_FS_ANY_ERR = GMR_FS_CRC_ERR | GMR_FS_LONG_ERR |
2221 GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
2222 GMR_FS_JABBER,
2223/* Rx GMAC FIFO Flush Mask (default) */
2224 RX_FF_FL_DEF_MSK = GMR_FS_CRC_ERR | GMR_FS_RX_FF_OV |GMR_FS_MII_ERR |
2225 GMR_FS_BAD_FC | GMR_FS_GOOD_FC | GMR_FS_UN_SIZE |
2226 GMR_FS_JABBER,
2227};
2228
2229/* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
2230enum {
2231 GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
2232 GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
2233 GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
2234
2235 GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
2236 GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */
2237 GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */
2238 GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
2239 GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
2240 GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
2241 GMF_CLI_RX_FC = 1<<4, /* Clear IRQ Rx Frame Complete */
2242 GMF_OPER_ON = 1<<3, /* Operational Mode On */
2243 GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
2244 GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
2245 GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
2246
2247 RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
2248};
2249
2250
2251/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
2252enum {
2253 GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */
2254 GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */
2255 GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */
2256
2257 GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
2258 GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
2259 GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
2260};
2261
2262/* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
2263enum {
2264 GMT_ST_START = 1<<2, /* Start Time Stamp Timer */
2265 GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */
2266 GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */
2267};
2268
2269/* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
2270enum {
2271 GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
2272 GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
2273 GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
2274 GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
2275 GMC_PAUSE_ON = 1<<3, /* Pause On */
2276 GMC_PAUSE_OFF = 1<<2, /* Pause Off */
2277 GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
2278 GMC_RST_SET = 1<<0, /* Set GMAC Reset */
2279};
2280
2281/* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
2282enum {
2283 GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
2284 GPC_INT_POL_HI = 1<<27, /* IRQ Polarity is Active HIGH */
2285 GPC_75_OHM = 1<<26, /* Use 75 Ohm Termination instead of 50 */
2286 GPC_DIS_FC = 1<<25, /* Disable Automatic Fiber/Copper Detection */
2287 GPC_DIS_SLEEP = 1<<24, /* Disable Energy Detect */
2288 GPC_HWCFG_M_3 = 1<<23, /* HWCFG_MODE[3] */
2289 GPC_HWCFG_M_2 = 1<<22, /* HWCFG_MODE[2] */
2290 GPC_HWCFG_M_1 = 1<<21, /* HWCFG_MODE[1] */
2291 GPC_HWCFG_M_0 = 1<<20, /* HWCFG_MODE[0] */
2292 GPC_ANEG_0 = 1<<19, /* ANEG[0] */
2293 GPC_ENA_XC = 1<<18, /* Enable MDI crossover */
2294 GPC_DIS_125 = 1<<17, /* Disable 125 MHz clock */
2295 GPC_ANEG_3 = 1<<16, /* ANEG[3] */
2296 GPC_ANEG_2 = 1<<15, /* ANEG[2] */
2297 GPC_ANEG_1 = 1<<14, /* ANEG[1] */
2298 GPC_ENA_PAUSE = 1<<13, /* Enable Pause (SYM_OR_REM) */
2299 GPC_PHYADDR_4 = 1<<12, /* Bit 4 of Phy Addr */
2300 GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */
2301 GPC_PHYADDR_2 = 1<<10, /* Bit 2 of Phy Addr */
2302 GPC_PHYADDR_1 = 1<<9, /* Bit 1 of Phy Addr */
2303 GPC_PHYADDR_0 = 1<<8, /* Bit 0 of Phy Addr */
2304 /* Bits 7..2: reserved */
2305 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
2306 GPC_RST_SET = 1<<0, /* Set GPHY Reset */
2307};
2308
2309#define GPC_HWCFG_GMII_COP (GPC_HWCFG_M_3|GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
2310#define GPC_HWCFG_GMII_FIB (GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
2311#define GPC_ANEG_ADV_ALL_M (GPC_ANEG_3 | GPC_ANEG_2 | GPC_ANEG_1 | GPC_ANEG_0)
2312
2313/* forced speed and duplex mode (don't mix with other ANEG bits) */
2314#define GPC_FRC10MBIT_HALF 0
2315#define GPC_FRC10MBIT_FULL GPC_ANEG_0
2316#define GPC_FRC100MBIT_HALF GPC_ANEG_1
2317#define GPC_FRC100MBIT_FULL (GPC_ANEG_0 | GPC_ANEG_1)
2318
2319/* auto-negotiation with limited advertised speeds */
2320/* mix only with master/slave settings (for copper) */
2321#define GPC_ADV_1000_HALF GPC_ANEG_2
2322#define GPC_ADV_1000_FULL GPC_ANEG_3
2323#define GPC_ADV_ALL (GPC_ANEG_2 | GPC_ANEG_3)
2324
2325/* master/slave settings */
2326/* only for copper with 1000 Mbps */
2327#define GPC_FORCE_MASTER 0
2328#define GPC_FORCE_SLAVE GPC_ANEG_0
2329#define GPC_PREF_MASTER GPC_ANEG_1
2330#define GPC_PREF_SLAVE (GPC_ANEG_1 | GPC_ANEG_0)
2331
2332/* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
2333/* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
2334enum {
2335 GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */
2336 GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */
2337 GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */
2338 GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */
2339 GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
2340 GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
2341
2342#define GMAC_DEF_MSK (GM_IS_TX_CO_OV | GM_IS_RX_CO_OV | GM_IS_TX_FF_UR)
2343
2344/* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
2345 /* Bits 15.. 2: reserved */
2346 GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
2347 GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
2348
2349
2350/* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
2351 WOL_CTL_LINK_CHG_OCC = 1<<15,
2352 WOL_CTL_MAGIC_PKT_OCC = 1<<14,
2353 WOL_CTL_PATTERN_OCC = 1<<13,
2354 WOL_CTL_CLEAR_RESULT = 1<<12,
2355 WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
2356 WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10,
2357 WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9,
2358 WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
2359 WOL_CTL_ENA_PME_ON_PATTERN = 1<<7,
2360 WOL_CTL_DIS_PME_ON_PATTERN = 1<<6,
2361 WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
2362 WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
2363 WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3,
2364 WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2,
2365 WOL_CTL_ENA_PATTERN_UNIT = 1<<1,
2366 WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
2367};
2368
2369#define WOL_CTL_DEFAULT \
2370 (WOL_CTL_DIS_PME_ON_LINK_CHG | \
2371 WOL_CTL_DIS_PME_ON_PATTERN | \
2372 WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
2373 WOL_CTL_DIS_LINK_CHG_UNIT | \
2374 WOL_CTL_DIS_PATTERN_UNIT | \
2375 WOL_CTL_DIS_MAGIC_PKT_UNIT)
2376
2377/* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
2378#define WOL_CTL_PATT_ENA(x) (1 << (x))
2379
2380
2381/* XMAC II registers */
2382enum {
2383 XM_MMU_CMD = 0x0000, /* 16 bit r/w MMU Command Register */
2384 XM_POFF = 0x0008, /* 32 bit r/w Packet Offset Register */
2385 XM_BURST = 0x000c, /* 32 bit r/w Burst Register for half duplex*/
2386 XM_1L_VLAN_TAG = 0x0010, /* 16 bit r/w One Level VLAN Tag ID */
2387 XM_2L_VLAN_TAG = 0x0014, /* 16 bit r/w Two Level VLAN Tag ID */
2388 XM_TX_CMD = 0x0020, /* 16 bit r/w Transmit Command Register */
2389 XM_TX_RT_LIM = 0x0024, /* 16 bit r/w Transmit Retry Limit Register */
2390 XM_TX_STIME = 0x0028, /* 16 bit r/w Transmit Slottime Register */
2391 XM_TX_IPG = 0x002c, /* 16 bit r/w Transmit Inter Packet Gap */
2392 XM_RX_CMD = 0x0030, /* 16 bit r/w Receive Command Register */
2393 XM_PHY_ADDR = 0x0034, /* 16 bit r/w PHY Address Register */
2394 XM_PHY_DATA = 0x0038, /* 16 bit r/w PHY Data Register */
2395 XM_GP_PORT = 0x0040, /* 32 bit r/w General Purpose Port Register */
2396 XM_IMSK = 0x0044, /* 16 bit r/w Interrupt Mask Register */
2397 XM_ISRC = 0x0048, /* 16 bit r/o Interrupt Status Register */
2398 XM_HW_CFG = 0x004c, /* 16 bit r/w Hardware Config Register */
2399 XM_TX_LO_WM = 0x0060, /* 16 bit r/w Tx FIFO Low Water Mark */
2400 XM_TX_HI_WM = 0x0062, /* 16 bit r/w Tx FIFO High Water Mark */
2401 XM_TX_THR = 0x0064, /* 16 bit r/w Tx Request Threshold */
2402 XM_HT_THR = 0x0066, /* 16 bit r/w Host Request Threshold */
2403 XM_PAUSE_DA = 0x0068, /* NA reg r/w Pause Destination Address */
2404 XM_CTL_PARA = 0x0070, /* 32 bit r/w Control Parameter Register */
2405 XM_MAC_OPCODE = 0x0074, /* 16 bit r/w Opcode for MAC control frames */
2406 XM_MAC_PTIME = 0x0076, /* 16 bit r/w Pause time for MAC ctrl frames*/
2407 XM_TX_STAT = 0x0078, /* 32 bit r/o Tx Status LIFO Register */
2408
2409 XM_EXM_START = 0x0080, /* r/w Start Address of the EXM Regs */
2410#define XM_EXM(reg) (XM_EXM_START + ((reg) << 3))
2411};
2412
2413enum {
2414 XM_SRC_CHK = 0x0100, /* NA reg r/w Source Check Address Register */
2415 XM_SA = 0x0108, /* NA reg r/w Station Address Register */
2416 XM_HSM = 0x0110, /* 64 bit r/w Hash Match Address Registers */
2417 XM_RX_LO_WM = 0x0118, /* 16 bit r/w Receive Low Water Mark */
2418 XM_RX_HI_WM = 0x011a, /* 16 bit r/w Receive High Water Mark */
2419 XM_RX_THR = 0x011c, /* 32 bit r/w Receive Request Threshold */
2420 XM_DEV_ID = 0x0120, /* 32 bit r/o Device ID Register */
2421 XM_MODE = 0x0124, /* 32 bit r/w Mode Register */
2422 XM_LSA = 0x0128, /* NA reg r/o Last Source Register */
2423 XM_TS_READ = 0x0130, /* 32 bit r/o Time Stamp Read Register */
2424 XM_TS_LOAD = 0x0134, /* 32 bit r/o Time Stamp Load Value */
2425 XM_STAT_CMD = 0x0200, /* 16 bit r/w Statistics Command Register */
2426 XM_RX_CNT_EV = 0x0204, /* 32 bit r/o Rx Counter Event Register */
2427 XM_TX_CNT_EV = 0x0208, /* 32 bit r/o Tx Counter Event Register */
2428 XM_RX_EV_MSK = 0x020c, /* 32 bit r/w Rx Counter Event Mask */
2429 XM_TX_EV_MSK = 0x0210, /* 32 bit r/w Tx Counter Event Mask */
2430 XM_TXF_OK = 0x0280, /* 32 bit r/o Frames Transmitted OK Conuter */
2431 XM_TXO_OK_HI = 0x0284, /* 32 bit r/o Octets Transmitted OK High Cnt*/
2432 XM_TXO_OK_LO = 0x0288, /* 32 bit r/o Octets Transmitted OK Low Cnt */
2433 XM_TXF_BC_OK = 0x028c, /* 32 bit r/o Broadcast Frames Xmitted OK */
2434 XM_TXF_MC_OK = 0x0290, /* 32 bit r/o Multicast Frames Xmitted OK */
2435 XM_TXF_UC_OK = 0x0294, /* 32 bit r/o Unicast Frames Xmitted OK */
2436 XM_TXF_LONG = 0x0298, /* 32 bit r/o Tx Long Frame Counter */
2437 XM_TXE_BURST = 0x029c, /* 32 bit r/o Tx Burst Event Counter */
2438 XM_TXF_MPAUSE = 0x02a0, /* 32 bit r/o Tx Pause MAC Ctrl Frame Cnt */
2439 XM_TXF_MCTRL = 0x02a4, /* 32 bit r/o Tx MAC Ctrl Frame Counter */
2440 XM_TXF_SNG_COL = 0x02a8, /* 32 bit r/o Tx Single Collision Counter */
2441 XM_TXF_MUL_COL = 0x02ac, /* 32 bit r/o Tx Multiple Collision Counter */
2442 XM_TXF_ABO_COL = 0x02b0, /* 32 bit r/o Tx aborted due to Exces. Col. */
2443 XM_TXF_LAT_COL = 0x02b4, /* 32 bit r/o Tx Late Collision Counter */
2444 XM_TXF_DEF = 0x02b8, /* 32 bit r/o Tx Deferred Frame Counter */
2445 XM_TXF_EX_DEF = 0x02bc, /* 32 bit r/o Tx Excessive Deferall Counter */
2446 XM_TXE_FIFO_UR = 0x02c0, /* 32 bit r/o Tx FIFO Underrun Event Cnt */
2447 XM_TXE_CS_ERR = 0x02c4, /* 32 bit r/o Tx Carrier Sense Error Cnt */
2448 XM_TXP_UTIL = 0x02c8, /* 32 bit r/o Tx Utilization in % */
2449 XM_TXF_64B = 0x02d0, /* 32 bit r/o 64 Byte Tx Frame Counter */
2450 XM_TXF_127B = 0x02d4, /* 32 bit r/o 65-127 Byte Tx Frame Counter */
2451 XM_TXF_255B = 0x02d8, /* 32 bit r/o 128-255 Byte Tx Frame Counter */
2452 XM_TXF_511B = 0x02dc, /* 32 bit r/o 256-511 Byte Tx Frame Counter */
2453 XM_TXF_1023B = 0x02e0, /* 32 bit r/o 512-1023 Byte Tx Frame Counter*/
2454 XM_TXF_MAX_SZ = 0x02e4, /* 32 bit r/o 1024-MaxSize Byte Tx Frame Cnt*/
2455 XM_RXF_OK = 0x0300, /* 32 bit r/o Frames Received OK */
2456 XM_RXO_OK_HI = 0x0304, /* 32 bit r/o Octets Received OK High Cnt */
2457 XM_RXO_OK_LO = 0x0308, /* 32 bit r/o Octets Received OK Low Counter*/
2458 XM_RXF_BC_OK = 0x030c, /* 32 bit r/o Broadcast Frames Received OK */
2459 XM_RXF_MC_OK = 0x0310, /* 32 bit r/o Multicast Frames Received OK */
2460 XM_RXF_UC_OK = 0x0314, /* 32 bit r/o Unicast Frames Received OK */
2461 XM_RXF_MPAUSE = 0x0318, /* 32 bit r/o Rx Pause MAC Ctrl Frame Cnt */
2462 XM_RXF_MCTRL = 0x031c, /* 32 bit r/o Rx MAC Ctrl Frame Counter */
2463 XM_RXF_INV_MP = 0x0320, /* 32 bit r/o Rx invalid Pause Frame Cnt */
2464 XM_RXF_INV_MOC = 0x0324, /* 32 bit r/o Rx Frames with inv. MAC Opcode*/
2465 XM_RXE_BURST = 0x0328, /* 32 bit r/o Rx Burst Event Counter */
2466 XM_RXE_FMISS = 0x032c, /* 32 bit r/o Rx Missed Frames Event Cnt */
2467 XM_RXF_FRA_ERR = 0x0330, /* 32 bit r/o Rx Framing Error Counter */
2468 XM_RXE_FIFO_OV = 0x0334, /* 32 bit r/o Rx FIFO overflow Event Cnt */
2469 XM_RXF_JAB_PKT = 0x0338, /* 32 bit r/o Rx Jabber Packet Frame Cnt */
2470 XM_RXE_CAR_ERR = 0x033c, /* 32 bit r/o Rx Carrier Event Error Cnt */
2471 XM_RXF_LEN_ERR = 0x0340, /* 32 bit r/o Rx in Range Length Error */
2472 XM_RXE_SYM_ERR = 0x0344, /* 32 bit r/o Rx Symbol Error Counter */
2473 XM_RXE_SHT_ERR = 0x0348, /* 32 bit r/o Rx Short Event Error Cnt */
2474 XM_RXE_RUNT = 0x034c, /* 32 bit r/o Rx Runt Event Counter */
2475 XM_RXF_LNG_ERR = 0x0350, /* 32 bit r/o Rx Frame too Long Error Cnt */
2476 XM_RXF_FCS_ERR = 0x0354, /* 32 bit r/o Rx Frame Check Seq. Error Cnt */
2477 XM_RXF_CEX_ERR = 0x035c, /* 32 bit r/o Rx Carrier Ext Error Frame Cnt*/
2478 XM_RXP_UTIL = 0x0360, /* 32 bit r/o Rx Utilization in % */
2479 XM_RXF_64B = 0x0368, /* 32 bit r/o 64 Byte Rx Frame Counter */
2480 XM_RXF_127B = 0x036c, /* 32 bit r/o 65-127 Byte Rx Frame Counter */
2481 XM_RXF_255B = 0x0370, /* 32 bit r/o 128-255 Byte Rx Frame Counter */
2482 XM_RXF_511B = 0x0374, /* 32 bit r/o 256-511 Byte Rx Frame Counter */
2483 XM_RXF_1023B = 0x0378, /* 32 bit r/o 512-1023 Byte Rx Frame Counter*/
2484 XM_RXF_MAX_SZ = 0x037c, /* 32 bit r/o 1024-MaxSize Byte Rx Frame Cnt*/
2485};
2486
2487/* XM_MMU_CMD 16 bit r/w MMU Command Register */
2488enum {
2489 XM_MMU_PHY_RDY = 1<<12,/* Bit 12: PHY Read Ready */
2490 XM_MMU_PHY_BUSY = 1<<11,/* Bit 11: PHY Busy */
2491 XM_MMU_IGN_PF = 1<<10,/* Bit 10: Ignore Pause Frame */
2492 XM_MMU_MAC_LB = 1<<9, /* Bit 9: Enable MAC Loopback */
2493 XM_MMU_FRC_COL = 1<<7, /* Bit 7: Force Collision */
2494 XM_MMU_SIM_COL = 1<<6, /* Bit 6: Simulate Collision */
2495 XM_MMU_NO_PRE = 1<<5, /* Bit 5: No MDIO Preamble */
2496 XM_MMU_GMII_FD = 1<<4, /* Bit 4: GMII uses Full Duplex */
2497 XM_MMU_RAT_CTRL = 1<<3, /* Bit 3: Enable Rate Control */
2498 XM_MMU_GMII_LOOP= 1<<2, /* Bit 2: PHY is in Loopback Mode */
2499 XM_MMU_ENA_RX = 1<<1, /* Bit 1: Enable Receiver */
2500 XM_MMU_ENA_TX = 1<<0, /* Bit 0: Enable Transmitter */
2501};
2502
2503
2504/* XM_TX_CMD 16 bit r/w Transmit Command Register */
2505enum {
2506 XM_TX_BK2BK = 1<<6, /* Bit 6: Ignor Carrier Sense (Tx Bk2Bk)*/
2507 XM_TX_ENC_BYP = 1<<5, /* Bit 5: Set Encoder in Bypass Mode */
2508 XM_TX_SAM_LINE = 1<<4, /* Bit 4: (sc) Start utilization calculation */
2509 XM_TX_NO_GIG_MD = 1<<3, /* Bit 3: Disable Carrier Extension */
2510 XM_TX_NO_PRE = 1<<2, /* Bit 2: Disable Preamble Generation */
2511 XM_TX_NO_CRC = 1<<1, /* Bit 1: Disable CRC Generation */
2512 XM_TX_AUTO_PAD = 1<<0, /* Bit 0: Enable Automatic Padding */
2513};
2514
2515/* XM_TX_RT_LIM 16 bit r/w Transmit Retry Limit Register */
2516#define XM_RT_LIM_MSK 0x1f /* Bit 4..0: Tx Retry Limit */
2517
2518
2519/* XM_TX_STIME 16 bit r/w Transmit Slottime Register */
2520#define XM_STIME_MSK 0x7f /* Bit 6..0: Tx Slottime bits */
2521
2522
2523/* XM_TX_IPG 16 bit r/w Transmit Inter Packet Gap */
2524#define XM_IPG_MSK 0xff /* Bit 7..0: IPG value bits */
2525
2526
2527/* XM_RX_CMD 16 bit r/w Receive Command Register */
2528enum {
2529 XM_RX_LENERR_OK = 1<<8, /* Bit 8 don't set Rx Err bit for */
2530 /* inrange error packets */
2531 XM_RX_BIG_PK_OK = 1<<7, /* Bit 7 don't set Rx Err bit for */
2532 /* jumbo packets */
2533 XM_RX_IPG_CAP = 1<<6, /* Bit 6 repl. type field with IPG */
2534 XM_RX_TP_MD = 1<<5, /* Bit 5: Enable transparent Mode */
2535 XM_RX_STRIP_FCS = 1<<4, /* Bit 4: Enable FCS Stripping */
2536 XM_RX_SELF_RX = 1<<3, /* Bit 3: Enable Rx of own packets */
2537 XM_RX_SAM_LINE = 1<<2, /* Bit 2: (sc) Start utilization calculation */
2538 XM_RX_STRIP_PAD = 1<<1, /* Bit 1: Strip pad bytes of Rx frames */
2539 XM_RX_DIS_CEXT = 1<<0, /* Bit 0: Disable carrier ext. check */
2540};
2541
2542
2543/* XM_PHY_ADDR 16 bit r/w PHY Address Register */
2544#define XM_PHY_ADDR_SZ 0x1f /* Bit 4..0: PHY Address bits */
2545
2546
2547/* XM_GP_PORT 32 bit r/w General Purpose Port Register */
2548enum {
2549 XM_GP_ANIP = 1<<6, /* Bit 6: (ro) Auto-Neg. in progress */
2550 XM_GP_FRC_INT = 1<<5, /* Bit 5: (sc) Force Interrupt */
2551 XM_GP_RES_MAC = 1<<3, /* Bit 3: (sc) Reset MAC and FIFOs */
2552 XM_GP_RES_STAT = 1<<2, /* Bit 2: (sc) Reset the statistics module */
2553 XM_GP_INP_ASS = 1<<0, /* Bit 0: (ro) GP Input Pin asserted */
2554};
2555
2556
2557/* XM_IMSK 16 bit r/w Interrupt Mask Register */
2558/* XM_ISRC 16 bit r/o Interrupt Status Register */
2559enum {
2560 XM_IS_LNK_AE = 1<<14, /* Bit 14: Link Asynchronous Event */
2561 XM_IS_TX_ABORT = 1<<13, /* Bit 13: Transmit Abort, late Col. etc */
2562 XM_IS_FRC_INT = 1<<12, /* Bit 12: Force INT bit set in GP */
2563 XM_IS_INP_ASS = 1<<11, /* Bit 11: Input Asserted, GP bit 0 set */
2564 XM_IS_LIPA_RC = 1<<10, /* Bit 10: Link Partner requests config */
2565 XM_IS_RX_PAGE = 1<<9, /* Bit 9: Page Received */
2566 XM_IS_TX_PAGE = 1<<8, /* Bit 8: Next Page Loaded for Transmit */
2567 XM_IS_AND = 1<<7, /* Bit 7: Auto-Negotiation Done */
2568 XM_IS_TSC_OV = 1<<6, /* Bit 6: Time Stamp Counter Overflow */
2569 XM_IS_RXC_OV = 1<<5, /* Bit 5: Rx Counter Event Overflow */
2570 XM_IS_TXC_OV = 1<<4, /* Bit 4: Tx Counter Event Overflow */
2571 XM_IS_RXF_OV = 1<<3, /* Bit 3: Receive FIFO Overflow */
2572 XM_IS_TXF_UR = 1<<2, /* Bit 2: Transmit FIFO Underrun */
2573 XM_IS_TX_COMP = 1<<1, /* Bit 1: Frame Tx Complete */
2574 XM_IS_RX_COMP = 1<<0, /* Bit 0: Frame Rx Complete */
2575};
2576
2577#define XM_DEF_MSK (~(XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE | \
2578 XM_IS_AND | XM_IS_RXC_OV | XM_IS_TXC_OV | \
2579 XM_IS_RXF_OV | XM_IS_TXF_UR))
2580
2581
2582/* XM_HW_CFG 16 bit r/w Hardware Config Register */
2583enum {
2584 XM_HW_GEN_EOP = 1<<3, /* Bit 3: generate End of Packet pulse */
2585 XM_HW_COM4SIG = 1<<2, /* Bit 2: use Comma Detect for Sig. Det.*/
2586 XM_HW_GMII_MD = 1<<0, /* Bit 0: GMII Interface selected */
2587};
2588
2589
2590/* XM_TX_LO_WM 16 bit r/w Tx FIFO Low Water Mark */
2591/* XM_TX_HI_WM 16 bit r/w Tx FIFO High Water Mark */
2592#define XM_TX_WM_MSK 0x01ff /* Bit 9.. 0 Tx FIFO Watermark bits */
2593
2594/* XM_TX_THR 16 bit r/w Tx Request Threshold */
2595/* XM_HT_THR 16 bit r/w Host Request Threshold */
2596/* XM_RX_THR 16 bit r/w Rx Request Threshold */
2597#define XM_THR_MSK 0x03ff /* Bit 10.. 0 Rx/Tx Request Threshold bits */
2598
2599
2600/* XM_TX_STAT 32 bit r/o Tx Status LIFO Register */
2601enum {
2602 XM_ST_VALID = (1UL<<31), /* Bit 31: Status Valid */
2603 XM_ST_BYTE_CNT = (0x3fffL<<17), /* Bit 30..17: Tx frame Length */
2604 XM_ST_RETRY_CNT = (0x1fL<<12), /* Bit 16..12: Retry Count */
2605 XM_ST_EX_COL = 1<<11, /* Bit 11: Excessive Collisions */
2606 XM_ST_EX_DEF = 1<<10, /* Bit 10: Excessive Deferral */
2607 XM_ST_BURST = 1<<9, /* Bit 9: p. xmitted in burst md*/
2608 XM_ST_DEFER = 1<<8, /* Bit 8: packet was defered */
2609 XM_ST_BC = 1<<7, /* Bit 7: Broadcast packet */
2610 XM_ST_MC = 1<<6, /* Bit 6: Multicast packet */
2611 XM_ST_UC = 1<<5, /* Bit 5: Unicast packet */
2612 XM_ST_TX_UR = 1<<4, /* Bit 4: FIFO Underrun occured */
2613 XM_ST_CS_ERR = 1<<3, /* Bit 3: Carrier Sense Error */
2614 XM_ST_LAT_COL = 1<<2, /* Bit 2: Late Collision Error */
2615 XM_ST_MUL_COL = 1<<1, /* Bit 1: Multiple Collisions */
2616 XM_ST_SGN_COL = 1<<0, /* Bit 0: Single Collision */
2617};
2618
2619/* XM_RX_LO_WM 16 bit r/w Receive Low Water Mark */
2620/* XM_RX_HI_WM 16 bit r/w Receive High Water Mark */
2621#define XM_RX_WM_MSK 0x03ff /* Bit 11.. 0: Rx FIFO Watermark bits */
2622
2623
2624/* XM_DEV_ID 32 bit r/o Device ID Register */
2625#define XM_DEV_OUI (0x00ffffffUL<<8) /* Bit 31..8: Device OUI */
2626#define XM_DEV_REV (0x07L << 5) /* Bit 7..5: Chip Rev Num */
2627
2628
2629/* XM_MODE 32 bit r/w Mode Register */
2630enum {
2631 XM_MD_ENA_REJ = 1<<26, /* Bit 26: Enable Frame Reject */
2632 XM_MD_SPOE_E = 1<<25, /* Bit 25: Send Pause on Edge */
2633 /* extern generated */
2634 XM_MD_TX_REP = 1<<24, /* Bit 24: Transmit Repeater Mode */
2635 XM_MD_SPOFF_I = 1<<23, /* Bit 23: Send Pause on FIFO full */
2636 /* intern generated */
2637 XM_MD_LE_STW = 1<<22, /* Bit 22: Rx Stat Word in Little Endian */
2638 XM_MD_TX_CONT = 1<<21, /* Bit 21: Send Continuous */
2639 XM_MD_TX_PAUSE = 1<<20, /* Bit 20: (sc) Send Pause Frame */
2640 XM_MD_ATS = 1<<19, /* Bit 19: Append Time Stamp */
2641 XM_MD_SPOL_I = 1<<18, /* Bit 18: Send Pause on Low */
2642 /* intern generated */
2643 XM_MD_SPOH_I = 1<<17, /* Bit 17: Send Pause on High */
2644 /* intern generated */
2645 XM_MD_CAP = 1<<16, /* Bit 16: Check Address Pair */
2646 XM_MD_ENA_HASH = 1<<15, /* Bit 15: Enable Hashing */
2647 XM_MD_CSA = 1<<14, /* Bit 14: Check Station Address */
2648 XM_MD_CAA = 1<<13, /* Bit 13: Check Address Array */
2649 XM_MD_RX_MCTRL = 1<<12, /* Bit 12: Rx MAC Control Frame */
2650 XM_MD_RX_RUNT = 1<<11, /* Bit 11: Rx Runt Frames */
2651 XM_MD_RX_IRLE = 1<<10, /* Bit 10: Rx in Range Len Err Frame */
2652 XM_MD_RX_LONG = 1<<9, /* Bit 9: Rx Long Frame */
2653 XM_MD_RX_CRCE = 1<<8, /* Bit 8: Rx CRC Error Frame */
2654 XM_MD_RX_ERR = 1<<7, /* Bit 7: Rx Error Frame */
2655 XM_MD_DIS_UC = 1<<6, /* Bit 6: Disable Rx Unicast */
2656 XM_MD_DIS_MC = 1<<5, /* Bit 5: Disable Rx Multicast */
2657 XM_MD_DIS_BC = 1<<4, /* Bit 4: Disable Rx Broadcast */
2658 XM_MD_ENA_PROM = 1<<3, /* Bit 3: Enable Promiscuous */
2659 XM_MD_ENA_BE = 1<<2, /* Bit 2: Enable Big Endian */
2660 XM_MD_FTF = 1<<1, /* Bit 1: (sc) Flush Tx FIFO */
2661 XM_MD_FRF = 1<<0, /* Bit 0: (sc) Flush Rx FIFO */
2662};
2663
2664#define XM_PAUSE_MODE (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I)
2665#define XM_DEF_MODE (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\
2666 XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA | XM_MD_CAA)
2667
2668/* XM_STAT_CMD 16 bit r/w Statistics Command Register */
2669enum {
2670 XM_SC_SNP_RXC = 1<<5, /* Bit 5: (sc) Snap Rx Counters */
2671 XM_SC_SNP_TXC = 1<<4, /* Bit 4: (sc) Snap Tx Counters */
2672 XM_SC_CP_RXC = 1<<3, /* Bit 3: Copy Rx Counters Continuously */
2673 XM_SC_CP_TXC = 1<<2, /* Bit 2: Copy Tx Counters Continuously */
2674 XM_SC_CLR_RXC = 1<<1, /* Bit 1: (sc) Clear Rx Counters */
2675 XM_SC_CLR_TXC = 1<<0, /* Bit 0: (sc) Clear Tx Counters */
2676};
2677
2678
2679/* XM_RX_CNT_EV 32 bit r/o Rx Counter Event Register */
2680/* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */
2681enum {
2682 XMR_MAX_SZ_OV = 1<<31, /* Bit 31: 1024-MaxSize Rx Cnt Ov*/
2683 XMR_1023B_OV = 1<<30, /* Bit 30: 512-1023Byte Rx Cnt Ov*/
2684 XMR_511B_OV = 1<<29, /* Bit 29: 256-511 Byte Rx Cnt Ov*/
2685 XMR_255B_OV = 1<<28, /* Bit 28: 128-255 Byte Rx Cnt Ov*/
2686 XMR_127B_OV = 1<<27, /* Bit 27: 65-127 Byte Rx Cnt Ov */
2687 XMR_64B_OV = 1<<26, /* Bit 26: 64 Byte Rx Cnt Ov */
2688 XMR_UTIL_OV = 1<<25, /* Bit 25: Rx Util Cnt Overflow */
2689 XMR_UTIL_UR = 1<<24, /* Bit 24: Rx Util Cnt Underrun */
2690 XMR_CEX_ERR_OV = 1<<23, /* Bit 23: CEXT Err Cnt Ov */
2691 XMR_FCS_ERR_OV = 1<<21, /* Bit 21: Rx FCS Error Cnt Ov */
2692 XMR_LNG_ERR_OV = 1<<20, /* Bit 20: Rx too Long Err Cnt Ov*/
2693 XMR_RUNT_OV = 1<<19, /* Bit 19: Runt Event Cnt Ov */
2694 XMR_SHT_ERR_OV = 1<<18, /* Bit 18: Rx Short Ev Err Cnt Ov*/
2695 XMR_SYM_ERR_OV = 1<<17, /* Bit 17: Rx Sym Err Cnt Ov */
2696 XMR_CAR_ERR_OV = 1<<15, /* Bit 15: Rx Carr Ev Err Cnt Ov */
2697 XMR_JAB_PKT_OV = 1<<14, /* Bit 14: Rx Jabb Packet Cnt Ov */
2698 XMR_FIFO_OV = 1<<13, /* Bit 13: Rx FIFO Ov Ev Cnt Ov */
2699 XMR_FRA_ERR_OV = 1<<12, /* Bit 12: Rx Framing Err Cnt Ov */
2700 XMR_FMISS_OV = 1<<11, /* Bit 11: Rx Missed Ev Cnt Ov */
2701 XMR_BURST = 1<<10, /* Bit 10: Rx Burst Event Cnt Ov */
2702 XMR_INV_MOC = 1<<9, /* Bit 9: Rx with inv. MAC OC Ov*/
2703 XMR_INV_MP = 1<<8, /* Bit 8: Rx inv Pause Frame Ov */
2704 XMR_MCTRL_OV = 1<<7, /* Bit 7: Rx MAC Ctrl-F Cnt Ov */
2705 XMR_MPAUSE_OV = 1<<6, /* Bit 6: Rx Pause MAC Ctrl-F Ov*/
2706 XMR_UC_OK_OV = 1<<5, /* Bit 5: Rx Unicast Frame CntOv*/
2707 XMR_MC_OK_OV = 1<<4, /* Bit 4: Rx Multicast Cnt Ov */
2708 XMR_BC_OK_OV = 1<<3, /* Bit 3: Rx Broadcast Cnt Ov */
2709 XMR_OK_LO_OV = 1<<2, /* Bit 2: Octets Rx OK Low CntOv*/
2710 XMR_OK_HI_OV = 1<<1, /* Bit 1: Octets Rx OK Hi Cnt Ov*/
2711 XMR_OK_OV = 1<<0, /* Bit 0: Frames Received Ok Ov */
2712};
2713
2714#define XMR_DEF_MSK (XMR_OK_LO_OV | XMR_OK_HI_OV)
2715
2716/* XM_TX_CNT_EV 32 bit r/o Tx Counter Event Register */
2717/* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */
2718enum {
2719 XMT_MAX_SZ_OV = 1<<25, /* Bit 25: 1024-MaxSize Tx Cnt Ov*/
2720 XMT_1023B_OV = 1<<24, /* Bit 24: 512-1023Byte Tx Cnt Ov*/
2721 XMT_511B_OV = 1<<23, /* Bit 23: 256-511 Byte Tx Cnt Ov*/
2722 XMT_255B_OV = 1<<22, /* Bit 22: 128-255 Byte Tx Cnt Ov*/
2723 XMT_127B_OV = 1<<21, /* Bit 21: 65-127 Byte Tx Cnt Ov */
2724 XMT_64B_OV = 1<<20, /* Bit 20: 64 Byte Tx Cnt Ov */
2725 XMT_UTIL_OV = 1<<19, /* Bit 19: Tx Util Cnt Overflow */
2726 XMT_UTIL_UR = 1<<18, /* Bit 18: Tx Util Cnt Underrun */
2727 XMT_CS_ERR_OV = 1<<17, /* Bit 17: Tx Carr Sen Err Cnt Ov*/
2728 XMT_FIFO_UR_OV = 1<<16, /* Bit 16: Tx FIFO Ur Ev Cnt Ov */
2729 XMT_EX_DEF_OV = 1<<15, /* Bit 15: Tx Ex Deferall Cnt Ov */
2730 XMT_DEF = 1<<14, /* Bit 14: Tx Deferred Cnt Ov */
2731 XMT_LAT_COL_OV = 1<<13, /* Bit 13: Tx Late Col Cnt Ov */
2732 XMT_ABO_COL_OV = 1<<12, /* Bit 12: Tx abo dueto Ex Col Ov*/
2733 XMT_MUL_COL_OV = 1<<11, /* Bit 11: Tx Mult Col Cnt Ov */
2734 XMT_SNG_COL = 1<<10, /* Bit 10: Tx Single Col Cnt Ov */
2735 XMT_MCTRL_OV = 1<<9, /* Bit 9: Tx MAC Ctrl Counter Ov*/
2736 XMT_MPAUSE = 1<<8, /* Bit 8: Tx Pause MAC Ctrl-F Ov*/
2737 XMT_BURST = 1<<7, /* Bit 7: Tx Burst Event Cnt Ov */
2738 XMT_LONG = 1<<6, /* Bit 6: Tx Long Frame Cnt Ov */
2739 XMT_UC_OK_OV = 1<<5, /* Bit 5: Tx Unicast Cnt Ov */
2740 XMT_MC_OK_OV = 1<<4, /* Bit 4: Tx Multicast Cnt Ov */
2741 XMT_BC_OK_OV = 1<<3, /* Bit 3: Tx Broadcast Cnt Ov */
2742 XMT_OK_LO_OV = 1<<2, /* Bit 2: Octets Tx OK Low CntOv*/
2743 XMT_OK_HI_OV = 1<<1, /* Bit 1: Octets Tx OK Hi Cnt Ov*/
2744 XMT_OK_OV = 1<<0, /* Bit 0: Frames Tx Ok Ov */
2745};
2746
2747#define XMT_DEF_MSK (XMT_OK_LO_OV | XMT_OK_HI_OV)
2748
2749struct skge_rx_desc {
2750 u32 control;
2751 u32 next_offset;
2752 u32 dma_lo;
2753 u32 dma_hi;
2754 u32 status;
2755 u32 timestamp;
2756 u16 csum2;
2757 u16 csum1;
2758 u16 csum2_start;
2759 u16 csum1_start;
2760};
2761
2762struct skge_tx_desc {
2763 u32 control;
2764 u32 next_offset;
2765 u32 dma_lo;
2766 u32 dma_hi;
2767 u32 status;
2768 u32 csum_offs;
2769 u16 csum_write;
2770 u16 csum_start;
2771 u32 rsvd;
2772};
2773
2774struct skge_element {
2775 struct skge_element *next;
2776 void *desc;
2777 struct sk_buff *skb;
2778 DECLARE_PCI_UNMAP_ADDR(mapaddr);
2779 DECLARE_PCI_UNMAP_LEN(maplen);
2780};
2781
2782struct skge_ring {
2783 struct skge_element *to_clean;
2784 struct skge_element *to_use;
2785 struct skge_element *start;
2786 unsigned long count;
2787};
2788
2789
2790struct skge_hw {
2791 void __iomem *regs;
2792 struct pci_dev *pdev;
2793 u32 intr_mask;
2794 struct net_device *dev[2];
2795
2796 u8 mac_cfg;
2797 u8 chip_id;
2798 u8 phy_type;
2799 u8 pmd_type;
2800 u16 phy_addr;
2801
2802 u32 ram_size;
2803 u32 ram_offset;
2804
2805 struct tasklet_struct ext_tasklet;
2806 spinlock_t phy_lock;
2807};
2808
2809static inline int isdualport(const struct skge_hw *hw)
2810{
2811 return !(hw->mac_cfg & CFG_SNG_MAC);
2812}
2813
2814static inline u8 chip_rev(const struct skge_hw *hw)
2815{
2816 return (hw->mac_cfg & CFG_CHIP_R_MSK) >> 4;
2817}
2818
2819static inline int iscopper(const struct skge_hw *hw)
2820{
2821 return (hw->pmd_type == 'T');
2822}
2823
2824enum {
2825 FLOW_MODE_NONE = 0, /* No Flow-Control */
2826 FLOW_MODE_LOC_SEND = 1, /* Local station sends PAUSE */
2827 FLOW_MODE_REM_SEND = 2, /* Symmetric or just remote */
2828 FLOW_MODE_SYMMETRIC = 3, /* Both stations may send PAUSE */
2829};
2830
2831struct skge_port {
2832 u32 msg_enable;
2833 struct skge_hw *hw;
2834 struct net_device *netdev;
2835 int port;
2836
2837 spinlock_t tx_lock;
2838 u32 tx_avail;
2839 struct skge_ring tx_ring;
2840 struct skge_ring rx_ring;
2841
2842 struct net_device_stats net_stats;
2843
2844 u8 rx_csum;
2845 u8 blink_on;
2846 u8 flow_control;
2847 u8 wol;
2848 u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */
2849 u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */
2850 u16 speed; /* SPEED_1000, SPEED_100, ... */
2851 u32 advertising;
2852
2853 void *mem; /* PCI memory for rings */
2854 dma_addr_t dma;
2855 unsigned long mem_size;
2856
2857 struct timer_list link_check;
2858 struct timer_list led_blink;
2859};
2860
2861
2862/* Register accessor for memory mapped device */
2863static inline u32 skge_read32(const struct skge_hw *hw, int reg)
2864{
2865 return readl(hw->regs + reg);
2866
2867}
2868
2869static inline u16 skge_read16(const struct skge_hw *hw, int reg)
2870{
2871 return readw(hw->regs + reg);
2872}
2873
2874static inline u8 skge_read8(const struct skge_hw *hw, int reg)
2875{
2876 return readb(hw->regs + reg);
2877}
2878
2879static inline void skge_write32(const struct skge_hw *hw, int reg, u32 val)
2880{
2881 writel(val, hw->regs + reg);
2882}
2883
2884static inline void skge_write16(const struct skge_hw *hw, int reg, u16 val)
2885{
2886 writew(val, hw->regs + reg);
2887}
2888
2889static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val)
2890{
2891 writeb(val, hw->regs + reg);
2892}
2893
2894/* MAC Related Registers inside the device. */
2895#define SKGEMAC_REG(port,reg) (((port)<<7)+(reg))
2896
2897/* PCI config space can be accessed via memory mapped space */
2898#define SKGEPCI_REG(reg) ((reg)+ 0x380)
2899
2900#define SKGEXM_REG(port, reg) \
2901 ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
2902
2903static inline u32 skge_xm_read32(const struct skge_hw *hw, int port, int reg)
2904{
2905 return skge_read32(hw, SKGEXM_REG(port,reg));
2906}
2907
2908static inline u16 skge_xm_read16(const struct skge_hw *hw, int port, int reg)
2909{
2910 return skge_read16(hw, SKGEXM_REG(port,reg));
2911}
2912
2913static inline u8 skge_xm_read8(const struct skge_hw *hw, int port, int reg)
2914{
2915 return skge_read8(hw, SKGEXM_REG(port,reg));
2916}
2917
2918static inline void skge_xm_write32(const struct skge_hw *hw, int port, int r, u32 v)
2919{
2920 skge_write32(hw, SKGEXM_REG(port,r), v);
2921}
2922
2923static inline void skge_xm_write16(const struct skge_hw *hw, int port, int r, u16 v)
2924{
2925 skge_write16(hw, SKGEXM_REG(port,r), v);
2926}
2927
2928static inline void skge_xm_write8(const struct skge_hw *hw, int port, int r, u8 v)
2929{
2930 skge_write8(hw, SKGEXM_REG(port,r), v);
2931}
2932
2933static inline void skge_xm_outhash(const struct skge_hw *hw, int port, int reg,
2934 const u8 *hash)
2935{
2936 skge_xm_write16(hw, port, reg,
2937 (u16)hash[0] | ((u16)hash[1] << 8));
2938 skge_xm_write16(hw, port, reg+2,
2939 (u16)hash[2] | ((u16)hash[3] << 8));
2940 skge_xm_write16(hw, port, reg+4,
2941 (u16)hash[4] | ((u16)hash[5] << 8));
2942 skge_xm_write16(hw, port, reg+6,
2943 (u16)hash[6] | ((u16)hash[7] << 8));
2944}
2945
2946static inline void skge_xm_outaddr(const struct skge_hw *hw, int port, int reg,
2947 const u8 *addr)
2948{
2949 skge_xm_write16(hw, port, reg,
2950 (u16)addr[0] | ((u16)addr[1] << 8));
2951 skge_xm_write16(hw, port, reg,
2952 (u16)addr[2] | ((u16)addr[3] << 8));
2953 skge_xm_write16(hw, port, reg,
2954 (u16)addr[4] | ((u16)addr[5] << 8));
2955}
2956
2957
2958#define SKGEGMA_REG(port,reg) \
2959 ((reg) + BASE_GMAC_1 + \
2960 (port) * (BASE_GMAC_2-BASE_GMAC_1))
2961
2962static inline u16 skge_gma_read16(const struct skge_hw *hw, int port, int reg)
2963{
2964 return skge_read16(hw, SKGEGMA_REG(port,reg));
2965}
2966
2967static inline u32 skge_gma_read32(const struct skge_hw *hw, int port, int reg)
2968{
2969 return (u32) skge_read16(hw, SKGEGMA_REG(port,reg))
2970 | ((u32)skge_read16(hw, SKGEGMA_REG(port,reg+4)) << 16);
2971}
2972
2973static inline u8 skge_gma_read8(const struct skge_hw *hw, int port, int reg)
2974{
2975 return skge_read8(hw, SKGEGMA_REG(port,reg));
2976}
2977
2978static inline void skge_gma_write16(const struct skge_hw *hw, int port, int r, u16 v)
2979{
2980 skge_write16(hw, SKGEGMA_REG(port,r), v);
2981}
2982
2983static inline void skge_gma_write32(const struct skge_hw *hw, int port, int r, u32 v)
2984{
2985 skge_write16(hw, SKGEGMA_REG(port, r), (u16) v);
2986 skge_write32(hw, SKGEGMA_REG(port, r+4), (u16)(v >> 16));
2987}
2988
2989static inline void skge_gma_write8(const struct skge_hw *hw, int port, int r, u8 v)
2990{
2991 skge_write8(hw, SKGEGMA_REG(port,r), v);
2992}
2993
2994static inline void skge_gm_set_addr(struct skge_hw *hw, int port, int reg,
2995 const u8 *addr)
2996{
2997 skge_gma_write16(hw, port, reg,
2998 (u16) addr[0] | ((u16) addr[1] << 8));
2999 skge_gma_write16(hw, port, reg+4,
3000 (u16) addr[2] | ((u16) addr[3] << 8));
3001 skge_gma_write16(hw, port, reg+8,
3002 (u16) addr[4] | ((u16) addr[5] << 8));
3003}
3004
3005#endif
diff --git a/drivers/net/slip.c b/drivers/net/slip.c
index 8f7841c0374d..c79e0ad4ba02 100644
--- a/drivers/net/slip.c
+++ b/drivers/net/slip.c
@@ -198,18 +198,12 @@ err_exit:
198static void 198static void
199sl_free_bufs(struct slip *sl) 199sl_free_bufs(struct slip *sl)
200{ 200{
201 void * tmp;
202
203 /* Free all SLIP frame buffers. */ 201 /* Free all SLIP frame buffers. */
204 tmp = xchg(&sl->rbuff, NULL); 202 kfree(xchg(&sl->rbuff, NULL));
205 kfree(tmp); 203 kfree(xchg(&sl->xbuff, NULL));
206 tmp = xchg(&sl->xbuff, NULL);
207 kfree(tmp);
208#ifdef SL_INCLUDE_CSLIP 204#ifdef SL_INCLUDE_CSLIP
209 tmp = xchg(&sl->cbuff, NULL); 205 kfree(xchg(&sl->cbuff, NULL));
210 kfree(tmp); 206 slhc_free(xchg(&sl->slcomp, NULL));
211 if ((tmp = xchg(&sl->slcomp, NULL)) != NULL)
212 slhc_free(tmp);
213#endif 207#endif
214} 208}
215 209
@@ -1430,7 +1424,7 @@ static void __exit slip_exit(void)
1430 kfree(slip_devs); 1424 kfree(slip_devs);
1431 slip_devs = NULL; 1425 slip_devs = NULL;
1432 1426
1433 if ((i = tty_register_ldisc(N_SLIP, NULL))) 1427 if ((i = tty_unregister_ldisc(N_SLIP)))
1434 { 1428 {
1435 printk(KERN_ERR "SLIP: can't unregister line discipline (err = %d)\n", i); 1429 printk(KERN_ERR "SLIP: can't unregister line discipline (err = %d)\n", i);
1436 } 1430 }
diff --git a/drivers/net/smc91x.c b/drivers/net/smc91x.c
index 5e561ba44333..fd80048f7f7a 100644
--- a/drivers/net/smc91x.c
+++ b/drivers/net/smc91x.c
@@ -129,7 +129,7 @@ MODULE_PARM_DESC(nowait, "set to 1 for no wait state");
129/* 129/*
130 * Transmit timeout, default 5 seconds. 130 * Transmit timeout, default 5 seconds.
131 */ 131 */
132static int watchdog = 5000; 132static int watchdog = 1000;
133module_param(watchdog, int, 0400); 133module_param(watchdog, int, 0400);
134MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); 134MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
135 135
@@ -660,15 +660,14 @@ static void smc_hardware_send_pkt(unsigned long data)
660 SMC_outw(((len & 1) ? (0x2000 | buf[len-1]) : 0), ioaddr, DATA_REG); 660 SMC_outw(((len & 1) ? (0x2000 | buf[len-1]) : 0), ioaddr, DATA_REG);
661 661
662 /* 662 /*
663 * If THROTTLE_TX_PKTS is set, we look at the TX_EMPTY flag 663 * If THROTTLE_TX_PKTS is set, we stop the queue here. This will
664 * before queueing this packet for TX, and if it's clear then 664 * have the effect of having at most one packet queued for TX
665 * we stop the queue here. This will have the effect of 665 * in the chip's memory at all time.
666 * having at most 2 packets queued for TX in the chip's memory 666 *
667 * at all time. If THROTTLE_TX_PKTS is not set then the queue 667 * If THROTTLE_TX_PKTS is not set then the queue is stopped only
668 * is stopped only when memory allocation (MC_ALLOC) does not 668 * when memory allocation (MC_ALLOC) does not succeed right away.
669 * succeed right away.
670 */ 669 */
671 if (THROTTLE_TX_PKTS && !(SMC_GET_INT() & IM_TX_EMPTY_INT)) 670 if (THROTTLE_TX_PKTS)
672 netif_stop_queue(dev); 671 netif_stop_queue(dev);
673 672
674 /* queue the packet for TX */ 673 /* queue the packet for TX */
@@ -792,17 +791,20 @@ static void smc_tx(struct net_device *dev)
792 DBG(2, "%s: TX STATUS 0x%04x PNR 0x%02x\n", 791 DBG(2, "%s: TX STATUS 0x%04x PNR 0x%02x\n",
793 dev->name, tx_status, packet_no); 792 dev->name, tx_status, packet_no);
794 793
795 if (!(tx_status & TS_SUCCESS)) 794 if (!(tx_status & ES_TX_SUC))
796 lp->stats.tx_errors++; 795 lp->stats.tx_errors++;
797 if (tx_status & TS_LOSTCAR) 796
797 if (tx_status & ES_LOSTCARR)
798 lp->stats.tx_carrier_errors++; 798 lp->stats.tx_carrier_errors++;
799 799
800 if (tx_status & TS_LATCOL) { 800 if (tx_status & (ES_LATCOL | ES_16COL)) {
801 PRINTK("%s: late collision occurred on last xmit\n", dev->name); 801 PRINTK("%s: %s occurred on last xmit\n", dev->name,
802 (tx_status & ES_LATCOL) ?
803 "late collision" : "too many collisions");
802 lp->stats.tx_window_errors++; 804 lp->stats.tx_window_errors++;
803 if (!(lp->stats.tx_window_errors & 63) && net_ratelimit()) { 805 if (!(lp->stats.tx_window_errors & 63) && net_ratelimit()) {
804 printk(KERN_INFO "%s: unexpectedly large numbers of " 806 printk(KERN_INFO "%s: unexpectedly large number of "
805 "late collisions. Please check duplex " 807 "bad collisions. Please check duplex "
806 "setting.\n", dev->name); 808 "setting.\n", dev->name);
807 } 809 }
808 } 810 }
@@ -1236,7 +1238,7 @@ static void smc_10bt_check_media(struct net_device *dev, int init)
1236 old_carrier = netif_carrier_ok(dev) ? 1 : 0; 1238 old_carrier = netif_carrier_ok(dev) ? 1 : 0;
1237 1239
1238 SMC_SELECT_BANK(0); 1240 SMC_SELECT_BANK(0);
1239 new_carrier = SMC_inw(ioaddr, EPH_STATUS_REG) & ES_LINK_OK ? 1 : 0; 1241 new_carrier = (SMC_GET_EPH_STATUS() & ES_LINK_OK) ? 1 : 0;
1240 SMC_SELECT_BANK(2); 1242 SMC_SELECT_BANK(2);
1241 1243
1242 if (init || (old_carrier != new_carrier)) { 1244 if (init || (old_carrier != new_carrier)) {
@@ -1308,15 +1310,16 @@ static irqreturn_t smc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1308 if (!status) 1310 if (!status)
1309 break; 1311 break;
1310 1312
1311 if (status & IM_RCV_INT) { 1313 if (status & IM_TX_INT) {
1312 DBG(3, "%s: RX irq\n", dev->name); 1314 /* do this before RX as it will free memory quickly */
1313 smc_rcv(dev);
1314 } else if (status & IM_TX_INT) {
1315 DBG(3, "%s: TX int\n", dev->name); 1315 DBG(3, "%s: TX int\n", dev->name);
1316 smc_tx(dev); 1316 smc_tx(dev);
1317 SMC_ACK_INT(IM_TX_INT); 1317 SMC_ACK_INT(IM_TX_INT);
1318 if (THROTTLE_TX_PKTS) 1318 if (THROTTLE_TX_PKTS)
1319 netif_wake_queue(dev); 1319 netif_wake_queue(dev);
1320 } else if (status & IM_RCV_INT) {
1321 DBG(3, "%s: RX irq\n", dev->name);
1322 smc_rcv(dev);
1320 } else if (status & IM_ALLOC_INT) { 1323 } else if (status & IM_ALLOC_INT) {
1321 DBG(3, "%s: Allocation irq\n", dev->name); 1324 DBG(3, "%s: Allocation irq\n", dev->name);
1322 tasklet_hi_schedule(&lp->tx_task); 1325 tasklet_hi_schedule(&lp->tx_task);
@@ -1337,7 +1340,10 @@ static irqreturn_t smc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1337 /* multiple collisions */ 1340 /* multiple collisions */
1338 lp->stats.collisions += card_stats & 0xF; 1341 lp->stats.collisions += card_stats & 0xF;
1339 } else if (status & IM_RX_OVRN_INT) { 1342 } else if (status & IM_RX_OVRN_INT) {
1340 DBG(1, "%s: RX overrun\n", dev->name); 1343 DBG(1, "%s: RX overrun (EPH_ST 0x%04x)\n", dev->name,
1344 ({ int eph_st; SMC_SELECT_BANK(0);
1345 eph_st = SMC_GET_EPH_STATUS();
1346 SMC_SELECT_BANK(2); eph_st; }) );
1341 SMC_ACK_INT(IM_RX_OVRN_INT); 1347 SMC_ACK_INT(IM_RX_OVRN_INT);
1342 lp->stats.rx_errors++; 1348 lp->stats.rx_errors++;
1343 lp->stats.rx_fifo_errors++; 1349 lp->stats.rx_fifo_errors++;
@@ -1389,7 +1395,7 @@ static void smc_timeout(struct net_device *dev)
1389{ 1395{
1390 struct smc_local *lp = netdev_priv(dev); 1396 struct smc_local *lp = netdev_priv(dev);
1391 void __iomem *ioaddr = lp->base; 1397 void __iomem *ioaddr = lp->base;
1392 int status, mask, meminfo, fifo; 1398 int status, mask, eph_st, meminfo, fifo;
1393 1399
1394 DBG(2, "%s: %s\n", dev->name, __FUNCTION__); 1400 DBG(2, "%s: %s\n", dev->name, __FUNCTION__);
1395 1401
@@ -1398,11 +1404,13 @@ static void smc_timeout(struct net_device *dev)
1398 mask = SMC_GET_INT_MASK(); 1404 mask = SMC_GET_INT_MASK();
1399 fifo = SMC_GET_FIFO(); 1405 fifo = SMC_GET_FIFO();
1400 SMC_SELECT_BANK(0); 1406 SMC_SELECT_BANK(0);
1407 eph_st = SMC_GET_EPH_STATUS();
1401 meminfo = SMC_GET_MIR(); 1408 meminfo = SMC_GET_MIR();
1402 SMC_SELECT_BANK(2); 1409 SMC_SELECT_BANK(2);
1403 spin_unlock_irq(&lp->lock); 1410 spin_unlock_irq(&lp->lock);
1404 PRINTK( "%s: INT 0x%02x MASK 0x%02x MEM 0x%04x FIFO 0x%04x\n", 1411 PRINTK( "%s: TX timeout (INT 0x%02x INTMASK 0x%02x "
1405 dev->name, status, mask, meminfo, fifo ); 1412 "MEM 0x%04x FIFO 0x%04x EPH_ST 0x%04x)\n",
1413 dev->name, status, mask, meminfo, fifo, eph_st );
1406 1414
1407 smc_reset(dev); 1415 smc_reset(dev);
1408 smc_enable(dev); 1416 smc_enable(dev);
@@ -1863,7 +1871,7 @@ static int __init smc_probe(struct net_device *dev, void __iomem *ioaddr)
1863 SMC_SELECT_BANK(1); 1871 SMC_SELECT_BANK(1);
1864 val = SMC_GET_BASE(); 1872 val = SMC_GET_BASE();
1865 val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT; 1873 val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT;
1866 if (((unsigned long)ioaddr & ((PAGE_SIZE-1)<<SMC_IO_SHIFT)) != val) { /*XXX: WTF? */ 1874 if (((unsigned int)ioaddr & (0x3e0 << SMC_IO_SHIFT)) != val) {
1867 printk("%s: IOADDR %p doesn't match configuration (%x).\n", 1875 printk("%s: IOADDR %p doesn't match configuration (%x).\n",
1868 CARDNAME, ioaddr, val); 1876 CARDNAME, ioaddr, val);
1869 } 1877 }
diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h
index ddd2688e7d33..946528e6b742 100644
--- a/drivers/net/smc91x.h
+++ b/drivers/net/smc91x.h
@@ -151,7 +151,7 @@
151 151
152/* We actually can't write halfwords properly if not word aligned */ 152/* We actually can't write halfwords properly if not word aligned */
153static inline void 153static inline void
154SMC_outw(u16 val, unsigned long ioaddr, int reg) 154SMC_outw(u16 val, void __iomem *ioaddr, int reg)
155{ 155{
156 if (reg & 2) { 156 if (reg & 2) {
157 unsigned int v = val << 16; 157 unsigned int v = val << 16;
@@ -317,7 +317,7 @@ static inline void SMC_outsw (unsigned long a, int r, unsigned char* p, int l)
317#define SMC_insl(a, r, p, l) \ 317#define SMC_insl(a, r, p, l) \
318 smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l) 318 smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l)
319static inline void 319static inline void
320smc_pxa_dma_insl(u_long ioaddr, u_long physaddr, int reg, int dma, 320smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
321 u_char *buf, int len) 321 u_char *buf, int len)
322{ 322{
323 dma_addr_t dmabuf; 323 dma_addr_t dmabuf;
@@ -355,7 +355,7 @@ smc_pxa_dma_insl(u_long ioaddr, u_long physaddr, int reg, int dma,
355#define SMC_insw(a, r, p, l) \ 355#define SMC_insw(a, r, p, l) \
356 smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l) 356 smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l)
357static inline void 357static inline void
358smc_pxa_dma_insw(u_long ioaddr, u_long physaddr, int reg, int dma, 358smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
359 u_char *buf, int len) 359 u_char *buf, int len)
360{ 360{
361 dma_addr_t dmabuf; 361 dma_addr_t dmabuf;
@@ -681,14 +681,6 @@ static const char * chip_ids[ 16 ] = {
681 681
682 682
683/* 683/*
684 . Transmit status bits
685*/
686#define TS_SUCCESS 0x0001
687#define TS_LOSTCAR 0x0400
688#define TS_LATCOL 0x0200
689#define TS_16COL 0x0010
690
691/*
692 . Receive status bits 684 . Receive status bits
693*/ 685*/
694#define RS_ALGNERR 0x8000 686#define RS_ALGNERR 0x8000
@@ -845,6 +837,7 @@ static const char * chip_ids[ 16 ] = {
845#define SMC_GET_FIFO() SMC_inw( ioaddr, FIFO_REG ) 837#define SMC_GET_FIFO() SMC_inw( ioaddr, FIFO_REG )
846#define SMC_GET_PTR() SMC_inw( ioaddr, PTR_REG ) 838#define SMC_GET_PTR() SMC_inw( ioaddr, PTR_REG )
847#define SMC_SET_PTR(x) SMC_outw( x, ioaddr, PTR_REG ) 839#define SMC_SET_PTR(x) SMC_outw( x, ioaddr, PTR_REG )
840#define SMC_GET_EPH_STATUS() SMC_inw( ioaddr, EPH_STATUS_REG )
848#define SMC_GET_RCR() SMC_inw( ioaddr, RCR_REG ) 841#define SMC_GET_RCR() SMC_inw( ioaddr, RCR_REG )
849#define SMC_SET_RCR(x) SMC_outw( x, ioaddr, RCR_REG ) 842#define SMC_SET_RCR(x) SMC_outw( x, ioaddr, RCR_REG )
850#define SMC_GET_REV() SMC_inw( ioaddr, REV_REG ) 843#define SMC_GET_REV() SMC_inw( ioaddr, REV_REG )
diff --git a/drivers/net/starfire.c b/drivers/net/starfire.c
index 236bdd3f6ba0..12e2b6826fa3 100644
--- a/drivers/net/starfire.c
+++ b/drivers/net/starfire.c
@@ -2,7 +2,7 @@
2/* 2/*
3 Written 1998-2000 by Donald Becker. 3 Written 1998-2000 by Donald Becker.
4 4
5 Current maintainer is Ion Badulescu <ionut@cs.columbia.edu>. Please 5 Current maintainer is Ion Badulescu <ionut ta badula tod org>. Please
6 send all bug reports to me, and not to Donald Becker, as this code 6 send all bug reports to me, and not to Donald Becker, as this code
7 has been heavily modified from Donald's original version. 7 has been heavily modified from Donald's original version.
8 8
@@ -129,12 +129,18 @@
129 - put the chip to a D3 slumber on driver unload 129 - put the chip to a D3 slumber on driver unload
130 - added config option to enable/disable NAPI 130 - added config option to enable/disable NAPI
131 131
132TODO: bugfixes (no bugs known as of right now) 132 LK1.4.2 (Ion Badulescu)
133 - finally added firmware (GPL'ed by Adaptec)
134 - removed compatibility code for 2.2.x
135
136TODO: - fix forced speed/duplexing code (broken a long time ago, when
137 somebody converted the driver to use the generic MII code)
138 - fix VLAN support
133*/ 139*/
134 140
135#define DRV_NAME "starfire" 141#define DRV_NAME "starfire"
136#define DRV_VERSION "1.03+LK1.4.1" 142#define DRV_VERSION "1.03+LK1.4.2"
137#define DRV_RELDATE "February 10, 2002" 143#define DRV_RELDATE "January 19, 2005"
138 144
139#include <linux/config.h> 145#include <linux/config.h>
140#include <linux/version.h> 146#include <linux/version.h>
@@ -145,25 +151,15 @@ TODO: bugfixes (no bugs known as of right now)
145#include <linux/etherdevice.h> 151#include <linux/etherdevice.h>
146#include <linux/init.h> 152#include <linux/init.h>
147#include <linux/delay.h> 153#include <linux/delay.h>
154#include <linux/crc32.h>
155#include <linux/ethtool.h>
156#include <linux/mii.h>
157#include <linux/if_vlan.h>
148#include <asm/processor.h> /* Processor type for cache alignment. */ 158#include <asm/processor.h> /* Processor type for cache alignment. */
149#include <asm/uaccess.h> 159#include <asm/uaccess.h>
150#include <asm/io.h> 160#include <asm/io.h>
151 161
152/* 162#include "starfire_firmware.h"
153 * Adaptec's license for their drivers (which is where I got the
154 * firmware files) does not allow one to redistribute them. Thus, we can't
155 * include the firmware with this driver.
156 *
157 * However, should a legal-to-distribute firmware become available,
158 * the driver developer would need only to obtain the firmware in the
159 * form of a C header file.
160 * Once that's done, the #undef below must be changed into a #define
161 * for this driver to really use the firmware. Note that Rx/Tx
162 * hardware TCP checksumming is not possible without the firmware.
163 *
164 * WANTED: legal firmware to include with this GPL'd driver.
165 */
166#undef HAS_FIRMWARE
167/* 163/*
168 * The current frame processor firmware fails to checksum a fragment 164 * The current frame processor firmware fails to checksum a fragment
169 * of length 1. If and when this is fixed, the #define below can be removed. 165 * of length 1. If and when this is fixed, the #define below can be removed.
@@ -172,13 +168,7 @@ TODO: bugfixes (no bugs known as of right now)
172/* 168/*
173 * Define this if using the driver with the zero-copy patch 169 * Define this if using the driver with the zero-copy patch
174 */ 170 */
175#if defined(HAS_FIRMWARE) && defined(MAX_SKB_FRAGS)
176#define ZEROCOPY 171#define ZEROCOPY
177#endif
178
179#ifdef HAS_FIRMWARE
180#include "starfire_firmware.h"
181#endif /* HAS_FIRMWARE */
182 172
183#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) 173#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
184#define VLAN_SUPPORT 174#define VLAN_SUPPORT
@@ -202,11 +192,7 @@ static int mtu;
202 The Starfire has a 512 element hash table based on the Ethernet CRC. */ 192 The Starfire has a 512 element hash table based on the Ethernet CRC. */
203static int multicast_filter_limit = 512; 193static int multicast_filter_limit = 512;
204/* Whether to do TCP/UDP checksums in hardware */ 194/* Whether to do TCP/UDP checksums in hardware */
205#ifdef HAS_FIRMWARE
206static int enable_hw_cksum = 1; 195static int enable_hw_cksum = 1;
207#else
208static int enable_hw_cksum = 0;
209#endif
210 196
211#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ 197#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
212/* 198/*
@@ -291,43 +277,15 @@ static int full_duplex[MAX_UNITS] = {0, };
291#define RX_DESC_ADDR_SIZE RxDescAddr32bit 277#define RX_DESC_ADDR_SIZE RxDescAddr32bit
292#endif 278#endif
293 279
294#ifdef MAX_SKB_FRAGS
295#define skb_first_frag_len(skb) skb_headlen(skb) 280#define skb_first_frag_len(skb) skb_headlen(skb)
296#define skb_num_frags(skb) (skb_shinfo(skb)->nr_frags + 1) 281#define skb_num_frags(skb) (skb_shinfo(skb)->nr_frags + 1)
297#else /* not MAX_SKB_FRAGS */
298#define skb_first_frag_len(skb) (skb->len)
299#define skb_num_frags(skb) 1
300#endif /* not MAX_SKB_FRAGS */
301
302/* 2.2.x compatibility code */
303#if LINUX_VERSION_CODE < 0x20300
304
305#include "starfire-kcomp22.h"
306
307#else /* LINUX_VERSION_CODE > 0x20300 */
308
309#include <linux/crc32.h>
310#include <linux/ethtool.h>
311#include <linux/mii.h>
312
313#include <linux/if_vlan.h>
314
315#define init_tx_timer(dev, func, timeout) \
316 dev->tx_timeout = func; \
317 dev->watchdog_timeo = timeout;
318#define kick_tx_timer(dev, func, timeout)
319
320#define netif_start_if(dev)
321#define netif_stop_if(dev)
322
323#define PCI_SLOT_NAME(pci_dev) pci_name(pci_dev)
324
325#endif /* LINUX_VERSION_CODE > 0x20300 */
326 282
327#ifdef HAVE_NETDEV_POLL 283#ifdef HAVE_NETDEV_POLL
328#define init_poll(dev) \ 284#define init_poll(dev) \
285do { \
329 dev->poll = &netdev_poll; \ 286 dev->poll = &netdev_poll; \
330 dev->weight = max_interrupt_work; 287 dev->weight = max_interrupt_work; \
288} while (0)
331#define netdev_rx(dev, ioaddr) \ 289#define netdev_rx(dev, ioaddr) \
332do { \ 290do { \
333 u32 intr_enable; \ 291 u32 intr_enable; \
@@ -341,7 +299,7 @@ do { \
341 /* Paranoia check */ \ 299 /* Paranoia check */ \
342 intr_enable = readl(ioaddr + IntrEnable); \ 300 intr_enable = readl(ioaddr + IntrEnable); \
343 if (intr_enable & (IntrRxDone | IntrRxEmpty)) { \ 301 if (intr_enable & (IntrRxDone | IntrRxEmpty)) { \
344 printk("%s: interrupt while in polling mode!\n", dev->name); \ 302 printk(KERN_INFO "%s: interrupt while in polling mode!\n", dev->name); \
345 intr_enable &= ~(IntrRxDone | IntrRxEmpty); \ 303 intr_enable &= ~(IntrRxDone | IntrRxEmpty); \
346 writel(intr_enable, ioaddr + IntrEnable); \ 304 writel(intr_enable, ioaddr + IntrEnable); \
347 } \ 305 } \
@@ -371,6 +329,7 @@ KERN_INFO " (unofficial 2.2/2.4 kernel port, version " DRV_VERSION ", " DRV_RELD
371MODULE_AUTHOR("Donald Becker <becker@scyld.com>"); 329MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
372MODULE_DESCRIPTION("Adaptec Starfire Ethernet driver"); 330MODULE_DESCRIPTION("Adaptec Starfire Ethernet driver");
373MODULE_LICENSE("GPL"); 331MODULE_LICENSE("GPL");
332MODULE_VERSION(DRV_VERSION);
374 333
375module_param(max_interrupt_work, int, 0); 334module_param(max_interrupt_work, int, 0);
376module_param(mtu, int, 0); 335module_param(mtu, int, 0);
@@ -425,7 +384,7 @@ on the 32/64 bitness of the architecture), and relies on automatic
425minimum-length padding. It does not use the completion queue 384minimum-length padding. It does not use the completion queue
426consumer index, but instead checks for non-zero status entries. 385consumer index, but instead checks for non-zero status entries.
427 386
428For receive this driver uses type 0/1/2/3 receive descriptors. The driver 387For receive this driver uses type 2/3 receive descriptors. The driver
429allocates full frame size skbuffs for the Rx ring buffers, so all frames 388allocates full frame size skbuffs for the Rx ring buffers, so all frames
430should fit in a single descriptor. The driver does not use the completion 389should fit in a single descriptor. The driver does not use the completion
431queue consumer index, but instead checks for non-zero status entries. 390queue consumer index, but instead checks for non-zero status entries.
@@ -476,7 +435,7 @@ IVc. Errata
476 435
477*/ 436*/
478 437
479 438
480 439
481enum chip_capability_flags {CanHaveMII=1, }; 440enum chip_capability_flags {CanHaveMII=1, };
482 441
@@ -670,7 +629,6 @@ struct full_rx_done_desc {
670 u32 timestamp; 629 u32 timestamp;
671}; 630};
672/* XXX: this is ugly and I'm not sure it's worth the trouble -Ion */ 631/* XXX: this is ugly and I'm not sure it's worth the trouble -Ion */
673#ifdef HAS_FIRMWARE
674#ifdef VLAN_SUPPORT 632#ifdef VLAN_SUPPORT
675typedef struct full_rx_done_desc rx_done_desc; 633typedef struct full_rx_done_desc rx_done_desc;
676#define RxComplType RxComplType3 634#define RxComplType RxComplType3
@@ -678,15 +636,6 @@ typedef struct full_rx_done_desc rx_done_desc;
678typedef struct csum_rx_done_desc rx_done_desc; 636typedef struct csum_rx_done_desc rx_done_desc;
679#define RxComplType RxComplType2 637#define RxComplType RxComplType2
680#endif /* not VLAN_SUPPORT */ 638#endif /* not VLAN_SUPPORT */
681#else /* not HAS_FIRMWARE */
682#ifdef VLAN_SUPPORT
683typedef struct basic_rx_done_desc rx_done_desc;
684#define RxComplType RxComplType1
685#else /* not VLAN_SUPPORT */
686typedef struct short_rx_done_desc rx_done_desc;
687#define RxComplType RxComplType0
688#endif /* not VLAN_SUPPORT */
689#endif /* not HAS_FIRMWARE */
690 639
691enum rx_done_bits { 640enum rx_done_bits {
692 RxOK=0x20000000, RxFIFOErr=0x10000000, RxBufQ2=0x08000000, 641 RxOK=0x20000000, RxFIFOErr=0x10000000, RxBufQ2=0x08000000,
@@ -898,13 +847,10 @@ static int __devinit starfire_init_one(struct pci_dev *pdev,
898 /* enable MWI -- it vastly improves Rx performance on sparc64 */ 847 /* enable MWI -- it vastly improves Rx performance on sparc64 */
899 pci_set_mwi(pdev); 848 pci_set_mwi(pdev);
900 849
901#ifdef MAX_SKB_FRAGS
902 dev->features |= NETIF_F_SG;
903#endif /* MAX_SKB_FRAGS */
904#ifdef ZEROCOPY 850#ifdef ZEROCOPY
905 /* Starfire can do TCP/UDP checksumming */ 851 /* Starfire can do TCP/UDP checksumming */
906 if (enable_hw_cksum) 852 if (enable_hw_cksum)
907 dev->features |= NETIF_F_IP_CSUM; 853 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
908#endif /* ZEROCOPY */ 854#endif /* ZEROCOPY */
909#ifdef VLAN_SUPPORT 855#ifdef VLAN_SUPPORT
910 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER; 856 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER;
@@ -1008,7 +954,8 @@ static int __devinit starfire_init_one(struct pci_dev *pdev,
1008 /* The chip-specific entries in the device structure. */ 954 /* The chip-specific entries in the device structure. */
1009 dev->open = &netdev_open; 955 dev->open = &netdev_open;
1010 dev->hard_start_xmit = &start_tx; 956 dev->hard_start_xmit = &start_tx;
1011 init_tx_timer(dev, tx_timeout, TX_TIMEOUT); 957 dev->tx_timeout = tx_timeout;
958 dev->watchdog_timeo = TX_TIMEOUT;
1012 init_poll(dev); 959 init_poll(dev);
1013 dev->stop = &netdev_close; 960 dev->stop = &netdev_close;
1014 dev->get_stats = &get_stats; 961 dev->get_stats = &get_stats;
@@ -1039,7 +986,7 @@ static int __devinit starfire_init_one(struct pci_dev *pdev,
1039 if ((mdio_read(dev, phy, MII_BMCR) & BMCR_RESET) == 0) 986 if ((mdio_read(dev, phy, MII_BMCR) & BMCR_RESET) == 0)
1040 break; 987 break;
1041 if (boguscnt == 0) { 988 if (boguscnt == 0) {
1042 printk("%s: PHY reset never completed!\n", dev->name); 989 printk("%s: PHY#%d reset never completed!\n", dev->name, phy);
1043 continue; 990 continue;
1044 } 991 }
1045 mii_status = mdio_read(dev, phy, MII_BMSR); 992 mii_status = mdio_read(dev, phy, MII_BMSR);
@@ -1110,6 +1057,7 @@ static int netdev_open(struct net_device *dev)
1110 size_t tx_done_q_size, rx_done_q_size, tx_ring_size, rx_ring_size; 1057 size_t tx_done_q_size, rx_done_q_size, tx_ring_size, rx_ring_size;
1111 1058
1112 /* Do we ever need to reset the chip??? */ 1059 /* Do we ever need to reset the chip??? */
1060
1113 retval = request_irq(dev->irq, &intr_handler, SA_SHIRQ, dev->name, dev); 1061 retval = request_irq(dev->irq, &intr_handler, SA_SHIRQ, dev->name, dev);
1114 if (retval) 1062 if (retval)
1115 return retval; 1063 return retval;
@@ -1211,7 +1159,6 @@ static int netdev_open(struct net_device *dev)
1211 1159
1212 writel(np->intr_timer_ctrl, ioaddr + IntrTimerCtrl); 1160 writel(np->intr_timer_ctrl, ioaddr + IntrTimerCtrl);
1213 1161
1214 netif_start_if(dev);
1215 netif_start_queue(dev); 1162 netif_start_queue(dev);
1216 1163
1217 if (debug > 1) 1164 if (debug > 1)
@@ -1238,13 +1185,11 @@ static int netdev_open(struct net_device *dev)
1238 writel(ETH_P_8021Q, ioaddr + VlanType); 1185 writel(ETH_P_8021Q, ioaddr + VlanType);
1239#endif /* VLAN_SUPPORT */ 1186#endif /* VLAN_SUPPORT */
1240 1187
1241#ifdef HAS_FIRMWARE
1242 /* Load Rx/Tx firmware into the frame processors */ 1188 /* Load Rx/Tx firmware into the frame processors */
1243 for (i = 0; i < FIRMWARE_RX_SIZE * 2; i++) 1189 for (i = 0; i < FIRMWARE_RX_SIZE * 2; i++)
1244 writel(firmware_rx[i], ioaddr + RxGfpMem + i * 4); 1190 writel(firmware_rx[i], ioaddr + RxGfpMem + i * 4);
1245 for (i = 0; i < FIRMWARE_TX_SIZE * 2; i++) 1191 for (i = 0; i < FIRMWARE_TX_SIZE * 2; i++)
1246 writel(firmware_tx[i], ioaddr + TxGfpMem + i * 4); 1192 writel(firmware_tx[i], ioaddr + TxGfpMem + i * 4);
1247#endif /* HAS_FIRMWARE */
1248 if (enable_hw_cksum) 1193 if (enable_hw_cksum)
1249 /* Enable the Rx and Tx units, and the Rx/Tx frame processors. */ 1194 /* Enable the Rx and Tx units, and the Rx/Tx frame processors. */
1250 writel(TxEnable|TxGFPEnable|RxEnable|RxGFPEnable, ioaddr + GenCtrl); 1195 writel(TxEnable|TxGFPEnable|RxEnable|RxGFPEnable, ioaddr + GenCtrl);
@@ -1378,8 +1323,6 @@ static int start_tx(struct sk_buff *skb, struct net_device *dev)
1378 u32 status; 1323 u32 status;
1379 int i; 1324 int i;
1380 1325
1381 kick_tx_timer(dev, tx_timeout, TX_TIMEOUT);
1382
1383 /* 1326 /*
1384 * be cautious here, wrapping the queue has weird semantics 1327 * be cautious here, wrapping the queue has weird semantics
1385 * and we may not have enough slots even when it seems we do. 1328 * and we may not have enough slots even when it seems we do.
@@ -1404,7 +1347,7 @@ static int start_tx(struct sk_buff *skb, struct net_device *dev)
1404 } 1347 }
1405 1348
1406 if (has_bad_length) 1349 if (has_bad_length)
1407 skb_checksum_help(skb); 1350 skb_checksum_help(skb, 0);
1408 } 1351 }
1409#endif /* ZEROCOPY && HAS_BROKEN_FIRMWARE */ 1352#endif /* ZEROCOPY && HAS_BROKEN_FIRMWARE */
1410 1353
@@ -1433,12 +1376,10 @@ static int start_tx(struct sk_buff *skb, struct net_device *dev)
1433 np->tx_info[entry].mapping = 1376 np->tx_info[entry].mapping =
1434 pci_map_single(np->pci_dev, skb->data, skb_first_frag_len(skb), PCI_DMA_TODEVICE); 1377 pci_map_single(np->pci_dev, skb->data, skb_first_frag_len(skb), PCI_DMA_TODEVICE);
1435 } else { 1378 } else {
1436#ifdef MAX_SKB_FRAGS
1437 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[i - 1]; 1379 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[i - 1];
1438 status |= this_frag->size; 1380 status |= this_frag->size;
1439 np->tx_info[entry].mapping = 1381 np->tx_info[entry].mapping =
1440 pci_map_single(np->pci_dev, page_address(this_frag->page) + this_frag->page_offset, this_frag->size, PCI_DMA_TODEVICE); 1382 pci_map_single(np->pci_dev, page_address(this_frag->page) + this_frag->page_offset, this_frag->size, PCI_DMA_TODEVICE);
1441#endif /* MAX_SKB_FRAGS */
1442 } 1383 }
1443 1384
1444 np->tx_ring[entry].addr = cpu_to_dma(np->tx_info[entry].mapping); 1385 np->tx_ring[entry].addr = cpu_to_dma(np->tx_info[entry].mapping);
@@ -1531,7 +1472,6 @@ static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *rgs
1531 np->tx_info[entry].mapping = 0; 1472 np->tx_info[entry].mapping = 0;
1532 np->dirty_tx += np->tx_info[entry].used_slots; 1473 np->dirty_tx += np->tx_info[entry].used_slots;
1533 entry = (entry + np->tx_info[entry].used_slots) % TX_RING_SIZE; 1474 entry = (entry + np->tx_info[entry].used_slots) % TX_RING_SIZE;
1534#ifdef MAX_SKB_FRAGS
1535 { 1475 {
1536 int i; 1476 int i;
1537 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1477 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
@@ -1543,7 +1483,7 @@ static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *rgs
1543 entry++; 1483 entry++;
1544 } 1484 }
1545 } 1485 }
1546#endif /* MAX_SKB_FRAGS */ 1486
1547 dev_kfree_skb_irq(skb); 1487 dev_kfree_skb_irq(skb);
1548 } 1488 }
1549 np->tx_done_q[np->tx_done].status = 0; 1489 np->tx_done_q[np->tx_done].status = 0;
@@ -1603,7 +1543,7 @@ static int __netdev_rx(struct net_device *dev, int *quota)
1603 if (debug > 4) 1543 if (debug > 4)
1604 printk(KERN_DEBUG " netdev_rx() status of %d was %#8.8x.\n", np->rx_done, desc_status); 1544 printk(KERN_DEBUG " netdev_rx() status of %d was %#8.8x.\n", np->rx_done, desc_status);
1605 if (!(desc_status & RxOK)) { 1545 if (!(desc_status & RxOK)) {
1606 /* There was a error. */ 1546 /* There was an error. */
1607 if (debug > 2) 1547 if (debug > 2)
1608 printk(KERN_DEBUG " netdev_rx() Rx error was %#8.8x.\n", desc_status); 1548 printk(KERN_DEBUG " netdev_rx() Rx error was %#8.8x.\n", desc_status);
1609 np->stats.rx_errors++; 1549 np->stats.rx_errors++;
@@ -1656,11 +1596,10 @@ static int __netdev_rx(struct net_device *dev, int *quota)
1656#endif 1596#endif
1657 1597
1658 skb->protocol = eth_type_trans(skb, dev); 1598 skb->protocol = eth_type_trans(skb, dev);
1659#if defined(HAS_FIRMWARE) || defined(VLAN_SUPPORT) 1599#ifdef VLAN_SUPPORT
1660 if (debug > 4) 1600 if (debug > 4)
1661 printk(KERN_DEBUG " netdev_rx() status2 of %d was %#4.4x.\n", np->rx_done, le16_to_cpu(desc->status2)); 1601 printk(KERN_DEBUG " netdev_rx() status2 of %d was %#4.4x.\n", np->rx_done, le16_to_cpu(desc->status2));
1662#endif 1602#endif
1663#ifdef HAS_FIRMWARE
1664 if (le16_to_cpu(desc->status2) & 0x0100) { 1603 if (le16_to_cpu(desc->status2) & 0x0100) {
1665 skb->ip_summed = CHECKSUM_UNNECESSARY; 1604 skb->ip_summed = CHECKSUM_UNNECESSARY;
1666 np->stats.rx_compressed++; 1605 np->stats.rx_compressed++;
@@ -1679,7 +1618,6 @@ static int __netdev_rx(struct net_device *dev, int *quota)
1679 skb->csum = le16_to_cpu(desc->csum); 1618 skb->csum = le16_to_cpu(desc->csum);
1680 printk(KERN_DEBUG "%s: checksum_hw, status2 = %#x\n", dev->name, le16_to_cpu(desc->status2)); 1619 printk(KERN_DEBUG "%s: checksum_hw, status2 = %#x\n", dev->name, le16_to_cpu(desc->status2));
1681 } 1620 }
1682#endif /* HAS_FIRMWARE */
1683#ifdef VLAN_SUPPORT 1621#ifdef VLAN_SUPPORT
1684 if (np->vlgrp && le16_to_cpu(desc->status2) & 0x0200) { 1622 if (np->vlgrp && le16_to_cpu(desc->status2) & 0x0200) {
1685 if (debug > 4) 1623 if (debug > 4)
@@ -1900,9 +1838,6 @@ static struct net_device_stats *get_stats(struct net_device *dev)
1900} 1838}
1901 1839
1902 1840
1903/* Chips may use the upper or lower CRC bits, and may reverse and/or invert
1904 them. Select the endian-ness that results in minimal calculations.
1905*/
1906static void set_rx_mode(struct net_device *dev) 1841static void set_rx_mode(struct net_device *dev)
1907{ 1842{
1908 struct netdev_private *np = netdev_priv(dev); 1843 struct netdev_private *np = netdev_priv(dev);
@@ -1969,6 +1904,8 @@ static void set_rx_mode(struct net_device *dev)
1969 memset(mc_filter, 0, sizeof(mc_filter)); 1904 memset(mc_filter, 0, sizeof(mc_filter));
1970 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; 1905 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1971 i++, mclist = mclist->next) { 1906 i++, mclist = mclist->next) {
1907 /* The chip uses the upper 9 CRC bits
1908 as index into the hash table */
1972 int bit_nr = ether_crc_le(ETH_ALEN, mclist->dmi_addr) >> 23; 1909 int bit_nr = ether_crc_le(ETH_ALEN, mclist->dmi_addr) >> 23;
1973 __u32 *fptr = (__u32 *) &mc_filter[(bit_nr >> 4) & ~1]; 1910 __u32 *fptr = (__u32 *) &mc_filter[(bit_nr >> 4) & ~1];
1974 1911
@@ -2001,7 +1938,7 @@ static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2001 struct netdev_private *np = netdev_priv(dev); 1938 struct netdev_private *np = netdev_priv(dev);
2002 strcpy(info->driver, DRV_NAME); 1939 strcpy(info->driver, DRV_NAME);
2003 strcpy(info->version, DRV_VERSION); 1940 strcpy(info->version, DRV_VERSION);
2004 strcpy(info->bus_info, PCI_SLOT_NAME(np->pci_dev)); 1941 strcpy(info->bus_info, pci_name(np->pci_dev));
2005} 1942}
2006 1943
2007static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 1944static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
@@ -2083,7 +2020,6 @@ static int netdev_close(struct net_device *dev)
2083 int i; 2020 int i;
2084 2021
2085 netif_stop_queue(dev); 2022 netif_stop_queue(dev);
2086 netif_stop_if(dev);
2087 2023
2088 if (debug > 1) { 2024 if (debug > 1) {
2089 printk(KERN_DEBUG "%s: Shutting down ethercard, Intr status %#8.8x.\n", 2025 printk(KERN_DEBUG "%s: Shutting down ethercard, Intr status %#8.8x.\n",
@@ -2184,7 +2120,13 @@ static int __init starfire_init (void)
2184/* when a module, this is printed whether or not devices are found in probe */ 2120/* when a module, this is printed whether or not devices are found in probe */
2185#ifdef MODULE 2121#ifdef MODULE
2186 printk(version); 2122 printk(version);
2123#ifdef HAVE_NETDEV_POLL
2124 printk(KERN_INFO DRV_NAME ": polling (NAPI) enabled\n");
2125#else
2126 printk(KERN_INFO DRV_NAME ": polling (NAPI) disabled\n");
2187#endif 2127#endif
2128#endif
2129
2188#ifndef ADDR_64BITS 2130#ifndef ADDR_64BITS
2189 /* we can do this test only at run-time... sigh */ 2131 /* we can do this test only at run-time... sigh */
2190 if (sizeof(dma_addr_t) == sizeof(u64)) { 2132 if (sizeof(dma_addr_t) == sizeof(u64)) {
@@ -2192,10 +2134,6 @@ static int __init starfire_init (void)
2192 return -ENODEV; 2134 return -ENODEV;
2193 } 2135 }
2194#endif /* not ADDR_64BITS */ 2136#endif /* not ADDR_64BITS */
2195#ifndef HAS_FIRMWARE
2196 /* unconditionally disable hw cksums if firmware is not present */
2197 enable_hw_cksum = 0;
2198#endif /* not HAS_FIRMWARE */
2199 return pci_module_init (&starfire_driver); 2137 return pci_module_init (&starfire_driver);
2200} 2138}
2201 2139
diff --git a/drivers/net/starfire_firmware.h b/drivers/net/starfire_firmware.h
new file mode 100644
index 000000000000..0a668528955d
--- /dev/null
+++ b/drivers/net/starfire_firmware.h
@@ -0,0 +1,346 @@
1/*
2 * Copyright 2003 Adaptec, Inc.
3 *
4 * Please read the following license before using the Adaptec Software
5 * ("Program"). If you do not agree to the license terms, do not use the
6 * Program:
7 *
8 * You agree to be bound by version 2 of the General Public License ("GPL")
9 * dated June 1991, which can be found at http://www.fsf.org/licenses/gpl.html.
10 * If the link is broken, write to Free Software Foundation, 59 Temple Place,
11 * Boston, Massachusetts 02111-1307.
12 *
13 * BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE IT IS LICENSED "AS IS" AND
14 * THERE IS NO WARRANTY FOR THE PROGRAM, INCLUDING BUT NOT LIMITED TO THE
15 * IMPLIED WARRANTIES OF MERCHANTIBILITY OR FITNESS FOR A PARTICULAR PURPOSE
16 * (TO THE EXTENT PERMITTED BY APPLICABLE LAW). USE OF THE PROGRAM IS AT YOUR
17 * OWN RISK. IN NO EVENT WILL ADAPTEC OR ITS LICENSORS BE LIABLE TO YOU FOR
18 * DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES
19 * ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM.
20 *
21 */
22
23static const u32 firmware_rx[] = {
24 0x010003dc, 0x00000000,
25 0x04000421, 0x00000086,
26 0x80000015, 0x0000180e,
27 0x81000015, 0x00006664,
28 0x1a0040ab, 0x00000b06,
29 0x14200011, 0x00000000,
30 0x14204022, 0x0000aaaa,
31 0x14204022, 0x00000300,
32 0x14204022, 0x00000000,
33 0x1a0040ab, 0x00000b14,
34 0x14200011, 0x00000000,
35 0x83000015, 0x00000002,
36 0x04000021, 0x00000000,
37 0x00000010, 0x00000000,
38 0x04000421, 0x00000087,
39 0x00000010, 0x00000000,
40 0x00000010, 0x00000000,
41 0x00008015, 0x00000000,
42 0x0000003e, 0x00000000,
43 0x00000010, 0x00000000,
44 0x82000015, 0x00004000,
45 0x009e8050, 0x00000000,
46 0x03008015, 0x00000000,
47 0x86008015, 0x00000000,
48 0x82000015, 0x00008000,
49 0x0100001c, 0x00000000,
50 0x000050a0, 0x0000010c,
51 0x4e20d011, 0x00006008,
52 0x1420d012, 0x00004008,
53 0x0000f090, 0x00007000,
54 0x0000c8b0, 0x00003000,
55 0x00004040, 0x00000000,
56 0x00108015, 0x00000000,
57 0x00a2c150, 0x00004000,
58 0x00a400b0, 0x00000014,
59 0x00000020, 0x00000000,
60 0x2500400d, 0x00002525,
61 0x00047220, 0x00003100,
62 0x00934070, 0x00000000,
63 0x00000020, 0x00000000,
64 0x00924460, 0x00000184,
65 0x2b20c011, 0x00000000,
66 0x0000c420, 0x00000540,
67 0x36014018, 0x0000422d,
68 0x14200011, 0x00000000,
69 0x00924460, 0x00000183,
70 0x3200001f, 0x00000034,
71 0x02ac0015, 0x00000002,
72 0x00a60110, 0x00000008,
73 0x42200011, 0x00000000,
74 0x00924060, 0x00000103,
75 0x0000001e, 0x00000000,
76 0x00000020, 0x00000100,
77 0x0000001e, 0x00000000,
78 0x00924460, 0x00000086,
79 0x00004080, 0x00000000,
80 0x0092c070, 0x00000000,
81 0x00924060, 0x00000100,
82 0x0000c890, 0x00005000,
83 0x00a6c110, 0x00000000,
84 0x00b0c090, 0x00000012,
85 0x021c0015, 0x00000000,
86 0x3200001f, 0x00000034,
87 0x00924460, 0x00000510,
88 0x44210011, 0x00000000,
89 0x42000011, 0x00000000,
90 0x83000015, 0x00000040,
91 0x00924460, 0x00000508,
92 0x45014018, 0x00004545,
93 0x00808050, 0x00000000,
94 0x62208012, 0x00000000,
95 0x82000015, 0x00000800,
96 0x15200011, 0x00000000,
97 0x00000010, 0x00000000,
98 0x00000010, 0x00000000,
99 0x00000010, 0x00000000,
100 0x00000010, 0x00000000,
101 0x00000010, 0x00000000,
102 0x80000015, 0x0000eea4,
103 0x81000015, 0x0000005f,
104 0x00000060, 0x00000000,
105 0x00004120, 0x00000000,
106 0x00004a00, 0x00004000,
107 0x00924460, 0x00000190,
108 0x5601401a, 0x00005956,
109 0x14000011, 0x00000000,
110 0x00934050, 0x00000018,
111 0x00930050, 0x00000018,
112 0x3601403a, 0x0000002d,
113 0x000643a9, 0x00000000,
114 0x0000c420, 0x00000140,
115 0x5601401a, 0x00005956,
116 0x14000011, 0x00000000,
117 0x00000010, 0x00000000,
118 0x00000010, 0x00000000,
119 0x000642a9, 0x00000000,
120 0x00024420, 0x00000183,
121 0x5601401a, 0x00005956,
122 0x82000015, 0x00002000,
123 0x15200011, 0x00000000,
124 0x82000015, 0x00000010,
125 0x15200011, 0x00000000,
126 0x82000015, 0x00000010,
127 0x15200011, 0x00000000,
128}; /* 104 Rx instructions */
129#define FIRMWARE_RX_SIZE 104
130
131static const u32 firmware_tx[] = {
132 0x010003dc, 0x00000000,
133 0x04000421, 0x00000086,
134 0x80000015, 0x0000180e,
135 0x81000015, 0x00006664,
136 0x1a0040ab, 0x00000b06,
137 0x14200011, 0x00000000,
138 0x14204022, 0x0000aaaa,
139 0x14204022, 0x00000300,
140 0x14204022, 0x00000000,
141 0x1a0040ab, 0x00000b14,
142 0x14200011, 0x00000000,
143 0x83000015, 0x00000002,
144 0x04000021, 0x00000000,
145 0x00000010, 0x00000000,
146 0x04000421, 0x00000087,
147 0x00000010, 0x00000000,
148 0x00000010, 0x00000000,
149 0x00008015, 0x00000000,
150 0x0000003e, 0x00000000,
151 0x00000010, 0x00000000,
152 0x82000015, 0x00004000,
153 0x009e8050, 0x00000000,
154 0x03008015, 0x00000000,
155 0x86008015, 0x00000000,
156 0x82000015, 0x00008000,
157 0x0100001c, 0x00000000,
158 0x000050a0, 0x0000010c,
159 0x4e20d011, 0x00006008,
160 0x1420d012, 0x00004008,
161 0x0000f090, 0x00007000,
162 0x0000c8b0, 0x00003000,
163 0x00004040, 0x00000000,
164 0x00108015, 0x00000000,
165 0x00a2c150, 0x00004000,
166 0x00a400b0, 0x00000014,
167 0x00000020, 0x00000000,
168 0x2500400d, 0x00002525,
169 0x00047220, 0x00003100,
170 0x00934070, 0x00000000,
171 0x00000020, 0x00000000,
172 0x00924460, 0x00000184,
173 0x2b20c011, 0x00000000,
174 0x0000c420, 0x00000540,
175 0x36014018, 0x0000422d,
176 0x14200011, 0x00000000,
177 0x00924460, 0x00000183,
178 0x3200001f, 0x00000034,
179 0x02ac0015, 0x00000002,
180 0x00a60110, 0x00000008,
181 0x42200011, 0x00000000,
182 0x00924060, 0x00000103,
183 0x0000001e, 0x00000000,
184 0x00000020, 0x00000100,
185 0x0000001e, 0x00000000,
186 0x00924460, 0x00000086,
187 0x00004080, 0x00000000,
188 0x0092c070, 0x00000000,
189 0x00924060, 0x00000100,
190 0x0000c890, 0x00005000,
191 0x00a6c110, 0x00000000,
192 0x00b0c090, 0x00000012,
193 0x021c0015, 0x00000000,
194 0x3200001f, 0x00000034,
195 0x00924460, 0x00000510,
196 0x44210011, 0x00000000,
197 0x42000011, 0x00000000,
198 0x83000015, 0x00000040,
199 0x00924460, 0x00000508,
200 0x45014018, 0x00004545,
201 0x00808050, 0x00000000,
202 0x62208012, 0x00000000,
203 0x82000015, 0x00000800,
204 0x15200011, 0x00000000,
205 0x00000010, 0x00000000,
206 0x00000010, 0x00000000,
207 0x00000010, 0x00000000,
208 0x00000010, 0x00000000,
209 0x00000010, 0x00000000,
210 0x80000015, 0x0000eea4,
211 0x81000015, 0x0000005f,
212 0x00000060, 0x00000000,
213 0x00004120, 0x00000000,
214 0x00004a00, 0x00004000,
215 0x00924460, 0x00000190,
216 0x5601401a, 0x00005956,
217 0x14000011, 0x00000000,
218 0x00934050, 0x00000018,
219 0x00930050, 0x00000018,
220 0x3601403a, 0x0000002d,
221 0x000643a9, 0x00000000,
222 0x0000c420, 0x00000140,
223 0x5601401a, 0x00005956,
224 0x14000011, 0x00000000,
225 0x00000010, 0x00000000,
226 0x00000010, 0x00000000,
227 0x000642a9, 0x00000000,
228 0x00024420, 0x00000183,
229 0x5601401a, 0x00005956,
230 0x82000015, 0x00002000,
231 0x15200011, 0x00000000,
232 0x82000015, 0x00000010,
233 0x15200011, 0x00000000,
234 0x82000015, 0x00000010,
235 0x15200011, 0x00000000,
236}; /* 104 Tx instructions */
237#define FIRMWARE_TX_SIZE 104
238#if 0
239static const u32 firmware_wol[] = {
240 0x010003dc, 0x00000000,
241 0x19000421, 0x00000087,
242 0x80000015, 0x00001a1a,
243 0x81000015, 0x00001a1a,
244 0x1a0040ab, 0x00000b06,
245 0x15200011, 0x00000000,
246 0x15204022, 0x0000aaaa,
247 0x15204022, 0x00000300,
248 0x15204022, 0x00000000,
249 0x1a0040ab, 0x00000b15,
250 0x15200011, 0x00000000,
251 0x83000015, 0x00000002,
252 0x04000021, 0x00000000,
253 0x00000010, 0x00000000,
254 0x04000421, 0x00000087,
255 0x00000010, 0x00000000,
256 0x00000010, 0x00000000,
257 0x00008015, 0x00000000,
258 0x0000003e, 0x00000000,
259 0x00000010, 0x00000000,
260 0x00000010, 0x00000000,
261 0x82000015, 0x00004000,
262 0x82000015, 0x00008000,
263 0x0000000c, 0x00000000,
264 0x00000010, 0x00000000,
265 0x00004080, 0x00000100,
266 0x1f20c011, 0x00001122,
267 0x2720f011, 0x00003011,
268 0x19200071, 0x00000000,
269 0x1a200051, 0x00000000,
270 0x00000010, 0x00000000,
271 0x00000010, 0x00000000,
272 0x1d2040a4, 0x00003344,
273 0x1d2040a2, 0x00005566,
274 0x000040a0, 0x00000100,
275 0x00108050, 0x00000001,
276 0x1a208012, 0x00000006,
277 0x82000015, 0x00008080,
278 0x010003dc, 0x00000000,
279 0x1d2040a4, 0x00002233,
280 0x1d2040a4, 0x00004455,
281 0x2d208011, 0x00000005,
282 0x1d2040a4, 0x00006611,
283 0x00108050, 0x00000001,
284 0x27200011, 0x00000000,
285 0x1d2050a4, 0x00006600,
286 0x82000015, 0x00008080,
287 0x010003dc, 0x00000000,
288 0x00000050, 0x00000000,
289 0x1b200031, 0x00000000,
290 0x0000001e, 0x00000000,
291 0x0000001e, 0x00000000,
292 0x0000001e, 0x00000000,
293 0x0000001e, 0x00000000,
294 0x00924460, 0x00000086,
295 0x00004080, 0x00000000,
296 0x0092c070, 0x00000000,
297 0x00924060, 0x00000100,
298 0x0000c890, 0x00005000,
299 0x00a6c110, 0x00000000,
300 0x00b0c090, 0x00000012,
301 0x021c0015, 0x00000000,
302 0x3200001f, 0x00000034,
303 0x00924460, 0x00000510,
304 0x44210011, 0x00000000,
305 0x42000011, 0x00000000,
306 0x83000015, 0x00000040,
307 0x00924460, 0x00000508,
308 0x476a0012, 0x00000100,
309 0x83000015, 0x00000008,
310 0x16200011, 0x00000000,
311 0x001e8050, 0x00000000,
312 0x001e8050, 0x00000000,
313 0x00808050, 0x00000000,
314 0x03008015, 0x00000000,
315 0x62208012, 0x00000000,
316 0x82000015, 0x00000800,
317 0x16200011, 0x00000000,
318 0x80000015, 0x0000eea4,
319 0x81000015, 0x0000005f,
320 0x00000020, 0x00000000,
321 0x00004120, 0x00000000,
322 0x00004a00, 0x00004000,
323 0x00924460, 0x00000190,
324 0x5c01401a, 0x0000595c,
325 0x15000011, 0x00000000,
326 0x00934050, 0x00000018,
327 0x00930050, 0x00000018,
328 0x3601403a, 0x0000002d,
329 0x00064029, 0x00000000,
330 0x0000c420, 0x00000140,
331 0x5c01401a, 0x0000595c,
332 0x15000011, 0x00000000,
333 0x00000010, 0x00000000,
334 0x00000010, 0x00000000,
335 0x00064029, 0x00000000,
336 0x00024420, 0x00000183,
337 0x5c01401a, 0x0000595c,
338 0x82000015, 0x00002000,
339 0x16200011, 0x00000000,
340 0x82000015, 0x00000010,
341 0x16200011, 0x00000000,
342 0x82000015, 0x00000010,
343 0x16200011, 0x00000000,
344}; /* 104 WoL instructions */
345#define FIRMWARE_WOL_SIZE 104
346#endif
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index f79b02e80e75..7e371b1209a1 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -7,7 +7,12 @@
7 * Copyright (C) 2005 Broadcom Corporation. 7 * Copyright (C) 2005 Broadcom Corporation.
8 * 8 *
9 * Firmware is: 9 * Firmware is:
10 * Copyright (C) 2000-2003 Broadcom Corporation. 10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
11 */ 16 */
12 17
13#include <linux/config.h> 18#include <linux/config.h>
@@ -61,8 +66,8 @@
61 66
62#define DRV_MODULE_NAME "tg3" 67#define DRV_MODULE_NAME "tg3"
63#define PFX DRV_MODULE_NAME ": " 68#define PFX DRV_MODULE_NAME ": "
64#define DRV_MODULE_VERSION "3.27" 69#define DRV_MODULE_VERSION "3.32"
65#define DRV_MODULE_RELDATE "May 5, 2005" 70#define DRV_MODULE_RELDATE "June 24, 2005"
66 71
67#define TG3_DEF_MAC_MODE 0 72#define TG3_DEF_MAC_MODE 0
68#define TG3_DEF_RX_MODE 0 73#define TG3_DEF_RX_MODE 0
@@ -133,6 +138,8 @@
133/* number of ETHTOOL_GSTATS u64's */ 138/* number of ETHTOOL_GSTATS u64's */
134#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64)) 139#define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
135 140
141#define TG3_NUM_TEST 6
142
136static char version[] __devinitdata = 143static char version[] __devinitdata =
137 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 144 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
138 145
@@ -206,6 +213,8 @@ static struct pci_device_id tg3_pci_tbl[] = {
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, 213 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
207 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752, 214 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, 215 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
216 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M,
217 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
209 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753, 218 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, 219 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
211 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M, 220 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
@@ -314,15 +323,24 @@ static struct {
314 { "nic_tx_threshold_hit" } 323 { "nic_tx_threshold_hit" }
315}; 324};
316 325
326static struct {
327 const char string[ETH_GSTRING_LEN];
328} ethtool_test_keys[TG3_NUM_TEST] = {
329 { "nvram test (online) " },
330 { "link test (online) " },
331 { "register test (offline)" },
332 { "memory test (offline)" },
333 { "loopback test (offline)" },
334 { "interrupt test (offline)" },
335};
336
317static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) 337static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
318{ 338{
319 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) { 339 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) {
320 unsigned long flags; 340 spin_lock_bh(&tp->indirect_lock);
321
322 spin_lock_irqsave(&tp->indirect_lock, flags);
323 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); 341 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
324 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); 342 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
325 spin_unlock_irqrestore(&tp->indirect_lock, flags); 343 spin_unlock_bh(&tp->indirect_lock);
326 } else { 344 } else {
327 writel(val, tp->regs + off); 345 writel(val, tp->regs + off);
328 if ((tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG) != 0) 346 if ((tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG) != 0)
@@ -333,12 +351,10 @@ static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
333static void _tw32_flush(struct tg3 *tp, u32 off, u32 val) 351static void _tw32_flush(struct tg3 *tp, u32 off, u32 val)
334{ 352{
335 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) { 353 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) != 0) {
336 unsigned long flags; 354 spin_lock_bh(&tp->indirect_lock);
337
338 spin_lock_irqsave(&tp->indirect_lock, flags);
339 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); 355 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
340 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); 356 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
341 spin_unlock_irqrestore(&tp->indirect_lock, flags); 357 spin_unlock_bh(&tp->indirect_lock);
342 } else { 358 } else {
343 void __iomem *dest = tp->regs + off; 359 void __iomem *dest = tp->regs + off;
344 writel(val, dest); 360 writel(val, dest);
@@ -378,28 +394,24 @@ static inline void _tw32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
378 394
379static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) 395static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
380{ 396{
381 unsigned long flags; 397 spin_lock_bh(&tp->indirect_lock);
382
383 spin_lock_irqsave(&tp->indirect_lock, flags);
384 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); 398 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
385 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); 399 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
386 400
387 /* Always leave this as zero. */ 401 /* Always leave this as zero. */
388 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); 402 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
389 spin_unlock_irqrestore(&tp->indirect_lock, flags); 403 spin_unlock_bh(&tp->indirect_lock);
390} 404}
391 405
392static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) 406static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
393{ 407{
394 unsigned long flags; 408 spin_lock_bh(&tp->indirect_lock);
395
396 spin_lock_irqsave(&tp->indirect_lock, flags);
397 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); 409 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
398 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); 410 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
399 411
400 /* Always leave this as zero. */ 412 /* Always leave this as zero. */
401 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); 413 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
402 spin_unlock_irqrestore(&tp->indirect_lock, flags); 414 spin_unlock_bh(&tp->indirect_lock);
403} 415}
404 416
405static void tg3_disable_ints(struct tg3 *tp) 417static void tg3_disable_ints(struct tg3 *tp)
@@ -418,11 +430,14 @@ static inline void tg3_cond_int(struct tg3 *tp)
418 430
419static void tg3_enable_ints(struct tg3 *tp) 431static void tg3_enable_ints(struct tg3 *tp)
420{ 432{
433 tp->irq_sync = 0;
434 wmb();
435
421 tw32(TG3PCI_MISC_HOST_CTRL, 436 tw32(TG3PCI_MISC_HOST_CTRL,
422 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); 437 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
423 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000000); 438 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
439 (tp->last_tag << 24));
424 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW); 440 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
425
426 tg3_cond_int(tp); 441 tg3_cond_int(tp);
427} 442}
428 443
@@ -455,16 +470,23 @@ static void tg3_restart_ints(struct tg3 *tp)
455{ 470{
456 tw32(TG3PCI_MISC_HOST_CTRL, 471 tw32(TG3PCI_MISC_HOST_CTRL,
457 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); 472 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
458 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000000); 473 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
474 tp->last_tag << 24);
459 mmiowb(); 475 mmiowb();
460 476
461 if (tg3_has_work(tp)) 477 /* When doing tagged status, this work check is unnecessary.
478 * The last_tag we write above tells the chip which piece of
479 * work we've completed.
480 */
481 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
482 tg3_has_work(tp))
462 tw32(HOSTCC_MODE, tp->coalesce_mode | 483 tw32(HOSTCC_MODE, tp->coalesce_mode |
463 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW)); 484 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
464} 485}
465 486
466static inline void tg3_netif_stop(struct tg3 *tp) 487static inline void tg3_netif_stop(struct tg3 *tp)
467{ 488{
489 tp->dev->trans_start = jiffies; /* prevent tx timeout */
468 netif_poll_disable(tp->dev); 490 netif_poll_disable(tp->dev);
469 netif_tx_disable(tp->dev); 491 netif_tx_disable(tp->dev);
470} 492}
@@ -477,7 +499,8 @@ static inline void tg3_netif_start(struct tg3 *tp)
477 * (such as after tg3_init_hw) 499 * (such as after tg3_init_hw)
478 */ 500 */
479 netif_poll_enable(tp->dev); 501 netif_poll_enable(tp->dev);
480 tg3_cond_int(tp); 502 tp->hw_status->status |= SD_STATUS_UPDATED;
503 tg3_enable_ints(tp);
481} 504}
482 505
483static void tg3_switch_clocks(struct tg3 *tp) 506static void tg3_switch_clocks(struct tg3 *tp)
@@ -2500,7 +2523,7 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2500 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { 2523 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2501 if (netif_carrier_ok(tp->dev)) { 2524 if (netif_carrier_ok(tp->dev)) {
2502 tw32(HOSTCC_STAT_COAL_TICKS, 2525 tw32(HOSTCC_STAT_COAL_TICKS,
2503 DEFAULT_STAT_COAL_TICKS); 2526 tp->coal.stats_block_coalesce_usecs);
2504 } else { 2527 } else {
2505 tw32(HOSTCC_STAT_COAL_TICKS, 0); 2528 tw32(HOSTCC_STAT_COAL_TICKS, 0);
2506 } 2529 }
@@ -2551,7 +2574,7 @@ static void tg3_tx(struct tg3 *tp)
2551 sw_idx = NEXT_TX(sw_idx); 2574 sw_idx = NEXT_TX(sw_idx);
2552 } 2575 }
2553 2576
2554 dev_kfree_skb_irq(skb); 2577 dev_kfree_skb(skb);
2555 } 2578 }
2556 2579
2557 tp->tx_cons = sw_idx; 2580 tp->tx_cons = sw_idx;
@@ -2857,11 +2880,8 @@ static int tg3_poll(struct net_device *netdev, int *budget)
2857{ 2880{
2858 struct tg3 *tp = netdev_priv(netdev); 2881 struct tg3 *tp = netdev_priv(netdev);
2859 struct tg3_hw_status *sblk = tp->hw_status; 2882 struct tg3_hw_status *sblk = tp->hw_status;
2860 unsigned long flags;
2861 int done; 2883 int done;
2862 2884
2863 spin_lock_irqsave(&tp->lock, flags);
2864
2865 /* handle link change and other phy events */ 2885 /* handle link change and other phy events */
2866 if (!(tp->tg3_flags & 2886 if (!(tp->tg3_flags &
2867 (TG3_FLAG_USE_LINKCHG_REG | 2887 (TG3_FLAG_USE_LINKCHG_REG |
@@ -2869,7 +2889,9 @@ static int tg3_poll(struct net_device *netdev, int *budget)
2869 if (sblk->status & SD_STATUS_LINK_CHG) { 2889 if (sblk->status & SD_STATUS_LINK_CHG) {
2870 sblk->status = SD_STATUS_UPDATED | 2890 sblk->status = SD_STATUS_UPDATED |
2871 (sblk->status & ~SD_STATUS_LINK_CHG); 2891 (sblk->status & ~SD_STATUS_LINK_CHG);
2892 spin_lock(&tp->lock);
2872 tg3_setup_phy(tp, 0); 2893 tg3_setup_phy(tp, 0);
2894 spin_unlock(&tp->lock);
2873 } 2895 }
2874 } 2896 }
2875 2897
@@ -2880,13 +2902,10 @@ static int tg3_poll(struct net_device *netdev, int *budget)
2880 spin_unlock(&tp->tx_lock); 2902 spin_unlock(&tp->tx_lock);
2881 } 2903 }
2882 2904
2883 spin_unlock_irqrestore(&tp->lock, flags);
2884
2885 /* run RX thread, within the bounds set by NAPI. 2905 /* run RX thread, within the bounds set by NAPI.
2886 * All RX "locking" is done by ensuring outside 2906 * All RX "locking" is done by ensuring outside
2887 * code synchronizes with dev->poll() 2907 * code synchronizes with dev->poll()
2888 */ 2908 */
2889 done = 1;
2890 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) { 2909 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
2891 int orig_budget = *budget; 2910 int orig_budget = *budget;
2892 int work_done; 2911 int work_done;
@@ -2898,22 +2917,59 @@ static int tg3_poll(struct net_device *netdev, int *budget)
2898 2917
2899 *budget -= work_done; 2918 *budget -= work_done;
2900 netdev->quota -= work_done; 2919 netdev->quota -= work_done;
2901
2902 if (work_done >= orig_budget)
2903 done = 0;
2904 } 2920 }
2905 2921
2922 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
2923 tp->last_tag = sblk->status_tag;
2924 rmb();
2925 sblk->status &= ~SD_STATUS_UPDATED;
2926
2906 /* if no more work, tell net stack and NIC we're done */ 2927 /* if no more work, tell net stack and NIC we're done */
2928 done = !tg3_has_work(tp);
2907 if (done) { 2929 if (done) {
2908 spin_lock_irqsave(&tp->lock, flags); 2930 spin_lock(&tp->lock);
2909 __netif_rx_complete(netdev); 2931 netif_rx_complete(netdev);
2910 tg3_restart_ints(tp); 2932 tg3_restart_ints(tp);
2911 spin_unlock_irqrestore(&tp->lock, flags); 2933 spin_unlock(&tp->lock);
2912 } 2934 }
2913 2935
2914 return (done ? 0 : 1); 2936 return (done ? 0 : 1);
2915} 2937}
2916 2938
2939static void tg3_irq_quiesce(struct tg3 *tp)
2940{
2941 BUG_ON(tp->irq_sync);
2942
2943 tp->irq_sync = 1;
2944 smp_mb();
2945
2946 synchronize_irq(tp->pdev->irq);
2947}
2948
2949static inline int tg3_irq_sync(struct tg3 *tp)
2950{
2951 return tp->irq_sync;
2952}
2953
2954/* Fully shutdown all tg3 driver activity elsewhere in the system.
2955 * If irq_sync is non-zero, then the IRQ handler must be synchronized
2956 * with as well. Most of the time, this is not necessary except when
2957 * shutting down the device.
2958 */
2959static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
2960{
2961 if (irq_sync)
2962 tg3_irq_quiesce(tp);
2963 spin_lock_bh(&tp->lock);
2964 spin_lock(&tp->tx_lock);
2965}
2966
2967static inline void tg3_full_unlock(struct tg3 *tp)
2968{
2969 spin_unlock(&tp->tx_lock);
2970 spin_unlock_bh(&tp->lock);
2971}
2972
2917/* MSI ISR - No need to check for interrupt sharing and no need to 2973/* MSI ISR - No need to check for interrupt sharing and no need to
2918 * flush status block and interrupt mailbox. PCI ordering rules 2974 * flush status block and interrupt mailbox. PCI ordering rules
2919 * guarantee that MSI will arrive after the status block. 2975 * guarantee that MSI will arrive after the status block.
@@ -2923,31 +2979,28 @@ static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs)
2923 struct net_device *dev = dev_id; 2979 struct net_device *dev = dev_id;
2924 struct tg3 *tp = netdev_priv(dev); 2980 struct tg3 *tp = netdev_priv(dev);
2925 struct tg3_hw_status *sblk = tp->hw_status; 2981 struct tg3_hw_status *sblk = tp->hw_status;
2926 unsigned long flags;
2927
2928 spin_lock_irqsave(&tp->lock, flags);
2929 2982
2930 /* 2983 /*
2931 * writing any value to intr-mbox-0 clears PCI INTA# and 2984 * Writing any value to intr-mbox-0 clears PCI INTA# and
2932 * chip-internal interrupt pending events. 2985 * chip-internal interrupt pending events.
2933 * writing non-zero to intr-mbox-0 additional tells the 2986 * Writing non-zero to intr-mbox-0 additional tells the
2934 * NIC to stop sending us irqs, engaging "in-intr-handler" 2987 * NIC to stop sending us irqs, engaging "in-intr-handler"
2935 * event coalescing. 2988 * event coalescing.
2936 */ 2989 */
2937 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); 2990 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
2991 tp->last_tag = sblk->status_tag;
2992 rmb();
2993 if (tg3_irq_sync(tp))
2994 goto out;
2938 sblk->status &= ~SD_STATUS_UPDATED; 2995 sblk->status &= ~SD_STATUS_UPDATED;
2939
2940 if (likely(tg3_has_work(tp))) 2996 if (likely(tg3_has_work(tp)))
2941 netif_rx_schedule(dev); /* schedule NAPI poll */ 2997 netif_rx_schedule(dev); /* schedule NAPI poll */
2942 else { 2998 else {
2943 /* no work, re-enable interrupts 2999 /* No work, re-enable interrupts. */
2944 */
2945 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 3000 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
2946 0x00000000); 3001 tp->last_tag << 24);
2947 } 3002 }
2948 3003out:
2949 spin_unlock_irqrestore(&tp->lock, flags);
2950
2951 return IRQ_RETVAL(1); 3004 return IRQ_RETVAL(1);
2952} 3005}
2953 3006
@@ -2956,10 +3009,50 @@ static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2956 struct net_device *dev = dev_id; 3009 struct net_device *dev = dev_id;
2957 struct tg3 *tp = netdev_priv(dev); 3010 struct tg3 *tp = netdev_priv(dev);
2958 struct tg3_hw_status *sblk = tp->hw_status; 3011 struct tg3_hw_status *sblk = tp->hw_status;
2959 unsigned long flags;
2960 unsigned int handled = 1; 3012 unsigned int handled = 1;
2961 3013
2962 spin_lock_irqsave(&tp->lock, flags); 3014 /* In INTx mode, it is possible for the interrupt to arrive at
3015 * the CPU before the status block posted prior to the interrupt.
3016 * Reading the PCI State register will confirm whether the
3017 * interrupt is ours and will flush the status block.
3018 */
3019 if ((sblk->status & SD_STATUS_UPDATED) ||
3020 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3021 /*
3022 * Writing any value to intr-mbox-0 clears PCI INTA# and
3023 * chip-internal interrupt pending events.
3024 * Writing non-zero to intr-mbox-0 additional tells the
3025 * NIC to stop sending us irqs, engaging "in-intr-handler"
3026 * event coalescing.
3027 */
3028 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3029 0x00000001);
3030 if (tg3_irq_sync(tp))
3031 goto out;
3032 sblk->status &= ~SD_STATUS_UPDATED;
3033 if (likely(tg3_has_work(tp)))
3034 netif_rx_schedule(dev); /* schedule NAPI poll */
3035 else {
3036 /* No work, shared interrupt perhaps? re-enable
3037 * interrupts, and flush that PCI write
3038 */
3039 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3040 0x00000000);
3041 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
3042 }
3043 } else { /* shared interrupt */
3044 handled = 0;
3045 }
3046out:
3047 return IRQ_RETVAL(handled);
3048}
3049
3050static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs *regs)
3051{
3052 struct net_device *dev = dev_id;
3053 struct tg3 *tp = netdev_priv(dev);
3054 struct tg3_hw_status *sblk = tp->hw_status;
3055 unsigned int handled = 1;
2963 3056
2964 /* In INTx mode, it is possible for the interrupt to arrive at 3057 /* In INTx mode, it is possible for the interrupt to arrive at
2965 * the CPU before the status block posted prior to the interrupt. 3058 * the CPU before the status block posted prior to the interrupt.
@@ -2977,13 +3070,11 @@ static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2977 */ 3070 */
2978 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 3071 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
2979 0x00000001); 3072 0x00000001);
2980 /* 3073 tp->last_tag = sblk->status_tag;
2981 * Flush PCI write. This also guarantees that our 3074 rmb();
2982 * status block has been flushed to host memory. 3075 if (tg3_irq_sync(tp))
2983 */ 3076 goto out;
2984 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
2985 sblk->status &= ~SD_STATUS_UPDATED; 3077 sblk->status &= ~SD_STATUS_UPDATED;
2986
2987 if (likely(tg3_has_work(tp))) 3078 if (likely(tg3_has_work(tp)))
2988 netif_rx_schedule(dev); /* schedule NAPI poll */ 3079 netif_rx_schedule(dev); /* schedule NAPI poll */
2989 else { 3080 else {
@@ -2991,15 +3082,13 @@ static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2991 * interrupts, and flush that PCI write 3082 * interrupts, and flush that PCI write
2992 */ 3083 */
2993 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 3084 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
2994 0x00000000); 3085 tp->last_tag << 24);
2995 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW); 3086 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
2996 } 3087 }
2997 } else { /* shared interrupt */ 3088 } else { /* shared interrupt */
2998 handled = 0; 3089 handled = 0;
2999 } 3090 }
3000 3091out:
3001 spin_unlock_irqrestore(&tp->lock, flags);
3002
3003 return IRQ_RETVAL(handled); 3092 return IRQ_RETVAL(handled);
3004} 3093}
3005 3094
@@ -3020,7 +3109,7 @@ static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3020} 3109}
3021 3110
3022static int tg3_init_hw(struct tg3 *); 3111static int tg3_init_hw(struct tg3 *);
3023static int tg3_halt(struct tg3 *, int); 3112static int tg3_halt(struct tg3 *, int, int);
3024 3113
3025#ifdef CONFIG_NET_POLL_CONTROLLER 3114#ifdef CONFIG_NET_POLL_CONTROLLER
3026static void tg3_poll_controller(struct net_device *dev) 3115static void tg3_poll_controller(struct net_device *dev)
@@ -3038,19 +3127,17 @@ static void tg3_reset_task(void *_data)
3038 3127
3039 tg3_netif_stop(tp); 3128 tg3_netif_stop(tp);
3040 3129
3041 spin_lock_irq(&tp->lock); 3130 tg3_full_lock(tp, 1);
3042 spin_lock(&tp->tx_lock);
3043 3131
3044 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER; 3132 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3045 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER; 3133 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3046 3134
3047 tg3_halt(tp, 0); 3135 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3048 tg3_init_hw(tp); 3136 tg3_init_hw(tp);
3049 3137
3050 tg3_netif_start(tp); 3138 tg3_netif_start(tp);
3051 3139
3052 spin_unlock(&tp->tx_lock); 3140 tg3_full_unlock(tp);
3053 spin_unlock_irq(&tp->lock);
3054 3141
3055 if (restart_timer) 3142 if (restart_timer)
3056 mod_timer(&tp->timer, jiffies + 1); 3143 mod_timer(&tp->timer, jiffies + 1);
@@ -3156,39 +3243,21 @@ static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3156 unsigned int i; 3243 unsigned int i;
3157 u32 len, entry, base_flags, mss; 3244 u32 len, entry, base_flags, mss;
3158 int would_hit_hwbug; 3245 int would_hit_hwbug;
3159 unsigned long flags;
3160 3246
3161 len = skb_headlen(skb); 3247 len = skb_headlen(skb);
3162 3248
3163 /* No BH disabling for tx_lock here. We are running in BH disabled 3249 /* No BH disabling for tx_lock here. We are running in BH disabled
3164 * context and TX reclaim runs via tp->poll inside of a software 3250 * context and TX reclaim runs via tp->poll inside of a software
3165 * interrupt. Rejoice! 3251 * interrupt. Furthermore, IRQ processing runs lockless so we have
3166 * 3252 * no IRQ context deadlocks to worry about either. Rejoice!
3167 * Actually, things are not so simple. If we are to take a hw
3168 * IRQ here, we can deadlock, consider:
3169 *
3170 * CPU1 CPU2
3171 * tg3_start_xmit
3172 * take tp->tx_lock
3173 * tg3_timer
3174 * take tp->lock
3175 * tg3_interrupt
3176 * spin on tp->lock
3177 * spin on tp->tx_lock
3178 *
3179 * So we really do need to disable interrupts when taking
3180 * tx_lock here.
3181 */ 3253 */
3182 local_irq_save(flags); 3254 if (!spin_trylock(&tp->tx_lock))
3183 if (!spin_trylock(&tp->tx_lock)) {
3184 local_irq_restore(flags);
3185 return NETDEV_TX_LOCKED; 3255 return NETDEV_TX_LOCKED;
3186 }
3187 3256
3188 /* This is a hard error, log it. */ 3257 /* This is a hard error, log it. */
3189 if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) { 3258 if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3190 netif_stop_queue(dev); 3259 netif_stop_queue(dev);
3191 spin_unlock_irqrestore(&tp->tx_lock, flags); 3260 spin_unlock(&tp->tx_lock);
3192 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n", 3261 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
3193 dev->name); 3262 dev->name);
3194 return NETDEV_TX_BUSY; 3263 return NETDEV_TX_BUSY;
@@ -3353,7 +3422,7 @@ static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3353 3422
3354out_unlock: 3423out_unlock:
3355 mmiowb(); 3424 mmiowb();
3356 spin_unlock_irqrestore(&tp->tx_lock, flags); 3425 spin_unlock(&tp->tx_lock);
3357 3426
3358 dev->trans_start = jiffies; 3427 dev->trans_start = jiffies;
3359 3428
@@ -3387,10 +3456,10 @@ static int tg3_change_mtu(struct net_device *dev, int new_mtu)
3387 } 3456 }
3388 3457
3389 tg3_netif_stop(tp); 3458 tg3_netif_stop(tp);
3390 spin_lock_irq(&tp->lock);
3391 spin_lock(&tp->tx_lock);
3392 3459
3393 tg3_halt(tp, 1); 3460 tg3_full_lock(tp, 1);
3461
3462 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3394 3463
3395 tg3_set_mtu(dev, tp, new_mtu); 3464 tg3_set_mtu(dev, tp, new_mtu);
3396 3465
@@ -3398,8 +3467,7 @@ static int tg3_change_mtu(struct net_device *dev, int new_mtu)
3398 3467
3399 tg3_netif_start(tp); 3468 tg3_netif_start(tp);
3400 3469
3401 spin_unlock(&tp->tx_lock); 3470 tg3_full_unlock(tp);
3402 spin_unlock_irq(&tp->lock);
3403 3471
3404 return 0; 3472 return 0;
3405} 3473}
@@ -4081,19 +4149,19 @@ static void tg3_stop_fw(struct tg3 *tp)
4081} 4149}
4082 4150
4083/* tp->lock is held. */ 4151/* tp->lock is held. */
4084static int tg3_halt(struct tg3 *tp, int silent) 4152static int tg3_halt(struct tg3 *tp, int kind, int silent)
4085{ 4153{
4086 int err; 4154 int err;
4087 4155
4088 tg3_stop_fw(tp); 4156 tg3_stop_fw(tp);
4089 4157
4090 tg3_write_sig_pre_reset(tp, RESET_KIND_SHUTDOWN); 4158 tg3_write_sig_pre_reset(tp, kind);
4091 4159
4092 tg3_abort_hw(tp, silent); 4160 tg3_abort_hw(tp, silent);
4093 err = tg3_chip_reset(tp); 4161 err = tg3_chip_reset(tp);
4094 4162
4095 tg3_write_sig_legacy(tp, RESET_KIND_SHUTDOWN); 4163 tg3_write_sig_legacy(tp, kind);
4096 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); 4164 tg3_write_sig_post_reset(tp, kind);
4097 4165
4098 if (err) 4166 if (err)
4099 return err; 4167 return err;
@@ -4307,7 +4375,12 @@ static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_b
4307 */ 4375 */
4308 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG; 4376 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
4309 4377
4378 /* It is possible that bootcode is still loading at this point.
4379 * Get the nvram lock first before halting the cpu.
4380 */
4381 tg3_nvram_lock(tp);
4310 err = tg3_halt_cpu(tp, cpu_base); 4382 err = tg3_halt_cpu(tp, cpu_base);
4383 tg3_nvram_unlock(tp);
4311 if (err) 4384 if (err)
4312 goto out; 4385 goto out;
4313 4386
@@ -5015,9 +5088,9 @@ static int tg3_set_mac_addr(struct net_device *dev, void *p)
5015 5088
5016 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 5089 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5017 5090
5018 spin_lock_irq(&tp->lock); 5091 spin_lock_bh(&tp->lock);
5019 __tg3_set_mac_addr(tp); 5092 __tg3_set_mac_addr(tp);
5020 spin_unlock_irq(&tp->lock); 5093 spin_unlock_bh(&tp->lock);
5021 5094
5022 return 0; 5095 return 0;
5023} 5096}
@@ -5044,6 +5117,27 @@ static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5044} 5117}
5045 5118
5046static void __tg3_set_rx_mode(struct net_device *); 5119static void __tg3_set_rx_mode(struct net_device *);
5120static void tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
5121{
5122 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5123 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5124 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5125 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5126 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5127 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5128 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5129 }
5130 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5131 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5132 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5133 u32 val = ec->stats_block_coalesce_usecs;
5134
5135 if (!netif_carrier_ok(tp->dev))
5136 val = 0;
5137
5138 tw32(HOSTCC_STAT_COAL_TICKS, val);
5139 }
5140}
5047 5141
5048/* tp->lock is held. */ 5142/* tp->lock is held. */
5049static int tg3_reset_hw(struct tg3 *tp) 5143static int tg3_reset_hw(struct tg3 *tp)
@@ -5366,16 +5460,7 @@ static int tg3_reset_hw(struct tg3 *tp)
5366 udelay(10); 5460 udelay(10);
5367 } 5461 }
5368 5462
5369 tw32(HOSTCC_RXCOL_TICKS, 0); 5463 tg3_set_coalesce(tp, &tp->coal);
5370 tw32(HOSTCC_TXCOL_TICKS, LOW_TXCOL_TICKS);
5371 tw32(HOSTCC_RXMAX_FRAMES, 1);
5372 tw32(HOSTCC_TXMAX_FRAMES, LOW_RXMAX_FRAMES);
5373 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5374 tw32(HOSTCC_RXCOAL_TICK_INT, 0);
5375 tw32(HOSTCC_TXCOAL_TICK_INT, 0);
5376 }
5377 tw32(HOSTCC_RXCOAL_MAXF_INT, 1);
5378 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
5379 5464
5380 /* set status block DMA address */ 5465 /* set status block DMA address */
5381 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, 5466 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
@@ -5388,8 +5473,6 @@ static int tg3_reset_hw(struct tg3 *tp)
5388 * the tg3_periodic_fetch_stats call there, and 5473 * the tg3_periodic_fetch_stats call there, and
5389 * tg3_get_stats to see how this works for 5705/5750 chips. 5474 * tg3_get_stats to see how this works for 5705/5750 chips.
5390 */ 5475 */
5391 tw32(HOSTCC_STAT_COAL_TICKS,
5392 DEFAULT_STAT_COAL_TICKS);
5393 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, 5476 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5394 ((u64) tp->stats_mapping >> 32)); 5477 ((u64) tp->stats_mapping >> 32));
5395 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, 5478 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
@@ -5445,7 +5528,8 @@ static int tg3_reset_hw(struct tg3 *tp)
5445 udelay(100); 5528 udelay(100);
5446 5529
5447 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0); 5530 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
5448 tr32(MAILBOX_INTERRUPT_0); 5531 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
5532 tp->last_tag = 0;
5449 5533
5450 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { 5534 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5451 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE); 5535 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
@@ -5643,9 +5727,6 @@ static int tg3_reset_hw(struct tg3 *tp)
5643 5727
5644 tg3_write_sig_post_reset(tp, RESET_KIND_INIT); 5728 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
5645 5729
5646 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
5647 tg3_enable_ints(tp);
5648
5649 return 0; 5730 return 0;
5650} 5731}
5651 5732
@@ -5718,36 +5799,35 @@ static void tg3_periodic_fetch_stats(struct tg3 *tp)
5718static void tg3_timer(unsigned long __opaque) 5799static void tg3_timer(unsigned long __opaque)
5719{ 5800{
5720 struct tg3 *tp = (struct tg3 *) __opaque; 5801 struct tg3 *tp = (struct tg3 *) __opaque;
5721 unsigned long flags;
5722 5802
5723 spin_lock_irqsave(&tp->lock, flags); 5803 spin_lock(&tp->lock);
5724 spin_lock(&tp->tx_lock);
5725 5804
5726 /* All of this garbage is because when using non-tagged 5805 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
5727 * IRQ status the mailbox/status_block protocol the chip 5806 /* All of this garbage is because when using non-tagged
5728 * uses with the cpu is race prone. 5807 * IRQ status the mailbox/status_block protocol the chip
5729 */ 5808 * uses with the cpu is race prone.
5730 if (tp->hw_status->status & SD_STATUS_UPDATED) { 5809 */
5731 tw32(GRC_LOCAL_CTRL, 5810 if (tp->hw_status->status & SD_STATUS_UPDATED) {
5732 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); 5811 tw32(GRC_LOCAL_CTRL,
5733 } else { 5812 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
5734 tw32(HOSTCC_MODE, tp->coalesce_mode | 5813 } else {
5735 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW)); 5814 tw32(HOSTCC_MODE, tp->coalesce_mode |
5736 } 5815 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
5816 }
5737 5817
5738 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { 5818 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
5739 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER; 5819 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
5740 spin_unlock(&tp->tx_lock); 5820 spin_unlock(&tp->lock);
5741 spin_unlock_irqrestore(&tp->lock, flags); 5821 schedule_work(&tp->reset_task);
5742 schedule_work(&tp->reset_task); 5822 return;
5743 return; 5823 }
5744 } 5824 }
5745 5825
5746 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5747 tg3_periodic_fetch_stats(tp);
5748
5749 /* This part only runs once per second. */ 5826 /* This part only runs once per second. */
5750 if (!--tp->timer_counter) { 5827 if (!--tp->timer_counter) {
5828 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5829 tg3_periodic_fetch_stats(tp);
5830
5751 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) { 5831 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
5752 u32 mac_stat; 5832 u32 mac_stat;
5753 int phy_event; 5833 int phy_event;
@@ -5805,8 +5885,7 @@ static void tg3_timer(unsigned long __opaque)
5805 tp->asf_counter = tp->asf_multiplier; 5885 tp->asf_counter = tp->asf_multiplier;
5806 } 5886 }
5807 5887
5808 spin_unlock(&tp->tx_lock); 5888 spin_unlock(&tp->lock);
5809 spin_unlock_irqrestore(&tp->lock, flags);
5810 5889
5811 tp->timer.expires = jiffies + tp->timer_offset; 5890 tp->timer.expires = jiffies + tp->timer_offset;
5812 add_timer(&tp->timer); 5891 add_timer(&tp->timer);
@@ -5818,6 +5897,9 @@ static int tg3_test_interrupt(struct tg3 *tp)
5818 int err, i; 5897 int err, i;
5819 u32 int_mbox = 0; 5898 u32 int_mbox = 0;
5820 5899
5900 if (!netif_running(dev))
5901 return -ENODEV;
5902
5821 tg3_disable_ints(tp); 5903 tg3_disable_ints(tp);
5822 5904
5823 free_irq(tp->pdev->irq, dev); 5905 free_irq(tp->pdev->irq, dev);
@@ -5846,9 +5928,13 @@ static int tg3_test_interrupt(struct tg3 *tp)
5846 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) 5928 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
5847 err = request_irq(tp->pdev->irq, tg3_msi, 5929 err = request_irq(tp->pdev->irq, tg3_msi,
5848 SA_SAMPLE_RANDOM, dev->name, dev); 5930 SA_SAMPLE_RANDOM, dev->name, dev);
5849 else 5931 else {
5850 err = request_irq(tp->pdev->irq, tg3_interrupt, 5932 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
5933 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
5934 fn = tg3_interrupt_tagged;
5935 err = request_irq(tp->pdev->irq, fn,
5851 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev); 5936 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
5937 }
5852 5938
5853 if (err) 5939 if (err)
5854 return err; 5940 return err;
@@ -5900,23 +5986,26 @@ static int tg3_test_msi(struct tg3 *tp)
5900 5986
5901 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI; 5987 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
5902 5988
5903 err = request_irq(tp->pdev->irq, tg3_interrupt, 5989 {
5904 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev); 5990 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
5991 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
5992 fn = tg3_interrupt_tagged;
5905 5993
5994 err = request_irq(tp->pdev->irq, fn,
5995 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
5996 }
5906 if (err) 5997 if (err)
5907 return err; 5998 return err;
5908 5999
5909 /* Need to reset the chip because the MSI cycle may have terminated 6000 /* Need to reset the chip because the MSI cycle may have terminated
5910 * with Master Abort. 6001 * with Master Abort.
5911 */ 6002 */
5912 spin_lock_irq(&tp->lock); 6003 tg3_full_lock(tp, 1);
5913 spin_lock(&tp->tx_lock);
5914 6004
5915 tg3_halt(tp, 1); 6005 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5916 err = tg3_init_hw(tp); 6006 err = tg3_init_hw(tp);
5917 6007
5918 spin_unlock(&tp->tx_lock); 6008 tg3_full_unlock(tp);
5919 spin_unlock_irq(&tp->lock);
5920 6009
5921 if (err) 6010 if (err)
5922 free_irq(tp->pdev->irq, dev); 6011 free_irq(tp->pdev->irq, dev);
@@ -5929,14 +6018,12 @@ static int tg3_open(struct net_device *dev)
5929 struct tg3 *tp = netdev_priv(dev); 6018 struct tg3 *tp = netdev_priv(dev);
5930 int err; 6019 int err;
5931 6020
5932 spin_lock_irq(&tp->lock); 6021 tg3_full_lock(tp, 0);
5933 spin_lock(&tp->tx_lock);
5934 6022
5935 tg3_disable_ints(tp); 6023 tg3_disable_ints(tp);
5936 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; 6024 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
5937 6025
5938 spin_unlock(&tp->tx_lock); 6026 tg3_full_unlock(tp);
5939 spin_unlock_irq(&tp->lock);
5940 6027
5941 /* The placement of this call is tied 6028 /* The placement of this call is tied
5942 * to the setup and use of Host TX descriptors. 6029 * to the setup and use of Host TX descriptors.
@@ -5948,7 +6035,13 @@ static int tg3_open(struct net_device *dev)
5948 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && 6035 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5949 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) && 6036 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
5950 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX)) { 6037 (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX)) {
5951 if (pci_enable_msi(tp->pdev) == 0) { 6038 /* All MSI supporting chips should support tagged
6039 * status. Assert that this is the case.
6040 */
6041 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6042 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
6043 "Not using MSI.\n", tp->dev->name);
6044 } else if (pci_enable_msi(tp->pdev) == 0) {
5952 u32 msi_mode; 6045 u32 msi_mode;
5953 6046
5954 msi_mode = tr32(MSGINT_MODE); 6047 msi_mode = tr32(MSGINT_MODE);
@@ -5959,9 +6052,14 @@ static int tg3_open(struct net_device *dev)
5959 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) 6052 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
5960 err = request_irq(tp->pdev->irq, tg3_msi, 6053 err = request_irq(tp->pdev->irq, tg3_msi,
5961 SA_SAMPLE_RANDOM, dev->name, dev); 6054 SA_SAMPLE_RANDOM, dev->name, dev);
5962 else 6055 else {
5963 err = request_irq(tp->pdev->irq, tg3_interrupt, 6056 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6057 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6058 fn = tg3_interrupt_tagged;
6059
6060 err = request_irq(tp->pdev->irq, fn,
5964 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev); 6061 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6062 }
5965 6063
5966 if (err) { 6064 if (err) {
5967 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { 6065 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
@@ -5972,17 +6070,23 @@ static int tg3_open(struct net_device *dev)
5972 return err; 6070 return err;
5973 } 6071 }
5974 6072
5975 spin_lock_irq(&tp->lock); 6073 tg3_full_lock(tp, 0);
5976 spin_lock(&tp->tx_lock);
5977 6074
5978 err = tg3_init_hw(tp); 6075 err = tg3_init_hw(tp);
5979 if (err) { 6076 if (err) {
5980 tg3_halt(tp, 1); 6077 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5981 tg3_free_rings(tp); 6078 tg3_free_rings(tp);
5982 } else { 6079 } else {
5983 tp->timer_offset = HZ / 10; 6080 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
5984 tp->timer_counter = tp->timer_multiplier = 10; 6081 tp->timer_offset = HZ;
5985 tp->asf_counter = tp->asf_multiplier = (10 * 120); 6082 else
6083 tp->timer_offset = HZ / 10;
6084
6085 BUG_ON(tp->timer_offset > HZ);
6086 tp->timer_counter = tp->timer_multiplier =
6087 (HZ / tp->timer_offset);
6088 tp->asf_counter = tp->asf_multiplier =
6089 ((HZ / tp->timer_offset) * 120);
5986 6090
5987 init_timer(&tp->timer); 6091 init_timer(&tp->timer);
5988 tp->timer.expires = jiffies + tp->timer_offset; 6092 tp->timer.expires = jiffies + tp->timer_offset;
@@ -5990,8 +6094,7 @@ static int tg3_open(struct net_device *dev)
5990 tp->timer.function = tg3_timer; 6094 tp->timer.function = tg3_timer;
5991 } 6095 }
5992 6096
5993 spin_unlock(&tp->tx_lock); 6097 tg3_full_unlock(tp);
5994 spin_unlock_irq(&tp->lock);
5995 6098
5996 if (err) { 6099 if (err) {
5997 free_irq(tp->pdev->irq, dev); 6100 free_irq(tp->pdev->irq, dev);
@@ -6005,34 +6108,31 @@ static int tg3_open(struct net_device *dev)
6005 6108
6006 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { 6109 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6007 err = tg3_test_msi(tp); 6110 err = tg3_test_msi(tp);
6111
6008 if (err) { 6112 if (err) {
6009 spin_lock_irq(&tp->lock); 6113 tg3_full_lock(tp, 0);
6010 spin_lock(&tp->tx_lock);
6011 6114
6012 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { 6115 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6013 pci_disable_msi(tp->pdev); 6116 pci_disable_msi(tp->pdev);
6014 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI; 6117 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6015 } 6118 }
6016 tg3_halt(tp, 1); 6119 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6017 tg3_free_rings(tp); 6120 tg3_free_rings(tp);
6018 tg3_free_consistent(tp); 6121 tg3_free_consistent(tp);
6019 6122
6020 spin_unlock(&tp->tx_lock); 6123 tg3_full_unlock(tp);
6021 spin_unlock_irq(&tp->lock);
6022 6124
6023 return err; 6125 return err;
6024 } 6126 }
6025 } 6127 }
6026 6128
6027 spin_lock_irq(&tp->lock); 6129 tg3_full_lock(tp, 0);
6028 spin_lock(&tp->tx_lock);
6029 6130
6030 add_timer(&tp->timer); 6131 add_timer(&tp->timer);
6031 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; 6132 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
6032 tg3_enable_ints(tp); 6133 tg3_enable_ints(tp);
6033 6134
6034 spin_unlock(&tp->tx_lock); 6135 tg3_full_unlock(tp);
6035 spin_unlock_irq(&tp->lock);
6036 6136
6037 netif_start_queue(dev); 6137 netif_start_queue(dev);
6038 6138
@@ -6278,23 +6378,21 @@ static int tg3_close(struct net_device *dev)
6278 6378
6279 del_timer_sync(&tp->timer); 6379 del_timer_sync(&tp->timer);
6280 6380
6281 spin_lock_irq(&tp->lock); 6381 tg3_full_lock(tp, 1);
6282 spin_lock(&tp->tx_lock);
6283#if 0 6382#if 0
6284 tg3_dump_state(tp); 6383 tg3_dump_state(tp);
6285#endif 6384#endif
6286 6385
6287 tg3_disable_ints(tp); 6386 tg3_disable_ints(tp);
6288 6387
6289 tg3_halt(tp, 1); 6388 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6290 tg3_free_rings(tp); 6389 tg3_free_rings(tp);
6291 tp->tg3_flags &= 6390 tp->tg3_flags &=
6292 ~(TG3_FLAG_INIT_COMPLETE | 6391 ~(TG3_FLAG_INIT_COMPLETE |
6293 TG3_FLAG_GOT_SERDES_FLOWCTL); 6392 TG3_FLAG_GOT_SERDES_FLOWCTL);
6294 netif_carrier_off(tp->dev); 6393 netif_carrier_off(tp->dev);
6295 6394
6296 spin_unlock(&tp->tx_lock); 6395 tg3_full_unlock(tp);
6297 spin_unlock_irq(&tp->lock);
6298 6396
6299 free_irq(tp->pdev->irq, dev); 6397 free_irq(tp->pdev->irq, dev);
6300 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { 6398 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
@@ -6331,16 +6429,15 @@ static unsigned long calc_crc_errors(struct tg3 *tp)
6331 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && 6429 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6332 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || 6430 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
6333 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { 6431 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
6334 unsigned long flags;
6335 u32 val; 6432 u32 val;
6336 6433
6337 spin_lock_irqsave(&tp->lock, flags); 6434 spin_lock_bh(&tp->lock);
6338 if (!tg3_readphy(tp, 0x1e, &val)) { 6435 if (!tg3_readphy(tp, 0x1e, &val)) {
6339 tg3_writephy(tp, 0x1e, val | 0x8000); 6436 tg3_writephy(tp, 0x1e, val | 0x8000);
6340 tg3_readphy(tp, 0x14, &val); 6437 tg3_readphy(tp, 0x14, &val);
6341 } else 6438 } else
6342 val = 0; 6439 val = 0;
6343 spin_unlock_irqrestore(&tp->lock, flags); 6440 spin_unlock_bh(&tp->lock);
6344 6441
6345 tp->phy_crc_errors += val; 6442 tp->phy_crc_errors += val;
6346 6443
@@ -6602,11 +6699,9 @@ static void tg3_set_rx_mode(struct net_device *dev)
6602{ 6699{
6603 struct tg3 *tp = netdev_priv(dev); 6700 struct tg3 *tp = netdev_priv(dev);
6604 6701
6605 spin_lock_irq(&tp->lock); 6702 tg3_full_lock(tp, 0);
6606 spin_lock(&tp->tx_lock);
6607 __tg3_set_rx_mode(dev); 6703 __tg3_set_rx_mode(dev);
6608 spin_unlock(&tp->tx_lock); 6704 tg3_full_unlock(tp);
6609 spin_unlock_irq(&tp->lock);
6610} 6705}
6611 6706
6612#define TG3_REGDUMP_LEN (32 * 1024) 6707#define TG3_REGDUMP_LEN (32 * 1024)
@@ -6628,8 +6723,7 @@ static void tg3_get_regs(struct net_device *dev,
6628 6723
6629 memset(p, 0, TG3_REGDUMP_LEN); 6724 memset(p, 0, TG3_REGDUMP_LEN);
6630 6725
6631 spin_lock_irq(&tp->lock); 6726 tg3_full_lock(tp, 0);
6632 spin_lock(&tp->tx_lock);
6633 6727
6634#define __GET_REG32(reg) (*(p)++ = tr32(reg)) 6728#define __GET_REG32(reg) (*(p)++ = tr32(reg))
6635#define GET_REG32_LOOP(base,len) \ 6729#define GET_REG32_LOOP(base,len) \
@@ -6679,8 +6773,7 @@ do { p = (u32 *)(orig_p + (reg)); \
6679#undef GET_REG32_LOOP 6773#undef GET_REG32_LOOP
6680#undef GET_REG32_1 6774#undef GET_REG32_1
6681 6775
6682 spin_unlock(&tp->tx_lock); 6776 tg3_full_unlock(tp);
6683 spin_unlock_irq(&tp->lock);
6684} 6777}
6685 6778
6686static int tg3_get_eeprom_len(struct net_device *dev) 6779static int tg3_get_eeprom_len(struct net_device *dev)
@@ -6856,8 +6949,7 @@ static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6856 return -EINVAL; 6949 return -EINVAL;
6857 } 6950 }
6858 6951
6859 spin_lock_irq(&tp->lock); 6952 tg3_full_lock(tp, 0);
6860 spin_lock(&tp->tx_lock);
6861 6953
6862 tp->link_config.autoneg = cmd->autoneg; 6954 tp->link_config.autoneg = cmd->autoneg;
6863 if (cmd->autoneg == AUTONEG_ENABLE) { 6955 if (cmd->autoneg == AUTONEG_ENABLE) {
@@ -6873,8 +6965,7 @@ static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6873 if (netif_running(dev)) 6965 if (netif_running(dev))
6874 tg3_setup_phy(tp, 1); 6966 tg3_setup_phy(tp, 1);
6875 6967
6876 spin_unlock(&tp->tx_lock); 6968 tg3_full_unlock(tp);
6877 spin_unlock_irq(&tp->lock);
6878 6969
6879 return 0; 6970 return 0;
6880} 6971}
@@ -6910,12 +7001,12 @@ static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6910 !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP)) 7001 !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
6911 return -EINVAL; 7002 return -EINVAL;
6912 7003
6913 spin_lock_irq(&tp->lock); 7004 spin_lock_bh(&tp->lock);
6914 if (wol->wolopts & WAKE_MAGIC) 7005 if (wol->wolopts & WAKE_MAGIC)
6915 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; 7006 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
6916 else 7007 else
6917 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE; 7008 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
6918 spin_unlock_irq(&tp->lock); 7009 spin_unlock_bh(&tp->lock);
6919 7010
6920 return 0; 7011 return 0;
6921} 7012}
@@ -6955,7 +7046,7 @@ static int tg3_nway_reset(struct net_device *dev)
6955 if (!netif_running(dev)) 7046 if (!netif_running(dev))
6956 return -EAGAIN; 7047 return -EAGAIN;
6957 7048
6958 spin_lock_irq(&tp->lock); 7049 spin_lock_bh(&tp->lock);
6959 r = -EINVAL; 7050 r = -EINVAL;
6960 tg3_readphy(tp, MII_BMCR, &bmcr); 7051 tg3_readphy(tp, MII_BMCR, &bmcr);
6961 if (!tg3_readphy(tp, MII_BMCR, &bmcr) && 7052 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
@@ -6963,7 +7054,7 @@ static int tg3_nway_reset(struct net_device *dev)
6963 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART); 7054 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART);
6964 r = 0; 7055 r = 0;
6965 } 7056 }
6966 spin_unlock_irq(&tp->lock); 7057 spin_unlock_bh(&tp->lock);
6967 7058
6968 return r; 7059 return r;
6969} 7060}
@@ -6985,17 +7076,19 @@ static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *
6985static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) 7076static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6986{ 7077{
6987 struct tg3 *tp = netdev_priv(dev); 7078 struct tg3 *tp = netdev_priv(dev);
7079 int irq_sync = 0;
6988 7080
6989 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) || 7081 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
6990 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) || 7082 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
6991 (ering->tx_pending > TG3_TX_RING_SIZE - 1)) 7083 (ering->tx_pending > TG3_TX_RING_SIZE - 1))
6992 return -EINVAL; 7084 return -EINVAL;
6993 7085
6994 if (netif_running(dev)) 7086 if (netif_running(dev)) {
6995 tg3_netif_stop(tp); 7087 tg3_netif_stop(tp);
7088 irq_sync = 1;
7089 }
6996 7090
6997 spin_lock_irq(&tp->lock); 7091 tg3_full_lock(tp, irq_sync);
6998 spin_lock(&tp->tx_lock);
6999 7092
7000 tp->rx_pending = ering->rx_pending; 7093 tp->rx_pending = ering->rx_pending;
7001 7094
@@ -7006,13 +7099,12 @@ static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *e
7006 tp->tx_pending = ering->tx_pending; 7099 tp->tx_pending = ering->tx_pending;
7007 7100
7008 if (netif_running(dev)) { 7101 if (netif_running(dev)) {
7009 tg3_halt(tp, 1); 7102 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7010 tg3_init_hw(tp); 7103 tg3_init_hw(tp);
7011 tg3_netif_start(tp); 7104 tg3_netif_start(tp);
7012 } 7105 }
7013 7106
7014 spin_unlock(&tp->tx_lock); 7107 tg3_full_unlock(tp);
7015 spin_unlock_irq(&tp->lock);
7016 7108
7017 return 0; 7109 return 0;
7018} 7110}
@@ -7029,12 +7121,15 @@ static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam
7029static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) 7121static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7030{ 7122{
7031 struct tg3 *tp = netdev_priv(dev); 7123 struct tg3 *tp = netdev_priv(dev);
7124 int irq_sync = 0;
7032 7125
7033 if (netif_running(dev)) 7126 if (netif_running(dev)) {
7034 tg3_netif_stop(tp); 7127 tg3_netif_stop(tp);
7128 irq_sync = 1;
7129 }
7130
7131 tg3_full_lock(tp, irq_sync);
7035 7132
7036 spin_lock_irq(&tp->lock);
7037 spin_lock(&tp->tx_lock);
7038 if (epause->autoneg) 7133 if (epause->autoneg)
7039 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; 7134 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
7040 else 7135 else
@@ -7049,12 +7144,12 @@ static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam
7049 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE; 7144 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
7050 7145
7051 if (netif_running(dev)) { 7146 if (netif_running(dev)) {
7052 tg3_halt(tp, 1); 7147 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7053 tg3_init_hw(tp); 7148 tg3_init_hw(tp);
7054 tg3_netif_start(tp); 7149 tg3_netif_start(tp);
7055 } 7150 }
7056 spin_unlock(&tp->tx_lock); 7151
7057 spin_unlock_irq(&tp->lock); 7152 tg3_full_unlock(tp);
7058 7153
7059 return 0; 7154 return 0;
7060} 7155}
@@ -7075,12 +7170,12 @@ static int tg3_set_rx_csum(struct net_device *dev, u32 data)
7075 return 0; 7170 return 0;
7076 } 7171 }
7077 7172
7078 spin_lock_irq(&tp->lock); 7173 spin_lock_bh(&tp->lock);
7079 if (data) 7174 if (data)
7080 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS; 7175 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
7081 else 7176 else
7082 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS; 7177 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
7083 spin_unlock_irq(&tp->lock); 7178 spin_unlock_bh(&tp->lock);
7084 7179
7085 return 0; 7180 return 0;
7086} 7181}
@@ -7108,12 +7203,20 @@ static int tg3_get_stats_count (struct net_device *dev)
7108 return TG3_NUM_STATS; 7203 return TG3_NUM_STATS;
7109} 7204}
7110 7205
7206static int tg3_get_test_count (struct net_device *dev)
7207{
7208 return TG3_NUM_TEST;
7209}
7210
7111static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf) 7211static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
7112{ 7212{
7113 switch (stringset) { 7213 switch (stringset) {
7114 case ETH_SS_STATS: 7214 case ETH_SS_STATS:
7115 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys)); 7215 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
7116 break; 7216 break;
7217 case ETH_SS_TEST:
7218 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
7219 break;
7117 default: 7220 default:
7118 WARN_ON(1); /* we need a WARN() */ 7221 WARN_ON(1); /* we need a WARN() */
7119 break; 7222 break;
@@ -7127,6 +7230,517 @@ static void tg3_get_ethtool_stats (struct net_device *dev,
7127 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats)); 7230 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
7128} 7231}
7129 7232
7233#define NVRAM_TEST_SIZE 0x100
7234
7235static int tg3_test_nvram(struct tg3 *tp)
7236{
7237 u32 *buf, csum;
7238 int i, j, err = 0;
7239
7240 buf = kmalloc(NVRAM_TEST_SIZE, GFP_KERNEL);
7241 if (buf == NULL)
7242 return -ENOMEM;
7243
7244 for (i = 0, j = 0; i < NVRAM_TEST_SIZE; i += 4, j++) {
7245 u32 val;
7246
7247 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
7248 break;
7249 buf[j] = cpu_to_le32(val);
7250 }
7251 if (i < NVRAM_TEST_SIZE)
7252 goto out;
7253
7254 err = -EIO;
7255 if (cpu_to_be32(buf[0]) != TG3_EEPROM_MAGIC)
7256 goto out;
7257
7258 /* Bootstrap checksum at offset 0x10 */
7259 csum = calc_crc((unsigned char *) buf, 0x10);
7260 if(csum != cpu_to_le32(buf[0x10/4]))
7261 goto out;
7262
7263 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
7264 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
7265 if (csum != cpu_to_le32(buf[0xfc/4]))
7266 goto out;
7267
7268 err = 0;
7269
7270out:
7271 kfree(buf);
7272 return err;
7273}
7274
7275#define TG3_SERDES_TIMEOUT_SEC 2
7276#define TG3_COPPER_TIMEOUT_SEC 6
7277
7278static int tg3_test_link(struct tg3 *tp)
7279{
7280 int i, max;
7281
7282 if (!netif_running(tp->dev))
7283 return -ENODEV;
7284
7285 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7286 max = TG3_SERDES_TIMEOUT_SEC;
7287 else
7288 max = TG3_COPPER_TIMEOUT_SEC;
7289
7290 for (i = 0; i < max; i++) {
7291 if (netif_carrier_ok(tp->dev))
7292 return 0;
7293
7294 if (msleep_interruptible(1000))
7295 break;
7296 }
7297
7298 return -EIO;
7299}
7300
7301/* Only test the commonly used registers */
7302static int tg3_test_registers(struct tg3 *tp)
7303{
7304 int i, is_5705;
7305 u32 offset, read_mask, write_mask, val, save_val, read_val;
7306 static struct {
7307 u16 offset;
7308 u16 flags;
7309#define TG3_FL_5705 0x1
7310#define TG3_FL_NOT_5705 0x2
7311#define TG3_FL_NOT_5788 0x4
7312 u32 read_mask;
7313 u32 write_mask;
7314 } reg_tbl[] = {
7315 /* MAC Control Registers */
7316 { MAC_MODE, TG3_FL_NOT_5705,
7317 0x00000000, 0x00ef6f8c },
7318 { MAC_MODE, TG3_FL_5705,
7319 0x00000000, 0x01ef6b8c },
7320 { MAC_STATUS, TG3_FL_NOT_5705,
7321 0x03800107, 0x00000000 },
7322 { MAC_STATUS, TG3_FL_5705,
7323 0x03800100, 0x00000000 },
7324 { MAC_ADDR_0_HIGH, 0x0000,
7325 0x00000000, 0x0000ffff },
7326 { MAC_ADDR_0_LOW, 0x0000,
7327 0x00000000, 0xffffffff },
7328 { MAC_RX_MTU_SIZE, 0x0000,
7329 0x00000000, 0x0000ffff },
7330 { MAC_TX_MODE, 0x0000,
7331 0x00000000, 0x00000070 },
7332 { MAC_TX_LENGTHS, 0x0000,
7333 0x00000000, 0x00003fff },
7334 { MAC_RX_MODE, TG3_FL_NOT_5705,
7335 0x00000000, 0x000007fc },
7336 { MAC_RX_MODE, TG3_FL_5705,
7337 0x00000000, 0x000007dc },
7338 { MAC_HASH_REG_0, 0x0000,
7339 0x00000000, 0xffffffff },
7340 { MAC_HASH_REG_1, 0x0000,
7341 0x00000000, 0xffffffff },
7342 { MAC_HASH_REG_2, 0x0000,
7343 0x00000000, 0xffffffff },
7344 { MAC_HASH_REG_3, 0x0000,
7345 0x00000000, 0xffffffff },
7346
7347 /* Receive Data and Receive BD Initiator Control Registers. */
7348 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
7349 0x00000000, 0xffffffff },
7350 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
7351 0x00000000, 0xffffffff },
7352 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
7353 0x00000000, 0x00000003 },
7354 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
7355 0x00000000, 0xffffffff },
7356 { RCVDBDI_STD_BD+0, 0x0000,
7357 0x00000000, 0xffffffff },
7358 { RCVDBDI_STD_BD+4, 0x0000,
7359 0x00000000, 0xffffffff },
7360 { RCVDBDI_STD_BD+8, 0x0000,
7361 0x00000000, 0xffff0002 },
7362 { RCVDBDI_STD_BD+0xc, 0x0000,
7363 0x00000000, 0xffffffff },
7364
7365 /* Receive BD Initiator Control Registers. */
7366 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
7367 0x00000000, 0xffffffff },
7368 { RCVBDI_STD_THRESH, TG3_FL_5705,
7369 0x00000000, 0x000003ff },
7370 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
7371 0x00000000, 0xffffffff },
7372
7373 /* Host Coalescing Control Registers. */
7374 { HOSTCC_MODE, TG3_FL_NOT_5705,
7375 0x00000000, 0x00000004 },
7376 { HOSTCC_MODE, TG3_FL_5705,
7377 0x00000000, 0x000000f6 },
7378 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
7379 0x00000000, 0xffffffff },
7380 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
7381 0x00000000, 0x000003ff },
7382 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
7383 0x00000000, 0xffffffff },
7384 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
7385 0x00000000, 0x000003ff },
7386 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
7387 0x00000000, 0xffffffff },
7388 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7389 0x00000000, 0x000000ff },
7390 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
7391 0x00000000, 0xffffffff },
7392 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7393 0x00000000, 0x000000ff },
7394 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
7395 0x00000000, 0xffffffff },
7396 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
7397 0x00000000, 0xffffffff },
7398 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7399 0x00000000, 0xffffffff },
7400 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7401 0x00000000, 0x000000ff },
7402 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7403 0x00000000, 0xffffffff },
7404 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7405 0x00000000, 0x000000ff },
7406 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
7407 0x00000000, 0xffffffff },
7408 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
7409 0x00000000, 0xffffffff },
7410 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
7411 0x00000000, 0xffffffff },
7412 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
7413 0x00000000, 0xffffffff },
7414 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
7415 0x00000000, 0xffffffff },
7416 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
7417 0xffffffff, 0x00000000 },
7418 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
7419 0xffffffff, 0x00000000 },
7420
7421 /* Buffer Manager Control Registers. */
7422 { BUFMGR_MB_POOL_ADDR, 0x0000,
7423 0x00000000, 0x007fff80 },
7424 { BUFMGR_MB_POOL_SIZE, 0x0000,
7425 0x00000000, 0x007fffff },
7426 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
7427 0x00000000, 0x0000003f },
7428 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
7429 0x00000000, 0x000001ff },
7430 { BUFMGR_MB_HIGH_WATER, 0x0000,
7431 0x00000000, 0x000001ff },
7432 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
7433 0xffffffff, 0x00000000 },
7434 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
7435 0xffffffff, 0x00000000 },
7436
7437 /* Mailbox Registers */
7438 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
7439 0x00000000, 0x000001ff },
7440 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
7441 0x00000000, 0x000001ff },
7442 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
7443 0x00000000, 0x000007ff },
7444 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
7445 0x00000000, 0x000001ff },
7446
7447 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
7448 };
7449
7450 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7451 is_5705 = 1;
7452 else
7453 is_5705 = 0;
7454
7455 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
7456 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
7457 continue;
7458
7459 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
7460 continue;
7461
7462 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7463 (reg_tbl[i].flags & TG3_FL_NOT_5788))
7464 continue;
7465
7466 offset = (u32) reg_tbl[i].offset;
7467 read_mask = reg_tbl[i].read_mask;
7468 write_mask = reg_tbl[i].write_mask;
7469
7470 /* Save the original register content */
7471 save_val = tr32(offset);
7472
7473 /* Determine the read-only value. */
7474 read_val = save_val & read_mask;
7475
7476 /* Write zero to the register, then make sure the read-only bits
7477 * are not changed and the read/write bits are all zeros.
7478 */
7479 tw32(offset, 0);
7480
7481 val = tr32(offset);
7482
7483 /* Test the read-only and read/write bits. */
7484 if (((val & read_mask) != read_val) || (val & write_mask))
7485 goto out;
7486
7487 /* Write ones to all the bits defined by RdMask and WrMask, then
7488 * make sure the read-only bits are not changed and the
7489 * read/write bits are all ones.
7490 */
7491 tw32(offset, read_mask | write_mask);
7492
7493 val = tr32(offset);
7494
7495 /* Test the read-only bits. */
7496 if ((val & read_mask) != read_val)
7497 goto out;
7498
7499 /* Test the read/write bits. */
7500 if ((val & write_mask) != write_mask)
7501 goto out;
7502
7503 tw32(offset, save_val);
7504 }
7505
7506 return 0;
7507
7508out:
7509 printk(KERN_ERR PFX "Register test failed at offset %x\n", offset);
7510 tw32(offset, save_val);
7511 return -EIO;
7512}
7513
7514static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
7515{
7516 static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7517 int i;
7518 u32 j;
7519
7520 for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
7521 for (j = 0; j < len; j += 4) {
7522 u32 val;
7523
7524 tg3_write_mem(tp, offset + j, test_pattern[i]);
7525 tg3_read_mem(tp, offset + j, &val);
7526 if (val != test_pattern[i])
7527 return -EIO;
7528 }
7529 }
7530 return 0;
7531}
7532
7533static int tg3_test_memory(struct tg3 *tp)
7534{
7535 static struct mem_entry {
7536 u32 offset;
7537 u32 len;
7538 } mem_tbl_570x[] = {
7539 { 0x00000000, 0x01000},
7540 { 0x00002000, 0x1c000},
7541 { 0xffffffff, 0x00000}
7542 }, mem_tbl_5705[] = {
7543 { 0x00000100, 0x0000c},
7544 { 0x00000200, 0x00008},
7545 { 0x00000b50, 0x00400},
7546 { 0x00004000, 0x00800},
7547 { 0x00006000, 0x01000},
7548 { 0x00008000, 0x02000},
7549 { 0x00010000, 0x0e000},
7550 { 0xffffffff, 0x00000}
7551 };
7552 struct mem_entry *mem_tbl;
7553 int err = 0;
7554 int i;
7555
7556 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7557 mem_tbl = mem_tbl_5705;
7558 else
7559 mem_tbl = mem_tbl_570x;
7560
7561 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
7562 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
7563 mem_tbl[i].len)) != 0)
7564 break;
7565 }
7566
7567 return err;
7568}
7569
7570static int tg3_test_loopback(struct tg3 *tp)
7571{
7572 u32 mac_mode, send_idx, rx_start_idx, rx_idx, tx_idx, opaque_key;
7573 u32 desc_idx;
7574 struct sk_buff *skb, *rx_skb;
7575 u8 *tx_data;
7576 dma_addr_t map;
7577 int num_pkts, tx_len, rx_len, i, err;
7578 struct tg3_rx_buffer_desc *desc;
7579
7580 if (!netif_running(tp->dev))
7581 return -ENODEV;
7582
7583 err = -EIO;
7584
7585 tg3_abort_hw(tp, 1);
7586
7587 tg3_reset_hw(tp);
7588
7589 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
7590 MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY |
7591 MAC_MODE_PORT_MODE_GMII;
7592 tw32(MAC_MODE, mac_mode);
7593
7594 tx_len = 1514;
7595 skb = dev_alloc_skb(tx_len);
7596 tx_data = skb_put(skb, tx_len);
7597 memcpy(tx_data, tp->dev->dev_addr, 6);
7598 memset(tx_data + 6, 0x0, 8);
7599
7600 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
7601
7602 for (i = 14; i < tx_len; i++)
7603 tx_data[i] = (u8) (i & 0xff);
7604
7605 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
7606
7607 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7608 HOSTCC_MODE_NOW);
7609
7610 udelay(10);
7611
7612 rx_start_idx = tp->hw_status->idx[0].rx_producer;
7613
7614 send_idx = 0;
7615 num_pkts = 0;
7616
7617 tg3_set_txd(tp, send_idx, map, tx_len, 0, 1);
7618
7619 send_idx++;
7620 num_pkts++;
7621
7622 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, send_idx);
7623 tr32(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
7624
7625 udelay(10);
7626
7627 for (i = 0; i < 10; i++) {
7628 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7629 HOSTCC_MODE_NOW);
7630
7631 udelay(10);
7632
7633 tx_idx = tp->hw_status->idx[0].tx_consumer;
7634 rx_idx = tp->hw_status->idx[0].rx_producer;
7635 if ((tx_idx == send_idx) &&
7636 (rx_idx == (rx_start_idx + num_pkts)))
7637 break;
7638 }
7639
7640 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
7641 dev_kfree_skb(skb);
7642
7643 if (tx_idx != send_idx)
7644 goto out;
7645
7646 if (rx_idx != rx_start_idx + num_pkts)
7647 goto out;
7648
7649 desc = &tp->rx_rcb[rx_start_idx];
7650 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
7651 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
7652 if (opaque_key != RXD_OPAQUE_RING_STD)
7653 goto out;
7654
7655 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
7656 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
7657 goto out;
7658
7659 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
7660 if (rx_len != tx_len)
7661 goto out;
7662
7663 rx_skb = tp->rx_std_buffers[desc_idx].skb;
7664
7665 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
7666 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
7667
7668 for (i = 14; i < tx_len; i++) {
7669 if (*(rx_skb->data + i) != (u8) (i & 0xff))
7670 goto out;
7671 }
7672 err = 0;
7673
7674 /* tg3_free_rings will unmap and free the rx_skb */
7675out:
7676 return err;
7677}
7678
7679static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
7680 u64 *data)
7681{
7682 struct tg3 *tp = netdev_priv(dev);
7683
7684 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
7685
7686 if (tg3_test_nvram(tp) != 0) {
7687 etest->flags |= ETH_TEST_FL_FAILED;
7688 data[0] = 1;
7689 }
7690 if (tg3_test_link(tp) != 0) {
7691 etest->flags |= ETH_TEST_FL_FAILED;
7692 data[1] = 1;
7693 }
7694 if (etest->flags & ETH_TEST_FL_OFFLINE) {
7695 int irq_sync = 0;
7696
7697 if (netif_running(dev)) {
7698 tg3_netif_stop(tp);
7699 irq_sync = 1;
7700 }
7701
7702 tg3_full_lock(tp, irq_sync);
7703
7704 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
7705 tg3_nvram_lock(tp);
7706 tg3_halt_cpu(tp, RX_CPU_BASE);
7707 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7708 tg3_halt_cpu(tp, TX_CPU_BASE);
7709 tg3_nvram_unlock(tp);
7710
7711 if (tg3_test_registers(tp) != 0) {
7712 etest->flags |= ETH_TEST_FL_FAILED;
7713 data[2] = 1;
7714 }
7715 if (tg3_test_memory(tp) != 0) {
7716 etest->flags |= ETH_TEST_FL_FAILED;
7717 data[3] = 1;
7718 }
7719 if (tg3_test_loopback(tp) != 0) {
7720 etest->flags |= ETH_TEST_FL_FAILED;
7721 data[4] = 1;
7722 }
7723
7724 tg3_full_unlock(tp);
7725
7726 if (tg3_test_interrupt(tp) != 0) {
7727 etest->flags |= ETH_TEST_FL_FAILED;
7728 data[5] = 1;
7729 }
7730
7731 tg3_full_lock(tp, 0);
7732
7733 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7734 if (netif_running(dev)) {
7735 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7736 tg3_init_hw(tp);
7737 tg3_netif_start(tp);
7738 }
7739
7740 tg3_full_unlock(tp);
7741 }
7742}
7743
7130static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 7744static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7131{ 7745{
7132 struct mii_ioctl_data *data = if_mii(ifr); 7746 struct mii_ioctl_data *data = if_mii(ifr);
@@ -7144,9 +7758,9 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7144 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) 7758 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7145 break; /* We have no PHY */ 7759 break; /* We have no PHY */
7146 7760
7147 spin_lock_irq(&tp->lock); 7761 spin_lock_bh(&tp->lock);
7148 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval); 7762 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
7149 spin_unlock_irq(&tp->lock); 7763 spin_unlock_bh(&tp->lock);
7150 7764
7151 data->val_out = mii_regval; 7765 data->val_out = mii_regval;
7152 7766
@@ -7160,9 +7774,9 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7160 if (!capable(CAP_NET_ADMIN)) 7774 if (!capable(CAP_NET_ADMIN))
7161 return -EPERM; 7775 return -EPERM;
7162 7776
7163 spin_lock_irq(&tp->lock); 7777 spin_lock_bh(&tp->lock);
7164 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in); 7778 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
7165 spin_unlock_irq(&tp->lock); 7779 spin_unlock_bh(&tp->lock);
7166 7780
7167 return err; 7781 return err;
7168 7782
@@ -7178,31 +7792,35 @@ static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
7178{ 7792{
7179 struct tg3 *tp = netdev_priv(dev); 7793 struct tg3 *tp = netdev_priv(dev);
7180 7794
7181 spin_lock_irq(&tp->lock); 7795 tg3_full_lock(tp, 0);
7182 spin_lock(&tp->tx_lock);
7183 7796
7184 tp->vlgrp = grp; 7797 tp->vlgrp = grp;
7185 7798
7186 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */ 7799 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
7187 __tg3_set_rx_mode(dev); 7800 __tg3_set_rx_mode(dev);
7188 7801
7189 spin_unlock(&tp->tx_lock); 7802 tg3_full_unlock(tp);
7190 spin_unlock_irq(&tp->lock);
7191} 7803}
7192 7804
7193static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) 7805static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
7194{ 7806{
7195 struct tg3 *tp = netdev_priv(dev); 7807 struct tg3 *tp = netdev_priv(dev);
7196 7808
7197 spin_lock_irq(&tp->lock); 7809 tg3_full_lock(tp, 0);
7198 spin_lock(&tp->tx_lock);
7199 if (tp->vlgrp) 7810 if (tp->vlgrp)
7200 tp->vlgrp->vlan_devices[vid] = NULL; 7811 tp->vlgrp->vlan_devices[vid] = NULL;
7201 spin_unlock(&tp->tx_lock); 7812 tg3_full_unlock(tp);
7202 spin_unlock_irq(&tp->lock);
7203} 7813}
7204#endif 7814#endif
7205 7815
7816static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
7817{
7818 struct tg3 *tp = netdev_priv(dev);
7819
7820 memcpy(ec, &tp->coal, sizeof(*ec));
7821 return 0;
7822}
7823
7206static struct ethtool_ops tg3_ethtool_ops = { 7824static struct ethtool_ops tg3_ethtool_ops = {
7207 .get_settings = tg3_get_settings, 7825 .get_settings = tg3_get_settings,
7208 .set_settings = tg3_set_settings, 7826 .set_settings = tg3_set_settings,
@@ -7232,9 +7850,12 @@ static struct ethtool_ops tg3_ethtool_ops = {
7232 .get_tso = ethtool_op_get_tso, 7850 .get_tso = ethtool_op_get_tso,
7233 .set_tso = tg3_set_tso, 7851 .set_tso = tg3_set_tso,
7234#endif 7852#endif
7853 .self_test_count = tg3_get_test_count,
7854 .self_test = tg3_self_test,
7235 .get_strings = tg3_get_strings, 7855 .get_strings = tg3_get_strings,
7236 .get_stats_count = tg3_get_stats_count, 7856 .get_stats_count = tg3_get_stats_count,
7237 .get_ethtool_stats = tg3_get_ethtool_stats, 7857 .get_ethtool_stats = tg3_get_ethtool_stats,
7858 .get_coalesce = tg3_get_coalesce,
7238}; 7859};
7239 7860
7240static void __devinit tg3_get_eeprom_size(struct tg3 *tp) 7861static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
@@ -7914,6 +8535,16 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
7914 8535
7915 case NIC_SRAM_DATA_CFG_LED_MODE_MAC: 8536 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
7916 tp->led_ctrl = LED_CTRL_MODE_MAC; 8537 tp->led_ctrl = LED_CTRL_MODE_MAC;
8538
8539 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
8540 * read on some older 5700/5701 bootcode.
8541 */
8542 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
8543 ASIC_REV_5700 ||
8544 GET_ASIC_REV(tp->pci_chip_rev_id) ==
8545 ASIC_REV_5701)
8546 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
8547
7917 break; 8548 break;
7918 8549
7919 case SHASTA_EXT_LED_SHARED: 8550 case SHASTA_EXT_LED_SHARED:
@@ -8422,15 +9053,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
8422 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) 9053 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8423 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG; 9054 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
8424 9055
8425 /* Only 5701 and later support tagged irq status mode.
8426 * Also, 5788 chips cannot use tagged irq status.
8427 *
8428 * However, since we are using NAPI avoid tagged irq status
8429 * because the interrupt condition is more difficult to
8430 * fully clear in that mode.
8431 */
8432 tp->coalesce_mode = 0; 9056 tp->coalesce_mode = 0;
8433
8434 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX && 9057 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
8435 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) 9058 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
8436 tp->coalesce_mode |= HOSTCC_MODE_32BYTE; 9059 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
@@ -8494,6 +9117,18 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
8494 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M)) 9117 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
8495 tp->tg3_flags2 |= TG3_FLG2_IS_5788; 9118 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
8496 9119
9120 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9121 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
9122 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
9123 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
9124 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
9125 HOSTCC_MODE_CLRTICK_TXBD);
9126
9127 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
9128 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9129 tp->misc_host_ctrl);
9130 }
9131
8497 /* these are limited to 10/100 only */ 9132 /* these are limited to 10/100 only */
8498 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && 9133 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
8499 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || 9134 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
@@ -8671,6 +9306,146 @@ static int __devinit tg3_get_device_address(struct tg3 *tp)
8671 return 0; 9306 return 0;
8672} 9307}
8673 9308
9309#define BOUNDARY_SINGLE_CACHELINE 1
9310#define BOUNDARY_MULTI_CACHELINE 2
9311
9312static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
9313{
9314 int cacheline_size;
9315 u8 byte;
9316 int goal;
9317
9318 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
9319 if (byte == 0)
9320 cacheline_size = 1024;
9321 else
9322 cacheline_size = (int) byte * 4;
9323
9324 /* On 5703 and later chips, the boundary bits have no
9325 * effect.
9326 */
9327 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9328 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
9329 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
9330 goto out;
9331
9332#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
9333 goal = BOUNDARY_MULTI_CACHELINE;
9334#else
9335#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
9336 goal = BOUNDARY_SINGLE_CACHELINE;
9337#else
9338 goal = 0;
9339#endif
9340#endif
9341
9342 if (!goal)
9343 goto out;
9344
9345 /* PCI controllers on most RISC systems tend to disconnect
9346 * when a device tries to burst across a cache-line boundary.
9347 * Therefore, letting tg3 do so just wastes PCI bandwidth.
9348 *
9349 * Unfortunately, for PCI-E there are only limited
9350 * write-side controls for this, and thus for reads
9351 * we will still get the disconnects. We'll also waste
9352 * these PCI cycles for both read and write for chips
9353 * other than 5700 and 5701 which do not implement the
9354 * boundary bits.
9355 */
9356 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
9357 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
9358 switch (cacheline_size) {
9359 case 16:
9360 case 32:
9361 case 64:
9362 case 128:
9363 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9364 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
9365 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
9366 } else {
9367 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
9368 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
9369 }
9370 break;
9371
9372 case 256:
9373 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
9374 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
9375 break;
9376
9377 default:
9378 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
9379 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
9380 break;
9381 };
9382 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
9383 switch (cacheline_size) {
9384 case 16:
9385 case 32:
9386 case 64:
9387 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9388 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
9389 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
9390 break;
9391 }
9392 /* fallthrough */
9393 case 128:
9394 default:
9395 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
9396 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
9397 break;
9398 };
9399 } else {
9400 switch (cacheline_size) {
9401 case 16:
9402 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9403 val |= (DMA_RWCTRL_READ_BNDRY_16 |
9404 DMA_RWCTRL_WRITE_BNDRY_16);
9405 break;
9406 }
9407 /* fallthrough */
9408 case 32:
9409 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9410 val |= (DMA_RWCTRL_READ_BNDRY_32 |
9411 DMA_RWCTRL_WRITE_BNDRY_32);
9412 break;
9413 }
9414 /* fallthrough */
9415 case 64:
9416 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9417 val |= (DMA_RWCTRL_READ_BNDRY_64 |
9418 DMA_RWCTRL_WRITE_BNDRY_64);
9419 break;
9420 }
9421 /* fallthrough */
9422 case 128:
9423 if (goal == BOUNDARY_SINGLE_CACHELINE) {
9424 val |= (DMA_RWCTRL_READ_BNDRY_128 |
9425 DMA_RWCTRL_WRITE_BNDRY_128);
9426 break;
9427 }
9428 /* fallthrough */
9429 case 256:
9430 val |= (DMA_RWCTRL_READ_BNDRY_256 |
9431 DMA_RWCTRL_WRITE_BNDRY_256);
9432 break;
9433 case 512:
9434 val |= (DMA_RWCTRL_READ_BNDRY_512 |
9435 DMA_RWCTRL_WRITE_BNDRY_512);
9436 break;
9437 case 1024:
9438 default:
9439 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
9440 DMA_RWCTRL_WRITE_BNDRY_1024);
9441 break;
9442 };
9443 }
9444
9445out:
9446 return val;
9447}
9448
8674static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device) 9449static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
8675{ 9450{
8676 struct tg3_internal_buffer_desc test_desc; 9451 struct tg3_internal_buffer_desc test_desc;
@@ -8752,12 +9527,12 @@ static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dm
8752 return ret; 9527 return ret;
8753} 9528}
8754 9529
8755#define TEST_BUFFER_SIZE 0x400 9530#define TEST_BUFFER_SIZE 0x2000
8756 9531
8757static int __devinit tg3_test_dma(struct tg3 *tp) 9532static int __devinit tg3_test_dma(struct tg3 *tp)
8758{ 9533{
8759 dma_addr_t buf_dma; 9534 dma_addr_t buf_dma;
8760 u32 *buf; 9535 u32 *buf, saved_dma_rwctrl;
8761 int ret; 9536 int ret;
8762 9537
8763 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma); 9538 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
@@ -8769,46 +9544,7 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
8769 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | 9544 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
8770 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT)); 9545 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
8771 9546
8772#ifndef CONFIG_X86 9547 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
8773 {
8774 u8 byte;
8775 int cacheline_size;
8776 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
8777
8778 if (byte == 0)
8779 cacheline_size = 1024;
8780 else
8781 cacheline_size = (int) byte * 4;
8782
8783 switch (cacheline_size) {
8784 case 16:
8785 case 32:
8786 case 64:
8787 case 128:
8788 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
8789 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8790 tp->dma_rwctrl |=
8791 DMA_RWCTRL_WRITE_BNDRY_384_PCIX;
8792 break;
8793 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
8794 tp->dma_rwctrl &=
8795 ~(DMA_RWCTRL_PCI_WRITE_CMD);
8796 tp->dma_rwctrl |=
8797 DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
8798 break;
8799 }
8800 /* fallthrough */
8801 case 256:
8802 if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
8803 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
8804 tp->dma_rwctrl |=
8805 DMA_RWCTRL_WRITE_BNDRY_256;
8806 else if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
8807 tp->dma_rwctrl |=
8808 DMA_RWCTRL_WRITE_BNDRY_256_PCIX;
8809 };
8810 }
8811#endif
8812 9548
8813 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { 9549 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
8814 /* DMA read watermark not used on PCIE */ 9550 /* DMA read watermark not used on PCIE */
@@ -8827,7 +9563,7 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
8827 if (ccval == 0x6 || ccval == 0x7) 9563 if (ccval == 0x6 || ccval == 0x7)
8828 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; 9564 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
8829 9565
8830 /* Set bit 23 to renable PCIX hw bug fix */ 9566 /* Set bit 23 to enable PCIX hw bug fix */
8831 tp->dma_rwctrl |= 0x009f0000; 9567 tp->dma_rwctrl |= 0x009f0000;
8832 } else { 9568 } else {
8833 tp->dma_rwctrl |= 0x001b000f; 9569 tp->dma_rwctrl |= 0x001b000f;
@@ -8868,6 +9604,13 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
8868 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) 9604 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
8869 goto out; 9605 goto out;
8870 9606
9607 /* It is best to perform DMA test with maximum write burst size
9608 * to expose the 5700/5701 write DMA bug.
9609 */
9610 saved_dma_rwctrl = tp->dma_rwctrl;
9611 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
9612 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9613
8871 while (1) { 9614 while (1) {
8872 u32 *p = buf, i; 9615 u32 *p = buf, i;
8873 9616
@@ -8906,8 +9649,9 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
8906 if (p[i] == i) 9649 if (p[i] == i)
8907 continue; 9650 continue;
8908 9651
8909 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) == 9652 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
8910 DMA_RWCTRL_WRITE_BNDRY_DISAB) { 9653 DMA_RWCTRL_WRITE_BNDRY_16) {
9654 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
8911 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; 9655 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
8912 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); 9656 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8913 break; 9657 break;
@@ -8924,6 +9668,28 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
8924 break; 9668 break;
8925 } 9669 }
8926 } 9670 }
9671 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
9672 DMA_RWCTRL_WRITE_BNDRY_16) {
9673 static struct pci_device_id dma_wait_state_chipsets[] = {
9674 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
9675 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
9676 { },
9677 };
9678
9679 /* DMA test passed without adjusting DMA boundary,
9680 * now look for chipsets that are known to expose the
9681 * DMA bug without failing the test.
9682 */
9683 if (pci_dev_present(dma_wait_state_chipsets)) {
9684 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
9685 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
9686 }
9687 else
9688 /* Safe to use the calculated DMA boundary. */
9689 tp->dma_rwctrl = saved_dma_rwctrl;
9690
9691 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9692 }
8927 9693
8928out: 9694out:
8929 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma); 9695 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
@@ -9011,6 +9777,31 @@ static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp)
9011 return peer; 9777 return peer;
9012} 9778}
9013 9779
9780static void __devinit tg3_init_coal(struct tg3 *tp)
9781{
9782 struct ethtool_coalesce *ec = &tp->coal;
9783
9784 memset(ec, 0, sizeof(*ec));
9785 ec->cmd = ETHTOOL_GCOALESCE;
9786 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
9787 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
9788 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
9789 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
9790 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
9791 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
9792 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
9793 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
9794 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
9795
9796 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
9797 HOSTCC_MODE_CLRTICK_TXBD)) {
9798 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
9799 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
9800 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
9801 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
9802 }
9803}
9804
9014static int __devinit tg3_init_one(struct pci_dev *pdev, 9805static int __devinit tg3_init_one(struct pci_dev *pdev,
9015 const struct pci_device_id *ent) 9806 const struct pci_device_id *ent)
9016{ 9807{
@@ -9232,7 +10023,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
9232 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { 10023 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
9233 pci_save_state(tp->pdev); 10024 pci_save_state(tp->pdev);
9234 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE); 10025 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
9235 tg3_halt(tp, 1); 10026 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9236 } 10027 }
9237 10028
9238 err = tg3_test_dma(tp); 10029 err = tg3_test_dma(tp);
@@ -9256,6 +10047,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
9256 /* flow control autonegotiation is default behavior */ 10047 /* flow control autonegotiation is default behavior */
9257 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; 10048 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9258 10049
10050 tg3_init_coal(tp);
10051
9259 err = register_netdev(dev); 10052 err = register_netdev(dev);
9260 if (err) { 10053 if (err) {
9261 printk(KERN_ERR PFX "Cannot register net device, " 10054 printk(KERN_ERR PFX "Cannot register net device, "
@@ -9298,6 +10091,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
9298 (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0, 10091 (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
9299 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0, 10092 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
9300 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0); 10093 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
10094 printk(KERN_INFO "%s: dma_rwctrl[%08x]\n",
10095 dev->name, tp->dma_rwctrl);
9301 10096
9302 return 0; 10097 return 0;
9303 10098
@@ -9345,24 +10140,19 @@ static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
9345 10140
9346 del_timer_sync(&tp->timer); 10141 del_timer_sync(&tp->timer);
9347 10142
9348 spin_lock_irq(&tp->lock); 10143 tg3_full_lock(tp, 1);
9349 spin_lock(&tp->tx_lock);
9350 tg3_disable_ints(tp); 10144 tg3_disable_ints(tp);
9351 spin_unlock(&tp->tx_lock); 10145 tg3_full_unlock(tp);
9352 spin_unlock_irq(&tp->lock);
9353 10146
9354 netif_device_detach(dev); 10147 netif_device_detach(dev);
9355 10148
9356 spin_lock_irq(&tp->lock); 10149 tg3_full_lock(tp, 0);
9357 spin_lock(&tp->tx_lock); 10150 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9358 tg3_halt(tp, 1); 10151 tg3_full_unlock(tp);
9359 spin_unlock(&tp->tx_lock);
9360 spin_unlock_irq(&tp->lock);
9361 10152
9362 err = tg3_set_power_state(tp, pci_choose_state(pdev, state)); 10153 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
9363 if (err) { 10154 if (err) {
9364 spin_lock_irq(&tp->lock); 10155 tg3_full_lock(tp, 0);
9365 spin_lock(&tp->tx_lock);
9366 10156
9367 tg3_init_hw(tp); 10157 tg3_init_hw(tp);
9368 10158
@@ -9372,8 +10162,7 @@ static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
9372 netif_device_attach(dev); 10162 netif_device_attach(dev);
9373 tg3_netif_start(tp); 10163 tg3_netif_start(tp);
9374 10164
9375 spin_unlock(&tp->tx_lock); 10165 tg3_full_unlock(tp);
9376 spin_unlock_irq(&tp->lock);
9377 } 10166 }
9378 10167
9379 return err; 10168 return err;
@@ -9396,20 +10185,16 @@ static int tg3_resume(struct pci_dev *pdev)
9396 10185
9397 netif_device_attach(dev); 10186 netif_device_attach(dev);
9398 10187
9399 spin_lock_irq(&tp->lock); 10188 tg3_full_lock(tp, 0);
9400 spin_lock(&tp->tx_lock);
9401 10189
9402 tg3_init_hw(tp); 10190 tg3_init_hw(tp);
9403 10191
9404 tp->timer.expires = jiffies + tp->timer_offset; 10192 tp->timer.expires = jiffies + tp->timer_offset;
9405 add_timer(&tp->timer); 10193 add_timer(&tp->timer);
9406 10194
9407 tg3_enable_ints(tp);
9408
9409 tg3_netif_start(tp); 10195 tg3_netif_start(tp);
9410 10196
9411 spin_unlock(&tp->tx_lock); 10197 tg3_full_unlock(tp);
9412 spin_unlock_irq(&tp->lock);
9413 10198
9414 return 0; 10199 return 0;
9415} 10200}
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 8de6f21037ba..99c5f9675a56 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -876,10 +876,12 @@
876#define HOSTCC_STATUS_ERROR_ATTN 0x00000004 876#define HOSTCC_STATUS_ERROR_ATTN 0x00000004
877#define HOSTCC_RXCOL_TICKS 0x00003c08 877#define HOSTCC_RXCOL_TICKS 0x00003c08
878#define LOW_RXCOL_TICKS 0x00000032 878#define LOW_RXCOL_TICKS 0x00000032
879#define LOW_RXCOL_TICKS_CLRTCKS 0x00000014
879#define DEFAULT_RXCOL_TICKS 0x00000048 880#define DEFAULT_RXCOL_TICKS 0x00000048
880#define HIGH_RXCOL_TICKS 0x00000096 881#define HIGH_RXCOL_TICKS 0x00000096
881#define HOSTCC_TXCOL_TICKS 0x00003c0c 882#define HOSTCC_TXCOL_TICKS 0x00003c0c
882#define LOW_TXCOL_TICKS 0x00000096 883#define LOW_TXCOL_TICKS 0x00000096
884#define LOW_TXCOL_TICKS_CLRTCKS 0x00000048
883#define DEFAULT_TXCOL_TICKS 0x0000012c 885#define DEFAULT_TXCOL_TICKS 0x0000012c
884#define HIGH_TXCOL_TICKS 0x00000145 886#define HIGH_TXCOL_TICKS 0x00000145
885#define HOSTCC_RXMAX_FRAMES 0x00003c10 887#define HOSTCC_RXMAX_FRAMES 0x00003c10
@@ -892,8 +894,10 @@
892#define HIGH_TXMAX_FRAMES 0x00000052 894#define HIGH_TXMAX_FRAMES 0x00000052
893#define HOSTCC_RXCOAL_TICK_INT 0x00003c18 895#define HOSTCC_RXCOAL_TICK_INT 0x00003c18
894#define DEFAULT_RXCOAL_TICK_INT 0x00000019 896#define DEFAULT_RXCOAL_TICK_INT 0x00000019
897#define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
895#define HOSTCC_TXCOAL_TICK_INT 0x00003c1c 898#define HOSTCC_TXCOAL_TICK_INT 0x00003c1c
896#define DEFAULT_TXCOAL_TICK_INT 0x00000019 899#define DEFAULT_TXCOAL_TICK_INT 0x00000019
900#define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
897#define HOSTCC_RXCOAL_MAXF_INT 0x00003c20 901#define HOSTCC_RXCOAL_MAXF_INT 0x00003c20
898#define DEFAULT_RXCOAL_MAXF_INT 0x00000005 902#define DEFAULT_RXCOAL_MAXF_INT 0x00000005
899#define HOSTCC_TXCOAL_MAXF_INT 0x00003c24 903#define HOSTCC_TXCOAL_MAXF_INT 0x00003c24
@@ -2002,17 +2006,31 @@ struct tg3_ethtool_stats {
2002struct tg3 { 2006struct tg3 {
2003 /* begin "general, frequently-used members" cacheline section */ 2007 /* begin "general, frequently-used members" cacheline section */
2004 2008
2009 /* If the IRQ handler (which runs lockless) needs to be
2010 * quiesced, the following bitmask state is used. The
2011 * SYNC flag is set by non-IRQ context code to initiate
2012 * the quiescence.
2013 *
2014 * When the IRQ handler notices that SYNC is set, it
2015 * disables interrupts and returns.
2016 *
2017 * When all outstanding IRQ handlers have returned after
2018 * the SYNC flag has been set, the setter can be assured
2019 * that interrupts will no longer get run.
2020 *
2021 * In this way all SMP driver locks are never acquired
2022 * in hw IRQ context, only sw IRQ context or lower.
2023 */
2024 unsigned int irq_sync;
2025
2005 /* SMP locking strategy: 2026 /* SMP locking strategy:
2006 * 2027 *
2007 * lock: Held during all operations except TX packet 2028 * lock: Held during all operations except TX packet
2008 * processing. 2029 * processing.
2009 * 2030 *
2010 * tx_lock: Held during tg3_start_xmit{,_4gbug} and tg3_tx 2031 * tx_lock: Held during tg3_start_xmit and tg3_tx
2011 * 2032 *
2012 * If you want to shut up all asynchronous processing you must 2033 * Both of these locks are to be held with BH safety.
2013 * acquire both locks, 'lock' taken before 'tx_lock'. IRQs must
2014 * be disabled to take 'lock' but only softirq disabling is
2015 * necessary for acquisition of 'tx_lock'.
2016 */ 2034 */
2017 spinlock_t lock; 2035 spinlock_t lock;
2018 spinlock_t indirect_lock; 2036 spinlock_t indirect_lock;
@@ -2023,6 +2041,7 @@ struct tg3 {
2023 2041
2024 struct tg3_hw_status *hw_status; 2042 struct tg3_hw_status *hw_status;
2025 dma_addr_t status_mapping; 2043 dma_addr_t status_mapping;
2044 u32 last_tag;
2026 2045
2027 u32 msg_enable; 2046 u32 msg_enable;
2028 2047
@@ -2068,6 +2087,7 @@ struct tg3 {
2068 2087
2069 u32 rx_offset; 2088 u32 rx_offset;
2070 u32 tg3_flags; 2089 u32 tg3_flags;
2090#define TG3_FLAG_TAGGED_STATUS 0x00000001
2071#define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002 2091#define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002
2072#define TG3_FLAG_RX_CHECKSUMS 0x00000004 2092#define TG3_FLAG_RX_CHECKSUMS 0x00000004
2073#define TG3_FLAG_USE_LINKCHG_REG 0x00000008 2093#define TG3_FLAG_USE_LINKCHG_REG 0x00000008
@@ -2225,7 +2245,7 @@ struct tg3 {
2225 2245
2226#define SST_25VF0X0_PAGE_SIZE 4098 2246#define SST_25VF0X0_PAGE_SIZE 4098
2227 2247
2228 2248 struct ethtool_coalesce coal;
2229}; 2249};
2230 2250
2231#endif /* !(_T3_H) */ 2251#endif /* !(_T3_H) */
diff --git a/drivers/net/tlan.c b/drivers/net/tlan.c
index a7ffa64502dd..cf31c0629852 100644
--- a/drivers/net/tlan.c
+++ b/drivers/net/tlan.c
@@ -193,6 +193,12 @@ static int aui[MAX_TLAN_BOARDS];
193static int duplex[MAX_TLAN_BOARDS]; 193static int duplex[MAX_TLAN_BOARDS];
194static int speed[MAX_TLAN_BOARDS]; 194static int speed[MAX_TLAN_BOARDS];
195static int boards_found; 195static int boards_found;
196module_param_array(aui, int, NULL, 0);
197module_param_array(duplex, int, NULL, 0);
198module_param_array(speed, int, NULL, 0);
199MODULE_PARM_DESC(aui, "ThunderLAN use AUI port(s) (0-1)");
200MODULE_PARM_DESC(duplex, "ThunderLAN duplex setting(s) (0-default, 1-half, 2-full)");
201MODULE_PARM_DESC(speed, "ThunderLAN port speen setting(s) (0,10,100)");
196 202
197MODULE_AUTHOR("Maintainer: Samuel Chessman <chessman@tux.org>"); 203MODULE_AUTHOR("Maintainer: Samuel Chessman <chessman@tux.org>");
198MODULE_DESCRIPTION("Driver for TI ThunderLAN based ethernet PCI adapters"); 204MODULE_DESCRIPTION("Driver for TI ThunderLAN based ethernet PCI adapters");
@@ -204,8 +210,13 @@ MODULE_LICENSE("GPL");
204 210
205/* Turn on debugging. See Documentation/networking/tlan.txt for details */ 211/* Turn on debugging. See Documentation/networking/tlan.txt for details */
206static int debug; 212static int debug;
213module_param(debug, int, 0);
214MODULE_PARM_DESC(debug, "ThunderLAN debug mask");
207 215
208static int bbuf; 216static int bbuf;
217module_param(bbuf, int, 0);
218MODULE_PARM_DESC(bbuf, "ThunderLAN use big buffer (0-1)");
219
209static u8 *TLanPadBuffer; 220static u8 *TLanPadBuffer;
210static dma_addr_t TLanPadBufferDMA; 221static dma_addr_t TLanPadBufferDMA;
211static char TLanSignature[] = "TLAN"; 222static char TLanSignature[] = "TLAN";
@@ -2381,6 +2392,7 @@ TLan_FinishReset( struct net_device *dev )
2381 TLan_SetTimer( dev, (10*HZ), TLAN_TIMER_FINISH_RESET ); 2392 TLan_SetTimer( dev, (10*HZ), TLAN_TIMER_FINISH_RESET );
2382 return; 2393 return;
2383 } 2394 }
2395 TLan_SetMulticastList(dev);
2384 2396
2385} /* TLan_FinishReset */ 2397} /* TLan_FinishReset */
2386 2398
@@ -2807,7 +2819,7 @@ void TLan_PhyMonitor( struct net_device *dev )
2807 if (priv->link) { 2819 if (priv->link) {
2808 priv->link = 0; 2820 priv->link = 0;
2809 printk(KERN_DEBUG "TLAN: %s has lost link\n", dev->name); 2821 printk(KERN_DEBUG "TLAN: %s has lost link\n", dev->name);
2810 dev->flags &= ~IFF_RUNNING; 2822 netif_carrier_off(dev);
2811 TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_LINK_BEAT ); 2823 TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_LINK_BEAT );
2812 return; 2824 return;
2813 } 2825 }
@@ -2817,7 +2829,7 @@ void TLan_PhyMonitor( struct net_device *dev )
2817 if ((phy_status & MII_GS_LINK) && !priv->link) { 2829 if ((phy_status & MII_GS_LINK) && !priv->link) {
2818 priv->link = 1; 2830 priv->link = 1;
2819 printk(KERN_DEBUG "TLAN: %s has reestablished link\n", dev->name); 2831 printk(KERN_DEBUG "TLAN: %s has reestablished link\n", dev->name);
2820 dev->flags |= IFF_RUNNING; 2832 netif_carrier_on(dev);
2821 } 2833 }
2822 2834
2823 /* Setup a new monitor */ 2835 /* Setup a new monitor */
diff --git a/drivers/net/tokenring/ibmtr.c b/drivers/net/tokenring/ibmtr.c
index c098863bdd9d..3873917a9c22 100644
--- a/drivers/net/tokenring/ibmtr.c
+++ b/drivers/net/tokenring/ibmtr.c
@@ -888,11 +888,6 @@ static int tok_open(struct net_device *dev)
888 ti->sap_status = CLOSED; /* CLOSED or OPEN */ 888 ti->sap_status = CLOSED; /* CLOSED or OPEN */
889 ti->open_failure = NO; /* NO or YES */ 889 ti->open_failure = NO; /* NO or YES */
890 ti->open_mode = MANUAL; /* MANUAL or AUTOMATIC */ 890 ti->open_mode = MANUAL; /* MANUAL or AUTOMATIC */
891 /* 12/2000 not typical Linux, but we can use RUNNING to let us know when
892 the network has crapped out or cables are disconnected. Useful because
893 the IFF_UP flag stays up the whole time, until ifconfig tr0 down.
894 */
895 dev->flags &= ~IFF_RUNNING;
896 891
897 ti->sram_phys &= ~1; /* to reverse what we do in tok_close */ 892 ti->sram_phys &= ~1; /* to reverse what we do in tok_close */
898 /* init the spinlock */ 893 /* init the spinlock */
@@ -1242,7 +1237,7 @@ irqreturn_t tok_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1242 ti->open_status = CLOSED; 1237 ti->open_status = CLOSED;
1243 ti->sap_status = CLOSED; 1238 ti->sap_status = CLOSED;
1244 ti->open_mode = AUTOMATIC; 1239 ti->open_mode = AUTOMATIC;
1245 dev->flags &= ~IFF_RUNNING; 1240 netif_carrier_off(dev);
1246 netif_stop_queue(dev); 1241 netif_stop_queue(dev);
1247 ti->open_action = RESTART; 1242 ti->open_action = RESTART;
1248 outb(0, dev->base_addr + ADAPTRESET); 1243 outb(0, dev->base_addr + ADAPTRESET);
@@ -1323,7 +1318,7 @@ irqreturn_t tok_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1323 break; 1318 break;
1324 } 1319 }
1325 netif_wake_queue(dev); 1320 netif_wake_queue(dev);
1326 dev->flags |= IFF_RUNNING;/*BMS 12/2000*/ 1321 netif_carrier_on(dev);
1327 break; 1322 break;
1328 case DIR_INTERRUPT: 1323 case DIR_INTERRUPT:
1329 case DIR_MOD_OPEN_PARAMS: 1324 case DIR_MOD_OPEN_PARAMS:
@@ -1427,7 +1422,7 @@ irqreturn_t tok_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1427 ring_status); 1422 ring_status);
1428 if(ring_status& (REMOVE_RECV|AUTO_REMOVAL|LOBE_FAULT)){ 1423 if(ring_status& (REMOVE_RECV|AUTO_REMOVAL|LOBE_FAULT)){
1429 netif_stop_queue(dev); 1424 netif_stop_queue(dev);
1430 dev->flags &= ~IFF_RUNNING;/*not typical Linux*/ 1425 netif_carrier_off(dev);
1431 DPRINTK("Remove received, or Auto-removal error" 1426 DPRINTK("Remove received, or Auto-removal error"
1432 ", or Lobe fault\n"); 1427 ", or Lobe fault\n");
1433 DPRINTK("We'll try to reopen the closed adapter" 1428 DPRINTK("We'll try to reopen the closed adapter"
diff --git a/drivers/net/tulip/media.c b/drivers/net/tulip/media.c
index edae09a4b021..919c40cd635c 100644
--- a/drivers/net/tulip/media.c
+++ b/drivers/net/tulip/media.c
@@ -174,6 +174,7 @@ void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int val)
174 break; 174 break;
175 } 175 }
176 spin_unlock_irqrestore(&tp->mii_lock, flags); 176 spin_unlock_irqrestore(&tp->mii_lock, flags);
177 return;
177 } 178 }
178 179
179 /* Establish sync by sending 32 logic ones. */ 180 /* Establish sync by sending 32 logic ones. */
diff --git a/drivers/net/tulip/tulip_core.c b/drivers/net/tulip/tulip_core.c
index d098b3ba3538..e0ae3ed6e578 100644
--- a/drivers/net/tulip/tulip_core.c
+++ b/drivers/net/tulip/tulip_core.c
@@ -1104,7 +1104,7 @@ static void set_rx_mode(struct net_device *dev)
1104 if (entry != 0) { 1104 if (entry != 0) {
1105 /* Avoid a chip errata by prefixing a dummy entry. Don't do 1105 /* Avoid a chip errata by prefixing a dummy entry. Don't do
1106 this on the ULI526X as it triggers a different problem */ 1106 this on the ULI526X as it triggers a different problem */
1107 if (!(tp->chip_id == ULI526X && (tp->revision = 0x40 || tp->revision == 0x50))) { 1107 if (!(tp->chip_id == ULI526X && (tp->revision == 0x40 || tp->revision == 0x50))) {
1108 tp->tx_buffers[entry].skb = NULL; 1108 tp->tx_buffers[entry].skb = NULL;
1109 tp->tx_buffers[entry].mapping = 0; 1109 tp->tx_buffers[entry].mapping = 0;
1110 tp->tx_ring[entry].length = 1110 tp->tx_ring[entry].length =
diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig
index 66b94668ddd8..18c27e1e7884 100644
--- a/drivers/net/wan/Kconfig
+++ b/drivers/net/wan/Kconfig
@@ -435,7 +435,7 @@ config VENDOR_SANGOMA
435 the driver to support. 435 the driver to support.
436 436
437 If you have one or more of these cards, say M to this option; 437 If you have one or more of these cards, say M to this option;
438 and read <file:Documentation/networking/wanpipe.txt>. 438 and read <file:Documentation/networking/wan-router.txt>.
439 439
440 To compile this driver as a module, choose M here: the 440 To compile this driver as a module, choose M here: the
441 module will be called wanpipe. 441 module will be called wanpipe.
diff --git a/drivers/net/wan/cosa.c b/drivers/net/wan/cosa.c
index 921a573372e9..7ff814fd65d0 100644
--- a/drivers/net/wan/cosa.c
+++ b/drivers/net/wan/cosa.c
@@ -235,7 +235,7 @@ static int dma[MAX_CARDS+1];
235static int irq[MAX_CARDS+1] = { -1, -1, -1, -1, -1, -1, 0, }; 235static int irq[MAX_CARDS+1] = { -1, -1, -1, -1, -1, -1, 0, };
236 236
237/* for class stuff*/ 237/* for class stuff*/
238static struct class_simple *cosa_class; 238static struct class *cosa_class;
239 239
240#ifdef MODULE 240#ifdef MODULE
241module_param_array(io, int, NULL, 0); 241module_param_array(io, int, NULL, 0);
@@ -394,19 +394,19 @@ static int __init cosa_init(void)
394 goto out; 394 goto out;
395 } 395 }
396 devfs_mk_dir("cosa"); 396 devfs_mk_dir("cosa");
397 cosa_class = class_simple_create(THIS_MODULE, "cosa"); 397 cosa_class = class_create(THIS_MODULE, "cosa");
398 if (IS_ERR(cosa_class)) { 398 if (IS_ERR(cosa_class)) {
399 err = PTR_ERR(cosa_class); 399 err = PTR_ERR(cosa_class);
400 goto out_chrdev; 400 goto out_chrdev;
401 } 401 }
402 for (i=0; i<nr_cards; i++) { 402 for (i=0; i<nr_cards; i++) {
403 class_simple_device_add(cosa_class, MKDEV(cosa_major, i), 403 class_device_create(cosa_class, MKDEV(cosa_major, i),
404 NULL, "cosa%d", i); 404 NULL, "cosa%d", i);
405 err = devfs_mk_cdev(MKDEV(cosa_major, i), 405 err = devfs_mk_cdev(MKDEV(cosa_major, i),
406 S_IFCHR|S_IRUSR|S_IWUSR, 406 S_IFCHR|S_IRUSR|S_IWUSR,
407 "cosa/%d", i); 407 "cosa/%d", i);
408 if (err) { 408 if (err) {
409 class_simple_device_remove(MKDEV(cosa_major, i)); 409 class_device_destroy(cosa_class, MKDEV(cosa_major, i));
410 goto out_chrdev; 410 goto out_chrdev;
411 } 411 }
412 } 412 }
@@ -427,10 +427,10 @@ static void __exit cosa_exit(void)
427 printk(KERN_INFO "Unloading the cosa module\n"); 427 printk(KERN_INFO "Unloading the cosa module\n");
428 428
429 for (i=0; i<nr_cards; i++) { 429 for (i=0; i<nr_cards; i++) {
430 class_simple_device_remove(MKDEV(cosa_major, i)); 430 class_device_destroy(cosa_class, MKDEV(cosa_major, i));
431 devfs_remove("cosa/%d", i); 431 devfs_remove("cosa/%d", i);
432 } 432 }
433 class_simple_destroy(cosa_class); 433 class_destroy(cosa_class);
434 devfs_remove("cosa"); 434 devfs_remove("cosa");
435 for (cosa=cosa_cards; nr_cards--; cosa++) { 435 for (cosa=cosa_cards; nr_cards--; cosa++) {
436 /* Clean up the per-channel data */ 436 /* Clean up the per-channel data */
diff --git a/drivers/net/wan/hdlc_fr.c b/drivers/net/wan/hdlc_fr.c
index 7f450b51a6cb..a5d6891c9d4c 100644
--- a/drivers/net/wan/hdlc_fr.c
+++ b/drivers/net/wan/hdlc_fr.c
@@ -2,7 +2,7 @@
2 * Generic HDLC support routines for Linux 2 * Generic HDLC support routines for Linux
3 * Frame Relay support 3 * Frame Relay support
4 * 4 *
5 * Copyright (C) 1999 - 2003 Krzysztof Halasa <khc@pm.waw.pl> 5 * Copyright (C) 1999 - 2005 Krzysztof Halasa <khc@pm.waw.pl>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License 8 * under the terms of version 2 of the GNU General Public License
@@ -27,6 +27,10 @@
27 active = open and "link reliable" 27 active = open and "link reliable"
28 exist = new = not used 28 exist = new = not used
29 29
30 CCITT LMI: ITU-T Q.933 Annex A
31 ANSI LMI: ANSI T1.617 Annex D
32 CISCO LMI: the original, aka "Gang of Four" LMI
33
30*/ 34*/
31 35
32#include <linux/module.h> 36#include <linux/module.h>
@@ -49,45 +53,41 @@
49#undef DEBUG_ECN 53#undef DEBUG_ECN
50#undef DEBUG_LINK 54#undef DEBUG_LINK
51 55
52#define MAXLEN_LMISTAT 20 /* max size of status enquiry frame */ 56#define FR_UI 0x03
53 57#define FR_PAD 0x00
54#define PVC_STATE_NEW 0x01 58
55#define PVC_STATE_ACTIVE 0x02 59#define NLPID_IP 0xCC
56#define PVC_STATE_FECN 0x08 /* FECN condition */ 60#define NLPID_IPV6 0x8E
57#define PVC_STATE_BECN 0x10 /* BECN condition */ 61#define NLPID_SNAP 0x80
58 62#define NLPID_PAD 0x00
59 63#define NLPID_CCITT_ANSI_LMI 0x08
60#define FR_UI 0x03 64#define NLPID_CISCO_LMI 0x09
61#define FR_PAD 0x00 65
62 66
63#define NLPID_IP 0xCC 67#define LMI_CCITT_ANSI_DLCI 0 /* LMI DLCI */
64#define NLPID_IPV6 0x8E 68#define LMI_CISCO_DLCI 1023
65#define NLPID_SNAP 0x80 69
66#define NLPID_PAD 0x00 70#define LMI_CALLREF 0x00 /* Call Reference */
67#define NLPID_Q933 0x08 71#define LMI_ANSI_LOCKSHIFT 0x95 /* ANSI locking shift */
68 72#define LMI_ANSI_CISCO_REPTYPE 0x01 /* report type */
69 73#define LMI_CCITT_REPTYPE 0x51
70#define LMI_DLCI 0 /* LMI DLCI */ 74#define LMI_ANSI_CISCO_ALIVE 0x03 /* keep alive */
71#define LMI_PROTO 0x08 75#define LMI_CCITT_ALIVE 0x53
72#define LMI_CALLREF 0x00 /* Call Reference */ 76#define LMI_ANSI_CISCO_PVCSTAT 0x07 /* PVC status */
73#define LMI_ANSI_LOCKSHIFT 0x95 /* ANSI lockshift */ 77#define LMI_CCITT_PVCSTAT 0x57
74#define LMI_REPTYPE 1 /* report type */ 78
75#define LMI_CCITT_REPTYPE 0x51 79#define LMI_FULLREP 0x00 /* full report */
76#define LMI_ALIVE 3 /* keep alive */ 80#define LMI_INTEGRITY 0x01 /* link integrity report */
77#define LMI_CCITT_ALIVE 0x53 81#define LMI_SINGLE 0x02 /* single PVC report */
78#define LMI_PVCSTAT 7 /* pvc status */ 82
79#define LMI_CCITT_PVCSTAT 0x57
80#define LMI_FULLREP 0 /* full report */
81#define LMI_INTEGRITY 1 /* link integrity report */
82#define LMI_SINGLE 2 /* single pvc report */
83#define LMI_STATUS_ENQUIRY 0x75 83#define LMI_STATUS_ENQUIRY 0x75
84#define LMI_STATUS 0x7D /* reply */ 84#define LMI_STATUS 0x7D /* reply */
85 85
86#define LMI_REPT_LEN 1 /* report type element length */ 86#define LMI_REPT_LEN 1 /* report type element length */
87#define LMI_INTEG_LEN 2 /* link integrity element length */ 87#define LMI_INTEG_LEN 2 /* link integrity element length */
88 88
89#define LMI_LENGTH 13 /* standard LMI frame length */ 89#define LMI_CCITT_CISCO_LENGTH 13 /* LMI frame lengths */
90#define LMI_ANSI_LENGTH 14 90#define LMI_ANSI_LENGTH 14
91 91
92 92
93typedef struct { 93typedef struct {
@@ -223,51 +223,34 @@ static inline struct net_device** get_dev_p(pvc_device *pvc, int type)
223} 223}
224 224
225 225
226static inline u16 status_to_dlci(u8 *status, int *active, int *new)
227{
228 *new = (status[2] & 0x08) ? 1 : 0;
229 *active = (status[2] & 0x02) ? 1 : 0;
230
231 return ((status[0] & 0x3F) << 4) | ((status[1] & 0x78) >> 3);
232}
233
234
235static inline void dlci_to_status(u16 dlci, u8 *status, int active, int new)
236{
237 status[0] = (dlci >> 4) & 0x3F;
238 status[1] = ((dlci << 3) & 0x78) | 0x80;
239 status[2] = 0x80;
240
241 if (new)
242 status[2] |= 0x08;
243 else if (active)
244 status[2] |= 0x02;
245}
246
247
248
249static int fr_hard_header(struct sk_buff **skb_p, u16 dlci) 226static int fr_hard_header(struct sk_buff **skb_p, u16 dlci)
250{ 227{
251 u16 head_len; 228 u16 head_len;
252 struct sk_buff *skb = *skb_p; 229 struct sk_buff *skb = *skb_p;
253 230
254 switch (skb->protocol) { 231 switch (skb->protocol) {
255 case __constant_ntohs(ETH_P_IP): 232 case __constant_ntohs(NLPID_CCITT_ANSI_LMI):
256 head_len = 4; 233 head_len = 4;
257 skb_push(skb, head_len); 234 skb_push(skb, head_len);
258 skb->data[3] = NLPID_IP; 235 skb->data[3] = NLPID_CCITT_ANSI_LMI;
259 break; 236 break;
260 237
261 case __constant_ntohs(ETH_P_IPV6): 238 case __constant_ntohs(NLPID_CISCO_LMI):
262 head_len = 4; 239 head_len = 4;
263 skb_push(skb, head_len); 240 skb_push(skb, head_len);
264 skb->data[3] = NLPID_IPV6; 241 skb->data[3] = NLPID_CISCO_LMI;
265 break; 242 break;
266 243
267 case __constant_ntohs(LMI_PROTO): 244 case __constant_ntohs(ETH_P_IP):
245 head_len = 4;
246 skb_push(skb, head_len);
247 skb->data[3] = NLPID_IP;
248 break;
249
250 case __constant_ntohs(ETH_P_IPV6):
268 head_len = 4; 251 head_len = 4;
269 skb_push(skb, head_len); 252 skb_push(skb, head_len);
270 skb->data[3] = LMI_PROTO; 253 skb->data[3] = NLPID_IPV6;
271 break; 254 break;
272 255
273 case __constant_ntohs(ETH_P_802_3): 256 case __constant_ntohs(ETH_P_802_3):
@@ -461,13 +444,14 @@ static void fr_lmi_send(struct net_device *dev, int fullrep)
461 hdlc_device *hdlc = dev_to_hdlc(dev); 444 hdlc_device *hdlc = dev_to_hdlc(dev);
462 struct sk_buff *skb; 445 struct sk_buff *skb;
463 pvc_device *pvc = hdlc->state.fr.first_pvc; 446 pvc_device *pvc = hdlc->state.fr.first_pvc;
464 int len = (hdlc->state.fr.settings.lmi == LMI_ANSI) ? LMI_ANSI_LENGTH 447 int lmi = hdlc->state.fr.settings.lmi;
465 : LMI_LENGTH; 448 int dce = hdlc->state.fr.settings.dce;
466 int stat_len = 3; 449 int len = lmi == LMI_ANSI ? LMI_ANSI_LENGTH : LMI_CCITT_CISCO_LENGTH;
450 int stat_len = (lmi == LMI_CISCO) ? 6 : 3;
467 u8 *data; 451 u8 *data;
468 int i = 0; 452 int i = 0;
469 453
470 if (hdlc->state.fr.settings.dce && fullrep) { 454 if (dce && fullrep) {
471 len += hdlc->state.fr.dce_pvc_count * (2 + stat_len); 455 len += hdlc->state.fr.dce_pvc_count * (2 + stat_len);
472 if (len > HDLC_MAX_MRU) { 456 if (len > HDLC_MAX_MRU) {
473 printk(KERN_WARNING "%s: Too many PVCs while sending " 457 printk(KERN_WARNING "%s: Too many PVCs while sending "
@@ -484,29 +468,31 @@ static void fr_lmi_send(struct net_device *dev, int fullrep)
484 } 468 }
485 memset(skb->data, 0, len); 469 memset(skb->data, 0, len);
486 skb_reserve(skb, 4); 470 skb_reserve(skb, 4);
487 skb->protocol = __constant_htons(LMI_PROTO); 471 if (lmi == LMI_CISCO) {
488 fr_hard_header(&skb, LMI_DLCI); 472 skb->protocol = __constant_htons(NLPID_CISCO_LMI);
473 fr_hard_header(&skb, LMI_CISCO_DLCI);
474 } else {
475 skb->protocol = __constant_htons(NLPID_CCITT_ANSI_LMI);
476 fr_hard_header(&skb, LMI_CCITT_ANSI_DLCI);
477 }
489 data = skb->tail; 478 data = skb->tail;
490 data[i++] = LMI_CALLREF; 479 data[i++] = LMI_CALLREF;
491 data[i++] = hdlc->state.fr.settings.dce 480 data[i++] = dce ? LMI_STATUS : LMI_STATUS_ENQUIRY;
492 ? LMI_STATUS : LMI_STATUS_ENQUIRY; 481 if (lmi == LMI_ANSI)
493 if (hdlc->state.fr.settings.lmi == LMI_ANSI)
494 data[i++] = LMI_ANSI_LOCKSHIFT; 482 data[i++] = LMI_ANSI_LOCKSHIFT;
495 data[i++] = (hdlc->state.fr.settings.lmi == LMI_CCITT) 483 data[i++] = lmi == LMI_CCITT ? LMI_CCITT_REPTYPE :
496 ? LMI_CCITT_REPTYPE : LMI_REPTYPE; 484 LMI_ANSI_CISCO_REPTYPE;
497 data[i++] = LMI_REPT_LEN; 485 data[i++] = LMI_REPT_LEN;
498 data[i++] = fullrep ? LMI_FULLREP : LMI_INTEGRITY; 486 data[i++] = fullrep ? LMI_FULLREP : LMI_INTEGRITY;
499 487 data[i++] = lmi == LMI_CCITT ? LMI_CCITT_ALIVE : LMI_ANSI_CISCO_ALIVE;
500 data[i++] = (hdlc->state.fr.settings.lmi == LMI_CCITT)
501 ? LMI_CCITT_ALIVE : LMI_ALIVE;
502 data[i++] = LMI_INTEG_LEN; 488 data[i++] = LMI_INTEG_LEN;
503 data[i++] = hdlc->state.fr.txseq =fr_lmi_nextseq(hdlc->state.fr.txseq); 489 data[i++] = hdlc->state.fr.txseq =fr_lmi_nextseq(hdlc->state.fr.txseq);
504 data[i++] = hdlc->state.fr.rxseq; 490 data[i++] = hdlc->state.fr.rxseq;
505 491
506 if (hdlc->state.fr.settings.dce && fullrep) { 492 if (dce && fullrep) {
507 while (pvc) { 493 while (pvc) {
508 data[i++] = (hdlc->state.fr.settings.lmi == LMI_CCITT) 494 data[i++] = lmi == LMI_CCITT ? LMI_CCITT_PVCSTAT :
509 ? LMI_CCITT_PVCSTAT : LMI_PVCSTAT; 495 LMI_ANSI_CISCO_PVCSTAT;
510 data[i++] = stat_len; 496 data[i++] = stat_len;
511 497
512 /* LMI start/restart */ 498 /* LMI start/restart */
@@ -523,8 +509,20 @@ static void fr_lmi_send(struct net_device *dev, int fullrep)
523 fr_log_dlci_active(pvc); 509 fr_log_dlci_active(pvc);
524 } 510 }
525 511
526 dlci_to_status(pvc->dlci, data + i, 512 if (lmi == LMI_CISCO) {
527 pvc->state.active, pvc->state.new); 513 data[i] = pvc->dlci >> 8;
514 data[i + 1] = pvc->dlci & 0xFF;
515 } else {
516 data[i] = (pvc->dlci >> 4) & 0x3F;
517 data[i + 1] = ((pvc->dlci << 3) & 0x78) | 0x80;
518 data[i + 2] = 0x80;
519 }
520
521 if (pvc->state.new)
522 data[i + 2] |= 0x08;
523 else if (pvc->state.active)
524 data[i + 2] |= 0x02;
525
528 i += stat_len; 526 i += stat_len;
529 pvc = pvc->next; 527 pvc = pvc->next;
530 } 528 }
@@ -569,6 +567,8 @@ static void fr_set_link_state(int reliable, struct net_device *dev)
569 pvc_carrier(0, pvc); 567 pvc_carrier(0, pvc);
570 pvc->state.exist = pvc->state.active = 0; 568 pvc->state.exist = pvc->state.active = 0;
571 pvc->state.new = 0; 569 pvc->state.new = 0;
570 if (!hdlc->state.fr.settings.dce)
571 pvc->state.bandwidth = 0;
572 pvc = pvc->next; 572 pvc = pvc->next;
573 } 573 }
574 } 574 }
@@ -583,11 +583,12 @@ static void fr_timer(unsigned long arg)
583 int i, cnt = 0, reliable; 583 int i, cnt = 0, reliable;
584 u32 list; 584 u32 list;
585 585
586 if (hdlc->state.fr.settings.dce) 586 if (hdlc->state.fr.settings.dce) {
587 reliable = hdlc->state.fr.request && 587 reliable = hdlc->state.fr.request &&
588 time_before(jiffies, hdlc->state.fr.last_poll + 588 time_before(jiffies, hdlc->state.fr.last_poll +
589 hdlc->state.fr.settings.t392 * HZ); 589 hdlc->state.fr.settings.t392 * HZ);
590 else { 590 hdlc->state.fr.request = 0;
591 } else {
591 hdlc->state.fr.last_errors <<= 1; /* Shift the list */ 592 hdlc->state.fr.last_errors <<= 1; /* Shift the list */
592 if (hdlc->state.fr.request) { 593 if (hdlc->state.fr.request) {
593 if (hdlc->state.fr.reliable) 594 if (hdlc->state.fr.reliable)
@@ -634,65 +635,88 @@ static void fr_timer(unsigned long arg)
634static int fr_lmi_recv(struct net_device *dev, struct sk_buff *skb) 635static int fr_lmi_recv(struct net_device *dev, struct sk_buff *skb)
635{ 636{
636 hdlc_device *hdlc = dev_to_hdlc(dev); 637 hdlc_device *hdlc = dev_to_hdlc(dev);
637 int stat_len;
638 pvc_device *pvc; 638 pvc_device *pvc;
639 int reptype = -1, error, no_ram;
640 u8 rxseq, txseq; 639 u8 rxseq, txseq;
641 int i; 640 int lmi = hdlc->state.fr.settings.lmi;
641 int dce = hdlc->state.fr.settings.dce;
642 int stat_len = (lmi == LMI_CISCO) ? 6 : 3, reptype, error, no_ram, i;
642 643
643 if (skb->len < ((hdlc->state.fr.settings.lmi == LMI_ANSI) 644 if (skb->len < (lmi == LMI_ANSI ? LMI_ANSI_LENGTH :
644 ? LMI_ANSI_LENGTH : LMI_LENGTH)) { 645 LMI_CCITT_CISCO_LENGTH)) {
645 printk(KERN_INFO "%s: Short LMI frame\n", dev->name); 646 printk(KERN_INFO "%s: Short LMI frame\n", dev->name);
646 return 1; 647 return 1;
647 } 648 }
648 649
649 if (skb->data[5] != (!hdlc->state.fr.settings.dce ? 650 if (skb->data[3] != (lmi == LMI_CISCO ? NLPID_CISCO_LMI :
650 LMI_STATUS : LMI_STATUS_ENQUIRY)) { 651 NLPID_CCITT_ANSI_LMI)) {
651 printk(KERN_INFO "%s: LMI msgtype=%x, Not LMI status %s\n", 652 printk(KERN_INFO "%s: Received non-LMI frame with LMI"
652 dev->name, skb->data[2], 653 " DLCI\n", dev->name);
653 hdlc->state.fr.settings.dce ? "enquiry" : "reply"); 654 return 1;
655 }
656
657 if (skb->data[4] != LMI_CALLREF) {
658 printk(KERN_INFO "%s: Invalid LMI Call reference (0x%02X)\n",
659 dev->name, skb->data[4]);
660 return 1;
661 }
662
663 if (skb->data[5] != (dce ? LMI_STATUS_ENQUIRY : LMI_STATUS)) {
664 printk(KERN_INFO "%s: Invalid LMI Message type (0x%02X)\n",
665 dev->name, skb->data[5]);
654 return 1; 666 return 1;
655 } 667 }
656 668
657 i = (hdlc->state.fr.settings.lmi == LMI_ANSI) ? 7 : 6; 669 if (lmi == LMI_ANSI) {
670 if (skb->data[6] != LMI_ANSI_LOCKSHIFT) {
671 printk(KERN_INFO "%s: Not ANSI locking shift in LMI"
672 " message (0x%02X)\n", dev->name, skb->data[6]);
673 return 1;
674 }
675 i = 7;
676 } else
677 i = 6;
658 678
659 if (skb->data[i] != 679 if (skb->data[i] != (lmi == LMI_CCITT ? LMI_CCITT_REPTYPE :
660 ((hdlc->state.fr.settings.lmi == LMI_CCITT) 680 LMI_ANSI_CISCO_REPTYPE)) {
661 ? LMI_CCITT_REPTYPE : LMI_REPTYPE)) { 681 printk(KERN_INFO "%s: Not an LMI Report type IE (0x%02X)\n",
662 printk(KERN_INFO "%s: Not a report type=%x\n",
663 dev->name, skb->data[i]); 682 dev->name, skb->data[i]);
664 return 1; 683 return 1;
665 } 684 }
666 i++;
667 685
668 i++; /* Skip length field */ 686 if (skb->data[++i] != LMI_REPT_LEN) {
687 printk(KERN_INFO "%s: Invalid LMI Report type IE length"
688 " (%u)\n", dev->name, skb->data[i]);
689 return 1;
690 }
669 691
670 reptype = skb->data[i++]; 692 reptype = skb->data[++i];
693 if (reptype != LMI_INTEGRITY && reptype != LMI_FULLREP) {
694 printk(KERN_INFO "%s: Unsupported LMI Report type (0x%02X)\n",
695 dev->name, reptype);
696 return 1;
697 }
671 698
672 if (skb->data[i]!= 699 if (skb->data[++i] != (lmi == LMI_CCITT ? LMI_CCITT_ALIVE :
673 ((hdlc->state.fr.settings.lmi == LMI_CCITT) 700 LMI_ANSI_CISCO_ALIVE)) {
674 ? LMI_CCITT_ALIVE : LMI_ALIVE)) { 701 printk(KERN_INFO "%s: Not an LMI Link integrity verification"
675 printk(KERN_INFO "%s: Unsupported status element=%x\n", 702 " IE (0x%02X)\n", dev->name, skb->data[i]);
676 dev->name, skb->data[i]);
677 return 1; 703 return 1;
678 } 704 }
679 i++;
680 705
681 i++; /* Skip length field */ 706 if (skb->data[++i] != LMI_INTEG_LEN) {
707 printk(KERN_INFO "%s: Invalid LMI Link integrity verification"
708 " IE length (%u)\n", dev->name, skb->data[i]);
709 return 1;
710 }
711 i++;
682 712
683 hdlc->state.fr.rxseq = skb->data[i++]; /* TX sequence from peer */ 713 hdlc->state.fr.rxseq = skb->data[i++]; /* TX sequence from peer */
684 rxseq = skb->data[i++]; /* Should confirm our sequence */ 714 rxseq = skb->data[i++]; /* Should confirm our sequence */
685 715
686 txseq = hdlc->state.fr.txseq; 716 txseq = hdlc->state.fr.txseq;
687 717
688 if (hdlc->state.fr.settings.dce) { 718 if (dce)
689 if (reptype != LMI_FULLREP && reptype != LMI_INTEGRITY) {
690 printk(KERN_INFO "%s: Unsupported report type=%x\n",
691 dev->name, reptype);
692 return 1;
693 }
694 hdlc->state.fr.last_poll = jiffies; 719 hdlc->state.fr.last_poll = jiffies;
695 }
696 720
697 error = 0; 721 error = 0;
698 if (!hdlc->state.fr.reliable) 722 if (!hdlc->state.fr.reliable)
@@ -703,7 +727,7 @@ static int fr_lmi_recv(struct net_device *dev, struct sk_buff *skb)
703 error = 1; 727 error = 1;
704 } 728 }
705 729
706 if (hdlc->state.fr.settings.dce) { 730 if (dce) {
707 if (hdlc->state.fr.fullrep_sent && !error) { 731 if (hdlc->state.fr.fullrep_sent && !error) {
708/* Stop sending full report - the last one has been confirmed by DTE */ 732/* Stop sending full report - the last one has been confirmed by DTE */
709 hdlc->state.fr.fullrep_sent = 0; 733 hdlc->state.fr.fullrep_sent = 0;
@@ -725,6 +749,7 @@ static int fr_lmi_recv(struct net_device *dev, struct sk_buff *skb)
725 hdlc->state.fr.dce_changed = 0; 749 hdlc->state.fr.dce_changed = 0;
726 } 750 }
727 751
752 hdlc->state.fr.request = 1; /* got request */
728 fr_lmi_send(dev, reptype == LMI_FULLREP ? 1 : 0); 753 fr_lmi_send(dev, reptype == LMI_FULLREP ? 1 : 0);
729 return 0; 754 return 0;
730 } 755 }
@@ -739,7 +764,6 @@ static int fr_lmi_recv(struct net_device *dev, struct sk_buff *skb)
739 if (reptype != LMI_FULLREP) 764 if (reptype != LMI_FULLREP)
740 return 0; 765 return 0;
741 766
742 stat_len = 3;
743 pvc = hdlc->state.fr.first_pvc; 767 pvc = hdlc->state.fr.first_pvc;
744 768
745 while (pvc) { 769 while (pvc) {
@@ -750,24 +774,35 @@ static int fr_lmi_recv(struct net_device *dev, struct sk_buff *skb)
750 no_ram = 0; 774 no_ram = 0;
751 while (skb->len >= i + 2 + stat_len) { 775 while (skb->len >= i + 2 + stat_len) {
752 u16 dlci; 776 u16 dlci;
777 u32 bw;
753 unsigned int active, new; 778 unsigned int active, new;
754 779
755 if (skb->data[i] != ((hdlc->state.fr.settings.lmi == LMI_CCITT) 780 if (skb->data[i] != (lmi == LMI_CCITT ? LMI_CCITT_PVCSTAT :
756 ? LMI_CCITT_PVCSTAT : LMI_PVCSTAT)) { 781 LMI_ANSI_CISCO_PVCSTAT)) {
757 printk(KERN_WARNING "%s: Invalid PVCSTAT ID: %x\n", 782 printk(KERN_INFO "%s: Not an LMI PVC status IE"
758 dev->name, skb->data[i]); 783 " (0x%02X)\n", dev->name, skb->data[i]);
759 return 1; 784 return 1;
760 } 785 }
761 i++;
762 786
763 if (skb->data[i] != stat_len) { 787 if (skb->data[++i] != stat_len) {
764 printk(KERN_WARNING "%s: Invalid PVCSTAT length: %x\n", 788 printk(KERN_INFO "%s: Invalid LMI PVC status IE length"
765 dev->name, skb->data[i]); 789 " (%u)\n", dev->name, skb->data[i]);
766 return 1; 790 return 1;
767 } 791 }
768 i++; 792 i++;
769 793
770 dlci = status_to_dlci(skb->data + i, &active, &new); 794 new = !! (skb->data[i + 2] & 0x08);
795 active = !! (skb->data[i + 2] & 0x02);
796 if (lmi == LMI_CISCO) {
797 dlci = (skb->data[i] << 8) | skb->data[i + 1];
798 bw = (skb->data[i + 3] << 16) |
799 (skb->data[i + 4] << 8) |
800 (skb->data[i + 5]);
801 } else {
802 dlci = ((skb->data[i] & 0x3F) << 4) |
803 ((skb->data[i + 1] & 0x78) >> 3);
804 bw = 0;
805 }
771 806
772 pvc = add_pvc(dev, dlci); 807 pvc = add_pvc(dev, dlci);
773 808
@@ -783,9 +818,11 @@ static int fr_lmi_recv(struct net_device *dev, struct sk_buff *skb)
783 pvc->state.deleted = 0; 818 pvc->state.deleted = 0;
784 if (active != pvc->state.active || 819 if (active != pvc->state.active ||
785 new != pvc->state.new || 820 new != pvc->state.new ||
821 bw != pvc->state.bandwidth ||
786 !pvc->state.exist) { 822 !pvc->state.exist) {
787 pvc->state.new = new; 823 pvc->state.new = new;
788 pvc->state.active = active; 824 pvc->state.active = active;
825 pvc->state.bandwidth = bw;
789 pvc_carrier(active, pvc); 826 pvc_carrier(active, pvc);
790 fr_log_dlci_active(pvc); 827 fr_log_dlci_active(pvc);
791 } 828 }
@@ -801,6 +838,7 @@ static int fr_lmi_recv(struct net_device *dev, struct sk_buff *skb)
801 pvc_carrier(0, pvc); 838 pvc_carrier(0, pvc);
802 pvc->state.active = pvc->state.new = 0; 839 pvc->state.active = pvc->state.new = 0;
803 pvc->state.exist = 0; 840 pvc->state.exist = 0;
841 pvc->state.bandwidth = 0;
804 fr_log_dlci_active(pvc); 842 fr_log_dlci_active(pvc);
805 } 843 }
806 pvc = pvc->next; 844 pvc = pvc->next;
@@ -829,22 +867,15 @@ static int fr_rx(struct sk_buff *skb)
829 867
830 dlci = q922_to_dlci(skb->data); 868 dlci = q922_to_dlci(skb->data);
831 869
832 if (dlci == LMI_DLCI) { 870 if ((dlci == LMI_CCITT_ANSI_DLCI &&
833 if (hdlc->state.fr.settings.lmi == LMI_NONE) 871 (hdlc->state.fr.settings.lmi == LMI_ANSI ||
834 goto rx_error; /* LMI packet with no LMI? */ 872 hdlc->state.fr.settings.lmi == LMI_CCITT)) ||
835 873 (dlci == LMI_CISCO_DLCI &&
836 if (data[3] == LMI_PROTO) { 874 hdlc->state.fr.settings.lmi == LMI_CISCO)) {
837 if (fr_lmi_recv(ndev, skb)) 875 if (fr_lmi_recv(ndev, skb))
838 goto rx_error; 876 goto rx_error;
839 else { 877 dev_kfree_skb_any(skb);
840 dev_kfree_skb_any(skb); 878 return NET_RX_SUCCESS;
841 return NET_RX_SUCCESS;
842 }
843 }
844
845 printk(KERN_INFO "%s: Received non-LMI frame with LMI DLCI\n",
846 ndev->name);
847 goto rx_error;
848 } 879 }
849 880
850 pvc = find_pvc(hdlc, dlci); 881 pvc = find_pvc(hdlc, dlci);
@@ -1170,7 +1201,8 @@ int hdlc_fr_ioctl(struct net_device *dev, struct ifreq *ifr)
1170 1201
1171 if ((new_settings.lmi != LMI_NONE && 1202 if ((new_settings.lmi != LMI_NONE &&
1172 new_settings.lmi != LMI_ANSI && 1203 new_settings.lmi != LMI_ANSI &&
1173 new_settings.lmi != LMI_CCITT) || 1204 new_settings.lmi != LMI_CCITT &&
1205 new_settings.lmi != LMI_CISCO) ||
1174 new_settings.t391 < 1 || 1206 new_settings.t391 < 1 ||
1175 new_settings.t392 < 2 || 1207 new_settings.t392 < 2 ||
1176 new_settings.n391 < 1 || 1208 new_settings.n391 < 1 ||
diff --git a/drivers/net/wan/hdlc_generic.c b/drivers/net/wan/hdlc_generic.c
index 6ed064cb4469..a63f6a2cc4f7 100644
--- a/drivers/net/wan/hdlc_generic.c
+++ b/drivers/net/wan/hdlc_generic.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Generic HDLC support routines for Linux 2 * Generic HDLC support routines for Linux
3 * 3 *
4 * Copyright (C) 1999 - 2003 Krzysztof Halasa <khc@pm.waw.pl> 4 * Copyright (C) 1999 - 2005 Krzysztof Halasa <khc@pm.waw.pl>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License 7 * under the terms of version 2 of the GNU General Public License
@@ -38,7 +38,7 @@
38#include <linux/hdlc.h> 38#include <linux/hdlc.h>
39 39
40 40
41static const char* version = "HDLC support module revision 1.17"; 41static const char* version = "HDLC support module revision 1.18";
42 42
43#undef DEBUG_LINK 43#undef DEBUG_LINK
44 44
@@ -126,10 +126,13 @@ void hdlc_set_carrier(int on, struct net_device *dev)
126 if (!hdlc->open) 126 if (!hdlc->open)
127 goto carrier_exit; 127 goto carrier_exit;
128 128
129 if (hdlc->carrier) 129 if (hdlc->carrier) {
130 printk(KERN_INFO "%s: Carrier detected\n", dev->name);
130 __hdlc_set_carrier_on(dev); 131 __hdlc_set_carrier_on(dev);
131 else 132 } else {
133 printk(KERN_INFO "%s: Carrier lost\n", dev->name);
132 __hdlc_set_carrier_off(dev); 134 __hdlc_set_carrier_off(dev);
135 }
133 136
134carrier_exit: 137carrier_exit:
135 spin_unlock_irqrestore(&hdlc->state_lock, flags); 138 spin_unlock_irqrestore(&hdlc->state_lock, flags);
@@ -157,8 +160,11 @@ int hdlc_open(struct net_device *dev)
157 160
158 spin_lock_irq(&hdlc->state_lock); 161 spin_lock_irq(&hdlc->state_lock);
159 162
160 if (hdlc->carrier) 163 if (hdlc->carrier) {
164 printk(KERN_INFO "%s: Carrier detected\n", dev->name);
161 __hdlc_set_carrier_on(dev); 165 __hdlc_set_carrier_on(dev);
166 } else
167 printk(KERN_INFO "%s: No carrier\n", dev->name);
162 168
163 hdlc->open = 1; 169 hdlc->open = 1;
164 170
diff --git a/drivers/net/wan/lmc/lmc_main.c b/drivers/net/wan/lmc/lmc_main.c
index 15e545f66cd7..2b948ea397d5 100644
--- a/drivers/net/wan/lmc/lmc_main.c
+++ b/drivers/net/wan/lmc/lmc_main.c
@@ -723,7 +723,7 @@ static void lmc_watchdog (unsigned long data) /*fold00*/
723 /* lmc_reset (sc); Why reset??? The link can go down ok */ 723 /* lmc_reset (sc); Why reset??? The link can go down ok */
724 724
725 /* Inform the world that link has been lost */ 725 /* Inform the world that link has been lost */
726 dev->flags &= ~IFF_RUNNING; 726 netif_carrier_off(dev);
727 } 727 }
728 728
729 /* 729 /*
@@ -736,7 +736,7 @@ static void lmc_watchdog (unsigned long data) /*fold00*/
736 /* lmc_reset (sc); Again why reset??? */ 736 /* lmc_reset (sc); Again why reset??? */
737 737
738 /* Inform the world that link protocol is back up. */ 738 /* Inform the world that link protocol is back up. */
739 dev->flags |= IFF_RUNNING; 739 netif_carrier_on(dev);
740 740
741 /* Now we have to tell the syncppp that we had an outage 741 /* Now we have to tell the syncppp that we had an outage
742 * and that it should deal. Calling sppp_reopen here 742 * and that it should deal. Calling sppp_reopen here
@@ -1168,8 +1168,6 @@ static void lmc_running_reset (struct net_device *dev) /*fold00*/
1168 sc->lmc_media->set_link_status (sc, 1); 1168 sc->lmc_media->set_link_status (sc, 1);
1169 sc->lmc_media->set_status (sc, NULL); 1169 sc->lmc_media->set_status (sc, NULL);
1170 1170
1171 //dev->flags |= IFF_RUNNING;
1172
1173 netif_wake_queue(dev); 1171 netif_wake_queue(dev);
1174 1172
1175 sc->lmc_txfull = 0; 1173 sc->lmc_txfull = 0;
@@ -1233,8 +1231,6 @@ static int lmc_ifdown (struct net_device *dev) /*fold00*/
1233 csr6 &= ~LMC_DEC_SR; /* Turn off the Receive bit */ 1231 csr6 &= ~LMC_DEC_SR; /* Turn off the Receive bit */
1234 LMC_CSR_WRITE (sc, csr_command, csr6); 1232 LMC_CSR_WRITE (sc, csr_command, csr6);
1235 1233
1236 dev->flags &= ~IFF_RUNNING;
1237
1238 sc->stats.rx_missed_errors += 1234 sc->stats.rx_missed_errors +=
1239 LMC_CSR_READ (sc, csr_missed_frames) & 0xffff; 1235 LMC_CSR_READ (sc, csr_missed_frames) & 0xffff;
1240 1236
diff --git a/drivers/net/wan/x25_asy.c b/drivers/net/wan/x25_asy.c
index 1c540d825551..bdf672c48182 100644
--- a/drivers/net/wan/x25_asy.c
+++ b/drivers/net/wan/x25_asy.c
@@ -829,7 +829,7 @@ static void __exit exit_x25_asy(void)
829 } 829 }
830 830
831 kfree(x25_asy_devs); 831 kfree(x25_asy_devs);
832 tty_register_ldisc(N_X25, NULL); 832 tty_unregister_ldisc(N_X25);
833} 833}
834 834
835module_init(init_x25_asy); 835module_init(init_x25_asy);
diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig
index 0aaa12c0c098..1d3231cc471a 100644
--- a/drivers/net/wireless/Kconfig
+++ b/drivers/net/wireless/Kconfig
@@ -323,7 +323,7 @@ config PRISM54
323 For a complete list of supported cards visit <http://prism54.org>. 323 For a complete list of supported cards visit <http://prism54.org>.
324 Here is the latest confirmed list of supported cards: 324 Here is the latest confirmed list of supported cards:
325 325
326 3com OfficeConnect 11g Cardbus Card aka 3CRWE154G72 326 3com OfficeConnect 11g Cardbus Card aka 3CRWE154G72 (version 1)
327 Allnet ALL0271 PCI Card 327 Allnet ALL0271 PCI Card
328 Compex WL54G Cardbus Card 328 Compex WL54G Cardbus Card
329 Corega CG-WLCB54GT Cardbus Card 329 Corega CG-WLCB54GT Cardbus Card
diff --git a/drivers/net/wireless/airo.c b/drivers/net/wireless/airo.c
index 463c789cdc77..d72e0385e4f2 100644
--- a/drivers/net/wireless/airo.c
+++ b/drivers/net/wireless/airo.c
@@ -754,7 +754,7 @@ typedef struct {
754 u8 zero; 754 u8 zero;
755 u8 ssidLen; 755 u8 ssidLen;
756 u8 ssid[32]; 756 u8 ssid[32];
757 u16 rssi; 757 u16 dBm;
758#define CAP_ESS (1<<0) 758#define CAP_ESS (1<<0)
759#define CAP_IBSS (1<<1) 759#define CAP_IBSS (1<<1)
760#define CAP_PRIVACY (1<<4) 760#define CAP_PRIVACY (1<<4)
@@ -1125,6 +1125,9 @@ static int micsetup(struct airo_info *ai);
1125static int encapsulate(struct airo_info *ai, etherHead *pPacket, MICBuffer *buffer, int len); 1125static int encapsulate(struct airo_info *ai, etherHead *pPacket, MICBuffer *buffer, int len);
1126static int decapsulate(struct airo_info *ai, MICBuffer *mic, etherHead *pPacket, u16 payLen); 1126static int decapsulate(struct airo_info *ai, MICBuffer *mic, etherHead *pPacket, u16 payLen);
1127 1127
1128static u8 airo_rssi_to_dbm (tdsRssiEntry *rssi_rid, u8 rssi);
1129static u8 airo_dbm_to_pct (tdsRssiEntry *rssi_rid, u8 dbm);
1130
1128#include <linux/crypto.h> 1131#include <linux/crypto.h>
1129#endif 1132#endif
1130 1133
@@ -1713,6 +1716,7 @@ static int readBSSListRid(struct airo_info *ai, int first,
1713 list->fh.dwell = le16_to_cpu(list->fh.dwell); 1716 list->fh.dwell = le16_to_cpu(list->fh.dwell);
1714 list->dsChannel = le16_to_cpu(list->dsChannel); 1717 list->dsChannel = le16_to_cpu(list->dsChannel);
1715 list->atimWindow = le16_to_cpu(list->atimWindow); 1718 list->atimWindow = le16_to_cpu(list->atimWindow);
1719 list->dBm = le16_to_cpu(list->dBm);
1716 return rc; 1720 return rc;
1717} 1721}
1718 1722
@@ -2914,7 +2918,7 @@ static int airo_thread(void *data) {
2914 flush_signals(current); 2918 flush_signals(current);
2915 2919
2916 /* make swsusp happy with our thread */ 2920 /* make swsusp happy with our thread */
2917 try_to_freeze(PF_FREEZE); 2921 try_to_freeze();
2918 2922
2919 if (test_bit(JOB_DIE, &ai->flags)) 2923 if (test_bit(JOB_DIE, &ai->flags))
2920 break; 2924 break;
@@ -3245,7 +3249,10 @@ badrx:
3245 wstats.level = 0x100 - apriv->rssi[hdr.rssi[1]].rssidBm; 3249 wstats.level = 0x100 - apriv->rssi[hdr.rssi[1]].rssidBm;
3246 else 3250 else
3247 wstats.level = (hdr.rssi[1] + 321) / 2; 3251 wstats.level = (hdr.rssi[1] + 321) / 2;
3248 wstats.updated = 3; 3252 wstats.noise = apriv->wstats.qual.noise;
3253 wstats.updated = IW_QUAL_LEVEL_UPDATED
3254 | IW_QUAL_QUAL_UPDATED
3255 | IW_QUAL_NOISE_UPDATED;
3249 /* Update spy records */ 3256 /* Update spy records */
3250 wireless_spy_update(dev, sa, &wstats); 3257 wireless_spy_update(dev, sa, &wstats);
3251 } 3258 }
@@ -3588,7 +3595,10 @@ void mpi_receive_802_11 (struct airo_info *ai)
3588 wstats.level = 0x100 - ai->rssi[hdr.rssi[1]].rssidBm; 3595 wstats.level = 0x100 - ai->rssi[hdr.rssi[1]].rssidBm;
3589 else 3596 else
3590 wstats.level = (hdr.rssi[1] + 321) / 2; 3597 wstats.level = (hdr.rssi[1] + 321) / 2;
3591 wstats.updated = 3; 3598 wstats.noise = ai->wstats.qual.noise;
3599 wstats.updated = IW_QUAL_QUAL_UPDATED
3600 | IW_QUAL_LEVEL_UPDATED
3601 | IW_QUAL_NOISE_UPDATED;
3592 /* Update spy records */ 3602 /* Update spy records */
3593 wireless_spy_update(ai->dev, sa, &wstats); 3603 wireless_spy_update(ai->dev, sa, &wstats);
3594 } 3604 }
@@ -3679,7 +3689,7 @@ static u16 setup_card(struct airo_info *ai, u8 *mac, int lock)
3679 status = PC4500_readrid(ai,RID_RSSI,&rssi_rid,sizeof(rssi_rid),lock); 3689 status = PC4500_readrid(ai,RID_RSSI,&rssi_rid,sizeof(rssi_rid),lock);
3680 if ( status == SUCCESS ) { 3690 if ( status == SUCCESS ) {
3681 if (ai->rssi || (ai->rssi = kmalloc(512, GFP_KERNEL)) != NULL) 3691 if (ai->rssi || (ai->rssi = kmalloc(512, GFP_KERNEL)) != NULL)
3682 memcpy(ai->rssi, (u8*)&rssi_rid + 2, 512); 3692 memcpy(ai->rssi, (u8*)&rssi_rid + 2, 512); /* Skip RID length member */
3683 } 3693 }
3684 else { 3694 else {
3685 if (ai->rssi) { 3695 if (ai->rssi) {
@@ -5348,7 +5358,7 @@ static int proc_BSSList_open( struct inode *inode, struct file *file ) {
5348 (int)BSSList_rid.bssid[5], 5358 (int)BSSList_rid.bssid[5],
5349 (int)BSSList_rid.ssidLen, 5359 (int)BSSList_rid.ssidLen,
5350 BSSList_rid.ssid, 5360 BSSList_rid.ssid,
5351 (int)BSSList_rid.rssi); 5361 (int)BSSList_rid.dBm);
5352 ptr += sprintf(ptr, " channel = %d %s %s %s %s\n", 5362 ptr += sprintf(ptr, " channel = %d %s %s %s %s\n",
5353 (int)BSSList_rid.dsChannel, 5363 (int)BSSList_rid.dsChannel,
5354 BSSList_rid.cap & CAP_ESS ? "ESS" : "", 5364 BSSList_rid.cap & CAP_ESS ? "ESS" : "",
@@ -5593,6 +5603,29 @@ static void __exit airo_cleanup_module( void )
5593 * would not work at all... - Jean II 5603 * would not work at all... - Jean II
5594 */ 5604 */
5595 5605
5606static u8 airo_rssi_to_dbm (tdsRssiEntry *rssi_rid, u8 rssi)
5607{
5608 if( !rssi_rid )
5609 return 0;
5610
5611 return (0x100 - rssi_rid[rssi].rssidBm);
5612}
5613
5614static u8 airo_dbm_to_pct (tdsRssiEntry *rssi_rid, u8 dbm)
5615{
5616 int i;
5617
5618 if( !rssi_rid )
5619 return 0;
5620
5621 for( i = 0; i < 256; i++ )
5622 if (rssi_rid[i].rssidBm == dbm)
5623 return rssi_rid[i].rssipct;
5624
5625 return 0;
5626}
5627
5628
5596static int airo_get_quality (StatusRid *status_rid, CapabilityRid *cap_rid) 5629static int airo_get_quality (StatusRid *status_rid, CapabilityRid *cap_rid)
5597{ 5630{
5598 int quality = 0; 5631 int quality = 0;
@@ -6443,11 +6476,29 @@ static int airo_get_range(struct net_device *dev,
6443 } 6476 }
6444 range->num_frequency = k; 6477 range->num_frequency = k;
6445 6478
6479 range->sensitivity = 65535;
6480
6446 /* Hum... Should put the right values there */ 6481 /* Hum... Should put the right values there */
6447 range->max_qual.qual = airo_get_max_quality(&cap_rid); 6482 if (local->rssi)
6448 range->max_qual.level = 0x100 - 120; /* -120 dBm */ 6483 range->max_qual.qual = 100; /* % */
6484 else
6485 range->max_qual.qual = airo_get_max_quality(&cap_rid);
6486 range->max_qual.level = 0; /* 0 means we use dBm */
6449 range->max_qual.noise = 0; 6487 range->max_qual.noise = 0;
6450 range->sensitivity = 65535; 6488 range->max_qual.updated = 0;
6489
6490 /* Experimental measurements - boundary 11/5.5 Mb/s */
6491 /* Note : with or without the (local->rssi), results
6492 * are somewhat different. - Jean II */
6493 if (local->rssi) {
6494 range->avg_qual.qual = 50; /* % */
6495 range->avg_qual.level = 186; /* -70 dBm */
6496 } else {
6497 range->avg_qual.qual = airo_get_avg_quality(&cap_rid);
6498 range->avg_qual.level = 176; /* -80 dBm */
6499 }
6500 range->avg_qual.noise = 0;
6501 range->avg_qual.updated = 0;
6451 6502
6452 for(i = 0 ; i < 8 ; i++) { 6503 for(i = 0 ; i < 8 ; i++) {
6453 range->bitrate[i] = cap_rid.supportedRates[i] * 500000; 6504 range->bitrate[i] = cap_rid.supportedRates[i] * 500000;
@@ -6508,15 +6559,6 @@ static int airo_get_range(struct net_device *dev,
6508 range->max_retry = 65535; 6559 range->max_retry = 65535;
6509 range->min_r_time = 1024; 6560 range->min_r_time = 1024;
6510 range->max_r_time = 65535 * 1024; 6561 range->max_r_time = 65535 * 1024;
6511 /* Experimental measurements - boundary 11/5.5 Mb/s */
6512 /* Note : with or without the (local->rssi), results
6513 * are somewhat different. - Jean II */
6514 range->avg_qual.qual = airo_get_avg_quality(&cap_rid);
6515 if (local->rssi)
6516 range->avg_qual.level = 186; /* -70 dBm */
6517 else
6518 range->avg_qual.level = 176; /* -80 dBm */
6519 range->avg_qual.noise = 0;
6520 6562
6521 /* Event capability (kernel + driver) */ 6563 /* Event capability (kernel + driver) */
6522 range->event_capa[0] = (IW_EVENT_CAPA_K_0 | 6564 range->event_capa[0] = (IW_EVENT_CAPA_K_0 |
@@ -6676,12 +6718,18 @@ static int airo_get_aplist(struct net_device *dev,
6676 loseSync = 0; 6718 loseSync = 0;
6677 memcpy(address[i].sa_data, BSSList.bssid, ETH_ALEN); 6719 memcpy(address[i].sa_data, BSSList.bssid, ETH_ALEN);
6678 address[i].sa_family = ARPHRD_ETHER; 6720 address[i].sa_family = ARPHRD_ETHER;
6679 if (local->rssi) 6721 if (local->rssi) {
6680 qual[i].level = 0x100 - local->rssi[BSSList.rssi].rssidBm; 6722 qual[i].level = 0x100 - BSSList.dBm;
6681 else 6723 qual[i].qual = airo_dbm_to_pct( local->rssi, BSSList.dBm );
6682 qual[i].level = (BSSList.rssi + 321) / 2; 6724 qual[i].updated = IW_QUAL_QUAL_UPDATED;
6683 qual[i].qual = qual[i].noise = 0; 6725 } else {
6684 qual[i].updated = 2; 6726 qual[i].level = (BSSList.dBm + 321) / 2;
6727 qual[i].qual = 0;
6728 qual[i].updated = IW_QUAL_QUAL_INVALID;
6729 }
6730 qual[i].noise = local->wstats.qual.noise;
6731 qual[i].updated = IW_QUAL_LEVEL_UPDATED
6732 | IW_QUAL_NOISE_UPDATED;
6685 if (BSSList.index == 0xffff) 6733 if (BSSList.index == 0xffff)
6686 break; 6734 break;
6687 } 6735 }
@@ -6760,7 +6808,7 @@ static int airo_set_scan(struct net_device *dev,
6760static inline char *airo_translate_scan(struct net_device *dev, 6808static inline char *airo_translate_scan(struct net_device *dev,
6761 char *current_ev, 6809 char *current_ev,
6762 char *end_buf, 6810 char *end_buf,
6763 BSSListRid *list) 6811 BSSListRid *bss)
6764{ 6812{
6765 struct airo_info *ai = dev->priv; 6813 struct airo_info *ai = dev->priv;
6766 struct iw_event iwe; /* Temporary buffer */ 6814 struct iw_event iwe; /* Temporary buffer */
@@ -6771,22 +6819,22 @@ static inline char *airo_translate_scan(struct net_device *dev,
6771 /* First entry *MUST* be the AP MAC address */ 6819 /* First entry *MUST* be the AP MAC address */
6772 iwe.cmd = SIOCGIWAP; 6820 iwe.cmd = SIOCGIWAP;
6773 iwe.u.ap_addr.sa_family = ARPHRD_ETHER; 6821 iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
6774 memcpy(iwe.u.ap_addr.sa_data, list->bssid, ETH_ALEN); 6822 memcpy(iwe.u.ap_addr.sa_data, bss->bssid, ETH_ALEN);
6775 current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, IW_EV_ADDR_LEN); 6823 current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, IW_EV_ADDR_LEN);
6776 6824
6777 /* Other entries will be displayed in the order we give them */ 6825 /* Other entries will be displayed in the order we give them */
6778 6826
6779 /* Add the ESSID */ 6827 /* Add the ESSID */
6780 iwe.u.data.length = list->ssidLen; 6828 iwe.u.data.length = bss->ssidLen;
6781 if(iwe.u.data.length > 32) 6829 if(iwe.u.data.length > 32)
6782 iwe.u.data.length = 32; 6830 iwe.u.data.length = 32;
6783 iwe.cmd = SIOCGIWESSID; 6831 iwe.cmd = SIOCGIWESSID;
6784 iwe.u.data.flags = 1; 6832 iwe.u.data.flags = 1;
6785 current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, list->ssid); 6833 current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, bss->ssid);
6786 6834
6787 /* Add mode */ 6835 /* Add mode */
6788 iwe.cmd = SIOCGIWMODE; 6836 iwe.cmd = SIOCGIWMODE;
6789 capabilities = le16_to_cpu(list->cap); 6837 capabilities = le16_to_cpu(bss->cap);
6790 if(capabilities & (CAP_ESS | CAP_IBSS)) { 6838 if(capabilities & (CAP_ESS | CAP_IBSS)) {
6791 if(capabilities & CAP_ESS) 6839 if(capabilities & CAP_ESS)
6792 iwe.u.mode = IW_MODE_MASTER; 6840 iwe.u.mode = IW_MODE_MASTER;
@@ -6797,19 +6845,25 @@ static inline char *airo_translate_scan(struct net_device *dev,
6797 6845
6798 /* Add frequency */ 6846 /* Add frequency */
6799 iwe.cmd = SIOCGIWFREQ; 6847 iwe.cmd = SIOCGIWFREQ;
6800 iwe.u.freq.m = le16_to_cpu(list->dsChannel); 6848 iwe.u.freq.m = le16_to_cpu(bss->dsChannel);
6801 iwe.u.freq.m = frequency_list[iwe.u.freq.m] * 100000; 6849 iwe.u.freq.m = frequency_list[iwe.u.freq.m] * 100000;
6802 iwe.u.freq.e = 1; 6850 iwe.u.freq.e = 1;
6803 current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, IW_EV_FREQ_LEN); 6851 current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, IW_EV_FREQ_LEN);
6804 6852
6805 /* Add quality statistics */ 6853 /* Add quality statistics */
6806 iwe.cmd = IWEVQUAL; 6854 iwe.cmd = IWEVQUAL;
6807 if (ai->rssi) 6855 if (ai->rssi) {
6808 iwe.u.qual.level = 0x100 - ai->rssi[list->rssi].rssidBm; 6856 iwe.u.qual.level = 0x100 - bss->dBm;
6809 else 6857 iwe.u.qual.qual = airo_dbm_to_pct( ai->rssi, bss->dBm );
6810 iwe.u.qual.level = (list->rssi + 321) / 2; 6858 iwe.u.qual.updated = IW_QUAL_QUAL_UPDATED;
6811 iwe.u.qual.noise = 0; 6859 } else {
6812 iwe.u.qual.qual = 0; 6860 iwe.u.qual.level = (bss->dBm + 321) / 2;
6861 iwe.u.qual.qual = 0;
6862 iwe.u.qual.updated = IW_QUAL_QUAL_INVALID;
6863 }
6864 iwe.u.qual.noise = ai->wstats.qual.noise;
6865 iwe.u.qual.updated = IW_QUAL_LEVEL_UPDATED
6866 | IW_QUAL_NOISE_UPDATED;
6813 current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, IW_EV_QUAL_LEN); 6867 current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, IW_EV_QUAL_LEN);
6814 6868
6815 /* Add encryption capability */ 6869 /* Add encryption capability */
@@ -6819,7 +6873,7 @@ static inline char *airo_translate_scan(struct net_device *dev,
6819 else 6873 else
6820 iwe.u.data.flags = IW_ENCODE_DISABLED; 6874 iwe.u.data.flags = IW_ENCODE_DISABLED;
6821 iwe.u.data.length = 0; 6875 iwe.u.data.length = 0;
6822 current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, list->ssid); 6876 current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, bss->ssid);
6823 6877
6824 /* Rate : stuffing multiple values in a single event require a bit 6878 /* Rate : stuffing multiple values in a single event require a bit
6825 * more of magic - Jean II */ 6879 * more of magic - Jean II */
@@ -6831,10 +6885,10 @@ static inline char *airo_translate_scan(struct net_device *dev,
6831 /* Max 8 values */ 6885 /* Max 8 values */
6832 for(i = 0 ; i < 8 ; i++) { 6886 for(i = 0 ; i < 8 ; i++) {
6833 /* NULL terminated */ 6887 /* NULL terminated */
6834 if(list->rates[i] == 0) 6888 if(bss->rates[i] == 0)
6835 break; 6889 break;
6836 /* Bit rate given in 500 kb/s units (+ 0x80) */ 6890 /* Bit rate given in 500 kb/s units (+ 0x80) */
6837 iwe.u.bitrate.value = ((list->rates[i] & 0x7f) * 500000); 6891 iwe.u.bitrate.value = ((bss->rates[i] & 0x7f) * 500000);
6838 /* Add new value to event */ 6892 /* Add new value to event */
6839 current_val = iwe_stream_add_value(current_ev, current_val, end_buf, &iwe, IW_EV_PARAM_LEN); 6893 current_val = iwe_stream_add_value(current_ev, current_val, end_buf, &iwe, IW_EV_PARAM_LEN);
6840 } 6894 }
@@ -7153,18 +7207,22 @@ static void airo_read_wireless_stats(struct airo_info *local)
7153 /* The status */ 7207 /* The status */
7154 local->wstats.status = status_rid.mode; 7208 local->wstats.status = status_rid.mode;
7155 7209
7156 /* Signal quality and co. But where is the noise level ??? */ 7210 /* Signal quality and co */
7157 local->wstats.qual.qual = airo_get_quality(&status_rid, &cap_rid); 7211 if (local->rssi) {
7158 if (local->rssi) 7212 local->wstats.qual.level = airo_rssi_to_dbm( local->rssi, status_rid.sigQuality );
7159 local->wstats.qual.level = 0x100 - local->rssi[status_rid.sigQuality].rssidBm; 7213 /* normalizedSignalStrength appears to be a percentage */
7160 else 7214 local->wstats.qual.qual = status_rid.normalizedSignalStrength;
7215 } else {
7161 local->wstats.qual.level = (status_rid.normalizedSignalStrength + 321) / 2; 7216 local->wstats.qual.level = (status_rid.normalizedSignalStrength + 321) / 2;
7217 local->wstats.qual.qual = airo_get_quality(&status_rid, &cap_rid);
7218 }
7219 local->wstats.qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_UPDATED;
7162 if (status_rid.len >= 124) { 7220 if (status_rid.len >= 124) {
7163 local->wstats.qual.noise = 256 - status_rid.noisedBm; 7221 local->wstats.qual.noise = 0x100 - status_rid.noisedBm;
7164 local->wstats.qual.updated = 7; 7222 local->wstats.qual.updated |= IW_QUAL_NOISE_UPDATED;
7165 } else { 7223 } else {
7166 local->wstats.qual.noise = 0; 7224 local->wstats.qual.noise = 0;
7167 local->wstats.qual.updated = 3; 7225 local->wstats.qual.updated |= IW_QUAL_NOISE_INVALID;
7168 } 7226 }
7169 7227
7170 /* Packets discarded in the wireless adapter due to wireless 7228 /* Packets discarded in the wireless adapter due to wireless
diff --git a/drivers/net/wireless/atmel_cs.c b/drivers/net/wireless/atmel_cs.c
index a91b507e0a7a..a4ed28d9c783 100644
--- a/drivers/net/wireless/atmel_cs.c
+++ b/drivers/net/wireless/atmel_cs.c
@@ -321,6 +321,7 @@ static struct {
321 { 0x01bf, 0x3302, NULL, ATMEL_FW_TYPE_502E, "Belkin F5D6020-V2" }, 321 { 0x01bf, 0x3302, NULL, ATMEL_FW_TYPE_502E, "Belkin F5D6020-V2" },
322 { 0, 0, "BT/Voyager 1020 Laptop Adapter", ATMEL_FW_TYPE_502, "BT Voyager 1020" }, 322 { 0, 0, "BT/Voyager 1020 Laptop Adapter", ATMEL_FW_TYPE_502, "BT Voyager 1020" },
323 { 0, 0, "IEEE 802.11b/Wireless LAN PC Card", ATMEL_FW_TYPE_502, "Siemens Gigaset PC Card II" }, 323 { 0, 0, "IEEE 802.11b/Wireless LAN PC Card", ATMEL_FW_TYPE_502, "Siemens Gigaset PC Card II" },
324 { 0, 0, "IEEE 802.11b/Wireless LAN Card S", ATMEL_FW_TYPE_504_2958, "Siemens Gigaset PC Card II" },
324 { 0, 0, "CNet/CNWLC 11Mbps Wireless PC Card V-5", ATMEL_FW_TYPE_502E, "CNet CNWLC-811ARL" }, 325 { 0, 0, "CNet/CNWLC 11Mbps Wireless PC Card V-5", ATMEL_FW_TYPE_502E, "CNet CNWLC-811ARL" },
325 { 0, 0, "Wireless/PC_CARD", ATMEL_FW_TYPE_502D, "Planet WL-3552" }, 326 { 0, 0, "Wireless/PC_CARD", ATMEL_FW_TYPE_502D, "Planet WL-3552" },
326 { 0, 0, "OEM/11Mbps Wireless LAN PC Card V-3", ATMEL_FW_TYPE_502, "OEM 11Mbps WLAN PCMCIA Card" }, 327 { 0, 0, "OEM/11Mbps Wireless LAN PC Card V-3", ATMEL_FW_TYPE_502, "OEM 11Mbps WLAN PCMCIA Card" },
diff --git a/drivers/net/wireless/orinoco.c b/drivers/net/wireless/orinoco.c
index a3a32430ae9d..b1078baa1d5e 100644
--- a/drivers/net/wireless/orinoco.c
+++ b/drivers/net/wireless/orinoco.c
@@ -492,6 +492,9 @@ EXPORT_SYMBOL(orinoco_debug);
492static int suppress_linkstatus; /* = 0 */ 492static int suppress_linkstatus; /* = 0 */
493module_param(suppress_linkstatus, bool, 0644); 493module_param(suppress_linkstatus, bool, 0644);
494MODULE_PARM_DESC(suppress_linkstatus, "Don't log link status changes"); 494MODULE_PARM_DESC(suppress_linkstatus, "Don't log link status changes");
495static int ignore_disconnect; /* = 0 */
496module_param(ignore_disconnect, int, 0644);
497MODULE_PARM_DESC(ignore_disconnect, "Don't report lost link to the network layer");
495 498
496/********************************************************************/ 499/********************************************************************/
497/* Compile time configuration and compatibility stuff */ 500/* Compile time configuration and compatibility stuff */
@@ -604,7 +607,6 @@ struct hermes_rx_descriptor {
604static int orinoco_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 607static int orinoco_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
605static int __orinoco_program_rids(struct net_device *dev); 608static int __orinoco_program_rids(struct net_device *dev);
606static void __orinoco_set_multicast_list(struct net_device *dev); 609static void __orinoco_set_multicast_list(struct net_device *dev);
607static int orinoco_debug_dump_recs(struct net_device *dev);
608 610
609/********************************************************************/ 611/********************************************************************/
610/* Internal helper functions */ 612/* Internal helper functions */
@@ -655,7 +657,7 @@ static int orinoco_open(struct net_device *dev)
655 return err; 657 return err;
656} 658}
657 659
658int orinoco_stop(struct net_device *dev) 660static int orinoco_stop(struct net_device *dev)
659{ 661{
660 struct orinoco_private *priv = netdev_priv(dev); 662 struct orinoco_private *priv = netdev_priv(dev);
661 int err = 0; 663 int err = 0;
@@ -686,7 +688,7 @@ static struct iw_statistics *orinoco_get_wireless_stats(struct net_device *dev)
686 struct orinoco_private *priv = netdev_priv(dev); 688 struct orinoco_private *priv = netdev_priv(dev);
687 hermes_t *hw = &priv->hw; 689 hermes_t *hw = &priv->hw;
688 struct iw_statistics *wstats = &priv->wstats; 690 struct iw_statistics *wstats = &priv->wstats;
689 int err = 0; 691 int err;
690 unsigned long flags; 692 unsigned long flags;
691 693
692 if (! netif_device_present(dev)) { 694 if (! netif_device_present(dev)) {
@@ -695,9 +697,21 @@ static struct iw_statistics *orinoco_get_wireless_stats(struct net_device *dev)
695 return NULL; /* FIXME: Can we do better than this? */ 697 return NULL; /* FIXME: Can we do better than this? */
696 } 698 }
697 699
700 /* If busy, return the old stats. Returning NULL may cause
701 * the interface to disappear from /proc/net/wireless */
698 if (orinoco_lock(priv, &flags) != 0) 702 if (orinoco_lock(priv, &flags) != 0)
699 return NULL; /* FIXME: Erg, we've been signalled, how 703 return wstats;
700 * do we propagate this back up? */ 704
705 /* We can't really wait for the tallies inquiry command to
706 * complete, so we just use the previous results and trigger
707 * a new tallies inquiry command for next time - Jean II */
708 /* FIXME: Really we should wait for the inquiry to come back -
709 * as it is the stats we give don't make a whole lot of sense.
710 * Unfortunately, it's not clear how to do that within the
711 * wireless extensions framework: I think we're in user
712 * context, but a lock seems to be held by the time we get in
713 * here so we're not safe to sleep here. */
714 hermes_inquire(hw, HERMES_INQ_TALLIES);
701 715
702 if (priv->iw_mode == IW_MODE_ADHOC) { 716 if (priv->iw_mode == IW_MODE_ADHOC) {
703 memset(&wstats->qual, 0, sizeof(wstats->qual)); 717 memset(&wstats->qual, 0, sizeof(wstats->qual));
@@ -716,25 +730,16 @@ static struct iw_statistics *orinoco_get_wireless_stats(struct net_device *dev)
716 730
717 err = HERMES_READ_RECORD(hw, USER_BAP, 731 err = HERMES_READ_RECORD(hw, USER_BAP,
718 HERMES_RID_COMMSQUALITY, &cq); 732 HERMES_RID_COMMSQUALITY, &cq);
719 733
720 wstats->qual.qual = (int)le16_to_cpu(cq.qual); 734 if (!err) {
721 wstats->qual.level = (int)le16_to_cpu(cq.signal) - 0x95; 735 wstats->qual.qual = (int)le16_to_cpu(cq.qual);
722 wstats->qual.noise = (int)le16_to_cpu(cq.noise) - 0x95; 736 wstats->qual.level = (int)le16_to_cpu(cq.signal) - 0x95;
723 wstats->qual.updated = 7; 737 wstats->qual.noise = (int)le16_to_cpu(cq.noise) - 0x95;
738 wstats->qual.updated = 7;
739 }
724 } 740 }
725 741
726 /* We can't really wait for the tallies inquiry command to
727 * complete, so we just use the previous results and trigger
728 * a new tallies inquiry command for next time - Jean II */
729 /* FIXME: We're in user context (I think?), so we should just
730 wait for the tallies to come through */
731 err = hermes_inquire(hw, HERMES_INQ_TALLIES);
732
733 orinoco_unlock(priv, &flags); 742 orinoco_unlock(priv, &flags);
734
735 if (err)
736 return NULL;
737
738 return wstats; 743 return wstats;
739} 744}
740 745
@@ -1275,9 +1280,10 @@ static void __orinoco_ev_info(struct net_device *dev, hermes_t *hw)
1275 len = sizeof(tallies); 1280 len = sizeof(tallies);
1276 } 1281 }
1277 1282
1278 /* Read directly the data (no seek) */ 1283 err = hermes_bap_pread(hw, IRQ_BAP, &tallies, len,
1279 hermes_read_words(hw, HERMES_DATA1, (void *) &tallies, 1284 infofid, sizeof(info));
1280 len / 2); /* FIXME: blech! */ 1285 if (err)
1286 break;
1281 1287
1282 /* Increment our various counters */ 1288 /* Increment our various counters */
1283 /* wstats->discard.nwid - no wrong BSSID stuff */ 1289 /* wstats->discard.nwid - no wrong BSSID stuff */
@@ -1307,8 +1313,10 @@ static void __orinoco_ev_info(struct net_device *dev, hermes_t *hw)
1307 break; 1313 break;
1308 } 1314 }
1309 1315
1310 hermes_read_words(hw, HERMES_DATA1, (void *) &linkstatus, 1316 err = hermes_bap_pread(hw, IRQ_BAP, &linkstatus, len,
1311 len / 2); 1317 infofid, sizeof(info));
1318 if (err)
1319 break;
1312 newstatus = le16_to_cpu(linkstatus.linkstatus); 1320 newstatus = le16_to_cpu(linkstatus.linkstatus);
1313 1321
1314 connected = (newstatus == HERMES_LINKSTATUS_CONNECTED) 1322 connected = (newstatus == HERMES_LINKSTATUS_CONNECTED)
@@ -1317,7 +1325,7 @@ static void __orinoco_ev_info(struct net_device *dev, hermes_t *hw)
1317 1325
1318 if (connected) 1326 if (connected)
1319 netif_carrier_on(dev); 1327 netif_carrier_on(dev);
1320 else 1328 else if (!ignore_disconnect)
1321 netif_carrier_off(dev); 1329 netif_carrier_off(dev);
1322 1330
1323 if (newstatus != priv->last_linkstatus) 1331 if (newstatus != priv->last_linkstatus)
@@ -1350,6 +1358,8 @@ int __orinoco_up(struct net_device *dev)
1350 struct hermes *hw = &priv->hw; 1358 struct hermes *hw = &priv->hw;
1351 int err; 1359 int err;
1352 1360
1361 netif_carrier_off(dev); /* just to make sure */
1362
1353 err = __orinoco_program_rids(dev); 1363 err = __orinoco_program_rids(dev);
1354 if (err) { 1364 if (err) {
1355 printk(KERN_ERR "%s: Error %d configuring card\n", 1365 printk(KERN_ERR "%s: Error %d configuring card\n",
@@ -1413,7 +1423,7 @@ int orinoco_reinit_firmware(struct net_device *dev)
1413 return err; 1423 return err;
1414 1424
1415 err = hermes_allocate(hw, priv->nicbuf_size, &priv->txfid); 1425 err = hermes_allocate(hw, priv->nicbuf_size, &priv->txfid);
1416 if (err == -EIO) { 1426 if (err == -EIO && priv->nicbuf_size > TX_NICBUF_SIZE_BUG) {
1417 /* Try workaround for old Symbol firmware bug */ 1427 /* Try workaround for old Symbol firmware bug */
1418 printk(KERN_WARNING "%s: firmware ALLOC bug detected " 1428 printk(KERN_WARNING "%s: firmware ALLOC bug detected "
1419 "(old Symbol firmware?). Trying to work around... ", 1429 "(old Symbol firmware?). Trying to work around... ",
@@ -1610,17 +1620,15 @@ static int __orinoco_program_rids(struct net_device *dev)
1610 return err; 1620 return err;
1611 } 1621 }
1612 /* Set the channel/frequency */ 1622 /* Set the channel/frequency */
1613 if (priv->channel == 0) { 1623 if (priv->channel != 0 && priv->iw_mode != IW_MODE_INFRA) {
1614 printk(KERN_DEBUG "%s: Channel is 0 in __orinoco_program_rids()\n", dev->name); 1624 err = hermes_write_wordrec(hw, USER_BAP,
1615 if (priv->createibss) 1625 HERMES_RID_CNFOWNCHANNEL,
1616 priv->channel = 10; 1626 priv->channel);
1617 } 1627 if (err) {
1618 err = hermes_write_wordrec(hw, USER_BAP, HERMES_RID_CNFOWNCHANNEL, 1628 printk(KERN_ERR "%s: Error %d setting channel %d\n",
1619 priv->channel); 1629 dev->name, err, priv->channel);
1620 if (err) { 1630 return err;
1621 printk(KERN_ERR "%s: Error %d setting channel\n", 1631 }
1622 dev->name, err);
1623 return err;
1624 } 1632 }
1625 1633
1626 if (priv->has_ibss) { 1634 if (priv->has_ibss) {
@@ -1916,7 +1924,7 @@ static void orinoco_reset(struct net_device *dev)
1916{ 1924{
1917 struct orinoco_private *priv = netdev_priv(dev); 1925 struct orinoco_private *priv = netdev_priv(dev);
1918 struct hermes *hw = &priv->hw; 1926 struct hermes *hw = &priv->hw;
1919 int err = 0; 1927 int err;
1920 unsigned long flags; 1928 unsigned long flags;
1921 1929
1922 if (orinoco_lock(priv, &flags) != 0) 1930 if (orinoco_lock(priv, &flags) != 0)
@@ -1938,20 +1946,20 @@ static void orinoco_reset(struct net_device *dev)
1938 1946
1939 orinoco_unlock(priv, &flags); 1947 orinoco_unlock(priv, &flags);
1940 1948
1941 if (priv->hard_reset) 1949 if (priv->hard_reset) {
1942 err = (*priv->hard_reset)(priv); 1950 err = (*priv->hard_reset)(priv);
1943 if (err) { 1951 if (err) {
1944 printk(KERN_ERR "%s: orinoco_reset: Error %d " 1952 printk(KERN_ERR "%s: orinoco_reset: Error %d "
1945 "performing hard reset\n", dev->name, err); 1953 "performing hard reset\n", dev->name, err);
1946 /* FIXME: shutdown of some sort */ 1954 goto disable;
1947 return; 1955 }
1948 } 1956 }
1949 1957
1950 err = orinoco_reinit_firmware(dev); 1958 err = orinoco_reinit_firmware(dev);
1951 if (err) { 1959 if (err) {
1952 printk(KERN_ERR "%s: orinoco_reset: Error %d re-initializing firmware\n", 1960 printk(KERN_ERR "%s: orinoco_reset: Error %d re-initializing firmware\n",
1953 dev->name, err); 1961 dev->name, err);
1954 return; 1962 goto disable;
1955 } 1963 }
1956 1964
1957 spin_lock_irq(&priv->lock); /* This has to be called from user context */ 1965 spin_lock_irq(&priv->lock); /* This has to be called from user context */
@@ -1972,6 +1980,10 @@ static void orinoco_reset(struct net_device *dev)
1972 spin_unlock_irq(&priv->lock); 1980 spin_unlock_irq(&priv->lock);
1973 1981
1974 return; 1982 return;
1983 disable:
1984 hermes_set_irqmask(hw, 0);
1985 netif_device_detach(dev);
1986 printk(KERN_ERR "%s: Device has been disabled!\n", dev->name);
1975} 1987}
1976 1988
1977/********************************************************************/ 1989/********************************************************************/
@@ -2056,7 +2068,7 @@ irqreturn_t orinoco_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2056 if (events & HERMES_EV_ALLOC) 2068 if (events & HERMES_EV_ALLOC)
2057 __orinoco_ev_alloc(dev, hw); 2069 __orinoco_ev_alloc(dev, hw);
2058 2070
2059 hermes_write_regn(hw, EVACK, events); 2071 hermes_write_regn(hw, EVACK, evstat);
2060 2072
2061 evstat = hermes_read_regn(hw, EVSTAT); 2073 evstat = hermes_read_regn(hw, EVSTAT);
2062 events = evstat & hw->inten; 2074 events = evstat & hw->inten;
@@ -2215,6 +2227,8 @@ static int determine_firmware(struct net_device *dev)
2215 firmver >= 0x31000; 2227 firmver >= 0x31000;
2216 priv->has_preamble = (firmver >= 0x20000); 2228 priv->has_preamble = (firmver >= 0x20000);
2217 priv->ibss_port = 4; 2229 priv->ibss_port = 4;
2230 priv->broken_disableport = (firmver == 0x25013) ||
2231 (firmver >= 0x30000 && firmver <= 0x31000);
2218 /* Tested with Intel firmware : 0x20015 => Jean II */ 2232 /* Tested with Intel firmware : 0x20015 => Jean II */
2219 /* Tested with 3Com firmware : 0x15012 & 0x22001 => Jean II */ 2233 /* Tested with 3Com firmware : 0x15012 & 0x22001 => Jean II */
2220 break; 2234 break;
@@ -2267,7 +2281,7 @@ static int orinoco_init(struct net_device *dev)
2267 priv->nicbuf_size = IEEE802_11_FRAME_LEN + ETH_HLEN; 2281 priv->nicbuf_size = IEEE802_11_FRAME_LEN + ETH_HLEN;
2268 2282
2269 /* Initialize the firmware */ 2283 /* Initialize the firmware */
2270 err = hermes_init(hw); 2284 err = orinoco_reinit_firmware(dev);
2271 if (err != 0) { 2285 if (err != 0) {
2272 printk(KERN_ERR "%s: failed to initialize firmware (err = %d)\n", 2286 printk(KERN_ERR "%s: failed to initialize firmware (err = %d)\n",
2273 dev->name, err); 2287 dev->name, err);
@@ -2400,31 +2414,12 @@ static int orinoco_init(struct net_device *dev)
2400 /* By default use IEEE/IBSS ad-hoc mode if we have it */ 2414 /* By default use IEEE/IBSS ad-hoc mode if we have it */
2401 priv->prefer_port3 = priv->has_port3 && (! priv->has_ibss); 2415 priv->prefer_port3 = priv->has_port3 && (! priv->has_ibss);
2402 set_port_type(priv); 2416 set_port_type(priv);
2403 priv->channel = 10; /* default channel, more-or-less arbitrary */ 2417 priv->channel = 0; /* use firmware default */
2404 2418
2405 priv->promiscuous = 0; 2419 priv->promiscuous = 0;
2406 priv->wep_on = 0; 2420 priv->wep_on = 0;
2407 priv->tx_key = 0; 2421 priv->tx_key = 0;
2408 2422
2409 err = hermes_allocate(hw, priv->nicbuf_size, &priv->txfid);
2410 if (err == -EIO) {
2411 /* Try workaround for old Symbol firmware bug */
2412 printk(KERN_WARNING "%s: firmware ALLOC bug detected "
2413 "(old Symbol firmware?). Trying to work around... ",
2414 dev->name);
2415
2416 priv->nicbuf_size = TX_NICBUF_SIZE_BUG;
2417 err = hermes_allocate(hw, priv->nicbuf_size, &priv->txfid);
2418 if (err)
2419 printk("failed!\n");
2420 else
2421 printk("ok.\n");
2422 }
2423 if (err) {
2424 printk("%s: Error %d allocating Tx buffer\n", dev->name, err);
2425 goto out;
2426 }
2427
2428 /* Make the hardware available, as long as it hasn't been 2423 /* Make the hardware available, as long as it hasn't been
2429 * removed elsewhere (e.g. by PCMCIA hot unplug) */ 2424 * removed elsewhere (e.g. by PCMCIA hot unplug) */
2430 spin_lock_irq(&priv->lock); 2425 spin_lock_irq(&priv->lock);
@@ -2450,7 +2445,7 @@ struct net_device *alloc_orinocodev(int sizeof_card,
2450 priv = netdev_priv(dev); 2445 priv = netdev_priv(dev);
2451 priv->ndev = dev; 2446 priv->ndev = dev;
2452 if (sizeof_card) 2447 if (sizeof_card)
2453 priv->card = (void *)((unsigned long)netdev_priv(dev) 2448 priv->card = (void *)((unsigned long)priv
2454 + sizeof(struct orinoco_private)); 2449 + sizeof(struct orinoco_private));
2455 else 2450 else
2456 priv->card = NULL; 2451 priv->card = NULL;
@@ -2555,6 +2550,7 @@ static int orinoco_hw_get_essid(struct orinoco_private *priv, int *active,
2555 } 2550 }
2556 2551
2557 len = le16_to_cpu(essidbuf.len); 2552 len = le16_to_cpu(essidbuf.len);
2553 BUG_ON(len > IW_ESSID_MAX_SIZE);
2558 2554
2559 memset(buf, 0, IW_ESSID_MAX_SIZE+1); 2555 memset(buf, 0, IW_ESSID_MAX_SIZE+1);
2560 memcpy(buf, p, len); 2556 memcpy(buf, p, len);
@@ -2923,13 +2919,14 @@ static int orinoco_ioctl_setessid(struct net_device *dev, struct iw_point *erq)
2923 memset(&essidbuf, 0, sizeof(essidbuf)); 2919 memset(&essidbuf, 0, sizeof(essidbuf));
2924 2920
2925 if (erq->flags) { 2921 if (erq->flags) {
2926 if (erq->length > IW_ESSID_MAX_SIZE) 2922 /* iwconfig includes the NUL in the specified length */
2923 if (erq->length > IW_ESSID_MAX_SIZE+1)
2927 return -E2BIG; 2924 return -E2BIG;
2928 2925
2929 if (copy_from_user(&essidbuf, erq->pointer, erq->length)) 2926 if (copy_from_user(&essidbuf, erq->pointer, erq->length))
2930 return -EFAULT; 2927 return -EFAULT;
2931 2928
2932 essidbuf[erq->length] = '\0'; 2929 essidbuf[IW_ESSID_MAX_SIZE] = '\0';
2933 } 2930 }
2934 2931
2935 if (orinoco_lock(priv, &flags) != 0) 2932 if (orinoco_lock(priv, &flags) != 0)
@@ -3855,7 +3852,6 @@ orinoco_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3855 { SIOCIWFIRSTPRIV + 0x7, 0, 3852 { SIOCIWFIRSTPRIV + 0x7, 0,
3856 IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 3853 IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1,
3857 "get_ibssport" }, 3854 "get_ibssport" },
3858 { SIOCIWLASTPRIV, 0, 0, "dump_recs" },
3859 }; 3855 };
3860 3856
3861 wrq->u.data.length = sizeof(privtab) / sizeof(privtab[0]); 3857 wrq->u.data.length = sizeof(privtab) / sizeof(privtab[0]);
@@ -3943,14 +3939,6 @@ orinoco_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3943 err = orinoco_ioctl_getibssport(dev, wrq); 3939 err = orinoco_ioctl_getibssport(dev, wrq);
3944 break; 3940 break;
3945 3941
3946 case SIOCIWLASTPRIV:
3947 err = orinoco_debug_dump_recs(dev);
3948 if (err)
3949 printk(KERN_ERR "%s: Unable to dump records (%d)\n",
3950 dev->name, err);
3951 break;
3952
3953
3954 default: 3942 default:
3955 err = -EOPNOTSUPP; 3943 err = -EOPNOTSUPP;
3956 } 3944 }
@@ -3964,187 +3952,6 @@ orinoco_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3964 return err; 3952 return err;
3965} 3953}
3966 3954
3967struct {
3968 u16 rid;
3969 char *name;
3970 int displaytype;
3971#define DISPLAY_WORDS 0
3972#define DISPLAY_BYTES 1
3973#define DISPLAY_STRING 2
3974#define DISPLAY_XSTRING 3
3975} record_table[] = {
3976#define DEBUG_REC(name,type) { HERMES_RID_##name, #name, DISPLAY_##type }
3977 DEBUG_REC(CNFPORTTYPE,WORDS),
3978 DEBUG_REC(CNFOWNMACADDR,BYTES),
3979 DEBUG_REC(CNFDESIREDSSID,STRING),
3980 DEBUG_REC(CNFOWNCHANNEL,WORDS),
3981 DEBUG_REC(CNFOWNSSID,STRING),
3982 DEBUG_REC(CNFOWNATIMWINDOW,WORDS),
3983 DEBUG_REC(CNFSYSTEMSCALE,WORDS),
3984 DEBUG_REC(CNFMAXDATALEN,WORDS),
3985 DEBUG_REC(CNFPMENABLED,WORDS),
3986 DEBUG_REC(CNFPMEPS,WORDS),
3987 DEBUG_REC(CNFMULTICASTRECEIVE,WORDS),
3988 DEBUG_REC(CNFMAXSLEEPDURATION,WORDS),
3989 DEBUG_REC(CNFPMHOLDOVERDURATION,WORDS),
3990 DEBUG_REC(CNFOWNNAME,STRING),
3991 DEBUG_REC(CNFOWNDTIMPERIOD,WORDS),
3992 DEBUG_REC(CNFMULTICASTPMBUFFERING,WORDS),
3993 DEBUG_REC(CNFWEPENABLED_AGERE,WORDS),
3994 DEBUG_REC(CNFMANDATORYBSSID_SYMBOL,WORDS),
3995 DEBUG_REC(CNFWEPDEFAULTKEYID,WORDS),
3996 DEBUG_REC(CNFDEFAULTKEY0,BYTES),
3997 DEBUG_REC(CNFDEFAULTKEY1,BYTES),
3998 DEBUG_REC(CNFMWOROBUST_AGERE,WORDS),
3999 DEBUG_REC(CNFDEFAULTKEY2,BYTES),
4000 DEBUG_REC(CNFDEFAULTKEY3,BYTES),
4001 DEBUG_REC(CNFWEPFLAGS_INTERSIL,WORDS),
4002 DEBUG_REC(CNFWEPKEYMAPPINGTABLE,WORDS),
4003 DEBUG_REC(CNFAUTHENTICATION,WORDS),
4004 DEBUG_REC(CNFMAXASSOCSTA,WORDS),
4005 DEBUG_REC(CNFKEYLENGTH_SYMBOL,WORDS),
4006 DEBUG_REC(CNFTXCONTROL,WORDS),
4007 DEBUG_REC(CNFROAMINGMODE,WORDS),
4008 DEBUG_REC(CNFHOSTAUTHENTICATION,WORDS),
4009 DEBUG_REC(CNFRCVCRCERROR,WORDS),
4010 DEBUG_REC(CNFMMLIFE,WORDS),
4011 DEBUG_REC(CNFALTRETRYCOUNT,WORDS),
4012 DEBUG_REC(CNFBEACONINT,WORDS),
4013 DEBUG_REC(CNFAPPCFINFO,WORDS),
4014 DEBUG_REC(CNFSTAPCFINFO,WORDS),
4015 DEBUG_REC(CNFPRIORITYQUSAGE,WORDS),
4016 DEBUG_REC(CNFTIMCTRL,WORDS),
4017 DEBUG_REC(CNFTHIRTY2TALLY,WORDS),
4018 DEBUG_REC(CNFENHSECURITY,WORDS),
4019 DEBUG_REC(CNFGROUPADDRESSES,BYTES),
4020 DEBUG_REC(CNFCREATEIBSS,WORDS),
4021 DEBUG_REC(CNFFRAGMENTATIONTHRESHOLD,WORDS),
4022 DEBUG_REC(CNFRTSTHRESHOLD,WORDS),
4023 DEBUG_REC(CNFTXRATECONTROL,WORDS),
4024 DEBUG_REC(CNFPROMISCUOUSMODE,WORDS),
4025 DEBUG_REC(CNFBASICRATES_SYMBOL,WORDS),
4026 DEBUG_REC(CNFPREAMBLE_SYMBOL,WORDS),
4027 DEBUG_REC(CNFSHORTPREAMBLE,WORDS),
4028 DEBUG_REC(CNFWEPKEYS_AGERE,BYTES),
4029 DEBUG_REC(CNFEXCLUDELONGPREAMBLE,WORDS),
4030 DEBUG_REC(CNFTXKEY_AGERE,WORDS),
4031 DEBUG_REC(CNFAUTHENTICATIONRSPTO,WORDS),
4032 DEBUG_REC(CNFBASICRATES,WORDS),
4033 DEBUG_REC(CNFSUPPORTEDRATES,WORDS),
4034 DEBUG_REC(CNFTICKTIME,WORDS),
4035 DEBUG_REC(CNFSCANREQUEST,WORDS),
4036 DEBUG_REC(CNFJOINREQUEST,WORDS),
4037 DEBUG_REC(CNFAUTHENTICATESTATION,WORDS),
4038 DEBUG_REC(CNFCHANNELINFOREQUEST,WORDS),
4039 DEBUG_REC(MAXLOADTIME,WORDS),
4040 DEBUG_REC(DOWNLOADBUFFER,WORDS),
4041 DEBUG_REC(PRIID,WORDS),
4042 DEBUG_REC(PRISUPRANGE,WORDS),
4043 DEBUG_REC(CFIACTRANGES,WORDS),
4044 DEBUG_REC(NICSERNUM,XSTRING),
4045 DEBUG_REC(NICID,WORDS),
4046 DEBUG_REC(MFISUPRANGE,WORDS),
4047 DEBUG_REC(CFISUPRANGE,WORDS),
4048 DEBUG_REC(CHANNELLIST,WORDS),
4049 DEBUG_REC(REGULATORYDOMAINS,WORDS),
4050 DEBUG_REC(TEMPTYPE,WORDS),
4051/* DEBUG_REC(CIS,BYTES), */
4052 DEBUG_REC(STAID,WORDS),
4053 DEBUG_REC(CURRENTSSID,STRING),
4054 DEBUG_REC(CURRENTBSSID,BYTES),
4055 DEBUG_REC(COMMSQUALITY,WORDS),
4056 DEBUG_REC(CURRENTTXRATE,WORDS),
4057 DEBUG_REC(CURRENTBEACONINTERVAL,WORDS),
4058 DEBUG_REC(CURRENTSCALETHRESHOLDS,WORDS),
4059 DEBUG_REC(PROTOCOLRSPTIME,WORDS),
4060 DEBUG_REC(SHORTRETRYLIMIT,WORDS),
4061 DEBUG_REC(LONGRETRYLIMIT,WORDS),
4062 DEBUG_REC(MAXTRANSMITLIFETIME,WORDS),
4063 DEBUG_REC(MAXRECEIVELIFETIME,WORDS),
4064 DEBUG_REC(CFPOLLABLE,WORDS),
4065 DEBUG_REC(AUTHENTICATIONALGORITHMS,WORDS),
4066 DEBUG_REC(PRIVACYOPTIONIMPLEMENTED,WORDS),
4067 DEBUG_REC(OWNMACADDR,BYTES),
4068 DEBUG_REC(SCANRESULTSTABLE,WORDS),
4069 DEBUG_REC(PHYTYPE,WORDS),
4070 DEBUG_REC(CURRENTCHANNEL,WORDS),
4071 DEBUG_REC(CURRENTPOWERSTATE,WORDS),
4072 DEBUG_REC(CCAMODE,WORDS),
4073 DEBUG_REC(SUPPORTEDDATARATES,WORDS),
4074 DEBUG_REC(BUILDSEQ,BYTES),
4075 DEBUG_REC(FWID,XSTRING)
4076#undef DEBUG_REC
4077};
4078
4079#define DEBUG_LTV_SIZE 128
4080
4081static int orinoco_debug_dump_recs(struct net_device *dev)
4082{
4083 struct orinoco_private *priv = netdev_priv(dev);
4084 hermes_t *hw = &priv->hw;
4085 u8 *val8;
4086 u16 *val16;
4087 int i,j;
4088 u16 length;
4089 int err;
4090
4091 /* I'm not sure: we might have a lock here, so we'd better go
4092 atomic, just in case. */
4093 val8 = kmalloc(DEBUG_LTV_SIZE + 2, GFP_ATOMIC);
4094 if (! val8)
4095 return -ENOMEM;
4096 val16 = (u16 *)val8;
4097
4098 for (i = 0; i < ARRAY_SIZE(record_table); i++) {
4099 u16 rid = record_table[i].rid;
4100 int len;
4101
4102 memset(val8, 0, DEBUG_LTV_SIZE + 2);
4103
4104 err = hermes_read_ltv(hw, USER_BAP, rid, DEBUG_LTV_SIZE,
4105 &length, val8);
4106 if (err) {
4107 DEBUG(0, "Error %d reading RID 0x%04x\n", err, rid);
4108 continue;
4109 }
4110 val16 = (u16 *)val8;
4111 if (length == 0)
4112 continue;
4113
4114 printk(KERN_DEBUG "%-15s (0x%04x): length=%d (%d bytes)\tvalue=",
4115 record_table[i].name,
4116 rid, length, (length-1)*2);
4117 len = min(((int)length-1)*2, DEBUG_LTV_SIZE);
4118
4119 switch (record_table[i].displaytype) {
4120 case DISPLAY_WORDS:
4121 for (j = 0; j < len / 2; j++)
4122 printk("%04X-", le16_to_cpu(val16[j]));
4123 break;
4124
4125 case DISPLAY_BYTES:
4126 default:
4127 for (j = 0; j < len; j++)
4128 printk("%02X:", val8[j]);
4129 break;
4130
4131 case DISPLAY_STRING:
4132 len = min(len, le16_to_cpu(val16[0])+2);
4133 val8[len] = '\0';
4134 printk("\"%s\"", (char *)&val16[1]);
4135 break;
4136
4137 case DISPLAY_XSTRING:
4138 printk("'%s'", (char *)val8);
4139 }
4140
4141 printk("\n");
4142 }
4143
4144 kfree(val8);
4145
4146 return 0;
4147}
4148 3955
4149/********************************************************************/ 3956/********************************************************************/
4150/* Debugging */ 3957/* Debugging */
@@ -4218,7 +4025,6 @@ EXPORT_SYMBOL(free_orinocodev);
4218 4025
4219EXPORT_SYMBOL(__orinoco_up); 4026EXPORT_SYMBOL(__orinoco_up);
4220EXPORT_SYMBOL(__orinoco_down); 4027EXPORT_SYMBOL(__orinoco_down);
4221EXPORT_SYMBOL(orinoco_stop);
4222EXPORT_SYMBOL(orinoco_reinit_firmware); 4028EXPORT_SYMBOL(orinoco_reinit_firmware);
4223 4029
4224EXPORT_SYMBOL(orinoco_interrupt); 4030EXPORT_SYMBOL(orinoco_interrupt);
diff --git a/drivers/net/wireless/orinoco.h b/drivers/net/wireless/orinoco.h
index 13e42c2afb27..f749b50d1088 100644
--- a/drivers/net/wireless/orinoco.h
+++ b/drivers/net/wireless/orinoco.h
@@ -119,7 +119,6 @@ extern struct net_device *alloc_orinocodev(int sizeof_card,
119extern void free_orinocodev(struct net_device *dev); 119extern void free_orinocodev(struct net_device *dev);
120extern int __orinoco_up(struct net_device *dev); 120extern int __orinoco_up(struct net_device *dev);
121extern int __orinoco_down(struct net_device *dev); 121extern int __orinoco_down(struct net_device *dev);
122extern int orinoco_stop(struct net_device *dev);
123extern int orinoco_reinit_firmware(struct net_device *dev); 122extern int orinoco_reinit_firmware(struct net_device *dev);
124extern irqreturn_t orinoco_interrupt(int irq, void * dev_id, struct pt_regs *regs); 123extern irqreturn_t orinoco_interrupt(int irq, void * dev_id, struct pt_regs *regs);
125 124
diff --git a/drivers/net/wireless/strip.c b/drivers/net/wireless/strip.c
index ec8cf29ffced..6c42b573a95a 100644
--- a/drivers/net/wireless/strip.c
+++ b/drivers/net/wireless/strip.c
@@ -2828,7 +2828,7 @@ static void __exit strip_exit_driver(void)
2828 /* Unregister with the /proc/net file here. */ 2828 /* Unregister with the /proc/net file here. */
2829 proc_net_remove("strip"); 2829 proc_net_remove("strip");
2830 2830
2831 if ((i = tty_register_ldisc(N_STRIP, NULL))) 2831 if ((i = tty_unregister_ldisc(N_STRIP)))
2832 printk(KERN_ERR "STRIP: can't unregister line discipline (err = %d)\n", i); 2832 printk(KERN_ERR "STRIP: can't unregister line discipline (err = %d)\n", i);
2833 2833
2834 printk(signoff); 2834 printk(signoff);
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 01:22:28 -0400