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authorEilon Greenstein <eilong@broadcom.com>2008-06-23 23:29:02 -0400
committerDavid S. Miller <davem@davemloft.net>2008-06-23 23:29:02 -0400
commitad8d394804b355bc623decc50748cd01dbc0783b (patch)
treebe2d1c7fc15fc6e1bd17a7d87c697254407fa865 /drivers/net
parentc18487ee24381b40df3b8b4f54dd13ee9367a1ce (diff)
bnx2x: New init infrastructure
This new initialization code supports the 57711 HW. It also supports the emulation and FPGA for the 57711 and 57710 initializations values (very small amount of code which is very helpful in the lab - less than 30 lines). The initialization is done via DMAE after the DMAE block is ready - before it is ready, some of the initialization is done via PCI configuration transactions (referred to as indirect write). A mutex to protect the DMAE from being overlapped was added. There are few new registers which needs to be initialized by SW - the full comment for those registers is added to the register file. A place holder for the 57711 (referred to as E1H) microcode was added- the microcode itself is too big and it is split over the following 4 patches Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/bnx2x.h99
-rw-r--r--drivers/net/bnx2x_hsi.h27
-rw-r--r--drivers/net/bnx2x_init.h345
-rw-r--r--drivers/net/bnx2x_init_values.h2149
-rw-r--r--drivers/net/bnx2x_main.c166
5 files changed, 2130 insertions, 656 deletions
diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h
index 2a13defda8ab..0979ca0ae408 100644
--- a/drivers/net/bnx2x.h
+++ b/drivers/net/bnx2x.h
@@ -557,25 +557,37 @@ struct bnx2x {
557 557
558 u32 shmem_base; 558 u32 shmem_base;
559 559
560 u32 chip_id; 560 u32 chip_id;
561/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 561/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
562#define CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0) 562#define CHIP_ID(bp) (bp->chip_id & 0xfffffff0)
563 563
564#define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000) 564#define CHIP_NUM(bp) (bp->chip_id >> 16)
565 565#define CHIP_NUM_57710 0x164e
566#define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000) 566#define CHIP_NUM_57711 0x164f
567#define CHIP_REV_Ax 0x00000000 567#define CHIP_NUM_57711E 0x1650
568#define CHIP_REV_Bx 0x00001000 568#define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
569#define CHIP_REV_Cx 0x00002000 569#define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
570#define CHIP_REV_EMUL 0x0000e000 570#define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
571#define CHIP_REV_FPGA 0x0000f000 571#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
572#define CHIP_REV_IS_SLOW(bp) ((CHIP_REV(bp) == CHIP_REV_EMUL) || \ 572 CHIP_IS_57711E(bp))
573 (CHIP_REV(bp) == CHIP_REV_FPGA)) 573#define IS_E1H_OFFSET CHIP_IS_E1H(bp)
574#define CHIP_REV_IS_EMUL(bp) (CHIP_REV(bp) == CHIP_REV_EMUL) 574
575#define CHIP_REV_IS_FPGA(bp) (CHIP_REV(bp) == CHIP_REV_FPGA) 575#define CHIP_REV(bp) (bp->chip_id & 0x0000f000)
576 576#define CHIP_REV_Ax 0x00000000
577#define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0) 577/* assume maximum 5 revisions */
578#define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0x0000000f) 578#define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
579/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
580#define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
581 !(CHIP_REV(bp) & 0x00001000))
582/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
583#define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
584 (CHIP_REV(bp) & 0x00001000))
585
586#define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
587 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
588
589#define CHIP_METAL(bp) (bp->chip_id & 0x00000ff0)
590#define CHIP_BOND_ID(bp) (bp->chip_id & 0x0000000f)
579 591
580 u16 fw_seq; 592 u16 fw_seq;
581 u16 fw_drv_pulse_wr_seq; 593 u16 fw_drv_pulse_wr_seq;
@@ -678,6 +690,13 @@ struct bnx2x {
678 struct dmae_command dmae; 690 struct dmae_command dmae;
679 int executer_idx; 691 int executer_idx;
680 692
693 int dmae_ready;
694 /* used to synchronize dmae accesses */
695 struct mutex dmae_mutex;
696 struct dmae_command init_dmae;
697
698
699
681 u32 old_brb_discard; 700 u32 old_brb_discard;
682 struct bmac_stats old_bmac; 701 struct bmac_stats old_bmac;
683 struct tstorm_per_client_stats old_tclient; 702 struct tstorm_per_client_stats old_tclient;
@@ -685,7 +704,7 @@ struct bnx2x {
685 void *gunzip_buf; 704 void *gunzip_buf;
686 dma_addr_t gunzip_mapping; 705 dma_addr_t gunzip_mapping;
687 int gunzip_outlen; 706 int gunzip_outlen;
688#define FW_BUF_SIZE 0x8000 707#define FW_BUF_SIZE 0x8000
689 708
690}; 709};
691 710
@@ -774,12 +793,6 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);
774#define STROM_ASSERT_ARRAY_SIZE 50 793#define STROM_ASSERT_ARRAY_SIZE 50
775 794
776 795
777#define MDIO_INDIRECT_REG_ADDR 0x1f
778#define MDIO_SET_REG_BANK(bp, reg_bank) \
779 bnx2x_mdio22_write(bp, MDIO_INDIRECT_REG_ADDR, reg_bank)
780
781#define MDIO_ACCESS_TIMEOUT 1000
782
783 796
784/* must be used on a CID before placing it on a HW ring */ 797/* must be used on a CID before placing it on a HW ring */
785#define HW_CID(bp, x) (x | (bp->port << 23)) 798#define HW_CID(bp, x) (x | (bp->port << 23))
@@ -818,6 +831,42 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);
818 DPM_TRIGER_TYPE); \ 831 DPM_TRIGER_TYPE); \
819 } while (0) 832 } while (0)
820 833
834/* DMAE command defines */
835#define DMAE_CMD_SRC_PCI 0
836#define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
837
838#define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
839#define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
840
841#define DMAE_CMD_C_DST_PCI 0
842#define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
843
844#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
845
846#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
847#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
848#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
849#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
850
851#define DMAE_CMD_PORT_0 0
852#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
853
854#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
855#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
856#define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
857
858#define DMAE_LEN32_RD_MAX 0x80
859#define DMAE_LEN32_WR_MAX 0x400
860
861#define DMAE_COMP_VAL 0xe0d0d0ae
862
863#define MAX_DMAE_C_PER_PORT 8
864#define INIT_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
865 BP_E1HVN(bp))
866#define PMF_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
867 E1HVN_MAX)
868
869
821/* PCIE link and speed */ 870/* PCIE link and speed */
822#define PCICFG_LINK_WIDTH 0x1f00000 871#define PCICFG_LINK_WIDTH 0x1f00000
823#define PCICFG_LINK_WIDTH_SHIFT 20 872#define PCICFG_LINK_WIDTH_SHIFT 20
diff --git a/drivers/net/bnx2x_hsi.h b/drivers/net/bnx2x_hsi.h
index b21075ccb52e..96208ace1466 100644
--- a/drivers/net/bnx2x_hsi.h
+++ b/drivers/net/bnx2x_hsi.h
@@ -522,8 +522,21 @@ struct dev_info { /* size */
522 522
523#define FUNC_0 0 523#define FUNC_0 0
524#define FUNC_1 1 524#define FUNC_1 1
525#define FUNC_2 2
526#define FUNC_3 3
527#define FUNC_4 4
528#define FUNC_5 5
529#define FUNC_6 6
530#define FUNC_7 7
525#define E1_FUNC_MAX 2 531#define E1_FUNC_MAX 2
526#define FUNC_MAX E1_FUNC_MAX 532#define E1H_FUNC_MAX 8
533
534#define VN_0 0
535#define VN_1 1
536#define VN_2 2
537#define VN_3 3
538#define E1VN_MAX 1
539#define E1HVN_MAX 4
527 540
528 541
529/* This value (in milliseconds) determines the frequency of the driver 542/* This value (in milliseconds) determines the frequency of the driver
@@ -747,7 +760,11 @@ struct shmem_region { /* SharedMem Offset (size) */
747 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ 760 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */
748 761
749 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ 762 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
750 struct drv_func_mb func_mb[FUNC_MAX]; /* 0x684 (44*2=0x58) */ 763#if defined(b710)
764 struct drv_func_mb func_mb[E1_FUNC_MAX]; /* 0x684 (44*2=0x58) */
765#else
766 struct drv_func_mb func_mb[E1H_FUNC_MAX];
767#endif
751 768
752}; /* 0x6dc */ 769}; /* 0x6dc */
753 770
@@ -901,8 +918,10 @@ struct dmae_command {
901#define DMAE_COMMAND_SRC_RESET_SHIFT 13 918#define DMAE_COMMAND_SRC_RESET_SHIFT 13
902#define DMAE_COMMAND_DST_RESET (0x1<<14) 919#define DMAE_COMMAND_DST_RESET (0x1<<14)
903#define DMAE_COMMAND_DST_RESET_SHIFT 14 920#define DMAE_COMMAND_DST_RESET_SHIFT 14
904#define DMAE_COMMAND_RESERVED0 (0x1FFFF<<15) 921#define DMAE_COMMAND_E1HVN (0x3<<15)
905#define DMAE_COMMAND_RESERVED0_SHIFT 15 922#define DMAE_COMMAND_E1HVN_SHIFT 15
923#define DMAE_COMMAND_RESERVED0 (0x7FFF<<17)
924#define DMAE_COMMAND_RESERVED0_SHIFT 17
906 u32 src_addr_lo; 925 u32 src_addr_lo;
907 u32 src_addr_hi; 926 u32 src_addr_hi;
908 u32 dst_addr_lo; 927 u32 dst_addr_lo;
diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h
index bb0ee2dd2d80..5a4e82b9e7bf 100644
--- a/drivers/net/bnx2x_init.h
+++ b/drivers/net/bnx2x_init.h
@@ -22,7 +22,8 @@
22#define INIT_ASIC 0x4 22#define INIT_ASIC 0x4
23#define INIT_HARDWARE 0x7 23#define INIT_HARDWARE 0x7
24 24
25#define STORM_INTMEM_SIZE (0x5800 / 4) 25#define STORM_INTMEM_SIZE_E1 (0x5800 / 4)
26#define STORM_INTMEM_SIZE_E1H (0x10000 / 4)
26#define TSTORM_INTMEM_ADDR 0x1a0000 27#define TSTORM_INTMEM_ADDR 0x1a0000
27#define CSTORM_INTMEM_ADDR 0x220000 28#define CSTORM_INTMEM_ADDR 0x220000
28#define XSTORM_INTMEM_ADDR 0x2a0000 29#define XSTORM_INTMEM_ADDR 0x2a0000
@@ -30,7 +31,7 @@
30 31
31 32
32/* Init operation types and structures */ 33/* Init operation types and structures */
33 34/* Common for both E1 and E1H */
34#define OP_RD 0x1 /* read single register */ 35#define OP_RD 0x1 /* read single register */
35#define OP_WR 0x2 /* write single register */ 36#define OP_WR 0x2 /* write single register */
36#define OP_IW 0x3 /* write single register using mailbox */ 37#define OP_IW 0x3 /* write single register using mailbox */
@@ -38,7 +39,37 @@
38#define OP_SI 0x5 /* copy a string using mailbox */ 39#define OP_SI 0x5 /* copy a string using mailbox */
39#define OP_ZR 0x6 /* clear memory */ 40#define OP_ZR 0x6 /* clear memory */
40#define OP_ZP 0x7 /* unzip then copy with DMAE */ 41#define OP_ZP 0x7 /* unzip then copy with DMAE */
41#define OP_WB 0x8 /* copy a string using DMAE */ 42#define OP_WR_64 0x8 /* write 64 bit pattern */
43#define OP_WB 0x9 /* copy a string using DMAE */
44
45/* Operation specific for E1 */
46#define OP_RD_E1 0xa /* read single register */
47#define OP_WR_E1 0xb /* write single register */
48#define OP_IW_E1 0xc /* write single register using mailbox */
49#define OP_SW_E1 0xd /* copy a string to the device */
50#define OP_SI_E1 0xe /* copy a string using mailbox */
51#define OP_ZR_E1 0xf /* clear memory */
52#define OP_ZP_E1 0x10 /* unzip then copy with DMAE */
53#define OP_WR_64_E1 0x11 /* write 64 bit pattern on E1 */
54#define OP_WB_E1 0x12 /* copy a string using DMAE */
55
56/* Operation specific for E1H */
57#define OP_RD_E1H 0x13 /* read single register */
58#define OP_WR_E1H 0x14 /* write single register */
59#define OP_IW_E1H 0x15 /* write single register using mailbox */
60#define OP_SW_E1H 0x16 /* copy a string to the device */
61#define OP_SI_E1H 0x17 /* copy a string using mailbox */
62#define OP_ZR_E1H 0x18 /* clear memory */
63#define OP_ZP_E1H 0x19 /* unzip then copy with DMAE */
64#define OP_WR_64_E1H 0x1a /* write 64 bit pattern on E1H */
65#define OP_WB_E1H 0x1b /* copy a string using DMAE */
66
67/* FPGA and EMUL specific operations */
68#define OP_WR_EMUL_E1H 0x1c /* write single register on E1H Emul */
69#define OP_WR_EMUL 0x1d /* write single register on Emulation */
70#define OP_WR_FPGA 0x1e /* write single register on FPGA */
71#define OP_WR_ASIC 0x1f /* write single register on ASIC */
72
42 73
43struct raw_op { 74struct raw_op {
44 u32 op :8; 75 u32 op :8;
@@ -117,11 +148,117 @@ static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data,
117 } 148 }
118} 149}
119 150
151static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len)
152{
153#ifdef USE_DMAE
154 int offset = 0;
155
156 if (bp->dmae_ready) {
157 while (len > DMAE_LEN32_WR_MAX) {
158 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
159 addr + offset, DMAE_LEN32_WR_MAX);
160 offset += DMAE_LEN32_WR_MAX * 4;
161 len -= DMAE_LEN32_WR_MAX;
162 }
163 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
164 addr + offset, len);
165 } else
166 bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len);
167#else
168 bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len);
169#endif
170}
171
172static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
173{
174 if ((len * 4) > FW_BUF_SIZE) {
175 BNX2X_ERR("LARGE DMAE OPERATION ! addr 0x%x len 0x%x\n",
176 addr, len*4);
177 return;
178 }
179 memset(bp->gunzip_buf, fill, len * 4);
180
181 bnx2x_write_big_buf(bp, addr, len);
182}
183
184static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr, const u32 *data,
185 u32 len64)
186{
187 u32 buf_len32 = FW_BUF_SIZE/4;
188 u32 len = len64*2;
189 u64 data64 = 0;
190 int i;
191
192 /* 64 bit value is in a blob: first low DWORD, then high DWORD */
193 data64 = HILO_U64((*(data + 1)), (*data));
194 len64 = min((u32)(FW_BUF_SIZE/8), len64);
195 for (i = 0; i < len64; i++) {
196 u64 *pdata = ((u64 *)(bp->gunzip_buf)) + i;
197
198 *pdata = data64;
199 }
200
201 for (i = 0; i < len; i += buf_len32) {
202 u32 cur_len = min(buf_len32, len - i);
203
204 bnx2x_write_big_buf(bp, addr + i * 4, cur_len);
205 }
206}
207
208/*********************************************************
209 There are different blobs for each PRAM section.
210 In addition, each blob write operation is divided into a few operations
211 in order to decrease the amount of phys. contigious buffer needed.
212 Thus, when we select a blob the address may be with some offset
213 from the beginning of PRAM section.
214 The same holds for the INT_TABLE sections.
215**********************************************************/
216#define IF_IS_INT_TABLE_ADDR(base, addr) \
217 if (((base) <= (addr)) && ((base) + 0x400 >= (addr)))
218
219#define IF_IS_PRAM_ADDR(base, addr) \
220 if (((base) <= (addr)) && ((base) + 0x40000 >= (addr)))
221
222static const u32 *bnx2x_sel_blob(u32 addr, const u32 *data, int is_e1)
223{
224 IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr)
225 data = is_e1 ? tsem_int_table_data_e1 :
226 tsem_int_table_data_e1h;
227 else
228 IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr)
229 data = is_e1 ? csem_int_table_data_e1 :
230 csem_int_table_data_e1h;
231 else
232 IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr)
233 data = is_e1 ? usem_int_table_data_e1 :
234 usem_int_table_data_e1h;
235 else
236 IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr)
237 data = is_e1 ? xsem_int_table_data_e1 :
238 xsem_int_table_data_e1h;
239 else
240 IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr)
241 data = is_e1 ? tsem_pram_data_e1 : tsem_pram_data_e1h;
242 else
243 IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr)
244 data = is_e1 ? csem_pram_data_e1 : csem_pram_data_e1h;
245 else
246 IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr)
247 data = is_e1 ? usem_pram_data_e1 : usem_pram_data_e1h;
248 else
249 IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr)
250 data = is_e1 ? xsem_pram_data_e1 : xsem_pram_data_e1h;
251
252 return data;
253}
254
120static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, const u32 *data, 255static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, const u32 *data,
121 u32 len, int gunzip) 256 u32 len, int gunzip, int is_e1, u32 blob_off)
122{ 257{
123 int offset = 0; 258 int offset = 0;
124 259
260 data = bnx2x_sel_blob(addr, data, is_e1) + blob_off;
261
125 if (gunzip) { 262 if (gunzip) {
126 int rc; 263 int rc;
127#ifdef __BIG_ENDIAN 264#ifdef __BIG_ENDIAN
@@ -136,64 +273,59 @@ static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, const u32 *data,
136#endif 273#endif
137 rc = bnx2x_gunzip(bp, (u8 *)data, len); 274 rc = bnx2x_gunzip(bp, (u8 *)data, len);
138 if (rc) { 275 if (rc) {
139 DP(NETIF_MSG_HW, "gunzip failed ! rc %d\n", rc); 276 BNX2X_ERR("gunzip failed ! rc %d\n", rc);
140 return; 277 return;
141 } 278 }
142 len = bp->gunzip_outlen; 279 len = bp->gunzip_outlen;
143#ifdef __BIG_ENDIAN 280#ifdef __BIG_ENDIAN
144 kfree(temp); 281 kfree(temp);
145 for (i = 0; i < len; i++) 282 for (i = 0; i < len; i++)
146 ((u32 *)bp->gunzip_buf)[i] = 283 ((u32 *)bp->gunzip_buf)[i] =
147 swab32(((u32 *)bp->gunzip_buf)[i]); 284 swab32(((u32 *)bp->gunzip_buf)[i]);
148#endif 285#endif
149 } else { 286 } else {
150 if ((len * 4) > FW_BUF_SIZE) { 287 if ((len * 4) > FW_BUF_SIZE) {
151 BNX2X_ERR("LARGE DMAE OPERATION ! len 0x%x\n", len*4); 288 BNX2X_ERR("LARGE DMAE OPERATION ! "
289 "addr 0x%x len 0x%x\n", addr, len*4);
152 return; 290 return;
153 } 291 }
154 memcpy(bp->gunzip_buf, data, len * 4); 292 memcpy(bp->gunzip_buf, data, len * 4);
155 } 293 }
156 294
157 while (len > DMAE_LEN32_MAX) { 295 if (bp->dmae_ready) {
158 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, 296 while (len > DMAE_LEN32_WR_MAX) {
159 addr + offset, DMAE_LEN32_MAX); 297 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
160 offset += DMAE_LEN32_MAX * 4; 298 addr + offset, DMAE_LEN32_WR_MAX);
161 len -= DMAE_LEN32_MAX; 299 offset += DMAE_LEN32_WR_MAX * 4;
162 } 300 len -= DMAE_LEN32_WR_MAX;
163 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, addr + offset, len); 301 }
164}
165
166#define INIT_MEM_WB(reg, data, reg_off, len) \
167 bnx2x_init_wr_wb(bp, reg + reg_off*4, data, len, 0)
168
169#define INIT_GUNZIP_DMAE(reg, data, reg_off, len) \
170 bnx2x_init_wr_wb(bp, reg + reg_off*4, data, len, 1)
171
172static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
173{
174 int offset = 0;
175
176 if ((len * 4) > FW_BUF_SIZE) {
177 BNX2X_ERR("LARGE DMAE OPERATION ! len 0x%x\n", len * 4);
178 return;
179 }
180 memset(bp->gunzip_buf, fill, len * 4);
181
182 while (len > DMAE_LEN32_MAX) {
183 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, 302 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
184 addr + offset, DMAE_LEN32_MAX); 303 addr + offset, len);
185 offset += DMAE_LEN32_MAX * 4; 304 } else
186 len -= DMAE_LEN32_MAX; 305 bnx2x_init_ind_wr(bp, addr, bp->gunzip_buf, len);
187 }
188 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, addr + offset, len);
189} 306}
190 307
191static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end) 308static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end)
192{ 309{
193 int i; 310 int is_e1 = CHIP_IS_E1(bp);
311 int is_e1h = CHIP_IS_E1H(bp);
312 int is_emul_e1h = (CHIP_REV_IS_EMUL(bp) && is_e1h);
313 int hw_wr, i;
194 union init_op *op; 314 union init_op *op;
195 u32 op_type, addr, len; 315 u32 op_type, addr, len;
196 const u32 *data; 316 const u32 *data, *data_base;
317
318 if (CHIP_REV_IS_FPGA(bp))
319 hw_wr = OP_WR_FPGA;
320 else if (CHIP_REV_IS_EMUL(bp))
321 hw_wr = OP_WR_EMUL;
322 else
323 hw_wr = OP_WR_ASIC;
324
325 if (is_e1)
326 data_base = init_data_e1;
327 else /* CHIP_IS_E1H(bp) */
328 data_base = init_data_e1h;
197 329
198 for (i = op_start; i < op_end; i++) { 330 for (i = op_start; i < op_end; i++) {
199 331
@@ -202,7 +334,30 @@ static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end)
202 op_type = op->str_wr.op; 334 op_type = op->str_wr.op;
203 addr = op->str_wr.offset; 335 addr = op->str_wr.offset;
204 len = op->str_wr.data_len; 336 len = op->str_wr.data_len;
205 data = init_data + op->str_wr.data_off; 337 data = data_base + op->str_wr.data_off;
338
339 /* carefull! it must be in order */
340 if (unlikely(op_type > OP_WB)) {
341
342 /* If E1 only */
343 if (op_type <= OP_WB_E1) {
344 if (is_e1)
345 op_type -= (OP_RD_E1 - OP_RD);
346
347 /* If E1H only */
348 } else if (op_type <= OP_WB_E1H) {
349 if (is_e1h)
350 op_type -= (OP_RD_E1H - OP_RD);
351 }
352
353 /* HW/EMUL specific */
354 if (op_type == hw_wr)
355 op_type = OP_WR;
356
357 /* EMUL on E1H is special */
358 if ((op_type == OP_WR_EMUL_E1H) && is_emul_e1h)
359 op_type = OP_WR;
360 }
206 361
207 switch (op_type) { 362 switch (op_type) {
208 case OP_RD: 363 case OP_RD:
@@ -215,7 +370,7 @@ static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end)
215 bnx2x_init_str_wr(bp, addr, data, len); 370 bnx2x_init_str_wr(bp, addr, data, len);
216 break; 371 break;
217 case OP_WB: 372 case OP_WB:
218 bnx2x_init_wr_wb(bp, addr, data, len, 0); 373 bnx2x_init_wr_wb(bp, addr, data, len, 0, is_e1, 0);
219 break; 374 break;
220 case OP_SI: 375 case OP_SI:
221 bnx2x_init_ind_wr(bp, addr, data, len); 376 bnx2x_init_ind_wr(bp, addr, data, len);
@@ -224,10 +379,21 @@ static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end)
224 bnx2x_init_fill(bp, addr, 0, op->zero.len); 379 bnx2x_init_fill(bp, addr, 0, op->zero.len);
225 break; 380 break;
226 case OP_ZP: 381 case OP_ZP:
227 bnx2x_init_wr_wb(bp, addr, data, len, 1); 382 bnx2x_init_wr_wb(bp, addr, data, len, 1, is_e1,
383 op->str_wr.data_off);
384 break;
385 case OP_WR_64:
386 bnx2x_init_wr_64(bp, addr, data, len);
228 break; 387 break;
229 default: 388 default:
230 BNX2X_ERR("BAD init operation!\n"); 389 /* happens whenever an op is of a diff HW */
390#if 0
391 DP(NETIF_MSG_HW, "skipping init operation "
392 "index %d[%d:%d]: type %d addr 0x%x "
393 "len %d(0x%x)\n",
394 i, op_start, op_end, op_type, addr, len, len);
395#endif
396 break;
231 } 397 }
232 } 398 }
233} 399}
@@ -238,7 +404,7 @@ static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end)
238****************************************************************************/ 404****************************************************************************/
239/* 405/*
240 * This code configures the PCI read/write arbiter 406 * This code configures the PCI read/write arbiter
241 * which implements a wighted round robin 407 * which implements a weighted round robin
242 * between the virtual queues in the chip. 408 * between the virtual queues in the chip.
243 * 409 *
244 * The values were derived for each PCI max payload and max request size. 410 * The values were derived for each PCI max payload and max request size.
@@ -308,7 +474,7 @@ static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
308 {{8 , 64 , 25}, {16 , 64 , 41}, {32 , 64 , 81} } 474 {{8 , 64 , 25}, {16 , 64 , 41}, {32 , 64 , 81} }
309}; 475};
310 476
311/* register adresses for read queues */ 477/* register addresses for read queues */
312static const struct arb_line read_arb_addr[NUM_RD_Q-1] = { 478static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
313 {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0, 479 {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
314 PXP2_REG_RQ_BW_RD_UBOUND0}, 480 PXP2_REG_RQ_BW_RD_UBOUND0},
@@ -368,7 +534,7 @@ static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
368 PXP2_REG_PSWRQ_BW_UB28} 534 PXP2_REG_PSWRQ_BW_UB28}
369}; 535};
370 536
371/* register adresses for wrtie queues */ 537/* register addresses for write queues */
372static const struct arb_line write_arb_addr[NUM_WR_Q-1] = { 538static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
373 {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1, 539 {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
374 PXP2_REG_PSWRQ_BW_UB1}, 540 PXP2_REG_PSWRQ_BW_UB1},
@@ -417,6 +583,10 @@ static void bnx2x_init_pxp(struct bnx2x *bp)
417 w_order, MAX_WR_ORD); 583 w_order, MAX_WR_ORD);
418 w_order = MAX_WR_ORD; 584 w_order = MAX_WR_ORD;
419 } 585 }
586 if (CHIP_REV_IS_FPGA(bp)) {
587 DP(NETIF_MSG_HW, "write order adjusted to 1 for FPGA\n");
588 w_order = 0;
589 }
420 DP(NETIF_MSG_HW, "read order %d write order %d\n", r_order, w_order); 590 DP(NETIF_MSG_HW, "read order %d write order %d\n", r_order, w_order);
421 591
422 for (i = 0; i < NUM_RD_Q-1; i++) { 592 for (i = 0; i < NUM_RD_Q-1; i++) {
@@ -474,7 +644,20 @@ static void bnx2x_init_pxp(struct bnx2x *bp)
474 REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00); 644 REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
475 645
476 REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order)); 646 REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
477 REG_WR(bp, PXP2_REG_WR_DMAE_TH, (128 << w_order)/16); 647
648 if (CHIP_IS_E1H(bp)) {
649 REG_WR(bp, PXP2_REG_WR_HC_MPS, w_order+1);
650 REG_WR(bp, PXP2_REG_WR_USDM_MPS, w_order+1);
651 REG_WR(bp, PXP2_REG_WR_CSDM_MPS, w_order+1);
652 REG_WR(bp, PXP2_REG_WR_TSDM_MPS, w_order+1);
653 REG_WR(bp, PXP2_REG_WR_XSDM_MPS, w_order+1);
654 REG_WR(bp, PXP2_REG_WR_QM_MPS, w_order+1);
655 REG_WR(bp, PXP2_REG_WR_TM_MPS, w_order+1);
656 REG_WR(bp, PXP2_REG_WR_SRC_MPS, w_order+1);
657 REG_WR(bp, PXP2_REG_WR_DBG_MPS, w_order+1);
658 REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2); /* DMAE is special */
659 REG_WR(bp, PXP2_REG_WR_CDU_MPS, w_order+1);
660 }
478} 661}
479 662
480 663
@@ -557,6 +740,72 @@ static u8 calc_crc8(u32 data, u8 crc)
557 return crc_res; 740 return crc_res;
558} 741}
559 742
743/* regiesers addresses are not in order
744 so these arrays help simplify the code */
745static const int cm_start[E1H_FUNC_MAX][9] = {
746 {MISC_FUNC0_START, TCM_FUNC0_START, UCM_FUNC0_START, CCM_FUNC0_START,
747 XCM_FUNC0_START, TSEM_FUNC0_START, USEM_FUNC0_START, CSEM_FUNC0_START,
748 XSEM_FUNC0_START},
749 {MISC_FUNC1_START, TCM_FUNC1_START, UCM_FUNC1_START, CCM_FUNC1_START,
750 XCM_FUNC1_START, TSEM_FUNC1_START, USEM_FUNC1_START, CSEM_FUNC1_START,
751 XSEM_FUNC1_START},
752 {MISC_FUNC2_START, TCM_FUNC2_START, UCM_FUNC2_START, CCM_FUNC2_START,
753 XCM_FUNC2_START, TSEM_FUNC2_START, USEM_FUNC2_START, CSEM_FUNC2_START,
754 XSEM_FUNC2_START},
755 {MISC_FUNC3_START, TCM_FUNC3_START, UCM_FUNC3_START, CCM_FUNC3_START,
756 XCM_FUNC3_START, TSEM_FUNC3_START, USEM_FUNC3_START, CSEM_FUNC3_START,
757 XSEM_FUNC3_START},
758 {MISC_FUNC4_START, TCM_FUNC4_START, UCM_FUNC4_START, CCM_FUNC4_START,
759 XCM_FUNC4_START, TSEM_FUNC4_START, USEM_FUNC4_START, CSEM_FUNC4_START,
760 XSEM_FUNC4_START},
761 {MISC_FUNC5_START, TCM_FUNC5_START, UCM_FUNC5_START, CCM_FUNC5_START,
762 XCM_FUNC5_START, TSEM_FUNC5_START, USEM_FUNC5_START, CSEM_FUNC5_START,
763 XSEM_FUNC5_START},
764 {MISC_FUNC6_START, TCM_FUNC6_START, UCM_FUNC6_START, CCM_FUNC6_START,
765 XCM_FUNC6_START, TSEM_FUNC6_START, USEM_FUNC6_START, CSEM_FUNC6_START,
766 XSEM_FUNC6_START},
767 {MISC_FUNC7_START, TCM_FUNC7_START, UCM_FUNC7_START, CCM_FUNC7_START,
768 XCM_FUNC7_START, TSEM_FUNC7_START, USEM_FUNC7_START, CSEM_FUNC7_START,
769 XSEM_FUNC7_START}
770};
771
772static const int cm_end[E1H_FUNC_MAX][9] = {
773 {MISC_FUNC0_END, TCM_FUNC0_END, UCM_FUNC0_END, CCM_FUNC0_END,
774 XCM_FUNC0_END, TSEM_FUNC0_END, USEM_FUNC0_END, CSEM_FUNC0_END,
775 XSEM_FUNC0_END},
776 {MISC_FUNC1_END, TCM_FUNC1_END, UCM_FUNC1_END, CCM_FUNC1_END,
777 XCM_FUNC1_END, TSEM_FUNC1_END, USEM_FUNC1_END, CSEM_FUNC1_END,
778 XSEM_FUNC1_END},
779 {MISC_FUNC2_END, TCM_FUNC2_END, UCM_FUNC2_END, CCM_FUNC2_END,
780 XCM_FUNC2_END, TSEM_FUNC2_END, USEM_FUNC2_END, CSEM_FUNC2_END,
781 XSEM_FUNC2_END},
782 {MISC_FUNC3_END, TCM_FUNC3_END, UCM_FUNC3_END, CCM_FUNC3_END,
783 XCM_FUNC3_END, TSEM_FUNC3_END, USEM_FUNC3_END, CSEM_FUNC3_END,
784 XSEM_FUNC3_END},
785 {MISC_FUNC4_END, TCM_FUNC4_END, UCM_FUNC4_END, CCM_FUNC4_END,
786 XCM_FUNC4_END, TSEM_FUNC4_END, USEM_FUNC4_END, CSEM_FUNC4_END,
787 XSEM_FUNC4_END},
788 {MISC_FUNC5_END, TCM_FUNC5_END, UCM_FUNC5_END, CCM_FUNC5_END,
789 XCM_FUNC5_END, TSEM_FUNC5_END, USEM_FUNC5_END, CSEM_FUNC5_END,
790 XSEM_FUNC5_END},
791 {MISC_FUNC6_END, TCM_FUNC6_END, UCM_FUNC6_END, CCM_FUNC6_END,
792 XCM_FUNC6_END, TSEM_FUNC6_END, USEM_FUNC6_END, CSEM_FUNC6_END,
793 XSEM_FUNC6_END},
794 {MISC_FUNC7_END, TCM_FUNC7_END, UCM_FUNC7_END, CCM_FUNC7_END,
795 XCM_FUNC7_END, TSEM_FUNC7_END, USEM_FUNC7_END, CSEM_FUNC7_END,
796 XSEM_FUNC7_END},
797};
798
799static const int hc_limits[E1H_FUNC_MAX][2] = {
800 {HC_FUNC0_START, HC_FUNC0_END},
801 {HC_FUNC1_START, HC_FUNC1_END},
802 {HC_FUNC2_START, HC_FUNC2_END},
803 {HC_FUNC3_START, HC_FUNC3_END},
804 {HC_FUNC4_START, HC_FUNC4_END},
805 {HC_FUNC5_START, HC_FUNC5_END},
806 {HC_FUNC6_START, HC_FUNC6_END},
807 {HC_FUNC7_START, HC_FUNC7_END}
808};
560 809
561#endif /* BNX2X_INIT_H */ 810#endif /* BNX2X_INIT_H */
562 811
diff --git a/drivers/net/bnx2x_init_values.h b/drivers/net/bnx2x_init_values.h
index bef0a9b19d68..41adbec37bdf 100644
--- a/drivers/net/bnx2x_init_values.h
+++ b/drivers/net/bnx2x_init_values.h
@@ -57,6 +57,7 @@ static const struct raw_op init_ops[] = {
57 {OP_RD, PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES, 0x0}, 57 {OP_RD, PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES, 0x0},
58 {OP_RD, PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES, 0x0}, 58 {OP_RD, PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES, 0x0},
59 {OP_RD, PRS_REG_NUM_OF_DEAD_CYCLES, 0x0}, 59 {OP_RD, PRS_REG_NUM_OF_DEAD_CYCLES, 0x0},
60 {OP_WR_E1H, PRS_REG_FCOE_TYPE, 0x8906},
60 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_0, 0xff}, 61 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_0, 0xff},
61 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_1, 0xff}, 62 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_1, 0xff},
62 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_2, 0xff}, 63 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_2, 0xff},
@@ -74,23 +75,27 @@ static const struct raw_op init_ops[] = {
74 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_5, 0x3f}, 75 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_5, 0x3f},
75 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_6, 0x3f}, 76 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_6, 0x3f},
76 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_7, 0x3f}, 77 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_7, 0x3f},
77#define PRS_COMMON_END 46 78#define PRS_COMMON_END 47
78#define PRS_PORT0_START 46 79#define SRCH_COMMON_START 47
79 {OP_WR, PRS_REG_CID_PORT_0, 0x0}, 80 {OP_WR_E1H, SRC_REG_E1HMF_ENABLE, 0x1},
80#define PRS_PORT0_END 47 81#define SRCH_COMMON_END 48
81#define PRS_PORT1_START 47
82 {OP_WR, PRS_REG_CID_PORT_1, 0x800000},
83#define PRS_PORT1_END 48
84#define TSDM_COMMON_START 48 82#define TSDM_COMMON_START 48
85 {OP_WR, TSDM_REG_CFC_RSP_START_ADDR, 0x411}, 83 {OP_WR_E1, TSDM_REG_CFC_RSP_START_ADDR, 0x411},
86 {OP_WR, TSDM_REG_CMP_COUNTER_START_ADDR, 0x400}, 84 {OP_WR_E1H, TSDM_REG_CFC_RSP_START_ADDR, 0x211},
87 {OP_WR, TSDM_REG_Q_COUNTER_START_ADDR, 0x404}, 85 {OP_WR_E1, TSDM_REG_CMP_COUNTER_START_ADDR, 0x400},
88 {OP_WR, TSDM_REG_PCK_END_MSG_START_ADDR, 0x419}, 86 {OP_WR_E1H, TSDM_REG_CMP_COUNTER_START_ADDR, 0x200},
87 {OP_WR_E1, TSDM_REG_Q_COUNTER_START_ADDR, 0x404},
88 {OP_WR_E1H, TSDM_REG_Q_COUNTER_START_ADDR, 0x204},
89 {OP_WR_E1, TSDM_REG_PCK_END_MSG_START_ADDR, 0x419},
90 {OP_WR_E1H, TSDM_REG_PCK_END_MSG_START_ADDR, 0x219},
89 {OP_WR, TSDM_REG_CMP_COUNTER_MAX0, 0xffff}, 91 {OP_WR, TSDM_REG_CMP_COUNTER_MAX0, 0xffff},
90 {OP_WR, TSDM_REG_CMP_COUNTER_MAX1, 0xffff}, 92 {OP_WR, TSDM_REG_CMP_COUNTER_MAX1, 0xffff},
91 {OP_WR, TSDM_REG_CMP_COUNTER_MAX2, 0xffff}, 93 {OP_WR, TSDM_REG_CMP_COUNTER_MAX2, 0xffff},
92 {OP_WR, TSDM_REG_CMP_COUNTER_MAX3, 0xffff}, 94 {OP_WR, TSDM_REG_CMP_COUNTER_MAX3, 0xffff},
93 {OP_ZR, TSDM_REG_AGG_INT_EVENT_0, 0x80}, 95 {OP_ZR, TSDM_REG_AGG_INT_EVENT_0, 0x2},
96 {OP_WR, TSDM_REG_AGG_INT_EVENT_2, 0x34},
97 {OP_WR, TSDM_REG_AGG_INT_EVENT_3, 0x35},
98 {OP_ZR, TSDM_REG_AGG_INT_EVENT_4, 0x7c},
94 {OP_WR, TSDM_REG_ENABLE_IN1, 0x7ffffff}, 99 {OP_WR, TSDM_REG_ENABLE_IN1, 0x7ffffff},
95 {OP_WR, TSDM_REG_ENABLE_IN2, 0x3f}, 100 {OP_WR, TSDM_REG_ENABLE_IN2, 0x3f},
96 {OP_WR, TSDM_REG_ENABLE_OUT1, 0x7ffffff}, 101 {OP_WR, TSDM_REG_ENABLE_OUT1, 0x7ffffff},
@@ -109,9 +114,12 @@ static const struct raw_op init_ops[] = {
109 {OP_RD, TSDM_REG_NUM_OF_PKT_END_MSG, 0x0}, 114 {OP_RD, TSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
110 {OP_RD, TSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0}, 115 {OP_RD, TSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
111 {OP_RD, TSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0}, 116 {OP_RD, TSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
112 {OP_WR, TSDM_REG_TIMER_TICK, 0x3e8}, 117 {OP_WR_E1, TSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
113#define TSDM_COMMON_END 76 118 {OP_WR_ASIC, TSDM_REG_TIMER_TICK, 0x3e8},
114#define TCM_COMMON_START 76 119 {OP_WR_EMUL, TSDM_REG_TIMER_TICK, 0x1},
120 {OP_WR_FPGA, TSDM_REG_TIMER_TICK, 0xa},
121#define TSDM_COMMON_END 86
122#define TCM_COMMON_START 86
115 {OP_WR, TCM_REG_XX_MAX_LL_SZ, 0x20}, 123 {OP_WR, TCM_REG_XX_MAX_LL_SZ, 0x20},
116 {OP_WR, TCM_REG_XX_OVFL_EVNT_ID, 0x32}, 124 {OP_WR, TCM_REG_XX_OVFL_EVNT_ID, 0x32},
117 {OP_WR, TCM_REG_TQM_TCM_HDR_P, 0x2150020}, 125 {OP_WR, TCM_REG_TQM_TCM_HDR_P, 0x2150020},
@@ -143,9 +151,14 @@ static const struct raw_op init_ops[] = {
143 {OP_WR, TCM_REG_N_SM_CTX_LD_3, 0x8}, 151 {OP_WR, TCM_REG_N_SM_CTX_LD_3, 0x8},
144 {OP_ZR, TCM_REG_N_SM_CTX_LD_4, 0x4}, 152 {OP_ZR, TCM_REG_N_SM_CTX_LD_4, 0x4},
145 {OP_WR, TCM_REG_TCM_REG0_SZ, 0x6}, 153 {OP_WR, TCM_REG_TCM_REG0_SZ, 0x6},
146 {OP_WR, TCM_REG_PHYS_QNUM0_0, 0xd}, 154 {OP_WR_E1, TCM_REG_PHYS_QNUM0_0, 0xd},
147 {OP_WR, TCM_REG_PHYS_QNUM0_1, 0x2d}, 155 {OP_WR_E1, TCM_REG_PHYS_QNUM0_1, 0x2d},
148 {OP_ZR, TCM_REG_PHYS_QNUM1_0, 0x6}, 156 {OP_WR_E1, TCM_REG_PHYS_QNUM1_0, 0x7},
157 {OP_WR_E1, TCM_REG_PHYS_QNUM1_1, 0x27},
158 {OP_WR_E1, TCM_REG_PHYS_QNUM2_0, 0x7},
159 {OP_WR_E1, TCM_REG_PHYS_QNUM2_1, 0x27},
160 {OP_WR_E1, TCM_REG_PHYS_QNUM3_0, 0x7},
161 {OP_WR_E1, TCM_REG_PHYS_QNUM3_1, 0x27},
149 {OP_WR, TCM_REG_TCM_STORM0_IFEN, 0x1}, 162 {OP_WR, TCM_REG_TCM_STORM0_IFEN, 0x1},
150 {OP_WR, TCM_REG_TCM_STORM1_IFEN, 0x1}, 163 {OP_WR, TCM_REG_TCM_STORM1_IFEN, 0x1},
151 {OP_WR, TCM_REG_TCM_TQM_IFEN, 0x1}, 164 {OP_WR, TCM_REG_TCM_TQM_IFEN, 0x1},
@@ -162,23 +175,75 @@ static const struct raw_op init_ops[] = {
162 {OP_WR, TCM_REG_CDU_SM_WR_IFEN, 0x1}, 175 {OP_WR, TCM_REG_CDU_SM_WR_IFEN, 0x1},
163 {OP_WR, TCM_REG_CDU_SM_RD_IFEN, 0x1}, 176 {OP_WR, TCM_REG_CDU_SM_RD_IFEN, 0x1},
164 {OP_WR, TCM_REG_TCM_CFC_IFEN, 0x1}, 177 {OP_WR, TCM_REG_TCM_CFC_IFEN, 0x1},
165#define TCM_COMMON_END 126 178#define TCM_COMMON_END 141
166#define BRB1_COMMON_START 126 179#define TCM_FUNC0_START 141
180 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0xd},
181 {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x7},
182 {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x7},
183 {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x7},
184#define TCM_FUNC0_END 145
185#define TCM_FUNC1_START 145
186 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x2d},
187 {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x27},
188 {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x27},
189 {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x27},
190#define TCM_FUNC1_END 149
191#define TCM_FUNC2_START 149
192 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0x1d},
193 {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x17},
194 {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x17},
195 {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x17},
196#define TCM_FUNC2_END 153
197#define TCM_FUNC3_START 153
198 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x3d},
199 {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x37},
200 {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x37},
201 {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x37},
202#define TCM_FUNC3_END 157
203#define TCM_FUNC4_START 157
204 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0x4d},
205 {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x47},
206 {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x47},
207 {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x47},
208#define TCM_FUNC4_END 161
209#define TCM_FUNC5_START 161
210 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x6d},
211 {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x67},
212 {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x67},
213 {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x67},
214#define TCM_FUNC5_END 165
215#define TCM_FUNC6_START 165
216 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0x5d},
217 {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x57},
218 {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x57},
219 {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x57},
220#define TCM_FUNC6_END 169
221#define TCM_FUNC7_START 169
222 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x7d},
223 {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x77},
224 {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x77},
225 {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x77},
226#define TCM_FUNC7_END 173
227#define BRB1_COMMON_START 173
167 {OP_SW, BRB1_REG_LL_RAM, 0x2000020}, 228 {OP_SW, BRB1_REG_LL_RAM, 0x2000020},
168 {OP_WR, BRB1_REG_SOFT_RESET, 0x1}, 229 {OP_WR, BRB1_REG_SOFT_RESET, 0x1},
169 {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_0, 0x0},
170 {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_1, 0x0},
171 {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_2, 0x0},
172 {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_3, 0x0},
173 {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_0, 0x0},
174 {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_1, 0x0},
175 {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_2, 0x0},
176 {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_3, 0x0},
177 {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_4, 0x0}, 230 {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_4, 0x0},
178 {OP_SW, BRB1_REG_FREE_LIST_PRS_CRDT, 0x30220}, 231 {OP_SW, BRB1_REG_FREE_LIST_PRS_CRDT, 0x30220},
179 {OP_WR, BRB1_REG_SOFT_RESET, 0x0}, 232 {OP_WR, BRB1_REG_SOFT_RESET, 0x0},
180#define BRB1_COMMON_END 139 233#define BRB1_COMMON_END 178
181#define TSEM_COMMON_START 139 234#define BRB1_PORT0_START 178
235 {OP_WR_E1, BRB1_REG_PAUSE_LOW_THRESHOLD_0, 0xb8},
236 {OP_WR_E1, BRB1_REG_PAUSE_HIGH_THRESHOLD_0, 0x114},
237 {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_0, 0x0},
238 {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_0, 0x0},
239#define BRB1_PORT0_END 182
240#define BRB1_PORT1_START 182
241 {OP_WR_E1, BRB1_REG_PAUSE_LOW_THRESHOLD_1, 0xb8},
242 {OP_WR_E1, BRB1_REG_PAUSE_HIGH_THRESHOLD_1, 0x114},
243 {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_1, 0x0},
244 {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_1, 0x0},
245#define BRB1_PORT1_END 186
246#define TSEM_COMMON_START 186
182 {OP_RD, TSEM_REG_MSG_NUM_FIC0, 0x0}, 247 {OP_RD, TSEM_REG_MSG_NUM_FIC0, 0x0},
183 {OP_RD, TSEM_REG_MSG_NUM_FIC1, 0x0}, 248 {OP_RD, TSEM_REG_MSG_NUM_FIC1, 0x0},
184 {OP_RD, TSEM_REG_MSG_NUM_FOC0, 0x0}, 249 {OP_RD, TSEM_REG_MSG_NUM_FOC0, 0x0},
@@ -222,106 +287,243 @@ static const struct raw_op init_ops[] = {
222 {OP_WR, TSEM_REG_FAST_MEMORY + 0x18040, 0x18}, 287 {OP_WR, TSEM_REG_FAST_MEMORY + 0x18040, 0x18},
223 {OP_WR, TSEM_REG_FAST_MEMORY + 0x18080, 0xc}, 288 {OP_WR, TSEM_REG_FAST_MEMORY + 0x18080, 0xc},
224 {OP_WR, TSEM_REG_FAST_MEMORY + 0x180c0, 0x20}, 289 {OP_WR, TSEM_REG_FAST_MEMORY + 0x180c0, 0x20},
225 {OP_WR, TSEM_REG_FAST_MEMORY + 0x18300, 0x7a120}, 290 {OP_WR_ASIC, TSEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
291 {OP_WR_EMUL, TSEM_REG_FAST_MEMORY + 0x18300, 0x138},
292 {OP_WR_FPGA, TSEM_REG_FAST_MEMORY + 0x18300, 0x1388},
226 {OP_WR, TSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4}, 293 {OP_WR, TSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
227 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x2000, 0x1b3}, 294 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2000, 0xb2},
228 {OP_SW, TSEM_REG_FAST_MEMORY + 0x2000 + 0x6cc, 0x10223}, 295 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x11480, 0x1},
229 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1020, 0xc8}, 296 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x23c8, 0xc1},
230 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1000, 0x2}, 297 {OP_WR_EMUL_E1H, TSEM_REG_FAST_MEMORY + 0x11480, 0x0},
231 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x800, 0x2}, 298 {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x23c8 + 0x304, 0x10223},
232 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x808, 0x2}, 299 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x1000, 0x2b3},
233 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x810, 0x4}, 300 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1020, 0xc8},
234 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1fa0, 0x4}, 301 {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x1000 + 0xacc, 0x10223},
235 {OP_SW, TSEM_REG_FAST_MEMORY + 0x4cf0, 0x80224}, 302 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1000, 0x2},
236 {OP_ZP, TSEM_REG_INT_TABLE, 0x8c022c}, 303 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xa020, 0xc8},
237 {OP_ZP, TSEM_REG_PRAM, 0x3395024f}, 304 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1c18, 0x4},
238 {OP_ZP, TSEM_REG_PRAM + 0x8000, 0x2c760f35}, 305 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xa000, 0x2},
239 {OP_ZP, TSEM_REG_PRAM + 0x10000, 0x5e1a53}, 306 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x800, 0x2},
240 {OP_ZP, TSEM_REG_PRAM + 0x18000, 0x5e1a6b}, 307 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x1ad0, 0x0},
241 {OP_ZP, TSEM_REG_PRAM + 0x20000, 0x5e1a83}, 308 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x808, 0x2},
242 {OP_ZP, TSEM_REG_PRAM + 0x28000, 0x5e1a9b}, 309 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3b28, 0x6},
243 {OP_ZP, TSEM_REG_PRAM + 0x30000, 0x5e1ab3}, 310 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x810, 0x4},
244 {OP_ZP, TSEM_REG_PRAM + 0x38000, 0x5e1acb}, 311 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5000, 0x2},
245#define TSEM_COMMON_END 202 312 {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb0, 0x40224},
246#define TSEM_PORT0_START 202 313 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5008, 0x4},
247 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x4000, 0x16c}, 314 {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x4cb0, 0x80228},
248 {OP_SW, TSEM_REG_FAST_MEMORY + 0x4000 + 0x5b0, 0x21ae3}, 315 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5018, 0x4},
249 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1370, 0xa}, 316 {OP_ZP_E1, TSEM_REG_INT_TABLE, 0x940000},
250 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x13c0, 0x6}, 317 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5028, 0x4},
251 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1418, 0xc}, 318 {OP_WR_64_E1, TSEM_REG_INT_TABLE + 0x360, 0x140230},
252 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1478, 0x12}, 319 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5038, 0x4},
253 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1508, 0x90}, 320 {OP_ZP_E1, TSEM_REG_PRAM, 0x6ab70000},
254 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x800, 0x2}, 321 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5048, 0x4},
255 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x820, 0x10}, 322 {OP_WR_64_E1, TSEM_REG_PRAM + 0x117f0, 0x5d020232},
256 {OP_SW, TSEM_REG_FAST_MEMORY + 0x820 + 0x40, 0x21ae5}, 323 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5058, 0x4},
257 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x2908, 0xa}, 324 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5068, 0x4},
258#define TSEM_PORT0_END 213 325 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5078, 0x2},
259#define TSEM_PORT1_START 213 326 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4000, 0x2},
260 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x45b8, 0x16c}, 327 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4008, 0x2},
261 {OP_SW, TSEM_REG_FAST_MEMORY + 0x45b8 + 0x5b0, 0x21ae7}, 328 {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x6140, 0x200224},
262 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1398, 0xa}, 329 {OP_ZP_E1H, TSEM_REG_INT_TABLE, 0x960000},
263 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x13d8, 0x6}, 330 {OP_WR_64_E1H, TSEM_REG_INT_TABLE + 0x360, 0x140244},
264 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1448, 0xc}, 331 {OP_ZP_E1H, TSEM_REG_PRAM, 0x6d080000},
265 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x14c0, 0x12}, 332 {OP_WR_64_E1H, TSEM_REG_PRAM + 0x11c70, 0x5c720246},
266 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x1748, 0x90}, 333#define TSEM_COMMON_END 272
267 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x808, 0x2}, 334#define TSEM_PORT0_START 272
268 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x868, 0x10}, 335 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x22c8, 0x20},
269 {OP_SW, TSEM_REG_FAST_MEMORY + 0x868 + 0x40, 0x21ae9}, 336 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x2000, 0x16c},
270 {OP_ZR, TSEM_REG_FAST_MEMORY + 0x2930, 0xa}, 337 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x4000, 0xfc},
271#define TSEM_PORT1_END 224 338 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb000, 0x28},
272#define MISC_COMMON_START 224 339 {OP_WR_E1, TSEM_REG_FAST_MEMORY + 0x4b60, 0x0},
273 {OP_WR, MISC_REG_GRC_TIMEOUT_EN, 0x1}, 340 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb140, 0xc},
341 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1400, 0xa},
342 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x32c0, 0x12},
343 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1450, 0x6},
344 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3350, 0xfa},
345 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1500, 0xe},
346 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x8108, 0x2},
347 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1570, 0x12},
348 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x9c0, 0xbe},
349 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x800, 0x2},
350 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x820, 0xe},
351 {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb0, 0x20234},
352 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2908, 0x2},
353#define TSEM_PORT0_END 290
354#define TSEM_PORT1_START 290
355 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2348, 0x20},
356 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x25b0, 0x16c},
357 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x43f0, 0xfc},
358 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb0a0, 0x28},
359 {OP_WR_E1, TSEM_REG_FAST_MEMORY + 0x4b64, 0x0},
360 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb170, 0xc},
361 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1428, 0xa},
362 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3308, 0x12},
363 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1468, 0x6},
364 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3738, 0xfa},
365 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1538, 0xe},
366 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x8110, 0x2},
367 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x15b8, 0x12},
368 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0xcb8, 0xbe},
369 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x808, 0x2},
370 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x858, 0xe},
371 {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb8, 0x20236},
372 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2910, 0x2},
373#define TSEM_PORT1_END 308
374#define TSEM_FUNC0_START 308
375 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b60, 0x0},
376 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3000, 0xe},
377 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x31c0, 0x8},
378 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5000, 0x2},
379 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5080, 0x12},
380 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4000, 0x2},
381#define TSEM_FUNC0_END 314
382#define TSEM_FUNC1_START 314
383 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b64, 0x0},
384 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3038, 0xe},
385 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x31e0, 0x8},
386 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5010, 0x2},
387 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x50c8, 0x12},
388 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4008, 0x2},
389#define TSEM_FUNC1_END 320
390#define TSEM_FUNC2_START 320
391 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b68, 0x0},
392 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3070, 0xe},
393 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3200, 0x8},
394 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5020, 0x2},
395 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5110, 0x12},
396 {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4010, 0x20248},
397#define TSEM_FUNC2_END 326
398#define TSEM_FUNC3_START 326
399 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b6c, 0x0},
400 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30a8, 0xe},
401 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3220, 0x8},
402 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5030, 0x2},
403 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5158, 0x12},
404 {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4018, 0x2024a},
405#define TSEM_FUNC3_END 332
406#define TSEM_FUNC4_START 332
407 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b70, 0x0},
408 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30e0, 0xe},
409 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3240, 0x8},
410 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5040, 0x2},
411 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x51a0, 0x12},
412 {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4020, 0x2024c},
413#define TSEM_FUNC4_END 338
414#define TSEM_FUNC5_START 338
415 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b74, 0x0},
416 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3118, 0xe},
417 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3260, 0x8},
418 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5050, 0x2},
419 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x51e8, 0x12},
420 {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4028, 0x2024e},
421#define TSEM_FUNC5_END 344
422#define TSEM_FUNC6_START 344
423 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b78, 0x0},
424 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3150, 0xe},
425 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3280, 0x8},
426 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5060, 0x2},
427 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5230, 0x12},
428 {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4030, 0x20250},
429#define TSEM_FUNC6_END 350
430#define TSEM_FUNC7_START 350
431 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b7c, 0x0},
432 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3188, 0xe},
433 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x32a0, 0x8},
434 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5070, 0x2},
435 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5278, 0x12},
436 {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4038, 0x20252},
437#define TSEM_FUNC7_END 356
438#define MISC_COMMON_START 356
439 {OP_WR_E1, MISC_REG_GRC_TIMEOUT_EN, 0x1},
274 {OP_WR, MISC_REG_PLL_STORM_CTRL_1, 0x71d2911}, 440 {OP_WR, MISC_REG_PLL_STORM_CTRL_1, 0x71d2911},
275 {OP_WR, MISC_REG_PLL_STORM_CTRL_2, 0x0}, 441 {OP_WR, MISC_REG_PLL_STORM_CTRL_2, 0x0},
276 {OP_WR, MISC_REG_PLL_STORM_CTRL_3, 0x9c0424}, 442 {OP_WR, MISC_REG_PLL_STORM_CTRL_3, 0x9c0424},
277 {OP_WR, MISC_REG_PLL_STORM_CTRL_4, 0x0}, 443 {OP_WR, MISC_REG_PLL_STORM_CTRL_4, 0x0},
278 {OP_WR, MISC_REG_LCPLL_CTRL_1, 0x209}, 444 {OP_WR, MISC_REG_LCPLL_CTRL_1, 0x209},
279#define MISC_COMMON_END 230 445 {OP_WR_E1, MISC_REG_SPIO, 0xff000000},
280#define NIG_COMMON_START 230 446#define MISC_COMMON_END 363
447#define MISC_FUNC0_START 363
448 {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0},
449#define MISC_FUNC0_END 364
450#define MISC_FUNC1_START 364
451 {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0},
452#define MISC_FUNC1_END 365
453#define MISC_FUNC2_START 365
454 {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0},
455#define MISC_FUNC2_END 366
456#define MISC_FUNC3_START 366
457 {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0},
458#define MISC_FUNC3_END 367
459#define MISC_FUNC4_START 367
460 {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0},
461#define MISC_FUNC4_END 368
462#define MISC_FUNC5_START 368
463 {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0},
464#define MISC_FUNC5_END 369
465#define MISC_FUNC6_START 369
466 {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0},
467#define MISC_FUNC6_END 370
468#define MISC_FUNC7_START 370
469 {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0},
470#define MISC_FUNC7_END 371
471#define NIG_COMMON_START 371
281 {OP_WR, NIG_REG_PBF_LB_IN_EN, 0x1}, 472 {OP_WR, NIG_REG_PBF_LB_IN_EN, 0x1},
282 {OP_WR, NIG_REG_PRS_REQ_IN_EN, 0x1}, 473 {OP_WR, NIG_REG_PRS_REQ_IN_EN, 0x1},
283 {OP_WR, NIG_REG_EGRESS_DEBUG_IN_EN, 0x1}, 474 {OP_WR, NIG_REG_EGRESS_DEBUG_IN_EN, 0x1},
284 {OP_WR, NIG_REG_BRB_LB_OUT_EN, 0x1}, 475 {OP_WR, NIG_REG_BRB_LB_OUT_EN, 0x1},
285 {OP_WR, NIG_REG_PRS_EOP_OUT_EN, 0x1}, 476 {OP_WR, NIG_REG_PRS_EOP_OUT_EN, 0x1},
286#define NIG_COMMON_END 235 477#define NIG_COMMON_END 376
287#define NIG_PORT0_START 235 478#define NIG_PORT0_START 376
288 {OP_WR, NIG_REG_LLH0_CM_HEADER, 0x300000}, 479 {OP_WR, NIG_REG_LLH0_CM_HEADER, 0x300000},
289 {OP_WR, NIG_REG_LLH0_EVENT_ID, 0x26}, 480 {OP_WR, NIG_REG_LLH0_EVENT_ID, 0x28},
290 {OP_WR, NIG_REG_LLH0_ERROR_MASK, 0x0}, 481 {OP_WR, NIG_REG_LLH0_ERROR_MASK, 0x0},
291 {OP_WR, NIG_REG_LLH0_XCM_MASK, 0x4}, 482 {OP_WR, NIG_REG_LLH0_XCM_MASK, 0x4},
292 {OP_WR, NIG_REG_LLH0_BRB1_NOT_MCP, 0x1}, 483 {OP_WR, NIG_REG_LLH0_BRB1_NOT_MCP, 0x1},
293 {OP_WR, NIG_REG_STATUS_INTERRUPT_PORT0, 0x0}, 484 {OP_WR, NIG_REG_STATUS_INTERRUPT_PORT0, 0x0},
485 {OP_WR_E1H, NIG_REG_LLH0_CLS_TYPE, 0x1},
294 {OP_WR, NIG_REG_LLH0_XCM_INIT_CREDIT, 0x30}, 486 {OP_WR, NIG_REG_LLH0_XCM_INIT_CREDIT, 0x30},
295 {OP_WR, NIG_REG_BRB0_PAUSE_IN_EN, 0x1}, 487 {OP_WR, NIG_REG_BRB0_PAUSE_IN_EN, 0x1},
296 {OP_WR, NIG_REG_EGRESS_PBF0_IN_EN, 0x1}, 488 {OP_WR, NIG_REG_EGRESS_PBF0_IN_EN, 0x1},
297 {OP_WR, NIG_REG_BRB0_OUT_EN, 0x1}, 489 {OP_WR, NIG_REG_BRB0_OUT_EN, 0x1},
298 {OP_WR, NIG_REG_XCM0_OUT_EN, 0x1}, 490 {OP_WR, NIG_REG_XCM0_OUT_EN, 0x1},
299#define NIG_PORT0_END 246 491#define NIG_PORT0_END 388
300#define NIG_PORT1_START 246 492#define NIG_PORT1_START 388
301 {OP_WR, NIG_REG_LLH1_CM_HEADER, 0x300000}, 493 {OP_WR, NIG_REG_LLH1_CM_HEADER, 0x300000},
302 {OP_WR, NIG_REG_LLH1_EVENT_ID, 0x26}, 494 {OP_WR, NIG_REG_LLH1_EVENT_ID, 0x28},
303 {OP_WR, NIG_REG_LLH1_ERROR_MASK, 0x0}, 495 {OP_WR, NIG_REG_LLH1_ERROR_MASK, 0x0},
304 {OP_WR, NIG_REG_LLH1_XCM_MASK, 0x4}, 496 {OP_WR, NIG_REG_LLH1_XCM_MASK, 0x4},
305 {OP_WR, NIG_REG_LLH1_BRB1_NOT_MCP, 0x1}, 497 {OP_WR, NIG_REG_LLH1_BRB1_NOT_MCP, 0x1},
306 {OP_WR, NIG_REG_STATUS_INTERRUPT_PORT1, 0x0}, 498 {OP_WR, NIG_REG_STATUS_INTERRUPT_PORT1, 0x0},
499 {OP_WR_E1H, NIG_REG_LLH1_CLS_TYPE, 0x1},
307 {OP_WR, NIG_REG_LLH1_XCM_INIT_CREDIT, 0x30}, 500 {OP_WR, NIG_REG_LLH1_XCM_INIT_CREDIT, 0x30},
308 {OP_WR, NIG_REG_BRB1_PAUSE_IN_EN, 0x1}, 501 {OP_WR, NIG_REG_BRB1_PAUSE_IN_EN, 0x1},
309 {OP_WR, NIG_REG_EGRESS_PBF1_IN_EN, 0x1}, 502 {OP_WR, NIG_REG_EGRESS_PBF1_IN_EN, 0x1},
310 {OP_WR, NIG_REG_BRB1_OUT_EN, 0x1}, 503 {OP_WR, NIG_REG_BRB1_OUT_EN, 0x1},
311 {OP_WR, NIG_REG_XCM1_OUT_EN, 0x1}, 504 {OP_WR, NIG_REG_XCM1_OUT_EN, 0x1},
312#define NIG_PORT1_END 257 505#define NIG_PORT1_END 400
313#define UPB_COMMON_START 257 506#define UPB_COMMON_START 400
314 {OP_WR, GRCBASE_UPB + PB_REG_CONTROL, 0x20}, 507 {OP_WR, GRCBASE_UPB + PB_REG_CONTROL, 0x20},
315#define UPB_COMMON_END 258 508#define UPB_COMMON_END 401
316#define CSDM_COMMON_START 258 509#define CSDM_COMMON_START 401
317 {OP_WR, CSDM_REG_CFC_RSP_START_ADDR, 0xa11}, 510 {OP_WR_E1, CSDM_REG_CFC_RSP_START_ADDR, 0xa11},
318 {OP_WR, CSDM_REG_CMP_COUNTER_START_ADDR, 0xa00}, 511 {OP_WR_E1H, CSDM_REG_CFC_RSP_START_ADDR, 0x211},
319 {OP_WR, CSDM_REG_Q_COUNTER_START_ADDR, 0xa04}, 512 {OP_WR_E1, CSDM_REG_CMP_COUNTER_START_ADDR, 0xa00},
513 {OP_WR_E1H, CSDM_REG_CMP_COUNTER_START_ADDR, 0x200},
514 {OP_WR_E1, CSDM_REG_Q_COUNTER_START_ADDR, 0xa04},
515 {OP_WR_E1H, CSDM_REG_Q_COUNTER_START_ADDR, 0x204},
320 {OP_WR, CSDM_REG_CMP_COUNTER_MAX0, 0xffff}, 516 {OP_WR, CSDM_REG_CMP_COUNTER_MAX0, 0xffff},
321 {OP_WR, CSDM_REG_CMP_COUNTER_MAX1, 0xffff}, 517 {OP_WR, CSDM_REG_CMP_COUNTER_MAX1, 0xffff},
322 {OP_WR, CSDM_REG_CMP_COUNTER_MAX2, 0xffff}, 518 {OP_WR, CSDM_REG_CMP_COUNTER_MAX2, 0xffff},
323 {OP_WR, CSDM_REG_CMP_COUNTER_MAX3, 0xffff}, 519 {OP_WR, CSDM_REG_CMP_COUNTER_MAX3, 0xffff},
324 {OP_ZR, CSDM_REG_AGG_INT_EVENT_0, 0x80}, 520 {OP_WR, CSDM_REG_AGG_INT_EVENT_0, 0xc6},
521 {OP_WR, CSDM_REG_AGG_INT_EVENT_1, 0x0},
522 {OP_WR, CSDM_REG_AGG_INT_EVENT_2, 0x34},
523 {OP_WR, CSDM_REG_AGG_INT_EVENT_3, 0x35},
524 {OP_ZR, CSDM_REG_AGG_INT_EVENT_4, 0x1c},
525 {OP_WR, CSDM_REG_AGG_INT_T_0, 0x1},
526 {OP_ZR, CSDM_REG_AGG_INT_T_1, 0x5f},
325 {OP_WR, CSDM_REG_ENABLE_IN1, 0x7ffffff}, 527 {OP_WR, CSDM_REG_ENABLE_IN1, 0x7ffffff},
326 {OP_WR, CSDM_REG_ENABLE_IN2, 0x3f}, 528 {OP_WR, CSDM_REG_ENABLE_IN2, 0x3f},
327 {OP_WR, CSDM_REG_ENABLE_OUT1, 0x7ffffff}, 529 {OP_WR, CSDM_REG_ENABLE_OUT1, 0x7ffffff},
@@ -340,19 +542,29 @@ static const struct raw_op init_ops[] = {
340 {OP_RD, CSDM_REG_NUM_OF_PKT_END_MSG, 0x0}, 542 {OP_RD, CSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
341 {OP_RD, CSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0}, 543 {OP_RD, CSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
342 {OP_RD, CSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0}, 544 {OP_RD, CSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
343 {OP_WR, CSDM_REG_TIMER_TICK, 0x3e8}, 545 {OP_WR_E1, CSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
344#define CSDM_COMMON_END 285 546 {OP_WR_ASIC, CSDM_REG_TIMER_TICK, 0x3e8},
345#define USDM_COMMON_START 285 547 {OP_WR_EMUL, CSDM_REG_TIMER_TICK, 0x1},
346 {OP_WR, USDM_REG_CFC_RSP_START_ADDR, 0xa11}, 548 {OP_WR_FPGA, CSDM_REG_TIMER_TICK, 0xa},
347 {OP_WR, USDM_REG_CMP_COUNTER_START_ADDR, 0xa00}, 549#define CSDM_COMMON_END 440
348 {OP_WR, USDM_REG_Q_COUNTER_START_ADDR, 0xa04}, 550#define USDM_COMMON_START 440
349 {OP_WR, USDM_REG_PCK_END_MSG_START_ADDR, 0xa21}, 551 {OP_WR_E1, USDM_REG_CFC_RSP_START_ADDR, 0xa11},
552 {OP_WR_E1H, USDM_REG_CFC_RSP_START_ADDR, 0x411},
553 {OP_WR_E1, USDM_REG_CMP_COUNTER_START_ADDR, 0xa00},
554 {OP_WR_E1H, USDM_REG_CMP_COUNTER_START_ADDR, 0x400},
555 {OP_WR_E1, USDM_REG_Q_COUNTER_START_ADDR, 0xa04},
556 {OP_WR_E1H, USDM_REG_Q_COUNTER_START_ADDR, 0x404},
557 {OP_WR_E1, USDM_REG_PCK_END_MSG_START_ADDR, 0xa21},
558 {OP_WR_E1H, USDM_REG_PCK_END_MSG_START_ADDR, 0x421},
350 {OP_WR, USDM_REG_CMP_COUNTER_MAX0, 0xffff}, 559 {OP_WR, USDM_REG_CMP_COUNTER_MAX0, 0xffff},
351 {OP_WR, USDM_REG_CMP_COUNTER_MAX1, 0xffff}, 560 {OP_WR, USDM_REG_CMP_COUNTER_MAX1, 0xffff},
352 {OP_WR, USDM_REG_CMP_COUNTER_MAX2, 0xffff}, 561 {OP_WR, USDM_REG_CMP_COUNTER_MAX2, 0xffff},
353 {OP_WR, USDM_REG_CMP_COUNTER_MAX3, 0xffff}, 562 {OP_WR, USDM_REG_CMP_COUNTER_MAX3, 0xffff},
354 {OP_WR, USDM_REG_AGG_INT_EVENT_0, 0x46}, 563 {OP_WR, USDM_REG_AGG_INT_EVENT_0, 0x46},
355 {OP_ZR, USDM_REG_AGG_INT_EVENT_1, 0x5f}, 564 {OP_WR, USDM_REG_AGG_INT_EVENT_1, 0x5},
565 {OP_WR, USDM_REG_AGG_INT_EVENT_2, 0x34},
566 {OP_WR, USDM_REG_AGG_INT_EVENT_3, 0x35},
567 {OP_ZR, USDM_REG_AGG_INT_EVENT_4, 0x5c},
356 {OP_WR, USDM_REG_AGG_INT_MODE_0, 0x1}, 568 {OP_WR, USDM_REG_AGG_INT_MODE_0, 0x1},
357 {OP_ZR, USDM_REG_AGG_INT_MODE_1, 0x1f}, 569 {OP_ZR, USDM_REG_AGG_INT_MODE_1, 0x1f},
358 {OP_WR, USDM_REG_ENABLE_IN1, 0x7ffffff}, 570 {OP_WR, USDM_REG_ENABLE_IN1, 0x7ffffff},
@@ -374,9 +586,12 @@ static const struct raw_op init_ops[] = {
374 {OP_RD, USDM_REG_NUM_OF_PKT_END_MSG, 0x0}, 586 {OP_RD, USDM_REG_NUM_OF_PKT_END_MSG, 0x0},
375 {OP_RD, USDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0}, 587 {OP_RD, USDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
376 {OP_RD, USDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0}, 588 {OP_RD, USDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
377 {OP_WR, USDM_REG_TIMER_TICK, 0x3e8}, 589 {OP_WR_E1, USDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
378#define USDM_COMMON_END 317 590 {OP_WR_ASIC, USDM_REG_TIMER_TICK, 0x3e8},
379#define CCM_COMMON_START 317 591 {OP_WR_EMUL, USDM_REG_TIMER_TICK, 0x1},
592 {OP_WR_FPGA, USDM_REG_TIMER_TICK, 0xa},
593#define USDM_COMMON_END 482
594#define CCM_COMMON_START 482
380 {OP_WR, CCM_REG_XX_OVFL_EVNT_ID, 0x32}, 595 {OP_WR, CCM_REG_XX_OVFL_EVNT_ID, 0x32},
381 {OP_WR, CCM_REG_CQM_CCM_HDR_P, 0x2150020}, 596 {OP_WR, CCM_REG_CQM_CCM_HDR_P, 0x2150020},
382 {OP_WR, CCM_REG_CQM_CCM_HDR_S, 0x2150020}, 597 {OP_WR, CCM_REG_CQM_CCM_HDR_S, 0x2150020},
@@ -401,23 +616,28 @@ static const struct raw_op init_ops[] = {
401 {OP_WR, CCM_REG_XX_INIT_CRD, 0x3}, 616 {OP_WR, CCM_REG_XX_INIT_CRD, 0x3},
402 {OP_WR, CCM_REG_XX_MSG_NUM, 0x18}, 617 {OP_WR, CCM_REG_XX_MSG_NUM, 0x18},
403 {OP_ZR, CCM_REG_XX_TABLE, 0x12}, 618 {OP_ZR, CCM_REG_XX_TABLE, 0x12},
404 {OP_SW, CCM_REG_XX_DESCR_TABLE, 0x241aeb}, 619 {OP_SW_E1, CCM_REG_XX_DESCR_TABLE, 0x240238},
620 {OP_SW_E1H, CCM_REG_XX_DESCR_TABLE, 0x240254},
405 {OP_WR, CCM_REG_N_SM_CTX_LD_0, 0x1}, 621 {OP_WR, CCM_REG_N_SM_CTX_LD_0, 0x1},
406 {OP_WR, CCM_REG_N_SM_CTX_LD_1, 0x2}, 622 {OP_WR, CCM_REG_N_SM_CTX_LD_1, 0x2},
407 {OP_WR, CCM_REG_N_SM_CTX_LD_2, 0x8}, 623 {OP_WR, CCM_REG_N_SM_CTX_LD_2, 0x8},
408 {OP_WR, CCM_REG_N_SM_CTX_LD_3, 0x8}, 624 {OP_WR, CCM_REG_N_SM_CTX_LD_3, 0x8},
409 {OP_ZR, CCM_REG_N_SM_CTX_LD_4, 0x4}, 625 {OP_ZR, CCM_REG_N_SM_CTX_LD_4, 0x4},
410 {OP_WR, CCM_REG_CCM_REG0_SZ, 0x4}, 626 {OP_WR, CCM_REG_CCM_REG0_SZ, 0x4},
411 {OP_WR, CCM_REG_QOS_PHYS_QNUM0_0, 0x9}, 627 {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM0_0, 0x9},
412 {OP_WR, CCM_REG_QOS_PHYS_QNUM0_1, 0x29}, 628 {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM0_1, 0x29},
413 {OP_WR, CCM_REG_QOS_PHYS_QNUM1_0, 0xa}, 629 {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM1_0, 0xa},
414 {OP_WR, CCM_REG_QOS_PHYS_QNUM1_1, 0x2a}, 630 {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM1_1, 0x2a},
415 {OP_ZR, CCM_REG_QOS_PHYS_QNUM2_0, 0x4}, 631 {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM2_0, 0x7},
416 {OP_WR, CCM_REG_PHYS_QNUM1_0, 0xc}, 632 {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM2_1, 0x27},
417 {OP_WR, CCM_REG_PHYS_QNUM1_1, 0x2c}, 633 {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM3_0, 0x7},
418 {OP_WR, CCM_REG_PHYS_QNUM2_0, 0xb}, 634 {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM3_1, 0x27},
419 {OP_WR, CCM_REG_PHYS_QNUM2_1, 0x2b}, 635 {OP_WR_E1, CCM_REG_PHYS_QNUM1_0, 0xc},
420 {OP_ZR, CCM_REG_PHYS_QNUM3_0, 0x2}, 636 {OP_WR_E1, CCM_REG_PHYS_QNUM1_1, 0x2c},
637 {OP_WR_E1, CCM_REG_PHYS_QNUM2_0, 0xc},
638 {OP_WR_E1, CCM_REG_PHYS_QNUM2_1, 0x2c},
639 {OP_WR_E1, CCM_REG_PHYS_QNUM3_0, 0xc},
640 {OP_WR_E1, CCM_REG_PHYS_QNUM3_1, 0x2c},
421 {OP_WR, CCM_REG_CCM_STORM0_IFEN, 0x1}, 641 {OP_WR, CCM_REG_CCM_STORM0_IFEN, 0x1},
422 {OP_WR, CCM_REG_CCM_STORM1_IFEN, 0x1}, 642 {OP_WR, CCM_REG_CCM_STORM1_IFEN, 0x1},
423 {OP_WR, CCM_REG_CCM_CQM_IFEN, 0x1}, 643 {OP_WR, CCM_REG_CCM_CQM_IFEN, 0x1},
@@ -433,8 +653,80 @@ static const struct raw_op init_ops[] = {
433 {OP_WR, CCM_REG_CDU_SM_WR_IFEN, 0x1}, 653 {OP_WR, CCM_REG_CDU_SM_WR_IFEN, 0x1},
434 {OP_WR, CCM_REG_CDU_SM_RD_IFEN, 0x1}, 654 {OP_WR, CCM_REG_CDU_SM_RD_IFEN, 0x1},
435 {OP_WR, CCM_REG_CCM_CFC_IFEN, 0x1}, 655 {OP_WR, CCM_REG_CCM_CFC_IFEN, 0x1},
436#define CCM_COMMON_END 373 656#define CCM_COMMON_END 543
437#define UCM_COMMON_START 373 657#define CCM_FUNC0_START 543
658 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x9},
659 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0xa},
660 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x7},
661 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_0, 0x7},
662 {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0xc},
663 {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0xb},
664 {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x7},
665#define CCM_FUNC0_END 550
666#define CCM_FUNC1_START 550
667 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x29},
668 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x2a},
669 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x27},
670 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_1, 0x27},
671 {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x2c},
672 {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x2b},
673 {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x27},
674#define CCM_FUNC1_END 557
675#define CCM_FUNC2_START 557
676 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x19},
677 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0x1a},
678 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x17},
679 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_0, 0x17},
680 {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0x1c},
681 {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0x1b},
682 {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x17},
683#define CCM_FUNC2_END 564
684#define CCM_FUNC3_START 564
685 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x39},
686 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x3a},
687 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x37},
688 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_1, 0x37},
689 {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x3c},
690 {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x3b},
691 {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x37},
692#define CCM_FUNC3_END 571
693#define CCM_FUNC4_START 571
694 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x49},
695 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0x4a},
696 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x47},
697 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_0, 0x47},
698 {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0x4c},
699 {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0x4b},
700 {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x47},
701#define CCM_FUNC4_END 578
702#define CCM_FUNC5_START 578
703 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x69},
704 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x6a},
705 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x67},
706 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_1, 0x67},
707 {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x6c},
708 {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x6b},
709 {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x67},
710#define CCM_FUNC5_END 585
711#define CCM_FUNC6_START 585
712 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x59},
713 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0x5a},
714 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x57},
715 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_0, 0x57},
716 {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0x5c},
717 {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0x5b},
718 {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x57},
719#define CCM_FUNC6_END 592
720#define CCM_FUNC7_START 592
721 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x79},
722 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x7a},
723 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x77},
724 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_1, 0x77},
725 {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x7c},
726 {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x7b},
727 {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x77},
728#define CCM_FUNC7_END 599
729#define UCM_COMMON_START 599
438 {OP_WR, UCM_REG_XX_OVFL_EVNT_ID, 0x32}, 730 {OP_WR, UCM_REG_XX_OVFL_EVNT_ID, 0x32},
439 {OP_WR, UCM_REG_UQM_UCM_HDR_P, 0x2150020}, 731 {OP_WR, UCM_REG_UQM_UCM_HDR_P, 0x2150020},
440 {OP_WR, UCM_REG_UQM_UCM_HDR_S, 0x2150020}, 732 {OP_WR, UCM_REG_UQM_UCM_HDR_S, 0x2150020},
@@ -457,20 +749,23 @@ static const struct raw_op init_ops[] = {
457 {OP_WR, UCM_REG_FIC1_INIT_CRD, 0x40}, 749 {OP_WR, UCM_REG_FIC1_INIT_CRD, 0x40},
458 {OP_WR, UCM_REG_TM_INIT_CRD, 0x4}, 750 {OP_WR, UCM_REG_TM_INIT_CRD, 0x4},
459 {OP_WR, UCM_REG_UQM_INIT_CRD, 0x20}, 751 {OP_WR, UCM_REG_UQM_INIT_CRD, 0x20},
460 {OP_WR, UCM_REG_XX_INIT_CRD, 0xc}, 752 {OP_WR, UCM_REG_XX_INIT_CRD, 0xe},
461 {OP_WR, UCM_REG_XX_MSG_NUM, 0x20}, 753 {OP_WR, UCM_REG_XX_MSG_NUM, 0x1b},
462 {OP_ZR, UCM_REG_XX_TABLE, 0x12}, 754 {OP_ZR, UCM_REG_XX_TABLE, 0x12},
463 {OP_SW, UCM_REG_XX_DESCR_TABLE, 0x201b0f}, 755 {OP_SW_E1, UCM_REG_XX_DESCR_TABLE, 0x1b025c},
464 {OP_WR, UCM_REG_N_SM_CTX_LD_0, 0xa}, 756 {OP_SW_E1H, UCM_REG_XX_DESCR_TABLE, 0x1b0278},
757 {OP_WR, UCM_REG_N_SM_CTX_LD_0, 0x10},
465 {OP_WR, UCM_REG_N_SM_CTX_LD_1, 0x7}, 758 {OP_WR, UCM_REG_N_SM_CTX_LD_1, 0x7},
466 {OP_WR, UCM_REG_N_SM_CTX_LD_2, 0xf}, 759 {OP_WR, UCM_REG_N_SM_CTX_LD_2, 0xf},
467 {OP_WR, UCM_REG_N_SM_CTX_LD_3, 0x10}, 760 {OP_WR, UCM_REG_N_SM_CTX_LD_3, 0x10},
468 {OP_ZR, UCM_REG_N_SM_CTX_LD_4, 0x4}, 761 {OP_ZR_E1, UCM_REG_N_SM_CTX_LD_4, 0x4},
762 {OP_WR_E1H, UCM_REG_N_SM_CTX_LD_4, 0xd},
763 {OP_ZR_E1H, UCM_REG_N_SM_CTX_LD_5, 0x3},
469 {OP_WR, UCM_REG_UCM_REG0_SZ, 0x3}, 764 {OP_WR, UCM_REG_UCM_REG0_SZ, 0x3},
470 {OP_WR, UCM_REG_PHYS_QNUM0_0, 0xf}, 765 {OP_WR_E1, UCM_REG_PHYS_QNUM0_0, 0xf},
471 {OP_WR, UCM_REG_PHYS_QNUM0_1, 0x2f}, 766 {OP_WR_E1, UCM_REG_PHYS_QNUM0_1, 0x2f},
472 {OP_WR, UCM_REG_PHYS_QNUM1_0, 0xe}, 767 {OP_WR_E1, UCM_REG_PHYS_QNUM1_0, 0xe},
473 {OP_WR, UCM_REG_PHYS_QNUM1_1, 0x2e}, 768 {OP_WR_E1, UCM_REG_PHYS_QNUM1_1, 0x2e},
474 {OP_WR, UCM_REG_UCM_STORM0_IFEN, 0x1}, 769 {OP_WR, UCM_REG_UCM_STORM0_IFEN, 0x1},
475 {OP_WR, UCM_REG_UCM_STORM1_IFEN, 0x1}, 770 {OP_WR, UCM_REG_UCM_STORM1_IFEN, 0x1},
476 {OP_WR, UCM_REG_UCM_UQM_IFEN, 0x1}, 771 {OP_WR, UCM_REG_UCM_UQM_IFEN, 0x1},
@@ -488,8 +783,56 @@ static const struct raw_op init_ops[] = {
488 {OP_WR, UCM_REG_CDU_SM_WR_IFEN, 0x1}, 783 {OP_WR, UCM_REG_CDU_SM_WR_IFEN, 0x1},
489 {OP_WR, UCM_REG_CDU_SM_RD_IFEN, 0x1}, 784 {OP_WR, UCM_REG_CDU_SM_RD_IFEN, 0x1},
490 {OP_WR, UCM_REG_UCM_CFC_IFEN, 0x1}, 785 {OP_WR, UCM_REG_UCM_CFC_IFEN, 0x1},
491#define UCM_COMMON_END 426 786#define UCM_COMMON_END 655
492#define USEM_COMMON_START 426 787#define UCM_FUNC0_START 655
788 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0xf},
789 {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0xe},
790 {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0},
791 {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0},
792#define UCM_FUNC0_END 659
793#define UCM_FUNC1_START 659
794 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x2f},
795 {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x2e},
796 {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0},
797 {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0},
798#define UCM_FUNC1_END 663
799#define UCM_FUNC2_START 663
800 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0x1f},
801 {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0x1e},
802 {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0},
803 {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0},
804#define UCM_FUNC2_END 667
805#define UCM_FUNC3_START 667
806 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x3f},
807 {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x3e},
808 {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0},
809 {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0},
810#define UCM_FUNC3_END 671
811#define UCM_FUNC4_START 671
812 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0x4f},
813 {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0x4e},
814 {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0},
815 {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0},
816#define UCM_FUNC4_END 675
817#define UCM_FUNC5_START 675
818 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x6f},
819 {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x6e},
820 {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0},
821 {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0},
822#define UCM_FUNC5_END 679
823#define UCM_FUNC6_START 679
824 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0x5f},
825 {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0x5e},
826 {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0},
827 {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0},
828#define UCM_FUNC6_END 683
829#define UCM_FUNC7_START 683
830 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x7f},
831 {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x7e},
832 {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0},
833 {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0},
834#define UCM_FUNC7_END 687
835#define USEM_COMMON_START 687
493 {OP_RD, USEM_REG_MSG_NUM_FIC0, 0x0}, 836 {OP_RD, USEM_REG_MSG_NUM_FIC0, 0x0},
494 {OP_RD, USEM_REG_MSG_NUM_FIC1, 0x0}, 837 {OP_RD, USEM_REG_MSG_NUM_FIC1, 0x0},
495 {OP_RD, USEM_REG_MSG_NUM_FOC0, 0x0}, 838 {OP_RD, USEM_REG_MSG_NUM_FOC0, 0x0},
@@ -533,87 +876,191 @@ static const struct raw_op init_ops[] = {
533 {OP_WR, USEM_REG_FAST_MEMORY + 0x18040, 0x4e}, 876 {OP_WR, USEM_REG_FAST_MEMORY + 0x18040, 0x4e},
534 {OP_WR, USEM_REG_FAST_MEMORY + 0x18080, 0x10}, 877 {OP_WR, USEM_REG_FAST_MEMORY + 0x18080, 0x10},
535 {OP_WR, USEM_REG_FAST_MEMORY + 0x180c0, 0x20}, 878 {OP_WR, USEM_REG_FAST_MEMORY + 0x180c0, 0x20},
536 {OP_WR, USEM_REG_FAST_MEMORY + 0x18300, 0x7a120}, 879 {OP_WR_ASIC, USEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
880 {OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x18300, 0x138},
881 {OP_WR_FPGA, USEM_REG_FAST_MEMORY + 0x18300, 0x1388},
537 {OP_WR, USEM_REG_FAST_MEMORY + 0x183c0, 0x1f4}, 882 {OP_WR, USEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
538 {OP_WR, USEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500}, 883 {OP_WR_ASIC, USEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500},
539 {OP_ZR, USEM_REG_FAST_MEMORY + 0x5000, 0x102}, 884 {OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x18380, 0x4c4b4},
540 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1020, 0xc8}, 885 {OP_WR_FPGA, USEM_REG_FAST_MEMORY + 0x18380, 0x4c4b40},
541 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1000, 0x2}, 886 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5000, 0x102},
542 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1e20, 0x40}, 887 {OP_WR_EMUL_E1H, USEM_REG_FAST_MEMORY + 0x11480, 0x0},
543 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3000, 0x400}, 888 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1020, 0xc8},
544 {OP_ZR, USEM_REG_FAST_MEMORY + 0x2400, 0x2}, 889 {OP_WR_E1H, USEM_REG_FAST_MEMORY + 0x11480, 0x1},
545 {OP_ZR, USEM_REG_FAST_MEMORY + 0x2408, 0x2}, 890 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1000, 0x2},
546 {OP_ZR, USEM_REG_FAST_MEMORY + 0x2410, 0x6}, 891 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x2000, 0x102},
547 {OP_SW, USEM_REG_FAST_MEMORY + 0x2410 + 0x18, 0x21b2f}, 892 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x57e8, 0x4},
548 {OP_ZR, USEM_REG_FAST_MEMORY + 0x4b68, 0x2}, 893 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x8020, 0xc8},
549 {OP_SW, USEM_REG_FAST_MEMORY + 0x4b68 + 0x8, 0x21b31}, 894 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x57d0, 0x5},
550 {OP_ZR, USEM_REG_FAST_MEMORY + 0x4b10, 0x2}, 895 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x8000, 0x2},
551 {OP_SW, USEM_REG_FAST_MEMORY + 0x2c30, 0x21b33}, 896 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x57d0 + 0x14, 0x10277},
897 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3760, 0x4},
898 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1e20, 0x42},
899 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3738, 0x9},
900 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3000, 0x400},
901 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x3738 + 0x24, 0x10293},
902 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x2c00, 0x2},
903 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3180, 0x42},
904 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x2c00 + 0x8, 0x20278},
905 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5000, 0x400},
906 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b68, 0x2},
907 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4000, 0x2},
908 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x4b68 + 0x8, 0x2027a},
909 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x4000 + 0x8, 0x20294},
910 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b10, 0x2},
911 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b68, 0x2},
912 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x2830, 0x2027c},
913 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x6b68 + 0x8, 0x20296},
914 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b10, 0x2},
915 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x74c0, 0x20298},
552 {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x1000000}, 916 {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x1000000},
553 {OP_SW, USEM_REG_FAST_MEMORY + 0x10c00, 0x101b35}, 917 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c00, 0x10027e},
918 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x10c00, 0x10029a},
554 {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x0}, 919 {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x0},
555 {OP_SW, USEM_REG_FAST_MEMORY + 0x10c40, 0x101b45}, 920 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c40, 0x10028e},
556 {OP_ZP, USEM_REG_INT_TABLE, 0xb41b55}, 921 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x10c40, 0x1002aa},
557 {OP_ZP, USEM_REG_PRAM, 0x32d01b82}, 922 {OP_ZP_E1, USEM_REG_INT_TABLE, 0xc20000},
558 {OP_ZP, USEM_REG_PRAM + 0x8000, 0x32172836}, 923 {OP_ZP_E1H, USEM_REG_INT_TABLE, 0xc40000},
559 {OP_ZP, USEM_REG_PRAM + 0x10000, 0x1a7a34bc}, 924 {OP_WR_64_E1, USEM_REG_INT_TABLE + 0x368, 0x13029e},
560 {OP_ZP, USEM_REG_PRAM + 0x18000, 0x5f3b5b}, 925 {OP_WR_64_E1H, USEM_REG_INT_TABLE + 0x368, 0x1302ba},
561 {OP_ZP, USEM_REG_PRAM + 0x20000, 0x5f3b73}, 926 {OP_ZP_E1, USEM_REG_PRAM, 0x975a0000},
562 {OP_ZP, USEM_REG_PRAM + 0x28000, 0x5f3b8b}, 927 {OP_ZP_E1H, USEM_REG_PRAM, 0x985c0000},
563 {OP_ZP, USEM_REG_PRAM + 0x30000, 0x5f3ba3}, 928 {OP_WR_64_E1, USEM_REG_PRAM + 0x17f90, 0x500e02a0},
564 {OP_ZP, USEM_REG_PRAM + 0x38000, 0x5f3bbb}, 929 {OP_WR_64_E1H, USEM_REG_PRAM + 0x18200, 0x4fc002bc},
565#define USEM_COMMON_END 498 930#define USEM_COMMON_END 781
566#define USEM_PORT0_START 498 931#define USEM_PORT0_START 781
567 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1400, 0xa0}, 932 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1400, 0xa0},
568 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1900, 0xa}, 933 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9000, 0xa0},
569 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1950, 0x2e}, 934 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1900, 0xa},
570 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1d00, 0x24}, 935 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9500, 0x28},
571 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3000, 0x20}, 936 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1950, 0x2e},
572 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3100, 0x20}, 937 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9640, 0x34},
573 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3200, 0x20}, 938 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1d00, 0x4},
574 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3300, 0x20}, 939 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3080, 0x20},
575 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3400, 0x20}, 940 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1d20, 0x20},
576 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3500, 0x20}, 941 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3288, 0x96},
577 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3600, 0x20}, 942 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5440, 0x72},
578 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3700, 0x20}, 943 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5000, 0x20},
579 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3800, 0x20}, 944 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3000, 0x20},
580 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3900, 0x20}, 945 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5100, 0x20},
581 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3a00, 0x20}, 946 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3100, 0x20},
582 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3b00, 0x20}, 947 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5200, 0x20},
583 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3c00, 0x20}, 948 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3200, 0x20},
584 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3d00, 0x20}, 949 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5300, 0x20},
585 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3e00, 0x20}, 950 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3300, 0x20},
586 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3f00, 0x20}, 951 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5400, 0x20},
587 {OP_ZR, USEM_REG_FAST_MEMORY + 0x2400, 0x2}, 952 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3400, 0x20},
588 {OP_ZR, USEM_REG_FAST_MEMORY + 0x4b78, 0x52}, 953 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5500, 0x20},
589 {OP_ZR, USEM_REG_FAST_MEMORY + 0x4e08, 0xc}, 954 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3500, 0x20},
590#define USEM_PORT0_END 521 955 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5600, 0x20},
591#define USEM_PORT1_START 521 956 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3600, 0x20},
592 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1680, 0xa0}, 957 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5700, 0x20},
593 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1928, 0xa}, 958 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3700, 0x20},
594 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1a08, 0x2e}, 959 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5800, 0x20},
595 {OP_ZR, USEM_REG_FAST_MEMORY + 0x1d90, 0x24}, 960 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3800, 0x20},
596 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3080, 0x20}, 961 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5900, 0x20},
597 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3180, 0x20}, 962 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3900, 0x20},
598 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3280, 0x20}, 963 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5a00, 0x20},
599 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3380, 0x20}, 964 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3a00, 0x20},
600 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3480, 0x20}, 965 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5b00, 0x20},
601 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3580, 0x20}, 966 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3b00, 0x20},
602 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3680, 0x20}, 967 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5c00, 0x20},
603 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3780, 0x20}, 968 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3c00, 0x20},
604 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3880, 0x20}, 969 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5d00, 0x20},
605 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3980, 0x20}, 970 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3d00, 0x20},
606 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3a80, 0x20}, 971 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5e00, 0x20},
607 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3b80, 0x20}, 972 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3e00, 0x20},
608 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3c80, 0x20}, 973 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5f00, 0x20},
609 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3d80, 0x20}, 974 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3f00, 0x20},
610 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3e80, 0x20}, 975 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b78, 0x52},
611 {OP_ZR, USEM_REG_FAST_MEMORY + 0x3f80, 0x20}, 976 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x2c10, 0x2},
612 {OP_ZR, USEM_REG_FAST_MEMORY + 0x2408, 0x2}, 977 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6e08, 0xc},
613 {OP_ZR, USEM_REG_FAST_MEMORY + 0x4cc0, 0x52}, 978 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b78, 0x52},
614 {OP_ZR, USEM_REG_FAST_MEMORY + 0x4e38, 0xc}, 979 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e08, 0xc},
615#define USEM_PORT1_END 544 980#define USEM_PORT0_END 829
616#define CSEM_COMMON_START 544 981#define USEM_PORT1_START 829
982 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1680, 0xa0},
983 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9280, 0xa0},
984 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1928, 0xa},
985 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x95a0, 0x28},
986 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1a08, 0x2e},
987 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9710, 0x34},
988 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1d10, 0x4},
989 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3100, 0x20},
990 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1da0, 0x20},
991 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x34e0, 0x96},
992 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5608, 0x72},
993 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5080, 0x20},
994 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3080, 0x20},
995 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5180, 0x20},
996 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3180, 0x20},
997 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5280, 0x20},
998 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3280, 0x20},
999 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5380, 0x20},
1000 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3380, 0x20},
1001 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5480, 0x20},
1002 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3480, 0x20},
1003 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5580, 0x20},
1004 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3580, 0x20},
1005 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5680, 0x20},
1006 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3680, 0x20},
1007 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5780, 0x20},
1008 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3780, 0x20},
1009 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5880, 0x20},
1010 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3880, 0x20},
1011 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5980, 0x20},
1012 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3980, 0x20},
1013 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5a80, 0x20},
1014 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3a80, 0x20},
1015 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5b80, 0x20},
1016 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3b80, 0x20},
1017 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5c80, 0x20},
1018 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3c80, 0x20},
1019 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5d80, 0x20},
1020 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3d80, 0x20},
1021 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5e80, 0x20},
1022 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3e80, 0x20},
1023 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5f80, 0x20},
1024 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3f80, 0x20},
1025 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6cc0, 0x52},
1026 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x2c20, 0x2},
1027 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6e38, 0xc},
1028 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4cc0, 0x52},
1029 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e38, 0xc},
1030#define USEM_PORT1_END 877
1031#define USEM_FUNC0_START 877
1032 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3000, 0x4},
1033 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4010, 0x2},
1034#define USEM_FUNC0_END 879
1035#define USEM_FUNC1_START 879
1036 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3010, 0x4},
1037 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4020, 0x2},
1038#define USEM_FUNC1_END 881
1039#define USEM_FUNC2_START 881
1040 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3020, 0x4},
1041 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4030, 0x2},
1042#define USEM_FUNC2_END 883
1043#define USEM_FUNC3_START 883
1044 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3030, 0x4},
1045 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4040, 0x2},
1046#define USEM_FUNC3_END 885
1047#define USEM_FUNC4_START 885
1048 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3040, 0x4},
1049 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4050, 0x2},
1050#define USEM_FUNC4_END 887
1051#define USEM_FUNC5_START 887
1052 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3050, 0x4},
1053 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4060, 0x2},
1054#define USEM_FUNC5_END 889
1055#define USEM_FUNC6_START 889
1056 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3060, 0x4},
1057 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4070, 0x2},
1058#define USEM_FUNC6_END 891
1059#define USEM_FUNC7_START 891
1060 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3070, 0x4},
1061 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4080, 0x2},
1062#define USEM_FUNC7_END 893
1063#define CSEM_COMMON_START 893
617 {OP_RD, CSEM_REG_MSG_NUM_FIC0, 0x0}, 1064 {OP_RD, CSEM_REG_MSG_NUM_FIC0, 0x0},
618 {OP_RD, CSEM_REG_MSG_NUM_FIC1, 0x0}, 1065 {OP_RD, CSEM_REG_MSG_NUM_FIC1, 0x0},
619 {OP_RD, CSEM_REG_MSG_NUM_FOC0, 0x0}, 1066 {OP_RD, CSEM_REG_MSG_NUM_FOC0, 0x0},
@@ -658,50 +1105,104 @@ static const struct raw_op init_ops[] = {
658 {OP_WR, CSEM_REG_FAST_MEMORY + 0x18080, 0x30}, 1105 {OP_WR, CSEM_REG_FAST_MEMORY + 0x18080, 0x30},
659 {OP_WR, CSEM_REG_FAST_MEMORY + 0x180c0, 0xe}, 1106 {OP_WR, CSEM_REG_FAST_MEMORY + 0x180c0, 0xe},
660 {OP_WR, CSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4}, 1107 {OP_WR, CSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
661 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x5000, 0x42}, 1108 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x5000, 0x42},
662 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1020, 0xc8}, 1109 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x11480, 0x1},
663 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1000, 0x2}, 1110 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1020, 0xc8},
664 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x2000, 0xc0}, 1111 {OP_WR_EMUL_E1H, CSEM_REG_FAST_MEMORY + 0x11480, 0x0},
665 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3070, 0x80}, 1112 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1000, 0x2},
666 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x4280, 0x4}, 1113 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x1000, 0x42},
667 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x25c0, 0x240}, 1114 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x2000, 0xc0},
668 {OP_SW, CSEM_REG_FAST_MEMORY + 0x25c0 + 0x900, 0x83bd3}, 1115 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x7020, 0xc8},
1116 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3070, 0x80},
1117 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x7000, 0x2},
1118 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x4280, 0x4},
1119 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x11e8, 0x0},
1120 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x25c0, 0x240},
1121 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3000, 0xc0},
1122 {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x2ec8, 0x802a2},
1123 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x4070, 0x80},
1124 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x5280, 0x4},
1125 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6280, 0x240},
1126 {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x6b88, 0x2002be},
669 {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x13fffff}, 1127 {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x13fffff},
670 {OP_SW, CSEM_REG_FAST_MEMORY + 0x10c00, 0x103bdb}, 1128 {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c00, 0x1002aa},
1129 {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x10c00, 0x1002de},
671 {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x0}, 1130 {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x0},
672 {OP_SW, CSEM_REG_FAST_MEMORY + 0x10c40, 0x103beb}, 1131 {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c40, 0x1002ba},
673 {OP_ZP, CSEM_REG_INT_TABLE, 0x5f3bfb}, 1132 {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x10c40, 0x1002ee},
674 {OP_ZP, CSEM_REG_PRAM, 0x32423c13}, 1133 {OP_ZP_E1, CSEM_REG_INT_TABLE, 0x6e0000},
675 {OP_ZP, CSEM_REG_PRAM + 0x8000, 0xf2148a4}, 1134 {OP_ZP_E1H, CSEM_REG_INT_TABLE, 0x6f0000},
676 {OP_ZP, CSEM_REG_PRAM + 0x10000, 0x5f4c6d}, 1135 {OP_WR_64_E1, CSEM_REG_INT_TABLE + 0x380, 0x1002ca},
677 {OP_ZP, CSEM_REG_PRAM + 0x18000, 0x5f4c85}, 1136 {OP_WR_64_E1H, CSEM_REG_INT_TABLE + 0x380, 0x1002fe},
678 {OP_ZP, CSEM_REG_PRAM + 0x20000, 0x5f4c9d}, 1137 {OP_ZP_E1, CSEM_REG_PRAM, 0x48bc0000},
679 {OP_ZP, CSEM_REG_PRAM + 0x28000, 0x5f4cb5}, 1138 {OP_ZP_E1H, CSEM_REG_PRAM, 0x493d0000},
680 {OP_ZP, CSEM_REG_PRAM + 0x30000, 0x5f4ccd}, 1139 {OP_WR_64_E1, CSEM_REG_PRAM + 0xb210, 0x682402cc},
681 {OP_ZP, CSEM_REG_PRAM + 0x38000, 0x5f4ce5}, 1140 {OP_WR_64_E1H, CSEM_REG_PRAM + 0xb430, 0x67e00300},
682#define CSEM_COMMON_END 609 1141#define CSEM_COMMON_END 970
683#define CSEM_PORT0_START 609 1142#define CSEM_PORT0_START 970
684 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1400, 0xa0}, 1143 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1400, 0xa0},
685 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1900, 0x10}, 1144 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8000, 0xa0},
686 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1980, 0x30}, 1145 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1900, 0x10},
687 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x2300, 0x2}, 1146 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8500, 0x40},
688 {OP_SW, CSEM_REG_FAST_MEMORY + 0x2300 + 0x8, 0x24cfd}, 1147 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1980, 0x30},
689 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3040, 0x6}, 1148 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8700, 0x3c},
690 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x2410, 0x30}, 1149 {OP_WR_E1, CSEM_REG_FAST_MEMORY + 0x5118, 0x0},
691#define CSEM_PORT0_END 616 1150 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x4040, 0x6},
692#define CSEM_PORT1_START 616 1151 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x2300, 0xe},
693 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1680, 0xa0}, 1152 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6040, 0x30},
694 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1940, 0x10}, 1153 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3040, 0x6},
695 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x1a40, 0x30}, 1154 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x2410, 0x30},
696 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x2310, 0x2}, 1155#define CSEM_PORT0_END 982
697 {OP_SW, CSEM_REG_FAST_MEMORY + 0x2310 + 0x8, 0x24cff}, 1156#define CSEM_PORT1_START 982
698 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x3058, 0x6}, 1157 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1680, 0xa0},
699 {OP_ZR, CSEM_REG_FAST_MEMORY + 0x24d0, 0x30}, 1158 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8280, 0xa0},
700#define CSEM_PORT1_END 623 1159 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1940, 0x10},
701#define XPB_COMMON_START 623 1160 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8600, 0x40},
1161 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1a40, 0x30},
1162 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x87f0, 0x3c},
1163 {OP_WR_E1, CSEM_REG_FAST_MEMORY + 0x511c, 0x0},
1164 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x4058, 0x6},
1165 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x2338, 0xe},
1166 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6100, 0x30},
1167 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3058, 0x6},
1168 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x24d0, 0x30},
1169#define CSEM_PORT1_END 994
1170#define CSEM_FUNC0_START 994
1171 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1148, 0x0},
1172 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3300, 0x2},
1173#define CSEM_FUNC0_END 996
1174#define CSEM_FUNC1_START 996
1175 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x114c, 0x0},
1176 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3308, 0x2},
1177#define CSEM_FUNC1_END 998
1178#define CSEM_FUNC2_START 998
1179 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1150, 0x0},
1180 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3310, 0x2},
1181#define CSEM_FUNC2_END 1000
1182#define CSEM_FUNC3_START 1000
1183 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1154, 0x0},
1184 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3318, 0x2},
1185#define CSEM_FUNC3_END 1002
1186#define CSEM_FUNC4_START 1002
1187 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1158, 0x0},
1188 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3320, 0x2},
1189#define CSEM_FUNC4_END 1004
1190#define CSEM_FUNC5_START 1004
1191 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x115c, 0x0},
1192 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3328, 0x2},
1193#define CSEM_FUNC5_END 1006
1194#define CSEM_FUNC6_START 1006
1195 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1160, 0x0},
1196 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3330, 0x2},
1197#define CSEM_FUNC6_END 1008
1198#define CSEM_FUNC7_START 1008
1199 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1164, 0x0},
1200 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3338, 0x2},
1201#define CSEM_FUNC7_END 1010
1202#define XPB_COMMON_START 1010
702 {OP_WR, GRCBASE_XPB + PB_REG_CONTROL, 0x20}, 1203 {OP_WR, GRCBASE_XPB + PB_REG_CONTROL, 0x20},
703#define XPB_COMMON_END 624 1204#define XPB_COMMON_END 1011
704#define DQ_COMMON_START 624 1205#define DQ_COMMON_START 1011
705 {OP_WR, DORQ_REG_MODE_ACT, 0x2}, 1206 {OP_WR, DORQ_REG_MODE_ACT, 0x2},
706 {OP_WR, DORQ_REG_NORM_CID_OFST, 0x3}, 1207 {OP_WR, DORQ_REG_NORM_CID_OFST, 0x3},
707 {OP_WR, DORQ_REG_OUTST_REQ, 0x4}, 1208 {OP_WR, DORQ_REG_OUTST_REQ, 0x4},
@@ -720,8 +1221,8 @@ static const struct raw_op init_ops[] = {
720 {OP_WR, DORQ_REG_DQ_FIFO_AFULL_TH, 0x76c}, 1221 {OP_WR, DORQ_REG_DQ_FIFO_AFULL_TH, 0x76c},
721 {OP_WR, DORQ_REG_REGN, 0x7c1004}, 1222 {OP_WR, DORQ_REG_REGN, 0x7c1004},
722 {OP_WR, DORQ_REG_IF_EN, 0xf}, 1223 {OP_WR, DORQ_REG_IF_EN, 0xf},
723#define DQ_COMMON_END 642 1224#define DQ_COMMON_END 1029
724#define TIMERS_COMMON_START 642 1225#define TIMERS_COMMON_START 1029
725 {OP_ZR, TM_REG_CLIN_PRIOR0_CLIENT, 0x2}, 1226 {OP_ZR, TM_REG_CLIN_PRIOR0_CLIENT, 0x2},
726 {OP_WR, TM_REG_LIN_SETCLR_FIFO_ALFULL_THR, 0x1c}, 1227 {OP_WR, TM_REG_LIN_SETCLR_FIFO_ALFULL_THR, 0x1c},
727 {OP_WR, TM_REG_CFC_AC_CRDCNT_VAL, 0x1}, 1228 {OP_WR, TM_REG_CFC_AC_CRDCNT_VAL, 0x1},
@@ -730,8 +1231,11 @@ static const struct raw_op init_ops[] = {
730 {OP_WR, TM_REG_CLOUT_CRDCNT1_VAL, 0x1}, 1231 {OP_WR, TM_REG_CLOUT_CRDCNT1_VAL, 0x1},
731 {OP_WR, TM_REG_CLOUT_CRDCNT2_VAL, 0x1}, 1232 {OP_WR, TM_REG_CLOUT_CRDCNT2_VAL, 0x1},
732 {OP_WR, TM_REG_EXP_CRDCNT_VAL, 0x1}, 1233 {OP_WR, TM_REG_EXP_CRDCNT_VAL, 0x1},
733 {OP_WR, TM_REG_PCIARB_CRDCNT_VAL, 0x2}, 1234 {OP_WR_E1, TM_REG_PCIARB_CRDCNT_VAL, 0x1},
734 {OP_WR, TM_REG_TIMER_TICK_SIZE, 0x3d090}, 1235 {OP_WR_E1H, TM_REG_PCIARB_CRDCNT_VAL, 0x2},
1236 {OP_WR_ASIC, TM_REG_TIMER_TICK_SIZE, 0x3d090},
1237 {OP_WR_EMUL, TM_REG_TIMER_TICK_SIZE, 0x9c},
1238 {OP_WR_FPGA, TM_REG_TIMER_TICK_SIZE, 0x9c4},
735 {OP_WR, TM_REG_CL0_CONT_REGION, 0x8}, 1239 {OP_WR, TM_REG_CL0_CONT_REGION, 0x8},
736 {OP_WR, TM_REG_CL1_CONT_REGION, 0xc}, 1240 {OP_WR, TM_REG_CL1_CONT_REGION, 0xc},
737 {OP_WR, TM_REG_CL2_CONT_REGION, 0x10}, 1241 {OP_WR, TM_REG_CL2_CONT_REGION, 0x10},
@@ -741,24 +1245,37 @@ static const struct raw_op init_ops[] = {
741 {OP_WR, TM_REG_EN_CL0_INPUT, 0x1}, 1245 {OP_WR, TM_REG_EN_CL0_INPUT, 0x1},
742 {OP_WR, TM_REG_EN_CL1_INPUT, 0x1}, 1246 {OP_WR, TM_REG_EN_CL1_INPUT, 0x1},
743 {OP_WR, TM_REG_EN_CL2_INPUT, 0x1}, 1247 {OP_WR, TM_REG_EN_CL2_INPUT, 0x1},
744#define TIMERS_COMMON_END 661 1248#define TIMERS_COMMON_END 1051
745#define TIMERS_PORT0_START 661 1249#define TIMERS_PORT0_START 1051
746 {OP_ZR, TM_REG_LIN0_PHY_ADDR, 0x2}, 1250 {OP_ZR, TM_REG_LIN0_PHY_ADDR, 0x2},
747#define TIMERS_PORT0_END 662 1251#define TIMERS_PORT0_END 1052
748#define TIMERS_PORT1_START 662 1252#define TIMERS_PORT1_START 1052
749 {OP_ZR, TM_REG_LIN1_PHY_ADDR, 0x2}, 1253 {OP_ZR, TM_REG_LIN1_PHY_ADDR, 0x2},
750#define TIMERS_PORT1_END 663 1254#define TIMERS_PORT1_END 1053
751#define XSDM_COMMON_START 663 1255#define XSDM_COMMON_START 1053
752 {OP_WR, XSDM_REG_CFC_RSP_START_ADDR, 0xa14}, 1256 {OP_WR_E1, XSDM_REG_CFC_RSP_START_ADDR, 0x614},
753 {OP_WR, XSDM_REG_CMP_COUNTER_START_ADDR, 0xa00}, 1257 {OP_WR_E1H, XSDM_REG_CFC_RSP_START_ADDR, 0x424},
754 {OP_WR, XSDM_REG_Q_COUNTER_START_ADDR, 0xa04}, 1258 {OP_WR_E1, XSDM_REG_CMP_COUNTER_START_ADDR, 0x600},
1259 {OP_WR_E1H, XSDM_REG_CMP_COUNTER_START_ADDR, 0x410},
1260 {OP_WR_E1, XSDM_REG_Q_COUNTER_START_ADDR, 0x604},
1261 {OP_WR_E1H, XSDM_REG_Q_COUNTER_START_ADDR, 0x414},
755 {OP_WR, XSDM_REG_CMP_COUNTER_MAX0, 0xffff}, 1262 {OP_WR, XSDM_REG_CMP_COUNTER_MAX0, 0xffff},
756 {OP_WR, XSDM_REG_CMP_COUNTER_MAX1, 0xffff}, 1263 {OP_WR, XSDM_REG_CMP_COUNTER_MAX1, 0xffff},
757 {OP_WR, XSDM_REG_CMP_COUNTER_MAX2, 0xffff}, 1264 {OP_WR, XSDM_REG_CMP_COUNTER_MAX2, 0xffff},
758 {OP_WR, XSDM_REG_CMP_COUNTER_MAX3, 0xffff}, 1265 {OP_WR, XSDM_REG_CMP_COUNTER_MAX3, 0xffff},
759 {OP_WR, XSDM_REG_AGG_INT_EVENT_0, 0x20}, 1266 {OP_WR, XSDM_REG_AGG_INT_EVENT_0, 0x20},
760 {OP_WR, XSDM_REG_AGG_INT_EVENT_1, 0x20}, 1267 {OP_WR, XSDM_REG_AGG_INT_EVENT_1, 0x20},
761 {OP_ZR, XSDM_REG_AGG_INT_EVENT_2, 0x5e}, 1268 {OP_WR, XSDM_REG_AGG_INT_EVENT_2, 0x34},
1269 {OP_WR, XSDM_REG_AGG_INT_EVENT_3, 0x35},
1270 {OP_WR, XSDM_REG_AGG_INT_EVENT_4, 0x23},
1271 {OP_WR, XSDM_REG_AGG_INT_EVENT_5, 0x24},
1272 {OP_WR, XSDM_REG_AGG_INT_EVENT_6, 0x25},
1273 {OP_WR, XSDM_REG_AGG_INT_EVENT_7, 0x26},
1274 {OP_WR, XSDM_REG_AGG_INT_EVENT_8, 0x27},
1275 {OP_WR, XSDM_REG_AGG_INT_EVENT_9, 0x29},
1276 {OP_WR, XSDM_REG_AGG_INT_EVENT_10, 0x2a},
1277 {OP_WR, XSDM_REG_AGG_INT_EVENT_11, 0x2b},
1278 {OP_ZR, XSDM_REG_AGG_INT_EVENT_12, 0x54},
762 {OP_WR, XSDM_REG_AGG_INT_MODE_0, 0x1}, 1279 {OP_WR, XSDM_REG_AGG_INT_MODE_0, 0x1},
763 {OP_ZR, XSDM_REG_AGG_INT_MODE_1, 0x1f}, 1280 {OP_ZR, XSDM_REG_AGG_INT_MODE_1, 0x1f},
764 {OP_WR, XSDM_REG_ENABLE_IN1, 0x7ffffff}, 1281 {OP_WR, XSDM_REG_ENABLE_IN1, 0x7ffffff},
@@ -779,9 +1296,12 @@ static const struct raw_op init_ops[] = {
779 {OP_RD, XSDM_REG_NUM_OF_PKT_END_MSG, 0x0}, 1296 {OP_RD, XSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
780 {OP_RD, XSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0}, 1297 {OP_RD, XSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
781 {OP_RD, XSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0}, 1298 {OP_RD, XSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
782 {OP_WR, XSDM_REG_TIMER_TICK, 0x3e8}, 1299 {OP_WR_E1, XSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
783#define XSDM_COMMON_END 694 1300 {OP_WR_ASIC, XSDM_REG_TIMER_TICK, 0x3e8},
784#define QM_COMMON_START 694 1301 {OP_WR_EMUL, XSDM_REG_TIMER_TICK, 0x1},
1302 {OP_WR_FPGA, XSDM_REG_TIMER_TICK, 0xa},
1303#define XSDM_COMMON_END 1100
1304#define QM_COMMON_START 1100
785 {OP_WR, QM_REG_ACTCTRINITVAL_0, 0x6}, 1305 {OP_WR, QM_REG_ACTCTRINITVAL_0, 0x6},
786 {OP_WR, QM_REG_ACTCTRINITVAL_1, 0x5}, 1306 {OP_WR, QM_REG_ACTCTRINITVAL_1, 0x5},
787 {OP_WR, QM_REG_ACTCTRINITVAL_2, 0xa}, 1307 {OP_WR, QM_REG_ACTCTRINITVAL_2, 0xa},
@@ -820,13 +1340,27 @@ static const struct raw_op init_ops[] = {
820 {OP_WR, QM_REG_WRRWEIGHTS_3, 0x1010120}, 1340 {OP_WR, QM_REG_WRRWEIGHTS_3, 0x1010120},
821 {OP_ZR, QM_REG_QVOQIDX_17, 0x4}, 1341 {OP_ZR, QM_REG_QVOQIDX_17, 0x4},
822 {OP_WR, QM_REG_WRRWEIGHTS_4, 0x1010101}, 1342 {OP_WR, QM_REG_WRRWEIGHTS_4, 0x1010101},
823 {OP_ZR, QM_REG_QVOQIDX_21, 0x4}, 1343 {OP_ZR_E1, QM_REG_QVOQIDX_21, 0x4},
824 {OP_WR, QM_REG_WRRWEIGHTS_5, 0x1010101}, 1344 {OP_WR_E1H, QM_REG_QVOQIDX_21, 0x0},
825 {OP_ZR, QM_REG_QVOQIDX_25, 0x4}, 1345 {OP_WR_E1, QM_REG_WRRWEIGHTS_5, 0x1010101},
826 {OP_WR, QM_REG_WRRWEIGHTS_6, 0x1010101}, 1346 {OP_WR_E1H, QM_REG_QVOQIDX_22, 0x4},
827 {OP_ZR, QM_REG_QVOQIDX_29, 0x3}, 1347 {OP_ZR_E1, QM_REG_QVOQIDX_25, 0x4},
1348 {OP_WR_E1H, QM_REG_QVOQIDX_23, 0x4},
1349 {OP_WR_E1, QM_REG_WRRWEIGHTS_6, 0x1010101},
1350 {OP_WR_E1H, QM_REG_QVOQIDX_24, 0x2},
1351 {OP_ZR_E1, QM_REG_QVOQIDX_29, 0x3},
1352 {OP_WR_E1H, QM_REG_WRRWEIGHTS_5, 0x8012004},
1353 {OP_WR_E1H, QM_REG_QVOQIDX_25, 0x5},
1354 {OP_WR_E1H, QM_REG_QVOQIDX_26, 0x5},
1355 {OP_WR_E1H, QM_REG_QVOQIDX_27, 0x5},
1356 {OP_WR_E1H, QM_REG_QVOQIDX_28, 0x5},
1357 {OP_WR_E1H, QM_REG_WRRWEIGHTS_6, 0x20081001},
1358 {OP_WR_E1H, QM_REG_QVOQIDX_29, 0x8},
1359 {OP_WR_E1H, QM_REG_QVOQIDX_30, 0x6},
1360 {OP_WR_E1H, QM_REG_QVOQIDX_31, 0x7},
828 {OP_WR, QM_REG_QVOQIDX_32, 0x1}, 1361 {OP_WR, QM_REG_QVOQIDX_32, 0x1},
829 {OP_WR, QM_REG_WRRWEIGHTS_7, 0x1010101}, 1362 {OP_WR_E1, QM_REG_WRRWEIGHTS_7, 0x1010101},
1363 {OP_WR_E1H, QM_REG_WRRWEIGHTS_7, 0x1010120},
830 {OP_WR, QM_REG_QVOQIDX_33, 0x1}, 1364 {OP_WR, QM_REG_QVOQIDX_33, 0x1},
831 {OP_WR, QM_REG_QVOQIDX_34, 0x1}, 1365 {OP_WR, QM_REG_QVOQIDX_34, 0x1},
832 {OP_WR, QM_REG_QVOQIDX_35, 0x1}, 1366 {OP_WR, QM_REG_QVOQIDX_35, 0x1},
@@ -853,36 +1387,169 @@ static const struct raw_op init_ops[] = {
853 {OP_WR, QM_REG_QVOQIDX_52, 0x1}, 1387 {OP_WR, QM_REG_QVOQIDX_52, 0x1},
854 {OP_WR, QM_REG_WRRWEIGHTS_12, 0x1010101}, 1388 {OP_WR, QM_REG_WRRWEIGHTS_12, 0x1010101},
855 {OP_WR, QM_REG_QVOQIDX_53, 0x1}, 1389 {OP_WR, QM_REG_QVOQIDX_53, 0x1},
856 {OP_WR, QM_REG_QVOQIDX_54, 0x1}, 1390 {OP_WR_E1, QM_REG_QVOQIDX_54, 0x1},
857 {OP_WR, QM_REG_QVOQIDX_55, 0x1}, 1391 {OP_WR_E1H, QM_REG_QVOQIDX_54, 0x4},
858 {OP_WR, QM_REG_QVOQIDX_56, 0x1}, 1392 {OP_WR_E1, QM_REG_QVOQIDX_55, 0x1},
859 {OP_WR, QM_REG_WRRWEIGHTS_13, 0x1010101}, 1393 {OP_WR_E1H, QM_REG_QVOQIDX_55, 0x4},
860 {OP_WR, QM_REG_QVOQIDX_57, 0x1}, 1394 {OP_WR_E1, QM_REG_QVOQIDX_56, 0x1},
861 {OP_WR, QM_REG_QVOQIDX_58, 0x1}, 1395 {OP_WR_E1H, QM_REG_QVOQIDX_56, 0x2},
862 {OP_WR, QM_REG_QVOQIDX_59, 0x1}, 1396 {OP_WR_E1, QM_REG_WRRWEIGHTS_13, 0x1010101},
863 {OP_WR, QM_REG_QVOQIDX_60, 0x1}, 1397 {OP_WR_E1H, QM_REG_WRRWEIGHTS_13, 0x8012004},
864 {OP_WR, QM_REG_WRRWEIGHTS_14, 0x1010101}, 1398 {OP_WR_E1, QM_REG_QVOQIDX_57, 0x1},
865 {OP_WR, QM_REG_QVOQIDX_61, 0x1}, 1399 {OP_WR_E1H, QM_REG_QVOQIDX_57, 0x5},
866 {OP_WR, QM_REG_QVOQIDX_62, 0x1}, 1400 {OP_WR_E1, QM_REG_QVOQIDX_58, 0x1},
867 {OP_WR, QM_REG_QVOQIDX_63, 0x1}, 1401 {OP_WR_E1H, QM_REG_QVOQIDX_58, 0x5},
868 {OP_WR, QM_REG_WRRWEIGHTS_15, 0x1010101}, 1402 {OP_WR_E1, QM_REG_QVOQIDX_59, 0x1},
869 {OP_WR, QM_REG_VOQQMASK_0_LSB, 0xffff003f}, 1403 {OP_WR_E1H, QM_REG_QVOQIDX_59, 0x5},
870 {OP_ZR, QM_REG_VOQQMASK_0_MSB, 0x2}, 1404 {OP_WR_E1, QM_REG_QVOQIDX_60, 0x1},
871 {OP_WR, QM_REG_VOQQMASK_1_MSB, 0xffff003f}, 1405 {OP_WR_E1H, QM_REG_QVOQIDX_60, 0x5},
872 {OP_WR, QM_REG_VOQQMASK_2_LSB, 0x100}, 1406 {OP_WR_E1, QM_REG_WRRWEIGHTS_14, 0x1010101},
873 {OP_WR, QM_REG_VOQQMASK_2_MSB, 0x100}, 1407 {OP_WR_E1H, QM_REG_WRRWEIGHTS_14, 0x20081001},
1408 {OP_WR_E1, QM_REG_QVOQIDX_61, 0x1},
1409 {OP_WR_E1H, QM_REG_QVOQIDX_61, 0x8},
1410 {OP_WR_E1, QM_REG_QVOQIDX_62, 0x1},
1411 {OP_WR_E1H, QM_REG_QVOQIDX_62, 0x6},
1412 {OP_WR_E1, QM_REG_QVOQIDX_63, 0x1},
1413 {OP_WR_E1H, QM_REG_QVOQIDX_63, 0x7},
1414 {OP_WR_E1, QM_REG_WRRWEIGHTS_15, 0x1010101},
1415 {OP_WR_E1H, QM_REG_QVOQIDX_64, 0x0},
1416 {OP_WR_E1, QM_REG_VOQQMASK_0_LSB, 0xffff003f},
1417 {OP_WR_E1H, QM_REG_WRRWEIGHTS_15, 0x1010120},
1418 {OP_ZR_E1, QM_REG_VOQQMASK_0_MSB, 0x2},
1419 {OP_ZR_E1H, QM_REG_QVOQIDX_65, 0x4},
1420 {OP_WR_E1, QM_REG_VOQQMASK_1_MSB, 0xffff003f},
1421 {OP_WR_E1H, QM_REG_WRRWEIGHTS_16, 0x1010101},
1422 {OP_WR_E1, QM_REG_VOQQMASK_2_LSB, 0x100},
1423 {OP_WR_E1H, QM_REG_QVOQIDX_69, 0x0},
1424 {OP_WR_E1, QM_REG_VOQQMASK_2_MSB, 0x100},
1425 {OP_WR_E1H, QM_REG_QVOQIDX_70, 0x4},
1426 {OP_WR_E1H, QM_REG_QVOQIDX_71, 0x4},
1427 {OP_WR_E1H, QM_REG_QVOQIDX_72, 0x2},
1428 {OP_WR_E1H, QM_REG_WRRWEIGHTS_17, 0x8012004},
1429 {OP_WR_E1H, QM_REG_QVOQIDX_73, 0x5},
1430 {OP_WR_E1H, QM_REG_QVOQIDX_74, 0x5},
1431 {OP_WR_E1H, QM_REG_QVOQIDX_75, 0x5},
1432 {OP_WR_E1H, QM_REG_QVOQIDX_76, 0x5},
1433 {OP_WR_E1H, QM_REG_WRRWEIGHTS_18, 0x20081001},
1434 {OP_WR_E1H, QM_REG_QVOQIDX_77, 0x8},
1435 {OP_WR_E1H, QM_REG_QVOQIDX_78, 0x6},
1436 {OP_WR_E1H, QM_REG_QVOQIDX_79, 0x7},
1437 {OP_WR_E1H, QM_REG_QVOQIDX_80, 0x0},
1438 {OP_WR_E1H, QM_REG_WRRWEIGHTS_19, 0x1010120},
1439 {OP_ZR_E1H, QM_REG_QVOQIDX_81, 0x4},
1440 {OP_WR_E1H, QM_REG_WRRWEIGHTS_20, 0x1010101},
1441 {OP_WR_E1H, QM_REG_QVOQIDX_85, 0x0},
1442 {OP_WR_E1H, QM_REG_QVOQIDX_86, 0x4},
1443 {OP_WR_E1H, QM_REG_QVOQIDX_87, 0x4},
1444 {OP_WR_E1H, QM_REG_QVOQIDX_88, 0x2},
1445 {OP_WR_E1H, QM_REG_WRRWEIGHTS_21, 0x8012004},
1446 {OP_WR_E1H, QM_REG_QVOQIDX_89, 0x5},
1447 {OP_WR_E1H, QM_REG_QVOQIDX_90, 0x5},
1448 {OP_WR_E1H, QM_REG_QVOQIDX_91, 0x5},
1449 {OP_WR_E1H, QM_REG_QVOQIDX_92, 0x5},
1450 {OP_WR_E1H, QM_REG_WRRWEIGHTS_22, 0x20081001},
1451 {OP_WR_E1H, QM_REG_QVOQIDX_93, 0x8},
1452 {OP_WR_E1H, QM_REG_QVOQIDX_94, 0x6},
1453 {OP_WR_E1H, QM_REG_QVOQIDX_95, 0x7},
1454 {OP_WR_E1H, QM_REG_QVOQIDX_96, 0x1},
1455 {OP_WR_E1H, QM_REG_WRRWEIGHTS_23, 0x1010120},
1456 {OP_WR_E1H, QM_REG_QVOQIDX_97, 0x1},
1457 {OP_WR_E1H, QM_REG_QVOQIDX_98, 0x1},
1458 {OP_WR_E1H, QM_REG_QVOQIDX_99, 0x1},
1459 {OP_WR_E1H, QM_REG_QVOQIDX_100, 0x1},
1460 {OP_WR_E1H, QM_REG_WRRWEIGHTS_24, 0x1010101},
1461 {OP_WR_E1H, QM_REG_QVOQIDX_101, 0x1},
1462 {OP_WR_E1H, QM_REG_QVOQIDX_102, 0x4},
1463 {OP_WR_E1H, QM_REG_QVOQIDX_103, 0x4},
1464 {OP_WR_E1H, QM_REG_QVOQIDX_104, 0x2},
1465 {OP_WR_E1H, QM_REG_WRRWEIGHTS_25, 0x8012004},
1466 {OP_WR_E1H, QM_REG_QVOQIDX_105, 0x5},
1467 {OP_WR_E1H, QM_REG_QVOQIDX_106, 0x5},
1468 {OP_WR_E1H, QM_REG_QVOQIDX_107, 0x5},
1469 {OP_WR_E1H, QM_REG_QVOQIDX_108, 0x5},
1470 {OP_WR_E1H, QM_REG_WRRWEIGHTS_26, 0x20081001},
1471 {OP_WR_E1H, QM_REG_QVOQIDX_109, 0x8},
1472 {OP_WR_E1H, QM_REG_QVOQIDX_110, 0x6},
1473 {OP_WR_E1H, QM_REG_QVOQIDX_111, 0x7},
1474 {OP_WR_E1H, QM_REG_QVOQIDX_112, 0x1},
1475 {OP_WR_E1H, QM_REG_WRRWEIGHTS_27, 0x1010120},
1476 {OP_WR_E1H, QM_REG_QVOQIDX_113, 0x1},
1477 {OP_WR_E1H, QM_REG_QVOQIDX_114, 0x1},
1478 {OP_WR_E1H, QM_REG_QVOQIDX_115, 0x1},
1479 {OP_WR_E1H, QM_REG_QVOQIDX_116, 0x1},
1480 {OP_WR_E1H, QM_REG_WRRWEIGHTS_28, 0x1010101},
1481 {OP_WR_E1H, QM_REG_QVOQIDX_117, 0x1},
1482 {OP_WR_E1H, QM_REG_QVOQIDX_118, 0x4},
1483 {OP_WR_E1H, QM_REG_QVOQIDX_119, 0x4},
1484 {OP_WR_E1H, QM_REG_QVOQIDX_120, 0x2},
1485 {OP_WR_E1H, QM_REG_WRRWEIGHTS_29, 0x8012004},
1486 {OP_WR_E1H, QM_REG_QVOQIDX_121, 0x5},
1487 {OP_WR_E1H, QM_REG_QVOQIDX_122, 0x5},
1488 {OP_WR_E1H, QM_REG_QVOQIDX_123, 0x5},
1489 {OP_WR_E1H, QM_REG_QVOQIDX_124, 0x5},
1490 {OP_WR_E1H, QM_REG_WRRWEIGHTS_30, 0x20081001},
1491 {OP_WR_E1H, QM_REG_QVOQIDX_125, 0x8},
1492 {OP_WR_E1H, QM_REG_QVOQIDX_126, 0x6},
1493 {OP_WR_E1H, QM_REG_QVOQIDX_127, 0x7},
1494 {OP_WR_E1H, QM_REG_WRRWEIGHTS_31, 0x1010120},
1495 {OP_WR_E1H, QM_REG_VOQQMASK_0_LSB, 0x3f003f},
1496 {OP_WR_E1H, QM_REG_VOQQMASK_0_MSB, 0x0},
1497 {OP_WR_E1H, QM_REG_VOQQMASK_0_LSB_EXT_A, 0x3f003f},
1498 {OP_WR_E1H, QM_REG_VOQQMASK_0_MSB_EXT_A, 0x0},
1499 {OP_WR_E1H, QM_REG_VOQQMASK_1_LSB, 0x0},
1500 {OP_WR_E1H, QM_REG_VOQQMASK_1_MSB, 0x3f003f},
1501 {OP_WR_E1H, QM_REG_VOQQMASK_1_LSB_EXT_A, 0x0},
1502 {OP_WR_E1H, QM_REG_VOQQMASK_1_MSB_EXT_A, 0x3f003f},
1503 {OP_WR_E1H, QM_REG_VOQQMASK_2_LSB, 0x1000100},
1504 {OP_WR_E1H, QM_REG_VOQQMASK_2_MSB, 0x1000100},
1505 {OP_WR_E1H, QM_REG_VOQQMASK_2_LSB_EXT_A, 0x1000100},
1506 {OP_WR_E1H, QM_REG_VOQQMASK_2_MSB_EXT_A, 0x1000100},
874 {OP_ZR, QM_REG_VOQQMASK_3_LSB, 0x2}, 1507 {OP_ZR, QM_REG_VOQQMASK_3_LSB, 0x2},
875 {OP_WR, QM_REG_VOQQMASK_4_LSB, 0xc0}, 1508 {OP_WR_E1, QM_REG_VOQQMASK_4_LSB, 0xc0},
876 {OP_WR, QM_REG_VOQQMASK_4_MSB, 0xc0}, 1509 {OP_WR_E1H, QM_REG_VOQQMASK_3_LSB_EXT_A, 0x0},
877 {OP_WR, QM_REG_VOQQMASK_5_LSB, 0x1e00}, 1510 {OP_WR_E1, QM_REG_VOQQMASK_4_MSB, 0xc0},
878 {OP_WR, QM_REG_VOQQMASK_5_MSB, 0x1e00}, 1511 {OP_WR_E1H, QM_REG_VOQQMASK_3_MSB_EXT_A, 0x0},
879 {OP_WR, QM_REG_VOQQMASK_6_LSB, 0x4000}, 1512 {OP_WR_E1, QM_REG_VOQQMASK_5_LSB, 0x1e00},
880 {OP_WR, QM_REG_VOQQMASK_6_MSB, 0x4000}, 1513 {OP_WR_E1H, QM_REG_VOQQMASK_4_LSB, 0xc000c0},
881 {OP_WR, QM_REG_VOQQMASK_7_LSB, 0x8000}, 1514 {OP_WR_E1, QM_REG_VOQQMASK_5_MSB, 0x1e00},
882 {OP_WR, QM_REG_VOQQMASK_7_MSB, 0x8000}, 1515 {OP_WR_E1H, QM_REG_VOQQMASK_4_MSB, 0xc000c0},
883 {OP_WR, QM_REG_VOQQMASK_8_LSB, 0x2000}, 1516 {OP_WR_E1, QM_REG_VOQQMASK_6_LSB, 0x4000},
884 {OP_WR, QM_REG_VOQQMASK_8_MSB, 0x2000}, 1517 {OP_WR_E1H, QM_REG_VOQQMASK_4_LSB_EXT_A, 0xc000c0},
885 {OP_ZR, QM_REG_VOQQMASK_9_LSB, 0x7}, 1518 {OP_WR_E1, QM_REG_VOQQMASK_6_MSB, 0x4000},
1519 {OP_WR_E1H, QM_REG_VOQQMASK_4_MSB_EXT_A, 0xc000c0},
1520 {OP_WR_E1, QM_REG_VOQQMASK_7_LSB, 0x8000},
1521 {OP_WR_E1H, QM_REG_VOQQMASK_5_LSB, 0x1e001e00},
1522 {OP_WR_E1, QM_REG_VOQQMASK_7_MSB, 0x8000},
1523 {OP_WR_E1H, QM_REG_VOQQMASK_5_MSB, 0x1e001e00},
1524 {OP_WR_E1, QM_REG_VOQQMASK_8_LSB, 0x2000},
1525 {OP_WR_E1H, QM_REG_VOQQMASK_5_LSB_EXT_A, 0x1e001e00},
1526 {OP_WR_E1, QM_REG_VOQQMASK_8_MSB, 0x2000},
1527 {OP_WR_E1H, QM_REG_VOQQMASK_5_MSB_EXT_A, 0x1e001e00},
1528 {OP_ZR_E1, QM_REG_VOQQMASK_9_LSB, 0x7},
1529 {OP_WR_E1H, QM_REG_VOQQMASK_6_LSB, 0x40004000},
1530 {OP_WR_E1H, QM_REG_VOQQMASK_6_MSB, 0x40004000},
1531 {OP_WR_E1H, QM_REG_VOQQMASK_6_LSB_EXT_A, 0x40004000},
1532 {OP_WR_E1H, QM_REG_VOQQMASK_6_MSB_EXT_A, 0x40004000},
1533 {OP_WR_E1H, QM_REG_VOQQMASK_7_LSB, 0x80008000},
1534 {OP_WR_E1H, QM_REG_VOQQMASK_7_MSB, 0x80008000},
1535 {OP_WR_E1H, QM_REG_VOQQMASK_7_LSB_EXT_A, 0x80008000},
1536 {OP_WR_E1H, QM_REG_VOQQMASK_7_MSB_EXT_A, 0x80008000},
1537 {OP_WR_E1H, QM_REG_VOQQMASK_8_LSB, 0x20002000},
1538 {OP_WR_E1H, QM_REG_VOQQMASK_8_MSB, 0x20002000},
1539 {OP_WR_E1H, QM_REG_VOQQMASK_8_LSB_EXT_A, 0x20002000},
1540 {OP_WR_E1H, QM_REG_VOQQMASK_8_MSB_EXT_A, 0x20002000},
1541 {OP_ZR_E1H, QM_REG_VOQQMASK_9_LSB, 0x2},
1542 {OP_WR_E1H, QM_REG_VOQQMASK_9_LSB_EXT_A, 0x0},
1543 {OP_WR_E1H, QM_REG_VOQQMASK_9_MSB_EXT_A, 0x0},
1544 {OP_WR_E1H, QM_REG_VOQQMASK_10_LSB, 0x0},
1545 {OP_WR_E1H, QM_REG_VOQQMASK_10_MSB, 0x0},
1546 {OP_WR_E1H, QM_REG_VOQQMASK_10_LSB_EXT_A, 0x0},
1547 {OP_WR_E1H, QM_REG_VOQQMASK_10_MSB_EXT_A, 0x0},
1548 {OP_WR_E1H, QM_REG_VOQQMASK_11_LSB, 0x0},
1549 {OP_WR_E1H, QM_REG_VOQQMASK_11_MSB, 0x0},
1550 {OP_WR_E1H, QM_REG_VOQQMASK_11_LSB_EXT_A, 0x0},
1551 {OP_WR_E1H, QM_REG_VOQQMASK_11_MSB_EXT_A, 0x0},
1552 {OP_WR_E1H, QM_REG_VOQPORT_0, 0x0},
886 {OP_WR, QM_REG_VOQPORT_1, 0x1}, 1553 {OP_WR, QM_REG_VOQPORT_1, 0x1},
887 {OP_ZR, QM_REG_VOQPORT_2, 0xa}, 1554 {OP_ZR, QM_REG_VOQPORT_2, 0xa},
888 {OP_WR, QM_REG_CMINTVOQMASK_0, 0xc08}, 1555 {OP_WR, QM_REG_CMINTVOQMASK_0, 0xc08},
@@ -893,8 +1560,12 @@ static const struct raw_op init_ops[] = {
893 {OP_WR, QM_REG_CMINTVOQMASK_5, 0x80}, 1560 {OP_WR, QM_REG_CMINTVOQMASK_5, 0x80},
894 {OP_WR, QM_REG_CMINTVOQMASK_6, 0x200}, 1561 {OP_WR, QM_REG_CMINTVOQMASK_6, 0x200},
895 {OP_WR, QM_REG_CMINTVOQMASK_7, 0x0}, 1562 {OP_WR, QM_REG_CMINTVOQMASK_7, 0x0},
896 {OP_WR, QM_REG_HWAEMPTYMASK_LSB, 0xffff01ff}, 1563 {OP_WR_E1, QM_REG_HWAEMPTYMASK_LSB, 0xffff01ff},
897 {OP_WR, QM_REG_HWAEMPTYMASK_MSB, 0xffff01ff}, 1564 {OP_WR_E1H, QM_REG_HWAEMPTYMASK_LSB, 0x1ff01ff},
1565 {OP_WR_E1, QM_REG_HWAEMPTYMASK_MSB, 0xffff01ff},
1566 {OP_WR_E1H, QM_REG_HWAEMPTYMASK_MSB, 0x1ff01ff},
1567 {OP_WR_E1H, QM_REG_HWAEMPTYMASK_LSB_EXT_A, 0x1ff01ff},
1568 {OP_WR_E1H, QM_REG_HWAEMPTYMASK_MSB_EXT_A, 0x1ff01ff},
898 {OP_WR, QM_REG_ENBYPVOQMASK, 0x13}, 1569 {OP_WR, QM_REG_ENBYPVOQMASK, 0x13},
899 {OP_WR, QM_REG_VOQCREDITAFULLTHR, 0x13f}, 1570 {OP_WR, QM_REG_VOQCREDITAFULLTHR, 0x13f},
900 {OP_WR, QM_REG_VOQINITCREDIT_0, 0x140}, 1571 {OP_WR, QM_REG_VOQINITCREDIT_0, 0x140},
@@ -910,15 +1581,29 @@ static const struct raw_op init_ops[] = {
910 {OP_WR, QM_REG_BYTECRDINITVAL, 0x8000}, 1581 {OP_WR, QM_REG_BYTECRDINITVAL, 0x8000},
911 {OP_WR, QM_REG_BYTECRDCOST, 0x25e4}, 1582 {OP_WR, QM_REG_BYTECRDCOST, 0x25e4},
912 {OP_WR, QM_REG_BYTECREDITAFULLTHR, 0x7fff}, 1583 {OP_WR, QM_REG_BYTECREDITAFULLTHR, 0x7fff},
913 {OP_WR, QM_REG_ENBYTECRD_LSB, 0x7}, 1584 {OP_WR_E1, QM_REG_ENBYTECRD_LSB, 0x7},
914 {OP_WR, QM_REG_ENBYTECRD_MSB, 0x7}, 1585 {OP_WR_E1H, QM_REG_ENBYTECRD_LSB, 0x70007},
1586 {OP_WR_E1, QM_REG_ENBYTECRD_MSB, 0x7},
1587 {OP_WR_E1H, QM_REG_ENBYTECRD_MSB, 0x70007},
1588 {OP_WR_E1H, QM_REG_ENBYTECRD_LSB_EXT_A, 0x70007},
1589 {OP_WR_E1H, QM_REG_ENBYTECRD_MSB_EXT_A, 0x70007},
915 {OP_WR, QM_REG_BYTECRDPORT_LSB, 0x0}, 1590 {OP_WR, QM_REG_BYTECRDPORT_LSB, 0x0},
916 {OP_WR, QM_REG_BYTECRDPORT_MSB, 0xffffffff}, 1591 {OP_WR, QM_REG_BYTECRDPORT_MSB, 0xffffffff},
917 {OP_WR, QM_REG_FUNCNUMSEL_LSB, 0x0}, 1592 {OP_WR_E1, QM_REG_FUNCNUMSEL_LSB, 0x0},
918 {OP_WR, QM_REG_FUNCNUMSEL_MSB, 0xffffffff}, 1593 {OP_WR_E1H, QM_REG_BYTECRDPORT_LSB_EXT_A, 0x0},
1594 {OP_WR_E1, QM_REG_FUNCNUMSEL_MSB, 0xffffffff},
1595 {OP_WR_E1H, QM_REG_BYTECRDPORT_MSB_EXT_A, 0xffffffff},
1596 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_0, 0x0},
1597 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_1, 0x2},
1598 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_2, 0x1},
1599 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_3, 0x3},
1600 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_4, 0x4},
1601 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_5, 0x6},
1602 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_6, 0x5},
1603 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_7, 0x7},
919 {OP_WR, QM_REG_CMINTEN, 0xff}, 1604 {OP_WR, QM_REG_CMINTEN, 0xff},
920#define QM_COMMON_END 829 1605#define QM_COMMON_END 1400
921#define PBF_COMMON_START 829 1606#define PBF_COMMON_START 1400
922 {OP_WR, PBF_REG_INIT, 0x1}, 1607 {OP_WR, PBF_REG_INIT, 0x1},
923 {OP_WR, PBF_REG_INIT_P4, 0x1}, 1608 {OP_WR, PBF_REG_INIT_P4, 0x1},
924 {OP_WR, PBF_REG_MAC_LB_ENABLE, 0x1}, 1609 {OP_WR, PBF_REG_MAC_LB_ENABLE, 0x1},
@@ -926,20 +1611,20 @@ static const struct raw_op init_ops[] = {
926 {OP_WR, PBF_REG_INIT_P4, 0x0}, 1611 {OP_WR, PBF_REG_INIT_P4, 0x0},
927 {OP_WR, PBF_REG_INIT, 0x0}, 1612 {OP_WR, PBF_REG_INIT, 0x0},
928 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P4, 0x0}, 1613 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P4, 0x0},
929#define PBF_COMMON_END 836 1614#define PBF_COMMON_END 1407
930#define PBF_PORT0_START 836 1615#define PBF_PORT0_START 1407
931 {OP_WR, PBF_REG_INIT_P0, 0x1}, 1616 {OP_WR, PBF_REG_INIT_P0, 0x1},
932 {OP_WR, PBF_REG_MAC_IF0_ENABLE, 0x1}, 1617 {OP_WR, PBF_REG_MAC_IF0_ENABLE, 0x1},
933 {OP_WR, PBF_REG_INIT_P0, 0x0}, 1618 {OP_WR, PBF_REG_INIT_P0, 0x0},
934 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P0, 0x0}, 1619 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P0, 0x0},
935#define PBF_PORT0_END 840 1620#define PBF_PORT0_END 1411
936#define PBF_PORT1_START 840 1621#define PBF_PORT1_START 1411
937 {OP_WR, PBF_REG_INIT_P1, 0x1}, 1622 {OP_WR, PBF_REG_INIT_P1, 0x1},
938 {OP_WR, PBF_REG_MAC_IF1_ENABLE, 0x1}, 1623 {OP_WR, PBF_REG_MAC_IF1_ENABLE, 0x1},
939 {OP_WR, PBF_REG_INIT_P1, 0x0}, 1624 {OP_WR, PBF_REG_INIT_P1, 0x0},
940 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P1, 0x0}, 1625 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P1, 0x0},
941#define PBF_PORT1_END 844 1626#define PBF_PORT1_END 1415
942#define XCM_COMMON_START 844 1627#define XCM_COMMON_START 1415
943 {OP_WR, XCM_REG_XX_OVFL_EVNT_ID, 0x32}, 1628 {OP_WR, XCM_REG_XX_OVFL_EVNT_ID, 0x32},
944 {OP_WR, XCM_REG_XQM_XCM_HDR_P, 0x3150020}, 1629 {OP_WR, XCM_REG_XQM_XCM_HDR_P, 0x3150020},
945 {OP_WR, XCM_REG_XQM_XCM_HDR_S, 0x3150020}, 1630 {OP_WR, XCM_REG_XQM_XCM_HDR_S, 0x3150020},
@@ -971,14 +1656,18 @@ static const struct raw_op init_ops[] = {
971 {OP_WR, XCM_REG_TM_INIT_CRD, 0x4}, 1656 {OP_WR, XCM_REG_TM_INIT_CRD, 0x4},
972 {OP_WR, XCM_REG_XQM_INIT_CRD, 0x20}, 1657 {OP_WR, XCM_REG_XQM_INIT_CRD, 0x20},
973 {OP_WR, XCM_REG_XX_INIT_CRD, 0x2}, 1658 {OP_WR, XCM_REG_XX_INIT_CRD, 0x2},
974 {OP_WR, XCM_REG_XX_MSG_NUM, 0x1f}, 1659 {OP_WR_E1, XCM_REG_XX_MSG_NUM, 0x1f},
1660 {OP_WR_E1H, XCM_REG_XX_MSG_NUM, 0x20},
975 {OP_ZR, XCM_REG_XX_TABLE, 0x12}, 1661 {OP_ZR, XCM_REG_XX_TABLE, 0x12},
976 {OP_SW, XCM_REG_XX_DESCR_TABLE, 0x1f4d01}, 1662 {OP_SW_E1, XCM_REG_XX_DESCR_TABLE, 0x1f02ce},
1663 {OP_SW_E1H, XCM_REG_XX_DESCR_TABLE, 0x1f0302},
977 {OP_WR, XCM_REG_N_SM_CTX_LD_0, 0xf}, 1664 {OP_WR, XCM_REG_N_SM_CTX_LD_0, 0xf},
978 {OP_WR, XCM_REG_N_SM_CTX_LD_1, 0x7}, 1665 {OP_WR, XCM_REG_N_SM_CTX_LD_1, 0x7},
979 {OP_WR, XCM_REG_N_SM_CTX_LD_2, 0xb}, 1666 {OP_WR, XCM_REG_N_SM_CTX_LD_2, 0xb},
980 {OP_WR, XCM_REG_N_SM_CTX_LD_3, 0xe}, 1667 {OP_WR, XCM_REG_N_SM_CTX_LD_3, 0xe},
981 {OP_ZR, XCM_REG_N_SM_CTX_LD_4, 0x4}, 1668 {OP_ZR_E1, XCM_REG_N_SM_CTX_LD_4, 0x4},
1669 {OP_WR_E1H, XCM_REG_N_SM_CTX_LD_4, 0xc},
1670 {OP_ZR_E1H, XCM_REG_N_SM_CTX_LD_5, 0x3},
982 {OP_WR, XCM_REG_XCM_REG0_SZ, 0x4}, 1671 {OP_WR, XCM_REG_XCM_REG0_SZ, 0x4},
983 {OP_WR, XCM_REG_XCM_STORM0_IFEN, 0x1}, 1672 {OP_WR, XCM_REG_XCM_STORM0_IFEN, 0x1},
984 {OP_WR, XCM_REG_XCM_STORM1_IFEN, 0x1}, 1673 {OP_WR, XCM_REG_XCM_STORM1_IFEN, 0x1},
@@ -1000,28 +1689,116 @@ static const struct raw_op init_ops[] = {
1000 {OP_WR, XCM_REG_CDU_SM_WR_IFEN, 0x1}, 1689 {OP_WR, XCM_REG_CDU_SM_WR_IFEN, 0x1},
1001 {OP_WR, XCM_REG_CDU_SM_RD_IFEN, 0x1}, 1690 {OP_WR, XCM_REG_CDU_SM_RD_IFEN, 0x1},
1002 {OP_WR, XCM_REG_XCM_CFC_IFEN, 0x1}, 1691 {OP_WR, XCM_REG_XCM_CFC_IFEN, 0x1},
1003#define XCM_COMMON_END 904 1692#define XCM_COMMON_END 1479
1004#define XCM_PORT0_START 904 1693#define XCM_PORT0_START 1479
1005 {OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8}, 1694 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
1006 {OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2}, 1695 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
1007 {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0}, 1696 {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
1008 {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0}, 1697 {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
1009 {OP_WR, XCM_REG_WU_DA_CNT_CMD00, 0x2}, 1698 {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD00, 0x2},
1010 {OP_WR, XCM_REG_WU_DA_CNT_CMD10, 0x2}, 1699 {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD10, 0x2},
1011 {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff}, 1700 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
1012 {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff}, 1701 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
1013#define XCM_PORT0_END 912 1702#define XCM_PORT0_END 1487
1014#define XCM_PORT1_START 912 1703#define XCM_PORT1_START 1487
1015 {OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8}, 1704 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
1016 {OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2}, 1705 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
1017 {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0}, 1706 {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
1018 {OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0}, 1707 {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
1019 {OP_WR, XCM_REG_WU_DA_CNT_CMD01, 0x2}, 1708 {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD01, 0x2},
1020 {OP_WR, XCM_REG_WU_DA_CNT_CMD11, 0x2}, 1709 {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD11, 0x2},
1021 {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff}, 1710 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
1022 {OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff}, 1711 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
1023#define XCM_PORT1_END 920 1712#define XCM_PORT1_END 1495
1024#define XSEM_COMMON_START 920 1713#define XCM_FUNC0_START 1495
1714 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
1715 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
1716 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
1717 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
1718 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD00, 0x2},
1719 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD10, 0x2},
1720 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
1721 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
1722 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
1723#define XCM_FUNC0_END 1504
1724#define XCM_FUNC1_START 1504
1725 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
1726 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
1727 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
1728 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
1729 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD01, 0x2},
1730 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD11, 0x2},
1731 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
1732 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
1733 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
1734#define XCM_FUNC1_END 1513
1735#define XCM_FUNC2_START 1513
1736 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
1737 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
1738 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
1739 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
1740 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD00, 0x2},
1741 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD10, 0x2},
1742 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
1743 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
1744 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
1745#define XCM_FUNC2_END 1522
1746#define XCM_FUNC3_START 1522
1747 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
1748 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
1749 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
1750 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
1751 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD01, 0x2},
1752 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD11, 0x2},
1753 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
1754 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
1755 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
1756#define XCM_FUNC3_END 1531
1757#define XCM_FUNC4_START 1531
1758 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
1759 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
1760 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
1761 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
1762 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD00, 0x2},
1763 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD10, 0x2},
1764 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
1765 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
1766 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
1767#define XCM_FUNC4_END 1540
1768#define XCM_FUNC5_START 1540
1769 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
1770 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
1771 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
1772 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
1773 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD01, 0x2},
1774 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD11, 0x2},
1775 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
1776 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
1777 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
1778#define XCM_FUNC5_END 1549
1779#define XCM_FUNC6_START 1549
1780 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
1781 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
1782 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
1783 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
1784 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD00, 0x2},
1785 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD10, 0x2},
1786 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
1787 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
1788 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
1789#define XCM_FUNC6_END 1558
1790#define XCM_FUNC7_START 1558
1791 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
1792 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
1793 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
1794 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
1795 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD01, 0x2},
1796 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD11, 0x2},
1797 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
1798 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
1799 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
1800#define XCM_FUNC7_END 1567
1801#define XSEM_COMMON_START 1567
1025 {OP_RD, XSEM_REG_MSG_NUM_FIC0, 0x0}, 1802 {OP_RD, XSEM_REG_MSG_NUM_FIC0, 0x0},
1026 {OP_RD, XSEM_REG_MSG_NUM_FIC1, 0x0}, 1803 {OP_RD, XSEM_REG_MSG_NUM_FIC1, 0x0},
1027 {OP_RD, XSEM_REG_MSG_NUM_FOC0, 0x0}, 1804 {OP_RD, XSEM_REG_MSG_NUM_FOC0, 0x0},
@@ -1065,157 +1842,398 @@ static const struct raw_op init_ops[] = {
1065 {OP_WR, XSEM_REG_FAST_MEMORY + 0x18040, 0x18}, 1842 {OP_WR, XSEM_REG_FAST_MEMORY + 0x18040, 0x18},
1066 {OP_WR, XSEM_REG_FAST_MEMORY + 0x18080, 0xc}, 1843 {OP_WR, XSEM_REG_FAST_MEMORY + 0x18080, 0xc},
1067 {OP_WR, XSEM_REG_FAST_MEMORY + 0x180c0, 0x66}, 1844 {OP_WR, XSEM_REG_FAST_MEMORY + 0x180c0, 0x66},
1068 {OP_WR, XSEM_REG_FAST_MEMORY + 0x18300, 0x7a120}, 1845 {OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
1846 {OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18300, 0x138},
1847 {OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18300, 0x1388},
1069 {OP_WR, XSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4}, 1848 {OP_WR, XSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
1070 {OP_WR, XSEM_REG_FAST_MEMORY + 0x18340, 0x1f4}, 1849 {OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18340, 0x1f4},
1071 {OP_WR, XSEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500}, 1850 {OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18340, 0x0},
1072 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x55d8, 0x2}, 1851 {OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18340, 0x5},
1073 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5000, 0x48}, 1852 {OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18380, 0x4c4b4},
1074 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1020, 0xc8}, 1853 {OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500},
1075 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1000, 0x2}, 1854 {OP_WR_EMUL_E1H, XSEM_REG_FAST_MEMORY + 0x11480, 0x0},
1076 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5128, 0x92}, 1855 {OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18380, 0x4c4b40},
1077 {OP_WR, XSEM_REG_FAST_MEMORY + 0x5378, 0x0}, 1856 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3d00, 0x4},
1078 {OP_SW, XSEM_REG_FAST_MEMORY + 0x5380, 0x24d20}, 1857 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x11480, 0x1},
1079 {OP_SW, XSEM_REG_FAST_MEMORY + 0x5428, 0x44d22}, 1858 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3000, 0x48},
1080 {OP_WR, XSEM_REG_FAST_MEMORY + 0x1518, 0x1}, 1859 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x28a8, 0x4},
1081 {OP_WR, XSEM_REG_FAST_MEMORY + 0x1830, 0x0}, 1860 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1020, 0xc8},
1082 {OP_WR, XSEM_REG_FAST_MEMORY + 0x1838, 0x0}, 1861 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2080, 0x48},
1083 {OP_SW, XSEM_REG_FAST_MEMORY + 0x1820, 0x24d26}, 1862 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1000, 0x2},
1084 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4ac0, 0x2}, 1863 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x9020, 0xc8},
1085 {OP_SW, XSEM_REG_FAST_MEMORY + 0x4ad8, 0x24d28}, 1864 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3128, 0x8e},
1086 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4b08, 0x4}, 1865 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x9000, 0x2},
1087 {OP_SW, XSEM_REG_FAST_MEMORY + 0x1f50, 0x24d2a}, 1866 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3368, 0x0},
1867 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x21a8, 0x86},
1868 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3370, 0x202ed},
1869 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2000, 0x20},
1870 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3b90, 0x402ef},
1871 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x23c8, 0x0},
1872 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1518, 0x1},
1873 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x23d0, 0x20321},
1874 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1830, 0x0},
1875 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2498, 0x40323},
1876 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1838, 0x0},
1877 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x2ac8, 0x0},
1878 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1820, 0x202f3},
1879 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x2ab8, 0x0},
1880 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4ac0, 0x2},
1881 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x3010, 0x1},
1882 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4b00, 0x4},
1883 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x4040, 0x10},
1884 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1f50, 0x202f5},
1885 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x4000, 0x100327},
1886 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6ac0, 0x2},
1887 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6b00, 0x4},
1888 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x83b0, 0x20337},
1088 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x0}, 1889 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x0},
1089 {OP_SW, XSEM_REG_FAST_MEMORY + 0x10c00, 0x104d2c}, 1890 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c00, 0x1002f7},
1891 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c00, 0x100339},
1090 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x1000000}, 1892 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x1000000},
1091 {OP_SW, XSEM_REG_FAST_MEMORY + 0x10c40, 0x84d3c}, 1893 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80307},
1894 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80349},
1092 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x2000000}, 1895 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x2000000},
1093 {OP_SW, XSEM_REG_FAST_MEMORY + 0x10c60, 0x84d44}, 1896 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c60, 0x8030f},
1094 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x3000000}, 1897 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c60, 0x80351},
1095 {OP_SW, XSEM_REG_FAST_MEMORY + 0x10c80, 0x84d4c}, 1898 {OP_ZP_E1, XSEM_REG_INT_TABLE, 0xab0000},
1096 {OP_ZP, XSEM_REG_INT_TABLE, 0x814d54}, 1899 {OP_ZP_E1H, XSEM_REG_INT_TABLE, 0xac0000},
1097 {OP_ZP, XSEM_REG_PRAM, 0x35774d75}, 1900 {OP_WR_64_E1, XSEM_REG_INT_TABLE + 0x368, 0x130317},
1098 {OP_ZP, XSEM_REG_PRAM + 0x8000, 0x36525ad3}, 1901 {OP_WR_64_E1H, XSEM_REG_INT_TABLE + 0x368, 0x130359},
1099 {OP_ZP, XSEM_REG_PRAM + 0x10000, 0x27266868}, 1902 {OP_ZP_E1, XSEM_REG_PRAM, 0xc09e0000},
1100 {OP_ZP, XSEM_REG_PRAM + 0x18000, 0x5e7232}, 1903 {OP_ZP_E1H, XSEM_REG_PRAM, 0xc3b20000},
1101 {OP_ZP, XSEM_REG_PRAM + 0x20000, 0x5e724a}, 1904 {OP_WR_64_E1, XSEM_REG_PRAM + 0x1c0c0, 0x47e80319},
1102 {OP_ZP, XSEM_REG_PRAM + 0x28000, 0x5e7262}, 1905 {OP_WR_64_E1H, XSEM_REG_PRAM + 0x1c8c0, 0x46e8035b},
1103 {OP_ZP, XSEM_REG_PRAM + 0x30000, 0x5e727a}, 1906#define XSEM_COMMON_END 1671
1104 {OP_ZP, XSEM_REG_PRAM + 0x38000, 0x5e7292}, 1907#define XSEM_PORT0_START 1671
1105#define XSEM_COMMON_END 1000 1908 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3ba0, 0x10},
1106#define XSEM_PORT0_START 1000 1909 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xc000, 0xfc},
1107 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1400, 0xa}, 1910 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3c20, 0x1c},
1108 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1450, 0x6}, 1911 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x24a8, 0x10},
1109 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5388, 0xc}, 1912 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1400, 0xa},
1110 {OP_SW, XSEM_REG_FAST_MEMORY + 0x5388 + 0x30, 0x272aa}, 1913 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2528, 0x1c},
1111 {OP_SW, XSEM_REG_FAST_MEMORY + 0x55e0, 0x772ac}, 1914 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1450, 0x6},
1112 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5600, 0x7}, 1915 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2608, 0x1c},
1113 {OP_WR, XSEM_REG_FAST_MEMORY + 0x1500, 0x0}, 1916 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3378, 0xfc},
1114 {OP_WR, XSEM_REG_FAST_MEMORY + 0x1508, 0x1}, 1917 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x26e8, 0x1c},
1115 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3020, 0x2}, 1918 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3b58, 0x0},
1116 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3030, 0x2}, 1919 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x27c8, 0x1c},
1117 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3000, 0x2}, 1920 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d10, 0x10031b},
1118 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3010, 0x2}, 1921 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa000, 0x28},
1119 {OP_WR, XSEM_REG_FAST_MEMORY + 0x3040, 0x0}, 1922 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1500, 0x0},
1120 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3048, 0xc}, 1923 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa140, 0xc},
1121 {OP_SW, XSEM_REG_FAST_MEMORY + 0x3048 + 0x30, 0x272b3}, 1924 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1508, 0x1},
1122 {OP_WR, XSEM_REG_FAST_MEMORY + 0x30b8, 0x1}, 1925 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x3000, 0x1},
1123 {OP_SW, XSEM_REG_FAST_MEMORY + 0x4ac8, 0x272b5}, 1926 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5020, 0x2},
1124 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4b18, 0x42}, 1927 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5030, 0x2},
1125 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4d28, 0x4}, 1928 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5000, 0x2},
1126#define XSEM_PORT0_END 1019 1929 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5010, 0x2},
1127#define XSEM_PORT1_START 1019 1930 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x5040, 0x0},
1128 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1428, 0xa}, 1931 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x5208, 0x1},
1129 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x1468, 0x6}, 1932 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x5048, 0xe},
1130 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x53c0, 0xc}, 1933 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x6ac8, 0x2035d},
1131 {OP_SW, XSEM_REG_FAST_MEMORY + 0x53c0 + 0x30, 0x272b7}, 1934 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x50b8, 0x1},
1132 {OP_SW, XSEM_REG_FAST_MEMORY + 0x5620, 0x772b9}, 1935 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6b10, 0x42},
1133 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5640, 0x7}, 1936 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ac8, 0x2032b},
1134 {OP_WR, XSEM_REG_FAST_MEMORY + 0x1504, 0x0}, 1937 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6d20, 0x4},
1135 {OP_WR, XSEM_REG_FAST_MEMORY + 0x150c, 0x1}, 1938 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4b10, 0x42},
1136 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3028, 0x2}, 1939 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4d20, 0x4},
1137 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3038, 0x2}, 1940#define XSEM_PORT0_END 1703
1138 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3008, 0x2}, 1941#define XSEM_PORT1_START 1703
1139 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3018, 0x2}, 1942 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3be0, 0x10},
1140 {OP_WR, XSEM_REG_FAST_MEMORY + 0x3044, 0x0}, 1943 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xc3f0, 0xfc},
1141 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x3080, 0xc}, 1944 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3c90, 0x1c},
1142 {OP_SW, XSEM_REG_FAST_MEMORY + 0x3080 + 0x30, 0x272c0}, 1945 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x24e8, 0x10},
1143 {OP_WR, XSEM_REG_FAST_MEMORY + 0x30bc, 0x1}, 1946 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1428, 0xa},
1144 {OP_SW, XSEM_REG_FAST_MEMORY + 0x4ad0, 0x272c2}, 1947 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2598, 0x1c},
1145 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4c20, 0x42}, 1948 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1468, 0x6},
1146 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x4d38, 0x4}, 1949 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2678, 0x1c},
1147#define XSEM_PORT1_END 1038 1950 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3768, 0xfc},
1148#define CDU_COMMON_START 1038 1951 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2758, 0x1c},
1952 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3b5c, 0x0},
1953 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2838, 0x1c},
1954 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d50, 0x10032d},
1955 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa0a0, 0x28},
1956 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1504, 0x0},
1957 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa170, 0xc},
1958 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x150c, 0x1},
1959 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x3004, 0x1},
1960 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5028, 0x2},
1961 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5038, 0x2},
1962 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5008, 0x2},
1963 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5018, 0x2},
1964 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x5044, 0x0},
1965 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x520c, 0x1},
1966 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x5080, 0xe},
1967 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x6ad0, 0x2035f},
1968 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x50bc, 0x1},
1969 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6c18, 0x42},
1970 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ad0, 0x2033d},
1971 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6d30, 0x4},
1972 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4c18, 0x42},
1973 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4d30, 0x4},
1974#define XSEM_PORT1_END 1735
1975#define XSEM_FUNC0_START 1735
1976 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e0, 0x0},
1977 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x28b8, 0x100361},
1978 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5048, 0xe},
1979#define XSEM_FUNC0_END 1738
1980#define XSEM_FUNC1_START 1738
1981 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e4, 0x0},
1982 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x28f8, 0x100371},
1983 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5080, 0xe},
1984#define XSEM_FUNC1_END 1741
1985#define XSEM_FUNC2_START 1741
1986 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e8, 0x0},
1987 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2938, 0x100381},
1988 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x50b8, 0xe},
1989#define XSEM_FUNC2_END 1744
1990#define XSEM_FUNC3_START 1744
1991 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7ec, 0x0},
1992 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2978, 0x100391},
1993 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x50f0, 0xe},
1994#define XSEM_FUNC3_END 1747
1995#define XSEM_FUNC4_START 1747
1996 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f0, 0x0},
1997 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x29b8, 0x1003a1},
1998 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5128, 0xe},
1999#define XSEM_FUNC4_END 1750
2000#define XSEM_FUNC5_START 1750
2001 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f4, 0x0},
2002 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x29f8, 0x1003b1},
2003 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5160, 0xe},
2004#define XSEM_FUNC5_END 1753
2005#define XSEM_FUNC6_START 1753
2006 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f8, 0x0},
2007 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2a38, 0x1003c1},
2008 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5198, 0xe},
2009#define XSEM_FUNC6_END 1756
2010#define XSEM_FUNC7_START 1756
2011 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7fc, 0x0},
2012 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2a78, 0x1003d1},
2013 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x51d0, 0xe},
2014#define XSEM_FUNC7_END 1759
2015#define CDU_COMMON_START 1759
1149 {OP_WR, CDU_REG_CDU_CONTROL0, 0x1}, 2016 {OP_WR, CDU_REG_CDU_CONTROL0, 0x1},
2017 {OP_WR_E1H, CDU_REG_MF_MODE, 0x1},
1150 {OP_WR, CDU_REG_CDU_CHK_MASK0, 0x3d000}, 2018 {OP_WR, CDU_REG_CDU_CHK_MASK0, 0x3d000},
1151 {OP_WR, CDU_REG_CDU_CHK_MASK1, 0x3d}, 2019 {OP_WR, CDU_REG_CDU_CHK_MASK1, 0x3d},
1152 {OP_WB, CDU_REG_L1TT, 0x20072c4}, 2020 {OP_WB_E1, CDU_REG_L1TT, 0x200033f},
1153 {OP_WB, CDU_REG_MATT, 0x2074c4}, 2021 {OP_WB_E1H, CDU_REG_L1TT, 0x20003e1},
1154 {OP_ZR, CDU_REG_MATT + 0x80, 0x20}, 2022 {OP_WB_E1, CDU_REG_MATT, 0x20053f},
1155#define CDU_COMMON_END 1044 2023 {OP_WB_E1H, CDU_REG_MATT, 0x2805e1},
1156#define DMAE_COMMON_START 1044 2024 {OP_ZR_E1, CDU_REG_MATT + 0x80, 0x2},
2025 {OP_WB_E1, CDU_REG_MATT + 0x88, 0x6055f},
2026 {OP_ZR, CDU_REG_MATT + 0xa0, 0x18},
2027#define CDU_COMMON_END 1770
2028#define DMAE_COMMON_START 1770
2029 {OP_ZR, DMAE_REG_CMD_MEM, 0xe0},
1157 {OP_WR, DMAE_REG_CRC16C_INIT, 0x0}, 2030 {OP_WR, DMAE_REG_CRC16C_INIT, 0x0},
1158 {OP_WR, DMAE_REG_CRC16T10_INIT, 0x1}, 2031 {OP_WR, DMAE_REG_CRC16T10_INIT, 0x1},
1159 {OP_WR, DMAE_REG_PXP_REQ_INIT_CRD, 0x2}, 2032 {OP_WR_E1, DMAE_REG_PXP_REQ_INIT_CRD, 0x1},
2033 {OP_WR_E1H, DMAE_REG_PXP_REQ_INIT_CRD, 0x2},
1160 {OP_WR, DMAE_REG_PCI_IFEN, 0x1}, 2034 {OP_WR, DMAE_REG_PCI_IFEN, 0x1},
1161 {OP_WR, DMAE_REG_GRC_IFEN, 0x1}, 2035 {OP_WR, DMAE_REG_GRC_IFEN, 0x1},
1162#define DMAE_COMMON_END 1049 2036#define DMAE_COMMON_END 1777
1163#define PXP_COMMON_START 1049 2037#define PXP_COMMON_START 1777
1164 {OP_SI, PXP_REG_HST_INBOUND_INT + 0x400, 0x574e4}, 2038 {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x400, 0x50565},
1165 {OP_SI, PXP_REG_HST_INBOUND_INT + 0x420, 0x574e9}, 2039 {OP_WB_E1H, PXP_REG_HST_INBOUND_INT + 0x400, 0x50609},
1166 {OP_SI, PXP_REG_HST_INBOUND_INT, 0x574ee}, 2040 {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x420, 0x5056a},
1167#define PXP_COMMON_END 1052 2041 {OP_WB_E1H, PXP_REG_HST_INBOUND_INT, 0x5060e},
1168#define CFC_COMMON_START 1052 2042 {OP_WB_E1, PXP_REG_HST_INBOUND_INT, 0x5056f},
2043#define PXP_COMMON_END 1782
2044#define CFC_COMMON_START 1782
2045 {OP_ZR_E1H, CFC_REG_LINK_LIST, 0x100},
1169 {OP_WR, CFC_REG_CONTROL0, 0x10}, 2046 {OP_WR, CFC_REG_CONTROL0, 0x10},
1170 {OP_WR, CFC_REG_DISABLE_ON_ERROR, 0x3fff}, 2047 {OP_WR, CFC_REG_DISABLE_ON_ERROR, 0x3fff},
1171 {OP_WR, CFC_REG_LCREQ_WEIGHTS, 0x84924a}, 2048 {OP_WR, CFC_REG_LCREQ_WEIGHTS, 0x84924a},
1172#define CFC_COMMON_END 1055 2049#define CFC_COMMON_END 1786
1173#define HC_COMMON_START 1055 2050#define HC_COMMON_START 1786
1174 {OP_ZR, HC_REG_USTORM_ADDR_FOR_COALESCE, 0x4}, 2051 {OP_ZR_E1, HC_REG_USTORM_ADDR_FOR_COALESCE, 0x4},
1175#define HC_COMMON_END 1056 2052#define HC_COMMON_END 1787
1176#define HC_PORT0_START 1056 2053#define HC_PORT0_START 1787
1177 {OP_WR, HC_REG_CONFIG_0, 0x1080}, 2054 {OP_WR_E1, HC_REG_CONFIG_0, 0x1080},
1178 {OP_ZR, HC_REG_UC_RAM_ADDR_0, 0x2}, 2055 {OP_ZR_E1, HC_REG_UC_RAM_ADDR_0, 0x2},
1179 {OP_WR, HC_REG_ATTN_NUM_P0, 0x10}, 2056 {OP_WR_E1, HC_REG_ATTN_NUM_P0, 0x10},
1180 {OP_WR, HC_REG_LEADING_EDGE_0, 0xffff}, 2057 {OP_WR_E1, HC_REG_LEADING_EDGE_0, 0xffff},
1181 {OP_WR, HC_REG_TRAILING_EDGE_0, 0xffff}, 2058 {OP_WR_E1, HC_REG_TRAILING_EDGE_0, 0xffff},
1182 {OP_WR, HC_REG_AGG_INT_0, 0x0}, 2059 {OP_WR_E1, HC_REG_AGG_INT_0, 0x0},
1183 {OP_WR, HC_REG_ATTN_IDX, 0x0}, 2060 {OP_WR_E1, HC_REG_ATTN_IDX, 0x0},
1184 {OP_ZR, HC_REG_ATTN_BIT, 0x2}, 2061 {OP_ZR_E1, HC_REG_ATTN_BIT, 0x2},
1185 {OP_WR, HC_REG_VQID_0, 0x2b5}, 2062 {OP_WR_E1, HC_REG_VQID_0, 0x2b5},
1186 {OP_WR, HC_REG_PCI_CONFIG_0, 0x0}, 2063 {OP_WR_E1, HC_REG_PCI_CONFIG_0, 0x0},
1187 {OP_ZR, HC_REG_P0_PROD_CONS, 0x4a}, 2064 {OP_ZR_E1, HC_REG_P0_PROD_CONS, 0x4a},
1188 {OP_ZR, HC_REG_PBA_COMMAND, 0x2}, 2065 {OP_WR_E1, HC_REG_INT_MASK, 0x1ffff},
1189 {OP_WR, HC_REG_INT_MASK, 0x1ffff}, 2066 {OP_ZR_E1, HC_REG_PBA_COMMAND, 0x2},
1190 {OP_WR, HC_REG_CONFIG_0, 0x1a82}, 2067 {OP_WR_E1, HC_REG_CONFIG_0, 0x1a80},
1191 {OP_ZR, HC_REG_STATISTIC_COUNTERS, 0x24}, 2068 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS, 0x24},
1192 {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a}, 2069 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
1193 {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a}, 2070 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
1194 {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a}, 2071 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
1195#define HC_PORT0_END 1074 2072 {OP_ZR_E1, HC_REG_PBA_COMMAND, 0x2},
1196#define HC_PORT1_START 1074 2073#define HC_PORT0_END 1806
1197 {OP_WR, HC_REG_CONFIG_1, 0x1080}, 2074#define HC_PORT1_START 1806
1198 {OP_ZR, HC_REG_UC_RAM_ADDR_1, 0x2}, 2075 {OP_WR_E1, HC_REG_CONFIG_1, 0x1080},
1199 {OP_WR, HC_REG_ATTN_NUM_P1, 0x10}, 2076 {OP_ZR_E1, HC_REG_UC_RAM_ADDR_1, 0x2},
1200 {OP_WR, HC_REG_LEADING_EDGE_1, 0xffff}, 2077 {OP_WR_E1, HC_REG_ATTN_NUM_P1, 0x10},
1201 {OP_WR, HC_REG_TRAILING_EDGE_1, 0xffff}, 2078 {OP_WR_E1, HC_REG_LEADING_EDGE_1, 0xffff},
1202 {OP_WR, HC_REG_AGG_INT_1, 0x0}, 2079 {OP_WR_E1, HC_REG_TRAILING_EDGE_1, 0xffff},
1203 {OP_WR, HC_REG_ATTN_IDX + 0x4, 0x0}, 2080 {OP_WR_E1, HC_REG_AGG_INT_1, 0x0},
1204 {OP_ZR, HC_REG_ATTN_BIT + 0x8, 0x2}, 2081 {OP_WR_E1, HC_REG_ATTN_IDX + 0x4, 0x0},
1205 {OP_WR, HC_REG_VQID_1, 0x2b5}, 2082 {OP_ZR_E1, HC_REG_ATTN_BIT + 0x8, 0x2},
1206 {OP_WR, HC_REG_PCI_CONFIG_1, 0x0}, 2083 {OP_WR_E1, HC_REG_VQID_1, 0x2b5},
1207 {OP_ZR, HC_REG_P1_PROD_CONS, 0x4a}, 2084 {OP_WR_E1, HC_REG_PCI_CONFIG_1, 0x0},
1208 {OP_ZR, HC_REG_PBA_COMMAND + 0x8, 0x2}, 2085 {OP_ZR_E1, HC_REG_P1_PROD_CONS, 0x4a},
1209 {OP_WR, HC_REG_INT_MASK + 0x4, 0x1ffff}, 2086 {OP_WR_E1, HC_REG_INT_MASK + 0x4, 0x1ffff},
1210 {OP_WR, HC_REG_CONFIG_1, 0x1a82}, 2087 {OP_ZR_E1, HC_REG_PBA_COMMAND + 0x8, 0x2},
1211 {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24}, 2088 {OP_WR_E1, HC_REG_CONFIG_1, 0x1a80},
1212 {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a}, 2089 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
1213 {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a}, 2090 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
1214 {OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a}, 2091 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
1215#define HC_PORT1_END 1092 2092 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
1216#define PXP2_COMMON_START 1092 2093 {OP_ZR_E1, HC_REG_PBA_COMMAND + 0x8, 0x2},
1217 {OP_WR, PXP2_REG_PGL_CONTROL0, 0xe38324}, 2094#define HC_PORT1_END 1825
2095#define HC_FUNC0_START 1825
2096 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
2097 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x0},
2098 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
2099 {OP_WR_E1H, HC_REG_ATTN_IDX, 0x0},
2100 {OP_ZR_E1H, HC_REG_ATTN_BIT, 0x2},
2101 {OP_WR_E1H, HC_REG_VQID_0, 0x2b5},
2102 {OP_WR_E1H, HC_REG_PCI_CONFIG_0, 0x0},
2103 {OP_ZR_E1H, HC_REG_P0_PROD_CONS, 0x4a},
2104 {OP_WR_E1H, HC_REG_INT_MASK, 0x1ffff},
2105 {OP_ZR_E1H, HC_REG_PBA_COMMAND, 0x2},
2106 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1a80},
2107 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS, 0x24},
2108 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
2109 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
2110 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
2111#define HC_FUNC0_END 1840
2112#define HC_FUNC1_START 1840
2113 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
2114 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x1},
2115 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
2116 {OP_WR_E1H, HC_REG_ATTN_IDX + 0x4, 0x0},
2117 {OP_ZR_E1H, HC_REG_ATTN_BIT + 0x8, 0x2},
2118 {OP_WR_E1H, HC_REG_VQID_1, 0x2b5},
2119 {OP_WR_E1H, HC_REG_PCI_CONFIG_1, 0x0},
2120 {OP_ZR_E1H, HC_REG_P1_PROD_CONS, 0x4a},
2121 {OP_WR_E1H, HC_REG_INT_MASK + 0x4, 0x1ffff},
2122 {OP_ZR_E1H, HC_REG_PBA_COMMAND + 0x8, 0x2},
2123 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1a80},
2124 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
2125 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
2126 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
2127 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
2128#define HC_FUNC1_END 1855
2129#define HC_FUNC2_START 1855
2130 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
2131 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x2},
2132 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
2133 {OP_WR_E1H, HC_REG_ATTN_IDX, 0x0},
2134 {OP_ZR_E1H, HC_REG_ATTN_BIT, 0x2},
2135 {OP_WR_E1H, HC_REG_VQID_0, 0x2b5},
2136 {OP_WR_E1H, HC_REG_PCI_CONFIG_0, 0x0},
2137 {OP_ZR_E1H, HC_REG_P0_PROD_CONS, 0x4a},
2138 {OP_WR_E1H, HC_REG_INT_MASK, 0x1ffff},
2139 {OP_ZR_E1H, HC_REG_PBA_COMMAND, 0x2},
2140 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1a80},
2141 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS, 0x24},
2142 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
2143 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
2144 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
2145#define HC_FUNC2_END 1870
2146#define HC_FUNC3_START 1870
2147 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
2148 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x3},
2149 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
2150 {OP_WR_E1H, HC_REG_ATTN_IDX + 0x4, 0x0},
2151 {OP_ZR_E1H, HC_REG_ATTN_BIT + 0x8, 0x2},
2152 {OP_WR_E1H, HC_REG_VQID_1, 0x2b5},
2153 {OP_WR_E1H, HC_REG_PCI_CONFIG_1, 0x0},
2154 {OP_ZR_E1H, HC_REG_P1_PROD_CONS, 0x4a},
2155 {OP_WR_E1H, HC_REG_INT_MASK + 0x4, 0x1ffff},
2156 {OP_ZR_E1H, HC_REG_PBA_COMMAND + 0x8, 0x2},
2157 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1a80},
2158 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
2159 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
2160 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
2161 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
2162#define HC_FUNC3_END 1885
2163#define HC_FUNC4_START 1885
2164 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
2165 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x4},
2166 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
2167 {OP_WR_E1H, HC_REG_ATTN_IDX, 0x0},
2168 {OP_ZR_E1H, HC_REG_ATTN_BIT, 0x2},
2169 {OP_WR_E1H, HC_REG_VQID_0, 0x2b5},
2170 {OP_WR_E1H, HC_REG_PCI_CONFIG_0, 0x0},
2171 {OP_ZR_E1H, HC_REG_P0_PROD_CONS, 0x4a},
2172 {OP_WR_E1H, HC_REG_INT_MASK, 0x1ffff},
2173 {OP_ZR_E1H, HC_REG_PBA_COMMAND, 0x2},
2174 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1a80},
2175 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS, 0x24},
2176 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
2177 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
2178 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
2179#define HC_FUNC4_END 1900
2180#define HC_FUNC5_START 1900
2181 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
2182 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x5},
2183 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
2184 {OP_WR_E1H, HC_REG_ATTN_IDX + 0x4, 0x0},
2185 {OP_ZR_E1H, HC_REG_ATTN_BIT + 0x8, 0x2},
2186 {OP_WR_E1H, HC_REG_VQID_1, 0x2b5},
2187 {OP_WR_E1H, HC_REG_PCI_CONFIG_1, 0x0},
2188 {OP_ZR_E1H, HC_REG_P1_PROD_CONS, 0x4a},
2189 {OP_WR_E1H, HC_REG_INT_MASK + 0x4, 0x1ffff},
2190 {OP_ZR_E1H, HC_REG_PBA_COMMAND + 0x8, 0x2},
2191 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1a80},
2192 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
2193 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
2194 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
2195 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
2196#define HC_FUNC5_END 1915
2197#define HC_FUNC6_START 1915
2198 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
2199 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x6},
2200 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
2201 {OP_WR_E1H, HC_REG_ATTN_IDX, 0x0},
2202 {OP_ZR_E1H, HC_REG_ATTN_BIT, 0x2},
2203 {OP_WR_E1H, HC_REG_VQID_0, 0x2b5},
2204 {OP_WR_E1H, HC_REG_PCI_CONFIG_0, 0x0},
2205 {OP_ZR_E1H, HC_REG_P0_PROD_CONS, 0x4a},
2206 {OP_WR_E1H, HC_REG_INT_MASK, 0x1ffff},
2207 {OP_ZR_E1H, HC_REG_PBA_COMMAND, 0x2},
2208 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1a80},
2209 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS, 0x24},
2210 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
2211 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
2212 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
2213#define HC_FUNC6_END 1930
2214#define HC_FUNC7_START 1930
2215 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
2216 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x7},
2217 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
2218 {OP_WR_E1H, HC_REG_ATTN_IDX + 0x4, 0x0},
2219 {OP_ZR_E1H, HC_REG_ATTN_BIT + 0x8, 0x2},
2220 {OP_WR_E1H, HC_REG_VQID_1, 0x2b5},
2221 {OP_WR_E1H, HC_REG_PCI_CONFIG_1, 0x0},
2222 {OP_ZR_E1H, HC_REG_P1_PROD_CONS, 0x4a},
2223 {OP_WR_E1H, HC_REG_INT_MASK + 0x4, 0x1ffff},
2224 {OP_ZR_E1H, HC_REG_PBA_COMMAND + 0x8, 0x2},
2225 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1a80},
2226 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
2227 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
2228 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
2229 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
2230#define HC_FUNC7_END 1945
2231#define PXP2_COMMON_START 1945
2232 {OP_WR_E1, PXP2_REG_PGL_CONTROL0, 0xe38340},
2233 {OP_WR_E1H, PXP2_REG_RQ_DRAM_ALIGN, 0x1},
1218 {OP_WR, PXP2_REG_PGL_CONTROL1, 0x3c10}, 2234 {OP_WR, PXP2_REG_PGL_CONTROL1, 0x3c10},
2235 {OP_WR_E1H, PXP2_REG_RQ_ELT_DISABLE, 0x1},
2236 {OP_WR_E1H, PXP2_REG_WR_REV_MODE, 0x0},
1219 {OP_WR, PXP2_REG_PGL_INT_TSDM_0, 0xffffffff}, 2237 {OP_WR, PXP2_REG_PGL_INT_TSDM_0, 0xffffffff},
1220 {OP_WR, PXP2_REG_PGL_INT_TSDM_1, 0xffffffff}, 2238 {OP_WR, PXP2_REG_PGL_INT_TSDM_1, 0xffffffff},
1221 {OP_WR, PXP2_REG_PGL_INT_TSDM_2, 0xffffffff}, 2239 {OP_WR, PXP2_REG_PGL_INT_TSDM_2, 0xffffffff},
@@ -1231,6 +2249,7 @@ static const struct raw_op init_ops[] = {
1231 {OP_WR, PXP2_REG_PGL_INT_USDM_5, 0xffffffff}, 2249 {OP_WR, PXP2_REG_PGL_INT_USDM_5, 0xffffffff},
1232 {OP_WR, PXP2_REG_PGL_INT_USDM_6, 0xffffffff}, 2250 {OP_WR, PXP2_REG_PGL_INT_USDM_6, 0xffffffff},
1233 {OP_WR, PXP2_REG_PGL_INT_USDM_7, 0xffffffff}, 2251 {OP_WR, PXP2_REG_PGL_INT_USDM_7, 0xffffffff},
2252 {OP_WR_E1H, PXP2_REG_PGL_INT_XSDM_1, 0xffffffff},
1234 {OP_WR, PXP2_REG_PGL_INT_XSDM_2, 0xffffffff}, 2253 {OP_WR, PXP2_REG_PGL_INT_XSDM_2, 0xffffffff},
1235 {OP_WR, PXP2_REG_PGL_INT_XSDM_3, 0xffffffff}, 2254 {OP_WR, PXP2_REG_PGL_INT_XSDM_3, 0xffffffff},
1236 {OP_WR, PXP2_REG_PGL_INT_XSDM_4, 0xffffffff}, 2255 {OP_WR, PXP2_REG_PGL_INT_XSDM_4, 0xffffffff},
@@ -1245,9 +2264,11 @@ static const struct raw_op init_ops[] = {
1245 {OP_WR, PXP2_REG_PGL_INT_CSDM_5, 0xffffffff}, 2264 {OP_WR, PXP2_REG_PGL_INT_CSDM_5, 0xffffffff},
1246 {OP_WR, PXP2_REG_PGL_INT_CSDM_6, 0xffffffff}, 2265 {OP_WR, PXP2_REG_PGL_INT_CSDM_6, 0xffffffff},
1247 {OP_WR, PXP2_REG_PGL_INT_CSDM_7, 0xffffffff}, 2266 {OP_WR, PXP2_REG_PGL_INT_CSDM_7, 0xffffffff},
1248 {OP_WR, PXP2_REG_PGL_INT_XSDM_0, 0xffff5330}, 2267 {OP_WR_E1, PXP2_REG_PGL_INT_XSDM_0, 0xffff3330},
1249 {OP_WR, PXP2_REG_PGL_INT_XSDM_1, 0xffff5348}, 2268 {OP_WR_E1H, PXP2_REG_PGL_INT_XSDM_0, 0xff802000},
1250 {OP_WR, PXP2_REG_PGL_INT_USDM_0, 0xf0003000}, 2269 {OP_WR_E1, PXP2_REG_PGL_INT_XSDM_1, 0xffff3340},
2270 {OP_WR_E1H, PXP2_REG_PGL_INT_USDM_0, 0xf0005000},
2271 {OP_WR_E1, PXP2_REG_PGL_INT_USDM_0, 0xf0003000},
1251 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ6, 0x8}, 2272 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ6, 0x8},
1252 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ9, 0x8}, 2273 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ9, 0x8},
1253 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ10, 0x8}, 2274 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ10, 0x8},
@@ -1257,6 +2278,7 @@ static const struct raw_op init_ops[] = {
1257 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ19, 0x4}, 2278 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ19, 0x4},
1258 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ22, 0x0}, 2279 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ22, 0x0},
1259 {OP_WR, PXP2_REG_RD_START_INIT, 0x1}, 2280 {OP_WR, PXP2_REG_RD_START_INIT, 0x1},
2281 {OP_WR, PXP2_REG_WR_DMAE_TH, 0x3f},
1260 {OP_WR, PXP2_REG_RQ_BW_RD_ADD0, 0x40}, 2282 {OP_WR, PXP2_REG_RQ_BW_RD_ADD0, 0x40},
1261 {OP_WR, PXP2_REG_PSWRQ_BW_ADD1, 0x1808}, 2283 {OP_WR, PXP2_REG_PSWRQ_BW_ADD1, 0x1808},
1262 {OP_WR, PXP2_REG_PSWRQ_BW_ADD2, 0x803}, 2284 {OP_WR, PXP2_REG_PSWRQ_BW_ADD2, 0x803},
@@ -1321,58 +2343,102 @@ static const struct raw_op init_ops[] = {
1321 {OP_WR, PXP2_REG_PSWRQ_BW_L2, 0x1004}, 2343 {OP_WR, PXP2_REG_PSWRQ_BW_L2, 0x1004},
1322 {OP_WR, PXP2_REG_PSWRQ_BW_RD, 0x106440}, 2344 {OP_WR, PXP2_REG_PSWRQ_BW_RD, 0x106440},
1323 {OP_WR, PXP2_REG_PSWRQ_BW_WR, 0x106440}, 2345 {OP_WR, PXP2_REG_PSWRQ_BW_WR, 0x106440},
2346 {OP_WR_E1H, PXP2_REG_RQ_ILT_MODE, 0x1},
1324 {OP_WR, PXP2_REG_RQ_RBC_DONE, 0x1}, 2347 {OP_WR, PXP2_REG_RQ_RBC_DONE, 0x1},
1325#define PXP2_COMMON_END 1200 2348#define PXP2_COMMON_END 2061
1326#define MISC_AEU_COMMON_START 1200 2349#define MISC_AEU_COMMON_START 2061
1327 {OP_ZR, MISC_REG_AEU_GENERAL_ATTN_0, 0x16}, 2350 {OP_ZR, MISC_REG_AEU_GENERAL_ATTN_0, 0x16},
1328#define MISC_AEU_COMMON_END 1201 2351 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_NIG_0, 0x55540000},
1329#define MISC_AEU_PORT0_START 1201 2352 {OP_WR_E1H, MISC_REG_AEU_ENABLE2_NIG_0, 0x55555555},
1330 {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xbf5c0000}, 2353 {OP_WR_E1H, MISC_REG_AEU_ENABLE3_NIG_0, 0x5555},
1331 {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0, 0xfff51fef}, 2354 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_NIG_0, 0xf0000000},
2355 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_PXP_0, 0x55540000},
2356 {OP_WR_E1H, MISC_REG_AEU_ENABLE2_PXP_0, 0x55555555},
2357 {OP_WR_E1H, MISC_REG_AEU_ENABLE3_PXP_0, 0x5555},
2358 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_PXP_0, 0xf0000000},
2359 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_NIG_1, 0x55540000},
2360 {OP_WR_E1H, MISC_REG_AEU_ENABLE2_NIG_1, 0x55555555},
2361 {OP_WR_E1H, MISC_REG_AEU_ENABLE3_NIG_1, 0x5555},
2362 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_NIG_1, 0xf0000000},
2363 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_PXP_1, 0x0},
2364 {OP_WR_E1H, MISC_REG_AEU_ENABLE2_PXP_1, 0x10000},
2365 {OP_WR_E1H, MISC_REG_AEU_ENABLE3_PXP_1, 0x5014},
2366 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_PXP_1, 0x0},
2367 {OP_WR_E1H, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0xc00},
2368 {OP_WR_E1H, MISC_REG_AEU_GENERAL_MASK, 0x3},
2369#define MISC_AEU_COMMON_END 2080
2370#define MISC_AEU_PORT0_START 2080
2371 {OP_WR_E1, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xbf5c0000},
2372 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xff5c0000},
2373 {OP_WR_E1, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0, 0xfff51fef},
2374 {OP_WR_E1H, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0, 0xfff55fff},
1332 {OP_WR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0, 0xffff}, 2375 {OP_WR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0, 0xffff},
1333 {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0, 0x500003e0}, 2376 {OP_WR_E1, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0, 0x500003e0},
2377 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0, 0xf00003e0},
1334 {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1, 0x0}, 2378 {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1, 0x0},
1335 {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1, 0xa000}, 2379 {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1, 0xa000},
1336 {OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1, 0x5}, 2380 {OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1, 0x5},
1337 {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2, 0xfe00000}, 2381 {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2, 0xfe00000},
1338 {OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3, 0x14}, 2382 {OP_ZR_E1, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3, 0x14},
1339 {OP_WR, MISC_REG_AEU_ENABLE1_NIG_0, 0x55540000}, 2383 {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3, 0x7},
1340 {OP_WR, MISC_REG_AEU_ENABLE2_NIG_0, 0x55555555}, 2384 {OP_WR_E1, MISC_REG_AEU_ENABLE1_NIG_0, 0x55540000},
1341 {OP_WR, MISC_REG_AEU_ENABLE3_NIG_0, 0x5555}, 2385 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4, 0x400},
1342 {OP_WR, MISC_REG_AEU_ENABLE4_NIG_0, 0x0}, 2386 {OP_WR_E1, MISC_REG_AEU_ENABLE2_NIG_0, 0x55555555},
1343 {OP_WR, MISC_REG_AEU_ENABLE1_PXP_0, 0x55540000}, 2387 {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5, 0x3},
1344 {OP_WR, MISC_REG_AEU_ENABLE2_PXP_0, 0x55555555}, 2388 {OP_WR_E1, MISC_REG_AEU_ENABLE3_NIG_0, 0x5555},
1345 {OP_WR, MISC_REG_AEU_ENABLE3_PXP_0, 0x5555}, 2389 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5, 0x1000},
1346 {OP_WR, MISC_REG_AEU_ENABLE4_PXP_0, 0x0}, 2390 {OP_WR_E1, MISC_REG_AEU_ENABLE4_NIG_0, 0x0},
1347 {OP_WR, MISC_REG_AEU_INVERTER_1_FUNC_0, 0x0}, 2391 {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6, 0x3},
1348 {OP_ZR, MISC_REG_AEU_INVERTER_2_FUNC_0, 0x3}, 2392 {OP_WR_E1, MISC_REG_AEU_ENABLE1_PXP_0, 0x55540000},
1349 {OP_WR, MISC_REG_AEU_MASK_ATTN_FUNC_0, 0x7}, 2393 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6, 0x4000},
1350#define MISC_AEU_PORT0_END 1221 2394 {OP_WR_E1, MISC_REG_AEU_ENABLE2_PXP_0, 0x55555555},
1351#define MISC_AEU_PORT1_START 1221 2395 {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7, 0x3},
1352 {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xbf5c0000}, 2396 {OP_WR_E1, MISC_REG_AEU_ENABLE3_PXP_0, 0x5555},
1353 {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0, 0xfff51fef}, 2397 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7, 0x10000},
2398 {OP_WR_E1, MISC_REG_AEU_ENABLE4_PXP_0, 0x0},
2399 {OP_ZR_E1H, MISC_REG_AEU_INVERTER_1_FUNC_0, 0x4},
2400 {OP_WR_E1, MISC_REG_AEU_INVERTER_1_FUNC_0, 0x0},
2401 {OP_ZR_E1, MISC_REG_AEU_INVERTER_2_FUNC_0, 0x3},
2402 {OP_WR_E1, MISC_REG_AEU_MASK_ATTN_FUNC_0, 0x7},
2403#define MISC_AEU_PORT0_END 2112
2404#define MISC_AEU_PORT1_START 2112
2405 {OP_WR_E1, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xbf5c0000},
2406 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xff5c0000},
2407 {OP_WR_E1, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0, 0xfff51fef},
2408 {OP_WR_E1H, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0, 0xfff55fff},
1354 {OP_WR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0, 0xffff}, 2409 {OP_WR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0, 0xffff},
1355 {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0, 0x500003e0}, 2410 {OP_WR_E1, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0, 0x500003e0},
2411 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0, 0xf00003e0},
1356 {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1, 0x0}, 2412 {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1, 0x0},
1357 {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1, 0xa000}, 2413 {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1, 0xa000},
1358 {OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1, 0x5}, 2414 {OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1, 0x5},
1359 {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2, 0xfe00000}, 2415 {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2, 0xfe00000},
1360 {OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3, 0x14}, 2416 {OP_ZR_E1, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3, 0x14},
1361 {OP_WR, MISC_REG_AEU_ENABLE1_NIG_1, 0x55540000}, 2417 {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3, 0x7},
1362 {OP_WR, MISC_REG_AEU_ENABLE2_NIG_1, 0x55555555}, 2418 {OP_WR_E1, MISC_REG_AEU_ENABLE1_NIG_1, 0x55540000},
1363 {OP_WR, MISC_REG_AEU_ENABLE3_NIG_1, 0x5555}, 2419 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4, 0x800},
1364 {OP_WR, MISC_REG_AEU_ENABLE4_NIG_1, 0x0}, 2420 {OP_WR_E1, MISC_REG_AEU_ENABLE2_NIG_1, 0x55555555},
1365 {OP_WR, MISC_REG_AEU_ENABLE1_PXP_1, 0x55540000}, 2421 {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5, 0x3},
1366 {OP_WR, MISC_REG_AEU_ENABLE2_PXP_1, 0x55555555}, 2422 {OP_WR_E1, MISC_REG_AEU_ENABLE3_NIG_1, 0x5555},
1367 {OP_WR, MISC_REG_AEU_ENABLE3_PXP_1, 0x5555}, 2423 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5, 0x2000},
1368 {OP_WR, MISC_REG_AEU_ENABLE4_PXP_1, 0x0}, 2424 {OP_WR_E1, MISC_REG_AEU_ENABLE4_NIG_1, 0x0},
1369 {OP_WR, MISC_REG_AEU_INVERTER_1_FUNC_1, 0x0}, 2425 {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6, 0x3},
1370 {OP_ZR, MISC_REG_AEU_INVERTER_2_FUNC_1, 0x3}, 2426 {OP_WR_E1, MISC_REG_AEU_ENABLE1_PXP_1, 0x55540000},
1371 {OP_WR, MISC_REG_AEU_MASK_ATTN_FUNC_1, 0x7} 2427 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6, 0x8000},
1372#define MISC_AEU_PORT1_END 1241 2428 {OP_WR_E1, MISC_REG_AEU_ENABLE2_PXP_1, 0x55555555},
2429 {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7, 0x3},
2430 {OP_WR_E1, MISC_REG_AEU_ENABLE3_PXP_1, 0x5555},
2431 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7, 0x20000},
2432 {OP_WR_E1, MISC_REG_AEU_ENABLE4_PXP_1, 0x0},
2433 {OP_ZR_E1H, MISC_REG_AEU_INVERTER_1_FUNC_1, 0x4},
2434 {OP_WR_E1, MISC_REG_AEU_INVERTER_1_FUNC_1, 0x0},
2435 {OP_ZR_E1, MISC_REG_AEU_INVERTER_2_FUNC_1, 0x3},
2436 {OP_WR_E1, MISC_REG_AEU_MASK_ATTN_FUNC_1, 0x7},
2437#define MISC_AEU_PORT1_END 2144
2438
1373}; 2439};
1374 2440
1375static const u32 init_data[] = { 2441static const u32 init_data_e1[] = {
1376 0x00010000, 0x000204c0, 0x00030980, 0x00040e40, 0x00051300, 0x000617c0, 2442 0x00010000, 0x000204c0, 0x00030980, 0x00040e40, 0x00051300, 0x000617c0,
1377 0x00071c80, 0x00082140, 0x00092600, 0x000a2ac0, 0x000b2f80, 0x000c3440, 2443 0x00071c80, 0x00082140, 0x00092600, 0x000a2ac0, 0x000b2f80, 0x000c3440,
1378 0x000d3900, 0x000e3dc0, 0x000f4280, 0x00104740, 0x00114c00, 0x001250c0, 2444 0x000d3900, 0x000e3dc0, 0x000f4280, 0x00104740, 0x00114c00, 0x001250c0,
@@ -6365,4 +7431,55 @@ static const u32 init_data[] = {
6365 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000 7431 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x00002000
6366}; 7432};
6367 7433
7434static const u32 init_data_e1h[] = {
7435};
7436
7437static const u32 tsem_int_table_data_e1[] = {
7438};
7439
7440static const u32 tsem_pram_data_e1[] = {
7441};
7442
7443static const u32 usem_int_table_data_e1[] = {
7444};
7445
7446static const u32 usem_pram_data_e1[] = {
7447};
7448
7449static const u32 csem_int_table_data_e1[] = {
7450};
7451
7452static const u32 csem_pram_data_e1[] = {
7453};
7454
7455static const u32 xsem_int_table_data_e1[] = {
7456};
7457
7458static const u32 xsem_pram_data_e1[] = {
7459};
7460
7461static const u32 tsem_int_table_data_e1h[] = {
7462};
7463
7464static const u32 tsem_pram_data_e1h[] = {
7465};
7466
7467static const u32 usem_int_table_data_e1h[] = {
7468};
7469
7470static const u32 usem_pram_data_e1h[] = {
7471};
7472
7473static const u32 csem_int_table_data_e1h[] = {
7474};
7475
7476static const u32 csem_pram_data_e1h[] = {
7477};
7478
7479static const u32 xsem_int_table_data_e1h[] = {
7480};
7481
7482static const u32 xsem_pram_data_e1h[] = {
7483};
7484
6368#endif /*__BNX2X_INIT_VALUES_H__*/ 7485#endif /*__BNX2X_INIT_VALUES_H__*/
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c
index 7b547f03b565..efa942688f84 100644
--- a/drivers/net/bnx2x_main.c
+++ b/drivers/net/bnx2x_main.c
@@ -137,7 +137,6 @@ static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
137 PCICFG_VENDOR_ID_OFFSET); 137 PCICFG_VENDOR_ID_OFFSET);
138} 138}
139 139
140#ifdef BNX2X_IND_RD
141static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) 140static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
142{ 141{
143 u32 val; 142 u32 val;
@@ -149,7 +148,6 @@ static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
149 148
150 return val; 149 return val;
151} 150}
152#endif
153 151
154static const u32 dmae_reg_go_c[] = { 152static const u32 dmae_reg_go_c[] = {
155 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 153 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
@@ -169,19 +167,29 @@ static void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae,
169 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { 167 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
170 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); 168 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
171 169
172/* DP(NETIF_MSG_DMAE, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n", 170 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
173 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i)); */ 171 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
174 } 172 }
175 REG_WR(bp, dmae_reg_go_c[idx], 1); 173 REG_WR(bp, dmae_reg_go_c[idx], 1);
176} 174}
177 175
178void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, 176void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
179 u32 dst_addr, u32 len32) 177 u32 len32)
180{ 178{
181 struct dmae_command *dmae = &bp->dmae; 179 struct dmae_command *dmae = &bp->init_dmae;
182 int port = bp->port;
183 u32 *wb_comp = bnx2x_sp(bp, wb_comp); 180 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
184 int timeout = 200; 181 int cnt = 200;
182
183 if (!bp->dmae_ready) {
184 u32 *data = bnx2x_sp(bp, wb_data[0]);
185
186 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
187 " using indirect\n", dst_addr, len32);
188 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
189 return;
190 }
191
192 mutex_lock(&bp->dmae_mutex);
185 193
186 memset(dmae, 0, sizeof(struct dmae_command)); 194 memset(dmae, 0, sizeof(struct dmae_command));
187 195
@@ -193,7 +201,7 @@ void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr,
193#else 201#else
194 DMAE_CMD_ENDIANITY_DW_SWAP | 202 DMAE_CMD_ENDIANITY_DW_SWAP |
195#endif 203#endif
196 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0)); 204 (bp->port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
197 dmae->src_addr_lo = U64_LO(dma_addr); 205 dmae->src_addr_lo = U64_LO(dma_addr);
198 dmae->src_addr_hi = U64_HI(dma_addr); 206 dmae->src_addr_hi = U64_HI(dma_addr);
199 dmae->dst_addr_lo = dst_addr >> 2; 207 dmae->dst_addr_lo = dst_addr >> 2;
@@ -201,48 +209,62 @@ void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr,
201 dmae->len = len32; 209 dmae->len = len32;
202 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); 210 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
203 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); 211 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
204 dmae->comp_val = BNX2X_WB_COMP_VAL; 212 dmae->comp_val = DMAE_COMP_VAL;
205 213
206/* 214 DP(BNX2X_MSG_OFF, "dmae: opcode 0x%08x\n"
207 DP(NETIF_MSG_DMAE, "dmae: opcode 0x%08x\n"
208 DP_LEVEL "src_addr [%x:%08x] len [%d *4] " 215 DP_LEVEL "src_addr [%x:%08x] len [%d *4] "
209 "dst_addr [%x:%08x (%08x)]\n" 216 "dst_addr [%x:%08x (%08x)]\n"
210 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n", 217 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
211 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 218 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
212 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, dst_addr, 219 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, dst_addr,
213 dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val); 220 dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
214*/ 221 DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
215/*
216 DP(NETIF_MSG_DMAE, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
217 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], 222 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
218 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); 223 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
219*/
220 224
221 *wb_comp = 0; 225 *wb_comp = 0;
222 226
223 bnx2x_post_dmae(bp, dmae, port * 8); 227 bnx2x_post_dmae(bp, dmae, (bp->port)*MAX_DMAE_C_PER_PORT);
224 228
225 udelay(5); 229 udelay(5);
226 /* adjust timeout for emulation/FPGA */ 230
227 if (CHIP_REV_IS_SLOW(bp)) 231 while (*wb_comp != DMAE_COMP_VAL) {
228 timeout *= 100; 232 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
229 while (*wb_comp != BNX2X_WB_COMP_VAL) { 233
230/* DP(NETIF_MSG_DMAE, "wb_comp 0x%08x\n", *wb_comp); */ 234 /* adjust delay for emulation/FPGA */
231 udelay(5); 235 if (CHIP_REV_IS_SLOW(bp))
232 if (!timeout) { 236 msleep(100);
237 else
238 udelay(5);
239
240 if (!cnt) {
233 BNX2X_ERR("dmae timeout!\n"); 241 BNX2X_ERR("dmae timeout!\n");
234 break; 242 break;
235 } 243 }
236 timeout--; 244 cnt--;
237 } 245 }
246
247 mutex_unlock(&bp->dmae_mutex);
238} 248}
239 249
240void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) 250void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
241{ 251{
242 struct dmae_command *dmae = &bp->dmae; 252 struct dmae_command *dmae = &bp->init_dmae;
243 int port = bp->port;
244 u32 *wb_comp = bnx2x_sp(bp, wb_comp); 253 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
245 int timeout = 200; 254 int cnt = 200;
255
256 if (!bp->dmae_ready) {
257 u32 *data = bnx2x_sp(bp, wb_data[0]);
258 int i;
259
260 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
261 " using indirect\n", src_addr, len32);
262 for (i = 0; i < len32; i++)
263 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
264 return;
265 }
266
267 mutex_lock(&bp->dmae_mutex);
246 268
247 memset(bnx2x_sp(bp, wb_data[0]), 0, sizeof(u32) * 4); 269 memset(bnx2x_sp(bp, wb_data[0]), 0, sizeof(u32) * 4);
248 memset(dmae, 0, sizeof(struct dmae_command)); 270 memset(dmae, 0, sizeof(struct dmae_command));
@@ -255,7 +277,7 @@ void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
255#else 277#else
256 DMAE_CMD_ENDIANITY_DW_SWAP | 278 DMAE_CMD_ENDIANITY_DW_SWAP |
257#endif 279#endif
258 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0)); 280 (bp->port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
259 dmae->src_addr_lo = src_addr >> 2; 281 dmae->src_addr_lo = src_addr >> 2;
260 dmae->src_addr_hi = 0; 282 dmae->src_addr_hi = 0;
261 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); 283 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
@@ -263,38 +285,64 @@ void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
263 dmae->len = len32; 285 dmae->len = len32;
264 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); 286 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
265 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); 287 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
266 dmae->comp_val = BNX2X_WB_COMP_VAL; 288 dmae->comp_val = DMAE_COMP_VAL;
267 289
268/* 290 DP(BNX2X_MSG_OFF, "dmae: opcode 0x%08x\n"
269 DP(NETIF_MSG_DMAE, "dmae: opcode 0x%08x\n"
270 DP_LEVEL "src_addr [%x:%08x] len [%d *4] " 291 DP_LEVEL "src_addr [%x:%08x] len [%d *4] "
271 "dst_addr [%x:%08x (%08x)]\n" 292 "dst_addr [%x:%08x (%08x)]\n"
272 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n", 293 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
273 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 294 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
274 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, src_addr, 295 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, src_addr,
275 dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val); 296 dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
276*/
277 297
278 *wb_comp = 0; 298 *wb_comp = 0;
279 299
280 bnx2x_post_dmae(bp, dmae, port * 8); 300 bnx2x_post_dmae(bp, dmae, (bp->port)*MAX_DMAE_C_PER_PORT);
281 301
282 udelay(5); 302 udelay(5);
283 while (*wb_comp != BNX2X_WB_COMP_VAL) { 303
284 udelay(5); 304 while (*wb_comp != DMAE_COMP_VAL) {
285 if (!timeout) { 305
306 /* adjust delay for emulation/FPGA */
307 if (CHIP_REV_IS_SLOW(bp))
308 msleep(100);
309 else
310 udelay(5);
311
312 if (!cnt) {
286 BNX2X_ERR("dmae timeout!\n"); 313 BNX2X_ERR("dmae timeout!\n");
287 break; 314 break;
288 } 315 }
289 timeout--; 316 cnt--;
290 } 317 }
291/* 318 DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
292 DP(NETIF_MSG_DMAE, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
293 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1], 319 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
294 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); 320 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
295*/ 321
322 mutex_unlock(&bp->dmae_mutex);
323}
324
325/* used only for slowpath so not inlined */
326static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
327{
328 u32 wb_write[2];
329
330 wb_write[0] = val_hi;
331 wb_write[1] = val_lo;
332 REG_WR_DMAE(bp, reg, wb_write, 2);
296} 333}
297 334
335#ifdef USE_WB_RD
336static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
337{
338 u32 wb_data[2];
339
340 REG_RD_DMAE(bp, reg, wb_data, 2);
341
342 return HILO_U64(wb_data[0], wb_data[1]);
343}
344#endif
345
298static int bnx2x_mc_assert(struct bnx2x *bp) 346static int bnx2x_mc_assert(struct bnx2x *bp)
299{ 347{
300 int i, j, rc = 0; 348 int i, j, rc = 0;
@@ -3438,17 +3486,12 @@ static int bnx2x_int_mem_test(struct bnx2x *bp)
3438 int count, i; 3486 int count, i;
3439 u32 val = 0; 3487 u32 val = 0;
3440 3488
3441 switch (CHIP_REV(bp)) { 3489 if (CHIP_REV_IS_FPGA(bp))
3442 case CHIP_REV_EMUL:
3443 factor = 200;
3444 break;
3445 case CHIP_REV_FPGA:
3446 factor = 120; 3490 factor = 120;
3447 break; 3491 else if (CHIP_REV_IS_EMUL(bp))
3448 default: 3492 factor = 200;
3493 else
3449 factor = 1; 3494 factor = 1;
3450 break;
3451 }
3452 3495
3453 DP(NETIF_MSG_HW, "start part1\n"); 3496 DP(NETIF_MSG_HW, "start part1\n");
3454 3497
@@ -3777,10 +3820,14 @@ static int bnx2x_function_init(struct bnx2x *bp, int mode)
3777 bnx2x_init_block(bp, USDM_COMMON_START, USDM_COMMON_END); 3820 bnx2x_init_block(bp, USDM_COMMON_START, USDM_COMMON_END);
3778 bnx2x_init_block(bp, XSDM_COMMON_START, XSDM_COMMON_END); 3821 bnx2x_init_block(bp, XSDM_COMMON_START, XSDM_COMMON_END);
3779 3822
3780 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE); 3823 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0,
3781 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE); 3824 STORM_INTMEM_SIZE_E1);
3782 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE); 3825 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0,
3783 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0, STORM_INTMEM_SIZE); 3826 STORM_INTMEM_SIZE_E1);
3827 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0,
3828 STORM_INTMEM_SIZE_E1);
3829 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0,
3830 STORM_INTMEM_SIZE_E1);
3784 3831
3785 bnx2x_init_block(bp, TSEM_COMMON_START, TSEM_COMMON_END); 3832 bnx2x_init_block(bp, TSEM_COMMON_START, TSEM_COMMON_END);
3786 bnx2x_init_block(bp, USEM_COMMON_START, USEM_COMMON_END); 3833 bnx2x_init_block(bp, USEM_COMMON_START, USEM_COMMON_END);
@@ -3990,8 +4037,7 @@ static int bnx2x_function_init(struct bnx2x *bp, int mode)
3990#endif 4037#endif
3991 /* Port DQ comes here */ 4038 /* Port DQ comes here */
3992 /* Port BRB1 comes here */ 4039 /* Port BRB1 comes here */
3993 bnx2x_init_block(bp, func ? PRS_PORT1_START : PRS_PORT0_START, 4040 /* Port PRS comes here */
3994 func ? PRS_PORT1_END : PRS_PORT0_END);
3995 /* Port TSDM comes here */ 4041 /* Port TSDM comes here */
3996 /* Port CSDM comes here */ 4042 /* Port CSDM comes here */
3997 /* Port USDM comes here */ 4043 /* Port USDM comes here */
@@ -7264,12 +7310,6 @@ static int __devinit bnx2x_init_board(struct pci_dev *pdev,
7264 7310
7265 bnx2x_get_hwinfo(bp); 7311 bnx2x_get_hwinfo(bp);
7266 7312
7267 if (CHIP_REV(bp) == CHIP_REV_FPGA) {
7268 printk(KERN_ERR PFX "FPGA detected. MCP disabled,"
7269 " will only init first device\n");
7270 onefunc = 1;
7271 nomcp = 1;
7272 }
7273 7313
7274 if (nomcp) { 7314 if (nomcp) {
7275 printk(KERN_ERR PFX "MCP disabled, will only" 7315 printk(KERN_ERR PFX "MCP disabled, will only"
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 14:43:43 -0500