diff options
author | Stephen Hemminger <shemminger@osdl.org> | 2005-06-27 14:33:02 -0400 |
---|---|---|
committer | Jeff Garzik <jgarzik@pobox.com> | 2005-06-27 18:05:05 -0400 |
commit | 955660652af35524974cf4623c02bc99a3785949 (patch) | |
tree | 1cc7d373fe1692be908d62b5145cb249c7c23499 /drivers/net | |
parent | 020f46a39eb7b99a575b9f4d105fce2b142acdf1 (diff) |
[PATCH] skge: whietspace cleanup
Cleanup whitespace around if() and switch() and end of lines
Signed-off-by: Stephen Hemminger <shemminger@osdl.org>
Diffstat (limited to 'drivers/net')
-rw-r--r-- | drivers/net/skge.c | 46 | ||||
-rw-r--r-- | drivers/net/skge.h | 48 |
2 files changed, 47 insertions, 47 deletions
diff --git a/drivers/net/skge.c b/drivers/net/skge.c index 30e8d589d167..2d15ed358a0a 100644 --- a/drivers/net/skge.c +++ b/drivers/net/skge.c | |||
@@ -170,7 +170,7 @@ static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |||
170 | struct skge_port *skge = netdev_priv(dev); | 170 | struct skge_port *skge = netdev_priv(dev); |
171 | struct skge_hw *hw = skge->hw; | 171 | struct skge_hw *hw = skge->hw; |
172 | 172 | ||
173 | if(wol->wolopts != WAKE_MAGIC && wol->wolopts != 0) | 173 | if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0) |
174 | return -EOPNOTSUPP; | 174 | return -EOPNOTSUPP; |
175 | 175 | ||
176 | if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw)) | 176 | if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw)) |
@@ -247,7 +247,7 @@ static u32 skge_modes(const struct skge_hw *hw) | |||
247 | 247 | ||
248 | if (iscopper(hw)) { | 248 | if (iscopper(hw)) { |
249 | modes |= ADVERTISED_TP; | 249 | modes |= ADVERTISED_TP; |
250 | switch(hw->chip_id) { | 250 | switch (hw->chip_id) { |
251 | case CHIP_ID_GENESIS: | 251 | case CHIP_ID_GENESIS: |
252 | modes &= ~(ADVERTISED_100baseT_Full | 252 | modes &= ~(ADVERTISED_100baseT_Full |
253 | | ADVERTISED_100baseT_Half | 253 | | ADVERTISED_100baseT_Half |
@@ -279,7 +279,7 @@ static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |||
279 | if (ecmd->advertising & skge_modes(hw)) | 279 | if (ecmd->advertising & skge_modes(hw)) |
280 | return -EINVAL; | 280 | return -EINVAL; |
281 | } else { | 281 | } else { |
282 | switch(ecmd->speed) { | 282 | switch (ecmd->speed) { |
283 | case SPEED_1000: | 283 | case SPEED_1000: |
284 | if (hw->chip_id == CHIP_ID_YUKON_FE) | 284 | if (hw->chip_id == CHIP_ID_YUKON_FE) |
285 | return -EINVAL; | 285 | return -EINVAL; |
@@ -393,7 +393,7 @@ static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |||
393 | { | 393 | { |
394 | int i; | 394 | int i; |
395 | 395 | ||
396 | switch(stringset) { | 396 | switch (stringset) { |
397 | case ETH_SS_STATS: | 397 | case ETH_SS_STATS: |
398 | for (i = 0; i < ARRAY_SIZE(skge_stats); i++) | 398 | for (i = 0; i < ARRAY_SIZE(skge_stats); i++) |
399 | memcpy(data + i * ETH_GSTRING_LEN, | 399 | memcpy(data + i * ETH_GSTRING_LEN, |
@@ -540,9 +540,9 @@ static int skge_set_pauseparam(struct net_device *dev, | |||
540 | skge->autoneg = ecmd->autoneg; | 540 | skge->autoneg = ecmd->autoneg; |
541 | if (ecmd->rx_pause && ecmd->tx_pause) | 541 | if (ecmd->rx_pause && ecmd->tx_pause) |
542 | skge->flow_control = FLOW_MODE_SYMMETRIC; | 542 | skge->flow_control = FLOW_MODE_SYMMETRIC; |
543 | else if(ecmd->rx_pause && !ecmd->tx_pause) | 543 | else if (ecmd->rx_pause && !ecmd->tx_pause) |
544 | skge->flow_control = FLOW_MODE_REM_SEND; | 544 | skge->flow_control = FLOW_MODE_REM_SEND; |
545 | else if(!ecmd->rx_pause && ecmd->tx_pause) | 545 | else if (!ecmd->rx_pause && ecmd->tx_pause) |
546 | skge->flow_control = FLOW_MODE_LOC_SEND; | 546 | skge->flow_control = FLOW_MODE_LOC_SEND; |
547 | else | 547 | else |
548 | skge->flow_control = FLOW_MODE_NONE; | 548 | skge->flow_control = FLOW_MODE_NONE; |
@@ -730,7 +730,7 @@ static int skge_phys_id(struct net_device *dev, u32 data) | |||
730 | { | 730 | { |
731 | struct skge_port *skge = netdev_priv(dev); | 731 | struct skge_port *skge = netdev_priv(dev); |
732 | 732 | ||
733 | if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ)) | 733 | if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ)) |
734 | data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ); | 734 | data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ); |
735 | 735 | ||
736 | /* start blinking */ | 736 | /* start blinking */ |
@@ -1960,7 +1960,7 @@ static u16 yukon_speed(const struct skge_hw *hw, u16 aux) | |||
1960 | if (hw->chip_id == CHIP_ID_YUKON_FE) | 1960 | if (hw->chip_id == CHIP_ID_YUKON_FE) |
1961 | return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10; | 1961 | return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10; |
1962 | 1962 | ||
1963 | switch(aux & PHY_M_PS_SPEED_MSK) { | 1963 | switch (aux & PHY_M_PS_SPEED_MSK) { |
1964 | case PHY_M_PS_SPEED_1000: | 1964 | case PHY_M_PS_SPEED_1000: |
1965 | return SPEED_1000; | 1965 | return SPEED_1000; |
1966 | case PHY_M_PS_SPEED_100: | 1966 | case PHY_M_PS_SPEED_100: |
@@ -2299,10 +2299,10 @@ static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev) | |||
2299 | 2299 | ||
2300 | local_irq_save(flags); | 2300 | local_irq_save(flags); |
2301 | if (!spin_trylock(&skge->tx_lock)) { | 2301 | if (!spin_trylock(&skge->tx_lock)) { |
2302 | /* Collision - tell upper layer to requeue */ | 2302 | /* Collision - tell upper layer to requeue */ |
2303 | local_irq_restore(flags); | 2303 | local_irq_restore(flags); |
2304 | return NETDEV_TX_LOCKED; | 2304 | return NETDEV_TX_LOCKED; |
2305 | } | 2305 | } |
2306 | 2306 | ||
2307 | if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) { | 2307 | if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) { |
2308 | netif_stop_queue(dev); | 2308 | netif_stop_queue(dev); |
@@ -2439,7 +2439,7 @@ static int skge_change_mtu(struct net_device *dev, int new_mtu) | |||
2439 | { | 2439 | { |
2440 | int err = 0; | 2440 | int err = 0; |
2441 | 2441 | ||
2442 | if(new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) | 2442 | if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) |
2443 | return -EINVAL; | 2443 | return -EINVAL; |
2444 | 2444 | ||
2445 | dev->mtu = new_mtu; | 2445 | dev->mtu = new_mtu; |
@@ -2473,7 +2473,7 @@ static void genesis_set_multicast(struct net_device *dev) | |||
2473 | memset(filter, 0xff, sizeof(filter)); | 2473 | memset(filter, 0xff, sizeof(filter)); |
2474 | else { | 2474 | else { |
2475 | memset(filter, 0, sizeof(filter)); | 2475 | memset(filter, 0, sizeof(filter)); |
2476 | for(i = 0; list && i < count; i++, list = list->next) { | 2476 | for (i = 0; list && i < count; i++, list = list->next) { |
2477 | u32 crc = crc32_le(~0, list->dmi_addr, ETH_ALEN); | 2477 | u32 crc = crc32_le(~0, list->dmi_addr, ETH_ALEN); |
2478 | u8 bit = 63 - (crc & 63); | 2478 | u8 bit = 63 - (crc & 63); |
2479 | 2479 | ||
@@ -2510,7 +2510,7 @@ static void yukon_set_multicast(struct net_device *dev) | |||
2510 | int i; | 2510 | int i; |
2511 | reg |= GM_RXCR_MCF_ENA; | 2511 | reg |= GM_RXCR_MCF_ENA; |
2512 | 2512 | ||
2513 | for(i = 0; list && i < dev->mc_count; i++, list = list->next) { | 2513 | for (i = 0; list && i < dev->mc_count; i++, list = list->next) { |
2514 | u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f; | 2514 | u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f; |
2515 | filter[bit/8] |= 1 << (bit%8); | 2515 | filter[bit/8] |= 1 << (bit%8); |
2516 | } | 2516 | } |
@@ -2657,7 +2657,7 @@ static inline void skge_tx_intr(struct net_device *dev) | |||
2657 | struct skge_element *e; | 2657 | struct skge_element *e; |
2658 | 2658 | ||
2659 | spin_lock(&skge->tx_lock); | 2659 | spin_lock(&skge->tx_lock); |
2660 | for(e = ring->to_clean; e != ring->to_use; e = e->next) { | 2660 | for (e = ring->to_clean; e != ring->to_use; e = e->next) { |
2661 | struct skge_tx_desc *td = e->desc; | 2661 | struct skge_tx_desc *td = e->desc; |
2662 | u32 control; | 2662 | u32 control; |
2663 | 2663 | ||
@@ -2712,7 +2712,7 @@ static void skge_pci_clear(struct skge_hw *hw) | |||
2712 | 2712 | ||
2713 | static void skge_mac_intr(struct skge_hw *hw, int port) | 2713 | static void skge_mac_intr(struct skge_hw *hw, int port) |
2714 | { | 2714 | { |
2715 | if (hw->chip_id == CHIP_ID_GENESIS) | 2715 | if (hw->chip_id == CHIP_ID_GENESIS) |
2716 | genesis_mac_intr(hw, port); | 2716 | genesis_mac_intr(hw, port); |
2717 | else | 2717 | else |
2718 | yukon_mac_intr(hw, port); | 2718 | yukon_mac_intr(hw, port); |
@@ -2847,7 +2847,7 @@ static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs) | |||
2847 | 2847 | ||
2848 | if (status & IS_MAC1) | 2848 | if (status & IS_MAC1) |
2849 | skge_mac_intr(hw, 0); | 2849 | skge_mac_intr(hw, 0); |
2850 | 2850 | ||
2851 | if (status & IS_MAC2) | 2851 | if (status & IS_MAC2) |
2852 | skge_mac_intr(hw, 1); | 2852 | skge_mac_intr(hw, 1); |
2853 | 2853 | ||
@@ -2952,7 +2952,7 @@ static int skge_reset(struct skge_hw *hw) | |||
2952 | hw->phy_type = skge_read8(hw, B2_E_1) & 0xf; | 2952 | hw->phy_type = skge_read8(hw, B2_E_1) & 0xf; |
2953 | hw->pmd_type = skge_read8(hw, B2_PMD_TYP); | 2953 | hw->pmd_type = skge_read8(hw, B2_PMD_TYP); |
2954 | 2954 | ||
2955 | switch(hw->chip_id) { | 2955 | switch (hw->chip_id) { |
2956 | case CHIP_ID_GENESIS: | 2956 | case CHIP_ID_GENESIS: |
2957 | switch (hw->phy_type) { | 2957 | switch (hw->phy_type) { |
2958 | case SK_PHY_XMAC: | 2958 | case SK_PHY_XMAC: |
@@ -3288,7 +3288,7 @@ static void __devexit skge_remove(struct pci_dev *pdev) | |||
3288 | struct skge_hw *hw = pci_get_drvdata(pdev); | 3288 | struct skge_hw *hw = pci_get_drvdata(pdev); |
3289 | struct net_device *dev0, *dev1; | 3289 | struct net_device *dev0, *dev1; |
3290 | 3290 | ||
3291 | if(!hw) | 3291 | if (!hw) |
3292 | return; | 3292 | return; |
3293 | 3293 | ||
3294 | if ((dev1 = hw->dev[1])) | 3294 | if ((dev1 = hw->dev[1])) |
@@ -3316,7 +3316,7 @@ static int skge_suspend(struct pci_dev *pdev, u32 state) | |||
3316 | struct skge_hw *hw = pci_get_drvdata(pdev); | 3316 | struct skge_hw *hw = pci_get_drvdata(pdev); |
3317 | int i, wol = 0; | 3317 | int i, wol = 0; |
3318 | 3318 | ||
3319 | for(i = 0; i < 2; i++) { | 3319 | for (i = 0; i < 2; i++) { |
3320 | struct net_device *dev = hw->dev[i]; | 3320 | struct net_device *dev = hw->dev[i]; |
3321 | 3321 | ||
3322 | if (dev) { | 3322 | if (dev) { |
@@ -3349,11 +3349,11 @@ static int skge_resume(struct pci_dev *pdev) | |||
3349 | 3349 | ||
3350 | skge_reset(hw); | 3350 | skge_reset(hw); |
3351 | 3351 | ||
3352 | for(i = 0; i < 2; i++) { | 3352 | for (i = 0; i < 2; i++) { |
3353 | struct net_device *dev = hw->dev[i]; | 3353 | struct net_device *dev = hw->dev[i]; |
3354 | if (dev) { | 3354 | if (dev) { |
3355 | netif_device_attach(dev); | 3355 | netif_device_attach(dev); |
3356 | if(netif_running(dev)) | 3356 | if (netif_running(dev)) |
3357 | skge_up(dev); | 3357 | skge_up(dev); |
3358 | } | 3358 | } |
3359 | } | 3359 | } |
diff --git a/drivers/net/skge.h b/drivers/net/skge.h index 36c62b68fab4..aad3aece30b5 100644 --- a/drivers/net/skge.h +++ b/drivers/net/skge.h | |||
@@ -537,7 +537,7 @@ enum { | |||
537 | 537 | ||
538 | /* Queue Register Offsets, use Q_ADDR() to access */ | 538 | /* Queue Register Offsets, use Q_ADDR() to access */ |
539 | enum { | 539 | enum { |
540 | B8_Q_REGS = 0x0400, /* base of Queue registers */ | 540 | B8_Q_REGS = 0x0400, /* base of Queue registers */ |
541 | Q_D = 0x00, /* 8*32 bit Current Descriptor */ | 541 | Q_D = 0x00, /* 8*32 bit Current Descriptor */ |
542 | Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */ | 542 | Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */ |
543 | Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */ | 543 | Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */ |
@@ -986,7 +986,7 @@ enum { | |||
986 | LINKLED_BLINK_OFF = 0x10, | 986 | LINKLED_BLINK_OFF = 0x10, |
987 | LINKLED_BLINK_ON = 0x20, | 987 | LINKLED_BLINK_ON = 0x20, |
988 | }; | 988 | }; |
989 | 989 | ||
990 | /* GMAC and GPHY Control Registers (YUKON only) */ | 990 | /* GMAC and GPHY Control Registers (YUKON only) */ |
991 | enum { | 991 | enum { |
992 | GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */ | 992 | GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */ |
@@ -1306,7 +1306,7 @@ enum { | |||
1306 | enum { | 1306 | enum { |
1307 | PHY_ANE_PAR_DF = 1<<4, /* Bit 4: Parallel Detection Fault */ | 1307 | PHY_ANE_PAR_DF = 1<<4, /* Bit 4: Parallel Detection Fault */ |
1308 | 1308 | ||
1309 | PHY_ANE_LP_CAP = 1<<0, /* Bit 0: Link Partner Auto-Neg. Cap. */ | 1309 | PHY_ANE_LP_CAP = 1<<0, /* Bit 0: Link Partner Auto-Neg. Cap. */ |
1310 | }; | 1310 | }; |
1311 | 1311 | ||
1312 | enum { | 1312 | enum { |
@@ -1718,7 +1718,7 @@ enum { | |||
1718 | PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */ | 1718 | PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */ |
1719 | }; | 1719 | }; |
1720 | 1720 | ||
1721 | #define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK) | 1721 | #define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK) |
1722 | 1722 | ||
1723 | enum { | 1723 | enum { |
1724 | PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */ | 1724 | PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */ |
@@ -2105,7 +2105,7 @@ enum { | |||
2105 | GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */ | 2105 | GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */ |
2106 | GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */ | 2106 | GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */ |
2107 | }; | 2107 | }; |
2108 | 2108 | ||
2109 | /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */ | 2109 | /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */ |
2110 | enum { | 2110 | enum { |
2111 | GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */ | 2111 | GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */ |
@@ -2127,7 +2127,7 @@ enum { | |||
2127 | 2127 | ||
2128 | #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100) | 2128 | #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100) |
2129 | #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS) | 2129 | #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS) |
2130 | 2130 | ||
2131 | /* GM_TX_CTRL 16 bit r/w Transmit Control Register */ | 2131 | /* GM_TX_CTRL 16 bit r/w Transmit Control Register */ |
2132 | enum { | 2132 | enum { |
2133 | GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */ | 2133 | GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */ |
@@ -2138,7 +2138,7 @@ enum { | |||
2138 | 2138 | ||
2139 | #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK) | 2139 | #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK) |
2140 | #define TX_COL_DEF 0x04 | 2140 | #define TX_COL_DEF 0x04 |
2141 | 2141 | ||
2142 | /* GM_RX_CTRL 16 bit r/w Receive Control Register */ | 2142 | /* GM_RX_CTRL 16 bit r/w Receive Control Register */ |
2143 | enum { | 2143 | enum { |
2144 | GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */ | 2144 | GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */ |
@@ -2146,7 +2146,7 @@ enum { | |||
2146 | GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */ | 2146 | GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */ |
2147 | GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */ | 2147 | GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */ |
2148 | }; | 2148 | }; |
2149 | 2149 | ||
2150 | /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */ | 2150 | /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */ |
2151 | enum { | 2151 | enum { |
2152 | GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */ | 2152 | GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */ |
@@ -2171,7 +2171,7 @@ enum { | |||
2171 | GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */ | 2171 | GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */ |
2172 | GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */ | 2172 | GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */ |
2173 | }; | 2173 | }; |
2174 | 2174 | ||
2175 | #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK) | 2175 | #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK) |
2176 | #define DATA_BLIND_DEF 0x04 | 2176 | #define DATA_BLIND_DEF 0x04 |
2177 | 2177 | ||
@@ -2186,7 +2186,7 @@ enum { | |||
2186 | GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */ | 2186 | GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */ |
2187 | GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */ | 2187 | GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */ |
2188 | }; | 2188 | }; |
2189 | 2189 | ||
2190 | #define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK) | 2190 | #define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK) |
2191 | #define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK) | 2191 | #define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK) |
2192 | 2192 | ||
@@ -2195,7 +2195,7 @@ enum { | |||
2195 | GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */ | 2195 | GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */ |
2196 | GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */ | 2196 | GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */ |
2197 | }; | 2197 | }; |
2198 | 2198 | ||
2199 | /* Receive Frame Status Encoding */ | 2199 | /* Receive Frame Status Encoding */ |
2200 | enum { | 2200 | enum { |
2201 | GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */ | 2201 | GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */ |
@@ -2217,12 +2217,12 @@ enum { | |||
2217 | /* | 2217 | /* |
2218 | * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR) | 2218 | * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR) |
2219 | */ | 2219 | */ |
2220 | GMR_FS_ANY_ERR = GMR_FS_CRC_ERR | GMR_FS_LONG_ERR | | 2220 | GMR_FS_ANY_ERR = GMR_FS_CRC_ERR | GMR_FS_LONG_ERR | |
2221 | GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC | | 2221 | GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC | |
2222 | GMR_FS_JABBER, | 2222 | GMR_FS_JABBER, |
2223 | /* Rx GMAC FIFO Flush Mask (default) */ | 2223 | /* Rx GMAC FIFO Flush Mask (default) */ |
2224 | RX_FF_FL_DEF_MSK = GMR_FS_CRC_ERR | GMR_FS_RX_FF_OV |GMR_FS_MII_ERR | | 2224 | RX_FF_FL_DEF_MSK = GMR_FS_CRC_ERR | GMR_FS_RX_FF_OV |GMR_FS_MII_ERR | |
2225 | GMR_FS_BAD_FC | GMR_FS_GOOD_FC | GMR_FS_UN_SIZE | | 2225 | GMR_FS_BAD_FC | GMR_FS_GOOD_FC | GMR_FS_UN_SIZE | |
2226 | GMR_FS_JABBER, | 2226 | GMR_FS_JABBER, |
2227 | }; | 2227 | }; |
2228 | 2228 | ||
@@ -2801,7 +2801,7 @@ struct skge_hw { | |||
2801 | 2801 | ||
2802 | u32 ram_size; | 2802 | u32 ram_size; |
2803 | u32 ram_offset; | 2803 | u32 ram_offset; |
2804 | 2804 | ||
2805 | struct tasklet_struct ext_tasklet; | 2805 | struct tasklet_struct ext_tasklet; |
2806 | spinlock_t phy_lock; | 2806 | spinlock_t phy_lock; |
2807 | }; | 2807 | }; |
@@ -2827,7 +2827,7 @@ enum { | |||
2827 | FLOW_MODE_REM_SEND = 2, /* Symmetric or just remote */ | 2827 | FLOW_MODE_REM_SEND = 2, /* Symmetric or just remote */ |
2828 | FLOW_MODE_SYMMETRIC = 3, /* Both stations may send PAUSE */ | 2828 | FLOW_MODE_SYMMETRIC = 3, /* Both stations may send PAUSE */ |
2829 | }; | 2829 | }; |
2830 | 2830 | ||
2831 | struct skge_port { | 2831 | struct skge_port { |
2832 | u32 msg_enable; | 2832 | u32 msg_enable; |
2833 | struct skge_hw *hw; | 2833 | struct skge_hw *hw; |
@@ -2933,24 +2933,24 @@ static inline void skge_xm_write8(const struct skge_hw *hw, int port, int r, u8 | |||
2933 | static inline void skge_xm_outhash(const struct skge_hw *hw, int port, int reg, | 2933 | static inline void skge_xm_outhash(const struct skge_hw *hw, int port, int reg, |
2934 | const u8 *hash) | 2934 | const u8 *hash) |
2935 | { | 2935 | { |
2936 | skge_xm_write16(hw, port, reg, | 2936 | skge_xm_write16(hw, port, reg, |
2937 | (u16)hash[0] | ((u16)hash[1] << 8)); | 2937 | (u16)hash[0] | ((u16)hash[1] << 8)); |
2938 | skge_xm_write16(hw, port, reg+2, | 2938 | skge_xm_write16(hw, port, reg+2, |
2939 | (u16)hash[2] | ((u16)hash[3] << 8)); | 2939 | (u16)hash[2] | ((u16)hash[3] << 8)); |
2940 | skge_xm_write16(hw, port, reg+4, | 2940 | skge_xm_write16(hw, port, reg+4, |
2941 | (u16)hash[4] | ((u16)hash[5] << 8)); | 2941 | (u16)hash[4] | ((u16)hash[5] << 8)); |
2942 | skge_xm_write16(hw, port, reg+6, | 2942 | skge_xm_write16(hw, port, reg+6, |
2943 | (u16)hash[6] | ((u16)hash[7] << 8)); | 2943 | (u16)hash[6] | ((u16)hash[7] << 8)); |
2944 | } | 2944 | } |
2945 | 2945 | ||
2946 | static inline void skge_xm_outaddr(const struct skge_hw *hw, int port, int reg, | 2946 | static inline void skge_xm_outaddr(const struct skge_hw *hw, int port, int reg, |
2947 | const u8 *addr) | 2947 | const u8 *addr) |
2948 | { | 2948 | { |
2949 | skge_xm_write16(hw, port, reg, | 2949 | skge_xm_write16(hw, port, reg, |
2950 | (u16)addr[0] | ((u16)addr[1] << 8)); | 2950 | (u16)addr[0] | ((u16)addr[1] << 8)); |
2951 | skge_xm_write16(hw, port, reg, | 2951 | skge_xm_write16(hw, port, reg, |
2952 | (u16)addr[2] | ((u16)addr[3] << 8)); | 2952 | (u16)addr[2] | ((u16)addr[3] << 8)); |
2953 | skge_xm_write16(hw, port, reg, | 2953 | skge_xm_write16(hw, port, reg, |
2954 | (u16)addr[4] | ((u16)addr[5] << 8)); | 2954 | (u16)addr[4] | ((u16)addr[5] << 8)); |
2955 | } | 2955 | } |
2956 | 2956 | ||
@@ -3001,5 +3001,5 @@ static inline void skge_gm_set_addr(struct skge_hw *hw, int port, int reg, | |||
3001 | skge_gma_write16(hw, port, reg+8, | 3001 | skge_gma_write16(hw, port, reg+8, |
3002 | (u16) addr[4] | ((u16) addr[5] << 8)); | 3002 | (u16) addr[4] | ((u16) addr[5] << 8)); |
3003 | } | 3003 | } |
3004 | 3004 | ||
3005 | #endif | 3005 | #endif |