aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net
diff options
context:
space:
mode:
authorPJ Waskiewicz <peter.p.waskiewicz.jr@intel.com>2009-02-27 10:44:30 -0500
committerDavid S. Miller <davem@davemloft.net>2009-03-01 03:24:33 -0500
commit11afc1b1fd802c11dc0fa986c210602c177f1e21 (patch)
tree16f46e5acf0aa7b5ec8b1a0cc07a0c89ac002642 /drivers/net
parent8010dc306ba39a8cdb3993d1e809fcb7dfdf089a (diff)
ixgbe: Add hardware specific initialization code for 82599 devices
This patch adds the hardware initialization code specific to 82599. This is similar to the 82598 hardware initialization code. It also includes all changes to the existing hardware init code to support 82599. Signed-off-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/ixgbe/ixgbe_82598.c7
-rw-r--r--drivers/net/ixgbe/ixgbe_82599.c1277
-rw-r--r--drivers/net/ixgbe/ixgbe_common.c319
-rw-r--r--drivers/net/ixgbe/ixgbe_common.h10
-rw-r--r--drivers/net/ixgbe/ixgbe_ethtool.c2
-rw-r--r--drivers/net/ixgbe/ixgbe_phy.c590
-rw-r--r--drivers/net/ixgbe/ixgbe_phy.h16
-rw-r--r--drivers/net/ixgbe/ixgbe_type.h766
8 files changed, 2928 insertions, 59 deletions
diff --git a/drivers/net/ixgbe/ixgbe_82598.c b/drivers/net/ixgbe/ixgbe_82598.c
index 51dba1c78e1e..623737fb719b 100644
--- a/drivers/net/ixgbe/ixgbe_82598.c
+++ b/drivers/net/ixgbe/ixgbe_82598.c
@@ -1046,9 +1046,9 @@ out:
1046 * 1046 *
1047 * Determines physical layer capabilities of the current configuration. 1047 * Determines physical layer capabilities of the current configuration.
1048 **/ 1048 **/
1049static s32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw) 1049static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1050{ 1050{
1051 s32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1051 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1052 1052
1053 switch (hw->device_id) { 1053 switch (hw->device_id) {
1054 case IXGBE_DEV_ID_82598: 1054 case IXGBE_DEV_ID_82598:
@@ -1111,8 +1111,11 @@ static struct ixgbe_mac_operations mac_ops_82598 = {
1111 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, 1111 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
1112 .get_media_type = &ixgbe_get_media_type_82598, 1112 .get_media_type = &ixgbe_get_media_type_82598,
1113 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598, 1113 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
1114 .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
1114 .get_mac_addr = &ixgbe_get_mac_addr_generic, 1115 .get_mac_addr = &ixgbe_get_mac_addr_generic,
1115 .stop_adapter = &ixgbe_stop_adapter_generic, 1116 .stop_adapter = &ixgbe_stop_adapter_generic,
1117 .get_bus_info = &ixgbe_get_bus_info_generic,
1118 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
1116 .read_analog_reg8 = &ixgbe_read_analog_reg8_82598, 1119 .read_analog_reg8 = &ixgbe_read_analog_reg8_82598,
1117 .write_analog_reg8 = &ixgbe_write_analog_reg8_82598, 1120 .write_analog_reg8 = &ixgbe_write_analog_reg8_82598,
1118 .setup_link = &ixgbe_setup_mac_link_82598, 1121 .setup_link = &ixgbe_setup_mac_link_82598,
diff --git a/drivers/net/ixgbe/ixgbe_82599.c b/drivers/net/ixgbe/ixgbe_82599.c
new file mode 100644
index 000000000000..cc3bfa195b78
--- /dev/null
+++ b/drivers/net/ixgbe/ixgbe_82599.c
@@ -0,0 +1,1277 @@
1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe.h"
33#include "ixgbe_phy.h"
34
35#define IXGBE_82599_MAX_TX_QUEUES 128
36#define IXGBE_82599_MAX_RX_QUEUES 128
37#define IXGBE_82599_RAR_ENTRIES 128
38#define IXGBE_82599_MC_TBL_SIZE 128
39#define IXGBE_82599_VFT_TBL_SIZE 128
40
41s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
43 bool *autoneg);
44enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw);
45s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw);
46s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
47 ixgbe_link_speed speed, bool autoneg,
48 bool autoneg_wait_to_complete);
49s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw);
50s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
51 ixgbe_link_speed *speed,
52 bool *link_up, bool link_up_wait_to_complete);
53s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
54 ixgbe_link_speed speed,
55 bool autoneg,
56 bool autoneg_wait_to_complete);
57static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
58 ixgbe_link_speed *speed,
59 bool *autoneg);
60static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw);
61static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
62 ixgbe_link_speed speed,
63 bool autoneg,
64 bool autoneg_wait_to_complete);
65s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw);
66s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
67s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
68s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan,
69 u32 vind, bool vlan_on);
70s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw);
71s32 ixgbe_blink_led_stop_82599(struct ixgbe_hw *hw, u32 index);
72s32 ixgbe_blink_led_start_82599(struct ixgbe_hw *hw, u32 index);
73s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw);
74s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);
75s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
76s32 ixgbe_start_hw_rev_0_82599(struct ixgbe_hw *hw);
77s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw);
78s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw);
79u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
80
81void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
82{
83 struct ixgbe_mac_info *mac = &hw->mac;
84 if (hw->phy.multispeed_fiber) {
85 /* Set up dual speed SFP+ support */
86 mac->ops.setup_link =
87 &ixgbe_setup_mac_link_multispeed_fiber;
88 mac->ops.setup_link_speed =
89 &ixgbe_setup_mac_link_speed_multispeed_fiber;
90 } else {
91 mac->ops.setup_link =
92 &ixgbe_setup_mac_link_82599;
93 mac->ops.setup_link_speed =
94 &ixgbe_setup_mac_link_speed_82599;
95 }
96}
97
98s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
99{
100 s32 ret_val = 0;
101 u16 list_offset, data_offset, data_value;
102
103 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
104 ixgbe_init_mac_link_ops_82599(hw);
105 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
106 &data_offset);
107
108 if (ret_val != 0)
109 goto setup_sfp_out;
110
111 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
112 while (data_value != 0xffff) {
113 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
114 IXGBE_WRITE_FLUSH(hw);
115 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
116 }
117 /* Now restart DSP */
118 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000102);
119 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, 0x00000b1d);
120 IXGBE_WRITE_FLUSH(hw);
121 }
122
123setup_sfp_out:
124 return ret_val;
125}
126
127/**
128 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
129 * @hw: pointer to hardware structure
130 *
131 * Read PCIe configuration space, and get the MSI-X vector count from
132 * the capabilities table.
133 **/
134u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
135{
136 struct ixgbe_adapter *adapter = hw->back;
137 u16 msix_count;
138 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
139 &msix_count);
140 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
141
142 /* MSI-X count is zero-based in HW, so increment to give proper value */
143 msix_count++;
144
145 return msix_count;
146}
147
148static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
149{
150 struct ixgbe_mac_info *mac = &hw->mac;
151 struct ixgbe_phy_info *phy = &hw->phy;
152 s32 ret_val;
153
154 /* Set the bus information prior to PHY identification */
155 mac->ops.get_bus_info(hw);
156
157 /* Call PHY identify routine to get the Cu or SFI phy type */
158 ret_val = phy->ops.identify(hw);
159
160 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
161 goto get_invariants_out;
162
163 ixgbe_init_mac_link_ops_82599(hw);
164
165 /* Setup SFP module if there is one present. */
166 ret_val = mac->ops.setup_sfp(hw);
167
168 /* If copper media, overwrite with copper function pointers */
169 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
170 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
171 mac->ops.setup_link_speed =
172 &ixgbe_setup_copper_link_speed_82599;
173 mac->ops.get_link_capabilities =
174 &ixgbe_get_copper_link_capabilities_82599;
175 }
176
177 /* PHY Init */
178 switch (hw->phy.type) {
179 case ixgbe_phy_tn:
180 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
181 phy->ops.get_firmware_version =
182 &ixgbe_get_phy_firmware_version_tnx;
183 break;
184 default:
185 break;
186 }
187
188 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
189 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
190 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
191 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
192 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
193 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
194
195get_invariants_out:
196 return ret_val;
197}
198
199/**
200 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
201 * @hw: pointer to hardware structure
202 * @speed: pointer to link speed
203 * @negotiation: true when autoneg or autotry is enabled
204 *
205 * Determines the link capabilities by reading the AUTOC register.
206 **/
207s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
208 ixgbe_link_speed *speed,
209 bool *negotiation)
210{
211 s32 status = 0;
212
213 switch (hw->mac.orig_autoc & IXGBE_AUTOC_LMS_MASK) {
214 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
215 *speed = IXGBE_LINK_SPEED_1GB_FULL;
216 *negotiation = false;
217 break;
218
219 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
220 *speed = IXGBE_LINK_SPEED_10GB_FULL;
221 *negotiation = false;
222 break;
223
224 case IXGBE_AUTOC_LMS_1G_AN:
225 *speed = IXGBE_LINK_SPEED_1GB_FULL;
226 *negotiation = true;
227 break;
228
229 case IXGBE_AUTOC_LMS_10G_SERIAL:
230 *speed = IXGBE_LINK_SPEED_10GB_FULL;
231 *negotiation = false;
232 break;
233
234 case IXGBE_AUTOC_LMS_KX4_KX_KR:
235 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
236 *speed = IXGBE_LINK_SPEED_UNKNOWN;
237 if (hw->mac.orig_autoc & IXGBE_AUTOC_KR_SUPP)
238 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
239 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX4_SUPP)
240 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
241 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX_SUPP)
242 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
243 *negotiation = true;
244 break;
245
246 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
247 *speed = IXGBE_LINK_SPEED_100_FULL;
248 if (hw->mac.orig_autoc & IXGBE_AUTOC_KR_SUPP)
249 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
250 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX4_SUPP)
251 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
252 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX_SUPP)
253 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
254 *negotiation = true;
255 break;
256
257 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
258 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
259 *negotiation = false;
260 break;
261
262 default:
263 status = IXGBE_ERR_LINK_SETUP;
264 goto out;
265 break;
266 }
267
268 if (hw->phy.multispeed_fiber) {
269 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
270 IXGBE_LINK_SPEED_1GB_FULL;
271 *negotiation = true;
272 }
273
274out:
275 return status;
276}
277
278/**
279 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
280 * @hw: pointer to hardware structure
281 * @speed: pointer to link speed
282 * @autoneg: boolean auto-negotiation value
283 *
284 * Determines the link capabilities by reading the AUTOC register.
285 **/
286static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
287 ixgbe_link_speed *speed,
288 bool *autoneg)
289{
290 s32 status = IXGBE_ERR_LINK_SETUP;
291 u16 speed_ability;
292
293 *speed = 0;
294 *autoneg = true;
295
296 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
297 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
298 &speed_ability);
299
300 if (status == 0) {
301 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
302 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
303 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
304 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
305 }
306
307 return status;
308}
309
310/**
311 * ixgbe_get_media_type_82599 - Get media type
312 * @hw: pointer to hardware structure
313 *
314 * Returns the media type (fiber, copper, backplane)
315 **/
316enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
317{
318 enum ixgbe_media_type media_type;
319
320 /* Detect if there is a copper PHY attached. */
321 if (hw->phy.type == ixgbe_phy_cu_unknown ||
322 hw->phy.type == ixgbe_phy_tn) {
323 media_type = ixgbe_media_type_copper;
324 goto out;
325 }
326
327 switch (hw->device_id) {
328 case IXGBE_DEV_ID_82599:
329 case IXGBE_DEV_ID_82599_KX4:
330 /* Default device ID is mezzanine card KX/KX4 */
331 media_type = ixgbe_media_type_backplane;
332 break;
333 case IXGBE_DEV_ID_82599_SFP:
334 media_type = ixgbe_media_type_fiber;
335 break;
336 default:
337 media_type = ixgbe_media_type_unknown;
338 break;
339 }
340out:
341 return media_type;
342}
343
344/**
345 * ixgbe_setup_mac_link_82599 - Setup MAC link settings
346 * @hw: pointer to hardware structure
347 *
348 * Configures link settings based on values in the ixgbe_hw struct.
349 * Restarts the link. Performs autonegotiation if needed.
350 **/
351s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw)
352{
353 u32 autoc_reg;
354 u32 links_reg;
355 u32 i;
356 s32 status = 0;
357
358 /* Restart link */
359 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
360 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
361 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
362
363 /* Only poll for autoneg to complete if specified to do so */
364 if (hw->phy.autoneg_wait_to_complete) {
365 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
366 IXGBE_AUTOC_LMS_KX4_KX_KR ||
367 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
368 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
369 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
370 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
371 links_reg = 0; /* Just in case Autoneg time = 0 */
372 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
373 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
374 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
375 break;
376 msleep(100);
377 }
378 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
379 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
380 hw_dbg(hw, "Autoneg did not complete.\n");
381 }
382 }
383 }
384
385 /* Set up flow control */
386 status = ixgbe_setup_fc_generic(hw, 0);
387
388 /* Add delay to filter out noises during initial link setup */
389 msleep(50);
390
391 return status;
392}
393
394/**
395 * ixgbe_setup_mac_link_multispeed_fiber - Setup MAC link settings
396 * @hw: pointer to hardware structure
397 *
398 * Configures link settings based on values in the ixgbe_hw struct.
399 * Restarts the link for multi-speed fiber at 1G speed, if link
400 * fails at 10G.
401 * Performs autonegotiation if needed.
402 **/
403s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw)
404{
405 s32 status = 0;
406 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_82599_AUTONEG;
407 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw,
408 link_speed,
409 true, true);
410 return status;
411}
412
413/**
414 * ixgbe_setup_mac_link_speed_multispeed_fiber - Set MAC link speed
415 * @hw: pointer to hardware structure
416 * @speed: new link speed
417 * @autoneg: true if autonegotiation enabled
418 * @autoneg_wait_to_complete: true when waiting for completion is needed
419 *
420 * Set the link speed in the AUTOC register and restarts link.
421 **/
422s32 ixgbe_setup_mac_link_speed_multispeed_fiber(struct ixgbe_hw *hw,
423 ixgbe_link_speed speed,
424 bool autoneg,
425 bool autoneg_wait_to_complete)
426{
427 s32 status = 0;
428 ixgbe_link_speed phy_link_speed;
429 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
430 u32 speedcnt = 0;
431 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
432 bool link_up = false;
433 bool negotiation;
434
435 /* Mask off requested but non-supported speeds */
436 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
437 speed &= phy_link_speed;
438
439 /*
440 * Try each speed one by one, highest priority first. We do this in
441 * software because 10gb fiber doesn't support speed autonegotiation.
442 */
443 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
444 speedcnt++;
445 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
446
447 /* Set hardware SDP's */
448 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
449 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
450
451 ixgbe_setup_mac_link_speed_82599(hw,
452 IXGBE_LINK_SPEED_10GB_FULL,
453 autoneg,
454 autoneg_wait_to_complete);
455
456 msleep(50);
457
458 /* If we have link, just jump out */
459 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
460 if (link_up)
461 goto out;
462 }
463
464 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
465 speedcnt++;
466 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
467 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
468
469 /* Set hardware SDP's */
470 esdp_reg &= ~IXGBE_ESDP_SDP5;
471 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
472 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
473
474 ixgbe_setup_mac_link_speed_82599(
475 hw, IXGBE_LINK_SPEED_1GB_FULL, autoneg,
476 autoneg_wait_to_complete);
477
478 msleep(50);
479
480 /* If we have link, just jump out */
481 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
482 if (link_up)
483 goto out;
484 }
485
486 /*
487 * We didn't get link. Configure back to the highest speed we tried,
488 * (if there was more than one). We call ourselves back with just the
489 * single highest speed that the user requested.
490 */
491 if (speedcnt > 1)
492 status = ixgbe_setup_mac_link_speed_multispeed_fiber(hw,
493 highest_link_speed,
494 autoneg,
495 autoneg_wait_to_complete);
496
497out:
498 return status;
499}
500
501/**
502 * ixgbe_check_mac_link_82599 - Determine link and speed status
503 * @hw: pointer to hardware structure
504 * @speed: pointer to link speed
505 * @link_up: true when link is up
506 * @link_up_wait_to_complete: bool used to wait for link up or not
507 *
508 * Reads the links register to determine if link is up and the current speed
509 **/
510s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
511 bool *link_up, bool link_up_wait_to_complete)
512{
513 u32 links_reg;
514 u32 i;
515
516 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
517 if (link_up_wait_to_complete) {
518 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
519 if (links_reg & IXGBE_LINKS_UP) {
520 *link_up = true;
521 break;
522 } else {
523 *link_up = false;
524 }
525 msleep(100);
526 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
527 }
528 } else {
529 if (links_reg & IXGBE_LINKS_UP)
530 *link_up = true;
531 else
532 *link_up = false;
533 }
534
535 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
536 IXGBE_LINKS_SPEED_10G_82599)
537 *speed = IXGBE_LINK_SPEED_10GB_FULL;
538 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
539 IXGBE_LINKS_SPEED_1G_82599)
540 *speed = IXGBE_LINK_SPEED_1GB_FULL;
541 else
542 *speed = IXGBE_LINK_SPEED_100_FULL;
543
544
545 return 0;
546}
547
548/**
549 * ixgbe_setup_mac_link_speed_82599 - Set MAC link speed
550 * @hw: pointer to hardware structure
551 * @speed: new link speed
552 * @autoneg: true if autonegotiation enabled
553 * @autoneg_wait_to_complete: true when waiting for completion is needed
554 *
555 * Set the link speed in the AUTOC register and restarts link.
556 **/
557s32 ixgbe_setup_mac_link_speed_82599(struct ixgbe_hw *hw,
558 ixgbe_link_speed speed, bool autoneg,
559 bool autoneg_wait_to_complete)
560{
561 s32 status = 0;
562 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
563 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
564 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
565 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
566 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
567 u32 links_reg;
568 u32 i;
569 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
570
571 /* Check to see if speed passed in is supported. */
572 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
573 speed &= link_capabilities;
574
575 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
576 status = IXGBE_ERR_LINK_SETUP;
577 } else if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
578 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
579 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
580 /* Set KX4/KX/KR support according to speed requested */
581 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
582 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
583 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX4_SUPP)
584 autoc |= IXGBE_AUTOC_KX4_SUPP;
585 if (hw->mac.orig_autoc & IXGBE_AUTOC_KR_SUPP)
586 autoc |= IXGBE_AUTOC_KR_SUPP;
587 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
588 autoc |= IXGBE_AUTOC_KX_SUPP;
589 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
590 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
591 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
592 /* Switch from 1G SFI to 10G SFI if requested */
593 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
594 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
595 autoc &= ~IXGBE_AUTOC_LMS_MASK;
596 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
597 }
598 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
599 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
600 /* Switch from 10G SFI to 1G SFI if requested */
601 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
602 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
603 autoc &= ~IXGBE_AUTOC_LMS_MASK;
604 if (autoneg)
605 autoc |= IXGBE_AUTOC_LMS_1G_AN;
606 else
607 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
608 }
609 }
610
611 if (status == 0) {
612 /* Restart link */
613 autoc |= IXGBE_AUTOC_AN_RESTART;
614 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
615
616 /* Only poll for autoneg to complete if specified to do so */
617 if (autoneg_wait_to_complete) {
618 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
619 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
620 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
621 links_reg = 0; /*Just in case Autoneg time=0*/
622 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
623 links_reg =
624 IXGBE_READ_REG(hw, IXGBE_LINKS);
625 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
626 break;
627 msleep(100);
628 }
629 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
630 status =
631 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
632 hw_dbg(hw, "Autoneg did not "
633 "complete.\n");
634 }
635 }
636 }
637
638 /* Set up flow control */
639 status = ixgbe_setup_fc_generic(hw, 0);
640
641 /* Add delay to filter out noises during initial link setup */
642 msleep(50);
643 }
644
645 return status;
646}
647
648/**
649 * ixgbe_setup_copper_link_82599 - Setup copper link settings
650 * @hw: pointer to hardware structure
651 *
652 * Restarts the link on PHY and then MAC. Performs autonegotiation if needed.
653 **/
654static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw)
655{
656 s32 status;
657
658 /* Restart autonegotiation on PHY */
659 status = hw->phy.ops.setup_link(hw);
660
661 /* Set up MAC */
662 ixgbe_setup_mac_link_82599(hw);
663
664 return status;
665}
666
667/**
668 * ixgbe_setup_copper_link_speed_82599 - Set the PHY autoneg advertised field
669 * @hw: pointer to hardware structure
670 * @speed: new link speed
671 * @autoneg: true if autonegotiation enabled
672 * @autoneg_wait_to_complete: true if waiting is needed to complete
673 *
674 * Restarts link on PHY and MAC based on settings passed in.
675 **/
676static s32 ixgbe_setup_copper_link_speed_82599(struct ixgbe_hw *hw,
677 ixgbe_link_speed speed,
678 bool autoneg,
679 bool autoneg_wait_to_complete)
680{
681 s32 status;
682
683 /* Setup the PHY according to input speed */
684 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
685 autoneg_wait_to_complete);
686 /* Set up MAC */
687 ixgbe_setup_mac_link_82599(hw);
688
689 return status;
690}
691
692/**
693 * ixgbe_reset_hw_82599 - Perform hardware reset
694 * @hw: pointer to hardware structure
695 *
696 * Resets the hardware by resetting the transmit and receive units, masks
697 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
698 * reset.
699 **/
700s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
701{
702 s32 status = 0;
703 u32 ctrl, ctrl_ext;
704 u32 i;
705 u32 autoc;
706 u32 autoc2;
707
708 /* Call adapter stop to disable tx/rx and clear interrupts */
709 hw->mac.ops.stop_adapter(hw);
710
711 /* Reset PHY */
712 hw->phy.ops.reset(hw);
713
714 /*
715 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
716 * access and verify no pending requests before reset
717 */
718 if (ixgbe_disable_pcie_master(hw) != 0) {
719 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
720 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
721 }
722
723 /*
724 * Issue global reset to the MAC. This needs to be a SW reset.
725 * If link reset is used, it might reset the MAC when mng is using it
726 */
727 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
728 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
729 IXGBE_WRITE_FLUSH(hw);
730
731 /* Poll for reset bit to self-clear indicating reset is complete */
732 for (i = 0; i < 10; i++) {
733 udelay(1);
734 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
735 if (!(ctrl & IXGBE_CTRL_RST))
736 break;
737 }
738 if (ctrl & IXGBE_CTRL_RST) {
739 status = IXGBE_ERR_RESET_FAILED;
740 hw_dbg(hw, "Reset polling failed to complete.\n");
741 }
742 /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
743 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
744 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
745 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
746
747 msleep(50);
748
749
750
751 /*
752 * Store the original AUTOC/AUTOC2 values if they have not been
753 * stored off yet. Otherwise restore the stored original
754 * values since the reset operation sets back to defaults.
755 */
756 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
757 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
758 if (hw->mac.orig_link_settings_stored == false) {
759 hw->mac.orig_autoc = autoc;
760 hw->mac.orig_autoc2 = autoc2;
761 hw->mac.orig_link_settings_stored = true;
762 } else {
763 if (autoc != hw->mac.orig_autoc)
764 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
765 IXGBE_AUTOC_AN_RESTART));
766
767 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
768 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
769 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
770 autoc2 |= (hw->mac.orig_autoc2 &
771 IXGBE_AUTOC2_UPPER_MASK);
772 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
773 }
774 }
775
776 /* Store the permanent mac address */
777 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
778
779 return status;
780}
781
782/**
783 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
784 * @hw: pointer to hardware struct
785 * @rar: receive address register index to disassociate
786 * @vmdq: VMDq pool index to remove from the rar
787 **/
788s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
789{
790 u32 mpsar_lo, mpsar_hi;
791 u32 rar_entries = hw->mac.num_rar_entries;
792
793 if (rar < rar_entries) {
794 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
795 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
796
797 if (!mpsar_lo && !mpsar_hi)
798 goto done;
799
800 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
801 if (mpsar_lo) {
802 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
803 mpsar_lo = 0;
804 }
805 if (mpsar_hi) {
806 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
807 mpsar_hi = 0;
808 }
809 } else if (vmdq < 32) {
810 mpsar_lo &= ~(1 << vmdq);
811 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
812 } else {
813 mpsar_hi &= ~(1 << (vmdq - 32));
814 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
815 }
816
817 /* was that the last pool using this rar? */
818 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
819 hw->mac.ops.clear_rar(hw, rar);
820 } else {
821 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
822 }
823
824done:
825 return 0;
826}
827
828/**
829 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
830 * @hw: pointer to hardware struct
831 * @rar: receive address register index to associate with a VMDq index
832 * @vmdq: VMDq pool index
833 **/
834s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
835{
836 u32 mpsar;
837 u32 rar_entries = hw->mac.num_rar_entries;
838
839 if (rar < rar_entries) {
840 if (vmdq < 32) {
841 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
842 mpsar |= 1 << vmdq;
843 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
844 } else {
845 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
846 mpsar |= 1 << (vmdq - 32);
847 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
848 }
849 } else {
850 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
851 }
852 return 0;
853}
854
855/**
856 * ixgbe_set_vfta_82599 - Set VLAN filter table
857 * @hw: pointer to hardware structure
858 * @vlan: VLAN id to write to VLAN filter
859 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
860 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
861 *
862 * Turn on/off specified VLAN in the VLAN filter table.
863 **/
864s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
865 bool vlan_on)
866{
867 u32 regindex;
868 u32 bitindex;
869 u32 bits;
870 u32 first_empty_slot;
871
872 if (vlan > 4095)
873 return IXGBE_ERR_PARAM;
874
875 /*
876 * this is a 2 part operation - first the VFTA, then the
877 * VLVF and VLVFB if vind is set
878 */
879
880 /* Part 1
881 * The VFTA is a bitstring made up of 128 32-bit registers
882 * that enable the particular VLAN id, much like the MTA:
883 * bits[11-5]: which register
884 * bits[4-0]: which bit in the register
885 */
886 regindex = (vlan >> 5) & 0x7F;
887 bitindex = vlan & 0x1F;
888 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
889 if (vlan_on)
890 bits |= (1 << bitindex);
891 else
892 bits &= ~(1 << bitindex);
893 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
894
895
896 /* Part 2
897 * If the vind is set
898 * Either vlan_on
899 * make sure the vlan is in VLVF
900 * set the vind bit in the matching VLVFB
901 * Or !vlan_on
902 * clear the pool bit and possibly the vind
903 */
904 if (vind) {
905 /* find the vlanid or the first empty slot */
906 first_empty_slot = 0;
907
908 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
909 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
910 if (!bits && !first_empty_slot)
911 first_empty_slot = regindex;
912 else if ((bits & 0x0FFF) == vlan)
913 break;
914 }
915
916 if (regindex >= IXGBE_VLVF_ENTRIES) {
917 if (first_empty_slot)
918 regindex = first_empty_slot;
919 else {
920 hw_dbg(hw, "No space in VLVF.\n");
921 goto out;
922 }
923 }
924
925 if (vlan_on) {
926 /* set the pool bit */
927 if (vind < 32) {
928 bits = IXGBE_READ_REG(hw,
929 IXGBE_VLVFB(regindex * 2));
930 bits |= (1 << vind);
931 IXGBE_WRITE_REG(hw,
932 IXGBE_VLVFB(regindex * 2), bits);
933 } else {
934 bits = IXGBE_READ_REG(hw,
935 IXGBE_VLVFB((regindex * 2) + 1));
936 bits |= (1 << vind);
937 IXGBE_WRITE_REG(hw,
938 IXGBE_VLVFB((regindex * 2) + 1), bits);
939 }
940 } else {
941 /* clear the pool bit */
942 if (vind < 32) {
943 bits = IXGBE_READ_REG(hw,
944 IXGBE_VLVFB(regindex * 2));
945 bits &= ~(1 << vind);
946 IXGBE_WRITE_REG(hw,
947 IXGBE_VLVFB(regindex * 2), bits);
948 bits |= IXGBE_READ_REG(hw,
949 IXGBE_VLVFB((regindex * 2) + 1));
950 } else {
951 bits = IXGBE_READ_REG(hw,
952 IXGBE_VLVFB((regindex * 2) + 1));
953 bits &= ~(1 << vind);
954 IXGBE_WRITE_REG(hw,
955 IXGBE_VLVFB((regindex * 2) + 1), bits);
956 bits |= IXGBE_READ_REG(hw,
957 IXGBE_VLVFB(regindex * 2));
958 }
959 }
960
961 if (bits)
962 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex),
963 (IXGBE_VLVF_VIEN | vlan));
964 else
965 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
966 }
967
968out:
969 return 0;
970}
971
972/**
973 * ixgbe_clear_vfta_82599 - Clear VLAN filter table
974 * @hw: pointer to hardware structure
975 *
976 * Clears the VLAN filer table, and the VMDq index associated with the filter
977 **/
978s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
979{
980 u32 offset;
981
982 for (offset = 0; offset < hw->mac.vft_size; offset++)
983 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
984
985 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
986 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
987 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
988 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
989 }
990
991 return 0;
992}
993
994/**
995 * ixgbe_blink_led_start_82599 - Blink LED based on index.
996 * @hw: pointer to hardware structure
997 * @index: led number to blink
998 **/
999s32 ixgbe_blink_led_start_82599(struct ixgbe_hw *hw, u32 index)
1000{
1001 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1002
1003 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1004 led_reg |= IXGBE_LED_BLINK(index);
1005 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1006 IXGBE_WRITE_FLUSH(hw);
1007
1008 return 0;
1009}
1010
1011/**
1012 * ixgbe_blink_led_stop_82599 - Stop blinking LED based on index.
1013 * @hw: pointer to hardware structure
1014 * @index: led number to stop blinking
1015 **/
1016s32 ixgbe_blink_led_stop_82599(struct ixgbe_hw *hw, u32 index)
1017{
1018 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1019
1020 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1021 led_reg &= ~IXGBE_LED_BLINK(index);
1022 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1023 IXGBE_WRITE_FLUSH(hw);
1024
1025 return 0;
1026}
1027
1028/**
1029 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1030 * @hw: pointer to hardware structure
1031 **/
1032s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
1033{
1034 int i;
1035 hw_dbg(hw, " Clearing UTA\n");
1036
1037 for (i = 0; i < 128; i++)
1038 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1039
1040 return 0;
1041}
1042
1043/**
1044 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1045 * @hw: pointer to hardware structure
1046 * @reg: analog register to read
1047 * @val: read value
1048 *
1049 * Performs read operation to Omer analog register specified.
1050 **/
1051s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1052{
1053 u32 core_ctl;
1054
1055 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1056 (reg << 8));
1057 IXGBE_WRITE_FLUSH(hw);
1058 udelay(10);
1059 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1060 *val = (u8)core_ctl;
1061
1062 return 0;
1063}
1064
1065/**
1066 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1067 * @hw: pointer to hardware structure
1068 * @reg: atlas register to write
1069 * @val: value to write
1070 *
1071 * Performs write operation to Omer analog register specified.
1072 **/
1073s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1074{
1075 u32 core_ctl;
1076
1077 core_ctl = (reg << 8) | val;
1078 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1079 IXGBE_WRITE_FLUSH(hw);
1080 udelay(10);
1081
1082 return 0;
1083}
1084
1085/**
1086 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1087 * @hw: pointer to hardware structure
1088 *
1089 * Starts the hardware using the generic start_hw function.
1090 * Then performs device-specific:
1091 * Clears the rate limiter registers.
1092 **/
1093s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1094{
1095 u32 q_num;
1096
1097 ixgbe_start_hw_generic(hw);
1098
1099 /* Clear the rate limiters */
1100 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
1101 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
1102 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
1103 }
1104 IXGBE_WRITE_FLUSH(hw);
1105
1106 return 0;
1107}
1108
1109/**
1110 * ixgbe_identify_phy_82599 - Get physical layer module
1111 * @hw: pointer to hardware structure
1112 *
1113 * Determines the physical layer module found on the current adapter.
1114 **/
1115s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1116{
1117 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1118 status = ixgbe_identify_phy_generic(hw);
1119 if (status != 0)
1120 status = ixgbe_identify_sfp_module_generic(hw);
1121 return status;
1122}
1123
1124/**
1125 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1126 * @hw: pointer to hardware structure
1127 *
1128 * Determines physical layer capabilities of the current configuration.
1129 **/
1130u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1131{
1132 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1133
1134 switch (hw->device_id) {
1135 case IXGBE_DEV_ID_82599:
1136 case IXGBE_DEV_ID_82599_KX4:
1137 /* Default device ID is mezzanine card KX/KX4 */
1138 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
1139 IXGBE_PHYSICAL_LAYER_1000BASE_KX);
1140 break;
1141 case IXGBE_DEV_ID_82599_SFP:
1142 hw->phy.ops.identify_sfp(hw);
1143
1144 switch (hw->phy.sfp_type) {
1145 case ixgbe_sfp_type_da_cu:
1146 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1147 break;
1148 case ixgbe_sfp_type_sr:
1149 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1150 break;
1151 case ixgbe_sfp_type_lr:
1152 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1153 break;
1154 default:
1155 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1156 break;
1157 }
1158 break;
1159 default:
1160 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1161 break;
1162 }
1163
1164 return physical_layer;
1165}
1166
1167/**
1168 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1169 * @hw: pointer to hardware structure
1170 * @regval: register value to write to RXCTRL
1171 *
1172 * Enables the Rx DMA unit for 82599
1173 **/
1174s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1175{
1176#define IXGBE_MAX_SECRX_POLL 30
1177 int i;
1178 int secrxreg;
1179
1180 /*
1181 * Workaround for 82599 silicon errata when enabling the Rx datapath.
1182 * If traffic is incoming before we enable the Rx unit, it could hang
1183 * the Rx DMA unit. Therefore, make sure the security engine is
1184 * completely disabled prior to enabling the Rx unit.
1185 */
1186 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1187 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
1188 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1189 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
1190 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
1191 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
1192 break;
1193 else
1194 udelay(10);
1195 }
1196
1197 /* For informational purposes only */
1198 if (i >= IXGBE_MAX_SECRX_POLL)
1199 hw_dbg(hw, "Rx unit being enabled before security "
1200 "path fully disabled. Continuing with init.\n");
1201
1202 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1203 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1204 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
1205 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1206 IXGBE_WRITE_FLUSH(hw);
1207
1208 return 0;
1209}
1210
1211static struct ixgbe_mac_operations mac_ops_82599 = {
1212 .init_hw = &ixgbe_init_hw_generic,
1213 .reset_hw = &ixgbe_reset_hw_82599,
1214 .start_hw = &ixgbe_start_hw_82599,
1215 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
1216 .get_media_type = &ixgbe_get_media_type_82599,
1217 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
1218 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
1219 .get_mac_addr = &ixgbe_get_mac_addr_generic,
1220 .stop_adapter = &ixgbe_stop_adapter_generic,
1221 .get_bus_info = &ixgbe_get_bus_info_generic,
1222 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
1223 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
1224 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
1225 .setup_link = &ixgbe_setup_mac_link_82599,
1226 .setup_link_speed = &ixgbe_setup_mac_link_speed_82599,
1227 .check_link = &ixgbe_check_mac_link_82599,
1228 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
1229 .led_on = &ixgbe_led_on_generic,
1230 .led_off = &ixgbe_led_off_generic,
1231 .blink_led_start = &ixgbe_blink_led_start_82599,
1232 .blink_led_stop = &ixgbe_blink_led_stop_82599,
1233 .set_rar = &ixgbe_set_rar_generic,
1234 .clear_rar = &ixgbe_clear_rar_generic,
1235 .set_vmdq = &ixgbe_set_vmdq_82599,
1236 .clear_vmdq = &ixgbe_clear_vmdq_82599,
1237 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
1238 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
1239 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
1240 .enable_mc = &ixgbe_enable_mc_generic,
1241 .disable_mc = &ixgbe_disable_mc_generic,
1242 .clear_vfta = &ixgbe_clear_vfta_82599,
1243 .set_vfta = &ixgbe_set_vfta_82599,
1244 .setup_fc = &ixgbe_setup_fc_generic,
1245 .init_uta_tables = &ixgbe_init_uta_tables_82599,
1246 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
1247};
1248
1249static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
1250 .init_params = &ixgbe_init_eeprom_params_generic,
1251 .read = &ixgbe_read_eeprom_generic,
1252 .write = &ixgbe_write_eeprom_generic,
1253 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
1254 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
1255};
1256
1257static struct ixgbe_phy_operations phy_ops_82599 = {
1258 .identify = &ixgbe_identify_phy_82599,
1259 .identify_sfp = &ixgbe_identify_sfp_module_generic,
1260 .reset = &ixgbe_reset_phy_generic,
1261 .read_reg = &ixgbe_read_phy_reg_generic,
1262 .write_reg = &ixgbe_write_phy_reg_generic,
1263 .setup_link = &ixgbe_setup_phy_link_generic,
1264 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
1265 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
1266 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
1267 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
1268 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
1269};
1270
1271struct ixgbe_info ixgbe_82599_info = {
1272 .mac = ixgbe_mac_82599EB,
1273 .get_invariants = &ixgbe_get_invariants_82599,
1274 .mac_ops = &mac_ops_82599,
1275 .eeprom_ops = &eeprom_ops_82599,
1276 .phy_ops = &phy_ops_82599,
1277};
diff --git a/drivers/net/ixgbe/ixgbe_common.c b/drivers/net/ixgbe/ixgbe_common.c
index 5ae93989784f..26ee8a04646e 100644
--- a/drivers/net/ixgbe/ixgbe_common.c
+++ b/drivers/net/ixgbe/ixgbe_common.c
@@ -29,6 +29,7 @@
29#include <linux/delay.h> 29#include <linux/delay.h>
30#include <linux/sched.h> 30#include <linux/sched.h>
31 31
32#include "ixgbe.h"
32#include "ixgbe_common.h" 33#include "ixgbe_common.h"
33#include "ixgbe_phy.h" 34#include "ixgbe_phy.h"
34 35
@@ -251,6 +252,81 @@ s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
251} 252}
252 253
253/** 254/**
255 * ixgbe_get_bus_info_generic - Generic set PCI bus info
256 * @hw: pointer to hardware structure
257 *
258 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
259 **/
260s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
261{
262 struct ixgbe_adapter *adapter = hw->back;
263 struct ixgbe_mac_info *mac = &hw->mac;
264 u16 link_status;
265
266 hw->bus.type = ixgbe_bus_type_pci_express;
267
268 /* Get the negotiated link width and speed from PCI config space */
269 pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS,
270 &link_status);
271
272 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
273 case IXGBE_PCI_LINK_WIDTH_1:
274 hw->bus.width = ixgbe_bus_width_pcie_x1;
275 break;
276 case IXGBE_PCI_LINK_WIDTH_2:
277 hw->bus.width = ixgbe_bus_width_pcie_x2;
278 break;
279 case IXGBE_PCI_LINK_WIDTH_4:
280 hw->bus.width = ixgbe_bus_width_pcie_x4;
281 break;
282 case IXGBE_PCI_LINK_WIDTH_8:
283 hw->bus.width = ixgbe_bus_width_pcie_x8;
284 break;
285 default:
286 hw->bus.width = ixgbe_bus_width_unknown;
287 break;
288 }
289
290 switch (link_status & IXGBE_PCI_LINK_SPEED) {
291 case IXGBE_PCI_LINK_SPEED_2500:
292 hw->bus.speed = ixgbe_bus_speed_2500;
293 break;
294 case IXGBE_PCI_LINK_SPEED_5000:
295 hw->bus.speed = ixgbe_bus_speed_5000;
296 break;
297 default:
298 hw->bus.speed = ixgbe_bus_speed_unknown;
299 break;
300 }
301
302 mac->ops.set_lan_id(hw);
303
304 return 0;
305}
306
307/**
308 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
309 * @hw: pointer to the HW structure
310 *
311 * Determines the LAN function id by reading memory-mapped registers
312 * and swaps the port value if requested.
313 **/
314void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
315{
316 struct ixgbe_bus_info *bus = &hw->bus;
317 u32 reg;
318
319 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
320 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
321 bus->lan_id = bus->func;
322
323 /* check for a port swap */
324 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
325 if (reg & IXGBE_FACTPS_LFS)
326 bus->func ^= 0x1;
327}
328
329/**
254 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 330 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
255 * @hw: pointer to hardware structure 331 * @hw: pointer to hardware structure
256 * 332 *
@@ -390,6 +466,73 @@ s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
390} 466}
391 467
392/** 468/**
469 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
470 * @hw: pointer to hardware structure
471 * @offset: offset within the EEPROM to be written to
472 * @data: 16 bit word to be written to the EEPROM
473 *
474 * If ixgbe_eeprom_update_checksum is not called after this function, the
475 * EEPROM will most likely contain an invalid checksum.
476 **/
477s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
478{
479 s32 status;
480 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
481
482 hw->eeprom.ops.init_params(hw);
483
484 if (offset >= hw->eeprom.word_size) {
485 status = IXGBE_ERR_EEPROM;
486 goto out;
487 }
488
489 /* Prepare the EEPROM for writing */
490 status = ixgbe_acquire_eeprom(hw);
491
492 if (status == 0) {
493 if (ixgbe_ready_eeprom(hw) != 0) {
494 ixgbe_release_eeprom(hw);
495 status = IXGBE_ERR_EEPROM;
496 }
497 }
498
499 if (status == 0) {
500 ixgbe_standby_eeprom(hw);
501
502 /* Send the WRITE ENABLE command (8 bit opcode ) */
503 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI,
504 IXGBE_EEPROM_OPCODE_BITS);
505
506 ixgbe_standby_eeprom(hw);
507
508 /*
509 * Some SPI eeproms use the 8th address bit embedded in the
510 * opcode
511 */
512 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
513 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
514
515 /* Send the Write command (8-bit opcode + addr) */
516 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
517 IXGBE_EEPROM_OPCODE_BITS);
518 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
519 hw->eeprom.address_bits);
520
521 /* Send the data */
522 data = (data >> 8) | (data << 8);
523 ixgbe_shift_out_eeprom_bits(hw, data, 16);
524 ixgbe_standby_eeprom(hw);
525
526 msleep(hw->eeprom.semaphore_delay);
527 /* Done with writing - release the EEPROM */
528 ixgbe_release_eeprom(hw);
529 }
530
531out:
532 return status;
533}
534
535/**
393 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 536 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
394 * @hw: pointer to hardware structure 537 * @hw: pointer to hardware structure
395 * @offset: offset within the EEPROM to be read 538 * @offset: offset within the EEPROM to be read
@@ -1487,6 +1630,101 @@ s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
1487} 1630}
1488 1631
1489/** 1632/**
1633 * ixgbe_fc_enable - Enable flow control
1634 * @hw: pointer to hardware structure
1635 * @packetbuf_num: packet buffer number (0-7)
1636 *
1637 * Enable flow control according to the current settings.
1638 **/
1639s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num)
1640{
1641 s32 ret_val = 0;
1642 u32 mflcn_reg;
1643 u32 fccfg_reg;
1644 u32 reg;
1645
1646 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
1647 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE);
1648
1649 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
1650 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
1651
1652 /*
1653 * The possible values of fc.current_mode are:
1654 * 0: Flow control is completely disabled
1655 * 1: Rx flow control is enabled (we can receive pause frames,
1656 * but not send pause frames).
1657 * 2: Tx flow control is enabled (we can send pause frames but
1658 * we do not support receiving pause frames).
1659 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1660 * other: Invalid.
1661 */
1662 switch (hw->fc.current_mode) {
1663 case ixgbe_fc_none:
1664 /* Flow control completely disabled by software override. */
1665 break;
1666 case ixgbe_fc_rx_pause:
1667 /*
1668 * Rx Flow control is enabled and Tx Flow control is
1669 * disabled by software override. Since there really
1670 * isn't a way to advertise that we are capable of RX
1671 * Pause ONLY, we will advertise that we support both
1672 * symmetric and asymmetric Rx PAUSE. Later, we will
1673 * disable the adapter's ability to send PAUSE frames.
1674 */
1675 mflcn_reg |= IXGBE_MFLCN_RFCE;
1676 break;
1677 case ixgbe_fc_tx_pause:
1678 /*
1679 * Tx Flow control is enabled, and Rx Flow control is
1680 * disabled by software override.
1681 */
1682 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1683 break;
1684 case ixgbe_fc_full:
1685 /* Flow control (both Rx and Tx) is enabled by SW override. */
1686 mflcn_reg |= IXGBE_MFLCN_RFCE;
1687 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1688 break;
1689 default:
1690 hw_dbg(hw, "Flow control param set incorrectly\n");
1691 ret_val = -IXGBE_ERR_CONFIG;
1692 goto out;
1693 break;
1694 }
1695
1696 /* Enable 802.3x based flow control settings. */
1697 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
1698 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
1699
1700 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
1701 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
1702 if (hw->fc.send_xon)
1703 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num),
1704 (hw->fc.low_water | IXGBE_FCRTL_XONE));
1705 else
1706 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num),
1707 hw->fc.low_water);
1708
1709 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num),
1710 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
1711 }
1712
1713 /* Configure pause time (2 TCs per register) */
1714 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num));
1715 if ((packetbuf_num & 1) == 0)
1716 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
1717 else
1718 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
1719 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
1720
1721 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
1722
1723out:
1724 return ret_val;
1725}
1726
1727/**
1490 * ixgbe_fc_autoneg - Configure flow control 1728 * ixgbe_fc_autoneg - Configure flow control
1491 * @hw: pointer to hardware structure 1729 * @hw: pointer to hardware structure
1492 * 1730 *
@@ -1625,6 +1863,74 @@ out:
1625} 1863}
1626 1864
1627/** 1865/**
1866 * ixgbe_setup_fc_generic - Set up flow control
1867 * @hw: pointer to hardware structure
1868 *
1869 * Sets up flow control.
1870 **/
1871s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
1872{
1873 s32 ret_val = 0;
1874 ixgbe_link_speed speed;
1875 bool link_up;
1876
1877 /* Validate the packetbuf configuration */
1878 if (packetbuf_num < 0 || packetbuf_num > 7) {
1879 hw_dbg(hw, "Invalid packet buffer number [%d], expected range "
1880 "is 0-7\n", packetbuf_num);
1881 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1882 goto out;
1883 }
1884
1885 /*
1886 * Validate the water mark configuration. Zero water marks are invalid
1887 * because it causes the controller to just blast out fc packets.
1888 */
1889 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
1890 hw_dbg(hw, "Invalid water mark configuration\n");
1891 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1892 goto out;
1893 }
1894
1895 /*
1896 * Validate the requested mode. Strict IEEE mode does not allow
1897 * ixgbe_fc_rx_pause because it will cause testing anomalies.
1898 */
1899 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
1900 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict "
1901 "IEEE mode\n");
1902 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1903 goto out;
1904 }
1905
1906 /*
1907 * 10gig parts do not have a word in the EEPROM to determine the
1908 * default flow control setting, so we explicitly set it to full.
1909 */
1910 if (hw->fc.requested_mode == ixgbe_fc_default)
1911 hw->fc.requested_mode = ixgbe_fc_full;
1912
1913 /*
1914 * Save off the requested flow control mode for use later. Depending
1915 * on the link partner's capabilities, we may or may not use this mode.
1916 */
1917 hw->fc.current_mode = hw->fc.requested_mode;
1918
1919 /* Decide whether to use autoneg or not. */
1920 hw->mac.ops.check_link(hw, &speed, &link_up, false);
1921 if (hw->phy.multispeed_fiber && (speed == IXGBE_LINK_SPEED_1GB_FULL))
1922 ret_val = ixgbe_fc_autoneg(hw);
1923
1924 if (ret_val)
1925 goto out;
1926
1927 ret_val = ixgbe_fc_enable(hw, packetbuf_num);
1928
1929out:
1930 return ret_val;
1931}
1932
1933/**
1628 * ixgbe_disable_pcie_master - Disable PCI-express master access 1934 * ixgbe_disable_pcie_master - Disable PCI-express master access
1629 * @hw: pointer to hardware structure 1935 * @hw: pointer to hardware structure
1630 * 1936 *
@@ -1732,3 +2038,16 @@ void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
1732 ixgbe_release_eeprom_semaphore(hw); 2038 ixgbe_release_eeprom_semaphore(hw);
1733} 2039}
1734 2040
2041/**
2042 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2043 * @hw: pointer to hardware structure
2044 * @regval: register value to write to RXCTRL
2045 *
2046 * Enables the Rx DMA unit
2047 **/
2048s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2049{
2050 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2051
2052 return 0;
2053}
diff --git a/drivers/net/ixgbe/ixgbe_common.h b/drivers/net/ixgbe/ixgbe_common.h
index c63021261e56..7e94d6d399ab 100644
--- a/drivers/net/ixgbe/ixgbe_common.h
+++ b/drivers/net/ixgbe/ixgbe_common.h
@@ -37,12 +37,14 @@ s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw);
37s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num); 37s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num);
38s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr); 38s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);
39s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw); 39s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);
40void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw);
40s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw); 41s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw);
41 42
42s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index); 43s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index);
43s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index); 44s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index);
44 45
45s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw); 46s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);
47s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
46s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data); 48s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data);
47s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 49s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
48 u16 *data); 50 u16 *data);
@@ -61,6 +63,7 @@ s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
61 u32 addr_count, ixgbe_mc_addr_itr func); 63 u32 addr_count, ixgbe_mc_addr_itr func);
62s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw); 64s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw);
63s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw); 65s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw);
66s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);
64s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw, s32 packetbuf_num); 67s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw, s32 packetbuf_num);
65s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packtetbuf_num); 68s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packtetbuf_num);
66s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw); 69s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw);
@@ -75,6 +78,13 @@ s32 ixgbe_write_analog_reg8_generic(struct ixgbe_hw *hw, u32 reg, u8 val);
75 78
76#define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg))) 79#define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
77 80
81#ifndef writeq
82#define writeq(val, addr) writel((u32) (val), addr); \
83 writel((u32) (val >> 32), (addr + 4));
84#endif
85
86#define IXGBE_WRITE_REG64(a, reg, value) writeq((value), ((a)->hw_addr + (reg)))
87
78#define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg)) 88#define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg))
79 89
80#define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) (\ 90#define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) (\
diff --git a/drivers/net/ixgbe/ixgbe_ethtool.c b/drivers/net/ixgbe/ixgbe_ethtool.c
index cec2f4e8c61e..35d820e6dfa8 100644
--- a/drivers/net/ixgbe/ixgbe_ethtool.c
+++ b/drivers/net/ixgbe/ixgbe_ethtool.c
@@ -469,7 +469,7 @@ static void ixgbe_get_regs(struct net_device *netdev,
469 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT); 469 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
470 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL); 470 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
471 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM); 471 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
472 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT); 472 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
473 473
474 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS); 474 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
475 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS); 475 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
diff --git a/drivers/net/ixgbe/ixgbe_phy.c b/drivers/net/ixgbe/ixgbe_phy.c
index 77ec26f5650a..14e9606aa3b3 100644
--- a/drivers/net/ixgbe/ixgbe_phy.c
+++ b/drivers/net/ixgbe/ixgbe_phy.c
@@ -32,6 +32,18 @@
32#include "ixgbe_common.h" 32#include "ixgbe_common.h"
33#include "ixgbe_phy.h" 33#include "ixgbe_phy.h"
34 34
35static void ixgbe_i2c_start(struct ixgbe_hw *hw);
36static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
37static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
38static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
39static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
40static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
41static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
42static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
43static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
44static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
45static bool ixgbe_get_i2c_data(u32 *i2cctl);
46static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
35static bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr); 47static bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
36static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); 48static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
37static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw); 49static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
@@ -543,8 +555,9 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
543 u8 identifier = 0; 555 u8 identifier = 0;
544 u8 comp_codes_1g = 0; 556 u8 comp_codes_1g = 0;
545 u8 comp_codes_10g = 0; 557 u8 comp_codes_10g = 0;
546 u8 oui_bytes[4] = {0, 0, 0, 0}; 558 u8 oui_bytes[3] = {0, 0, 0};
547 u8 transmission_media = 0; 559 u8 transmission_media = 0;
560 u16 enforce_sfp = 0;
548 561
549 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 562 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
550 &identifier); 563 &identifier);
@@ -564,18 +577,48 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
564 577
565 /* ID Module 578 /* ID Module
566 * ========= 579 * =========
567 * 0 SFP_DA_CU 580 * 0 SFP_DA_CU
568 * 1 SFP_SR 581 * 1 SFP_SR
569 * 2 SFP_LR 582 * 2 SFP_LR
583 * 3 SFP_DA_CORE0 - 82599-specific
584 * 4 SFP_DA_CORE1 - 82599-specific
585 * 5 SFP_SR/LR_CORE0 - 82599-specific
586 * 6 SFP_SR/LR_CORE1 - 82599-specific
570 */ 587 */
571 if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE) 588 if (hw->mac.type == ixgbe_mac_82598EB) {
572 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 589 if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE)
573 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 590 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
574 hw->phy.sfp_type = ixgbe_sfp_type_sr; 591 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
575 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 592 hw->phy.sfp_type = ixgbe_sfp_type_sr;
576 hw->phy.sfp_type = ixgbe_sfp_type_lr; 593 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
577 else 594 hw->phy.sfp_type = ixgbe_sfp_type_lr;
578 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 595 else
596 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
597 } else if (hw->mac.type == ixgbe_mac_82599EB) {
598 if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE)
599 if (hw->bus.lan_id == 0)
600 hw->phy.sfp_type =
601 ixgbe_sfp_type_da_cu_core0;
602 else
603 hw->phy.sfp_type =
604 ixgbe_sfp_type_da_cu_core1;
605 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
606 if (hw->bus.lan_id == 0)
607 hw->phy.sfp_type =
608 ixgbe_sfp_type_srlr_core0;
609 else
610 hw->phy.sfp_type =
611 ixgbe_sfp_type_srlr_core1;
612 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
613 if (hw->bus.lan_id == 0)
614 hw->phy.sfp_type =
615 ixgbe_sfp_type_srlr_core0;
616 else
617 hw->phy.sfp_type =
618 ixgbe_sfp_type_srlr_core1;
619 else
620 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
621 }
579 622
580 /* Determine PHY vendor */ 623 /* Determine PHY vendor */
581 if (hw->phy.type == ixgbe_phy_unknown) { 624 if (hw->phy.type == ixgbe_phy_unknown) {
@@ -607,6 +650,9 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
607 case IXGBE_SFF_VENDOR_OUI_AVAGO: 650 case IXGBE_SFF_VENDOR_OUI_AVAGO:
608 hw->phy.type = ixgbe_phy_sfp_avago; 651 hw->phy.type = ixgbe_phy_sfp_avago;
609 break; 652 break;
653 case IXGBE_SFF_VENDOR_OUI_INTEL:
654 hw->phy.type = ixgbe_phy_sfp_intel;
655 break;
610 default: 656 default:
611 if (transmission_media & 657 if (transmission_media &
612 IXGBE_SFF_TWIN_AX_CAPABLE) 658 IXGBE_SFF_TWIN_AX_CAPABLE)
@@ -616,7 +662,28 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
616 break; 662 break;
617 } 663 }
618 } 664 }
619 status = 0; 665 if (hw->mac.type == ixgbe_mac_82598EB ||
666 (hw->phy.sfp_type != ixgbe_sfp_type_sr &&
667 hw->phy.sfp_type != ixgbe_sfp_type_lr &&
668 hw->phy.sfp_type != ixgbe_sfp_type_srlr_core0 &&
669 hw->phy.sfp_type != ixgbe_sfp_type_srlr_core1)) {
670 status = 0;
671 goto out;
672 }
673
674 hw->eeprom.ops.read(hw, IXGBE_PHY_ENFORCE_INTEL_SFP_OFFSET,
675 &enforce_sfp);
676 if (!(enforce_sfp & IXGBE_PHY_ALLOW_ANY_SFP)) {
677 /* Make sure we're a supported PHY type */
678 if (hw->phy.type == ixgbe_phy_sfp_intel) {
679 status = 0;
680 } else {
681 hw_dbg(hw, "SFP+ module not supported\n");
682 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
683 }
684 } else {
685 status = 0;
686 }
620 } 687 }
621 688
622out: 689out:
@@ -651,7 +718,7 @@ s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
651 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset); 718 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
652 719
653 if ((!*list_offset) || (*list_offset == 0xFFFF)) 720 if ((!*list_offset) || (*list_offset == 0xFFFF))
654 return IXGBE_ERR_PHY; 721 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
655 722
656 /* Shift offset to first ID word */ 723 /* Shift offset to first ID word */
657 (*list_offset)++; 724 (*list_offset)++;
@@ -688,6 +755,501 @@ s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
688} 755}
689 756
690/** 757/**
758 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
759 * @hw: pointer to hardware structure
760 * @byte_offset: EEPROM byte offset to read
761 * @eeprom_data: value read
762 *
763 * Performs byte read operation to SFP module's EEPROM over I2C interface.
764 **/
765s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
766 u8 *eeprom_data)
767{
768 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
769 IXGBE_I2C_EEPROM_DEV_ADDR,
770 eeprom_data);
771}
772
773/**
774 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
775 * @hw: pointer to hardware structure
776 * @byte_offset: EEPROM byte offset to write
777 * @eeprom_data: value to write
778 *
779 * Performs byte write operation to SFP module's EEPROM over I2C interface.
780 **/
781s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
782 u8 eeprom_data)
783{
784 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
785 IXGBE_I2C_EEPROM_DEV_ADDR,
786 eeprom_data);
787}
788
789/**
790 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
791 * @hw: pointer to hardware structure
792 * @byte_offset: byte offset to read
793 * @data: value read
794 *
795 * Performs byte read operation to SFP module's EEPROM over I2C interface at
796 * a specified deivce address.
797 **/
798s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
799 u8 dev_addr, u8 *data)
800{
801 s32 status = 0;
802 u32 max_retry = 1;
803 u32 retry = 0;
804 bool nack = 1;
805
806 do {
807 ixgbe_i2c_start(hw);
808
809 /* Device Address and write indication */
810 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
811 if (status != 0)
812 goto fail;
813
814 status = ixgbe_get_i2c_ack(hw);
815 if (status != 0)
816 goto fail;
817
818 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
819 if (status != 0)
820 goto fail;
821
822 status = ixgbe_get_i2c_ack(hw);
823 if (status != 0)
824 goto fail;
825
826 ixgbe_i2c_start(hw);
827
828 /* Device Address and read indication */
829 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
830 if (status != 0)
831 goto fail;
832
833 status = ixgbe_get_i2c_ack(hw);
834 if (status != 0)
835 goto fail;
836
837 status = ixgbe_clock_in_i2c_byte(hw, data);
838 if (status != 0)
839 goto fail;
840
841 status = ixgbe_clock_out_i2c_bit(hw, nack);
842 if (status != 0)
843 goto fail;
844
845 ixgbe_i2c_stop(hw);
846 break;
847
848fail:
849 ixgbe_i2c_bus_clear(hw);
850 retry++;
851 if (retry < max_retry)
852 hw_dbg(hw, "I2C byte read error - Retrying.\n");
853 else
854 hw_dbg(hw, "I2C byte read error.\n");
855
856 } while (retry < max_retry);
857
858 return status;
859}
860
861/**
862 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
863 * @hw: pointer to hardware structure
864 * @byte_offset: byte offset to write
865 * @data: value to write
866 *
867 * Performs byte write operation to SFP module's EEPROM over I2C interface at
868 * a specified device address.
869 **/
870s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
871 u8 dev_addr, u8 data)
872{
873 s32 status = 0;
874 u32 max_retry = 1;
875 u32 retry = 0;
876
877 do {
878 ixgbe_i2c_start(hw);
879
880 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
881 if (status != 0)
882 goto fail;
883
884 status = ixgbe_get_i2c_ack(hw);
885 if (status != 0)
886 goto fail;
887
888 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
889 if (status != 0)
890 goto fail;
891
892 status = ixgbe_get_i2c_ack(hw);
893 if (status != 0)
894 goto fail;
895
896 status = ixgbe_clock_out_i2c_byte(hw, data);
897 if (status != 0)
898 goto fail;
899
900 status = ixgbe_get_i2c_ack(hw);
901 if (status != 0)
902 goto fail;
903
904 ixgbe_i2c_stop(hw);
905 break;
906
907fail:
908 ixgbe_i2c_bus_clear(hw);
909 retry++;
910 if (retry < max_retry)
911 hw_dbg(hw, "I2C byte write error - Retrying.\n");
912 else
913 hw_dbg(hw, "I2C byte write error.\n");
914 } while (retry < max_retry);
915
916 return status;
917}
918
919/**
920 * ixgbe_i2c_start - Sets I2C start condition
921 * @hw: pointer to hardware structure
922 *
923 * Sets I2C start condition (High -> Low on SDA while SCL is High)
924 **/
925static void ixgbe_i2c_start(struct ixgbe_hw *hw)
926{
927 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
928
929 /* Start condition must begin with data and clock high */
930 ixgbe_set_i2c_data(hw, &i2cctl, 1);
931 ixgbe_raise_i2c_clk(hw, &i2cctl);
932
933 /* Setup time for start condition (4.7us) */
934 udelay(IXGBE_I2C_T_SU_STA);
935
936 ixgbe_set_i2c_data(hw, &i2cctl, 0);
937
938 /* Hold time for start condition (4us) */
939 udelay(IXGBE_I2C_T_HD_STA);
940
941 ixgbe_lower_i2c_clk(hw, &i2cctl);
942
943 /* Minimum low period of clock is 4.7 us */
944 udelay(IXGBE_I2C_T_LOW);
945
946}
947
948/**
949 * ixgbe_i2c_stop - Sets I2C stop condition
950 * @hw: pointer to hardware structure
951 *
952 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
953 **/
954static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
955{
956 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
957
958 /* Stop condition must begin with data low and clock high */
959 ixgbe_set_i2c_data(hw, &i2cctl, 0);
960 ixgbe_raise_i2c_clk(hw, &i2cctl);
961
962 /* Setup time for stop condition (4us) */
963 udelay(IXGBE_I2C_T_SU_STO);
964
965 ixgbe_set_i2c_data(hw, &i2cctl, 1);
966
967 /* bus free time between stop and start (4.7us)*/
968 udelay(IXGBE_I2C_T_BUF);
969}
970
971/**
972 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
973 * @hw: pointer to hardware structure
974 * @data: data byte to clock in
975 *
976 * Clocks in one byte data via I2C data/clock
977 **/
978static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
979{
980 s32 status = 0;
981 s32 i;
982 bool bit = 0;
983
984 for (i = 7; i >= 0; i--) {
985 status = ixgbe_clock_in_i2c_bit(hw, &bit);
986 *data |= bit << i;
987
988 if (status != 0)
989 break;
990 }
991
992 return status;
993}
994
995/**
996 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
997 * @hw: pointer to hardware structure
998 * @data: data byte clocked out
999 *
1000 * Clocks out one byte data via I2C data/clock
1001 **/
1002static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1003{
1004 s32 status = 0;
1005 s32 i;
1006 u32 i2cctl;
1007 bool bit = 0;
1008
1009 for (i = 7; i >= 0; i--) {
1010 bit = (data >> i) & 0x1;
1011 status = ixgbe_clock_out_i2c_bit(hw, bit);
1012
1013 if (status != 0)
1014 break;
1015 }
1016
1017 /* Release SDA line (set high) */
1018 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1019 i2cctl |= IXGBE_I2C_DATA_OUT;
1020 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1021
1022 return status;
1023}
1024
1025/**
1026 * ixgbe_get_i2c_ack - Polls for I2C ACK
1027 * @hw: pointer to hardware structure
1028 *
1029 * Clocks in/out one bit via I2C data/clock
1030 **/
1031static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1032{
1033 s32 status;
1034 u32 i = 0;
1035 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1036 u32 timeout = 10;
1037 bool ack = 1;
1038
1039 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1040
1041 if (status != 0)
1042 goto out;
1043
1044 /* Minimum high period of clock is 4us */
1045 udelay(IXGBE_I2C_T_HIGH);
1046
1047 /* Poll for ACK. Note that ACK in I2C spec is
1048 * transition from 1 to 0 */
1049 for (i = 0; i < timeout; i++) {
1050 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1051 ack = ixgbe_get_i2c_data(&i2cctl);
1052
1053 udelay(1);
1054 if (ack == 0)
1055 break;
1056 }
1057
1058 if (ack == 1) {
1059 hw_dbg(hw, "I2C ack was not received.\n");
1060 status = IXGBE_ERR_I2C;
1061 }
1062
1063 ixgbe_lower_i2c_clk(hw, &i2cctl);
1064
1065 /* Minimum low period of clock is 4.7 us */
1066 udelay(IXGBE_I2C_T_LOW);
1067
1068out:
1069 return status;
1070}
1071
1072/**
1073 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1074 * @hw: pointer to hardware structure
1075 * @data: read data value
1076 *
1077 * Clocks in one bit via I2C data/clock
1078 **/
1079static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1080{
1081 s32 status;
1082 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1083
1084 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1085
1086 /* Minimum high period of clock is 4us */
1087 udelay(IXGBE_I2C_T_HIGH);
1088
1089 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1090 *data = ixgbe_get_i2c_data(&i2cctl);
1091
1092 ixgbe_lower_i2c_clk(hw, &i2cctl);
1093
1094 /* Minimum low period of clock is 4.7 us */
1095 udelay(IXGBE_I2C_T_LOW);
1096
1097 return status;
1098}
1099
1100/**
1101 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1102 * @hw: pointer to hardware structure
1103 * @data: data value to write
1104 *
1105 * Clocks out one bit via I2C data/clock
1106 **/
1107static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1108{
1109 s32 status;
1110 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1111
1112 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1113 if (status == 0) {
1114 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1115
1116 /* Minimum high period of clock is 4us */
1117 udelay(IXGBE_I2C_T_HIGH);
1118
1119 ixgbe_lower_i2c_clk(hw, &i2cctl);
1120
1121 /* Minimum low period of clock is 4.7 us.
1122 * This also takes care of the data hold time.
1123 */
1124 udelay(IXGBE_I2C_T_LOW);
1125 } else {
1126 status = IXGBE_ERR_I2C;
1127 hw_dbg(hw, "I2C data was not set to %X\n", data);
1128 }
1129
1130 return status;
1131}
1132/**
1133 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1134 * @hw: pointer to hardware structure
1135 * @i2cctl: Current value of I2CCTL register
1136 *
1137 * Raises the I2C clock line '0'->'1'
1138 **/
1139static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1140{
1141 s32 status = 0;
1142
1143 *i2cctl |= IXGBE_I2C_CLK_OUT;
1144
1145 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1146
1147 /* SCL rise time (1000ns) */
1148 udelay(IXGBE_I2C_T_RISE);
1149
1150 return status;
1151}
1152
1153/**
1154 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1155 * @hw: pointer to hardware structure
1156 * @i2cctl: Current value of I2CCTL register
1157 *
1158 * Lowers the I2C clock line '1'->'0'
1159 **/
1160static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1161{
1162
1163 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1164
1165 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1166
1167 /* SCL fall time (300ns) */
1168 udelay(IXGBE_I2C_T_FALL);
1169}
1170
1171/**
1172 * ixgbe_set_i2c_data - Sets the I2C data bit
1173 * @hw: pointer to hardware structure
1174 * @i2cctl: Current value of I2CCTL register
1175 * @data: I2C data value (0 or 1) to set
1176 *
1177 * Sets the I2C data bit
1178 **/
1179static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1180{
1181 s32 status = 0;
1182
1183 if (data)
1184 *i2cctl |= IXGBE_I2C_DATA_OUT;
1185 else
1186 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1187
1188 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1189
1190 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1191 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1192
1193 /* Verify data was set correctly */
1194 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1195 if (data != ixgbe_get_i2c_data(i2cctl)) {
1196 status = IXGBE_ERR_I2C;
1197 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1198 }
1199
1200 return status;
1201}
1202
1203/**
1204 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1205 * @hw: pointer to hardware structure
1206 * @i2cctl: Current value of I2CCTL register
1207 *
1208 * Returns the I2C data bit value
1209 **/
1210static bool ixgbe_get_i2c_data(u32 *i2cctl)
1211{
1212 bool data;
1213
1214 if (*i2cctl & IXGBE_I2C_DATA_IN)
1215 data = 1;
1216 else
1217 data = 0;
1218
1219 return data;
1220}
1221
1222/**
1223 * ixgbe_i2c_bus_clear - Clears the I2C bus
1224 * @hw: pointer to hardware structure
1225 *
1226 * Clears the I2C bus by sending nine clock pulses.
1227 * Used when data line is stuck low.
1228 **/
1229static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1230{
1231 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1232 u32 i;
1233
1234 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1235
1236 for (i = 0; i < 9; i++) {
1237 ixgbe_raise_i2c_clk(hw, &i2cctl);
1238
1239 /* Min high period of clock is 4us */
1240 udelay(IXGBE_I2C_T_HIGH);
1241
1242 ixgbe_lower_i2c_clk(hw, &i2cctl);
1243
1244 /* Min low period of clock is 4.7us*/
1245 udelay(IXGBE_I2C_T_LOW);
1246 }
1247
1248 /* Put the i2c bus back to default state */
1249 ixgbe_i2c_stop(hw);
1250}
1251
1252/**
691 * ixgbe_check_phy_link_tnx - Determine link and speed status 1253 * ixgbe_check_phy_link_tnx - Determine link and speed status
692 * @hw: pointer to hardware structure 1254 * @hw: pointer to hardware structure
693 * 1255 *
diff --git a/drivers/net/ixgbe/ixgbe_phy.h b/drivers/net/ixgbe/ixgbe_phy.h
index 539a3061eb29..cc5f1b3287e1 100644
--- a/drivers/net/ixgbe/ixgbe_phy.h
+++ b/drivers/net/ixgbe/ixgbe_phy.h
@@ -54,14 +54,15 @@
54#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3 54#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
55 55
56/* Bit-shift macros */ 56/* Bit-shift macros */
57#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 12 57#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 24
58#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 8 58#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 16
59#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 4 59#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 8
60 60
61/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */ 61/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
62#define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600 62#define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600
63#define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500 63#define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500
64#define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00 64#define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00
65#define IXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100
65 66
66/* I2C SDA and SCL timing parameters for standard mode */ 67/* I2C SDA and SCL timing parameters for standard mode */
67#define IXGBE_I2C_T_HD_STA 4 68#define IXGBE_I2C_T_HD_STA 4
@@ -101,5 +102,12 @@ s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
101s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 102s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
102 u16 *list_offset, 103 u16 *list_offset,
103 u16 *data_offset); 104 u16 *data_offset);
104 105s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
106 u8 dev_addr, u8 *data);
107s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
108 u8 dev_addr, u8 data);
109s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
110 u8 *eeprom_data);
111s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
112 u8 eeprom_data);
105#endif /* _IXGBE_PHY_H_ */ 113#endif /* _IXGBE_PHY_H_ */
diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h
index 237c688f8b6e..60905936d927 100644
--- a/drivers/net/ixgbe/ixgbe_type.h
+++ b/drivers/net/ixgbe/ixgbe_type.h
@@ -45,6 +45,9 @@
45#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1 45#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
46#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1 46#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
47#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4 47#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
48#define IXGBE_DEV_ID_82599 0x10D8
49#define IXGBE_DEV_ID_82599_KX4 0x10F7
50#define IXGBE_DEV_ID_82599_SFP 0x10FB
48 51
49/* General Registers */ 52/* General Registers */
50#define IXGBE_CTRL 0x00000 53#define IXGBE_CTRL 0x00000
@@ -52,9 +55,12 @@
52#define IXGBE_CTRL_EXT 0x00018 55#define IXGBE_CTRL_EXT 0x00018
53#define IXGBE_ESDP 0x00020 56#define IXGBE_ESDP 0x00020
54#define IXGBE_EODSDP 0x00028 57#define IXGBE_EODSDP 0x00028
58#define IXGBE_I2CCTL 0x00028
55#define IXGBE_LEDCTL 0x00200 59#define IXGBE_LEDCTL 0x00200
56#define IXGBE_FRTIMER 0x00048 60#define IXGBE_FRTIMER 0x00048
57#define IXGBE_TCPTIMER 0x0004C 61#define IXGBE_TCPTIMER 0x0004C
62#define IXGBE_CORESPARE 0x00600
63#define IXGBE_EXVET 0x05078
58 64
59/* NVM Registers */ 65/* NVM Registers */
60#define IXGBE_EEC 0x10010 66#define IXGBE_EEC 0x10010
@@ -68,6 +74,19 @@
68#define IXGBE_FLOP 0x1013C 74#define IXGBE_FLOP 0x1013C
69#define IXGBE_GRC 0x10200 75#define IXGBE_GRC 0x10200
70 76
77/* General Receive Control */
78#define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */
79#define IXGBE_GRC_APME 0x00000002 /* Advanced Power Management Enable */
80
81#define IXGBE_VPDDIAG0 0x10204
82#define IXGBE_VPDDIAG1 0x10208
83
84/* I2CCTL Bit Masks */
85#define IXGBE_I2C_CLK_IN 0x00000001
86#define IXGBE_I2C_CLK_OUT 0x00000002
87#define IXGBE_I2C_DATA_IN 0x00000004
88#define IXGBE_I2C_DATA_OUT 0x00000008
89
71/* Interrupt Registers */ 90/* Interrupt Registers */
72#define IXGBE_EICR 0x00800 91#define IXGBE_EICR 0x00800
73#define IXGBE_EICS 0x00808 92#define IXGBE_EICS 0x00808
@@ -75,28 +94,54 @@
75#define IXGBE_EIMC 0x00888 94#define IXGBE_EIMC 0x00888
76#define IXGBE_EIAC 0x00810 95#define IXGBE_EIAC 0x00810
77#define IXGBE_EIAM 0x00890 96#define IXGBE_EIAM 0x00890
78#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : (0x012300 + ((_i) * 4))) 97#define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)
98#define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4)
99#define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4)
100#define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4)
101#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
102 (0x012300 + (((_i) - 24) * 4)))
103#define IXGBE_EITR_ITR_INT_MASK 0x00000FFF
104#define IXGBE_EITR_LLI_MOD 0x00008000
105#define IXGBE_EITR_CNT_WDIS 0x80000000
79#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */ 106#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
107#define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */
108#define IXGBE_EITRSEL 0x00894
80#define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */ 109#define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */
81#define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */ 110#define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */
82#define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4))) 111#define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
83#define IXGBE_GPIE 0x00898 112#define IXGBE_GPIE 0x00898
84 113
85/* Flow Control Registers */ 114/* Flow Control Registers */
115#define IXGBE_FCADBUL 0x03210
116#define IXGBE_FCADBUH 0x03214
117#define IXGBE_FCAMACL 0x04328
118#define IXGBE_FCAMACH 0x0432C
119#define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */
120#define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */
86#define IXGBE_PFCTOP 0x03008 121#define IXGBE_PFCTOP 0x03008
87#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */ 122#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
88#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */ 123#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
89#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */ 124#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
90#define IXGBE_FCRTV 0x032A0 125#define IXGBE_FCRTV 0x032A0
126#define IXGBE_FCCFG 0x03D00
91#define IXGBE_TFCS 0x0CE00 127#define IXGBE_TFCS 0x0CE00
92 128
93/* Receive DMA Registers */ 129/* Receive DMA Registers */
94#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : (0x0D000 + ((_i - 64) * 0x40))) 130#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
95#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : (0x0D004 + ((_i - 64) * 0x40))) 131 (0x0D000 + ((_i - 64) * 0x40)))
96#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : (0x0D008 + ((_i - 64) * 0x40))) 132#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
97#define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : (0x0D010 + ((_i - 64) * 0x40))) 133 (0x0D004 + ((_i - 64) * 0x40)))
98#define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : (0x0D018 + ((_i - 64) * 0x40))) 134#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
99#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : (0x0D028 + ((_i - 64) * 0x40))) 135 (0x0D008 + ((_i - 64) * 0x40)))
136#define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
137 (0x0D010 + ((_i - 64) * 0x40)))
138#define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
139 (0x0D018 + ((_i - 64) * 0x40)))
140#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
141 (0x0D028 + ((_i - 64) * 0x40)))
142#define IXGBE_RDDCC 0x02F20
143#define IXGBE_RXMEMWRAP 0x03190
144#define IXGBE_STARCTRL 0x03024
100/* 145/*
101 * Split and Replication Receive Control Registers 146 * Split and Replication Receive Control Registers
102 * 00-15 : 0x02100 + n*4 147 * 00-15 : 0x02100 + n*4
@@ -129,10 +174,15 @@
129#define IXGBE_DRECCCTL_DISABLE 0 174#define IXGBE_DRECCCTL_DISABLE 0
130/* Multicast Table Array - 128 entries */ 175/* Multicast Table Array - 128 entries */
131#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4)) 176#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4))
132#define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : (0x0A200 + ((_i) * 8))) 177#define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
133#define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : (0x0A204 + ((_i) * 8))) 178 (0x0A200 + ((_i) * 8)))
179#define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
180 (0x0A204 + ((_i) * 8)))
181#define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8))
182#define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8))
134/* Packet split receive type */ 183/* Packet split receive type */
135#define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : (0x0EA00 + ((_i) * 4))) 184#define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
185 (0x0EA00 + ((_i) * 4)))
136/* array of 4096 1-bit vlan filters */ 186/* array of 4096 1-bit vlan filters */
137#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4)) 187#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))
138/*array of 4096 4-bit vlan vmdq indices */ 188/*array of 4096 4-bit vlan vmdq indices */
@@ -141,6 +191,28 @@
141#define IXGBE_VLNCTRL 0x05088 191#define IXGBE_VLNCTRL 0x05088
142#define IXGBE_MCSTCTRL 0x05090 192#define IXGBE_MCSTCTRL 0x05090
143#define IXGBE_MRQC 0x05818 193#define IXGBE_MRQC 0x05818
194#define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */
195#define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */
196#define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */
197#define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
198#define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */
199#define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */
200#define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */
201#define IXGBE_RQTC 0x0EC70
202#define IXGBE_MTQC 0x08120
203#define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */
204#define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */
205#define IXGBE_VT_CTL 0x051B0
206#define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4))
207#define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4))
208#define IXGBE_QDE 0x2F04
209#define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */
210#define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4))
211#define IXGBE_VMRCTL(_i) (0x0F600 + ((_i) * 4))
212#define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4))
213#define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4))
214#define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
215#define IXGBE_LLITHRESH 0x0EC90
144#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */ 216#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */
145#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */ 217#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */
146#define IXGBE_IMIRVP 0x05AC0 218#define IXGBE_IMIRVP 0x05AC0
@@ -148,7 +220,6 @@
148#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */ 220#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */
149#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */ 221#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */
150 222
151
152/* Transmit DMA registers */ 223/* Transmit DMA registers */
153#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/ 224#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/
154#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40)) 225#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
@@ -160,7 +231,20 @@
160#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40)) 231#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
161#define IXGBE_DTXCTL 0x07E00 232#define IXGBE_DTXCTL 0x07E00
162 233
234#define IXGBE_DMATXCTL 0x04A80
235#define IXGBE_DTXMXSZRQ 0x08100
236#define IXGBE_DTXTCPFLGL 0x04A88
237#define IXGBE_DTXTCPFLGH 0x04A8C
238#define IXGBE_LBDRPEN 0x0CA00
239#define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
240
241#define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */
242#define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */
243#define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */
244#define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */
163#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */ 245#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
246/* Tx DCA Control register : 128 of these (0-127) */
247#define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40))
164#define IXGBE_TIPG 0x0CB00 248#define IXGBE_TIPG 0x0CB00
165#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */ 249#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */
166#define IXGBE_MNGTXMAP 0x0CD10 250#define IXGBE_MNGTXMAP 0x0CD10
@@ -177,9 +261,69 @@
177 261
178#define IXGBE_WUPL 0x05900 262#define IXGBE_WUPL 0x05900
179#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */ 263#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
180#define IXGBE_FHFT 0x09000 /* Flex host filter table 9000-93FC */ 264#define IXGBE_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flex host filter table */
181 265#define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100)) /* Ext Flexible Host
182/* Music registers */ 266 * Filter Table */
267
268#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
269#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
270
271/* Each Flexible Filter is at most 128 (0x80) bytes in length */
272#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128
273#define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */
274#define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */
275
276/* Definitions for power management and wakeup registers */
277/* Wake Up Control */
278#define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */
279#define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */
280#define IXGBE_WUC_ADVD3WUC 0x00000010 /* D3Cold wake up cap. enable*/
281
282/* Wake Up Filter Control */
283#define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
284#define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
285#define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
286#define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
287#define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
288#define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
289#define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
290#define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
291#define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */
292
293#define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
294#define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
295#define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
296#define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
297#define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
298#define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
299#define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
300#define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */
301#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */
302#define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all 6 wakeup filters*/
303#define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
304
305/* Wake Up Status */
306#define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC
307#define IXGBE_WUS_MAG IXGBE_WUFC_MAG
308#define IXGBE_WUS_EX IXGBE_WUFC_EX
309#define IXGBE_WUS_MC IXGBE_WUFC_MC
310#define IXGBE_WUS_BC IXGBE_WUFC_BC
311#define IXGBE_WUS_ARP IXGBE_WUFC_ARP
312#define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4
313#define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6
314#define IXGBE_WUS_MNG IXGBE_WUFC_MNG
315#define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0
316#define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1
317#define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2
318#define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3
319#define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4
320#define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5
321#define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS
322
323/* Wake Up Packet Length */
324#define IXGBE_WUPL_LENGTH_MASK 0xFFFF
325
326/* DCB registers */
183#define IXGBE_RMCS 0x03D00 327#define IXGBE_RMCS 0x03D00
184#define IXGBE_DPMCS 0x07F40 328#define IXGBE_DPMCS 0x07F40
185#define IXGBE_PDPMCS 0x0CD00 329#define IXGBE_PDPMCS 0x0CD00
@@ -192,6 +336,122 @@
192#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ 336#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
193 337
194 338
339/* Security Control Registers */
340#define IXGBE_SECTXCTRL 0x08800
341#define IXGBE_SECTXSTAT 0x08804
342#define IXGBE_SECTXBUFFAF 0x08808
343#define IXGBE_SECTXMINIFG 0x08810
344#define IXGBE_SECTXSTAT 0x08804
345#define IXGBE_SECRXCTRL 0x08D00
346#define IXGBE_SECRXSTAT 0x08D04
347
348/* Security Bit Fields and Masks */
349#define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001
350#define IXGBE_SECTXCTRL_TX_DIS 0x00000002
351#define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004
352
353#define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001
354#define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002
355
356#define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001
357#define IXGBE_SECRXCTRL_RX_DIS 0x00000002
358
359#define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001
360#define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002
361
362/* LinkSec (MacSec) Registers */
363#define IXGBE_LSECTXCAP 0x08A00
364#define IXGBE_LSECRXCAP 0x08F00
365#define IXGBE_LSECTXCTRL 0x08A04
366#define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */
367#define IXGBE_LSECTXSCH 0x08A0C /* SCI High */
368#define IXGBE_LSECTXSA 0x08A10
369#define IXGBE_LSECTXPN0 0x08A14
370#define IXGBE_LSECTXPN1 0x08A18
371#define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
372#define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
373#define IXGBE_LSECRXCTRL 0x08F04
374#define IXGBE_LSECRXSCL 0x08F08
375#define IXGBE_LSECRXSCH 0x08F0C
376#define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
377#define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
378#define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
379#define IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */
380#define IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */
381#define IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */
382#define IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */
383#define IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */
384#define IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */
385#define IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */
386#define IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */
387#define IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */
388#define IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */
389#define IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */
390#define IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */
391#define IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */
392#define IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */
393#define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */
394#define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */
395#define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */
396#define IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */
397#define IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */
398
399/* LinkSec (MacSec) Bit Fields and Masks */
400#define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000
401#define IXGBE_LSECTXCAP_SUM_SHIFT 16
402#define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000
403#define IXGBE_LSECRXCAP_SUM_SHIFT 16
404
405#define IXGBE_LSECTXCTRL_EN_MASK 0x00000003
406#define IXGBE_LSECTXCTRL_DISABLE 0x0
407#define IXGBE_LSECTXCTRL_AUTH 0x1
408#define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2
409#define IXGBE_LSECTXCTRL_AISCI 0x00000020
410#define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
411#define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8
412
413#define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C
414#define IXGBE_LSECRXCTRL_EN_SHIFT 2
415#define IXGBE_LSECRXCTRL_DISABLE 0x0
416#define IXGBE_LSECRXCTRL_CHECK 0x1
417#define IXGBE_LSECRXCTRL_STRICT 0x2
418#define IXGBE_LSECRXCTRL_DROP 0x3
419#define IXGBE_LSECRXCTRL_PLSH 0x00000040
420#define IXGBE_LSECRXCTRL_RP 0x00000080
421#define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33
422
423/* IpSec Registers */
424#define IXGBE_IPSTXIDX 0x08900
425#define IXGBE_IPSTXSALT 0x08904
426#define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */
427#define IXGBE_IPSRXIDX 0x08E00
428#define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
429#define IXGBE_IPSRXSPI 0x08E14
430#define IXGBE_IPSRXIPIDX 0x08E18
431#define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
432#define IXGBE_IPSRXSALT 0x08E2C
433#define IXGBE_IPSRXMOD 0x08E30
434
435#define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4
436
437/* DCB registers */
438#define IXGBE_RTRPCS 0x02430
439#define IXGBE_RTTDCS 0x04900
440#define IXGBE_RTTPCS 0x0CD00
441#define IXGBE_RTRUP2TC 0x03020
442#define IXGBE_RTTUP2TC 0x0C800
443#define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */
444#define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */
445#define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */
446#define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */
447#define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
448#define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
449#define IXGBE_RTTDQSEL 0x04904
450#define IXGBE_RTTDT1C 0x04908
451#define IXGBE_RTTDT1S 0x0490C
452#define IXGBE_RTTDTECC 0x04990
453#define IXGBE_RTTDTECC_NO_BCN 0x00000100
454#define IXGBE_RTTBCNRC 0x04984
195 455
196/* Stats registers */ 456/* Stats registers */
197#define IXGBE_CRCERRS 0x04000 457#define IXGBE_CRCERRS 0x04000
@@ -206,6 +466,11 @@
206#define IXGBE_LXONRXC 0x0CF60 466#define IXGBE_LXONRXC 0x0CF60
207#define IXGBE_LXOFFTXC 0x03F68 467#define IXGBE_LXOFFTXC 0x03F68
208#define IXGBE_LXOFFRXC 0x0CF68 468#define IXGBE_LXOFFRXC 0x0CF68
469#define IXGBE_LXONRXCNT 0x041A4
470#define IXGBE_LXOFFRXCNT 0x041A8
471#define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */
472#define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */
473#define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */
209#define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/ 474#define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
210#define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/ 475#define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
211#define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/ 476#define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
@@ -245,14 +510,20 @@
245#define IXGBE_MPTC 0x040F0 510#define IXGBE_MPTC 0x040F0
246#define IXGBE_BPTC 0x040F4 511#define IXGBE_BPTC 0x040F4
247#define IXGBE_XEC 0x04120 512#define IXGBE_XEC 0x04120
513#define IXGBE_SSVPC 0x08780
248 514
249#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) /* 16 of these */ 515#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
250#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : (0x08600 + ((_i) * 4))) 516#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
517 (0x08600 + ((_i) * 4)))
518#define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4))
251 519
252#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */ 520#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
253#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */ 521#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
254#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ 522#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
255#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */ 523#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
524#define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */
525#define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */
526#define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */
256 527
257/* Management */ 528/* Management */
258#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */ 529#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
@@ -265,6 +536,9 @@
265#define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */ 536#define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
266#define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */ 537#define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
267#define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */ 538#define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */
539#define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
540#define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
541#define IXGBE_LSWFW 0x15014
268 542
269/* ARC Subsystem registers */ 543/* ARC Subsystem registers */
270#define IXGBE_HICR 0x15F00 544#define IXGBE_HICR 0x15F00
@@ -297,16 +571,65 @@
297#define IXGBE_DCA_ID 0x11070 571#define IXGBE_DCA_ID 0x11070
298#define IXGBE_DCA_CTRL 0x11074 572#define IXGBE_DCA_CTRL 0x11074
299 573
574/* PCIe registers 82599-specific */
575#define IXGBE_GCR_EXT 0x11050
576#define IXGBE_GSCL_5_82599 0x11030
577#define IXGBE_GSCL_6_82599 0x11034
578#define IXGBE_GSCL_7_82599 0x11038
579#define IXGBE_GSCL_8_82599 0x1103C
580#define IXGBE_PHYADR_82599 0x11040
581#define IXGBE_PHYDAT_82599 0x11044
582#define IXGBE_PHYCTL_82599 0x11048
583#define IXGBE_PBACLR_82599 0x11068
584#define IXGBE_CIAA_82599 0x11088
585#define IXGBE_CIAD_82599 0x1108C
586#define IXGBE_PCIE_DIAG_0_82599 0x11090
587#define IXGBE_PCIE_DIAG_1_82599 0x11094
588#define IXGBE_PCIE_DIAG_2_82599 0x11098
589#define IXGBE_PCIE_DIAG_3_82599 0x1109C
590#define IXGBE_PCIE_DIAG_4_82599 0x110A0
591#define IXGBE_PCIE_DIAG_5_82599 0x110A4
592#define IXGBE_PCIE_DIAG_6_82599 0x110A8
593#define IXGBE_PCIE_DIAG_7_82599 0x110C0
594#define IXGBE_INTRPT_CSR_82599 0x110B0
595#define IXGBE_INTRPT_MASK_82599 0x110B8
596#define IXGBE_CDQ_MBR_82599 0x110B4
597#define IXGBE_MISC_REG_82599 0x110F0
598#define IXGBE_ECC_CTRL_0_82599 0x11100
599#define IXGBE_ECC_CTRL_1_82599 0x11104
600#define IXGBE_ECC_STATUS_82599 0x110E0
601#define IXGBE_BAR_CTRL_82599 0x110F4
602
603/* Time Sync Registers */
604#define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */
605#define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */
606#define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */
607#define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */
608#define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */
609#define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */
610#define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */
611#define IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */
612#define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */
613#define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */
614#define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */
615#define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */
616#define IXGBE_RXUDP 0x08C1C /* Time Sync Rx UDP Port - RW */
617
300/* Diagnostic Registers */ 618/* Diagnostic Registers */
301#define IXGBE_RDSTATCTL 0x02C20 619#define IXGBE_RDSTATCTL 0x02C20
302#define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */ 620#define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
303#define IXGBE_RDHMPN 0x02F08 621#define IXGBE_RDHMPN 0x02F08
304#define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4)) 622#define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4))
305#define IXGBE_RDPROBE 0x02F20 623#define IXGBE_RDPROBE 0x02F20
624#define IXGBE_RDMAM 0x02F30
625#define IXGBE_RDMAD 0x02F34
306#define IXGBE_TDSTATCTL 0x07C20 626#define IXGBE_TDSTATCTL 0x07C20
307#define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */ 627#define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
308#define IXGBE_TDHMPN 0x07F08 628#define IXGBE_TDHMPN 0x07F08
629#define IXGBE_TDHMPN2 0x082FC
630#define IXGBE_TXDESCIC 0x082CC
309#define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4)) 631#define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4))
632#define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4))
310#define IXGBE_TDPROBE 0x07F20 633#define IXGBE_TDPROBE 0x07F20
311#define IXGBE_TXBUFCTRL 0x0C600 634#define IXGBE_TXBUFCTRL 0x0C600
312#define IXGBE_TXBUFDATA0 0x0C610 635#define IXGBE_TXBUFDATA0 0x0C610
@@ -334,6 +657,8 @@
334#define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/ 657#define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
335#define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/ 658#define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
336#define IXGBE_PCIEECCCTL 0x1106C 659#define IXGBE_PCIEECCCTL 0x1106C
660#define IXGBE_PCIEECCCTL0 0x11100
661#define IXGBE_PCIEECCCTL1 0x11104
337#define IXGBE_PBTXECC 0x0C300 662#define IXGBE_PBTXECC 0x0C300
338#define IXGBE_PBRXECC 0x03300 663#define IXGBE_PBRXECC 0x03300
339#define IXGBE_GHECCR 0x110B0 664#define IXGBE_GHECCR 0x110B0
@@ -359,24 +684,61 @@
359#define IXGBE_MSRWD 0x04260 684#define IXGBE_MSRWD 0x04260
360#define IXGBE_MLADD 0x04264 685#define IXGBE_MLADD 0x04264
361#define IXGBE_MHADD 0x04268 686#define IXGBE_MHADD 0x04268
687#define IXGBE_MAXFRS 0x04268
362#define IXGBE_TREG 0x0426C 688#define IXGBE_TREG 0x0426C
363#define IXGBE_PCSS1 0x04288 689#define IXGBE_PCSS1 0x04288
364#define IXGBE_PCSS2 0x0428C 690#define IXGBE_PCSS2 0x0428C
365#define IXGBE_XPCSS 0x04290 691#define IXGBE_XPCSS 0x04290
692#define IXGBE_MFLCN 0x04294
366#define IXGBE_SERDESC 0x04298 693#define IXGBE_SERDESC 0x04298
367#define IXGBE_MACS 0x0429C 694#define IXGBE_MACS 0x0429C
368#define IXGBE_AUTOC 0x042A0 695#define IXGBE_AUTOC 0x042A0
369#define IXGBE_LINKS 0x042A4 696#define IXGBE_LINKS 0x042A4
697#define IXGBE_LINKS2 0x04324
370#define IXGBE_AUTOC2 0x042A8 698#define IXGBE_AUTOC2 0x042A8
371#define IXGBE_AUTOC3 0x042AC 699#define IXGBE_AUTOC3 0x042AC
372#define IXGBE_ANLP1 0x042B0 700#define IXGBE_ANLP1 0x042B0
373#define IXGBE_ANLP2 0x042B4 701#define IXGBE_ANLP2 0x042B4
374#define IXGBE_ATLASCTL 0x04800 702#define IXGBE_ATLASCTL 0x04800
703#define IXGBE_MMNGC 0x042D0
704#define IXGBE_ANLPNP1 0x042D4
705#define IXGBE_ANLPNP2 0x042D8
706#define IXGBE_KRPCSFC 0x042E0
707#define IXGBE_KRPCSS 0x042E4
708#define IXGBE_FECS1 0x042E8
709#define IXGBE_FECS2 0x042EC
710#define IXGBE_SMADARCTL 0x14F10
711#define IXGBE_MPVC 0x04318
712#define IXGBE_SGMIIC 0x04314
713
714/* Omer CORECTL */
715#define IXGBE_CORECTL 0x014F00
716/* BARCTRL */
717#define IXGBE_BARCTRL 0x110F4
718#define IXGBE_BARCTRL_FLSIZE 0x0700
719#define IXGBE_BARCTRL_CSRSIZE 0x2000
375 720
376/* RDRXCTL Bit Masks */ 721/* RDRXCTL Bit Masks */
377#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */ 722#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */
723#define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */
378#define IXGBE_RDRXCTL_MVMEN 0x00000020 724#define IXGBE_RDRXCTL_MVMEN 0x00000020
379#define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */ 725#define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */
726#define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */
727
728/* RQTC Bit Masks and Shifts */
729#define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4)
730#define IXGBE_RQTC_TC0_MASK (0x7 << 0)
731#define IXGBE_RQTC_TC1_MASK (0x7 << 4)
732#define IXGBE_RQTC_TC2_MASK (0x7 << 8)
733#define IXGBE_RQTC_TC3_MASK (0x7 << 12)
734#define IXGBE_RQTC_TC4_MASK (0x7 << 16)
735#define IXGBE_RQTC_TC5_MASK (0x7 << 20)
736#define IXGBE_RQTC_TC6_MASK (0x7 << 24)
737#define IXGBE_RQTC_TC7_MASK (0x7 << 28)
738
739/* PSRTYPE.RQPL Bit masks and shift */
740#define IXGBE_PSRTYPE_RQPL_MASK 0x7
741#define IXGBE_PSRTYPE_RQPL_SHIFT 29
380 742
381/* CTRL Bit Masks */ 743/* CTRL Bit Masks */
382#define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */ 744#define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */
@@ -391,6 +753,7 @@
391#define IXGBE_MHADD_MFS_SHIFT 16 753#define IXGBE_MHADD_MFS_SHIFT 16
392 754
393/* Extended Device Control */ 755/* Extended Device Control */
756#define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */
394#define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */ 757#define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */
395#define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 758#define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
396#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 759#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
@@ -403,6 +766,8 @@
403#define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 766#define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
404 767
405#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 768#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
769#define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */
770#define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */
406#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */ 771#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
407#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */ 772#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
408#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */ 773#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
@@ -411,6 +776,8 @@
411#define IXGBE_DCA_RXCTRL_DESC_HSRO_EN (1 << 15) /* DCA Rx Split Header RO */ 776#define IXGBE_DCA_RXCTRL_DESC_HSRO_EN (1 << 15) /* DCA Rx Split Header RO */
412 777
413#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 778#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
779#define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */
780#define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */
414#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ 781#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
415#define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */ 782#define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
416#define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */ 783#define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */
@@ -454,6 +821,8 @@
454#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0 821#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
455#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0 822#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
456 823
824/* Omer bit masks */
825#define IXGBE_CORECTL_WRITE_CMD 0x00010000
457 826
458/* Device Type definitions for new protocol MDIO commands */ 827/* Device Type definitions for new protocol MDIO commands */
459#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1 828#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1
@@ -481,8 +850,11 @@
481#define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */ 850#define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */
482#define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */ 851#define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */
483#define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */ 852#define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */
853#define IXGBE_MDIO_PHY_EXT_ABILITY 0xB /* Ext Ability Reg */
854#define IXGBE_MDIO_PHY_10GBASET_ABILITY 0x0004 /* 10GBaseT capable */
855#define IXGBE_MDIO_PHY_1000BASET_ABILITY 0x0020 /* 1000BaseT capable */
484 856
485#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Address Reg */ 857#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
486#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */ 858#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
487#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */ 859#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
488 860
@@ -497,7 +869,7 @@
497#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0 869#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
498#define IXGBE_MAX_PHY_ADDR 32 870#define IXGBE_MAX_PHY_ADDR 32
499 871
500/* PHY IDs */ 872/* PHY IDs*/
501#define TN1010_PHY_ID 0x00A19410 873#define TN1010_PHY_ID 0x00A19410
502#define TNX_FW_REV 0xB 874#define TNX_FW_REV 0xB
503#define QT2022_PHY_ID 0x0043A400 875#define QT2022_PHY_ID 0x0043A400
@@ -517,15 +889,22 @@
517#define IXGBE_CONTROL_NL 0x000F 889#define IXGBE_CONTROL_NL 0x000F
518#define IXGBE_CONTROL_EOL_NL 0x0FFF 890#define IXGBE_CONTROL_EOL_NL 0x0FFF
519#define IXGBE_CONTROL_SOL_NL 0x0000 891#define IXGBE_CONTROL_SOL_NL 0x0000
892#define IXGBE_PHY_ENFORCE_INTEL_SFP_OFFSET 0x002C
893#define IXGBE_PHY_ALLOW_ANY_SFP 0x1
520 894
521/* General purpose Interrupt Enable */ 895/* General purpose Interrupt Enable */
522#define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */ 896#define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */
523#define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */ 897#define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */
898#define IXGBE_SDP2_GPIEN 0x00000004 /* SDP2 */
524#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */ 899#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */
525#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */ 900#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */
526#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */ 901#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */
527#define IXGBE_GPIE_EIAME 0x40000000 902#define IXGBE_GPIE_EIAME 0x40000000
528#define IXGBE_GPIE_PBA_SUPPORT 0x80000000 903#define IXGBE_GPIE_PBA_SUPPORT 0x80000000
904#define IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */
905#define IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */
906#define IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */
907#define IXGBE_GPIE_VTMODE_64 0x0000C000 /* 64 VFs 2 queues per VF */
529 908
530/* Transmit Flow Control status */ 909/* Transmit Flow Control status */
531#define IXGBE_TFCS_TXOFF 0x00000001 910#define IXGBE_TFCS_TXOFF 0x00000001
@@ -566,6 +945,21 @@
566#define IXGBE_VMD_CTL_VMDQ_EN 0x00000001 945#define IXGBE_VMD_CTL_VMDQ_EN 0x00000001
567#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002 946#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
568 947
948/* VT_CTL bitmasks */
949#define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */
950#define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */
951#define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */
952
953/* VMOLR bitmasks */
954#define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */
955#define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */
956#define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */
957#define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */
958#define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */
959
960/* VFRE bitmask */
961#define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF
962
569/* RDHMPN and TDHMPN bitmasks */ 963/* RDHMPN and TDHMPN bitmasks */
570#define IXGBE_RDHMPN_RDICADDR 0x007FF800 964#define IXGBE_RDHMPN_RDICADDR 0x007FF800
571#define IXGBE_RDHMPN_RDICRDREQ 0x00800000 965#define IXGBE_RDHMPN_RDICRDREQ 0x00800000
@@ -574,13 +968,39 @@
574#define IXGBE_TDHMPN_TDICRDREQ 0x00800000 968#define IXGBE_TDHMPN_TDICRDREQ 0x00800000
575#define IXGBE_TDHMPN_TDICADDR_SHIFT 11 969#define IXGBE_TDHMPN_TDICADDR_SHIFT 11
576 970
971#define IXGBE_RDMAM_MEM_SEL_SHIFT 13
972#define IXGBE_RDMAM_DWORD_SHIFT 9
973#define IXGBE_RDMAM_DESC_COMP_FIFO 1
974#define IXGBE_RDMAM_DFC_CMD_FIFO 2
975#define IXGBE_RDMAM_TCN_STATUS_RAM 4
976#define IXGBE_RDMAM_WB_COLL_FIFO 5
977#define IXGBE_RDMAM_QSC_CNT_RAM 6
978#define IXGBE_RDMAM_QSC_QUEUE_CNT 8
979#define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA
980#define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135
981#define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4
982#define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48
983#define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7
984#define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256
985#define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9
986#define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8
987#define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4
988#define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64
989#define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4
990#define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32
991#define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4
992#define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128
993#define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8
994
995#define IXGBE_TXDESCIC_READY 0x80000000
996
577/* Receive Checksum Control */ 997/* Receive Checksum Control */
578#define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 998#define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
579#define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 999#define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
580 1000
581/* FCRTL Bit Masks */ 1001/* FCRTL Bit Masks */
582#define IXGBE_FCRTL_XONE 0x80000000 /* bit 31, XON enable */ 1002#define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */
583#define IXGBE_FCRTH_FCEN 0x80000000 /* Rx Flow control enable */ 1003#define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */
584 1004
585/* PAP bit masks*/ 1005/* PAP bit masks*/
586#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */ 1006#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */
@@ -590,19 +1010,29 @@
590/* Receive Arbitration Control: 0 Round Robin, 1 DFP */ 1010/* Receive Arbitration Control: 0 Round Robin, 1 DFP */
591#define IXGBE_RMCS_RAC 0x00000004 1011#define IXGBE_RMCS_RAC 0x00000004
592#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */ 1012#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */
593#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority flow control ena */ 1013#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */
594#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority flow control ena */ 1014#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */
595#define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */ 1015#define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */
596 1016
1017/* FCCFG Bit Masks */
1018#define IXGBE_FCCFG_TFCE_802_3X 0x00000008 /* Tx link FC enable */
1019#define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010 /* Tx priority FC enable */
597 1020
598/* Interrupt register bitmasks */ 1021/* Interrupt register bitmasks */
599 1022
600/* Extended Interrupt Cause Read */ 1023/* Extended Interrupt Cause Read */
601#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */ 1024#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */
1025#define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */
1026#define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */
1027#define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */
1028#define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */
602#define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */ 1029#define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */
1030#define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */
603#define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */ 1031#define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */
604#define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */ 1032#define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */
605#define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */ 1033#define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */
1034#define IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */
1035#define IXGBE_EICR_ECC 0x10000000 /* ECC Error */
606#define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */ 1036#define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */
607#define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */ 1037#define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */
608#define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ 1038#define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
@@ -610,10 +1040,16 @@
610 1040
611/* Extended Interrupt Cause Set */ 1041/* Extended Interrupt Cause Set */
612#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1042#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1043#define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1044#define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */
1045#define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */
1046#define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
613#define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */ 1047#define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */
614#define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 1048#define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
615#define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 1049#define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
616#define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 1050#define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1051#define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1052#define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */
617#define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1053#define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
618#define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */ 1054#define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */
619#define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1055#define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
@@ -621,10 +1057,16 @@
621 1057
622/* Extended Interrupt Mask Set */ 1058/* Extended Interrupt Mask Set */
623#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1059#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1060#define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1061#define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1062#define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */
1063#define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
624#define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */ 1064#define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */
625#define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 1065#define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
626#define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 1066#define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
627#define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 1067#define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1068#define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1069#define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */
628#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1070#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
629#define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */ 1071#define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */
630#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1072#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
@@ -632,10 +1074,16 @@
632 1074
633/* Extended Interrupt Mask Clear */ 1075/* Extended Interrupt Mask Clear */
634#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1076#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1077#define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1078#define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1079#define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */
1080#define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
635#define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */ 1081#define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */
636#define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 1082#define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
637#define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 1083#define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
638#define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 1084#define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1085#define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1086#define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */
639#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1087#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
640#define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */ 1088#define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */
641#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1089#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
@@ -658,6 +1106,33 @@
658#define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */ 1106#define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */
659#define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ 1107#define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */
660#define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */ 1108#define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */
1109#define IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */
1110#define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */
1111#define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */
1112#define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */
1113#define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */
1114#define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */
1115#define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */
1116#define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass check of control bits */
1117#define IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */
1118#define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */
1119#define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */
1120#define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007 /* VLAN priority mask */
1121#define IXGBE_IMIRVP_PRIORITY_EN 0x00000008 /* VLAN priority enable */
1122
1123#define IXGBE_MAX_FTQF_FILTERS 128
1124#define IXGBE_FTQF_PROTOCOL_MASK 0x00000003
1125#define IXGBE_FTQF_PROTOCOL_TCP 0x00000000
1126#define IXGBE_FTQF_PROTOCOL_UDP 0x00000001
1127#define IXGBE_FTQF_PROTOCOL_SCTP 2
1128#define IXGBE_FTQF_PRIORITY_MASK 0x00000007
1129#define IXGBE_FTQF_PRIORITY_SHIFT 2
1130#define IXGBE_FTQF_POOL_MASK 0x0000003F
1131#define IXGBE_FTQF_POOL_SHIFT 8
1132#define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F
1133#define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25
1134#define IXGBE_FTQF_POOL_MASK_EN 0x40000000
1135#define IXGBE_FTQF_QUEUE_ENABLE 0x80000000
661 1136
662/* Interrupt clear mask */ 1137/* Interrupt clear mask */
663#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF 1138#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF
@@ -677,6 +1152,31 @@
677 1152
678#define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */ 1153#define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
679 1154
1155/* ETYPE Queue Filter/Select Bit Masks */
1156#define IXGBE_MAX_ETQF_FILTERS 8
1157#define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */
1158#define IXGBE_ETQF_1588 0x40000000 /* bit 30 */
1159#define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */
1160#define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */
1161
1162#define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */
1163#define IXGBE_ETQS_RX_QUEUE_SHIFT 16
1164#define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */
1165#define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */
1166
1167/*
1168 * ETQF filter list: one static filter per filter consumer. This is
1169 * to avoid filter collisions later. Add new filters
1170 * here!!
1171 *
1172 * Current filters:
1173 * EAPOL 802.1x (0x888e): Filter 0
1174 * BCN (0x8904): Filter 1
1175 * 1588 (0x88f7): Filter 3
1176 */
1177#define IXGBE_ETQF_FILTER_EAPOL 0
1178#define IXGBE_ETQF_FILTER_BCN 1
1179#define IXGBE_ETQF_FILTER_1588 3
680/* VLAN Control Bit Masks */ 1180/* VLAN Control Bit Masks */
681#define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */ 1181#define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */
682#define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */ 1182#define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */
@@ -684,21 +1184,28 @@
684#define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */ 1184#define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */
685#define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */ 1185#define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */
686 1186
1187/* VLAN pool filtering masks */
1188#define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */
1189#define IXGBE_VLVF_ENTRIES 64
687 1190
688#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */ 1191#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */
689 1192
690/* STATUS Bit Masks */ 1193/* STATUS Bit Masks */
691#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */ 1194#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
692#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */ 1195#define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/
1196#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */
693 1197
694#define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */ 1198#define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */
695#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */ 1199#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */
696 1200
697/* ESDP Bit Masks */ 1201/* ESDP Bit Masks */
698#define IXGBE_ESDP_SDP4 0x00000001 /* SDP4 Data Value */ 1202#define IXGBE_ESDP_SDP0 0x00000001
699#define IXGBE_ESDP_SDP5 0x00000002 /* SDP5 Data Value */ 1203#define IXGBE_ESDP_SDP1 0x00000002
1204#define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
1205#define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
1206#define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
700#define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */ 1207#define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */
701#define IXGBE_ESDP_SDP5_DIR 0x00000008 /* SDP5 IO direction */ 1208#define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */
702 1209
703/* LEDCTL Bit Masks */ 1210/* LEDCTL Bit Masks */
704#define IXGBE_LED_IVRT_BASE 0x00000040 1211#define IXGBE_LED_IVRT_BASE 0x00000040
@@ -730,9 +1237,17 @@
730#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000 1237#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
731#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000 1238#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
732#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000 1239#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
1240#define IXGBE_AUTOC_FECA 0x00040000
1241#define IXGBE_AUTOC_FECR 0x00020000
1242#define IXGBE_AUTOC_KR_SUPP 0x00010000
733#define IXGBE_AUTOC_AN_RESTART 0x00001000 1243#define IXGBE_AUTOC_AN_RESTART 0x00001000
734#define IXGBE_AUTOC_FLU 0x00000001 1244#define IXGBE_AUTOC_FLU 0x00000001
735#define IXGBE_AUTOC_LMS_SHIFT 13 1245#define IXGBE_AUTOC_LMS_SHIFT 13
1246#define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT)
1247#define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1248#define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT)
1249#define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1250#define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)
736#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT) 1251#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
737#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT) 1252#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
738#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT) 1253#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
@@ -741,15 +1256,24 @@
741#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) 1256#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
742#define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1257#define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
743 1258
744#define IXGBE_AUTOC_1G_PMA_PMD 0x00000200 1259#define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200
745#define IXGBE_AUTOC_10G_PMA_PMD 0x00000180 1260#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9
746#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7 1261#define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180
747#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9 1262#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
748#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1263#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
749#define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1264#define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
750#define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 1265#define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
751#define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1266#define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
752#define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 1267#define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1268#define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1269#define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1270
1271#define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000
1272#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000
1273#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16
1274#define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1275#define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1276#define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
753 1277
754/* LINKS Bit Masks */ 1278/* LINKS Bit Masks */
755#define IXGBE_LINKS_KX_AN_COMP 0x80000000 1279#define IXGBE_LINKS_KX_AN_COMP 0x80000000
@@ -759,6 +1283,7 @@
759#define IXGBE_LINKS_RX_MODE 0x06000000 1283#define IXGBE_LINKS_RX_MODE 0x06000000
760#define IXGBE_LINKS_TX_MODE 0x01800000 1284#define IXGBE_LINKS_TX_MODE 0x01800000
761#define IXGBE_LINKS_XGXS_EN 0x00400000 1285#define IXGBE_LINKS_XGXS_EN 0x00400000
1286#define IXGBE_LINKS_SGMII_EN 0x02000000
762#define IXGBE_LINKS_PCS_1G_EN 0x00200000 1287#define IXGBE_LINKS_PCS_1G_EN 0x00200000
763#define IXGBE_LINKS_1G_AN_EN 0x00100000 1288#define IXGBE_LINKS_1G_AN_EN 0x00100000
764#define IXGBE_LINKS_KX_AN_IDLE 0x00080000 1289#define IXGBE_LINKS_KX_AN_IDLE 0x00080000
@@ -768,6 +1293,10 @@
768#define IXGBE_LINKS_TL_FAULT 0x00001000 1293#define IXGBE_LINKS_TL_FAULT 0x00001000
769#define IXGBE_LINKS_SIGNAL 0x00000F00 1294#define IXGBE_LINKS_SIGNAL 0x00000F00
770 1295
1296#define IXGBE_LINKS_SPEED_82599 0x30000000
1297#define IXGBE_LINKS_SPEED_10G_82599 0x30000000
1298#define IXGBE_LINKS_SPEED_1G_82599 0x20000000
1299#define IXGBE_LINKS_SPEED_100_82599 0x10000000
771#define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */ 1300#define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
772#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 1301#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
773 1302
@@ -844,6 +1373,7 @@
844#define IXGBE_FW_PTR 0x0F 1373#define IXGBE_FW_PTR 0x0F
845#define IXGBE_PBANUM0_PTR 0x15 1374#define IXGBE_PBANUM0_PTR 0x15
846#define IXGBE_PBANUM1_PTR 0x16 1375#define IXGBE_PBANUM1_PTR 0x16
1376#define IXGBE_PCIE_MSIX_82599_CAPS 0x72
847#define IXGBE_PCIE_MSIX_82598_CAPS 0x62 1377#define IXGBE_PCIE_MSIX_82598_CAPS 0x62
848 1378
849/* MSI-X capability fields masks */ 1379/* MSI-X capability fields masks */
@@ -896,6 +1426,8 @@
896#define IXGBE_PCI_LINK_SPEED 0xF 1426#define IXGBE_PCI_LINK_SPEED 0xF
897#define IXGBE_PCI_LINK_SPEED_2500 0x1 1427#define IXGBE_PCI_LINK_SPEED_2500 0x1
898#define IXGBE_PCI_LINK_SPEED_5000 0x2 1428#define IXGBE_PCI_LINK_SPEED_5000 0x2
1429#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
1430#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
899 1431
900/* Number of 100 microseconds we wait for PCI Express master disable */ 1432/* Number of 100 microseconds we wait for PCI Express master disable */
901#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800 1433#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
@@ -948,6 +1480,7 @@
948#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */ 1480#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */
949#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */ 1481#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */
950#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */ 1482#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
1483#define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */
951 1484
952#define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */ 1485#define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
953#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/ 1486#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
@@ -958,9 +1491,23 @@
958/* Receive Priority Flow Control Enable */ 1491/* Receive Priority Flow Control Enable */
959#define IXGBE_FCTRL_RPFCE 0x00004000 1492#define IXGBE_FCTRL_RPFCE 0x00004000
960#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */ 1493#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
1494#define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */
1495#define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */
1496#define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */
1497#define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */
961 1498
962/* Multiple Receive Queue Control */ 1499/* Multiple Receive Queue Control */
963#define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */ 1500#define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */
1501#define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */
1502#define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */
1503#define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */
1504#define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */
1505#define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */
1506#define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */
1507#define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */
1508#define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */
1509#define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */
1510#define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */
964#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000 1511#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
965#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 1512#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
966#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000 1513#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000
@@ -971,6 +1518,12 @@
971#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 1518#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
972#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 1519#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
973#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000 1520#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
1521#define IXGBE_MRQC_L3L4TXSWEN 0x00008000
1522
1523/* Queue Drop Enable */
1524#define IXGBE_QDE_ENABLE 0x00000001
1525#define IXGBE_QDE_IDX_MASK 0x00007F00
1526#define IXGBE_QDE_IDX_SHIFT 8
974 1527
975#define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 1528#define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
976#define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 1529#define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
@@ -982,10 +1535,25 @@
982#define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 1535#define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
983#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 1536#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */
984 1537
1538#define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000
1539#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
1540#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000
1541#define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000
1542#define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000
1543/* Multiple Transmit Queue Command Register */
1544#define IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */
1545#define IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */
1546#define IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */
1547#define IXGBE_MTQC_64VF 0x8 /* 2 TX Queues per pool w/64VF's */
1548#define IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */
1549
985/* Receive Descriptor bit definitions */ 1550/* Receive Descriptor bit definitions */
986#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */ 1551#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */
987#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */ 1552#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */
1553#define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */
988#define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 1554#define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
1555#define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */
1556#define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004
989#define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 1557#define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
990#define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */ 1558#define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */
991#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 1559#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
@@ -994,6 +1562,10 @@
994#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */ 1562#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */
995#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 1563#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
996#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 1564#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
1565#define IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */
1566#define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */
1567#define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */
1568#define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */
997#define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 1569#define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
998#define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */ 1570#define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */
999#define IXGBE_RXD_ERR_LE 0x02 /* Length Error */ 1571#define IXGBE_RXD_ERR_LE 0x02 /* Length Error */
@@ -1002,6 +1574,8 @@
1002#define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */ 1574#define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */
1003#define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */ 1575#define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */
1004#define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */ 1576#define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */
1577#define IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */
1578#define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */
1005#define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */ 1579#define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */
1006#define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */ 1580#define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */
1007#define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */ 1581#define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */
@@ -1016,9 +1590,23 @@
1016#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */ 1590#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */
1017#define IXGBE_RXD_CFI_SHIFT 12 1591#define IXGBE_RXD_CFI_SHIFT 12
1018 1592
1593#define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */
1594#define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */
1595#define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */
1596#define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */
1597#define IXGBE_RXDADV_STAT_MASK 0x000fffff /* Stat/NEXTP: bit 0-19 */
1598
1599/* PSRTYPE bit definitions */
1600#define IXGBE_PSRTYPE_TCPHDR 0x00000010
1601#define IXGBE_PSRTYPE_UDPHDR 0x00000020
1602#define IXGBE_PSRTYPE_IPV4HDR 0x00000100
1603#define IXGBE_PSRTYPE_IPV6HDR 0x00000200
1019 1604
1020/* SRRCTL bit definitions */ 1605/* SRRCTL bit definitions */
1021#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */ 1606#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */
1607#define IXGBE_SRRCTL_RDMTS_SHIFT 22
1608#define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000
1609#define IXGBE_SRRCTL_DROP_EN 0x10000000
1022#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F 1610#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
1023#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00 1611#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
1024#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000 1612#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
@@ -1033,6 +1621,7 @@
1033 1621
1034#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F 1622#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F
1035#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0 1623#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0
1624#define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0
1036#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0 1625#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0
1037#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5 1626#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5
1038#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000 1627#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000
@@ -1060,6 +1649,20 @@
1060#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ 1649#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
1061#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ 1650#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
1062#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ 1651#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
1652#define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */
1653#define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */
1654#define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */
1655#define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */
1656#define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */
1657#define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */
1658
1659/* Security Processing bit Indication */
1660#define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000
1661#define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000
1662#define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000
1663#define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000
1664#define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000
1665
1063/* Masks to determine if packets should be dropped due to frame errors */ 1666/* Masks to determine if packets should be dropped due to frame errors */
1064#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \ 1667#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
1065 IXGBE_RXD_ERR_CE | \ 1668 IXGBE_RXD_ERR_CE | \
@@ -1089,6 +1692,14 @@
1089#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */ 1692#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */
1090#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 1693#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
1091 1694
1695/* Little Endian defines */
1696#ifndef __le32
1697#define __le32 u32
1698#endif
1699#ifndef __le64
1700#define __le64 u64
1701
1702#endif
1092 1703
1093/* Transmit Descriptor - Legacy */ 1704/* Transmit Descriptor - Legacy */
1094struct ixgbe_legacy_tx_desc { 1705struct ixgbe_legacy_tx_desc {
@@ -1176,6 +1787,9 @@ struct ixgbe_adv_tx_context_desc {
1176 1787
1177/* Adv Transmit Descriptor Config Masks */ 1788/* Adv Transmit Descriptor Config Masks */
1178#define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */ 1789#define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */
1790#define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */
1791#define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */
1792#define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */
1179#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */ 1793#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */
1180#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */ 1794#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */
1181#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 1795#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
@@ -1210,6 +1824,9 @@ struct ixgbe_adv_tx_context_desc {
1210#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 1824#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
1211#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ 1825#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
1212#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /*Req requires Markers and CRC*/ 1826#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /*Req requires Markers and CRC*/
1827#define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */
1828#define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
1829#define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */
1213#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 1830#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
1214#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 1831#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
1215 1832
@@ -1223,6 +1840,12 @@ typedef u32 ixgbe_link_speed;
1223#define IXGBE_LINK_SPEED_10GB_FULL 0x0080 1840#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
1224#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \ 1841#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
1225 IXGBE_LINK_SPEED_10GB_FULL) 1842 IXGBE_LINK_SPEED_10GB_FULL)
1843#define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
1844 IXGBE_LINK_SPEED_1GB_FULL | \
1845 IXGBE_LINK_SPEED_10GB_FULL)
1846
1847#define IXGBE_PCIE_DEV_CTRL_2 0xC8
1848#define PCIE_COMPL_TO_VALUE 0x05
1226 1849
1227/* Physical layer type */ 1850/* Physical layer type */
1228typedef u32 ixgbe_physical_layer; 1851typedef u32 ixgbe_physical_layer;
@@ -1239,7 +1862,6 @@ typedef u32 ixgbe_physical_layer;
1239#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200 1862#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200
1240#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400 1863#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400
1241 1864
1242
1243enum ixgbe_eeprom_type { 1865enum ixgbe_eeprom_type {
1244 ixgbe_eeprom_uninitialized = 0, 1866 ixgbe_eeprom_uninitialized = 0,
1245 ixgbe_eeprom_spi, 1867 ixgbe_eeprom_spi,
@@ -1249,12 +1871,14 @@ enum ixgbe_eeprom_type {
1249enum ixgbe_mac_type { 1871enum ixgbe_mac_type {
1250 ixgbe_mac_unknown = 0, 1872 ixgbe_mac_unknown = 0,
1251 ixgbe_mac_82598EB, 1873 ixgbe_mac_82598EB,
1874 ixgbe_mac_82599EB,
1252 ixgbe_num_macs 1875 ixgbe_num_macs
1253}; 1876};
1254 1877
1255enum ixgbe_phy_type { 1878enum ixgbe_phy_type {
1256 ixgbe_phy_unknown = 0, 1879 ixgbe_phy_unknown = 0,
1257 ixgbe_phy_tn, 1880 ixgbe_phy_tn,
1881 ixgbe_phy_cu_unknown,
1258 ixgbe_phy_qt, 1882 ixgbe_phy_qt,
1259 ixgbe_phy_xaui, 1883 ixgbe_phy_xaui,
1260 ixgbe_phy_nl, 1884 ixgbe_phy_nl,
@@ -1263,22 +1887,31 @@ enum ixgbe_phy_type {
1263 ixgbe_phy_sfp_avago, 1887 ixgbe_phy_sfp_avago,
1264 ixgbe_phy_sfp_ftl, 1888 ixgbe_phy_sfp_ftl,
1265 ixgbe_phy_sfp_unknown, 1889 ixgbe_phy_sfp_unknown,
1890 ixgbe_phy_sfp_intel,
1266 ixgbe_phy_generic 1891 ixgbe_phy_generic
1267}; 1892};
1268 1893
1269/* 1894/*
1270 * SFP+ module type IDs: 1895 * SFP+ module type IDs:
1271 * 1896 *
1272 * ID Module Type 1897 * ID Module Type
1273 * ============= 1898 * =============
1274 * 0 SFP_DA_CU 1899 * 0 SFP_DA_CU
1275 * 1 SFP_SR 1900 * 1 SFP_SR
1276 * 2 SFP_LR 1901 * 2 SFP_LR
1902 * 3 SFP_DA_CU_CORE0 - 82599-specific
1903 * 4 SFP_DA_CU_CORE1 - 82599-specific
1904 * 5 SFP_SR/LR_CORE0 - 82599-specific
1905 * 6 SFP_SR/LR_CORE1 - 82599-specific
1277 */ 1906 */
1278enum ixgbe_sfp_type { 1907enum ixgbe_sfp_type {
1279 ixgbe_sfp_type_da_cu = 0, 1908 ixgbe_sfp_type_da_cu = 0,
1280 ixgbe_sfp_type_sr = 1, 1909 ixgbe_sfp_type_sr = 1,
1281 ixgbe_sfp_type_lr = 2, 1910 ixgbe_sfp_type_lr = 2,
1911 ixgbe_sfp_type_da_cu_core0 = 3,
1912 ixgbe_sfp_type_da_cu_core1 = 4,
1913 ixgbe_sfp_type_srlr_core0 = 5,
1914 ixgbe_sfp_type_srlr_core1 = 6,
1282 ixgbe_sfp_type_not_present = 0xFFFE, 1915 ixgbe_sfp_type_not_present = 0xFFFE,
1283 ixgbe_sfp_type_unknown = 0xFFFF 1916 ixgbe_sfp_type_unknown = 0xFFFF
1284}; 1917};
@@ -1300,6 +1933,40 @@ enum ixgbe_fc_mode {
1300 ixgbe_fc_default 1933 ixgbe_fc_default
1301}; 1934};
1302 1935
1936/* PCI bus types */
1937enum ixgbe_bus_type {
1938 ixgbe_bus_type_unknown = 0,
1939 ixgbe_bus_type_pci,
1940 ixgbe_bus_type_pcix,
1941 ixgbe_bus_type_pci_express,
1942 ixgbe_bus_type_reserved
1943};
1944
1945/* PCI bus speeds */
1946enum ixgbe_bus_speed {
1947 ixgbe_bus_speed_unknown = 0,
1948 ixgbe_bus_speed_33,
1949 ixgbe_bus_speed_66,
1950 ixgbe_bus_speed_100,
1951 ixgbe_bus_speed_120,
1952 ixgbe_bus_speed_133,
1953 ixgbe_bus_speed_2500,
1954 ixgbe_bus_speed_5000,
1955 ixgbe_bus_speed_reserved
1956};
1957
1958/* PCI bus widths */
1959enum ixgbe_bus_width {
1960 ixgbe_bus_width_unknown = 0,
1961 ixgbe_bus_width_pcie_x1,
1962 ixgbe_bus_width_pcie_x2,
1963 ixgbe_bus_width_pcie_x4 = 4,
1964 ixgbe_bus_width_pcie_x8 = 8,
1965 ixgbe_bus_width_32,
1966 ixgbe_bus_width_64,
1967 ixgbe_bus_width_reserved
1968};
1969
1303struct ixgbe_addr_filter_info { 1970struct ixgbe_addr_filter_info {
1304 u32 num_mc_addrs; 1971 u32 num_mc_addrs;
1305 u32 rar_used_count; 1972 u32 rar_used_count;
@@ -1309,6 +1976,16 @@ struct ixgbe_addr_filter_info {
1309 bool user_set_promisc; 1976 bool user_set_promisc;
1310}; 1977};
1311 1978
1979/* Bus parameters */
1980struct ixgbe_bus_info {
1981 enum ixgbe_bus_speed speed;
1982 enum ixgbe_bus_width width;
1983 enum ixgbe_bus_type type;
1984
1985 u16 func;
1986 u16 lan_id;
1987};
1988
1312/* Flow control parameters */ 1989/* Flow control parameters */
1313struct ixgbe_fc_info { 1990struct ixgbe_fc_info {
1314 u32 high_water; /* Flow Control High-water */ 1991 u32 high_water; /* Flow Control High-water */
@@ -1377,6 +2054,14 @@ struct ixgbe_hw_stats {
1377 u64 qptc[16]; 2054 u64 qptc[16];
1378 u64 qbrc[16]; 2055 u64 qbrc[16];
1379 u64 qbtc[16]; 2056 u64 qbtc[16];
2057 u64 qprdc[16];
2058 u64 pxon2offc[8];
2059 u64 fdirustat_add;
2060 u64 fdirustat_remove;
2061 u64 fdirfstat_fadd;
2062 u64 fdirfstat_fremove;
2063 u64 fdirmatch;
2064 u64 fdirmiss;
1380}; 2065};
1381 2066
1382/* forward declaration */ 2067/* forward declaration */
@@ -1401,12 +2086,15 @@ struct ixgbe_mac_operations {
1401 s32 (*start_hw)(struct ixgbe_hw *); 2086 s32 (*start_hw)(struct ixgbe_hw *);
1402 s32 (*clear_hw_cntrs)(struct ixgbe_hw *); 2087 s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
1403 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *); 2088 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
1404 s32 (*get_supported_physical_layer)(struct ixgbe_hw *); 2089 u32 (*get_supported_physical_layer)(struct ixgbe_hw *);
1405 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *); 2090 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
1406 s32 (*stop_adapter)(struct ixgbe_hw *); 2091 s32 (*stop_adapter)(struct ixgbe_hw *);
1407 s32 (*get_bus_info)(struct ixgbe_hw *); 2092 s32 (*get_bus_info)(struct ixgbe_hw *);
2093 void (*set_lan_id)(struct ixgbe_hw *);
1408 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*); 2094 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
1409 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8); 2095 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
2096 s32 (*setup_sfp)(struct ixgbe_hw *);
2097 s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
1410 2098
1411 /* Link */ 2099 /* Link */
1412 s32 (*setup_link)(struct ixgbe_hw *); 2100 s32 (*setup_link)(struct ixgbe_hw *);
@@ -1462,7 +2150,7 @@ struct ixgbe_phy_operations {
1462struct ixgbe_eeprom_info { 2150struct ixgbe_eeprom_info {
1463 struct ixgbe_eeprom_operations ops; 2151 struct ixgbe_eeprom_operations ops;
1464 enum ixgbe_eeprom_type type; 2152 enum ixgbe_eeprom_type type;
1465 u32 semaphore_delay; 2153 u32 semaphore_delay;
1466 u16 word_size; 2154 u16 word_size;
1467 u16 address_bits; 2155 u16 address_bits;
1468}; 2156};
@@ -1508,6 +2196,7 @@ struct ixgbe_hw {
1508 struct ixgbe_fc_info fc; 2196 struct ixgbe_fc_info fc;
1509 struct ixgbe_phy_info phy; 2197 struct ixgbe_phy_info phy;
1510 struct ixgbe_eeprom_info eeprom; 2198 struct ixgbe_eeprom_info eeprom;
2199 struct ixgbe_bus_info bus;
1511 u16 device_id; 2200 u16 device_id;
1512 u16 vendor_id; 2201 u16 vendor_id;
1513 u16 subsystem_device_id; 2202 u16 subsystem_device_id;
@@ -1546,6 +2235,7 @@ struct ixgbe_info {
1546#define IXGBE_ERR_I2C -18 2235#define IXGBE_ERR_I2C -18
1547#define IXGBE_ERR_SFP_NOT_SUPPORTED -19 2236#define IXGBE_ERR_SFP_NOT_SUPPORTED -19
1548#define IXGBE_ERR_SFP_NOT_PRESENT -20 2237#define IXGBE_ERR_SFP_NOT_PRESENT -20
2238#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21
1549#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF 2239#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
1550 2240
1551#endif /* _IXGBE_TYPE_H_ */ 2241#endif /* _IXGBE_TYPE_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 12:29:33 -0500