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authorClaudio Lanconelli <lanconelli.claudio@eptar.com>2008-01-14 05:00:28 -0500
committerDavid S. Miller <davem@davemloft.net>2008-01-28 18:08:03 -0500
commit3ec9c11da03342b556f11724ea005e60160bc744 (patch)
treee8972ea222a0b73c8f55cab4fe9124da7da33590 /drivers/net
parenta24a789cc6b0a736759bd221b0a32f9a240c2f6e (diff)
add driver for enc28j60 ethernet chip
Signed-off-by: Claudio Lanconelli <lanconelli.claudio@eptar.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/Kconfig18
-rw-r--r--drivers/net/Makefile1
-rw-r--r--drivers/net/enc28j60.c1600
-rw-r--r--drivers/net/enc28j60_hw.h309
4 files changed, 1928 insertions, 0 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 9d8c5fc822fe..f87d9ff3311a 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -912,6 +912,24 @@ config DM9000
912 To compile this driver as a module, choose M here. The module 912 To compile this driver as a module, choose M here. The module
913 will be called dm9000. 913 will be called dm9000.
914 914
915config ENC28J60
916 tristate "ENC28J60 support"
917 depends on EXPERIMENTAL && SPI && NET_ETHERNET
918 select CRC32
919 ---help---
920 Support for the Microchip EN28J60 ethernet chip.
921
922 To compile this driver as a module, choose M here and read
923 <file:Documentation/networking/net-modules.txt>. The module will be
924 called enc28j60.
925
926config ENC28J60_WRITEVERIFY
927 bool "Enable write verify"
928 depends on ENC28J60
929 ---help---
930 Enable the verify after the buffer write useful for debugging purpose.
931 If unsure, say N.
932
915config SMC911X 933config SMC911X
916 tristate "SMSC LAN911[5678] support" 934 tristate "SMSC LAN911[5678] support"
917 select CRC32 935 select CRC32
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 5e36f203ce5c..79fe3f158af1 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -218,6 +218,7 @@ obj-$(CONFIG_DM9000) += dm9000.o
218obj-$(CONFIG_FEC_8XX) += fec_8xx/ 218obj-$(CONFIG_FEC_8XX) += fec_8xx/
219obj-$(CONFIG_PASEMI_MAC) += pasemi_mac.o 219obj-$(CONFIG_PASEMI_MAC) += pasemi_mac.o
220obj-$(CONFIG_MLX4_CORE) += mlx4/ 220obj-$(CONFIG_MLX4_CORE) += mlx4/
221obj-$(CONFIG_ENC28J60) += enc28j60.o
221 222
222obj-$(CONFIG_MACB) += macb.o 223obj-$(CONFIG_MACB) += macb.o
223 224
diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c
new file mode 100644
index 000000000000..0809a6a5a286
--- /dev/null
+++ b/drivers/net/enc28j60.c
@@ -0,0 +1,1600 @@
1/*
2 * Microchip ENC28J60 ethernet driver (MAC + PHY)
3 *
4 * Copyright (C) 2007 Eurek srl
5 * Author: Claudio Lanconelli <lanconelli.claudio@eptar.com>
6 * based on enc28j60.c written by David Anders for 2.4 kernel version
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * $Id: enc28j60.c,v 1.22 2007/12/20 10:47:01 claudio Exp $
14 */
15
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/fcntl.h>
20#include <linux/interrupt.h>
21#include <linux/slab.h>
22#include <linux/string.h>
23#include <linux/errno.h>
24#include <linux/init.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/ethtool.h>
28#include <linux/tcp.h>
29#include <linux/skbuff.h>
30#include <linux/delay.h>
31#include <linux/spi/spi.h>
32
33#include "enc28j60_hw.h"
34
35#define DRV_NAME "enc28j60"
36#define DRV_VERSION "1.01"
37
38#define SPI_OPLEN 1
39
40#define ENC28J60_MSG_DEFAULT \
41 (NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK)
42
43/* Buffer size required for the largest SPI transfer (i.e., reading a
44 * frame). */
45#define SPI_TRANSFER_BUF_LEN (4 + MAX_FRAMELEN)
46
47#define TX_TIMEOUT (4 * HZ)
48
49/* Max TX retries in case of collision as suggested by errata datasheet */
50#define MAX_TX_RETRYCOUNT 16
51
52enum {
53 RXFILTER_NORMAL,
54 RXFILTER_MULTI,
55 RXFILTER_PROMISC
56};
57
58/* Driver local data */
59struct enc28j60_net {
60 struct net_device *netdev;
61 struct spi_device *spi;
62 struct mutex lock;
63 struct sk_buff *tx_skb;
64 struct work_struct tx_work;
65 struct work_struct irq_work;
66 struct work_struct setrx_work;
67 struct work_struct restart_work;
68 u8 bank; /* current register bank selected */
69 u16 next_pk_ptr; /* next packet pointer within FIFO */
70 u16 max_pk_counter; /* statistics: max packet counter */
71 u16 tx_retry_count;
72 bool hw_enable;
73 bool full_duplex;
74 int rxfilter;
75 u32 msg_enable;
76 u8 spi_transfer_buf[SPI_TRANSFER_BUF_LEN];
77};
78
79/* use ethtool to change the level for any given device */
80static struct {
81 u32 msg_enable;
82} debug = { -1 };
83
84/*
85 * SPI read buffer
86 * wait for the SPI transfer and copy received data to destination
87 */
88static int
89spi_read_buf(struct enc28j60_net *priv, int len, u8 *data)
90{
91 u8 *rx_buf = priv->spi_transfer_buf + 4;
92 u8 *tx_buf = priv->spi_transfer_buf;
93 struct spi_transfer t = {
94 .tx_buf = tx_buf,
95 .rx_buf = rx_buf,
96 .len = SPI_OPLEN + len,
97 };
98 struct spi_message msg;
99 int ret;
100
101 tx_buf[0] = ENC28J60_READ_BUF_MEM;
102 tx_buf[1] = tx_buf[2] = tx_buf[3] = 0; /* don't care */
103
104 spi_message_init(&msg);
105 spi_message_add_tail(&t, &msg);
106 ret = spi_sync(priv->spi, &msg);
107 if (ret == 0) {
108 memcpy(data, &rx_buf[SPI_OPLEN], len);
109 ret = msg.status;
110 }
111 if (ret && netif_msg_drv(priv))
112 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
113 __FUNCTION__, ret);
114
115 return ret;
116}
117
118/*
119 * SPI write buffer
120 */
121static int spi_write_buf(struct enc28j60_net *priv, int len,
122 const u8 *data)
123{
124 int ret;
125
126 if (len > SPI_TRANSFER_BUF_LEN - 1 || len <= 0)
127 ret = -EINVAL;
128 else {
129 priv->spi_transfer_buf[0] = ENC28J60_WRITE_BUF_MEM;
130 memcpy(&priv->spi_transfer_buf[1], data, len);
131 ret = spi_write(priv->spi, priv->spi_transfer_buf, len + 1);
132 if (ret && netif_msg_drv(priv))
133 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
134 __FUNCTION__, ret);
135 }
136 return ret;
137}
138
139/*
140 * basic SPI read operation
141 */
142static u8 spi_read_op(struct enc28j60_net *priv, u8 op,
143 u8 addr)
144{
145 u8 tx_buf[2];
146 u8 rx_buf[4];
147 u8 val = 0;
148 int ret;
149 int slen = SPI_OPLEN;
150
151 /* do dummy read if needed */
152 if (addr & SPRD_MASK)
153 slen++;
154
155 tx_buf[0] = op | (addr & ADDR_MASK);
156 ret = spi_write_then_read(priv->spi, tx_buf, 1, rx_buf, slen);
157 if (ret)
158 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
159 __FUNCTION__, ret);
160 else
161 val = rx_buf[slen - 1];
162
163 return val;
164}
165
166/*
167 * basic SPI write operation
168 */
169static int spi_write_op(struct enc28j60_net *priv, u8 op,
170 u8 addr, u8 val)
171{
172 int ret;
173
174 priv->spi_transfer_buf[0] = op | (addr & ADDR_MASK);
175 priv->spi_transfer_buf[1] = val;
176 ret = spi_write(priv->spi, priv->spi_transfer_buf, 2);
177 if (ret && netif_msg_drv(priv))
178 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
179 __FUNCTION__, ret);
180 return ret;
181}
182
183static void enc28j60_soft_reset(struct enc28j60_net *priv)
184{
185 if (netif_msg_hw(priv))
186 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __FUNCTION__);
187
188 spi_write_op(priv, ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
189 /* Errata workaround #1, CLKRDY check is unreliable,
190 * delay at least 1 mS instead */
191 udelay(2000);
192}
193
194/*
195 * select the current register bank if necessary
196 */
197static void enc28j60_set_bank(struct enc28j60_net *priv, u8 addr)
198{
199 if ((addr & BANK_MASK) != priv->bank) {
200 u8 b = (addr & BANK_MASK) >> 5;
201
202 if (b != (ECON1_BSEL1 | ECON1_BSEL0))
203 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
204 ECON1_BSEL1 | ECON1_BSEL0);
205 if (b != 0)
206 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1, b);
207 priv->bank = (addr & BANK_MASK);
208 }
209}
210
211/*
212 * Register access routines through the SPI bus.
213 * Every register access comes in two flavours:
214 * - nolock_xxx: caller needs to invoke mutex_lock, usually to access
215 * atomically more than one register
216 * - locked_xxx: caller doesn't need to invoke mutex_lock, single access
217 *
218 * Some registers can be accessed through the bit field clear and
219 * bit field set to avoid a read modify write cycle.
220 */
221
222/*
223 * Register bit field Set
224 */
225static void nolock_reg_bfset(struct enc28j60_net *priv,
226 u8 addr, u8 mask)
227{
228 enc28j60_set_bank(priv, addr);
229 spi_write_op(priv, ENC28J60_BIT_FIELD_SET, addr, mask);
230}
231
232static void locked_reg_bfset(struct enc28j60_net *priv,
233 u8 addr, u8 mask)
234{
235 mutex_lock(&priv->lock);
236 nolock_reg_bfset(priv, addr, mask);
237 mutex_unlock(&priv->lock);
238}
239
240/*
241 * Register bit field Clear
242 */
243static void nolock_reg_bfclr(struct enc28j60_net *priv,
244 u8 addr, u8 mask)
245{
246 enc28j60_set_bank(priv, addr);
247 spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, addr, mask);
248}
249
250static void locked_reg_bfclr(struct enc28j60_net *priv,
251 u8 addr, u8 mask)
252{
253 mutex_lock(&priv->lock);
254 nolock_reg_bfclr(priv, addr, mask);
255 mutex_unlock(&priv->lock);
256}
257
258/*
259 * Register byte read
260 */
261static int nolock_regb_read(struct enc28j60_net *priv,
262 u8 address)
263{
264 enc28j60_set_bank(priv, address);
265 return spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
266}
267
268static int locked_regb_read(struct enc28j60_net *priv,
269 u8 address)
270{
271 int ret;
272
273 mutex_lock(&priv->lock);
274 ret = nolock_regb_read(priv, address);
275 mutex_unlock(&priv->lock);
276
277 return ret;
278}
279
280/*
281 * Register word read
282 */
283static int nolock_regw_read(struct enc28j60_net *priv,
284 u8 address)
285{
286 int rl, rh;
287
288 enc28j60_set_bank(priv, address);
289 rl = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
290 rh = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address + 1);
291
292 return (rh << 8) | rl;
293}
294
295static int locked_regw_read(struct enc28j60_net *priv,
296 u8 address)
297{
298 int ret;
299
300 mutex_lock(&priv->lock);
301 ret = nolock_regw_read(priv, address);
302 mutex_unlock(&priv->lock);
303
304 return ret;
305}
306
307/*
308 * Register byte write
309 */
310static void nolock_regb_write(struct enc28j60_net *priv,
311 u8 address, u8 data)
312{
313 enc28j60_set_bank(priv, address);
314 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, data);
315}
316
317static void locked_regb_write(struct enc28j60_net *priv,
318 u8 address, u8 data)
319{
320 mutex_lock(&priv->lock);
321 nolock_regb_write(priv, address, data);
322 mutex_unlock(&priv->lock);
323}
324
325/*
326 * Register word write
327 */
328static void nolock_regw_write(struct enc28j60_net *priv,
329 u8 address, u16 data)
330{
331 enc28j60_set_bank(priv, address);
332 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, (u8) data);
333 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address + 1,
334 (u8) (data >> 8));
335}
336
337static void locked_regw_write(struct enc28j60_net *priv,
338 u8 address, u16 data)
339{
340 mutex_lock(&priv->lock);
341 nolock_regw_write(priv, address, data);
342 mutex_unlock(&priv->lock);
343}
344
345/*
346 * Buffer memory read
347 * Select the starting address and execute a SPI buffer read
348 */
349static void enc28j60_mem_read(struct enc28j60_net *priv,
350 u16 addr, int len, u8 *data)
351{
352 mutex_lock(&priv->lock);
353 nolock_regw_write(priv, ERDPTL, addr);
354#ifdef CONFIG_ENC28J60_WRITEVERIFY
355 if (netif_msg_drv(priv)) {
356 u16 reg;
357 reg = nolock_regw_read(priv, ERDPTL);
358 if (reg != addr)
359 printk(KERN_DEBUG DRV_NAME ": %s() error writing ERDPT "
360 "(0x%04x - 0x%04x)\n", __FUNCTION__, reg, addr);
361 }
362#endif
363 spi_read_buf(priv, len, data);
364 mutex_unlock(&priv->lock);
365}
366
367/*
368 * Write packet to enc28j60 TX buffer memory
369 */
370static void
371enc28j60_packet_write(struct enc28j60_net *priv, int len, const u8 *data)
372{
373 mutex_lock(&priv->lock);
374 /* Set the write pointer to start of transmit buffer area */
375 nolock_regw_write(priv, EWRPTL, TXSTART_INIT);
376#ifdef CONFIG_ENC28J60_WRITEVERIFY
377 if (netif_msg_drv(priv)) {
378 u16 reg;
379 reg = nolock_regw_read(priv, EWRPTL);
380 if (reg != TXSTART_INIT)
381 printk(KERN_DEBUG DRV_NAME
382 ": %s() ERWPT:0x%04x != 0x%04x\n",
383 __FUNCTION__, reg, TXSTART_INIT);
384 }
385#endif
386 /* Set the TXND pointer to correspond to the packet size given */
387 nolock_regw_write(priv, ETXNDL, TXSTART_INIT + len);
388 /* write per-packet control byte */
389 spi_write_op(priv, ENC28J60_WRITE_BUF_MEM, 0, 0x00);
390 if (netif_msg_hw(priv))
391 printk(KERN_DEBUG DRV_NAME
392 ": %s() after control byte ERWPT:0x%04x\n",
393 __FUNCTION__, nolock_regw_read(priv, EWRPTL));
394 /* copy the packet into the transmit buffer */
395 spi_write_buf(priv, len, data);
396 if (netif_msg_hw(priv))
397 printk(KERN_DEBUG DRV_NAME
398 ": %s() after write packet ERWPT:0x%04x, len=%d\n",
399 __FUNCTION__, nolock_regw_read(priv, EWRPTL), len);
400 mutex_unlock(&priv->lock);
401}
402
403/*
404 * Wait until the PHY operation is complete.
405 */
406static int wait_phy_ready(struct enc28j60_net *priv)
407{
408 unsigned long timeout = jiffies + 20 * HZ / 1000;
409 int ret = 1;
410
411 /* 20 msec timeout read */
412 while (nolock_regb_read(priv, MISTAT) & MISTAT_BUSY) {
413 if (time_after(jiffies, timeout)) {
414 if (netif_msg_drv(priv))
415 printk(KERN_DEBUG DRV_NAME
416 ": PHY ready timeout!\n");
417 ret = 0;
418 break;
419 }
420 cpu_relax();
421 }
422 return ret;
423}
424
425/*
426 * PHY register read
427 * PHY registers are not accessed directly, but through the MII
428 */
429static u16 enc28j60_phy_read(struct enc28j60_net *priv, u8 address)
430{
431 u16 ret;
432
433 mutex_lock(&priv->lock);
434 /* set the PHY register address */
435 nolock_regb_write(priv, MIREGADR, address);
436 /* start the register read operation */
437 nolock_regb_write(priv, MICMD, MICMD_MIIRD);
438 /* wait until the PHY read completes */
439 wait_phy_ready(priv);
440 /* quit reading */
441 nolock_regb_write(priv, MICMD, 0x00);
442 /* return the data */
443 ret = nolock_regw_read(priv, MIRDL);
444 mutex_unlock(&priv->lock);
445
446 return ret;
447}
448
449static int enc28j60_phy_write(struct enc28j60_net *priv, u8 address, u16 data)
450{
451 int ret;
452
453 mutex_lock(&priv->lock);
454 /* set the PHY register address */
455 nolock_regb_write(priv, MIREGADR, address);
456 /* write the PHY data */
457 nolock_regw_write(priv, MIWRL, data);
458 /* wait until the PHY write completes and return */
459 ret = wait_phy_ready(priv);
460 mutex_unlock(&priv->lock);
461
462 return ret;
463}
464
465/*
466 * Program the hardware MAC address from dev->dev_addr.
467 */
468static int enc28j60_set_hw_macaddr(struct net_device *ndev)
469{
470 int ret;
471 struct enc28j60_net *priv = netdev_priv(ndev);
472
473 mutex_lock(&priv->lock);
474 if (!priv->hw_enable) {
475 if (netif_msg_drv(priv)) {
476 DECLARE_MAC_BUF(mac);
477 printk(KERN_INFO DRV_NAME
478 ": %s: Setting MAC address to %s\n",
479 ndev->name, print_mac(mac, ndev->dev_addr));
480 }
481 /* NOTE: MAC address in ENC28J60 is byte-backward */
482 nolock_regb_write(priv, MAADR5, ndev->dev_addr[0]);
483 nolock_regb_write(priv, MAADR4, ndev->dev_addr[1]);
484 nolock_regb_write(priv, MAADR3, ndev->dev_addr[2]);
485 nolock_regb_write(priv, MAADR2, ndev->dev_addr[3]);
486 nolock_regb_write(priv, MAADR1, ndev->dev_addr[4]);
487 nolock_regb_write(priv, MAADR0, ndev->dev_addr[5]);
488 ret = 0;
489 } else {
490 if (netif_msg_drv(priv))
491 printk(KERN_DEBUG DRV_NAME
492 ": %s() Hardware must be disabled to set "
493 "Mac address\n", __FUNCTION__);
494 ret = -EBUSY;
495 }
496 mutex_unlock(&priv->lock);
497 return ret;
498}
499
500/*
501 * Store the new hardware address in dev->dev_addr, and update the MAC.
502 */
503static int enc28j60_set_mac_address(struct net_device *dev, void *addr)
504{
505 struct sockaddr *address = addr;
506
507 if (netif_running(dev))
508 return -EBUSY;
509 if (!is_valid_ether_addr(address->sa_data))
510 return -EADDRNOTAVAIL;
511
512 memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
513 return enc28j60_set_hw_macaddr(dev);
514}
515
516/*
517 * Debug routine to dump useful register contents
518 */
519static void enc28j60_dump_regs(struct enc28j60_net *priv, const char *msg)
520{
521 mutex_lock(&priv->lock);
522 printk(KERN_DEBUG DRV_NAME " %s\n"
523 "HwRevID: 0x%02x\n"
524 "Cntrl: ECON1 ECON2 ESTAT EIR EIE\n"
525 " 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n"
526 "MAC : MACON1 MACON3 MACON4\n"
527 " 0x%02x 0x%02x 0x%02x\n"
528 "Rx : ERXST ERXND ERXWRPT ERXRDPT ERXFCON EPKTCNT MAMXFL\n"
529 " 0x%04x 0x%04x 0x%04x 0x%04x "
530 "0x%02x 0x%02x 0x%04x\n"
531 "Tx : ETXST ETXND MACLCON1 MACLCON2 MAPHSUP\n"
532 " 0x%04x 0x%04x 0x%02x 0x%02x 0x%02x\n",
533 msg, nolock_regb_read(priv, EREVID),
534 nolock_regb_read(priv, ECON1), nolock_regb_read(priv, ECON2),
535 nolock_regb_read(priv, ESTAT), nolock_regb_read(priv, EIR),
536 nolock_regb_read(priv, EIE), nolock_regb_read(priv, MACON1),
537 nolock_regb_read(priv, MACON3), nolock_regb_read(priv, MACON4),
538 nolock_regw_read(priv, ERXSTL), nolock_regw_read(priv, ERXNDL),
539 nolock_regw_read(priv, ERXWRPTL),
540 nolock_regw_read(priv, ERXRDPTL),
541 nolock_regb_read(priv, ERXFCON),
542 nolock_regb_read(priv, EPKTCNT),
543 nolock_regw_read(priv, MAMXFLL), nolock_regw_read(priv, ETXSTL),
544 nolock_regw_read(priv, ETXNDL),
545 nolock_regb_read(priv, MACLCON1),
546 nolock_regb_read(priv, MACLCON2),
547 nolock_regb_read(priv, MAPHSUP));
548 mutex_unlock(&priv->lock);
549}
550
551/*
552 * ERXRDPT need to be set always at odd addresses, refer to errata datasheet
553 */
554static u16 erxrdpt_workaround(u16 next_packet_ptr, u16 start, u16 end)
555{
556 u16 erxrdpt;
557
558 if ((next_packet_ptr - 1 < start) || (next_packet_ptr - 1 > end))
559 erxrdpt = end;
560 else
561 erxrdpt = next_packet_ptr - 1;
562
563 return erxrdpt;
564}
565
566static void nolock_rxfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
567{
568 u16 erxrdpt;
569
570 if (start > 0x1FFF || end > 0x1FFF || start > end) {
571 if (netif_msg_drv(priv))
572 printk(KERN_ERR DRV_NAME ": %s(%d, %d) RXFIFO "
573 "bad parameters!\n", __FUNCTION__, start, end);
574 return;
575 }
576 /* set receive buffer start + end */
577 priv->next_pk_ptr = start;
578 nolock_regw_write(priv, ERXSTL, start);
579 erxrdpt = erxrdpt_workaround(priv->next_pk_ptr, start, end);
580 nolock_regw_write(priv, ERXRDPTL, erxrdpt);
581 nolock_regw_write(priv, ERXNDL, end);
582}
583
584static void nolock_txfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
585{
586 if (start > 0x1FFF || end > 0x1FFF || start > end) {
587 if (netif_msg_drv(priv))
588 printk(KERN_ERR DRV_NAME ": %s(%d, %d) TXFIFO "
589 "bad parameters!\n", __FUNCTION__, start, end);
590 return;
591 }
592 /* set transmit buffer start + end */
593 nolock_regw_write(priv, ETXSTL, start);
594 nolock_regw_write(priv, ETXNDL, end);
595}
596
597static int enc28j60_hw_init(struct enc28j60_net *priv)
598{
599 u8 reg;
600
601 if (netif_msg_drv(priv))
602 printk(KERN_DEBUG DRV_NAME ": %s() - %s\n", __FUNCTION__,
603 priv->full_duplex ? "FullDuplex" : "HalfDuplex");
604
605 mutex_lock(&priv->lock);
606 /* first reset the chip */
607 enc28j60_soft_reset(priv);
608 /* Clear ECON1 */
609 spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, ECON1, 0x00);
610 priv->bank = 0;
611 priv->hw_enable = false;
612 priv->tx_retry_count = 0;
613 priv->max_pk_counter = 0;
614 priv->rxfilter = RXFILTER_NORMAL;
615 /* enable address auto increment */
616 nolock_regb_write(priv, ECON2, ECON2_AUTOINC);
617
618 nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
619 nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
620 mutex_unlock(&priv->lock);
621
622 /*
623 * Check the RevID.
624 * If it's 0x00 or 0xFF probably the enc28j60 is not mounted or
625 * damaged
626 */
627 reg = locked_regb_read(priv, EREVID);
628 if (netif_msg_drv(priv))
629 printk(KERN_INFO DRV_NAME ": chip RevID: 0x%02x\n", reg);
630 if (reg == 0x00 || reg == 0xff) {
631 if (netif_msg_drv(priv))
632 printk(KERN_DEBUG DRV_NAME ": %s() Invalid RevId %d\n",
633 __FUNCTION__, reg);
634 return 0;
635 }
636
637 /* default filter mode: (unicast OR broadcast) AND crc valid */
638 locked_regb_write(priv, ERXFCON,
639 ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN);
640
641 /* enable MAC receive */
642 locked_regb_write(priv, MACON1,
643 MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);
644 /* enable automatic padding and CRC operations */
645 if (priv->full_duplex) {
646 locked_regb_write(priv, MACON3,
647 MACON3_PADCFG0 | MACON3_TXCRCEN |
648 MACON3_FRMLNEN | MACON3_FULDPX);
649 /* set inter-frame gap (non-back-to-back) */
650 locked_regb_write(priv, MAIPGL, 0x12);
651 /* set inter-frame gap (back-to-back) */
652 locked_regb_write(priv, MABBIPG, 0x15);
653 } else {
654 locked_regb_write(priv, MACON3,
655 MACON3_PADCFG0 | MACON3_TXCRCEN |
656 MACON3_FRMLNEN);
657 locked_regb_write(priv, MACON4, 1 << 6); /* DEFER bit */
658 /* set inter-frame gap (non-back-to-back) */
659 locked_regw_write(priv, MAIPGL, 0x0C12);
660 /* set inter-frame gap (back-to-back) */
661 locked_regb_write(priv, MABBIPG, 0x12);
662 }
663 /*
664 * MACLCON1 (default)
665 * MACLCON2 (default)
666 * Set the maximum packet size which the controller will accept
667 */
668 locked_regw_write(priv, MAMXFLL, MAX_FRAMELEN);
669
670 /* Configure LEDs */
671 if (!enc28j60_phy_write(priv, PHLCON, ENC28J60_LAMPS_MODE))
672 return 0;
673
674 if (priv->full_duplex) {
675 if (!enc28j60_phy_write(priv, PHCON1, PHCON1_PDPXMD))
676 return 0;
677 if (!enc28j60_phy_write(priv, PHCON2, 0x00))
678 return 0;
679 } else {
680 if (!enc28j60_phy_write(priv, PHCON1, 0x00))
681 return 0;
682 if (!enc28j60_phy_write(priv, PHCON2, PHCON2_HDLDIS))
683 return 0;
684 }
685 if (netif_msg_hw(priv))
686 enc28j60_dump_regs(priv, "Hw initialized.");
687
688 return 1;
689}
690
691static void enc28j60_hw_enable(struct enc28j60_net *priv)
692{
693 /* enable interrutps */
694 if (netif_msg_hw(priv))
695 printk(KERN_DEBUG DRV_NAME ": %s() enabling interrupts.\n",
696 __FUNCTION__);
697
698 enc28j60_phy_write(priv, PHIE, PHIE_PGEIE | PHIE_PLNKIE);
699
700 mutex_lock(&priv->lock);
701 nolock_reg_bfclr(priv, EIR, EIR_DMAIF | EIR_LINKIF |
702 EIR_TXIF | EIR_TXERIF | EIR_RXERIF | EIR_PKTIF);
703 nolock_regb_write(priv, EIE, EIE_INTIE | EIE_PKTIE | EIE_LINKIE |
704 EIE_TXIE | EIE_TXERIE | EIE_RXERIE);
705
706 /* enable receive logic */
707 nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
708 priv->hw_enable = true;
709 mutex_unlock(&priv->lock);
710}
711
712static void enc28j60_hw_disable(struct enc28j60_net *priv)
713{
714 mutex_lock(&priv->lock);
715 /* disable interrutps and packet reception */
716 nolock_regb_write(priv, EIE, 0x00);
717 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
718 priv->hw_enable = false;
719 mutex_unlock(&priv->lock);
720}
721
722static int
723enc28j60_setlink(struct net_device *ndev, u8 autoneg, u16 speed, u8 duplex)
724{
725 struct enc28j60_net *priv = netdev_priv(ndev);
726 int ret = 0;
727
728 if (!priv->hw_enable) {
729 if (autoneg == AUTONEG_DISABLE && speed == SPEED_10) {
730 priv->full_duplex = (duplex == DUPLEX_FULL);
731 if (!enc28j60_hw_init(priv)) {
732 if (netif_msg_drv(priv))
733 dev_err(&ndev->dev,
734 "hw_reset() failed\n");
735 ret = -EINVAL;
736 }
737 } else {
738 if (netif_msg_link(priv))
739 dev_warn(&ndev->dev,
740 "unsupported link setting\n");
741 ret = -EOPNOTSUPP;
742 }
743 } else {
744 if (netif_msg_link(priv))
745 dev_warn(&ndev->dev, "Warning: hw must be disabled "
746 "to set link mode\n");
747 ret = -EBUSY;
748 }
749 return ret;
750}
751
752/*
753 * Read the Transmit Status Vector
754 */
755static void enc28j60_read_tsv(struct enc28j60_net *priv, u8 tsv[TSV_SIZE])
756{
757 int endptr;
758
759 endptr = locked_regw_read(priv, ETXNDL);
760 if (netif_msg_hw(priv))
761 printk(KERN_DEBUG DRV_NAME ": reading TSV at addr:0x%04x\n",
762 endptr + 1);
763 enc28j60_mem_read(priv, endptr + 1, sizeof(tsv), tsv);
764}
765
766static void enc28j60_dump_tsv(struct enc28j60_net *priv, const char *msg,
767 u8 tsv[TSV_SIZE])
768{
769 u16 tmp1, tmp2;
770
771 printk(KERN_DEBUG DRV_NAME ": %s - TSV:\n", msg);
772 tmp1 = tsv[1];
773 tmp1 <<= 8;
774 tmp1 |= tsv[0];
775
776 tmp2 = tsv[5];
777 tmp2 <<= 8;
778 tmp2 |= tsv[4];
779
780 printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, CollisionCount: %d,"
781 " TotByteOnWire: %d\n", tmp1, tsv[2] & 0x0f, tmp2);
782 printk(KERN_DEBUG DRV_NAME ": TxDone: %d, CRCErr:%d, LenChkErr: %d,"
783 " LenOutOfRange: %d\n", TSV_GETBIT(tsv, TSV_TXDONE),
784 TSV_GETBIT(tsv, TSV_TXCRCERROR),
785 TSV_GETBIT(tsv, TSV_TXLENCHKERROR),
786 TSV_GETBIT(tsv, TSV_TXLENOUTOFRANGE));
787 printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, "
788 "PacketDefer: %d, ExDefer: %d\n",
789 TSV_GETBIT(tsv, TSV_TXMULTICAST),
790 TSV_GETBIT(tsv, TSV_TXBROADCAST),
791 TSV_GETBIT(tsv, TSV_TXPACKETDEFER),
792 TSV_GETBIT(tsv, TSV_TXEXDEFER));
793 printk(KERN_DEBUG DRV_NAME ": ExCollision: %d, LateCollision: %d, "
794 "Giant: %d, Underrun: %d\n",
795 TSV_GETBIT(tsv, TSV_TXEXCOLLISION),
796 TSV_GETBIT(tsv, TSV_TXLATECOLLISION),
797 TSV_GETBIT(tsv, TSV_TXGIANT), TSV_GETBIT(tsv, TSV_TXUNDERRUN));
798 printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d, "
799 "BackPressApp: %d, VLanTagFrame: %d\n",
800 TSV_GETBIT(tsv, TSV_TXCONTROLFRAME),
801 TSV_GETBIT(tsv, TSV_TXPAUSEFRAME),
802 TSV_GETBIT(tsv, TSV_BACKPRESSUREAPP),
803 TSV_GETBIT(tsv, TSV_TXVLANTAGFRAME));
804}
805
806/*
807 * Receive Status vector
808 */
809static void enc28j60_dump_rsv(struct enc28j60_net *priv, const char *msg,
810 u16 pk_ptr, int len, u16 sts)
811{
812 printk(KERN_DEBUG DRV_NAME ": %s - NextPk: 0x%04x - RSV:\n",
813 msg, pk_ptr);
814 printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, DribbleNibble: %d\n", len,
815 RSV_GETBIT(sts, RSV_DRIBBLENIBBLE));
816 printk(KERN_DEBUG DRV_NAME ": RxOK: %d, CRCErr:%d, LenChkErr: %d,"
817 " LenOutOfRange: %d\n", RSV_GETBIT(sts, RSV_RXOK),
818 RSV_GETBIT(sts, RSV_CRCERROR),
819 RSV_GETBIT(sts, RSV_LENCHECKERR),
820 RSV_GETBIT(sts, RSV_LENOUTOFRANGE));
821 printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, "
822 "LongDropEvent: %d, CarrierEvent: %d\n",
823 RSV_GETBIT(sts, RSV_RXMULTICAST),
824 RSV_GETBIT(sts, RSV_RXBROADCAST),
825 RSV_GETBIT(sts, RSV_RXLONGEVDROPEV),
826 RSV_GETBIT(sts, RSV_CARRIEREV));
827 printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d,"
828 " UnknownOp: %d, VLanTagFrame: %d\n",
829 RSV_GETBIT(sts, RSV_RXCONTROLFRAME),
830 RSV_GETBIT(sts, RSV_RXPAUSEFRAME),
831 RSV_GETBIT(sts, RSV_RXUNKNOWNOPCODE),
832 RSV_GETBIT(sts, RSV_RXTYPEVLAN));
833}
834
835static void dump_packet(const char *msg, int len, const char *data)
836{
837 printk(KERN_DEBUG DRV_NAME ": %s - packet len:%d\n", msg, len);
838 print_hex_dump(KERN_DEBUG, "pk data: ", DUMP_PREFIX_OFFSET, 16, 1,
839 data, len, true);
840}
841
842/*
843 * Hardware receive function.
844 * Read the buffer memory, update the FIFO pointer to free the buffer,
845 * check the status vector and decrement the packet counter.
846 */
847static void enc28j60_hw_rx(struct net_device *ndev)
848{
849 struct enc28j60_net *priv = netdev_priv(ndev);
850 struct sk_buff *skb = NULL;
851 u16 erxrdpt, next_packet, rxstat;
852 u8 rsv[RSV_SIZE];
853 int len;
854
855 if (netif_msg_rx_status(priv))
856 printk(KERN_DEBUG DRV_NAME ": RX pk_addr:0x%04x\n",
857 priv->next_pk_ptr);
858
859 if (unlikely(priv->next_pk_ptr > RXEND_INIT)) {
860 if (netif_msg_rx_err(priv))
861 dev_err(&ndev->dev,
862 "%s() Invalid packet address!! 0x%04x\n",
863 __FUNCTION__, priv->next_pk_ptr);
864 /* packet address corrupted: reset RX logic */
865 mutex_lock(&priv->lock);
866 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
867 nolock_reg_bfset(priv, ECON1, ECON1_RXRST);
868 nolock_reg_bfclr(priv, ECON1, ECON1_RXRST);
869 nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
870 nolock_reg_bfclr(priv, EIR, EIR_RXERIF);
871 nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
872 mutex_unlock(&priv->lock);
873 ndev->stats.rx_errors++;
874 return;
875 }
876 /* Read next packet pointer and rx status vector */
877 enc28j60_mem_read(priv, priv->next_pk_ptr, sizeof(rsv), rsv);
878
879 next_packet = rsv[1];
880 next_packet <<= 8;
881 next_packet |= rsv[0];
882
883 len = rsv[3];
884 len <<= 8;
885 len |= rsv[2];
886
887 rxstat = rsv[5];
888 rxstat <<= 8;
889 rxstat |= rsv[4];
890
891 if (netif_msg_rx_status(priv))
892 enc28j60_dump_rsv(priv, __FUNCTION__, next_packet, len, rxstat);
893
894 if (!RSV_GETBIT(rxstat, RSV_RXOK)) {
895 if (netif_msg_rx_err(priv))
896 dev_err(&ndev->dev, "Rx Error (%04x)\n", rxstat);
897 ndev->stats.rx_errors++;
898 if (RSV_GETBIT(rxstat, RSV_CRCERROR))
899 ndev->stats.rx_crc_errors++;
900 if (RSV_GETBIT(rxstat, RSV_LENCHECKERR))
901 ndev->stats.rx_frame_errors++;
902 } else {
903 skb = dev_alloc_skb(len);
904 if (!skb) {
905 if (netif_msg_rx_err(priv))
906 dev_err(&ndev->dev,
907 "out of memory for Rx'd frame\n");
908 ndev->stats.rx_dropped++;
909 } else {
910 skb->dev = ndev;
911 /* copy the packet from the receive buffer */
912 enc28j60_mem_read(priv, priv->next_pk_ptr + sizeof(rsv),
913 len, skb_put(skb, len));
914 if (netif_msg_pktdata(priv))
915 dump_packet(__FUNCTION__, skb->len, skb->data);
916 skb->protocol = eth_type_trans(skb, ndev);
917 /* update statistics */
918 ndev->stats.rx_packets++;
919 ndev->stats.rx_bytes += len;
920 ndev->last_rx = jiffies;
921 netif_rx(skb);
922 }
923 }
924 /*
925 * Move the RX read pointer to the start of the next
926 * received packet.
927 * This frees the memory we just read out
928 */
929 erxrdpt = erxrdpt_workaround(next_packet, RXSTART_INIT, RXEND_INIT);
930 if (netif_msg_hw(priv))
931 printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT:0x%04x\n",
932 __FUNCTION__, erxrdpt);
933
934 mutex_lock(&priv->lock);
935 nolock_regw_write(priv, ERXRDPTL, erxrdpt);
936#ifdef CONFIG_ENC28J60_WRITEVERIFY
937 if (netif_msg_drv(priv)) {
938 u16 reg;
939 reg = nolock_regw_read(priv, ERXRDPTL);
940 if (reg != erxrdpt)
941 printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT verify "
942 "error (0x%04x - 0x%04x)\n", __FUNCTION__,
943 reg, erxrdpt);
944 }
945#endif
946 priv->next_pk_ptr = next_packet;
947 /* we are done with this packet, decrement the packet counter */
948 nolock_reg_bfset(priv, ECON2, ECON2_PKTDEC);
949 mutex_unlock(&priv->lock);
950}
951
952/*
953 * Calculate free space in RxFIFO
954 */
955static int enc28j60_get_free_rxfifo(struct enc28j60_net *priv)
956{
957 int epkcnt, erxst, erxnd, erxwr, erxrd;
958 int free_space;
959
960 mutex_lock(&priv->lock);
961 epkcnt = nolock_regb_read(priv, EPKTCNT);
962 if (epkcnt >= 255)
963 free_space = -1;
964 else {
965 erxst = nolock_regw_read(priv, ERXSTL);
966 erxnd = nolock_regw_read(priv, ERXNDL);
967 erxwr = nolock_regw_read(priv, ERXWRPTL);
968 erxrd = nolock_regw_read(priv, ERXRDPTL);
969
970 if (erxwr > erxrd)
971 free_space = (erxnd - erxst) - (erxwr - erxrd);
972 else if (erxwr == erxrd)
973 free_space = (erxnd - erxst);
974 else
975 free_space = erxrd - erxwr - 1;
976 }
977 mutex_unlock(&priv->lock);
978 if (netif_msg_rx_status(priv))
979 printk(KERN_DEBUG DRV_NAME ": %s() free_space = %d\n",
980 __FUNCTION__, free_space);
981 return free_space;
982}
983
984/*
985 * Access the PHY to determine link status
986 */
987static void enc28j60_check_link_status(struct net_device *ndev)
988{
989 struct enc28j60_net *priv = netdev_priv(ndev);
990 u16 reg;
991 int duplex;
992
993 reg = enc28j60_phy_read(priv, PHSTAT2);
994 if (netif_msg_hw(priv))
995 printk(KERN_DEBUG DRV_NAME ": %s() PHSTAT1: %04x, "
996 "PHSTAT2: %04x\n", __FUNCTION__,
997 enc28j60_phy_read(priv, PHSTAT1), reg);
998 duplex = reg & PHSTAT2_DPXSTAT;
999
1000 if (reg & PHSTAT2_LSTAT) {
1001 netif_carrier_on(ndev);
1002 if (netif_msg_ifup(priv))
1003 dev_info(&ndev->dev, "link up - %s\n",
1004 duplex ? "Full duplex" : "Half duplex");
1005 } else {
1006 if (netif_msg_ifdown(priv))
1007 dev_info(&ndev->dev, "link down\n");
1008 netif_carrier_off(ndev);
1009 }
1010}
1011
1012static void enc28j60_tx_clear(struct net_device *ndev, bool err)
1013{
1014 struct enc28j60_net *priv = netdev_priv(ndev);
1015
1016 if (err)
1017 ndev->stats.tx_errors++;
1018 else
1019 ndev->stats.tx_packets++;
1020
1021 if (priv->tx_skb) {
1022 if (!err)
1023 ndev->stats.tx_bytes += priv->tx_skb->len;
1024 dev_kfree_skb(priv->tx_skb);
1025 priv->tx_skb = NULL;
1026 }
1027 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1028 netif_wake_queue(ndev);
1029}
1030
1031/*
1032 * RX handler
1033 * ignore PKTIF because is unreliable! (look at the errata datasheet)
1034 * check EPKTCNT is the suggested workaround.
1035 * We don't need to clear interrupt flag, automatically done when
1036 * enc28j60_hw_rx() decrements the packet counter.
1037 * Returns how many packet processed.
1038 */
1039static int enc28j60_rx_interrupt(struct net_device *ndev)
1040{
1041 struct enc28j60_net *priv = netdev_priv(ndev);
1042 int pk_counter, ret;
1043
1044 pk_counter = locked_regb_read(priv, EPKTCNT);
1045 if (pk_counter && netif_msg_intr(priv))
1046 printk(KERN_DEBUG DRV_NAME ": intRX, pk_cnt: %d\n", pk_counter);
1047 if (pk_counter > priv->max_pk_counter) {
1048 /* update statistics */
1049 priv->max_pk_counter = pk_counter;
1050 if (netif_msg_rx_status(priv) && priv->max_pk_counter > 1)
1051 printk(KERN_DEBUG DRV_NAME ": RX max_pk_cnt: %d\n",
1052 priv->max_pk_counter);
1053 }
1054 ret = pk_counter;
1055 while (pk_counter-- > 0)
1056 enc28j60_hw_rx(ndev);
1057
1058 return ret;
1059}
1060
1061static void enc28j60_irq_work_handler(struct work_struct *work)
1062{
1063 struct enc28j60_net *priv =
1064 container_of(work, struct enc28j60_net, irq_work);
1065 struct net_device *ndev = priv->netdev;
1066 int intflags, loop;
1067
1068 if (netif_msg_intr(priv))
1069 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __FUNCTION__);
1070 /* disable further interrupts */
1071 locked_reg_bfclr(priv, EIE, EIE_INTIE);
1072
1073 do {
1074 loop = 0;
1075 intflags = locked_regb_read(priv, EIR);
1076 /* DMA interrupt handler (not currently used) */
1077 if ((intflags & EIR_DMAIF) != 0) {
1078 loop++;
1079 if (netif_msg_intr(priv))
1080 printk(KERN_DEBUG DRV_NAME
1081 ": intDMA(%d)\n", loop);
1082 locked_reg_bfclr(priv, EIR, EIR_DMAIF);
1083 }
1084 /* LINK changed handler */
1085 if ((intflags & EIR_LINKIF) != 0) {
1086 loop++;
1087 if (netif_msg_intr(priv))
1088 printk(KERN_DEBUG DRV_NAME
1089 ": intLINK(%d)\n", loop);
1090 enc28j60_check_link_status(ndev);
1091 /* read PHIR to clear the flag */
1092 enc28j60_phy_read(priv, PHIR);
1093 }
1094 /* TX complete handler */
1095 if ((intflags & EIR_TXIF) != 0) {
1096 bool err = false;
1097 loop++;
1098 if (netif_msg_intr(priv))
1099 printk(KERN_DEBUG DRV_NAME
1100 ": intTX(%d)\n", loop);
1101 priv->tx_retry_count = 0;
1102 if (locked_regb_read(priv, ESTAT) & ESTAT_TXABRT) {
1103 if (netif_msg_tx_err(priv))
1104 dev_err(&ndev->dev,
1105 "Tx Error (aborted)\n");
1106 err = true;
1107 }
1108 if (netif_msg_tx_done(priv)) {
1109 u8 tsv[TSV_SIZE];
1110 enc28j60_read_tsv(priv, tsv);
1111 enc28j60_dump_tsv(priv, "Tx Done", tsv);
1112 }
1113 enc28j60_tx_clear(ndev, err);
1114 locked_reg_bfclr(priv, EIR, EIR_TXIF);
1115 }
1116 /* TX Error handler */
1117 if ((intflags & EIR_TXERIF) != 0) {
1118 u8 tsv[TSV_SIZE];
1119
1120 loop++;
1121 if (netif_msg_intr(priv))
1122 printk(KERN_DEBUG DRV_NAME
1123 ": intTXErr(%d)\n", loop);
1124 locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1125 enc28j60_read_tsv(priv, tsv);
1126 if (netif_msg_tx_err(priv))
1127 enc28j60_dump_tsv(priv, "Tx Error", tsv);
1128 /* Reset TX logic */
1129 mutex_lock(&priv->lock);
1130 nolock_reg_bfset(priv, ECON1, ECON1_TXRST);
1131 nolock_reg_bfclr(priv, ECON1, ECON1_TXRST);
1132 nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
1133 mutex_unlock(&priv->lock);
1134 /* Transmit Late collision check for retransmit */
1135 if (TSV_GETBIT(tsv, TSV_TXLATECOLLISION)) {
1136 if (netif_msg_tx_err(priv))
1137 printk(KERN_DEBUG DRV_NAME
1138 ": LateCollision TXErr (%d)\n",
1139 priv->tx_retry_count);
1140 if (priv->tx_retry_count++ < MAX_TX_RETRYCOUNT)
1141 locked_reg_bfset(priv, ECON1,
1142 ECON1_TXRTS);
1143 else
1144 enc28j60_tx_clear(ndev, true);
1145 } else
1146 enc28j60_tx_clear(ndev, true);
1147 locked_reg_bfclr(priv, EIR, EIR_TXERIF);
1148 }
1149 /* RX Error handler */
1150 if ((intflags & EIR_RXERIF) != 0) {
1151 loop++;
1152 if (netif_msg_intr(priv))
1153 printk(KERN_DEBUG DRV_NAME
1154 ": intRXErr(%d)\n", loop);
1155 /* Check free FIFO space to flag RX overrun */
1156 if (enc28j60_get_free_rxfifo(priv) <= 0) {
1157 if (netif_msg_rx_err(priv))
1158 printk(KERN_DEBUG DRV_NAME
1159 ": RX Overrun\n");
1160 ndev->stats.rx_dropped++;
1161 }
1162 locked_reg_bfclr(priv, EIR, EIR_RXERIF);
1163 }
1164 /* RX handler */
1165 if (enc28j60_rx_interrupt(ndev))
1166 loop++;
1167 } while (loop);
1168
1169 /* re-enable interrupts */
1170 locked_reg_bfset(priv, EIE, EIE_INTIE);
1171 if (netif_msg_intr(priv))
1172 printk(KERN_DEBUG DRV_NAME ": %s() exit\n", __FUNCTION__);
1173}
1174
1175/*
1176 * Hardware transmit function.
1177 * Fill the buffer memory and send the contents of the transmit buffer
1178 * onto the network
1179 */
1180static void enc28j60_hw_tx(struct enc28j60_net *priv)
1181{
1182 if (netif_msg_tx_queued(priv))
1183 printk(KERN_DEBUG DRV_NAME
1184 ": Tx Packet Len:%d\n", priv->tx_skb->len);
1185
1186 if (netif_msg_pktdata(priv))
1187 dump_packet(__FUNCTION__,
1188 priv->tx_skb->len, priv->tx_skb->data);
1189 enc28j60_packet_write(priv, priv->tx_skb->len, priv->tx_skb->data);
1190
1191#ifdef CONFIG_ENC28J60_WRITEVERIFY
1192 /* readback and verify written data */
1193 if (netif_msg_drv(priv)) {
1194 int test_len, k;
1195 u8 test_buf[64]; /* limit the test to the first 64 bytes */
1196 int okflag;
1197
1198 test_len = priv->tx_skb->len;
1199 if (test_len > sizeof(test_buf))
1200 test_len = sizeof(test_buf);
1201
1202 /* + 1 to skip control byte */
1203 enc28j60_mem_read(priv, TXSTART_INIT + 1, test_len, test_buf);
1204 okflag = 1;
1205 for (k = 0; k < test_len; k++) {
1206 if (priv->tx_skb->data[k] != test_buf[k]) {
1207 printk(KERN_DEBUG DRV_NAME
1208 ": Error, %d location differ: "
1209 "0x%02x-0x%02x\n", k,
1210 priv->tx_skb->data[k], test_buf[k]);
1211 okflag = 0;
1212 }
1213 }
1214 if (!okflag)
1215 printk(KERN_DEBUG DRV_NAME ": Tx write buffer, "
1216 "verify ERROR!\n");
1217 }
1218#endif
1219 /* set TX request flag */
1220 locked_reg_bfset(priv, ECON1, ECON1_TXRTS);
1221}
1222
1223static int enc28j60_send_packet(struct sk_buff *skb, struct net_device *dev)
1224{
1225 struct enc28j60_net *priv = netdev_priv(dev);
1226
1227 if (netif_msg_tx_queued(priv))
1228 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __FUNCTION__);
1229
1230 /* If some error occurs while trying to transmit this
1231 * packet, you should return '1' from this function.
1232 * In such a case you _may not_ do anything to the
1233 * SKB, it is still owned by the network queueing
1234 * layer when an error is returned. This means you
1235 * may not modify any SKB fields, you may not free
1236 * the SKB, etc.
1237 */
1238 netif_stop_queue(dev);
1239
1240 /* save the timestamp */
1241 priv->netdev->trans_start = jiffies;
1242 /* Remember the skb for deferred processing */
1243 priv->tx_skb = skb;
1244 schedule_work(&priv->tx_work);
1245
1246 return 0;
1247}
1248
1249static void enc28j60_tx_work_handler(struct work_struct *work)
1250{
1251 struct enc28j60_net *priv =
1252 container_of(work, struct enc28j60_net, tx_work);
1253
1254 /* actual delivery of data */
1255 enc28j60_hw_tx(priv);
1256}
1257
1258static irqreturn_t enc28j60_irq(int irq, void *dev_id)
1259{
1260 struct enc28j60_net *priv = dev_id;
1261
1262 /*
1263 * Can't do anything in interrupt context because we need to
1264 * block (spi_sync() is blocking) so fire of the interrupt
1265 * handling workqueue.
1266 * Remember that we access enc28j60 registers through SPI bus
1267 * via spi_sync() call.
1268 */
1269 schedule_work(&priv->irq_work);
1270
1271 return IRQ_HANDLED;
1272}
1273
1274static void enc28j60_tx_timeout(struct net_device *ndev)
1275{
1276 struct enc28j60_net *priv = netdev_priv(ndev);
1277
1278 if (netif_msg_timer(priv))
1279 dev_err(&ndev->dev, DRV_NAME " tx timeout\n");
1280
1281 ndev->stats.tx_errors++;
1282 /* can't restart safely under softirq */
1283 schedule_work(&priv->restart_work);
1284}
1285
1286/*
1287 * Open/initialize the board. This is called (in the current kernel)
1288 * sometime after booting when the 'ifconfig' program is run.
1289 *
1290 * This routine should set everything up anew at each open, even
1291 * registers that "should" only need to be set once at boot, so that
1292 * there is non-reboot way to recover if something goes wrong.
1293 */
1294static int enc28j60_net_open(struct net_device *dev)
1295{
1296 struct enc28j60_net *priv = netdev_priv(dev);
1297
1298 if (netif_msg_drv(priv))
1299 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __FUNCTION__);
1300
1301 if (!is_valid_ether_addr(dev->dev_addr)) {
1302 if (netif_msg_ifup(priv)) {
1303 DECLARE_MAC_BUF(mac);
1304 dev_err(&dev->dev, "invalid MAC address %s\n",
1305 print_mac(mac, dev->dev_addr));
1306 }
1307 return -EADDRNOTAVAIL;
1308 }
1309 /* Reset the hardware here */
1310 enc28j60_hw_disable(priv);
1311 if (!enc28j60_hw_init(priv)) {
1312 if (netif_msg_ifup(priv))
1313 dev_err(&dev->dev, "hw_reset() failed\n");
1314 return -EINVAL;
1315 }
1316 /* Update the MAC address (in case user has changed it) */
1317 enc28j60_set_hw_macaddr(dev);
1318 /* Enable interrupts */
1319 enc28j60_hw_enable(priv);
1320 /* check link status */
1321 enc28j60_check_link_status(dev);
1322 /* We are now ready to accept transmit requests from
1323 * the queueing layer of the networking.
1324 */
1325 netif_start_queue(dev);
1326
1327 return 0;
1328}
1329
1330/* The inverse routine to net_open(). */
1331static int enc28j60_net_close(struct net_device *dev)
1332{
1333 struct enc28j60_net *priv = netdev_priv(dev);
1334
1335 if (netif_msg_drv(priv))
1336 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __FUNCTION__);
1337
1338 enc28j60_hw_disable(priv);
1339 netif_stop_queue(dev);
1340
1341 return 0;
1342}
1343
1344/*
1345 * Set or clear the multicast filter for this adapter
1346 * num_addrs == -1 Promiscuous mode, receive all packets
1347 * num_addrs == 0 Normal mode, filter out multicast packets
1348 * num_addrs > 0 Multicast mode, receive normal and MC packets
1349 */
1350static void enc28j60_set_multicast_list(struct net_device *dev)
1351{
1352 struct enc28j60_net *priv = netdev_priv(dev);
1353 int oldfilter = priv->rxfilter;
1354
1355 if (dev->flags & IFF_PROMISC) {
1356 if (netif_msg_link(priv))
1357 dev_info(&dev->dev, "promiscuous mode\n");
1358 priv->rxfilter = RXFILTER_PROMISC;
1359 } else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count) {
1360 if (netif_msg_link(priv))
1361 dev_info(&dev->dev, "%smulticast mode\n",
1362 (dev->flags & IFF_ALLMULTI) ? "all-" : "");
1363 priv->rxfilter = RXFILTER_MULTI;
1364 } else {
1365 if (netif_msg_link(priv))
1366 dev_info(&dev->dev, "normal mode\n");
1367 priv->rxfilter = RXFILTER_NORMAL;
1368 }
1369
1370 if (oldfilter != priv->rxfilter)
1371 schedule_work(&priv->setrx_work);
1372}
1373
1374static void enc28j60_setrx_work_handler(struct work_struct *work)
1375{
1376 struct enc28j60_net *priv =
1377 container_of(work, struct enc28j60_net, setrx_work);
1378
1379 if (priv->rxfilter == RXFILTER_PROMISC) {
1380 if (netif_msg_drv(priv))
1381 printk(KERN_DEBUG DRV_NAME ": promiscuous mode\n");
1382 locked_regb_write(priv, ERXFCON, 0x00);
1383 } else if (priv->rxfilter == RXFILTER_MULTI) {
1384 if (netif_msg_drv(priv))
1385 printk(KERN_DEBUG DRV_NAME ": multicast mode\n");
1386 locked_regb_write(priv, ERXFCON,
1387 ERXFCON_UCEN | ERXFCON_CRCEN |
1388 ERXFCON_BCEN | ERXFCON_MCEN);
1389 } else {
1390 if (netif_msg_drv(priv))
1391 printk(KERN_DEBUG DRV_NAME ": normal mode\n");
1392 locked_regb_write(priv, ERXFCON,
1393 ERXFCON_UCEN | ERXFCON_CRCEN |
1394 ERXFCON_BCEN);
1395 }
1396}
1397
1398static void enc28j60_restart_work_handler(struct work_struct *work)
1399{
1400 struct enc28j60_net *priv =
1401 container_of(work, struct enc28j60_net, restart_work);
1402 struct net_device *ndev = priv->netdev;
1403 int ret;
1404
1405 rtnl_lock();
1406 if (netif_running(ndev)) {
1407 enc28j60_net_close(ndev);
1408 ret = enc28j60_net_open(ndev);
1409 if (unlikely(ret)) {
1410 dev_info(&ndev->dev, " could not restart %d\n", ret);
1411 dev_close(ndev);
1412 }
1413 }
1414 rtnl_unlock();
1415}
1416
1417/* ......................... ETHTOOL SUPPORT ........................... */
1418
1419static void
1420enc28j60_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1421{
1422 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1423 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1424 strlcpy(info->bus_info,
1425 dev->dev.parent->bus_id, sizeof(info->bus_info));
1426}
1427
1428static int
1429enc28j60_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1430{
1431 struct enc28j60_net *priv = netdev_priv(dev);
1432
1433 cmd->transceiver = XCVR_INTERNAL;
1434 cmd->supported = SUPPORTED_10baseT_Half
1435 | SUPPORTED_10baseT_Full
1436 | SUPPORTED_TP;
1437 cmd->speed = SPEED_10;
1438 cmd->duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1439 cmd->port = PORT_TP;
1440 cmd->autoneg = AUTONEG_DISABLE;
1441
1442 return 0;
1443}
1444
1445static int
1446enc28j60_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1447{
1448 return enc28j60_setlink(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1449}
1450
1451static u32 enc28j60_get_msglevel(struct net_device *dev)
1452{
1453 struct enc28j60_net *priv = netdev_priv(dev);
1454 return priv->msg_enable;
1455}
1456
1457static void enc28j60_set_msglevel(struct net_device *dev, u32 val)
1458{
1459 struct enc28j60_net *priv = netdev_priv(dev);
1460 priv->msg_enable = val;
1461}
1462
1463static const struct ethtool_ops enc28j60_ethtool_ops = {
1464 .get_settings = enc28j60_get_settings,
1465 .set_settings = enc28j60_set_settings,
1466 .get_drvinfo = enc28j60_get_drvinfo,
1467 .get_msglevel = enc28j60_get_msglevel,
1468 .set_msglevel = enc28j60_set_msglevel,
1469};
1470
1471static int enc28j60_chipset_init(struct net_device *dev)
1472{
1473 struct enc28j60_net *priv = netdev_priv(dev);
1474
1475 return enc28j60_hw_init(priv);
1476}
1477
1478static int __devinit enc28j60_probe(struct spi_device *spi)
1479{
1480 struct net_device *dev;
1481 struct enc28j60_net *priv;
1482 int ret = 0;
1483
1484 if (netif_msg_drv(&debug))
1485 dev_info(&spi->dev, DRV_NAME " Ethernet driver %s loaded\n",
1486 DRV_VERSION);
1487
1488 dev = alloc_etherdev(sizeof(struct enc28j60_net));
1489 if (!dev) {
1490 if (netif_msg_drv(&debug))
1491 dev_err(&spi->dev, DRV_NAME
1492 ": unable to alloc new ethernet\n");
1493 ret = -ENOMEM;
1494 goto error_alloc;
1495 }
1496 priv = netdev_priv(dev);
1497
1498 priv->netdev = dev; /* priv to netdev reference */
1499 priv->spi = spi; /* priv to spi reference */
1500 priv->msg_enable = netif_msg_init(debug.msg_enable,
1501 ENC28J60_MSG_DEFAULT);
1502 mutex_init(&priv->lock);
1503 INIT_WORK(&priv->tx_work, enc28j60_tx_work_handler);
1504 INIT_WORK(&priv->setrx_work, enc28j60_setrx_work_handler);
1505 INIT_WORK(&priv->irq_work, enc28j60_irq_work_handler);
1506 INIT_WORK(&priv->restart_work, enc28j60_restart_work_handler);
1507 dev_set_drvdata(&spi->dev, priv); /* spi to priv reference */
1508 SET_NETDEV_DEV(dev, &spi->dev);
1509
1510 if (!enc28j60_chipset_init(dev)) {
1511 if (netif_msg_probe(priv))
1512 dev_info(&spi->dev, DRV_NAME " chip not found\n");
1513 ret = -EIO;
1514 goto error_irq;
1515 }
1516 random_ether_addr(dev->dev_addr);
1517 enc28j60_set_hw_macaddr(dev);
1518
1519 ret = request_irq(spi->irq, enc28j60_irq, IRQF_TRIGGER_FALLING,
1520 DRV_NAME, priv);
1521 if (ret < 0) {
1522 if (netif_msg_probe(priv))
1523 dev_err(&spi->dev, DRV_NAME ": request irq %d failed "
1524 "(ret = %d)\n", spi->irq, ret);
1525 goto error_irq;
1526 }
1527
1528 dev->if_port = IF_PORT_10BASET;
1529 dev->irq = spi->irq;
1530 dev->open = enc28j60_net_open;
1531 dev->stop = enc28j60_net_close;
1532 dev->hard_start_xmit = enc28j60_send_packet;
1533 dev->set_multicast_list = &enc28j60_set_multicast_list;
1534 dev->set_mac_address = enc28j60_set_mac_address;
1535 dev->tx_timeout = &enc28j60_tx_timeout;
1536 dev->watchdog_timeo = TX_TIMEOUT;
1537 SET_ETHTOOL_OPS(dev, &enc28j60_ethtool_ops);
1538
1539 ret = register_netdev(dev);
1540 if (ret) {
1541 if (netif_msg_probe(priv))
1542 dev_err(&spi->dev, "register netdev " DRV_NAME
1543 " failed (ret = %d)\n", ret);
1544 goto error_register;
1545 }
1546 dev_info(&dev->dev, DRV_NAME " driver registered\n");
1547
1548 return 0;
1549
1550error_register:
1551 free_irq(spi->irq, priv);
1552error_irq:
1553 free_netdev(dev);
1554error_alloc:
1555 return ret;
1556}
1557
1558static int enc28j60_remove(struct spi_device *spi)
1559{
1560 struct enc28j60_net *priv = dev_get_drvdata(&spi->dev);
1561
1562 if (netif_msg_drv(priv))
1563 printk(KERN_DEBUG DRV_NAME ": remove\n");
1564
1565 unregister_netdev(priv->netdev);
1566 free_irq(spi->irq, priv);
1567 free_netdev(priv->netdev);
1568
1569 return 0;
1570}
1571
1572static struct spi_driver enc28j60_driver = {
1573 .driver = {
1574 .name = DRV_NAME,
1575 .bus = &spi_bus_type,
1576 .owner = THIS_MODULE,
1577 },
1578 .probe = enc28j60_probe,
1579 .remove = __devexit_p(enc28j60_remove),
1580};
1581
1582static int __init enc28j60_init(void)
1583{
1584 return spi_register_driver(&enc28j60_driver);
1585}
1586
1587module_init(enc28j60_init);
1588
1589static void __exit enc28j60_exit(void)
1590{
1591 spi_unregister_driver(&enc28j60_driver);
1592}
1593
1594module_exit(enc28j60_exit);
1595
1596MODULE_DESCRIPTION(DRV_NAME " ethernet driver");
1597MODULE_AUTHOR("Claudio Lanconelli <lanconelli.claudio@eptar.com>");
1598MODULE_LICENSE("GPL");
1599module_param_named(debug, debug.msg_enable, int, 0);
1600MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., ffff=all)");
diff --git a/drivers/net/enc28j60_hw.h b/drivers/net/enc28j60_hw.h
new file mode 100644
index 000000000000..1a0b20969f80
--- /dev/null
+++ b/drivers/net/enc28j60_hw.h
@@ -0,0 +1,309 @@
1/*
2 * enc28j60_hw.h: EDTP FrameThrower style enc28j60 registers
3 *
4 * $Id: enc28j60_hw.h,v 1.9 2007/12/14 11:59:16 claudio Exp $
5 */
6
7#ifndef _ENC28J60_HW_H
8#define _ENC28J60_HW_H
9
10/*
11 * ENC28J60 Control Registers
12 * Control register definitions are a combination of address,
13 * bank number, and Ethernet/MAC/PHY indicator bits.
14 * - Register address (bits 0-4)
15 * - Bank number (bits 5-6)
16 * - MAC/MII indicator (bit 7)
17 */
18#define ADDR_MASK 0x1F
19#define BANK_MASK 0x60
20#define SPRD_MASK 0x80
21/* All-bank registers */
22#define EIE 0x1B
23#define EIR 0x1C
24#define ESTAT 0x1D
25#define ECON2 0x1E
26#define ECON1 0x1F
27/* Bank 0 registers */
28#define ERDPTL (0x00|0x00)
29#define ERDPTH (0x01|0x00)
30#define EWRPTL (0x02|0x00)
31#define EWRPTH (0x03|0x00)
32#define ETXSTL (0x04|0x00)
33#define ETXSTH (0x05|0x00)
34#define ETXNDL (0x06|0x00)
35#define ETXNDH (0x07|0x00)
36#define ERXSTL (0x08|0x00)
37#define ERXSTH (0x09|0x00)
38#define ERXNDL (0x0A|0x00)
39#define ERXNDH (0x0B|0x00)
40#define ERXRDPTL (0x0C|0x00)
41#define ERXRDPTH (0x0D|0x00)
42#define ERXWRPTL (0x0E|0x00)
43#define ERXWRPTH (0x0F|0x00)
44#define EDMASTL (0x10|0x00)
45#define EDMASTH (0x11|0x00)
46#define EDMANDL (0x12|0x00)
47#define EDMANDH (0x13|0x00)
48#define EDMADSTL (0x14|0x00)
49#define EDMADSTH (0x15|0x00)
50#define EDMACSL (0x16|0x00)
51#define EDMACSH (0x17|0x00)
52/* Bank 1 registers */
53#define EHT0 (0x00|0x20)
54#define EHT1 (0x01|0x20)
55#define EHT2 (0x02|0x20)
56#define EHT3 (0x03|0x20)
57#define EHT4 (0x04|0x20)
58#define EHT5 (0x05|0x20)
59#define EHT6 (0x06|0x20)
60#define EHT7 (0x07|0x20)
61#define EPMM0 (0x08|0x20)
62#define EPMM1 (0x09|0x20)
63#define EPMM2 (0x0A|0x20)
64#define EPMM3 (0x0B|0x20)
65#define EPMM4 (0x0C|0x20)
66#define EPMM5 (0x0D|0x20)
67#define EPMM6 (0x0E|0x20)
68#define EPMM7 (0x0F|0x20)
69#define EPMCSL (0x10|0x20)
70#define EPMCSH (0x11|0x20)
71#define EPMOL (0x14|0x20)
72#define EPMOH (0x15|0x20)
73#define EWOLIE (0x16|0x20)
74#define EWOLIR (0x17|0x20)
75#define ERXFCON (0x18|0x20)
76#define EPKTCNT (0x19|0x20)
77/* Bank 2 registers */
78#define MACON1 (0x00|0x40|SPRD_MASK)
79/* #define MACON2 (0x01|0x40|SPRD_MASK) */
80#define MACON3 (0x02|0x40|SPRD_MASK)
81#define MACON4 (0x03|0x40|SPRD_MASK)
82#define MABBIPG (0x04|0x40|SPRD_MASK)
83#define MAIPGL (0x06|0x40|SPRD_MASK)
84#define MAIPGH (0x07|0x40|SPRD_MASK)
85#define MACLCON1 (0x08|0x40|SPRD_MASK)
86#define MACLCON2 (0x09|0x40|SPRD_MASK)
87#define MAMXFLL (0x0A|0x40|SPRD_MASK)
88#define MAMXFLH (0x0B|0x40|SPRD_MASK)
89#define MAPHSUP (0x0D|0x40|SPRD_MASK)
90#define MICON (0x11|0x40|SPRD_MASK)
91#define MICMD (0x12|0x40|SPRD_MASK)
92#define MIREGADR (0x14|0x40|SPRD_MASK)
93#define MIWRL (0x16|0x40|SPRD_MASK)
94#define MIWRH (0x17|0x40|SPRD_MASK)
95#define MIRDL (0x18|0x40|SPRD_MASK)
96#define MIRDH (0x19|0x40|SPRD_MASK)
97/* Bank 3 registers */
98#define MAADR1 (0x00|0x60|SPRD_MASK)
99#define MAADR0 (0x01|0x60|SPRD_MASK)
100#define MAADR3 (0x02|0x60|SPRD_MASK)
101#define MAADR2 (0x03|0x60|SPRD_MASK)
102#define MAADR5 (0x04|0x60|SPRD_MASK)
103#define MAADR4 (0x05|0x60|SPRD_MASK)
104#define EBSTSD (0x06|0x60)
105#define EBSTCON (0x07|0x60)
106#define EBSTCSL (0x08|0x60)
107#define EBSTCSH (0x09|0x60)
108#define MISTAT (0x0A|0x60|SPRD_MASK)
109#define EREVID (0x12|0x60)
110#define ECOCON (0x15|0x60)
111#define EFLOCON (0x17|0x60)
112#define EPAUSL (0x18|0x60)
113#define EPAUSH (0x19|0x60)
114/* PHY registers */
115#define PHCON1 0x00
116#define PHSTAT1 0x01
117#define PHHID1 0x02
118#define PHHID2 0x03
119#define PHCON2 0x10
120#define PHSTAT2 0x11
121#define PHIE 0x12
122#define PHIR 0x13
123#define PHLCON 0x14
124
125/* ENC28J60 EIE Register Bit Definitions */
126#define EIE_INTIE 0x80
127#define EIE_PKTIE 0x40
128#define EIE_DMAIE 0x20
129#define EIE_LINKIE 0x10
130#define EIE_TXIE 0x08
131/* #define EIE_WOLIE 0x04 (reserved) */
132#define EIE_TXERIE 0x02
133#define EIE_RXERIE 0x01
134/* ENC28J60 EIR Register Bit Definitions */
135#define EIR_PKTIF 0x40
136#define EIR_DMAIF 0x20
137#define EIR_LINKIF 0x10
138#define EIR_TXIF 0x08
139/* #define EIR_WOLIF 0x04 (reserved) */
140#define EIR_TXERIF 0x02
141#define EIR_RXERIF 0x01
142/* ENC28J60 ESTAT Register Bit Definitions */
143#define ESTAT_INT 0x80
144#define ESTAT_LATECOL 0x10
145#define ESTAT_RXBUSY 0x04
146#define ESTAT_TXABRT 0x02
147#define ESTAT_CLKRDY 0x01
148/* ENC28J60 ECON2 Register Bit Definitions */
149#define ECON2_AUTOINC 0x80
150#define ECON2_PKTDEC 0x40
151#define ECON2_PWRSV 0x20
152#define ECON2_VRPS 0x08
153/* ENC28J60 ECON1 Register Bit Definitions */
154#define ECON1_TXRST 0x80
155#define ECON1_RXRST 0x40
156#define ECON1_DMAST 0x20
157#define ECON1_CSUMEN 0x10
158#define ECON1_TXRTS 0x08
159#define ECON1_RXEN 0x04
160#define ECON1_BSEL1 0x02
161#define ECON1_BSEL0 0x01
162/* ENC28J60 MACON1 Register Bit Definitions */
163#define MACON1_LOOPBK 0x10
164#define MACON1_TXPAUS 0x08
165#define MACON1_RXPAUS 0x04
166#define MACON1_PASSALL 0x02
167#define MACON1_MARXEN 0x01
168/* ENC28J60 MACON2 Register Bit Definitions */
169#define MACON2_MARST 0x80
170#define MACON2_RNDRST 0x40
171#define MACON2_MARXRST 0x08
172#define MACON2_RFUNRST 0x04
173#define MACON2_MATXRST 0x02
174#define MACON2_TFUNRST 0x01
175/* ENC28J60 MACON3 Register Bit Definitions */
176#define MACON3_PADCFG2 0x80
177#define MACON3_PADCFG1 0x40
178#define MACON3_PADCFG0 0x20
179#define MACON3_TXCRCEN 0x10
180#define MACON3_PHDRLEN 0x08
181#define MACON3_HFRMLEN 0x04
182#define MACON3_FRMLNEN 0x02
183#define MACON3_FULDPX 0x01
184/* ENC28J60 MICMD Register Bit Definitions */
185#define MICMD_MIISCAN 0x02
186#define MICMD_MIIRD 0x01
187/* ENC28J60 MISTAT Register Bit Definitions */
188#define MISTAT_NVALID 0x04
189#define MISTAT_SCAN 0x02
190#define MISTAT_BUSY 0x01
191/* ENC28J60 ERXFCON Register Bit Definitions */
192#define ERXFCON_UCEN 0x80
193#define ERXFCON_ANDOR 0x40
194#define ERXFCON_CRCEN 0x20
195#define ERXFCON_PMEN 0x10
196#define ERXFCON_MPEN 0x08
197#define ERXFCON_HTEN 0x04
198#define ERXFCON_MCEN 0x02
199#define ERXFCON_BCEN 0x01
200
201/* ENC28J60 PHY PHCON1 Register Bit Definitions */
202#define PHCON1_PRST 0x8000
203#define PHCON1_PLOOPBK 0x4000
204#define PHCON1_PPWRSV 0x0800
205#define PHCON1_PDPXMD 0x0100
206/* ENC28J60 PHY PHSTAT1 Register Bit Definitions */
207#define PHSTAT1_PFDPX 0x1000
208#define PHSTAT1_PHDPX 0x0800
209#define PHSTAT1_LLSTAT 0x0004
210#define PHSTAT1_JBSTAT 0x0002
211/* ENC28J60 PHY PHSTAT2 Register Bit Definitions */
212#define PHSTAT2_TXSTAT (1 << 13)
213#define PHSTAT2_RXSTAT (1 << 12)
214#define PHSTAT2_COLSTAT (1 << 11)
215#define PHSTAT2_LSTAT (1 << 10)
216#define PHSTAT2_DPXSTAT (1 << 9)
217#define PHSTAT2_PLRITY (1 << 5)
218/* ENC28J60 PHY PHCON2 Register Bit Definitions */
219#define PHCON2_FRCLINK 0x4000
220#define PHCON2_TXDIS 0x2000
221#define PHCON2_JABBER 0x0400
222#define PHCON2_HDLDIS 0x0100
223/* ENC28J60 PHY PHIE Register Bit Definitions */
224#define PHIE_PLNKIE (1 << 4)
225#define PHIE_PGEIE (1 << 1)
226/* ENC28J60 PHY PHIR Register Bit Definitions */
227#define PHIR_PLNKIF (1 << 4)
228#define PHIR_PGEIF (1 << 1)
229
230/* ENC28J60 Packet Control Byte Bit Definitions */
231#define PKTCTRL_PHUGEEN 0x08
232#define PKTCTRL_PPADEN 0x04
233#define PKTCTRL_PCRCEN 0x02
234#define PKTCTRL_POVERRIDE 0x01
235
236/* ENC28J60 Transmit Status Vector */
237#define TSV_TXBYTECNT 0
238#define TSV_TXCOLLISIONCNT 16
239#define TSV_TXCRCERROR 20
240#define TSV_TXLENCHKERROR 21
241#define TSV_TXLENOUTOFRANGE 22
242#define TSV_TXDONE 23
243#define TSV_TXMULTICAST 24
244#define TSV_TXBROADCAST 25
245#define TSV_TXPACKETDEFER 26
246#define TSV_TXEXDEFER 27
247#define TSV_TXEXCOLLISION 28
248#define TSV_TXLATECOLLISION 29
249#define TSV_TXGIANT 30
250#define TSV_TXUNDERRUN 31
251#define TSV_TOTBYTETXONWIRE 32
252#define TSV_TXCONTROLFRAME 48
253#define TSV_TXPAUSEFRAME 49
254#define TSV_BACKPRESSUREAPP 50
255#define TSV_TXVLANTAGFRAME 51
256
257#define TSV_SIZE 7
258#define TSV_BYTEOF(x) ((x) / 8)
259#define TSV_BITMASK(x) (1 << ((x) % 8))
260#define TSV_GETBIT(x, y) (((x)[TSV_BYTEOF(y)] & TSV_BITMASK(y)) ? 1 : 0)
261
262/* ENC28J60 Receive Status Vector */
263#define RSV_RXLONGEVDROPEV 16
264#define RSV_CARRIEREV 18
265#define RSV_CRCERROR 20
266#define RSV_LENCHECKERR 21
267#define RSV_LENOUTOFRANGE 22
268#define RSV_RXOK 23
269#define RSV_RXMULTICAST 24
270#define RSV_RXBROADCAST 25
271#define RSV_DRIBBLENIBBLE 26
272#define RSV_RXCONTROLFRAME 27
273#define RSV_RXPAUSEFRAME 28
274#define RSV_RXUNKNOWNOPCODE 29
275#define RSV_RXTYPEVLAN 30
276
277#define RSV_SIZE 6
278#define RSV_BITMASK(x) (1 << ((x) - 16))
279#define RSV_GETBIT(x, y) (((x) & RSV_BITMASK(y)) ? 1 : 0)
280
281
282/* SPI operation codes */
283#define ENC28J60_READ_CTRL_REG 0x00
284#define ENC28J60_READ_BUF_MEM 0x3A
285#define ENC28J60_WRITE_CTRL_REG 0x40
286#define ENC28J60_WRITE_BUF_MEM 0x7A
287#define ENC28J60_BIT_FIELD_SET 0x80
288#define ENC28J60_BIT_FIELD_CLR 0xA0
289#define ENC28J60_SOFT_RESET 0xFF
290
291
292/* buffer boundaries applied to internal 8K ram
293 * entire available packet buffer space is allocated.
294 * Give TX buffer space for one full ethernet frame (~1500 bytes)
295 * receive buffer gets the rest */
296#define TXSTART_INIT 0x1A00
297#define TXEND_INIT 0x1FFF
298
299/* Put RX buffer at 0 as suggested by the Errata datasheet */
300#define RXSTART_INIT 0x0000
301#define RXEND_INIT 0x19FF
302
303/* maximum ethernet frame length */
304#define MAX_FRAMELEN 1518
305
306/* Prefered half duplex: LEDA: Link status LEDB: Rx/Tx activity */
307#define ENC28J60_LAMPS_MODE 0x3476
308
309#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-30 04:08:24 -0500