diff options
author | Wey-Yi Guy <wey-yi.w.guy@intel.com> | 2011-03-22 11:05:37 -0400 |
---|---|---|
committer | Wey-Yi Guy <wey-yi.w.guy@intel.com> | 2011-03-25 09:58:47 -0400 |
commit | f7d046f91bd165e747b9a95d089a4168b6f9796a (patch) | |
tree | dafe14f7cd42b95588104c819bb85f2a5dd6dc18 /drivers/net | |
parent | 2a226ab67f2f9c46e534f37f867d3bf3af335d02 (diff) |
iwlagn: remove reference to 3945 and 4965
After driver split, remove the unused reference to 3945 and 4965
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Diffstat (limited to 'drivers/net')
-rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-agn.c | 39 | ||||
-rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-csr.h | 39 | ||||
-rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-eeprom.c | 2 |
3 files changed, 23 insertions, 57 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.c b/drivers/net/wireless/iwlwifi/iwl-agn.c index bd980a2da413..9251c68934dd 100644 --- a/drivers/net/wireless/iwlwifi/iwl-agn.c +++ b/drivers/net/wireless/iwlwifi/iwl-agn.c | |||
@@ -409,7 +409,7 @@ int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, | |||
409 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | 409 | * Tell nic where to find circular buffer of Tx Frame Descriptors for |
410 | * given Tx queue, and enable the DMA channel used for that queue. | 410 | * given Tx queue, and enable the DMA channel used for that queue. |
411 | * | 411 | * |
412 | * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA | 412 | * supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA |
413 | * channels supported in hardware. | 413 | * channels supported in hardware. |
414 | */ | 414 | */ |
415 | int iwl_hw_tx_queue_init(struct iwl_priv *priv, | 415 | int iwl_hw_tx_queue_init(struct iwl_priv *priv, |
@@ -986,7 +986,7 @@ static void iwl_irq_tasklet(struct iwl_priv *priv) | |||
986 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | 986 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { |
987 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); | 987 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
988 | iwl_write32(priv, CSR_FH_INT_STATUS, | 988 | iwl_write32(priv, CSR_FH_INT_STATUS, |
989 | CSR49_FH_INT_RX_MASK); | 989 | CSR_FH_INT_RX_MASK); |
990 | } | 990 | } |
991 | if (inta & CSR_INT_BIT_RX_PERIODIC) { | 991 | if (inta & CSR_INT_BIT_RX_PERIODIC) { |
992 | handled |= CSR_INT_BIT_RX_PERIODIC; | 992 | handled |= CSR_INT_BIT_RX_PERIODIC; |
@@ -1024,7 +1024,7 @@ static void iwl_irq_tasklet(struct iwl_priv *priv) | |||
1024 | 1024 | ||
1025 | /* This "Tx" DMA channel is used only for loading uCode */ | 1025 | /* This "Tx" DMA channel is used only for loading uCode */ |
1026 | if (inta & CSR_INT_BIT_FH_TX) { | 1026 | if (inta & CSR_INT_BIT_FH_TX) { |
1027 | iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK); | 1027 | iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); |
1028 | IWL_DEBUG_ISR(priv, "uCode load interrupt\n"); | 1028 | IWL_DEBUG_ISR(priv, "uCode load interrupt\n"); |
1029 | priv->isr_stats.tx++; | 1029 | priv->isr_stats.tx++; |
1030 | handled |= CSR_INT_BIT_FH_TX; | 1030 | handled |= CSR_INT_BIT_FH_TX; |
@@ -1259,28 +1259,19 @@ static int iwlagn_load_legacy_firmware(struct iwl_priv *priv, | |||
1259 | 1259 | ||
1260 | switch (api_ver) { | 1260 | switch (api_ver) { |
1261 | default: | 1261 | default: |
1262 | /* | 1262 | hdr_size = 28; |
1263 | * 4965 doesn't revision the firmware file format | 1263 | if (ucode_raw->size < hdr_size) { |
1264 | * along with the API version, it always uses v1 | 1264 | IWL_ERR(priv, "File size too small!\n"); |
1265 | * file format. | 1265 | return -EINVAL; |
1266 | */ | ||
1267 | if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) != | ||
1268 | CSR_HW_REV_TYPE_4965) { | ||
1269 | hdr_size = 28; | ||
1270 | if (ucode_raw->size < hdr_size) { | ||
1271 | IWL_ERR(priv, "File size too small!\n"); | ||
1272 | return -EINVAL; | ||
1273 | } | ||
1274 | pieces->build = le32_to_cpu(ucode->u.v2.build); | ||
1275 | pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size); | ||
1276 | pieces->data_size = le32_to_cpu(ucode->u.v2.data_size); | ||
1277 | pieces->init_size = le32_to_cpu(ucode->u.v2.init_size); | ||
1278 | pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size); | ||
1279 | pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size); | ||
1280 | src = ucode->u.v2.data; | ||
1281 | break; | ||
1282 | } | 1266 | } |
1283 | /* fall through for 4965 */ | 1267 | pieces->build = le32_to_cpu(ucode->u.v2.build); |
1268 | pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size); | ||
1269 | pieces->data_size = le32_to_cpu(ucode->u.v2.data_size); | ||
1270 | pieces->init_size = le32_to_cpu(ucode->u.v2.init_size); | ||
1271 | pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size); | ||
1272 | pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size); | ||
1273 | src = ucode->u.v2.data; | ||
1274 | break; | ||
1284 | case 0: | 1275 | case 0: |
1285 | case 1: | 1276 | case 1: |
1286 | case 2: | 1277 | case 2: |
diff --git a/drivers/net/wireless/iwlwifi/iwl-csr.h b/drivers/net/wireless/iwlwifi/iwl-csr.h index f52bc040bcbf..1123319f2e2b 100644 --- a/drivers/net/wireless/iwlwifi/iwl-csr.h +++ b/drivers/net/wireless/iwlwifi/iwl-csr.h | |||
@@ -155,18 +155,10 @@ | |||
155 | #define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250) | 155 | #define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250) |
156 | 156 | ||
157 | /* Bits for CSR_HW_IF_CONFIG_REG */ | 157 | /* Bits for CSR_HW_IF_CONFIG_REG */ |
158 | #define CSR49_HW_IF_CONFIG_REG_BIT_4965_R (0x00000010) | ||
159 | #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00) | 158 | #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00) |
160 | #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) | 159 | #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) |
161 | #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) | 160 | #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) |
162 | 161 | ||
163 | #define CSR39_HW_IF_CONFIG_REG_BIT_3945_MB (0x00000100) | ||
164 | #define CSR39_HW_IF_CONFIG_REG_BIT_3945_MM (0x00000200) | ||
165 | #define CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC (0x00000400) | ||
166 | #define CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE (0x00000800) | ||
167 | #define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000) | ||
168 | #define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000) | ||
169 | |||
170 | #define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) | 162 | #define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) |
171 | #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) | 163 | #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) |
172 | #define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ | 164 | #define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ |
@@ -186,7 +178,7 @@ | |||
186 | #define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ | 178 | #define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ |
187 | #define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ | 179 | #define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ |
188 | #define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ | 180 | #define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ |
189 | #define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses, 3945 */ | 181 | #define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ |
190 | #define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ | 182 | #define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ |
191 | #define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ | 183 | #define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ |
192 | 184 | ||
@@ -202,29 +194,17 @@ | |||
202 | /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ | 194 | /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ |
203 | #define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ | 195 | #define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ |
204 | #define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ | 196 | #define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ |
205 | #define CSR39_FH_INT_BIT_RX_CHNL2 (1 << 18) /* Rx channel 2 (3945 only) */ | ||
206 | #define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ | 197 | #define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ |
207 | #define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ | 198 | #define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ |
208 | #define CSR39_FH_INT_BIT_TX_CHNL6 (1 << 6) /* Tx channel 6 (3945 only) */ | ||
209 | #define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ | 199 | #define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ |
210 | #define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ | 200 | #define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ |
211 | 201 | ||
212 | #define CSR39_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \ | 202 | #define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \ |
213 | CSR39_FH_INT_BIT_RX_CHNL2 | \ | 203 | CSR_FH_INT_BIT_RX_CHNL1 | \ |
214 | CSR_FH_INT_BIT_RX_CHNL1 | \ | 204 | CSR_FH_INT_BIT_RX_CHNL0) |
215 | CSR_FH_INT_BIT_RX_CHNL0) | ||
216 | |||
217 | |||
218 | #define CSR39_FH_INT_TX_MASK (CSR39_FH_INT_BIT_TX_CHNL6 | \ | ||
219 | CSR_FH_INT_BIT_TX_CHNL1 | \ | ||
220 | CSR_FH_INT_BIT_TX_CHNL0) | ||
221 | |||
222 | #define CSR49_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \ | ||
223 | CSR_FH_INT_BIT_RX_CHNL1 | \ | ||
224 | CSR_FH_INT_BIT_RX_CHNL0) | ||
225 | 205 | ||
226 | #define CSR49_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \ | 206 | #define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \ |
227 | CSR_FH_INT_BIT_TX_CHNL0) | 207 | CSR_FH_INT_BIT_TX_CHNL0) |
228 | 208 | ||
229 | /* GPIO */ | 209 | /* GPIO */ |
230 | #define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) | 210 | #define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) |
@@ -268,7 +248,7 @@ | |||
268 | * Indicates MAC (ucode processor, etc.) is powered up and can run. | 248 | * Indicates MAC (ucode processor, etc.) is powered up and can run. |
269 | * Internal resources are accessible. | 249 | * Internal resources are accessible. |
270 | * NOTE: This does not indicate that the processor is actually running. | 250 | * NOTE: This does not indicate that the processor is actually running. |
271 | * NOTE: This does not indicate that 4965 or 3945 has completed | 251 | * NOTE: This does not indicate that device has completed |
272 | * init or post-power-down restore of internal SRAM memory. | 252 | * init or post-power-down restore of internal SRAM memory. |
273 | * Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that | 253 | * Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that |
274 | * SRAM is restored and uCode is in normal operation mode. | 254 | * SRAM is restored and uCode is in normal operation mode. |
@@ -291,8 +271,6 @@ | |||
291 | 271 | ||
292 | /* HW REV */ | 272 | /* HW REV */ |
293 | #define CSR_HW_REV_TYPE_MSK (0x00001F0) | 273 | #define CSR_HW_REV_TYPE_MSK (0x00001F0) |
294 | #define CSR_HW_REV_TYPE_3945 (0x00000D0) | ||
295 | #define CSR_HW_REV_TYPE_4965 (0x0000000) | ||
296 | #define CSR_HW_REV_TYPE_5300 (0x0000020) | 274 | #define CSR_HW_REV_TYPE_5300 (0x0000020) |
297 | #define CSR_HW_REV_TYPE_5350 (0x0000030) | 275 | #define CSR_HW_REV_TYPE_5350 (0x0000030) |
298 | #define CSR_HW_REV_TYPE_5100 (0x0000050) | 276 | #define CSR_HW_REV_TYPE_5100 (0x0000050) |
@@ -363,7 +341,7 @@ | |||
363 | * 0: MAC_SLEEP | 341 | * 0: MAC_SLEEP |
364 | * uCode sets this when preparing a power-saving power-down. | 342 | * uCode sets this when preparing a power-saving power-down. |
365 | * uCode resets this when power-up is complete and SRAM is sane. | 343 | * uCode resets this when power-up is complete and SRAM is sane. |
366 | * NOTE: 3945/4965 saves internal SRAM data to host when powering down, | 344 | * NOTE: device saves internal SRAM data to host when powering down, |
367 | * and must restore this data after powering back up. | 345 | * and must restore this data after powering back up. |
368 | * MAC_SLEEP is the best indication that restore is complete. | 346 | * MAC_SLEEP is the best indication that restore is complete. |
369 | * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and | 347 | * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and |
@@ -394,7 +372,6 @@ | |||
394 | #define CSR_LED_REG_TRUN_OFF (0x38) | 372 | #define CSR_LED_REG_TRUN_OFF (0x38) |
395 | 373 | ||
396 | /* ANA_PLL */ | 374 | /* ANA_PLL */ |
397 | #define CSR39_ANA_PLL_CFG_VAL (0x01000000) | ||
398 | #define CSR50_ANA_PLL_CFG_VAL (0x00880300) | 375 | #define CSR50_ANA_PLL_CFG_VAL (0x00880300) |
399 | 376 | ||
400 | /* HPET MEM debug */ | 377 | /* HPET MEM debug */ |
diff --git a/drivers/net/wireless/iwlwifi/iwl-eeprom.c b/drivers/net/wireless/iwlwifi/iwl-eeprom.c index 833194a2c639..c831a0f24613 100644 --- a/drivers/net/wireless/iwlwifi/iwl-eeprom.c +++ b/drivers/net/wireless/iwlwifi/iwl-eeprom.c | |||
@@ -198,8 +198,6 @@ static int iwlcore_get_nvm_type(struct iwl_priv *priv) | |||
198 | case CSR_HW_REV_TYPE_NONE: | 198 | case CSR_HW_REV_TYPE_NONE: |
199 | IWL_ERR(priv, "Unknown hardware type\n"); | 199 | IWL_ERR(priv, "Unknown hardware type\n"); |
200 | return -ENOENT; | 200 | return -ENOENT; |
201 | case CSR_HW_REV_TYPE_3945: | ||
202 | case CSR_HW_REV_TYPE_4965: | ||
203 | case CSR_HW_REV_TYPE_5300: | 201 | case CSR_HW_REV_TYPE_5300: |
204 | case CSR_HW_REV_TYPE_5350: | 202 | case CSR_HW_REV_TYPE_5350: |
205 | case CSR_HW_REV_TYPE_5100: | 203 | case CSR_HW_REV_TYPE_5100: |