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authorRickard Strandqvist <rickard_strandqvist@spectrumdigital.se>2014-06-23 17:48:17 -0400
committerJohn W. Linville <linville@tuxdriver.com>2014-06-25 15:40:32 -0400
commit8a607208f522e6b37a93c9258d28d75c15263961 (patch)
tree8d398c596adac62c51bddf2ab710d3b8fd443fed /drivers/net
parent8ac3a2aa7224a7d05f1a71240663c80532969791 (diff)
rtlwifi/rtl8192de: Fix media status register mask
bt_msr & 0xfc will never match 0x3. Fix this by using a mask that actually matches the available types. Signed-off-by: Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se> Reviewed-by: Peter Wu <peter@lekensteyn.nl> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/hw.c2
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/reg.h1
2 files changed, 2 insertions, 1 deletions
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/hw.c b/drivers/net/wireless/rtlwifi/rtl8192de/hw.c
index 2b08671004a0..280c3da42993 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192de/hw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/hw.c
@@ -1128,7 +1128,7 @@ static int _rtl92de_set_media_status(struct ieee80211_hw *hw,
1128 } 1128 }
1129 rtl_write_byte(rtlpriv, REG_CR + 2, bt_msr); 1129 rtl_write_byte(rtlpriv, REG_CR + 2, bt_msr);
1130 rtlpriv->cfg->ops->led_control(hw, ledaction); 1130 rtlpriv->cfg->ops->led_control(hw, ledaction);
1131 if ((bt_msr & 0xfc) == MSR_AP) 1131 if ((bt_msr & MSR_MASK) == MSR_AP)
1132 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 1132 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1133 else 1133 else
1134 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 1134 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/reg.h b/drivers/net/wireless/rtlwifi/rtl8192de/reg.h
index 7f29b8d765b3..315a298bab06 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192de/reg.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/reg.h
@@ -369,6 +369,7 @@
369#define MSR_ADHOC 0x01 369#define MSR_ADHOC 0x01
370#define MSR_INFRA 0x02 370#define MSR_INFRA 0x02
371#define MSR_AP 0x03 371#define MSR_AP 0x03
372#define MSR_MASK 0x03
372 373
373/* 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) */ 374/* 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) */
374/* ----------------------------------------------------- */ 375/* ----------------------------------------------------- */