diff options
author | Sean Hefty <sean.hefty@intel.com> | 2011-06-02 13:43:26 -0400 |
---|---|---|
committer | Roland Dreier <roland@purestorage.com> | 2011-10-13 12:43:46 -0400 |
commit | 18abd5ea571608a7c726fc56e21d3e31f9febfd0 (patch) | |
tree | e2694cadf06a995e658ec30f7a3bd22835dcda7a /drivers/net | |
parent | 012a8ff577f95211c6ffd3b77a94c34ebae009b6 (diff) |
IB/mlx4: Add support for XRC SRQs
Allow the user to create XRC SRQs. This patch is based on a patch
from Jack Morgenstrein <jackm@dev.mellanox.co.il>.
Signed-off-by: Sean Hefty <sean.hefty@intel.com>
Signed-off-by: Roland Dreier <roland@purestorage.com>
Diffstat (limited to 'drivers/net')
-rw-r--r-- | drivers/net/mlx4/srq.c | 20 |
1 files changed, 11 insertions, 9 deletions
diff --git a/drivers/net/mlx4/srq.c b/drivers/net/mlx4/srq.c index 3b07b80a0456..a20b141dbb5c 100644 --- a/drivers/net/mlx4/srq.c +++ b/drivers/net/mlx4/srq.c | |||
@@ -40,20 +40,20 @@ | |||
40 | struct mlx4_srq_context { | 40 | struct mlx4_srq_context { |
41 | __be32 state_logsize_srqn; | 41 | __be32 state_logsize_srqn; |
42 | u8 logstride; | 42 | u8 logstride; |
43 | u8 reserved1[3]; | 43 | u8 reserved1; |
44 | u8 pg_offset; | 44 | __be16 xrcd; |
45 | u8 reserved2[3]; | 45 | __be32 pg_offset_cqn; |
46 | u32 reserved3; | 46 | u32 reserved2; |
47 | u8 log_page_size; | 47 | u8 log_page_size; |
48 | u8 reserved4[2]; | 48 | u8 reserved3[2]; |
49 | u8 mtt_base_addr_h; | 49 | u8 mtt_base_addr_h; |
50 | __be32 mtt_base_addr_l; | 50 | __be32 mtt_base_addr_l; |
51 | __be32 pd; | 51 | __be32 pd; |
52 | __be16 limit_watermark; | 52 | __be16 limit_watermark; |
53 | __be16 wqe_cnt; | 53 | __be16 wqe_cnt; |
54 | u16 reserved5; | 54 | u16 reserved4; |
55 | __be16 wqe_counter; | 55 | __be16 wqe_counter; |
56 | u32 reserved6; | 56 | u32 reserved5; |
57 | __be64 db_rec_addr; | 57 | __be64 db_rec_addr; |
58 | }; | 58 | }; |
59 | 59 | ||
@@ -109,8 +109,8 @@ static int mlx4_QUERY_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox | |||
109 | MLX4_CMD_TIME_CLASS_A); | 109 | MLX4_CMD_TIME_CLASS_A); |
110 | } | 110 | } |
111 | 111 | ||
112 | int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt, | 112 | int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcd, |
113 | u64 db_rec, struct mlx4_srq *srq) | 113 | struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq) |
114 | { | 114 | { |
115 | struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table; | 115 | struct mlx4_srq_table *srq_table = &mlx4_priv(dev)->srq_table; |
116 | struct mlx4_cmd_mailbox *mailbox; | 116 | struct mlx4_cmd_mailbox *mailbox; |
@@ -148,6 +148,8 @@ int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt, | |||
148 | srq_context->state_logsize_srqn = cpu_to_be32((ilog2(srq->max) << 24) | | 148 | srq_context->state_logsize_srqn = cpu_to_be32((ilog2(srq->max) << 24) | |
149 | srq->srqn); | 149 | srq->srqn); |
150 | srq_context->logstride = srq->wqe_shift - 4; | 150 | srq_context->logstride = srq->wqe_shift - 4; |
151 | srq_context->xrcd = cpu_to_be16(xrcd); | ||
152 | srq_context->pg_offset_cqn = cpu_to_be32(cqn & 0xffffff); | ||
151 | srq_context->log_page_size = mtt->page_shift - MLX4_ICM_PAGE_SHIFT; | 153 | srq_context->log_page_size = mtt->page_shift - MLX4_ICM_PAGE_SHIFT; |
152 | 154 | ||
153 | mtt_addr = mlx4_mtt_addr(dev, mtt); | 155 | mtt_addr = mlx4_mtt_addr(dev, mtt); |