diff options
author | Stanislaw Gruszka <sgruszka@redhat.com> | 2011-12-23 02:13:43 -0500 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2012-01-04 14:30:44 -0500 |
commit | 17d4eca6432bb1d4753d7894b824271673a1640a (patch) | |
tree | c8ad71a2202b7ff618fe8dd5c38fec07c31980f1 /drivers/net | |
parent | d71be937202853eda76562e9678073465d5c0fa8 (diff) |
iwlegacy: move some i/o helpers out of inline
This save us about 20k of text size, and should have no impact on
performance as hot paths do not use much I/O.
Before:
text data bss dec hex filename
108512 1784 168 110464 1af80 drivers/net/wireless/iwlegacy/iwl3945.ko
165730 2164 156 168050 29072 drivers/net/wireless/iwlegacy/iwl4965.ko
91942 328 48 92318 1689e drivers/net/wireless/iwlegacy/iwlegacy.ko
After:
text data bss dec hex filename
95556 1784 168 97508 17ce4 drivers/net/wireless/iwlegacy/iwl3945.ko
154853 2164 156 157173 265f5 drivers/net/wireless/iwlegacy/iwl4965.ko
91634 328 48 92010 1676a drivers/net/wireless/iwlegacy/iwlegacy.ko
Signed-off-by: Stanislaw Gruszka <sgruszka@redhat.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net')
-rw-r--r-- | drivers/net/wireless/iwlegacy/common.c | 161 | ||||
-rw-r--r-- | drivers/net/wireless/iwlegacy/common.h | 206 |
2 files changed, 175 insertions, 192 deletions
diff --git a/drivers/net/wireless/iwlegacy/common.c b/drivers/net/wireless/iwlegacy/common.c index 881ba043770a..36454d0bbeed 100644 --- a/drivers/net/wireless/iwlegacy/common.c +++ b/drivers/net/wireless/iwlegacy/common.c | |||
@@ -42,6 +42,167 @@ | |||
42 | 42 | ||
43 | #include "common.h" | 43 | #include "common.h" |
44 | 44 | ||
45 | int | ||
46 | _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout) | ||
47 | { | ||
48 | const int interval = 10; /* microseconds */ | ||
49 | int t = 0; | ||
50 | |||
51 | do { | ||
52 | if ((_il_rd(il, addr) & mask) == (bits & mask)) | ||
53 | return t; | ||
54 | udelay(interval); | ||
55 | t += interval; | ||
56 | } while (t < timeout); | ||
57 | |||
58 | return -ETIMEDOUT; | ||
59 | } | ||
60 | EXPORT_SYMBOL(_il_poll_bit); | ||
61 | |||
62 | void | ||
63 | il_set_bit(struct il_priv *p, u32 r, u32 m) | ||
64 | { | ||
65 | unsigned long reg_flags; | ||
66 | |||
67 | spin_lock_irqsave(&p->reg_lock, reg_flags); | ||
68 | _il_set_bit(p, r, m); | ||
69 | spin_unlock_irqrestore(&p->reg_lock, reg_flags); | ||
70 | } | ||
71 | EXPORT_SYMBOL(il_set_bit); | ||
72 | |||
73 | void | ||
74 | il_clear_bit(struct il_priv *p, u32 r, u32 m) | ||
75 | { | ||
76 | unsigned long reg_flags; | ||
77 | |||
78 | spin_lock_irqsave(&p->reg_lock, reg_flags); | ||
79 | _il_clear_bit(p, r, m); | ||
80 | spin_unlock_irqrestore(&p->reg_lock, reg_flags); | ||
81 | } | ||
82 | EXPORT_SYMBOL(il_clear_bit); | ||
83 | |||
84 | int | ||
85 | _il_grab_nic_access(struct il_priv *il) | ||
86 | { | ||
87 | int ret; | ||
88 | u32 val; | ||
89 | |||
90 | /* this bit wakes up the NIC */ | ||
91 | _il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | ||
92 | |||
93 | /* | ||
94 | * These bits say the device is running, and should keep running for | ||
95 | * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), | ||
96 | * but they do not indicate that embedded SRAM is restored yet; | ||
97 | * 3945 and 4965 have volatile SRAM, and must save/restore contents | ||
98 | * to/from host DRAM when sleeping/waking for power-saving. | ||
99 | * Each direction takes approximately 1/4 millisecond; with this | ||
100 | * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a | ||
101 | * series of register accesses are expected (e.g. reading Event Log), | ||
102 | * to keep device from sleeping. | ||
103 | * | ||
104 | * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that | ||
105 | * SRAM is okay/restored. We don't check that here because this call | ||
106 | * is just for hardware register access; but GP1 MAC_SLEEP check is a | ||
107 | * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log). | ||
108 | * | ||
109 | */ | ||
110 | ret = | ||
111 | _il_poll_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, | ||
112 | (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | | ||
113 | CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); | ||
114 | if (ret < 0) { | ||
115 | val = _il_rd(il, CSR_GP_CNTRL); | ||
116 | IL_ERR("MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val); | ||
117 | _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); | ||
118 | return -EIO; | ||
119 | } | ||
120 | |||
121 | return 0; | ||
122 | } | ||
123 | EXPORT_SYMBOL_GPL(_il_grab_nic_access); | ||
124 | |||
125 | int | ||
126 | il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout) | ||
127 | { | ||
128 | const int interval = 10; /* microseconds */ | ||
129 | int t = 0; | ||
130 | |||
131 | do { | ||
132 | if ((il_rd(il, addr) & mask) == mask) | ||
133 | return t; | ||
134 | udelay(interval); | ||
135 | t += interval; | ||
136 | } while (t < timeout); | ||
137 | |||
138 | return -ETIMEDOUT; | ||
139 | } | ||
140 | EXPORT_SYMBOL(il_poll_bit); | ||
141 | |||
142 | u32 | ||
143 | il_rd_prph(struct il_priv *il, u32 reg) | ||
144 | { | ||
145 | unsigned long reg_flags; | ||
146 | u32 val; | ||
147 | |||
148 | spin_lock_irqsave(&il->reg_lock, reg_flags); | ||
149 | _il_grab_nic_access(il); | ||
150 | val = _il_rd_prph(il, reg); | ||
151 | _il_release_nic_access(il); | ||
152 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); | ||
153 | return val; | ||
154 | } | ||
155 | EXPORT_SYMBOL(il_rd_prph); | ||
156 | |||
157 | void | ||
158 | il_wr_prph(struct il_priv *il, u32 addr, u32 val) | ||
159 | { | ||
160 | unsigned long reg_flags; | ||
161 | |||
162 | spin_lock_irqsave(&il->reg_lock, reg_flags); | ||
163 | if (!_il_grab_nic_access(il)) { | ||
164 | _il_wr_prph(il, addr, val); | ||
165 | _il_release_nic_access(il); | ||
166 | } | ||
167 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); | ||
168 | } | ||
169 | EXPORT_SYMBOL(il_wr_prph); | ||
170 | |||
171 | u32 | ||
172 | il_read_targ_mem(struct il_priv *il, u32 addr) | ||
173 | { | ||
174 | unsigned long reg_flags; | ||
175 | u32 value; | ||
176 | |||
177 | spin_lock_irqsave(&il->reg_lock, reg_flags); | ||
178 | _il_grab_nic_access(il); | ||
179 | |||
180 | _il_wr(il, HBUS_TARG_MEM_RADDR, addr); | ||
181 | rmb(); | ||
182 | value = _il_rd(il, HBUS_TARG_MEM_RDAT); | ||
183 | |||
184 | _il_release_nic_access(il); | ||
185 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); | ||
186 | return value; | ||
187 | } | ||
188 | EXPORT_SYMBOL(il_read_targ_mem); | ||
189 | |||
190 | void | ||
191 | il_write_targ_mem(struct il_priv *il, u32 addr, u32 val) | ||
192 | { | ||
193 | unsigned long reg_flags; | ||
194 | |||
195 | spin_lock_irqsave(&il->reg_lock, reg_flags); | ||
196 | if (!_il_grab_nic_access(il)) { | ||
197 | _il_wr(il, HBUS_TARG_MEM_WADDR, addr); | ||
198 | wmb(); | ||
199 | _il_wr(il, HBUS_TARG_MEM_WDAT, val); | ||
200 | _il_release_nic_access(il); | ||
201 | } | ||
202 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); | ||
203 | } | ||
204 | EXPORT_SYMBOL(il_write_targ_mem); | ||
205 | |||
45 | const char * | 206 | const char * |
46 | il_get_cmd_string(u8 cmd) | 207 | il_get_cmd_string(u8 cmd) |
47 | { | 208 | { |
diff --git a/drivers/net/wireless/iwlegacy/common.h b/drivers/net/wireless/iwlegacy/common.h index 1bc0b02f559c..abfa388588be 100644 --- a/drivers/net/wireless/iwlegacy/common.h +++ b/drivers/net/wireless/iwlegacy/common.h | |||
@@ -31,6 +31,7 @@ | |||
31 | #include <linux/kernel.h> | 31 | #include <linux/kernel.h> |
32 | #include <linux/leds.h> | 32 | #include <linux/leds.h> |
33 | #include <linux/wait.h> | 33 | #include <linux/wait.h> |
34 | #include <linux/io.h> | ||
34 | #include <net/mac80211.h> | 35 | #include <net/mac80211.h> |
35 | #include <net/ieee80211_radiotap.h> | 36 | #include <net/ieee80211_radiotap.h> |
36 | 37 | ||
@@ -2163,7 +2164,15 @@ void il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info, | |||
2163 | 2164 | ||
2164 | irqreturn_t il_isr(int irq, void *data); | 2165 | irqreturn_t il_isr(int irq, void *data); |
2165 | 2166 | ||
2166 | #include <linux/io.h> | 2167 | extern void il_set_bit(struct il_priv *p, u32 r, u32 m); |
2168 | extern void il_clear_bit(struct il_priv *p, u32 r, u32 m); | ||
2169 | extern int _il_grab_nic_access(struct il_priv *il); | ||
2170 | extern int _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout); | ||
2171 | extern int il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout); | ||
2172 | extern u32 il_rd_prph(struct il_priv *il, u32 reg); | ||
2173 | extern void il_wr_prph(struct il_priv *il, u32 addr, u32 val); | ||
2174 | extern u32 il_read_targ_mem(struct il_priv *il, u32 addr); | ||
2175 | extern void il_write_targ_mem(struct il_priv *il, u32 addr, u32 val); | ||
2167 | 2176 | ||
2168 | static inline void | 2177 | static inline void |
2169 | _il_write8(struct il_priv *il, u32 ofs, u8 val) | 2178 | _il_write8(struct il_priv *il, u32 ofs, u8 val) |
@@ -2184,38 +2193,6 @@ _il_rd(struct il_priv *il, u32 ofs) | |||
2184 | return ioread32(il->hw_base + ofs); | 2193 | return ioread32(il->hw_base + ofs); |
2185 | } | 2194 | } |
2186 | 2195 | ||
2187 | #define IL_POLL_INTERVAL 10 /* microseconds */ | ||
2188 | static inline int | ||
2189 | _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout) | ||
2190 | { | ||
2191 | int t = 0; | ||
2192 | |||
2193 | do { | ||
2194 | if ((_il_rd(il, addr) & mask) == (bits & mask)) | ||
2195 | return t; | ||
2196 | udelay(IL_POLL_INTERVAL); | ||
2197 | t += IL_POLL_INTERVAL; | ||
2198 | } while (t < timeout); | ||
2199 | |||
2200 | return -ETIMEDOUT; | ||
2201 | } | ||
2202 | |||
2203 | static inline void | ||
2204 | _il_set_bit(struct il_priv *il, u32 reg, u32 mask) | ||
2205 | { | ||
2206 | _il_wr(il, reg, _il_rd(il, reg) | mask); | ||
2207 | } | ||
2208 | |||
2209 | static inline void | ||
2210 | il_set_bit(struct il_priv *p, u32 r, u32 m) | ||
2211 | { | ||
2212 | unsigned long reg_flags; | ||
2213 | |||
2214 | spin_lock_irqsave(&p->reg_lock, reg_flags); | ||
2215 | _il_set_bit(p, r, m); | ||
2216 | spin_unlock_irqrestore(&p->reg_lock, reg_flags); | ||
2217 | } | ||
2218 | |||
2219 | static inline void | 2196 | static inline void |
2220 | _il_clear_bit(struct il_priv *il, u32 reg, u32 mask) | 2197 | _il_clear_bit(struct il_priv *il, u32 reg, u32 mask) |
2221 | { | 2198 | { |
@@ -2223,53 +2200,9 @@ _il_clear_bit(struct il_priv *il, u32 reg, u32 mask) | |||
2223 | } | 2200 | } |
2224 | 2201 | ||
2225 | static inline void | 2202 | static inline void |
2226 | il_clear_bit(struct il_priv *p, u32 r, u32 m) | 2203 | _il_set_bit(struct il_priv *il, u32 reg, u32 mask) |
2227 | { | ||
2228 | unsigned long reg_flags; | ||
2229 | |||
2230 | spin_lock_irqsave(&p->reg_lock, reg_flags); | ||
2231 | _il_clear_bit(p, r, m); | ||
2232 | spin_unlock_irqrestore(&p->reg_lock, reg_flags); | ||
2233 | } | ||
2234 | |||
2235 | static inline int | ||
2236 | _il_grab_nic_access(struct il_priv *il) | ||
2237 | { | 2204 | { |
2238 | int ret; | 2205 | _il_wr(il, reg, _il_rd(il, reg) | mask); |
2239 | u32 val; | ||
2240 | |||
2241 | /* this bit wakes up the NIC */ | ||
2242 | _il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | ||
2243 | |||
2244 | /* | ||
2245 | * These bits say the device is running, and should keep running for | ||
2246 | * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), | ||
2247 | * but they do not indicate that embedded SRAM is restored yet; | ||
2248 | * 3945 and 4965 have volatile SRAM, and must save/restore contents | ||
2249 | * to/from host DRAM when sleeping/waking for power-saving. | ||
2250 | * Each direction takes approximately 1/4 millisecond; with this | ||
2251 | * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a | ||
2252 | * series of register accesses are expected (e.g. reading Event Log), | ||
2253 | * to keep device from sleeping. | ||
2254 | * | ||
2255 | * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that | ||
2256 | * SRAM is okay/restored. We don't check that here because this call | ||
2257 | * is just for hardware register access; but GP1 MAC_SLEEP check is a | ||
2258 | * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log). | ||
2259 | * | ||
2260 | */ | ||
2261 | ret = | ||
2262 | _il_poll_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, | ||
2263 | (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | | ||
2264 | CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); | ||
2265 | if (ret < 0) { | ||
2266 | val = _il_rd(il, CSR_GP_CNTRL); | ||
2267 | IL_ERR("MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val); | ||
2268 | _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); | ||
2269 | return -EIO; | ||
2270 | } | ||
2271 | |||
2272 | return 0; | ||
2273 | } | 2206 | } |
2274 | 2207 | ||
2275 | static inline void | 2208 | static inline void |
@@ -2290,7 +2223,6 @@ il_rd(struct il_priv *il, u32 reg) | |||
2290 | _il_release_nic_access(il); | 2223 | _il_release_nic_access(il); |
2291 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); | 2224 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); |
2292 | return value; | 2225 | return value; |
2293 | |||
2294 | } | 2226 | } |
2295 | 2227 | ||
2296 | static inline void | 2228 | static inline void |
@@ -2306,32 +2238,6 @@ il_wr(struct il_priv *il, u32 reg, u32 value) | |||
2306 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); | 2238 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); |
2307 | } | 2239 | } |
2308 | 2240 | ||
2309 | static inline void | ||
2310 | il_write_reg_buf(struct il_priv *il, u32 reg, u32 len, u32 * values) | ||
2311 | { | ||
2312 | u32 count = sizeof(u32); | ||
2313 | |||
2314 | if (il != NULL && values != NULL) { | ||
2315 | for (; 0 < len; len -= count, reg += count, values++) | ||
2316 | il_wr(il, reg, *values); | ||
2317 | } | ||
2318 | } | ||
2319 | |||
2320 | static inline int | ||
2321 | il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout) | ||
2322 | { | ||
2323 | int t = 0; | ||
2324 | |||
2325 | do { | ||
2326 | if ((il_rd(il, addr) & mask) == mask) | ||
2327 | return t; | ||
2328 | udelay(IL_POLL_INTERVAL); | ||
2329 | t += IL_POLL_INTERVAL; | ||
2330 | } while (t < timeout); | ||
2331 | |||
2332 | return -ETIMEDOUT; | ||
2333 | } | ||
2334 | |||
2335 | static inline u32 | 2241 | static inline u32 |
2336 | _il_rd_prph(struct il_priv *il, u32 reg) | 2242 | _il_rd_prph(struct il_priv *il, u32 reg) |
2337 | { | 2243 | { |
@@ -2340,20 +2246,6 @@ _il_rd_prph(struct il_priv *il, u32 reg) | |||
2340 | return _il_rd(il, HBUS_TARG_PRPH_RDAT); | 2246 | return _il_rd(il, HBUS_TARG_PRPH_RDAT); |
2341 | } | 2247 | } |
2342 | 2248 | ||
2343 | static inline u32 | ||
2344 | il_rd_prph(struct il_priv *il, u32 reg) | ||
2345 | { | ||
2346 | unsigned long reg_flags; | ||
2347 | u32 val; | ||
2348 | |||
2349 | spin_lock_irqsave(&il->reg_lock, reg_flags); | ||
2350 | _il_grab_nic_access(il); | ||
2351 | val = _il_rd_prph(il, reg); | ||
2352 | _il_release_nic_access(il); | ||
2353 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); | ||
2354 | return val; | ||
2355 | } | ||
2356 | |||
2357 | static inline void | 2249 | static inline void |
2358 | _il_wr_prph(struct il_priv *il, u32 addr, u32 val) | 2250 | _il_wr_prph(struct il_priv *il, u32 addr, u32 val) |
2359 | { | 2251 | { |
@@ -2363,37 +2255,17 @@ _il_wr_prph(struct il_priv *il, u32 addr, u32 val) | |||
2363 | } | 2255 | } |
2364 | 2256 | ||
2365 | static inline void | 2257 | static inline void |
2366 | il_wr_prph(struct il_priv *il, u32 addr, u32 val) | ||
2367 | { | ||
2368 | unsigned long reg_flags; | ||
2369 | |||
2370 | spin_lock_irqsave(&il->reg_lock, reg_flags); | ||
2371 | if (!_il_grab_nic_access(il)) { | ||
2372 | _il_wr_prph(il, addr, val); | ||
2373 | _il_release_nic_access(il); | ||
2374 | } | ||
2375 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); | ||
2376 | } | ||
2377 | |||
2378 | #define _il_set_bits_prph(il, reg, mask) \ | ||
2379 | _il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask)) | ||
2380 | |||
2381 | static inline void | ||
2382 | il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask) | 2258 | il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask) |
2383 | { | 2259 | { |
2384 | unsigned long reg_flags; | 2260 | unsigned long reg_flags; |
2385 | 2261 | ||
2386 | spin_lock_irqsave(&il->reg_lock, reg_flags); | 2262 | spin_lock_irqsave(&il->reg_lock, reg_flags); |
2387 | _il_grab_nic_access(il); | 2263 | _il_grab_nic_access(il); |
2388 | _il_set_bits_prph(il, reg, mask); | 2264 | _il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask)); |
2389 | _il_release_nic_access(il); | 2265 | _il_release_nic_access(il); |
2390 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); | 2266 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); |
2391 | } | 2267 | } |
2392 | 2268 | ||
2393 | #define _il_set_bits_mask_prph(il, reg, bits, mask) \ | ||
2394 | _il_wr_prph(il, reg, \ | ||
2395 | ((_il_rd_prph(il, reg) & mask) | bits)) | ||
2396 | |||
2397 | static inline void | 2269 | static inline void |
2398 | il_set_bits_mask_prph(struct il_priv *il, u32 reg, u32 bits, u32 mask) | 2270 | il_set_bits_mask_prph(struct il_priv *il, u32 reg, u32 bits, u32 mask) |
2399 | { | 2271 | { |
@@ -2401,7 +2273,7 @@ il_set_bits_mask_prph(struct il_priv *il, u32 reg, u32 bits, u32 mask) | |||
2401 | 2273 | ||
2402 | spin_lock_irqsave(&il->reg_lock, reg_flags); | 2274 | spin_lock_irqsave(&il->reg_lock, reg_flags); |
2403 | _il_grab_nic_access(il); | 2275 | _il_grab_nic_access(il); |
2404 | _il_set_bits_mask_prph(il, reg, bits, mask); | 2276 | _il_wr_prph(il, reg, ((_il_rd_prph(il, reg) & mask) | bits)); |
2405 | _il_release_nic_access(il); | 2277 | _il_release_nic_access(il); |
2406 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); | 2278 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); |
2407 | } | 2279 | } |
@@ -2420,56 +2292,6 @@ il_clear_bits_prph(struct il_priv *il, u32 reg, u32 mask) | |||
2420 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); | 2292 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); |
2421 | } | 2293 | } |
2422 | 2294 | ||
2423 | static inline u32 | ||
2424 | il_read_targ_mem(struct il_priv *il, u32 addr) | ||
2425 | { | ||
2426 | unsigned long reg_flags; | ||
2427 | u32 value; | ||
2428 | |||
2429 | spin_lock_irqsave(&il->reg_lock, reg_flags); | ||
2430 | _il_grab_nic_access(il); | ||
2431 | |||
2432 | _il_wr(il, HBUS_TARG_MEM_RADDR, addr); | ||
2433 | rmb(); | ||
2434 | value = _il_rd(il, HBUS_TARG_MEM_RDAT); | ||
2435 | |||
2436 | _il_release_nic_access(il); | ||
2437 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); | ||
2438 | return value; | ||
2439 | } | ||
2440 | |||
2441 | static inline void | ||
2442 | il_write_targ_mem(struct il_priv *il, u32 addr, u32 val) | ||
2443 | { | ||
2444 | unsigned long reg_flags; | ||
2445 | |||
2446 | spin_lock_irqsave(&il->reg_lock, reg_flags); | ||
2447 | if (!_il_grab_nic_access(il)) { | ||
2448 | _il_wr(il, HBUS_TARG_MEM_WADDR, addr); | ||
2449 | wmb(); | ||
2450 | _il_wr(il, HBUS_TARG_MEM_WDAT, val); | ||
2451 | _il_release_nic_access(il); | ||
2452 | } | ||
2453 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); | ||
2454 | } | ||
2455 | |||
2456 | static inline void | ||
2457 | il_write_targ_mem_buf(struct il_priv *il, u32 addr, u32 len, u32 * values) | ||
2458 | { | ||
2459 | unsigned long reg_flags; | ||
2460 | |||
2461 | spin_lock_irqsave(&il->reg_lock, reg_flags); | ||
2462 | if (!_il_grab_nic_access(il)) { | ||
2463 | _il_wr(il, HBUS_TARG_MEM_WADDR, addr); | ||
2464 | wmb(); | ||
2465 | for (; 0 < len; len -= sizeof(u32), values++) | ||
2466 | _il_wr(il, HBUS_TARG_MEM_WDAT, *values); | ||
2467 | |||
2468 | _il_release_nic_access(il); | ||
2469 | } | ||
2470 | spin_unlock_irqrestore(&il->reg_lock, reg_flags); | ||
2471 | } | ||
2472 | |||
2473 | #define HW_KEY_DYNAMIC 0 | 2295 | #define HW_KEY_DYNAMIC 0 |
2474 | #define HW_KEY_DEFAULT 1 | 2296 | #define HW_KEY_DEFAULT 1 |
2475 | 2297 | ||