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authorStephen Hemminger <shemminger@osdl.org>2006-09-26 14:57:38 -0400
committerJeff Garzik <jeff@garzik.org>2006-09-27 17:56:31 -0400
commit91aeb3edbcf4e6ed72d138ac8c22fd68e6d717c3 (patch)
tree47e6dc5ace173532b438f35a1e899545178abcc9 /drivers/net
parente0ed5459030a8c9ddde44ef49bcb63aa6db425e1 (diff)
[PATCH] sky2: use standard pci register capabilties for error register
Use the standard pci capability mechanism to access PCI express error registers, rather than hard coding the offset. Mask off the PCI express error from ever occuring on non-PCI express systems. Signed-off-by: Stephen Hemminger <shemminger@osdl.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/sky2.c32
-rw-r--r--drivers/net/sky2.h45
2 files changed, 25 insertions, 52 deletions
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index 3ff2f426fd63..d3174ed8e454 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -2093,7 +2093,7 @@ static void sky2_hw_intr(struct sky2_hw *hw)
2093 2093
2094 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2094 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2095 sky2_pci_write16(hw, PCI_STATUS, 2095 sky2_pci_write16(hw, PCI_STATUS,
2096 pci_err | PCI_STATUS_ERROR_BITS); 2096 pci_err | PCI_STATUS_ERROR_BITS);
2097 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2097 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2098 } 2098 }
2099 2099
@@ -2101,7 +2101,8 @@ static void sky2_hw_intr(struct sky2_hw *hw)
2101 /* PCI-Express uncorrectable Error occurred */ 2101 /* PCI-Express uncorrectable Error occurred */
2102 u32 pex_err; 2102 u32 pex_err;
2103 2103
2104 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT); 2104 pex_err = sky2_pci_read32(hw,
2105 hw->err_cap + PCI_ERR_UNCOR_STATUS);
2105 2106
2106 if (net_ratelimit()) 2107 if (net_ratelimit())
2107 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n", 2108 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
@@ -2109,15 +2110,20 @@ static void sky2_hw_intr(struct sky2_hw *hw)
2109 2110
2110 /* clear the interrupt */ 2111 /* clear the interrupt */
2111 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2112 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2112 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 2113 sky2_pci_write32(hw,
2113 0xffffffffUL); 2114 hw->err_cap + PCI_ERR_UNCOR_STATUS,
2115 0xffffffffUL);
2114 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2116 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2115 2117
2116 if (pex_err & PEX_FATAL_ERRORS) { 2118
2119 /* In case of fatal error mask off to keep from getting stuck */
2120 if (pex_err & (PCI_ERR_UNC_POISON_TLP | PCI_ERR_UNC_FCP
2121 | PCI_ERR_UNC_DLP)) {
2117 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); 2122 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2118 hwmsk &= ~Y2_IS_PCI_EXP; 2123 hwmsk &= ~Y2_IS_PCI_EXP;
2119 sky2_write32(hw, B0_HWE_IMSK, hwmsk); 2124 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2120 } 2125 }
2126
2121 } 2127 }
2122 2128
2123 if (status & Y2_HWE_L1_MASK) 2129 if (status & Y2_HWE_L1_MASK)
@@ -2298,6 +2304,7 @@ static int sky2_reset(struct sky2_hw *hw)
2298 u16 status; 2304 u16 status;
2299 u8 t8; 2305 u8 t8;
2300 int i; 2306 int i;
2307 u32 msk;
2301 2308
2302 sky2_write8(hw, B0_CTST, CS_RST_CLR); 2309 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2303 2310
@@ -2338,9 +2345,13 @@ static int sky2_reset(struct sky2_hw *hw)
2338 sky2_write8(hw, B0_CTST, CS_MRST_CLR); 2345 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2339 2346
2340 /* clear any PEX errors */ 2347 /* clear any PEX errors */
2341 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) 2348 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) {
2342 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL); 2349 hw->err_cap = pci_find_ext_capability(hw->pdev, PCI_EXT_CAP_ID_ERR);
2343 2350 if (hw->err_cap)
2351 sky2_pci_write32(hw,
2352 hw->err_cap + PCI_ERR_UNCOR_STATUS,
2353 0xffffffffUL);
2354 }
2344 2355
2345 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP); 2356 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2346 hw->ports = 1; 2357 hw->ports = 1;
@@ -2397,7 +2408,10 @@ static int sky2_reset(struct sky2_hw *hw)
2397 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); 2408 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2398 } 2409 }
2399 2410
2400 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK); 2411 msk = Y2_HWE_ALL_MASK;
2412 if (!hw->err_cap)
2413 msk &= ~Y2_IS_PCI_EXP;
2414 sky2_write32(hw, B0_HWE_IMSK, msk);
2401 2415
2402 for (i = 0; i < hw->ports; i++) 2416 for (i = 0; i < hw->ports; i++)
2403 sky2_gmac_reset(hw, i); 2417 sky2_gmac_reset(hw, i);
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index 4c13c371bc21..b2981565e9e3 100644
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -4,24 +4,15 @@
4#ifndef _SKY2_H 4#ifndef _SKY2_H
5#define _SKY2_H 5#define _SKY2_H
6 6
7/* PCI config registers */ 7/* PCI device specific config registers */
8enum { 8enum {
9 PCI_DEV_REG1 = 0x40, 9 PCI_DEV_REG1 = 0x40,
10 PCI_DEV_REG2 = 0x44, 10 PCI_DEV_REG2 = 0x44,
11 PCI_DEV_STATUS = 0x7c,
12 PCI_DEV_REG3 = 0x80, 11 PCI_DEV_REG3 = 0x80,
13 PCI_DEV_REG4 = 0x84, 12 PCI_DEV_REG4 = 0x84,
14 PCI_DEV_REG5 = 0x88, 13 PCI_DEV_REG5 = 0x88,
15}; 14};
16 15
17enum {
18 PEX_DEV_CAP = 0xe4,
19 PEX_DEV_CTRL = 0xe8,
20 PEX_DEV_STA = 0xea,
21 PEX_LNK_STAT = 0xf2,
22 PEX_UNC_ERR_STAT= 0x104,
23};
24
25/* Yukon-2 */ 16/* Yukon-2 */
26enum pci_dev_reg_1 { 17enum pci_dev_reg_1 {
27 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */ 18 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
@@ -70,39 +61,6 @@ enum pci_dev_reg_4 {
70 PCI_STATUS_REC_MASTER_ABORT | \ 61 PCI_STATUS_REC_MASTER_ABORT | \
71 PCI_STATUS_REC_TARGET_ABORT | \ 62 PCI_STATUS_REC_TARGET_ABORT | \
72 PCI_STATUS_PARITY) 63 PCI_STATUS_PARITY)
73
74enum pex_dev_ctrl {
75 PEX_DC_MAX_RRS_MSK = 7<<12, /* Bit 14..12: Max. Read Request Size */
76 PEX_DC_EN_NO_SNOOP = 1<<11,/* Enable No Snoop */
77 PEX_DC_EN_AUX_POW = 1<<10,/* Enable AUX Power */
78 PEX_DC_EN_PHANTOM = 1<<9, /* Enable Phantom Functions */
79 PEX_DC_EN_EXT_TAG = 1<<8, /* Enable Extended Tag Field */
80 PEX_DC_MAX_PLS_MSK = 7<<5, /* Bit 7.. 5: Max. Payload Size Mask */
81 PEX_DC_EN_REL_ORD = 1<<4, /* Enable Relaxed Ordering */
82 PEX_DC_EN_UNS_RQ_RP = 1<<3, /* Enable Unsupported Request Reporting */
83 PEX_DC_EN_FAT_ER_RP = 1<<2, /* Enable Fatal Error Reporting */
84 PEX_DC_EN_NFA_ER_RP = 1<<1, /* Enable Non-Fatal Error Reporting */
85 PEX_DC_EN_COR_ER_RP = 1<<0, /* Enable Correctable Error Reporting */
86};
87#define PEX_DC_MAX_RD_RQ_SIZE(x) (((x)<<12) & PEX_DC_MAX_RRS_MSK)
88
89/* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */
90enum pex_err {
91 PEX_UNSUP_REQ = 1<<20, /* Unsupported Request Error */
92
93 PEX_MALFOR_TLP = 1<<18, /* Malformed TLP */
94
95 PEX_UNEXP_COMP = 1<<16, /* Unexpected Completion */
96
97 PEX_COMP_TO = 1<<14, /* Completion Timeout */
98 PEX_FLOW_CTRL_P = 1<<13, /* Flow Control Protocol Error */
99 PEX_POIS_TLP = 1<<12, /* Poisoned TLP */
100
101 PEX_DATA_LINK_P = 1<<4, /* Data Link Protocol Error */
102 PEX_FATAL_ERRORS= (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P),
103};
104
105
106enum csr_regs { 64enum csr_regs {
107 B0_RAP = 0x0000, 65 B0_RAP = 0x0000,
108 B0_CTST = 0x0004, 66 B0_CTST = 0x0004,
@@ -1873,6 +1831,7 @@ struct sky2_hw {
1873 struct net_device *dev[2]; 1831 struct net_device *dev[2];
1874 1832
1875 int pm_cap; 1833 int pm_cap;
1834 int err_cap;
1876 u8 chip_id; 1835 u8 chip_id;
1877 u8 chip_rev; 1836 u8 chip_rev;
1878 u8 pmd_type; 1837 u8 pmd_type;