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authorLinus Torvalds <torvalds@woody.osdl.org>2007-01-09 12:37:18 -0500
committerLinus Torvalds <torvalds@woody.osdl.org>2007-01-09 12:37:18 -0500
commit76a2f047880c2c7779f8950c50ee8f3855a5e6df (patch)
treea491d075e353b1ed01b069cca4963b21085d818e /drivers/net
parent97bee8e25da4dfc3b7a369fb2c2f280f5c1918c2 (diff)
parentcb48cfe8079ddda78425a16d6c1be57d822b365b (diff)
Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6: [TCP]: Fix iov_len calculation in tcp_v4_send_ack(). [NETFILTER]: nf_conntrack_netbios_ns: fix uninitialized member in expectation [TG3]: Add PHY workaround for 5755M. [BNX2]: Update version and reldate. [BNX2]: Fix bug in bnx2_nvram_write(). [BNX2]: Fix 5709 Serdes detection. [BNX2]: Don't apply CRC PHY workaround to 5709. NetLabel: correct CIPSO tag handling when adding new DOI definitions NetLabel: correct locking in selinux_netlbl_socket_setsid() [Bluetooth] Correct SCO buffer for Broadcom based Dell laptops [Bluetooth] Correct SCO buffer for Broadcom based HP laptops [Bluetooth] Correct SCO buffer size for another ThinkPad laptop [Bluetooth] Handle device registration failures [Bluetooth] Fix uninitialized return value for RFCOMM sendmsg() [Bluetooth] More checks if DLC is still attached to the TTY [Bluetooth] Add packet size checks for CAPI messages [X25]: Trivial, SOCK_DEBUG's in x25_facilities missing newlines [INET]: Fix incorrect "inet_sock->is_icsk" assignment.
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/bnx2.c75
-rw-r--r--drivers/net/tg3.c17
-rw-r--r--drivers/net/tg3.h4
3 files changed, 71 insertions, 25 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index ada5e9b9988c..ca5acc4736df 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -57,8 +57,8 @@
57 57
58#define DRV_MODULE_NAME "bnx2" 58#define DRV_MODULE_NAME "bnx2"
59#define PFX DRV_MODULE_NAME ": " 59#define PFX DRV_MODULE_NAME ": "
60#define DRV_MODULE_VERSION "1.5.2" 60#define DRV_MODULE_VERSION "1.5.3"
61#define DRV_MODULE_RELDATE "December 13, 2006" 61#define DRV_MODULE_RELDATE "January 8, 2007"
62 62
63#define RUN_AT(x) (jiffies + (x)) 63#define RUN_AT(x) (jiffies + (x))
64 64
@@ -1345,8 +1345,6 @@ bnx2_init_copper_phy(struct bnx2 *bp)
1345{ 1345{
1346 u32 val; 1346 u32 val;
1347 1347
1348 bp->phy_flags |= PHY_CRC_FIX_FLAG;
1349
1350 if (bp->phy_flags & PHY_CRC_FIX_FLAG) { 1348 if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1351 bnx2_write_phy(bp, 0x18, 0x0c00); 1349 bnx2_write_phy(bp, 0x18, 0x0c00);
1352 bnx2_write_phy(bp, 0x17, 0x000a); 1350 bnx2_write_phy(bp, 0x17, 0x000a);
@@ -3085,7 +3083,7 @@ bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
3085 int buf_size) 3083 int buf_size)
3086{ 3084{
3087 u32 written, offset32, len32; 3085 u32 written, offset32, len32;
3088 u8 *buf, start[4], end[4], *flash_buffer = NULL; 3086 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
3089 int rc = 0; 3087 int rc = 0;
3090 int align_start, align_end; 3088 int align_start, align_end;
3091 3089
@@ -3113,16 +3111,17 @@ bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
3113 } 3111 }
3114 3112
3115 if (align_start || align_end) { 3113 if (align_start || align_end) {
3116 buf = kmalloc(len32, GFP_KERNEL); 3114 align_buf = kmalloc(len32, GFP_KERNEL);
3117 if (buf == NULL) 3115 if (align_buf == NULL)
3118 return -ENOMEM; 3116 return -ENOMEM;
3119 if (align_start) { 3117 if (align_start) {
3120 memcpy(buf, start, 4); 3118 memcpy(align_buf, start, 4);
3121 } 3119 }
3122 if (align_end) { 3120 if (align_end) {
3123 memcpy(buf + len32 - 4, end, 4); 3121 memcpy(align_buf + len32 - 4, end, 4);
3124 } 3122 }
3125 memcpy(buf + align_start, data_buf, buf_size); 3123 memcpy(align_buf + align_start, data_buf, buf_size);
3124 buf = align_buf;
3126 } 3125 }
3127 3126
3128 if (bp->flash_info->buffered == 0) { 3127 if (bp->flash_info->buffered == 0) {
@@ -3256,11 +3255,8 @@ bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
3256 } 3255 }
3257 3256
3258nvram_write_end: 3257nvram_write_end:
3259 if (bp->flash_info->buffered == 0) 3258 kfree(flash_buffer);
3260 kfree(flash_buffer); 3259 kfree(align_buf);
3261
3262 if (align_start || align_end)
3263 kfree(buf);
3264 return rc; 3260 return rc;
3265} 3261}
3266 3262
@@ -5645,6 +5641,44 @@ poll_bnx2(struct net_device *dev)
5645} 5641}
5646#endif 5642#endif
5647 5643
5644static void __devinit
5645bnx2_get_5709_media(struct bnx2 *bp)
5646{
5647 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
5648 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
5649 u32 strap;
5650
5651 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
5652 return;
5653 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
5654 bp->phy_flags |= PHY_SERDES_FLAG;
5655 return;
5656 }
5657
5658 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
5659 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
5660 else
5661 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
5662
5663 if (PCI_FUNC(bp->pdev->devfn) == 0) {
5664 switch (strap) {
5665 case 0x4:
5666 case 0x5:
5667 case 0x6:
5668 bp->phy_flags |= PHY_SERDES_FLAG;
5669 return;
5670 }
5671 } else {
5672 switch (strap) {
5673 case 0x1:
5674 case 0x2:
5675 case 0x4:
5676 bp->phy_flags |= PHY_SERDES_FLAG;
5677 return;
5678 }
5679 }
5680}
5681
5648static int __devinit 5682static int __devinit
5649bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) 5683bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5650{ 5684{
@@ -5865,10 +5899,9 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5865 bp->phy_addr = 1; 5899 bp->phy_addr = 1;
5866 5900
5867 /* Disable WOL support if we are running on a SERDES chip. */ 5901 /* Disable WOL support if we are running on a SERDES chip. */
5868 if (CHIP_NUM(bp) == CHIP_NUM_5709) { 5902 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5869 if (CHIP_BOND_ID(bp) != BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) 5903 bnx2_get_5709_media(bp);
5870 bp->phy_flags |= PHY_SERDES_FLAG; 5904 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
5871 } else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
5872 bp->phy_flags |= PHY_SERDES_FLAG; 5905 bp->phy_flags |= PHY_SERDES_FLAG;
5873 5906
5874 if (bp->phy_flags & PHY_SERDES_FLAG) { 5907 if (bp->phy_flags & PHY_SERDES_FLAG) {
@@ -5880,7 +5913,9 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5880 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G) 5913 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
5881 bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG; 5914 bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
5882 } 5915 }
5883 } 5916 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
5917 CHIP_NUM(bp) == CHIP_NUM_5708)
5918 bp->phy_flags |= PHY_CRC_FIX_FLAG;
5884 5919
5885 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) || 5920 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
5886 (CHIP_ID(bp) == CHIP_ID_5708_B0) || 5921 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 4056ba1ff3c7..f4bf62c2a7a5 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -68,8 +68,8 @@
68 68
69#define DRV_MODULE_NAME "tg3" 69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": " 70#define PFX DRV_MODULE_NAME ": "
71#define DRV_MODULE_VERSION "3.71" 71#define DRV_MODULE_VERSION "3.72"
72#define DRV_MODULE_RELDATE "December 15, 2006" 72#define DRV_MODULE_RELDATE "January 8, 2007"
73 73
74#define TG3_DEF_MAC_MODE 0 74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0 75#define TG3_DEF_RX_MODE 0
@@ -1015,7 +1015,12 @@ out:
1015 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) { 1015 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1016 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); 1016 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1017 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); 1017 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1018 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); 1018 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1019 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1020 tg3_writephy(tp, MII_TG3_TEST1,
1021 MII_TG3_TEST1_TRIM_EN | 0x4);
1022 } else
1023 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1019 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); 1024 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1020 } 1025 }
1021 /* Set Extended packet length bit (bit 14) on all chips that */ 1026 /* Set Extended packet length bit (bit 14) on all chips that */
@@ -10803,9 +10808,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
10803 10808
10804 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { 10809 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10805 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || 10810 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10806 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) 10811 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
10807 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG; 10812 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10808 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) 10813 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
10814 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
10815 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10809 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG; 10816 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10810 } 10817 }
10811 10818
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index cf78a7e5997b..80f59ac7ec58 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1658,6 +1658,9 @@
1658#define MII_TG3_EPHY_TEST 0x1f /* 5906 PHY register */ 1658#define MII_TG3_EPHY_TEST 0x1f /* 5906 PHY register */
1659#define MII_TG3_EPHY_SHADOW_EN 0x80 1659#define MII_TG3_EPHY_SHADOW_EN 0x80
1660 1660
1661#define MII_TG3_TEST1 0x1e
1662#define MII_TG3_TEST1_TRIM_EN 0x0010
1663
1661/* There are two ways to manage the TX descriptors on the tigon3. 1664/* There are two ways to manage the TX descriptors on the tigon3.
1662 * Either the descriptors are in host DMA'able memory, or they 1665 * Either the descriptors are in host DMA'able memory, or they
1663 * exist only in the cards on-chip SRAM. All 16 send bds are under 1666 * exist only in the cards on-chip SRAM. All 16 send bds are under
@@ -2256,6 +2259,7 @@ struct tg3 {
2256#define TG3_FLG2_1SHOT_MSI 0x10000000 2259#define TG3_FLG2_1SHOT_MSI 0x10000000
2257#define TG3_FLG2_PHY_JITTER_BUG 0x20000000 2260#define TG3_FLG2_PHY_JITTER_BUG 0x20000000
2258#define TG3_FLG2_NO_FWARE_REPORTED 0x40000000 2261#define TG3_FLG2_NO_FWARE_REPORTED 0x40000000
2262#define TG3_FLG2_PHY_ADJUST_TRIM 0x80000000
2259 2263
2260 u32 split_mode_max_reqs; 2264 u32 split_mode_max_reqs;
2261#define SPLIT_MODE_5704_MAX_REQ 3 2265#define SPLIT_MODE_5704_MAX_REQ 3