diff options
author | Matt Carlson <mcarlson@broadcom.com> | 2008-12-21 23:19:57 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2008-12-21 23:19:57 -0500 |
commit | 69fc405318967c7913e5b55cf3906250a26b49d0 (patch) | |
tree | 9b885268fd7cf4d9f6170b8791b934bdd44bb2e3 /drivers/net | |
parent | 027455adacdc142cc018e555ce391014fa227e70 (diff) |
tg3: Remove unused cfgspc device members
This patch removes the pci_bist and pci_hdr_type members from the
device structure and removes the code that references them. They are
not really used.
The patch rounds out the changes by moving the pci_cmd member to plug
a structure hole that would have been created. On 32-bit systems, this
movement removes a subsequent structure hole later in the structure. On
64-bit systems though, the movement merely consolidates two holes into
one larger hole.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Benjamin Li <benli@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r-- | drivers/net/tg3.c | 23 | ||||
-rw-r--r-- | drivers/net/tg3.h | 4 |
2 files changed, 7 insertions, 20 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 9af8c9bb9864..218c11a6ff80 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -12160,7 +12160,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) | |||
12160 | { }, | 12160 | { }, |
12161 | }; | 12161 | }; |
12162 | u32 misc_ctrl_reg; | 12162 | u32 misc_ctrl_reg; |
12163 | u32 cacheline_sz_reg; | ||
12164 | u32 pci_state_reg, grc_misc_cfg; | 12163 | u32 pci_state_reg, grc_misc_cfg; |
12165 | u32 val; | 12164 | u32 val; |
12166 | u16 pci_cmd; | 12165 | u16 pci_cmd; |
@@ -12330,14 +12329,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) | |||
12330 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | 12329 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, |
12331 | tp->misc_host_ctrl); | 12330 | tp->misc_host_ctrl); |
12332 | 12331 | ||
12333 | pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ, | ||
12334 | &cacheline_sz_reg); | ||
12335 | |||
12336 | tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff; | ||
12337 | tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff; | ||
12338 | tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff; | ||
12339 | tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff; | ||
12340 | |||
12341 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || | 12332 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || |
12342 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) | 12333 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) |
12343 | tp->pdev_peer = tg3_find_peer(tp); | 12334 | tp->pdev_peer = tg3_find_peer(tp); |
@@ -12447,17 +12438,15 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) | |||
12447 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | 12438 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) |
12448 | tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER; | 12439 | tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER; |
12449 | 12440 | ||
12441 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, | ||
12442 | &tp->pci_cacheline_sz); | ||
12443 | pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, | ||
12444 | &tp->pci_lat_timer); | ||
12450 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && | 12445 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && |
12451 | tp->pci_lat_timer < 64) { | 12446 | tp->pci_lat_timer < 64) { |
12452 | tp->pci_lat_timer = 64; | 12447 | tp->pci_lat_timer = 64; |
12453 | 12448 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
12454 | cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0); | 12449 | tp->pci_lat_timer); |
12455 | cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8); | ||
12456 | cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16); | ||
12457 | cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24); | ||
12458 | |||
12459 | pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ, | ||
12460 | cacheline_sz_reg); | ||
12461 | } | 12450 | } |
12462 | 12451 | ||
12463 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) { | 12452 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) { |
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index f3cda6428af6..814d82b934db 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h | |||
@@ -2676,10 +2676,9 @@ struct tg3 { | |||
2676 | 2676 | ||
2677 | /* PCI block */ | 2677 | /* PCI block */ |
2678 | u32 pci_chip_rev_id; | 2678 | u32 pci_chip_rev_id; |
2679 | u16 pci_cmd; | ||
2679 | u8 pci_cacheline_sz; | 2680 | u8 pci_cacheline_sz; |
2680 | u8 pci_lat_timer; | 2681 | u8 pci_lat_timer; |
2681 | u8 pci_hdr_type; | ||
2682 | u8 pci_bist; | ||
2683 | 2682 | ||
2684 | int pm_cap; | 2683 | int pm_cap; |
2685 | int msi_cap; | 2684 | int msi_cap; |
@@ -2730,7 +2729,6 @@ struct tg3 { | |||
2730 | 2729 | ||
2731 | u32 led_ctrl; | 2730 | u32 led_ctrl; |
2732 | u32 phy_otp; | 2731 | u32 phy_otp; |
2733 | u16 pci_cmd; | ||
2734 | 2732 | ||
2735 | char board_part_number[24]; | 2733 | char board_part_number[24]; |
2736 | #define TG3_VER_SIZE 32 | 2734 | #define TG3_VER_SIZE 32 |