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authorMichael Chan <mchan@broadcom.com>2008-01-30 00:33:03 -0500
committerDavid S. Miller <davem@davemloft.net>2008-01-31 22:27:12 -0500
commitf3014c0cb60ec15a0a2542cbfae7e8d888aa5cf8 (patch)
tree9b57e7a8c0efdbdaccd9ee1800d3e924ebebbd70 /drivers/net
parentb6c0632105f7d7548f1d642ba830088478d4f2b0 (diff)
[BNX2]: Fix 5706 serdes link down bug.
1. Correct the MII expansion serdes control register definition. 2. Check an additional RUDI_INVALID bit when determining 5706S link. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/bnx2.c2
-rw-r--r--drivers/net/bnx2.h3
2 files changed, 3 insertions, 2 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 34aebc6e7589..353c73fa3433 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -5315,7 +5315,7 @@ bnx2_5706_serdes_has_link(struct bnx2 *bp)
5315 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); 5315 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5316 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg); 5316 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5317 5317
5318 if (an_dbg & MISC_SHDW_AN_DBG_NOSYNC) 5318 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5319 return 0; 5319 return 0;
5320 5320
5321 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1); 5321 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index d8e034700c36..059e1159647f 100644
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -6346,11 +6346,12 @@ struct l2_fhdr {
6346#define MII_BNX2_DSP_EXPAND_REG 0x0f00 6346#define MII_BNX2_DSP_EXPAND_REG 0x0f00
6347#define MII_EXPAND_REG1 (MII_BNX2_DSP_EXPAND_REG | 1) 6347#define MII_EXPAND_REG1 (MII_BNX2_DSP_EXPAND_REG | 1)
6348#define MII_EXPAND_REG1_RUDI_C 0x20 6348#define MII_EXPAND_REG1_RUDI_C 0x20
6349#define MII_EXPAND_SERDES_CTL (MII_BNX2_DSP_EXPAND_REG | 2) 6349#define MII_EXPAND_SERDES_CTL (MII_BNX2_DSP_EXPAND_REG | 3)
6350 6350
6351#define MII_BNX2_MISC_SHADOW 0x1c 6351#define MII_BNX2_MISC_SHADOW 0x1c
6352#define MISC_SHDW_AN_DBG 0x6800 6352#define MISC_SHDW_AN_DBG 0x6800
6353#define MISC_SHDW_AN_DBG_NOSYNC 0x0002 6353#define MISC_SHDW_AN_DBG_NOSYNC 0x0002
6354#define MISC_SHDW_AN_DBG_RUDI_INVALID 0x0100
6354#define MISC_SHDW_MODE_CTL 0x7c00 6355#define MISC_SHDW_MODE_CTL 0x7c00
6355#define MISC_SHDW_MODE_CTL_SIG_DET 0x0010 6356#define MISC_SHDW_MODE_CTL_SIG_DET 0x0010
6356 6357