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authorLinus Torvalds <torvalds@g5.osdl.org>2006-06-20 17:49:00 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-06-20 17:49:00 -0400
commitff9144530e9cfe8923e00172e3f8ff83c3b8ff8b (patch)
treec64a9528dde590b9f3174125ad361f46ee30bba8 /drivers/net
parent25f42b6af09e34c3f92107b36b5aa6edc2fdba2f (diff)
parent96ce2385dd2817da549910001a69ac0a2762a1b9 (diff)
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: (22 commits) [ARM] 3559/1: S3C2442: core and serial port [ARM] 3557/1: S3C24XX: centralise and cleanup uart registration [ARM] 3558/1: SMDK24XX: LED platform devices [ARM] 3534/1: add spi support to lubbock platform [ARM] 3554/1: ARM: Fix dyntick locking [ARM] 3553/1: S3C24XX: earlier print of cpu idcode info [ARM] 3552/1: S3C24XX: Move VA of GPIO for low-level debug [ARM] 3551/1: S3C24XX: PM code failes to compile with CONFIG_DCACHE_WRITETHROUGH [ARM] 3550/1: OSIRIS: fix serial port map for 1:1 [ARM] 3548/1: Fix the ARMv6 CPU id in compressed/head.S [ARM] 3335/1: Old-abi Thumb sys_syscall broken [ARM] 3467/1: [3/3] Support for Philips PNX4008 platform: defconfig [ARM] 3466/1: [2/3] Support for Philips PNX4008 platform: chip support [ARM] 3465/1: [1/3] Support for Philips PNX4008 platform: headers [ARM] 3407/1: lpd7x: documetation update [ARM] 3406/1: lpd7x: compilation fix for smc91x [ARM] 3405/1: lpd7a40x: CPLD ssp driver [ARM] 3404/1: lpd7a40x: AMBA CLCD support [ARM] 3403/1: lpd7a40x: updated default configurations [ARM] 3402/1: lpd7a40x: serial driver bug fix ...
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/smc91x.h44
1 files changed, 28 insertions, 16 deletions
diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h
index f72a4f57905a..bf776125ca38 100644
--- a/drivers/net/smc91x.h
+++ b/drivers/net/smc91x.h
@@ -260,15 +260,17 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg)
260#define RPC_LSA_DEFAULT RPC_LED_TX_RX 260#define RPC_LSA_DEFAULT RPC_LED_TX_RX
261#define RPC_LSB_DEFAULT RPC_LED_100_10 261#define RPC_LSB_DEFAULT RPC_LED_100_10
262 262
263#elif defined(CONFIG_MACH_LPD7A400) || defined(CONFIG_MACH_LPD7A404) 263#elif defined(CONFIG_MACH_LPD79520) \
264 || defined(CONFIG_MACH_LPD7A400) \
265 || defined(CONFIG_MACH_LPD7A404)
264 266
265/* The LPD7A40X_IOBARRIER is necessary to overcome a mismatch between 267/* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
266 * the way that the CPU handles chip selects and the way that the SMC 268 * way that the CPU handles chip selects and the way that the SMC chip
267 * chip expects the chip select to operate. Refer to 269 * expects the chip select to operate. Refer to
268 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from 270 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
269 * IOBARRIER is a byte as a least-common denominator of possible 271 * IOBARRIER is a byte, in order that we read the least-common
270 * regions to use as the barrier. It would be wasteful to read 32 272 * denominator. It would be wasteful to read 32 bits from an 8-bit
271 * bits from a byte oriented region. 273 * accessible region.
272 * 274 *
273 * There is no explicit protection against interrupts intervening 275 * There is no explicit protection against interrupts intervening
274 * between the writew and the IOBARRIER. In SMC ISR there is a 276 * between the writew and the IOBARRIER. In SMC ISR there is a
@@ -287,25 +289,35 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg)
287#define SMC_CAN_USE_16BIT 1 289#define SMC_CAN_USE_16BIT 1
288#define SMC_CAN_USE_32BIT 0 290#define SMC_CAN_USE_32BIT 0
289#define SMC_NOWAIT 0 291#define SMC_NOWAIT 0
290#define LPD7A40X_IOBARRIER readb (IOBARRIER_VIRT) 292#define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
291 293
292#define SMC_inw(a,r) readw ((void*) ((a) + (r))) 294#define SMC_inw(a,r)\
293#define SMC_insw(a,r,p,l) readsw ((void*) ((a) + (r)), p, l) 295 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
294#define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7A40X_IOBARRIER; }) 296#define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
295 297
296#define SMC_outsw LPD7A40X_SMC_outsw 298#define SMC_insw LPD7_SMC_insw
299static inline void LPD7_SMC_insw (unsigned char* a, int r,
300 unsigned char* p, int l)
301{
302 unsigned short* ps = (unsigned short*) p;
303 while (l-- > 0) {
304 *ps++ = readw (a + r);
305 LPD7X_IOBARRIER;
306 }
307}
297 308
298static inline void LPD7A40X_SMC_outsw(unsigned long a, int r, 309#define SMC_outsw LPD7_SMC_outsw
299 unsigned char* p, int l) 310static inline void LPD7_SMC_outsw (unsigned char* a, int r,
311 unsigned char* p, int l)
300{ 312{
301 unsigned short* ps = (unsigned short*) p; 313 unsigned short* ps = (unsigned short*) p;
302 while (l-- > 0) { 314 while (l-- > 0) {
303 writew (*ps++, a + r); 315 writew (*ps++, a + r);
304 LPD7A40X_IOBARRIER; 316 LPD7X_IOBARRIER;
305 } 317 }
306} 318}
307 319
308#define SMC_INTERRUPT_PREAMBLE LPD7A40X_IOBARRIER 320#define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
309 321
310#define RPC_LSA_DEFAULT RPC_LED_TX_RX 322#define RPC_LSA_DEFAULT RPC_LED_TX_RX
311#define RPC_LSB_DEFAULT RPC_LED_100_10 323#define RPC_LSB_DEFAULT RPC_LED_100_10