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authorDavid S. Miller <davem@sunset.davemloft.net>2006-06-09 14:58:36 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2006-06-09 15:03:51 -0400
commitf49639e643e69ff233b14966b8d48541d2e17517 (patch)
tree8faeabd3bfc855f0a0a5a5a37d9fdbeed27a3f20 /drivers/net
parent5224e6cc3ab5ae03895bbb67f4a26ce72e62ce58 (diff)
[TG3]: Handle Sun onboard tg3 chips more correctly.
Get rid of all the SUN_570X logic and instead: 1) Make sure MEMARB_ENABLE is set when we probe the SRAM for config information. If that is off we will get timeouts. 2) Always try to sync with the firmware, if there is no firmware running do not treat it as an error and instead just report it the first time we notice this condition. 3) If there is no valid SRAM signature, assume the device is onboard by setting TG3_FLAG_EEPROM_WRITE_PROT. Update driver version and release date. With help from Michael Chan and Fabio Massimo Di Nitto. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/tg3.c144
-rw-r--r--drivers/net/tg3.h3
2 files changed, 50 insertions, 97 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 49ad60b72657..862c226dbbe2 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -69,8 +69,8 @@
69 69
70#define DRV_MODULE_NAME "tg3" 70#define DRV_MODULE_NAME "tg3"
71#define PFX DRV_MODULE_NAME ": " 71#define PFX DRV_MODULE_NAME ": "
72#define DRV_MODULE_VERSION "3.58" 72#define DRV_MODULE_VERSION "3.59"
73#define DRV_MODULE_RELDATE "May 22, 2006" 73#define DRV_MODULE_RELDATE "June 8, 2006"
74 74
75#define TG3_DEF_MAC_MODE 0 75#define TG3_DEF_MAC_MODE 0
76#define TG3_DEF_RX_MODE 0 76#define TG3_DEF_RX_MODE 0
@@ -4485,9 +4485,8 @@ static void tg3_disable_nvram_access(struct tg3 *tp)
4485/* tp->lock is held. */ 4485/* tp->lock is held. */
4486static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) 4486static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4487{ 4487{
4488 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) 4488 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4489 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX, 4489 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4490 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4491 4490
4492 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) { 4491 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4493 switch (kind) { 4492 switch (kind) {
@@ -4568,13 +4567,12 @@ static int tg3_chip_reset(struct tg3 *tp)
4568 void (*write_op)(struct tg3 *, u32, u32); 4567 void (*write_op)(struct tg3 *, u32, u32);
4569 int i; 4568 int i;
4570 4569
4571 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) { 4570 tg3_nvram_lock(tp);
4572 tg3_nvram_lock(tp); 4571
4573 /* No matching tg3_nvram_unlock() after this because 4572 /* No matching tg3_nvram_unlock() after this because
4574 * chip reset below will undo the nvram lock. 4573 * chip reset below will undo the nvram lock.
4575 */ 4574 */
4576 tp->nvram_lock_cnt = 0; 4575 tp->nvram_lock_cnt = 0;
4577 }
4578 4576
4579 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || 4577 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4580 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || 4578 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
@@ -4727,20 +4725,25 @@ static int tg3_chip_reset(struct tg3 *tp)
4727 tw32_f(MAC_MODE, 0); 4725 tw32_f(MAC_MODE, 0);
4728 udelay(40); 4726 udelay(40);
4729 4727
4730 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) { 4728 /* Wait for firmware initialization to complete. */
4731 /* Wait for firmware initialization to complete. */ 4729 for (i = 0; i < 100000; i++) {
4732 for (i = 0; i < 100000; i++) { 4730 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4733 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); 4731 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4734 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) 4732 break;
4735 break; 4733 udelay(10);
4736 udelay(10); 4734 }
4737 } 4735
4738 if (i >= 100000) { 4736 /* Chip might not be fitted with firmare. Some Sun onboard
4739 printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, " 4737 * parts are configured like that. So don't signal the timeout
4740 "firmware will not restart magic=%08x\n", 4738 * of the above loop as an error, but do report the lack of
4741 tp->dev->name, val); 4739 * running firmware once.
4742 return -ENODEV; 4740 */
4743 } 4741 if (i >= 100000 &&
4742 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4743 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4744
4745 printk(KERN_INFO PFX "%s: No firmware running.\n",
4746 tp->dev->name);
4744 } 4747 }
4745 4748
4746 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && 4749 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
@@ -9075,9 +9078,6 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
9075{ 9078{
9076 int j; 9079 int j;
9077 9080
9078 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
9079 return;
9080
9081 tw32_f(GRC_EEPROM_ADDR, 9081 tw32_f(GRC_EEPROM_ADDR,
9082 (EEPROM_ADDR_FSM_RESET | 9082 (EEPROM_ADDR_FSM_RESET |
9083 (EEPROM_DEFAULT_CLOCK_PERIOD << 9083 (EEPROM_DEFAULT_CLOCK_PERIOD <<
@@ -9210,11 +9210,6 @@ static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9210{ 9210{
9211 int ret; 9211 int ret;
9212 9212
9213 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
9214 printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 570X\n");
9215 return -EINVAL;
9216 }
9217
9218 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) 9213 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9219 return tg3_nvram_read_using_eeprom(tp, offset, val); 9214 return tg3_nvram_read_using_eeprom(tp, offset, val);
9220 9215
@@ -9447,11 +9442,6 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9447{ 9442{
9448 int ret; 9443 int ret;
9449 9444
9450 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
9451 printk(KERN_ERR PFX "Attempt to do nvram_write on Sun 570X\n");
9452 return -EINVAL;
9453 }
9454
9455 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { 9445 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9456 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & 9446 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9457 ~GRC_LCLCTRL_GPIO_OUTPUT1); 9447 ~GRC_LCLCTRL_GPIO_OUTPUT1);
@@ -9578,15 +9568,19 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9578 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, 9568 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9579 tp->misc_host_ctrl); 9569 tp->misc_host_ctrl);
9580 9570
9571 /* The memory arbiter has to be enabled in order for SRAM accesses
9572 * to succeed. Normally on powerup the tg3 chip firmware will make
9573 * sure it is enabled, but other entities such as system netboot
9574 * code might disable it.
9575 */
9576 val = tr32(MEMARB_MODE);
9577 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9578
9581 tp->phy_id = PHY_ID_INVALID; 9579 tp->phy_id = PHY_ID_INVALID;
9582 tp->led_ctrl = LED_CTRL_MODE_PHY_1; 9580 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9583 9581
9584 /* Do not even try poking around in here on Sun parts. */ 9582 /* Assume an onboard device by default. */
9585 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) { 9583 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9586 /* All SUN chips are built-in LOMs. */
9587 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9588 return;
9589 }
9590 9584
9591 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); 9585 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9592 if (val == NIC_SRAM_DATA_SIG_MAGIC) { 9586 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
@@ -9686,6 +9680,8 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9686 9680
9687 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) 9681 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP)
9688 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT; 9682 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9683 else
9684 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9689 9685
9690 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { 9686 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
9691 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; 9687 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
@@ -9834,16 +9830,8 @@ static void __devinit tg3_read_partno(struct tg3 *tp)
9834 int i; 9830 int i;
9835 u32 magic; 9831 u32 magic;
9836 9832
9837 if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
9838 /* Sun decided not to put the necessary bits in the
9839 * NVRAM of their onboard tg3 parts :(
9840 */
9841 strcpy(tp->board_part_number, "Sun 570X");
9842 return;
9843 }
9844
9845 if (tg3_nvram_read_swab(tp, 0x0, &magic)) 9833 if (tg3_nvram_read_swab(tp, 0x0, &magic))
9846 return; 9834 goto out_not_found;
9847 9835
9848 if (magic == TG3_EEPROM_MAGIC) { 9836 if (magic == TG3_EEPROM_MAGIC) {
9849 for (i = 0; i < 256; i += 4) { 9837 for (i = 0; i < 256; i += 4) {
@@ -9874,6 +9862,9 @@ static void __devinit tg3_read_partno(struct tg3 *tp)
9874 break; 9862 break;
9875 msleep(1); 9863 msleep(1);
9876 } 9864 }
9865 if (!(tmp16 & 0x8000))
9866 goto out_not_found;
9867
9877 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA, 9868 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
9878 &tmp); 9869 &tmp);
9879 tmp = cpu_to_le32(tmp); 9870 tmp = cpu_to_le32(tmp);
@@ -9965,37 +9956,6 @@ static void __devinit tg3_read_fw_ver(struct tg3 *tp)
9965 } 9956 }
9966} 9957}
9967 9958
9968#ifdef CONFIG_SPARC64
9969static int __devinit tg3_is_sun_570X(struct tg3 *tp)
9970{
9971 struct pci_dev *pdev = tp->pdev;
9972 struct pcidev_cookie *pcp = pdev->sysdata;
9973
9974 if (pcp != NULL) {
9975 int node = pcp->prom_node;
9976 u32 venid;
9977 int err;
9978
9979 err = prom_getproperty(node, "subsystem-vendor-id",
9980 (char *) &venid, sizeof(venid));
9981 if (err == 0 || err == -1)
9982 return 0;
9983 if (venid == PCI_VENDOR_ID_SUN)
9984 return 1;
9985
9986 /* TG3 chips onboard the SunBlade-2500 don't have the
9987 * subsystem-vendor-id set to PCI_VENDOR_ID_SUN but they
9988 * are distinguishable from non-Sun variants by being
9989 * named "network" by the firmware. Non-Sun cards will
9990 * show up as being named "ethernet".
9991 */
9992 if (!strcmp(pcp->prom_name, "network"))
9993 return 1;
9994 }
9995 return 0;
9996}
9997#endif
9998
9999static int __devinit tg3_get_invariants(struct tg3 *tp) 9959static int __devinit tg3_get_invariants(struct tg3 *tp)
10000{ 9960{
10001 static struct pci_device_id write_reorder_chipsets[] = { 9961 static struct pci_device_id write_reorder_chipsets[] = {
@@ -10012,11 +9972,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
10012 u16 pci_cmd; 9972 u16 pci_cmd;
10013 int err; 9973 int err;
10014 9974
10015#ifdef CONFIG_SPARC64
10016 if (tg3_is_sun_570X(tp))
10017 tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
10018#endif
10019
10020 /* Force memory write invalidate off. If we leave it on, 9975 /* Force memory write invalidate off. If we leave it on,
10021 * then on 5700_BX chips we have to enable a workaround. 9976 * then on 5700_BX chips we have to enable a workaround.
10022 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary 9977 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
@@ -10312,8 +10267,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
10312 if (tp->write32 == tg3_write_indirect_reg32 || 10267 if (tp->write32 == tg3_write_indirect_reg32 ||
10313 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) && 10268 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10314 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || 10269 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10315 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) || 10270 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
10316 (tp->tg3_flags2 & TG3_FLG2_SUN_570X))
10317 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG; 10271 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10318 10272
10319 /* Get eeprom hw config before calling tg3_set_power_state(). 10273 /* Get eeprom hw config before calling tg3_set_power_state().
@@ -10594,8 +10548,7 @@ static int __devinit tg3_get_device_address(struct tg3 *tp)
10594#endif 10548#endif
10595 10549
10596 mac_offset = 0x7c; 10550 mac_offset = 0x7c;
10597 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && 10551 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
10598 !(tp->tg3_flags & TG3_FLG2_SUN_570X)) ||
10599 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { 10552 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10600 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) 10553 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
10601 mac_offset = 0xcc; 10554 mac_offset = 0xcc;
@@ -10622,8 +10575,7 @@ static int __devinit tg3_get_device_address(struct tg3 *tp)
10622 } 10575 }
10623 if (!addr_ok) { 10576 if (!addr_ok) {
10624 /* Next, try NVRAM. */ 10577 /* Next, try NVRAM. */
10625 if (!(tp->tg3_flags & TG3_FLG2_SUN_570X) && 10578 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
10626 !tg3_nvram_read(tp, mac_offset + 0, &hi) &&
10627 !tg3_nvram_read(tp, mac_offset + 4, &lo)) { 10579 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
10628 dev->dev_addr[0] = ((hi >> 16) & 0xff); 10580 dev->dev_addr[0] = ((hi >> 16) & 0xff);
10629 dev->dev_addr[1] = ((hi >> 24) & 0xff); 10581 dev->dev_addr[1] = ((hi >> 24) & 0xff);
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 0e29b885d449..ff0faab94bd5 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2184,7 +2184,7 @@ struct tg3 {
2184#define TG3_FLAG_INIT_COMPLETE 0x80000000 2184#define TG3_FLAG_INIT_COMPLETE 0x80000000
2185 u32 tg3_flags2; 2185 u32 tg3_flags2;
2186#define TG3_FLG2_RESTART_TIMER 0x00000001 2186#define TG3_FLG2_RESTART_TIMER 0x00000001
2187#define TG3_FLG2_SUN_570X 0x00000002 2187/* 0x00000002 available */
2188#define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004 2188#define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004
2189#define TG3_FLG2_IS_5788 0x00000008 2189#define TG3_FLG2_IS_5788 0x00000008
2190#define TG3_FLG2_MAX_RXPEND_64 0x00000010 2190#define TG3_FLG2_MAX_RXPEND_64 0x00000010
@@ -2216,6 +2216,7 @@ struct tg3 {
2216#define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2) 2216#define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2)
2217#define TG3_FLG2_1SHOT_MSI 0x10000000 2217#define TG3_FLG2_1SHOT_MSI 0x10000000
2218#define TG3_FLG2_PHY_JITTER_BUG 0x20000000 2218#define TG3_FLG2_PHY_JITTER_BUG 0x20000000
2219#define TG3_FLG2_NO_FWARE_REPORTED 0x40000000
2219 2220
2220 u32 split_mode_max_reqs; 2221 u32 split_mode_max_reqs;
2221#define SPLIT_MODE_5704_MAX_REQ 3 2222#define SPLIT_MODE_5704_MAX_REQ 3