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authorMichael Chan <mchan@broadcom.com>2005-04-25 18:14:03 -0400
committerDavid S. Miller <davem@davemloft.net>2005-04-25 18:14:03 -0400
commit483ba50bd41d14d5325d6cd9935de86a982d08a2 (patch)
tree885f84a0fe56ed5e3d793a5414c8ec5bb6c8a633 /drivers/net
parentcbdbf00aaf0addd391259f94aaa8e7dc1bfc9081 (diff)
[TG3]: Fix bug in tg3_rx()
This patch fixes a bug that causes tg3_has_work() to always return 1. rx work is determined by comparing tp->rx_rcb_ptr with the current hw producer index. The hw producer index is modulo the ring size, but tp- >rx_rcb_ptr is a free running counter that goes up beyond the ring size. After the ring wraps around once, tg3_has_work() will always return 1. The fix is to always do modulo arithmetic on tp->rx_rcb_ptr. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/tg3.c14
1 files changed, 6 insertions, 8 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 10d476153ee0..e53c1dc58d08 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -2686,8 +2686,8 @@ static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
2686static int tg3_rx(struct tg3 *tp, int budget) 2686static int tg3_rx(struct tg3 *tp, int budget)
2687{ 2687{
2688 u32 work_mask; 2688 u32 work_mask;
2689 u32 rx_rcb_ptr = tp->rx_rcb_ptr; 2689 u32 sw_idx = tp->rx_rcb_ptr;
2690 u16 hw_idx, sw_idx; 2690 u16 hw_idx;
2691 int received; 2691 int received;
2692 2692
2693 hw_idx = tp->hw_status->idx[0].rx_producer; 2693 hw_idx = tp->hw_status->idx[0].rx_producer;
@@ -2696,7 +2696,6 @@ static int tg3_rx(struct tg3 *tp, int budget)
2696 * the opaque cookie. 2696 * the opaque cookie.
2697 */ 2697 */
2698 rmb(); 2698 rmb();
2699 sw_idx = rx_rcb_ptr % TG3_RX_RCB_RING_SIZE(tp);
2700 work_mask = 0; 2699 work_mask = 0;
2701 received = 0; 2700 received = 0;
2702 while (sw_idx != hw_idx && budget > 0) { 2701 while (sw_idx != hw_idx && budget > 0) {
@@ -2801,14 +2800,13 @@ static int tg3_rx(struct tg3 *tp, int budget)
2801next_pkt: 2800next_pkt:
2802 (*post_ptr)++; 2801 (*post_ptr)++;
2803next_pkt_nopost: 2802next_pkt_nopost:
2804 rx_rcb_ptr++; 2803 sw_idx++;
2805 sw_idx = rx_rcb_ptr % TG3_RX_RCB_RING_SIZE(tp); 2804 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
2806 } 2805 }
2807 2806
2808 /* ACK the status ring. */ 2807 /* ACK the status ring. */
2809 tp->rx_rcb_ptr = rx_rcb_ptr; 2808 tp->rx_rcb_ptr = sw_idx;
2810 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 2809 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
2811 (rx_rcb_ptr % TG3_RX_RCB_RING_SIZE(tp)));
2812 2810
2813 /* Refill RX ring(s). */ 2811 /* Refill RX ring(s). */
2814 if (work_mask & RXD_OPAQUE_RING_STD) { 2812 if (work_mask & RXD_OPAQUE_RING_STD) {