aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net
diff options
context:
space:
mode:
authorDhananjay Phadke <dhananjay@netxen.com>2009-04-07 18:50:45 -0400
committerDavid S. Miller <davem@davemloft.net>2009-04-08 18:58:29 -0400
commitf98a9f693b5f4919d9c4085a2fd8d67c7e152f3e (patch)
treeef0acb778f9bdb7fed66de7f099f772ef7af1175 /drivers/net
parent1fbe63235893e5dce28fe91d8465dd231b0cb3d9 (diff)
netxen: sanitize function names
Replace superfluous wrapper functions with two macros: NXWR32 replaces netxen_nic_reg_write, netxen_nic_write_w0, netxen_nic_read_w1, netxen_crb_writelit_adapter. NXRD32 replaces netxen_nic_reg_read, netxen_nic_read_w0, netxen_nic_read_w1. Signed-off-by: Dhananjay Phadke <dhananjay@netxen.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/netxen/netxen_nic.h19
-rw-r--r--drivers/net/netxen/netxen_nic_ctx.c29
-rw-r--r--drivers/net/netxen/netxen_nic_ethtool.c59
-rw-r--r--drivers/net/netxen/netxen_nic_hw.c187
-rw-r--r--drivers/net/netxen/netxen_nic_init.c93
-rw-r--r--drivers/net/netxen/netxen_nic_main.c83
-rw-r--r--drivers/net/netxen/netxen_nic_niu.c169
7 files changed, 233 insertions, 406 deletions
diff --git a/drivers/net/netxen/netxen_nic.h b/drivers/net/netxen/netxen_nic.h
index 1e4190dd0c16..f13fd0282f55 100644
--- a/drivers/net/netxen/netxen_nic.h
+++ b/drivers/net/netxen/netxen_nic.h
@@ -1312,12 +1312,11 @@ int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
1312/* Functions available from netxen_nic_hw.c */ 1312/* Functions available from netxen_nic_hw.c */
1313int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu); 1313int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
1314int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu); 1314int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
1315void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val); 1315
1316int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off); 1316#define NXRD32(adapter, off) \
1317void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value); 1317 (adapter->hw_read_wx(adapter, off))
1318u32 netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index); 1318#define NXWR32(adapter, off, val) \
1319void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value); 1319 (adapter->hw_write_wx(adapter, off, val))
1320u32 netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index);
1321 1320
1322int netxen_nic_get_board_info(struct netxen_adapter *adapter); 1321int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1323void netxen_nic_get_firmware_info(struct netxen_adapter *adapter); 1322void netxen_nic_get_firmware_info(struct netxen_adapter *adapter);
@@ -1348,8 +1347,6 @@ int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1348 u64 off, void *data, int size); 1347 u64 off, void *data, int size);
1349int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter, 1348int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1350 u64 off, void *data, int size); 1349 u64 off, void *data, int size);
1351void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
1352 unsigned long off, int data);
1353int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter, 1350int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1354 u64 off, u32 data); 1351 u64 off, u32 data);
1355u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off); 1352u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off);
@@ -1478,8 +1475,7 @@ dma_watchdog_shutdown_request(struct netxen_adapter *adapter)
1478 1475
1479 /* Send the disable request */ 1476 /* Send the disable request */
1480 netxen_set_dma_watchdog_disable_req(ctrl); 1477 netxen_set_dma_watchdog_disable_req(ctrl);
1481 netxen_crb_writelit_adapter(adapter, 1478 NXWR32(adapter, NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1482 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1483 1479
1484 return 0; 1480 return 0;
1485} 1481}
@@ -1509,8 +1505,7 @@ dma_watchdog_wakeup(struct netxen_adapter *adapter)
1509 /* send the wakeup request */ 1505 /* send the wakeup request */
1510 netxen_set_dma_watchdog_enable_req(ctrl); 1506 netxen_set_dma_watchdog_enable_req(ctrl);
1511 1507
1512 netxen_crb_writelit_adapter(adapter, 1508 NXWR32(adapter, NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1513 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1514 1509
1515 return 0; 1510 return 0;
1516} 1511}
diff --git a/drivers/net/netxen/netxen_nic_ctx.c b/drivers/net/netxen/netxen_nic_ctx.c
index 7a13ee8144ee..32f48398398b 100644
--- a/drivers/net/netxen/netxen_nic_ctx.c
+++ b/drivers/net/netxen/netxen_nic_ctx.c
@@ -41,8 +41,7 @@ netxen_api_lock(struct netxen_adapter *adapter)
41 41
42 for (;;) { 42 for (;;) {
43 /* Acquire PCIE HW semaphore5 */ 43 /* Acquire PCIE HW semaphore5 */
44 done = netxen_nic_read_w0(adapter, 44 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM5_LOCK));
45 NETXEN_PCIE_REG(PCIE_SEM5_LOCK));
46 45
47 if (done == 1) 46 if (done == 1)
48 break; 47 break;
@@ -56,7 +55,7 @@ netxen_api_lock(struct netxen_adapter *adapter)
56 } 55 }
57 56
58#if 0 57#if 0
59 netxen_nic_write_w1(adapter, 58 NXWR32(adapter,
60 NETXEN_API_LOCK_ID, NX_OS_API_LOCK_DRIVER); 59 NETXEN_API_LOCK_ID, NX_OS_API_LOCK_DRIVER);
61#endif 60#endif
62 return 0; 61 return 0;
@@ -66,8 +65,7 @@ static int
66netxen_api_unlock(struct netxen_adapter *adapter) 65netxen_api_unlock(struct netxen_adapter *adapter)
67{ 66{
68 /* Release PCIE HW semaphore5 */ 67 /* Release PCIE HW semaphore5 */
69 netxen_nic_read_w0(adapter, 68 NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM5_UNLOCK));
70 NETXEN_PCIE_REG(PCIE_SEM5_UNLOCK));
71 return 0; 69 return 0;
72} 70}
73 71
@@ -84,7 +82,7 @@ netxen_poll_rsp(struct netxen_adapter *adapter)
84 if (++timeout > NX_OS_CRB_RETRY_COUNT) 82 if (++timeout > NX_OS_CRB_RETRY_COUNT)
85 return NX_CDRP_RSP_TIMEOUT; 83 return NX_CDRP_RSP_TIMEOUT;
86 84
87 rsp = netxen_nic_read_w1(adapter, NX_CDRP_CRB_OFFSET); 85 rsp = NXRD32(adapter, NX_CDRP_CRB_OFFSET);
88 } while (!NX_CDRP_IS_RSP(rsp)); 86 } while (!NX_CDRP_IS_RSP(rsp));
89 87
90 return rsp; 88 return rsp;
@@ -104,16 +102,15 @@ netxen_issue_cmd(struct netxen_adapter *adapter,
104 if (netxen_api_lock(adapter)) 102 if (netxen_api_lock(adapter))
105 return NX_RCODE_TIMEOUT; 103 return NX_RCODE_TIMEOUT;
106 104
107 netxen_nic_write_w1(adapter, NX_SIGN_CRB_OFFSET, signature); 105 NXWR32(adapter, NX_SIGN_CRB_OFFSET, signature);
108 106
109 netxen_nic_write_w1(adapter, NX_ARG1_CRB_OFFSET, arg1); 107 NXWR32(adapter, NX_ARG1_CRB_OFFSET, arg1);
110 108
111 netxen_nic_write_w1(adapter, NX_ARG2_CRB_OFFSET, arg2); 109 NXWR32(adapter, NX_ARG2_CRB_OFFSET, arg2);
112 110
113 netxen_nic_write_w1(adapter, NX_ARG3_CRB_OFFSET, arg3); 111 NXWR32(adapter, NX_ARG3_CRB_OFFSET, arg3);
114 112
115 netxen_nic_write_w1(adapter, NX_CDRP_CRB_OFFSET, 113 NXWR32(adapter, NX_CDRP_CRB_OFFSET, NX_CDRP_FORM_CMD(cmd));
116 NX_CDRP_FORM_CMD(cmd));
117 114
118 rsp = netxen_poll_rsp(adapter); 115 rsp = netxen_poll_rsp(adapter);
119 116
@@ -123,7 +120,7 @@ netxen_issue_cmd(struct netxen_adapter *adapter,
123 120
124 rcode = NX_RCODE_TIMEOUT; 121 rcode = NX_RCODE_TIMEOUT;
125 } else if (rsp == NX_CDRP_RSP_FAIL) { 122 } else if (rsp == NX_CDRP_RSP_FAIL) {
126 rcode = netxen_nic_read_w1(adapter, NX_ARG1_CRB_OFFSET); 123 rcode = NXRD32(adapter, NX_ARG1_CRB_OFFSET);
127 124
128 printk(KERN_ERR "%s: failed card response code:0x%x\n", 125 printk(KERN_ERR "%s: failed card response code:0x%x\n",
129 netxen_nic_driver_name, rcode); 126 netxen_nic_driver_name, rcode);
@@ -515,11 +512,11 @@ netxen_init_old_ctx(struct netxen_adapter *adapter)
515 adapter->ctx_desc->sts_ring_addr = cpu_to_le64(sds_ring->phys_addr); 512 adapter->ctx_desc->sts_ring_addr = cpu_to_le64(sds_ring->phys_addr);
516 adapter->ctx_desc->sts_ring_size = cpu_to_le32(sds_ring->num_desc); 513 adapter->ctx_desc->sts_ring_size = cpu_to_le32(sds_ring->num_desc);
517 514
518 adapter->hw_write_wx(adapter, CRB_CTX_ADDR_REG_LO(func_id), 515 NXWR32(adapter, CRB_CTX_ADDR_REG_LO(func_id),
519 lower32(adapter->ctx_desc_phys_addr)); 516 lower32(adapter->ctx_desc_phys_addr));
520 adapter->hw_write_wx(adapter, CRB_CTX_ADDR_REG_HI(func_id), 517 NXWR32(adapter, CRB_CTX_ADDR_REG_HI(func_id),
521 upper32(adapter->ctx_desc_phys_addr)); 518 upper32(adapter->ctx_desc_phys_addr));
522 adapter->hw_write_wx(adapter, CRB_CTX_SIGNATURE_REG(func_id), 519 NXWR32(adapter, CRB_CTX_SIGNATURE_REG(func_id),
523 NETXEN_CTX_SIGNATURE | func_id); 520 NETXEN_CTX_SIGNATURE | func_id);
524 return 0; 521 return 0;
525} 522}
diff --git a/drivers/net/netxen/netxen_nic_ethtool.c b/drivers/net/netxen/netxen_nic_ethtool.c
index 6c5a111e80bf..a452b2facb77 100644
--- a/drivers/net/netxen/netxen_nic_ethtool.c
+++ b/drivers/net/netxen/netxen_nic_ethtool.c
@@ -92,12 +92,9 @@ netxen_nic_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo)
92 strncpy(drvinfo->driver, netxen_nic_driver_name, 32); 92 strncpy(drvinfo->driver, netxen_nic_driver_name, 32);
93 strncpy(drvinfo->version, NETXEN_NIC_LINUX_VERSIONID, 32); 93 strncpy(drvinfo->version, NETXEN_NIC_LINUX_VERSIONID, 32);
94 write_lock_irqsave(&adapter->adapter_lock, flags); 94 write_lock_irqsave(&adapter->adapter_lock, flags);
95 fw_major = adapter->hw_read_wx(adapter, 95 fw_major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
96 NETXEN_FW_VERSION_MAJOR); 96 fw_minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
97 fw_minor = adapter->hw_read_wx(adapter, 97 fw_build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
98 NETXEN_FW_VERSION_MINOR);
99 fw_build = adapter->hw_read_wx(adapter,
100 NETXEN_FW_VERSION_SUB);
101 write_unlock_irqrestore(&adapter->adapter_lock, flags); 98 write_unlock_irqrestore(&adapter->adapter_lock, flags);
102 sprintf(drvinfo->fw_version, "%d.%d.%d", fw_major, fw_minor, fw_build); 99 sprintf(drvinfo->fw_version, "%d.%d.%d", fw_major, fw_minor, fw_build);
103 100
@@ -135,7 +132,7 @@ netxen_nic_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
135 } else if (adapter->ahw.port_type == NETXEN_NIC_XGBE) { 132 } else if (adapter->ahw.port_type == NETXEN_NIC_XGBE) {
136 u32 val; 133 u32 val;
137 134
138 val = adapter->hw_read_wx(adapter, NETXEN_PORT_MODE_ADDR); 135 val = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
139 if (val == NETXEN_PORT_MODE_802_3_AP) { 136 if (val == NETXEN_PORT_MODE_802_3_AP) {
140 ecmd->supported = SUPPORTED_1000baseT_Full; 137 ecmd->supported = SUPPORTED_1000baseT_Full;
141 ecmd->advertising = ADVERTISED_1000baseT_Full; 138 ecmd->advertising = ADVERTISED_1000baseT_Full;
@@ -156,8 +153,7 @@ netxen_nic_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
156 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { 153 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
157 u16 pcifn = adapter->ahw.pci_func; 154 u16 pcifn = adapter->ahw.pci_func;
158 155
159 val = adapter->hw_read_wx(adapter, 156 val = NXRD32(adapter, P3_LINK_SPEED_REG(pcifn));
160 P3_LINK_SPEED_REG(pcifn));
161 ecmd->speed = P3_LINK_SPEED_MHZ * 157 ecmd->speed = P3_LINK_SPEED_MHZ *
162 P3_LINK_SPEED_VAL(pcifn, val); 158 P3_LINK_SPEED_VAL(pcifn, val);
163 } else 159 } else
@@ -423,12 +419,11 @@ netxen_nic_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *p)
423 regs->version = (1 << 24) | (adapter->ahw.revision_id << 16) | 419 regs->version = (1 << 24) | (adapter->ahw.revision_id << 16) |
424 (adapter->pdev)->device; 420 (adapter->pdev)->device;
425 /* which mode */ 421 /* which mode */
426 regs_buff[0] = adapter->hw_read_wx(adapter, NETXEN_NIU_MODE); 422 regs_buff[0] = NXRD32(adapter, NETXEN_NIU_MODE);
427 mode = regs_buff[0]; 423 mode = regs_buff[0];
428 424
429 /* Common registers to all the modes */ 425 /* Common registers to all the modes */
430 regs_buff[2] = adapter->hw_read_wx(adapter, 426 regs_buff[2] = NXRD32(adapter, NETXEN_NIU_STRAP_VALUE_SAVE_HIGHER);
431 NETXEN_NIU_STRAP_VALUE_SAVE_HIGHER);
432 /* GB/XGB Mode */ 427 /* GB/XGB Mode */
433 mode = (mode / 2) - 1; 428 mode = (mode / 2) - 1;
434 window = 0; 429 window = 0;
@@ -439,7 +434,7 @@ netxen_nic_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *p)
439 window = adapter->physical_port * 434 window = adapter->physical_port *
440 NETXEN_NIC_PORT_WINDOW; 435 NETXEN_NIC_PORT_WINDOW;
441 436
442 regs_buff[i] = adapter->hw_read_wx(adapter, 437 regs_buff[i] = NXRD32(adapter,
443 niu_registers[mode].reg[i - 3] + window); 438 niu_registers[mode].reg[i - 3] + window);
444 } 439 }
445 440
@@ -464,7 +459,7 @@ static u32 netxen_nic_test_link(struct net_device *dev)
464 return !val; 459 return !val;
465 } 460 }
466 } else if (adapter->ahw.port_type == NETXEN_NIC_XGBE) { 461 } else if (adapter->ahw.port_type == NETXEN_NIC_XGBE) {
467 val = adapter->hw_read_wx(adapter, CRB_XG_STATE); 462 val = NXRD32(adapter, CRB_XG_STATE);
468 return (val == XG_LINK_UP) ? 0 : 1; 463 return (val == XG_LINK_UP) ? 0 : 1;
469 } 464 }
470 return -EIO; 465 return -EIO;
@@ -528,10 +523,9 @@ netxen_nic_get_pauseparam(struct net_device *dev,
528 if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS)) 523 if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
529 return; 524 return;
530 /* get flow control settings */ 525 /* get flow control settings */
531 val = netxen_nic_read_w0(adapter, 526 val = NXRD32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port));
532 NETXEN_NIU_GB_MAC_CONFIG_0(port));
533 pause->rx_pause = netxen_gb_get_rx_flowctl(val); 527 pause->rx_pause = netxen_gb_get_rx_flowctl(val);
534 val = netxen_nic_read_w0(adapter, NETXEN_NIU_GB_PAUSE_CTL); 528 val = NXRD32(adapter, NETXEN_NIU_GB_PAUSE_CTL);
535 switch (port) { 529 switch (port) {
536 case 0: 530 case 0:
537 pause->tx_pause = !(netxen_gb_get_gb0_mask(val)); 531 pause->tx_pause = !(netxen_gb_get_gb0_mask(val));
@@ -551,7 +545,7 @@ netxen_nic_get_pauseparam(struct net_device *dev,
551 if ((port < 0) || (port > NETXEN_NIU_MAX_XG_PORTS)) 545 if ((port < 0) || (port > NETXEN_NIU_MAX_XG_PORTS))
552 return; 546 return;
553 pause->rx_pause = 1; 547 pause->rx_pause = 1;
554 val = netxen_nic_read_w0(adapter, NETXEN_NIU_XG_PAUSE_CTL); 548 val = NXRD32(adapter, NETXEN_NIU_XG_PAUSE_CTL);
555 if (port == 0) 549 if (port == 0)
556 pause->tx_pause = !(netxen_xg_get_xg0_mask(val)); 550 pause->tx_pause = !(netxen_xg_get_xg0_mask(val));
557 else 551 else
@@ -574,18 +568,17 @@ netxen_nic_set_pauseparam(struct net_device *dev,
574 if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS)) 568 if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
575 return -EIO; 569 return -EIO;
576 /* set flow control */ 570 /* set flow control */
577 val = netxen_nic_read_w0(adapter, 571 val = NXRD32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port));
578 NETXEN_NIU_GB_MAC_CONFIG_0(port));
579 572
580 if (pause->rx_pause) 573 if (pause->rx_pause)
581 netxen_gb_rx_flowctl(val); 574 netxen_gb_rx_flowctl(val);
582 else 575 else
583 netxen_gb_unset_rx_flowctl(val); 576 netxen_gb_unset_rx_flowctl(val);
584 577
585 netxen_nic_write_w0(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 578 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
586 val); 579 val);
587 /* set autoneg */ 580 /* set autoneg */
588 val = netxen_nic_read_w0(adapter, NETXEN_NIU_GB_PAUSE_CTL); 581 val = NXRD32(adapter, NETXEN_NIU_GB_PAUSE_CTL);
589 switch (port) { 582 switch (port) {
590 case 0: 583 case 0:
591 if (pause->tx_pause) 584 if (pause->tx_pause)
@@ -613,11 +606,11 @@ netxen_nic_set_pauseparam(struct net_device *dev,
613 netxen_gb_set_gb3_mask(val); 606 netxen_gb_set_gb3_mask(val);
614 break; 607 break;
615 } 608 }
616 netxen_nic_write_w0(adapter, NETXEN_NIU_GB_PAUSE_CTL, val); 609 NXWR32(adapter, NETXEN_NIU_GB_PAUSE_CTL, val);
617 } else if (adapter->ahw.port_type == NETXEN_NIC_XGBE) { 610 } else if (adapter->ahw.port_type == NETXEN_NIC_XGBE) {
618 if ((port < 0) || (port > NETXEN_NIU_MAX_XG_PORTS)) 611 if ((port < 0) || (port > NETXEN_NIU_MAX_XG_PORTS))
619 return -EIO; 612 return -EIO;
620 val = netxen_nic_read_w0(adapter, NETXEN_NIU_XG_PAUSE_CTL); 613 val = NXRD32(adapter, NETXEN_NIU_XG_PAUSE_CTL);
621 if (port == 0) { 614 if (port == 0) {
622 if (pause->tx_pause) 615 if (pause->tx_pause)
623 netxen_xg_unset_xg0_mask(val); 616 netxen_xg_unset_xg0_mask(val);
@@ -629,7 +622,7 @@ netxen_nic_set_pauseparam(struct net_device *dev,
629 else 622 else
630 netxen_xg_set_xg1_mask(val); 623 netxen_xg_set_xg1_mask(val);
631 } 624 }
632 netxen_nic_write_w0(adapter, NETXEN_NIU_XG_PAUSE_CTL, val); 625 NXWR32(adapter, NETXEN_NIU_XG_PAUSE_CTL, val);
633 } else { 626 } else {
634 printk(KERN_ERR "%s: Unknown board type: %x\n", 627 printk(KERN_ERR "%s: Unknown board type: %x\n",
635 netxen_nic_driver_name, 628 netxen_nic_driver_name,
@@ -643,14 +636,14 @@ static int netxen_nic_reg_test(struct net_device *dev)
643 struct netxen_adapter *adapter = netdev_priv(dev); 636 struct netxen_adapter *adapter = netdev_priv(dev);
644 u32 data_read, data_written; 637 u32 data_read, data_written;
645 638
646 data_read = netxen_nic_read_w0(adapter, NETXEN_PCIX_PH_REG(0)); 639 data_read = NXRD32(adapter, NETXEN_PCIX_PH_REG(0));
647 if ((data_read & 0xffff) != PHAN_VENDOR_ID) 640 if ((data_read & 0xffff) != PHAN_VENDOR_ID)
648 return 1; 641 return 1;
649 642
650 data_written = (u32)0xa5a5a5a5; 643 data_written = (u32)0xa5a5a5a5;
651 644
652 netxen_nic_reg_write(adapter, CRB_SCRATCHPAD_TEST, data_written); 645 NXWR32(adapter, CRB_SCRATCHPAD_TEST, data_written);
653 data_read = adapter->hw_read_wx(adapter, CRB_SCRATCHPAD_TEST); 646 data_read = NXRD32(adapter, CRB_SCRATCHPAD_TEST);
654 if (data_written != data_read) 647 if (data_written != data_read)
655 return 1; 648 return 1;
656 649
@@ -767,11 +760,11 @@ netxen_nic_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
767 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) 760 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
768 return; 761 return;
769 762
770 wol_cfg = netxen_nic_reg_read(adapter, NETXEN_WOL_CONFIG_NV); 763 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
771 if (wol_cfg & (1UL << adapter->portnum)) 764 if (wol_cfg & (1UL << adapter->portnum))
772 wol->supported |= WAKE_MAGIC; 765 wol->supported |= WAKE_MAGIC;
773 766
774 wol_cfg = netxen_nic_reg_read(adapter, NETXEN_WOL_CONFIG); 767 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
775 if (wol_cfg & (1UL << adapter->portnum)) 768 if (wol_cfg & (1UL << adapter->portnum))
776 wol->wolopts |= WAKE_MAGIC; 769 wol->wolopts |= WAKE_MAGIC;
777} 770}
@@ -788,16 +781,16 @@ netxen_nic_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
788 if (wol->wolopts & ~WAKE_MAGIC) 781 if (wol->wolopts & ~WAKE_MAGIC)
789 return -EOPNOTSUPP; 782 return -EOPNOTSUPP;
790 783
791 wol_cfg = netxen_nic_reg_read(adapter, NETXEN_WOL_CONFIG_NV); 784 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
792 if (!(wol_cfg & (1 << adapter->portnum))) 785 if (!(wol_cfg & (1 << adapter->portnum)))
793 return -EOPNOTSUPP; 786 return -EOPNOTSUPP;
794 787
795 wol_cfg = netxen_nic_reg_read(adapter, NETXEN_WOL_CONFIG); 788 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
796 if (wol->wolopts & WAKE_MAGIC) 789 if (wol->wolopts & WAKE_MAGIC)
797 wol_cfg |= 1UL << adapter->portnum; 790 wol_cfg |= 1UL << adapter->portnum;
798 else 791 else
799 wol_cfg &= ~(1UL << adapter->portnum); 792 wol_cfg &= ~(1UL << adapter->portnum);
800 netxen_nic_reg_write(adapter, NETXEN_WOL_CONFIG, wol_cfg); 793 NXWR32(adapter, NETXEN_WOL_CONFIG, wol_cfg);
801 794
802 return 0; 795 return 0;
803} 796}
diff --git a/drivers/net/netxen/netxen_nic_hw.c b/drivers/net/netxen/netxen_nic_hw.c
index 87cda65ef66b..9439f89869de 100644
--- a/drivers/net/netxen/netxen_nic_hw.c
+++ b/drivers/net/netxen/netxen_nic_hw.c
@@ -361,22 +361,20 @@ netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
361 if (adapter->mc_enabled) 361 if (adapter->mc_enabled)
362 return 0; 362 return 0;
363 363
364 val = adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG); 364 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
365 val |= (1UL << (28+port)); 365 val |= (1UL << (28+port));
366 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, val); 366 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
367 367
368 /* add broadcast addr to filter */ 368 /* add broadcast addr to filter */
369 val = 0xffffff; 369 val = 0xffffff;
370 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val); 370 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
371 netxen_crb_writelit_adapter(adapter, 371 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
372 NETXEN_UNICAST_ADDR(port, 0)+4, val);
373 372
374 /* add station addr to filter */ 373 /* add station addr to filter */
375 val = MAC_HI(addr); 374 val = MAC_HI(addr);
376 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), val); 375 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
377 val = MAC_LO(addr); 376 val = MAC_LO(addr);
378 netxen_crb_writelit_adapter(adapter, 377 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val);
379 NETXEN_UNICAST_ADDR(port, 1)+4, val);
380 378
381 adapter->mc_enabled = 1; 379 adapter->mc_enabled = 1;
382 return 0; 380 return 0;
@@ -392,18 +390,17 @@ netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
392 if (!adapter->mc_enabled) 390 if (!adapter->mc_enabled)
393 return 0; 391 return 0;
394 392
395 val = adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG); 393 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
396 val &= ~(1UL << (28+port)); 394 val &= ~(1UL << (28+port));
397 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, val); 395 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
398 396
399 val = MAC_HI(addr); 397 val = MAC_HI(addr);
400 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val); 398 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
401 val = MAC_LO(addr); 399 val = MAC_LO(addr);
402 netxen_crb_writelit_adapter(adapter, 400 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
403 NETXEN_UNICAST_ADDR(port, 0)+4, val);
404 401
405 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), 0); 402 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
406 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0); 403 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
407 404
408 adapter->mc_enabled = 0; 405 adapter->mc_enabled = 0;
409 return 0; 406 return 0;
@@ -419,10 +416,8 @@ netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
419 lo = MAC_LO(addr); 416 lo = MAC_LO(addr);
420 hi = MAC_HI(addr); 417 hi = MAC_HI(addr);
421 418
422 netxen_crb_writelit_adapter(adapter, 419 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi);
423 NETXEN_MCAST_ADDR(port, index), hi); 420 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo);
424 netxen_crb_writelit_adapter(adapter,
425 NETXEN_MCAST_ADDR(port, index)+4, lo);
426 421
427 return 0; 422 return 0;
428} 423}
@@ -863,8 +858,8 @@ int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
863 crbaddr = CRB_MAC_BLOCK_START + 858 crbaddr = CRB_MAC_BLOCK_START +
864 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1)); 859 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
865 860
866 mac_lo = adapter->hw_read_wx(adapter, crbaddr); 861 mac_lo = NXRD32(adapter, crbaddr);
867 mac_hi = adapter->hw_read_wx(adapter, crbaddr+4); 862 mac_hi = NXRD32(adapter, crbaddr+4);
868 863
869 if (pci_func & 1) 864 if (pci_func & 1)
870 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16)); 865 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
@@ -882,8 +877,7 @@ static int crb_win_lock(struct netxen_adapter *adapter)
882 877
883 while (!done) { 878 while (!done) {
884 /* acquire semaphore3 from PCI HW block */ 879 /* acquire semaphore3 from PCI HW block */
885 done = adapter->hw_read_wx(adapter, 880 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM7_LOCK));
886 NETXEN_PCIE_REG(PCIE_SEM7_LOCK));
887 if (done == 1) 881 if (done == 1)
888 break; 882 break;
889 if (timeout >= CRB_WIN_LOCK_TIMEOUT) 883 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
@@ -891,8 +885,7 @@ static int crb_win_lock(struct netxen_adapter *adapter)
891 timeout++; 885 timeout++;
892 udelay(1); 886 udelay(1);
893 } 887 }
894 netxen_crb_writelit_adapter(adapter, 888 NXWR32(adapter, NETXEN_CRB_WIN_LOCK_ID, adapter->portnum);
895 NETXEN_CRB_WIN_LOCK_ID, adapter->portnum);
896 return 0; 889 return 0;
897} 890}
898 891
@@ -900,8 +893,7 @@ static void crb_win_unlock(struct netxen_adapter *adapter)
900{ 893{
901 int val; 894 int val;
902 895
903 val = adapter->hw_read_wx(adapter, 896 val = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK));
904 NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK));
905} 897}
906 898
907/* 899/*
@@ -1037,8 +1029,7 @@ netxen_do_load_firmware(struct netxen_adapter *adapter, const char *fwname,
1037 dev_info(&pdev->dev, "loading firmware from flash\n"); 1029 dev_info(&pdev->dev, "loading firmware from flash\n");
1038 1030
1039 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) 1031 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1040 adapter->hw_write_wx(adapter, 1032 NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
1041 NETXEN_ROMUSB_GLB_CAS_RST, 1);
1042 1033
1043 if (fw) { 1034 if (fw) {
1044 __le64 data; 1035 __le64 data;
@@ -1090,13 +1081,10 @@ netxen_do_load_firmware(struct netxen_adapter *adapter, const char *fwname,
1090 msleep(1); 1081 msleep(1);
1091 1082
1092 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) 1083 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
1093 adapter->hw_write_wx(adapter, 1084 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
1094 NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
1095 else { 1085 else {
1096 adapter->hw_write_wx(adapter, 1086 NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
1097 NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff); 1087 NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
1098 adapter->hw_write_wx(adapter,
1099 NETXEN_ROMUSB_GLB_CAS_RST, 0);
1100 } 1088 }
1101 1089
1102 return 0; 1090 return 0;
@@ -1154,8 +1142,7 @@ netxen_validate_firmware(struct netxen_adapter *adapter, const char *fwname,
1154 if (NETXEN_VERSION_CODE(major, minor, build) > ver) 1142 if (NETXEN_VERSION_CODE(major, minor, build) > ver)
1155 return -EINVAL; 1143 return -EINVAL;
1156 1144
1157 netxen_nic_reg_write(adapter, NETXEN_CAM_RAM(0x1fc), 1145 NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
1158 NETXEN_BDINFO_MAGIC);
1159 return 0; 1146 return 0;
1160} 1147}
1161 1148
@@ -1183,8 +1170,7 @@ request_mn:
1183 netxen_rom_fast_read(adapter, 1170 netxen_rom_fast_read(adapter,
1184 NX_FW_VERSION_OFFSET, (int *)&flashed_ver); 1171 NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
1185 if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) { 1172 if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
1186 capability = adapter->hw_read_wx(adapter, 1173 capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
1187 NX_PEG_TUNE_CAPABILITY);
1188 if (capability & NX_PEG_TUNE_MN_PRESENT) { 1174 if (capability & NX_PEG_TUNE_MN_PRESENT) {
1189 fw_type = NX_P3_MN_ROMIMAGE; 1175 fw_type = NX_P3_MN_ROMIMAGE;
1190 goto request_fw; 1176 goto request_fw;
@@ -1332,38 +1318,6 @@ netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off)
1332 return data; 1318 return data;
1333} 1319}
1334 1320
1335void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
1336{
1337 adapter->hw_write_wx(adapter, off, val);
1338}
1339
1340int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
1341{
1342 return adapter->hw_read_wx(adapter, off);
1343}
1344
1345/* Change the window to 0, write and change back to window 1. */
1346void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
1347{
1348 adapter->hw_write_wx(adapter, index, value);
1349}
1350
1351/* Change the window to 0, read and change back to window 1. */
1352u32 netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index)
1353{
1354 return adapter->hw_read_wx(adapter, index);
1355}
1356
1357void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value)
1358{
1359 adapter->hw_write_wx(adapter, index, value);
1360}
1361
1362u32 netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index)
1363{
1364 return adapter->hw_read_wx(adapter, index);
1365}
1366
1367/* 1321/*
1368 * check memory access boundary. 1322 * check memory access boundary.
1369 * used by test agent. support ddr access only for now 1323 * used by test agent. support ddr access only for now
@@ -1475,10 +1429,9 @@ netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1475 /* DDR network side */ 1429 /* DDR network side */
1476 window = MN_WIN(addr); 1430 window = MN_WIN(addr);
1477 adapter->ahw.ddr_mn_window = window; 1431 adapter->ahw.ddr_mn_window = window;
1478 adapter->hw_write_wx(adapter, 1432 NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1479 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1480 window); 1433 window);
1481 win_read = adapter->hw_read_wx(adapter, 1434 win_read = NXRD32(adapter,
1482 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE); 1435 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE);
1483 if ((win_read << 17) != window) { 1436 if ((win_read << 17) != window) {
1484 printk(KERN_INFO "Written MNwin (0x%x) != " 1437 printk(KERN_INFO "Written MNwin (0x%x) != "
@@ -1494,10 +1447,9 @@ netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1494 1447
1495 window = OCM_WIN(addr); 1448 window = OCM_WIN(addr);
1496 adapter->ahw.ddr_mn_window = window; 1449 adapter->ahw.ddr_mn_window = window;
1497 adapter->hw_write_wx(adapter, 1450 NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1498 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1499 window); 1451 window);
1500 win_read = adapter->hw_read_wx(adapter, 1452 win_read = NXRD32(adapter,
1501 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE); 1453 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE);
1502 if ((win_read >> 7) != window) { 1454 if ((win_read >> 7) != window) {
1503 printk(KERN_INFO "%s: Written OCMwin (0x%x) != " 1455 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
@@ -1511,10 +1463,9 @@ netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1511 /* QDR network side */ 1463 /* QDR network side */
1512 window = MS_WIN(addr); 1464 window = MS_WIN(addr);
1513 adapter->ahw.qdr_sn_window = window; 1465 adapter->ahw.qdr_sn_window = window;
1514 adapter->hw_write_wx(adapter, 1466 NXWR32(adapter, adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1515 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1516 window); 1467 window);
1517 win_read = adapter->hw_read_wx(adapter, 1468 win_read = NXRD32(adapter,
1518 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE); 1469 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE);
1519 if (win_read != window) { 1470 if (win_read != window) {
1520 printk(KERN_INFO "%s: Written MSwin (0x%x) != " 1471 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
@@ -1961,27 +1912,20 @@ netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1961 1912
1962 for (i = 0; i < loop; i++) { 1913 for (i = 0; i < loop; i++) {
1963 temp = off8 + (i << 3); 1914 temp = off8 + (i << 3);
1964 adapter->hw_write_wx(adapter, 1915 NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1965 mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1966 temp = 0; 1916 temp = 0;
1967 adapter->hw_write_wx(adapter, 1917 NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1968 mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1969 temp = word[i] & 0xffffffff; 1918 temp = word[i] & 0xffffffff;
1970 adapter->hw_write_wx(adapter, 1919 NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1971 mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1972 temp = (word[i] >> 32) & 0xffffffff; 1920 temp = (word[i] >> 32) & 0xffffffff;
1973 adapter->hw_write_wx(adapter, 1921 NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1974 mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1975 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1922 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1976 adapter->hw_write_wx(adapter, 1923 NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp);
1977 mem_crb+MIU_TEST_AGT_CTRL, temp);
1978 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1924 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1979 adapter->hw_write_wx(adapter, 1925 NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp);
1980 mem_crb+MIU_TEST_AGT_CTRL, temp);
1981 1926
1982 for (j = 0; j < MAX_CTL_CHECK; j++) { 1927 for (j = 0; j < MAX_CTL_CHECK; j++) {
1983 temp = adapter->hw_read_wx(adapter, 1928 temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL);
1984 mem_crb + MIU_TEST_AGT_CTRL);
1985 if ((temp & MIU_TA_CTL_BUSY) == 0) 1929 if ((temp & MIU_TA_CTL_BUSY) == 0)
1986 break; 1930 break;
1987 } 1931 }
@@ -2038,21 +1982,16 @@ netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
2038 1982
2039 for (i = 0; i < loop; i++) { 1983 for (i = 0; i < loop; i++) {
2040 temp = off8 + (i << 3); 1984 temp = off8 + (i << 3);
2041 adapter->hw_write_wx(adapter, 1985 NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
2042 mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
2043 temp = 0; 1986 temp = 0;
2044 adapter->hw_write_wx(adapter, 1987 NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
2045 mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
2046 temp = MIU_TA_CTL_ENABLE; 1988 temp = MIU_TA_CTL_ENABLE;
2047 adapter->hw_write_wx(adapter, 1989 NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp);
2048 mem_crb + MIU_TEST_AGT_CTRL, temp);
2049 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1990 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
2050 adapter->hw_write_wx(adapter, 1991 NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp);
2051 mem_crb + MIU_TEST_AGT_CTRL, temp);
2052 1992
2053 for (j = 0; j < MAX_CTL_CHECK; j++) { 1993 for (j = 0; j < MAX_CTL_CHECK; j++) {
2054 temp = adapter->hw_read_wx(adapter, 1994 temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL);
2055 mem_crb + MIU_TEST_AGT_CTRL);
2056 if ((temp & MIU_TA_CTL_BUSY) == 0) 1995 if ((temp & MIU_TA_CTL_BUSY) == 0)
2057 break; 1996 break;
2058 } 1997 }
@@ -2067,7 +2006,7 @@ netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
2067 start = off0[i] >> 2; 2006 start = off0[i] >> 2;
2068 end = (off0[i] + sz[i] - 1) >> 2; 2007 end = (off0[i] + sz[i] - 1) >> 2;
2069 for (k = start; k <= end; k++) { 2008 for (k = start; k <= end; k++) {
2070 temp = adapter->hw_read_wx(adapter, 2009 temp = NXRD32(adapter,
2071 mem_crb + MIU_TEST_AGT_RDDATA(k)); 2010 mem_crb + MIU_TEST_AGT_RDDATA(k));
2072 word[i] |= ((uint64_t)temp << (32 * k)); 2011 word[i] |= ((uint64_t)temp << (32 * k));
2073 } 2012 }
@@ -2111,14 +2050,14 @@ netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
2111int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter, 2050int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
2112 u64 off, u32 data) 2051 u64 off, u32 data)
2113{ 2052{
2114 adapter->hw_write_wx(adapter, off, data); 2053 NXWR32(adapter, off, data);
2115 2054
2116 return 0; 2055 return 0;
2117} 2056}
2118 2057
2119u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off) 2058u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off)
2120{ 2059{
2121 return adapter->hw_read_wx(adapter, off); 2060 return NXRD32(adapter, off);
2122} 2061}
2123 2062
2124int netxen_nic_get_board_info(struct netxen_adapter *adapter) 2063int netxen_nic_get_board_info(struct netxen_adapter *adapter)
@@ -2152,8 +2091,7 @@ int netxen_nic_get_board_info(struct netxen_adapter *adapter)
2152 adapter->ahw.board_type = board_type; 2091 adapter->ahw.board_type = board_type;
2153 2092
2154 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) { 2093 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
2155 u32 gpio = netxen_nic_reg_read(adapter, 2094 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I);
2156 NETXEN_ROMUSB_GLB_PAD_GPIO_I);
2157 if ((gpio & 0x8000) == 0) 2095 if ((gpio & 0x8000) == 0)
2158 board_type = NETXEN_BRDTYPE_P3_10G_TP; 2096 board_type = NETXEN_BRDTYPE_P3_10G_TP;
2159 } 2097 }
@@ -2205,8 +2143,7 @@ int netxen_nic_get_board_info(struct netxen_adapter *adapter)
2205int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu) 2143int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
2206{ 2144{
2207 new_mtu += MTU_FUDGE_FACTOR; 2145 new_mtu += MTU_FUDGE_FACTOR;
2208 netxen_nic_write_w0(adapter, 2146 NXWR32(adapter, NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
2209 NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
2210 new_mtu); 2147 new_mtu);
2211 return 0; 2148 return 0;
2212} 2149}
@@ -2215,21 +2152,12 @@ int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
2215{ 2152{
2216 new_mtu += MTU_FUDGE_FACTOR; 2153 new_mtu += MTU_FUDGE_FACTOR;
2217 if (adapter->physical_port == 0) 2154 if (adapter->physical_port == 0)
2218 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, 2155 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
2219 new_mtu);
2220 else 2156 else
2221 netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, 2157 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
2222 new_mtu);
2223 return 0; 2158 return 0;
2224} 2159}
2225 2160
2226void
2227netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
2228 unsigned long off, int data)
2229{
2230 adapter->hw_write_wx(adapter, off, data);
2231}
2232
2233void netxen_nic_set_link_parameters(struct netxen_adapter *adapter) 2161void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
2234{ 2162{
2235 __u32 status; 2163 __u32 status;
@@ -2244,8 +2172,7 @@ void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
2244 } 2172 }
2245 2173
2246 if (adapter->ahw.port_type == NETXEN_NIC_GBE) { 2174 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
2247 port_mode = adapter->hw_read_wx(adapter, 2175 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
2248 NETXEN_PORT_MODE_ADDR);
2249 if (port_mode == NETXEN_PORT_MODE_802_3_AP) { 2176 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
2250 adapter->link_speed = SPEED_1000; 2177 adapter->link_speed = SPEED_1000;
2251 adapter->link_duplex = DUPLEX_FULL; 2178 adapter->link_duplex = DUPLEX_FULL;
@@ -2322,9 +2249,9 @@ void netxen_nic_get_firmware_info(struct netxen_adapter *adapter)
2322 addr += sizeof(u32); 2249 addr += sizeof(u32);
2323 } 2250 }
2324 2251
2325 fw_major = adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MAJOR); 2252 fw_major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
2326 fw_minor = adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MINOR); 2253 fw_minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
2327 fw_build = adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_SUB); 2254 fw_build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
2328 2255
2329 adapter->fw_major = fw_major; 2256 adapter->fw_major = fw_major;
2330 adapter->fw_version = NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build); 2257 adapter->fw_version = NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build);
@@ -2347,7 +2274,7 @@ void netxen_nic_get_firmware_info(struct netxen_adapter *adapter)
2347 fw_major, fw_minor, fw_build); 2274 fw_major, fw_minor, fw_build);
2348 2275
2349 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { 2276 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
2350 i = adapter->hw_read_wx(adapter, NETXEN_MIU_MN_CONTROL); 2277 i = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
2351 adapter->ahw.cut_through = (i & 0x4) ? 1 : 0; 2278 adapter->ahw.cut_through = (i & 0x4) ? 1 : 0;
2352 dev_info(&pdev->dev, "firmware running in %s mode\n", 2279 dev_info(&pdev->dev, "firmware running in %s mode\n",
2353 adapter->ahw.cut_through ? "cut-through" : "legacy"); 2280 adapter->ahw.cut_through ? "cut-through" : "legacy");
@@ -2362,9 +2289,9 @@ netxen_nic_wol_supported(struct netxen_adapter *adapter)
2362 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) 2289 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
2363 return 0; 2290 return 0;
2364 2291
2365 wol_cfg = netxen_nic_reg_read(adapter, NETXEN_WOL_CONFIG_NV); 2292 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
2366 if (wol_cfg & (1UL << adapter->portnum)) { 2293 if (wol_cfg & (1UL << adapter->portnum)) {
2367 wol_cfg = netxen_nic_reg_read(adapter, NETXEN_WOL_CONFIG); 2294 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
2368 if (wol_cfg & (1 << adapter->portnum)) 2295 if (wol_cfg & (1 << adapter->portnum))
2369 return 1; 2296 return 1;
2370 } 2297 }
diff --git a/drivers/net/netxen/netxen_nic_init.c b/drivers/net/netxen/netxen_nic_init.c
index 83116c2817b0..0c91238133f0 100644
--- a/drivers/net/netxen/netxen_nic_init.c
+++ b/drivers/net/netxen/netxen_nic_init.c
@@ -368,8 +368,7 @@ static int rom_lock(struct netxen_adapter *adapter)
368 368
369 while (!done) { 369 while (!done) {
370 /* acquire semaphore2 from PCI HW block */ 370 /* acquire semaphore2 from PCI HW block */
371 done = netxen_nic_read_w0(adapter, 371 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK));
372 NETXEN_PCIE_REG(PCIE_SEM2_LOCK));
373 if (done == 1) 372 if (done == 1)
374 break; 373 break;
375 if (timeout >= rom_lock_timeout) 374 if (timeout >= rom_lock_timeout)
@@ -386,7 +385,7 @@ static int rom_lock(struct netxen_adapter *adapter)
386 cpu_relax(); /*This a nop instr on i386 */ 385 cpu_relax(); /*This a nop instr on i386 */
387 } 386 }
388 } 387 }
389 netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER); 388 NXWR32(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
390 return 0; 389 return 0;
391} 390}
392 391
@@ -398,7 +397,7 @@ static int netxen_wait_rom_done(struct netxen_adapter *adapter)
398 cond_resched(); 397 cond_resched();
399 398
400 while (done == 0) { 399 while (done == 0) {
401 done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS); 400 done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
402 done &= 2; 401 done &= 2;
403 timeout++; 402 timeout++;
404 if (timeout >= rom_max_timeout) { 403 if (timeout >= rom_max_timeout) {
@@ -412,27 +411,27 @@ static int netxen_wait_rom_done(struct netxen_adapter *adapter)
412static void netxen_rom_unlock(struct netxen_adapter *adapter) 411static void netxen_rom_unlock(struct netxen_adapter *adapter)
413{ 412{
414 /* release semaphore2 */ 413 /* release semaphore2 */
415 netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK)); 414 NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK));
416 415
417} 416}
418 417
419static int do_rom_fast_read(struct netxen_adapter *adapter, 418static int do_rom_fast_read(struct netxen_adapter *adapter,
420 int addr, int *valp) 419 int addr, int *valp)
421{ 420{
422 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr); 421 NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
423 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 422 NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
424 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3); 423 NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
425 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb); 424 NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
426 if (netxen_wait_rom_done(adapter)) { 425 if (netxen_wait_rom_done(adapter)) {
427 printk("Error waiting for rom done\n"); 426 printk("Error waiting for rom done\n");
428 return -EIO; 427 return -EIO;
429 } 428 }
430 /* reset abyte_cnt and dummy_byte_cnt */ 429 /* reset abyte_cnt and dummy_byte_cnt */
431 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0); 430 NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
432 udelay(10); 431 udelay(10);
433 netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 432 NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
434 433
435 *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA); 434 *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
436 return 0; 435 return 0;
437} 436}
438 437
@@ -496,8 +495,7 @@ int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
496 495
497 /* resetall */ 496 /* resetall */
498 rom_lock(adapter); 497 rom_lock(adapter);
499 netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 498 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
500 0xffffffff);
501 netxen_rom_unlock(adapter); 499 netxen_rom_unlock(adapter);
502 500
503 if (verbose) { 501 if (verbose) {
@@ -621,7 +619,7 @@ int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
621 } 619 }
622 } 620 }
623 621
624 adapter->hw_write_wx(adapter, off, buf[i].data); 622 NXWR32(adapter, off, buf[i].data);
625 623
626 msleep(init_delay); 624 msleep(init_delay);
627 } 625 }
@@ -631,33 +629,31 @@ int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
631 629
632 /* unreset_net_cache */ 630 /* unreset_net_cache */
633 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { 631 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
634 val = adapter->hw_read_wx(adapter, 632 val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
635 NETXEN_ROMUSB_GLB_SW_RESET); 633 NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
636 netxen_crb_writelit_adapter(adapter,
637 NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
638 } 634 }
639 635
640 /* p2dn replyCount */ 636 /* p2dn replyCount */
641 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e); 637 NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
642 /* disable_peg_cache 0 */ 638 /* disable_peg_cache 0 */
643 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8); 639 NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
644 /* disable_peg_cache 1 */ 640 /* disable_peg_cache 1 */
645 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8); 641 NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
646 642
647 /* peg_clr_all */ 643 /* peg_clr_all */
648 644
649 /* peg_clr 0 */ 645 /* peg_clr 0 */
650 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0); 646 NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
651 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0); 647 NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
652 /* peg_clr 1 */ 648 /* peg_clr 1 */
653 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0); 649 NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
654 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0); 650 NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
655 /* peg_clr 2 */ 651 /* peg_clr 2 */
656 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0); 652 NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
657 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0); 653 NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
658 /* peg_clr 3 */ 654 /* peg_clr 3 */
659 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0); 655 NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
660 netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0); 656 NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
661 return 0; 657 return 0;
662} 658}
663 659
@@ -681,12 +677,12 @@ int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
681 hi = (addr >> 32) & 0xffffffff; 677 hi = (addr >> 32) & 0xffffffff;
682 lo = addr & 0xffffffff; 678 lo = addr & 0xffffffff;
683 679
684 adapter->hw_write_wx(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi); 680 NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
685 adapter->hw_write_wx(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo); 681 NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
686 682
687 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { 683 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
688 uint32_t temp = 0; 684 uint32_t temp = 0;
689 adapter->hw_write_wx(adapter, CRB_HOST_DUMMY_BUF, temp); 685 NXWR32(adapter, CRB_HOST_DUMMY_BUF, temp);
690 } 686 }
691 687
692 return 0; 688 return 0;
@@ -728,8 +724,7 @@ int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
728 724
729 if (!pegtune_val) { 725 if (!pegtune_val) {
730 do { 726 do {
731 val = adapter->hw_read_wx(adapter, 727 val = NXRD32(adapter, CRB_CMDPEG_STATE);
732 CRB_CMDPEG_STATE);
733 728
734 if (val == PHAN_INITIALIZE_COMPLETE || 729 if (val == PHAN_INITIALIZE_COMPLETE ||
735 val == PHAN_INITIALIZE_ACK) 730 val == PHAN_INITIALIZE_ACK)
@@ -740,7 +735,7 @@ int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
740 } while (--retries); 735 } while (--retries);
741 736
742 if (!retries) { 737 if (!retries) {
743 pegtune_val = adapter->hw_read_wx(adapter, 738 pegtune_val = NXRD32(adapter,
744 NETXEN_ROMUSB_GLB_PEGTUNE_DONE); 739 NETXEN_ROMUSB_GLB_PEGTUNE_DONE);
745 printk(KERN_WARNING "netxen_phantom_init: init failed, " 740 printk(KERN_WARNING "netxen_phantom_init: init failed, "
746 "pegtune_val=%x\n", pegtune_val); 741 "pegtune_val=%x\n", pegtune_val);
@@ -758,7 +753,7 @@ netxen_receive_peg_ready(struct netxen_adapter *adapter)
758 int retries = 2000; 753 int retries = 2000;
759 754
760 do { 755 do {
761 val = adapter->hw_read_wx(adapter, CRB_RCVPEG_STATE); 756 val = NXRD32(adapter, CRB_RCVPEG_STATE);
762 757
763 if (val == PHAN_PEG_RCV_INITIALIZED) 758 if (val == PHAN_PEG_RCV_INITIALIZED)
764 return 0; 759 return 0;
@@ -784,18 +779,13 @@ int netxen_init_firmware(struct netxen_adapter *adapter)
784 if (err) 779 if (err)
785 return err; 780 return err;
786 781
787 adapter->hw_write_wx(adapter, 782 NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
788 CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT); 783 NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
789 adapter->hw_write_wx(adapter, 784 NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
790 CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC); 785 NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
791 adapter->hw_write_wx(adapter,
792 CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
793 adapter->hw_write_wx(adapter,
794 CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
795 786
796 if (adapter->fw_version >= NETXEN_VERSION_CODE(4, 0, 222)) { 787 if (adapter->fw_version >= NETXEN_VERSION_CODE(4, 0, 222)) {
797 adapter->capabilities = netxen_nic_reg_read(adapter, 788 adapter->capabilities = NXRD32(adapter, CRB_FW_CAPABILITIES_1);
798 CRB_FW_CAPABILITIES_1);
799 } 789 }
800 790
801 return err; 791 return err;
@@ -1057,8 +1047,7 @@ skip:
1057 1047
1058 if (count) { 1048 if (count) {
1059 sds_ring->consumer = consumer; 1049 sds_ring->consumer = consumer;
1060 adapter->hw_write_wx(adapter, 1050 NXWR32(adapter, sds_ring->crb_sts_consumer, consumer);
1061 sds_ring->crb_sts_consumer, consumer);
1062 } 1051 }
1063 1052
1064 return count; 1053 return count;
@@ -1176,8 +1165,7 @@ netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1176 1165
1177 if (count) { 1166 if (count) {
1178 rds_ring->producer = producer; 1167 rds_ring->producer = producer;
1179 adapter->hw_write_wx(adapter, 1168 NXWR32(adapter, rds_ring->crb_rcv_producer,
1180 rds_ring->crb_rcv_producer,
1181 (producer-1) & (rds_ring->num_desc-1)); 1169 (producer-1) & (rds_ring->num_desc-1));
1182 1170
1183 if (adapter->fw_major < 4) { 1171 if (adapter->fw_major < 4) {
@@ -1237,8 +1225,7 @@ netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
1237 1225
1238 if (count) { 1226 if (count) {
1239 rds_ring->producer = producer; 1227 rds_ring->producer = producer;
1240 adapter->hw_write_wx(adapter, 1228 NXWR32(adapter, rds_ring->crb_rcv_producer,
1241 rds_ring->crb_rcv_producer,
1242 (producer - 1) & (rds_ring->num_desc - 1)); 1229 (producer - 1) & (rds_ring->num_desc - 1));
1243 wmb(); 1230 wmb();
1244 } 1231 }
diff --git a/drivers/net/netxen/netxen_nic_main.c b/drivers/net/netxen/netxen_nic_main.c
index 31966a044900..8426092deda3 100644
--- a/drivers/net/netxen/netxen_nic_main.c
+++ b/drivers/net/netxen/netxen_nic_main.c
@@ -109,8 +109,7 @@ void
109netxen_nic_update_cmd_producer(struct netxen_adapter *adapter, 109netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
110 struct nx_host_tx_ring *tx_ring, u32 producer) 110 struct nx_host_tx_ring *tx_ring, u32 producer)
111{ 111{
112 adapter->hw_write_wx(adapter, 112 NXWR32(adapter, tx_ring->crb_cmd_producer, producer);
113 tx_ring->crb_cmd_producer, producer);
114} 113}
115 114
116static uint32_t crb_cmd_consumer[4] = { 115static uint32_t crb_cmd_consumer[4] = {
@@ -122,8 +121,7 @@ static inline void
122netxen_nic_update_cmd_consumer(struct netxen_adapter *adapter, 121netxen_nic_update_cmd_consumer(struct netxen_adapter *adapter,
123 struct nx_host_tx_ring *tx_ring, u32 consumer) 122 struct nx_host_tx_ring *tx_ring, u32 consumer)
124{ 123{
125 adapter->hw_write_wx(adapter, 124 NXWR32(adapter, tx_ring->crb_cmd_consumer, consumer);
126 tx_ring->crb_cmd_consumer, consumer);
127} 125}
128 126
129static uint32_t msi_tgt_status[8] = { 127static uint32_t msi_tgt_status[8] = {
@@ -139,14 +137,14 @@ static inline void netxen_nic_disable_int(struct nx_host_sds_ring *sds_ring)
139{ 137{
140 struct netxen_adapter *adapter = sds_ring->adapter; 138 struct netxen_adapter *adapter = sds_ring->adapter;
141 139
142 adapter->hw_write_wx(adapter, sds_ring->crb_intr_mask, 0); 140 NXWR32(adapter, sds_ring->crb_intr_mask, 0);
143} 141}
144 142
145static inline void netxen_nic_enable_int(struct nx_host_sds_ring *sds_ring) 143static inline void netxen_nic_enable_int(struct nx_host_sds_ring *sds_ring)
146{ 144{
147 struct netxen_adapter *adapter = sds_ring->adapter; 145 struct netxen_adapter *adapter = sds_ring->adapter;
148 146
149 adapter->hw_write_wx(adapter, sds_ring->crb_intr_mask, 0x1); 147 NXWR32(adapter, sds_ring->crb_intr_mask, 0x1);
150 148
151 if (!NETXEN_IS_MSI_FAMILY(adapter)) 149 if (!NETXEN_IS_MSI_FAMILY(adapter))
152 adapter->pci_write_immediate(adapter, 150 adapter->pci_write_immediate(adapter,
@@ -262,7 +260,7 @@ nx_update_dma_mask(struct netxen_adapter *adapter)
262 260
263 change = 0; 261 change = 0;
264 262
265 shift = netxen_nic_reg_read(adapter, CRB_DMA_SHIFT); 263 shift = NXRD32(adapter, CRB_DMA_SHIFT);
266 if (shift >= 32) 264 if (shift >= 32)
267 return 0; 265 return 0;
268 266
@@ -309,42 +307,34 @@ netxen_check_hw_init(struct netxen_adapter *adapter, int first_boot)
309 307
310 if (first_boot == 0x55555555) { 308 if (first_boot == 0x55555555) {
311 /* This is the first boot after power up */ 309 /* This is the first boot after power up */
312 adapter->hw_write_wx(adapter, 310 NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
313 NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
314 311
315 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id)) 312 if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
316 return 0; 313 return 0;
317 314
318 /* PCI bus master workaround */ 315 /* PCI bus master workaround */
319 first_boot = adapter->hw_read_wx(adapter, NETXEN_PCIE_REG(0x4)); 316 first_boot = NXRD32(adapter, NETXEN_PCIE_REG(0x4));
320 if (!(first_boot & 0x4)) { 317 if (!(first_boot & 0x4)) {
321 first_boot |= 0x4; 318 first_boot |= 0x4;
322 adapter->hw_write_wx(adapter, 319 NXWR32(adapter, NETXEN_PCIE_REG(0x4), first_boot);
323 NETXEN_PCIE_REG(0x4), first_boot); 320 first_boot = NXRD32(adapter, NETXEN_PCIE_REG(0x4));
324 first_boot = adapter->hw_read_wx(adapter,
325 NETXEN_PCIE_REG(0x4));
326 } 321 }
327 322
328 /* This is the first boot after power up */ 323 /* This is the first boot after power up */
329 first_boot = adapter->hw_read_wx(adapter, 324 first_boot = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
330 NETXEN_ROMUSB_GLB_SW_RESET);
331 if (first_boot != 0x80000f) { 325 if (first_boot != 0x80000f) {
332 /* clear the register for future unloads/loads */ 326 /* clear the register for future unloads/loads */
333 adapter->hw_write_wx(adapter, 327 NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), 0);
334 NETXEN_CAM_RAM(0x1fc), 0);
335 return -EIO; 328 return -EIO;
336 } 329 }
337 330
338 /* Start P2 boot loader */ 331 /* Start P2 boot loader */
339 val = adapter->hw_read_wx(adapter, 332 val = NXRD32(adapter, NETXEN_ROMUSB_GLB_PEGTUNE_DONE);
340 NETXEN_ROMUSB_GLB_PEGTUNE_DONE); 333 NXWR32(adapter, NETXEN_ROMUSB_GLB_PEGTUNE_DONE, val | 0x1);
341 adapter->hw_write_wx(adapter,
342 NETXEN_ROMUSB_GLB_PEGTUNE_DONE, val | 0x1);
343 timeout = 0; 334 timeout = 0;
344 do { 335 do {
345 msleep(1); 336 msleep(1);
346 val = adapter->hw_read_wx(adapter, 337 val = NXRD32(adapter, NETXEN_CAM_RAM(0x1fc));
347 NETXEN_CAM_RAM(0x1fc));
348 338
349 if (++timeout > 5000) 339 if (++timeout > 5000)
350 return -EIO; 340 return -EIO;
@@ -363,24 +353,19 @@ static void netxen_set_port_mode(struct netxen_adapter *adapter)
363 (val == NETXEN_BRDTYPE_P3_XG_LOM)) { 353 (val == NETXEN_BRDTYPE_P3_XG_LOM)) {
364 if (port_mode == NETXEN_PORT_MODE_802_3_AP) { 354 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
365 data = NETXEN_PORT_MODE_802_3_AP; 355 data = NETXEN_PORT_MODE_802_3_AP;
366 adapter->hw_write_wx(adapter, 356 NXWR32(adapter, NETXEN_PORT_MODE_ADDR, data);
367 NETXEN_PORT_MODE_ADDR, data);
368 } else if (port_mode == NETXEN_PORT_MODE_XG) { 357 } else if (port_mode == NETXEN_PORT_MODE_XG) {
369 data = NETXEN_PORT_MODE_XG; 358 data = NETXEN_PORT_MODE_XG;
370 adapter->hw_write_wx(adapter, 359 NXWR32(adapter, NETXEN_PORT_MODE_ADDR, data);
371 NETXEN_PORT_MODE_ADDR, data);
372 } else if (port_mode == NETXEN_PORT_MODE_AUTO_NEG_1G) { 360 } else if (port_mode == NETXEN_PORT_MODE_AUTO_NEG_1G) {
373 data = NETXEN_PORT_MODE_AUTO_NEG_1G; 361 data = NETXEN_PORT_MODE_AUTO_NEG_1G;
374 adapter->hw_write_wx(adapter, 362 NXWR32(adapter, NETXEN_PORT_MODE_ADDR, data);
375 NETXEN_PORT_MODE_ADDR, data);
376 } else if (port_mode == NETXEN_PORT_MODE_AUTO_NEG_XG) { 363 } else if (port_mode == NETXEN_PORT_MODE_AUTO_NEG_XG) {
377 data = NETXEN_PORT_MODE_AUTO_NEG_XG; 364 data = NETXEN_PORT_MODE_AUTO_NEG_XG;
378 adapter->hw_write_wx(adapter, 365 NXWR32(adapter, NETXEN_PORT_MODE_ADDR, data);
379 NETXEN_PORT_MODE_ADDR, data);
380 } else { 366 } else {
381 data = NETXEN_PORT_MODE_AUTO_NEG; 367 data = NETXEN_PORT_MODE_AUTO_NEG;
382 adapter->hw_write_wx(adapter, 368 NXWR32(adapter, NETXEN_PORT_MODE_ADDR, data);
383 NETXEN_PORT_MODE_ADDR, data);
384 } 369 }
385 370
386 if ((wol_port_mode != NETXEN_PORT_MODE_802_3_AP) && 371 if ((wol_port_mode != NETXEN_PORT_MODE_802_3_AP) &&
@@ -389,8 +374,7 @@ static void netxen_set_port_mode(struct netxen_adapter *adapter)
389 (wol_port_mode != NETXEN_PORT_MODE_AUTO_NEG_XG)) { 374 (wol_port_mode != NETXEN_PORT_MODE_AUTO_NEG_XG)) {
390 wol_port_mode = NETXEN_PORT_MODE_AUTO_NEG; 375 wol_port_mode = NETXEN_PORT_MODE_AUTO_NEG;
391 } 376 }
392 adapter->hw_write_wx(adapter, NETXEN_WOL_PORT_MODE, 377 NXWR32(adapter, NETXEN_WOL_PORT_MODE, wol_port_mode);
393 wol_port_mode);
394 } 378 }
395} 379}
396 380
@@ -674,8 +658,7 @@ netxen_start_firmware(struct netxen_adapter *adapter)
674 if (!first_driver) 658 if (!first_driver)
675 return 0; 659 return 0;
676 660
677 first_boot = adapter->hw_read_wx(adapter, 661 first_boot = NXRD32(adapter, NETXEN_CAM_RAM(0x1fc));
678 NETXEN_CAM_RAM(0x1fc));
679 662
680 err = netxen_check_hw_init(adapter, first_boot); 663 err = netxen_check_hw_init(adapter, first_boot);
681 if (err) { 664 if (err) {
@@ -684,13 +667,12 @@ netxen_start_firmware(struct netxen_adapter *adapter)
684 } 667 }
685 668
686 if (first_boot != 0x55555555) { 669 if (first_boot != 0x55555555) {
687 adapter->hw_write_wx(adapter, 670 NXWR32(adapter, CRB_CMDPEG_STATE, 0);
688 CRB_CMDPEG_STATE, 0);
689 netxen_pinit_from_rom(adapter, 0); 671 netxen_pinit_from_rom(adapter, 0);
690 msleep(1); 672 msleep(1);
691 } 673 }
692 674
693 netxen_nic_reg_write(adapter, CRB_DMA_SHIFT, 0x55555555); 675 NXWR32(adapter, CRB_DMA_SHIFT, 0x55555555);
694 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) 676 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
695 netxen_set_port_mode(adapter); 677 netxen_set_port_mode(adapter);
696 678
@@ -702,8 +684,7 @@ netxen_start_firmware(struct netxen_adapter *adapter)
702 val = 0x7654; 684 val = 0x7654;
703 if (adapter->ahw.port_type == NETXEN_NIC_XGBE) 685 if (adapter->ahw.port_type == NETXEN_NIC_XGBE)
704 val |= 0x0f000000; 686 val |= 0x0f000000;
705 netxen_crb_writelit_adapter(adapter, 687 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
706 NETXEN_MAC_ADDR_CNTL_REG, val);
707 688
708 } 689 }
709 690
@@ -717,7 +698,7 @@ netxen_start_firmware(struct netxen_adapter *adapter)
717 val = (_NETXEN_NIC_LINUX_MAJOR << 16) 698 val = (_NETXEN_NIC_LINUX_MAJOR << 16)
718 | ((_NETXEN_NIC_LINUX_MINOR << 8)) 699 | ((_NETXEN_NIC_LINUX_MINOR << 8))
719 | (_NETXEN_NIC_LINUX_SUBVERSION); 700 | (_NETXEN_NIC_LINUX_SUBVERSION);
720 adapter->hw_write_wx(adapter, CRB_DRIVER_VERSION, val); 701 NXWR32(adapter, CRB_DRIVER_VERSION, val);
721 702
722 /* Handshake with the card before we register the devices. */ 703 /* Handshake with the card before we register the devices. */
723 err = netxen_phantom_init(adapter, NETXEN_NIC_PEG_TUNE); 704 err = netxen_phantom_init(adapter, NETXEN_NIC_PEG_TUNE);
@@ -1032,8 +1013,7 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1032 */ 1013 */
1033 adapter->physical_port = adapter->portnum; 1014 adapter->physical_port = adapter->portnum;
1034 if (adapter->fw_major < 4) { 1015 if (adapter->fw_major < 4) {
1035 i = adapter->hw_read_wx(adapter, 1016 i = NXRD32(adapter, CRB_V2P(adapter->portnum));
1036 CRB_V2P(adapter->portnum));
1037 if (i != 0x55555555) 1017 if (i != 0x55555555)
1038 adapter->physical_port = i; 1018 adapter->physical_port = i;
1039 } 1019 }
@@ -1480,7 +1460,7 @@ static int netxen_nic_check_temp(struct netxen_adapter *adapter)
1480 uint32_t temp, temp_state, temp_val; 1460 uint32_t temp, temp_state, temp_val;
1481 int rv = 0; 1461 int rv = 0;
1482 1462
1483 temp = adapter->hw_read_wx(adapter, CRB_TEMP_STATE); 1463 temp = NXRD32(adapter, CRB_TEMP_STATE);
1484 1464
1485 temp_state = nx_get_temp_state(temp); 1465 temp_state = nx_get_temp_state(temp);
1486 temp_val = nx_get_temp_val(temp); 1466 temp_val = nx_get_temp_val(temp);
@@ -1551,11 +1531,11 @@ static void netxen_nic_handle_phy_intr(struct netxen_adapter *adapter)
1551 port = adapter->physical_port; 1531 port = adapter->physical_port;
1552 1532
1553 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { 1533 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
1554 val = adapter->hw_read_wx(adapter, CRB_XG_STATE_P3); 1534 val = NXRD32(adapter, CRB_XG_STATE_P3);
1555 val = XG_LINK_STATE_P3(adapter->ahw.pci_func, val); 1535 val = XG_LINK_STATE_P3(adapter->ahw.pci_func, val);
1556 linkup = (val == XG_LINK_UP_P3); 1536 linkup = (val == XG_LINK_UP_P3);
1557 } else { 1537 } else {
1558 val = adapter->hw_read_wx(adapter, CRB_XG_STATE); 1538 val = NXRD32(adapter, CRB_XG_STATE);
1559 if (adapter->ahw.port_type == NETXEN_NIC_GBE) 1539 if (adapter->ahw.port_type == NETXEN_NIC_GBE)
1560 linkup = (val >> port) & 1; 1540 linkup = (val >> port) & 1;
1561 else { 1541 else {
@@ -1650,15 +1630,14 @@ static irqreturn_t netxen_intr(int irq, void *data)
1650 } else { 1630 } else {
1651 unsigned long our_int = 0; 1631 unsigned long our_int = 0;
1652 1632
1653 our_int = adapter->hw_read_wx(adapter, CRB_INT_VECTOR); 1633 our_int = NXRD32(adapter, CRB_INT_VECTOR);
1654 1634
1655 /* not our interrupt */ 1635 /* not our interrupt */
1656 if (!test_and_clear_bit((7 + adapter->portnum), &our_int)) 1636 if (!test_and_clear_bit((7 + adapter->portnum), &our_int))
1657 return IRQ_NONE; 1637 return IRQ_NONE;
1658 1638
1659 /* claim interrupt */ 1639 /* claim interrupt */
1660 adapter->hw_write_wx(adapter, 1640 NXWR32(adapter, CRB_INT_VECTOR, (our_int & 0xffffffff));
1661 CRB_INT_VECTOR, (our_int & 0xffffffff));
1662 } 1641 }
1663 1642
1664 /* clear interrupt */ 1643 /* clear interrupt */
diff --git a/drivers/net/netxen/netxen_nic_niu.c b/drivers/net/netxen/netxen_nic_niu.c
index b54a63a64e7b..5e2698bf575a 100644
--- a/drivers/net/netxen/netxen_nic_niu.c
+++ b/drivers/net/netxen/netxen_nic_niu.c
@@ -43,8 +43,7 @@ static int phy_lock(struct netxen_adapter *adapter)
43 int done = 0, timeout = 0; 43 int done = 0, timeout = 0;
44 44
45 while (!done) { 45 while (!done) {
46 done = netxen_nic_reg_read(adapter, 46 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM3_LOCK));
47 NETXEN_PCIE_REG(PCIE_SEM3_LOCK));
48 if (done == 1) 47 if (done == 1)
49 break; 48 break;
50 if (timeout >= phy_lock_timeout) { 49 if (timeout >= phy_lock_timeout) {
@@ -59,8 +58,7 @@ static int phy_lock(struct netxen_adapter *adapter)
59 } 58 }
60 } 59 }
61 60
62 netxen_crb_writelit_adapter(adapter, 61 NXWR32(adapter, NETXEN_PHY_LOCK_ID, PHY_LOCK_DRIVER);
63 NETXEN_PHY_LOCK_ID, PHY_LOCK_DRIVER);
64 return 0; 62 return 0;
65} 63}
66 64
@@ -105,7 +103,7 @@ int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
105 * so it cannot be in reset 103 * so it cannot be in reset
106 */ 104 */
107 105
108 mac_cfg0 = adapter->hw_read_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0)); 106 mac_cfg0 = NXRD32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0));
109 if (netxen_gb_get_soft_reset(mac_cfg0)) { 107 if (netxen_gb_get_soft_reset(mac_cfg0)) {
110 __u32 temp; 108 __u32 temp;
111 temp = 0; 109 temp = 0;
@@ -113,8 +111,7 @@ int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
113 netxen_gb_rx_reset_pb(temp); 111 netxen_gb_rx_reset_pb(temp);
114 netxen_gb_tx_reset_mac(temp); 112 netxen_gb_tx_reset_mac(temp);
115 netxen_gb_rx_reset_mac(temp); 113 netxen_gb_rx_reset_mac(temp);
116 if (adapter->hw_write_wx(adapter, 114 if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), temp))
117 NETXEN_NIU_GB_MAC_CONFIG_0(0), temp))
118 return -EIO; 115 return -EIO;
119 restore = 1; 116 restore = 1;
120 } 117 }
@@ -122,38 +119,32 @@ int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
122 address = 0; 119 address = 0;
123 netxen_gb_mii_mgmt_reg_addr(address, reg); 120 netxen_gb_mii_mgmt_reg_addr(address, reg);
124 netxen_gb_mii_mgmt_phy_addr(address, phy); 121 netxen_gb_mii_mgmt_phy_addr(address, phy);
125 if (adapter->hw_write_wx(adapter, 122 if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0), address))
126 NETXEN_NIU_GB_MII_MGMT_ADDR(0), address))
127 return -EIO; 123 return -EIO;
128 command = 0; /* turn off any prior activity */ 124 command = 0; /* turn off any prior activity */
129 if (adapter->hw_write_wx(adapter, 125 if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0), command))
130 NETXEN_NIU_GB_MII_MGMT_COMMAND(0), command))
131 return -EIO; 126 return -EIO;
132 /* send read command */ 127 /* send read command */
133 netxen_gb_mii_mgmt_set_read_cycle(command); 128 netxen_gb_mii_mgmt_set_read_cycle(command);
134 if (adapter->hw_write_wx(adapter, 129 if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0), command))
135 NETXEN_NIU_GB_MII_MGMT_COMMAND(0), command))
136 return -EIO; 130 return -EIO;
137 131
138 status = 0; 132 status = 0;
139 do { 133 do {
140 status = adapter->hw_read_wx(adapter, 134 status = NXRD32(adapter, NETXEN_NIU_GB_MII_MGMT_INDICATE(0));
141 NETXEN_NIU_GB_MII_MGMT_INDICATE(0));
142 timeout++; 135 timeout++;
143 } while ((netxen_get_gb_mii_mgmt_busy(status) 136 } while ((netxen_get_gb_mii_mgmt_busy(status)
144 || netxen_get_gb_mii_mgmt_notvalid(status)) 137 || netxen_get_gb_mii_mgmt_notvalid(status))
145 && (timeout++ < NETXEN_NIU_PHY_WAITMAX)); 138 && (timeout++ < NETXEN_NIU_PHY_WAITMAX));
146 139
147 if (timeout < NETXEN_NIU_PHY_WAITMAX) { 140 if (timeout < NETXEN_NIU_PHY_WAITMAX) {
148 *readval = adapter->hw_read_wx(adapter, 141 *readval = NXRD32(adapter, NETXEN_NIU_GB_MII_MGMT_STATUS(0));
149 NETXEN_NIU_GB_MII_MGMT_STATUS(0));
150 result = 0; 142 result = 0;
151 } else 143 } else
152 result = -1; 144 result = -1;
153 145
154 if (restore) 146 if (restore)
155 if (adapter->hw_write_wx(adapter, 147 if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), mac_cfg0))
156 NETXEN_NIU_GB_MAC_CONFIG_0(0), mac_cfg0))
157 return -EIO; 148 return -EIO;
158 phy_unlock(adapter); 149 phy_unlock(adapter);
159 return result; 150 return result;
@@ -189,7 +180,7 @@ int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, long reg,
189 * cannot be in reset 180 * cannot be in reset
190 */ 181 */
191 182
192 mac_cfg0 = adapter->hw_read_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0)); 183 mac_cfg0 = NXRD32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0));
193 if (netxen_gb_get_soft_reset(mac_cfg0)) { 184 if (netxen_gb_get_soft_reset(mac_cfg0)) {
194 __u32 temp; 185 __u32 temp;
195 temp = 0; 186 temp = 0;
@@ -198,32 +189,27 @@ int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, long reg,
198 netxen_gb_tx_reset_mac(temp); 189 netxen_gb_tx_reset_mac(temp);
199 netxen_gb_rx_reset_mac(temp); 190 netxen_gb_rx_reset_mac(temp);
200 191
201 if (adapter->hw_write_wx(adapter, 192 if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), temp))
202 NETXEN_NIU_GB_MAC_CONFIG_0(0), temp))
203 return -EIO; 193 return -EIO;
204 restore = 1; 194 restore = 1;
205 } 195 }
206 196
207 command = 0; /* turn off any prior activity */ 197 command = 0; /* turn off any prior activity */
208 if (adapter->hw_write_wx(adapter, 198 if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0), command))
209 NETXEN_NIU_GB_MII_MGMT_COMMAND(0), command))
210 return -EIO; 199 return -EIO;
211 200
212 address = 0; 201 address = 0;
213 netxen_gb_mii_mgmt_reg_addr(address, reg); 202 netxen_gb_mii_mgmt_reg_addr(address, reg);
214 netxen_gb_mii_mgmt_phy_addr(address, phy); 203 netxen_gb_mii_mgmt_phy_addr(address, phy);
215 if (adapter->hw_write_wx(adapter, 204 if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0), address))
216 NETXEN_NIU_GB_MII_MGMT_ADDR(0), address))
217 return -EIO; 205 return -EIO;
218 206
219 if (adapter->hw_write_wx(adapter, 207 if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_CTRL(0), val))
220 NETXEN_NIU_GB_MII_MGMT_CTRL(0), val))
221 return -EIO; 208 return -EIO;
222 209
223 status = 0; 210 status = 0;
224 do { 211 do {
225 status = adapter->hw_read_wx(adapter, 212 status = NXRD32(adapter, NETXEN_NIU_GB_MII_MGMT_INDICATE(0));
226 NETXEN_NIU_GB_MII_MGMT_INDICATE(0));
227 timeout++; 213 timeout++;
228 } while ((netxen_get_gb_mii_mgmt_busy(status)) 214 } while ((netxen_get_gb_mii_mgmt_busy(status))
229 && (timeout++ < NETXEN_NIU_PHY_WAITMAX)); 215 && (timeout++ < NETXEN_NIU_PHY_WAITMAX));
@@ -235,8 +221,7 @@ int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, long reg,
235 221
236 /* restore the state of port 0 MAC in case we tampered with it */ 222 /* restore the state of port 0 MAC in case we tampered with it */
237 if (restore) 223 if (restore)
238 if (adapter->hw_write_wx(adapter, 224 if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), mac_cfg0))
239 NETXEN_NIU_GB_MAC_CONFIG_0(0), mac_cfg0))
240 return -EIO; 225 return -EIO;
241 226
242 return result; 227 return result;
@@ -244,7 +229,7 @@ int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, long reg,
244 229
245int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter) 230int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter)
246{ 231{
247 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_INT_MASK, 0x3f); 232 NXWR32(adapter, NETXEN_NIU_INT_MASK, 0x3f);
248 return 0; 233 return 0;
249} 234}
250 235
@@ -267,7 +252,7 @@ int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter)
267 252
268int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter) 253int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter)
269{ 254{
270 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_INT_MASK, 0x7f); 255 NXWR32(adapter, NETXEN_NIU_INT_MASK, 0x7f);
271 return 0; 256 return 0;
272} 257}
273 258
@@ -301,30 +286,21 @@ static int netxen_niu_gbe_clear_phy_interrupts(struct netxen_adapter *adapter)
301static void netxen_niu_gbe_set_mii_mode(struct netxen_adapter *adapter, 286static void netxen_niu_gbe_set_mii_mode(struct netxen_adapter *adapter,
302 int port, long enable) 287 int port, long enable)
303{ 288{
304 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_MODE, 0x2); 289 NXWR32(adapter, NETXEN_NIU_MODE, 0x2);
305 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 290 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x80000000);
306 0x80000000); 291 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x0000f0025);
307 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 292 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port), 0xf1ff);
308 0x0000f0025); 293 NXWR32(adapter, NETXEN_NIU_GB0_GMII_MODE + (port << 3), 0);
309 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port), 294 NXWR32(adapter, NETXEN_NIU_GB0_MII_MODE + (port << 3), 1);
310 0xf1ff); 295 NXWR32(adapter, (NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0);
311 netxen_crb_writelit_adapter(adapter, 296 NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7);
312 NETXEN_NIU_GB0_GMII_MODE + (port << 3), 0);
313 netxen_crb_writelit_adapter(adapter,
314 NETXEN_NIU_GB0_MII_MODE + (port << 3), 1);
315 netxen_crb_writelit_adapter(adapter,
316 (NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0);
317 netxen_crb_writelit_adapter(adapter,
318 NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7);
319 297
320 if (enable) { 298 if (enable) {
321 /* 299 /*
322 * Do NOT enable flow control until a suitable solution for 300 * Do NOT enable flow control until a suitable solution for
323 * shutting down pause frames is found. 301 * shutting down pause frames is found.
324 */ 302 */
325 netxen_crb_writelit_adapter(adapter, 303 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x5);
326 NETXEN_NIU_GB_MAC_CONFIG_0(port),
327 0x5);
328 } 304 }
329 305
330 if (netxen_niu_gbe_enable_phy_interrupts(adapter)) 306 if (netxen_niu_gbe_enable_phy_interrupts(adapter))
@@ -339,30 +315,21 @@ static void netxen_niu_gbe_set_mii_mode(struct netxen_adapter *adapter,
339static void netxen_niu_gbe_set_gmii_mode(struct netxen_adapter *adapter, 315static void netxen_niu_gbe_set_gmii_mode(struct netxen_adapter *adapter,
340 int port, long enable) 316 int port, long enable)
341{ 317{
342 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_MODE, 0x2); 318 NXWR32(adapter, NETXEN_NIU_MODE, 0x2);
343 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 319 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x80000000);
344 0x80000000); 320 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x0000f0025);
345 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 321 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port), 0xf2ff);
346 0x0000f0025); 322 NXWR32(adapter, NETXEN_NIU_GB0_MII_MODE + (port << 3), 0);
347 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port), 323 NXWR32(adapter, NETXEN_NIU_GB0_GMII_MODE + (port << 3), 1);
348 0xf2ff); 324 NXWR32(adapter, (NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0);
349 netxen_crb_writelit_adapter(adapter, 325 NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7);
350 NETXEN_NIU_GB0_MII_MODE + (port << 3), 0);
351 netxen_crb_writelit_adapter(adapter,
352 NETXEN_NIU_GB0_GMII_MODE + (port << 3), 1);
353 netxen_crb_writelit_adapter(adapter,
354 (NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0);
355 netxen_crb_writelit_adapter(adapter,
356 NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7);
357 326
358 if (enable) { 327 if (enable) {
359 /* 328 /*
360 * Do NOT enable flow control until a suitable solution for 329 * Do NOT enable flow control until a suitable solution for
361 * shutting down pause frames is found. 330 * shutting down pause frames is found.
362 */ 331 */
363 netxen_crb_writelit_adapter(adapter, 332 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x5);
364 NETXEN_NIU_GB_MAC_CONFIG_0(port),
365 0x5);
366 } 333 }
367 334
368 if (netxen_niu_gbe_enable_phy_interrupts(adapter)) 335 if (netxen_niu_gbe_enable_phy_interrupts(adapter))
@@ -402,17 +369,12 @@ int netxen_niu_gbe_init_port(struct netxen_adapter *adapter, int port)
402 * plugged in. 369 * plugged in.
403 */ 370 */
404 371
405 netxen_crb_writelit_adapter(adapter, 372 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
406 NETXEN_NIU_GB_MAC_CONFIG_0
407 (port),
408 NETXEN_GB_MAC_SOFT_RESET); 373 NETXEN_GB_MAC_SOFT_RESET);
409 netxen_crb_writelit_adapter(adapter, 374 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
410 NETXEN_NIU_GB_MAC_CONFIG_0 375 NETXEN_GB_MAC_RESET_PROT_BLK |
411 (port), 376 NETXEN_GB_MAC_ENABLE_TX_RX |
412 NETXEN_GB_MAC_RESET_PROT_BLK 377 NETXEN_GB_MAC_PAUSED_FRMS);
413 | NETXEN_GB_MAC_ENABLE_TX_RX
414 |
415 NETXEN_GB_MAC_PAUSED_FRMS);
416 if (netxen_niu_gbe_clear_phy_interrupts(adapter)) 378 if (netxen_niu_gbe_clear_phy_interrupts(adapter))
417 printk(KERN_ERR 379 printk(KERN_ERR
418 "ERROR clearing PHY interrupts\n"); 380 "ERROR clearing PHY interrupts\n");
@@ -433,10 +395,8 @@ int netxen_niu_gbe_init_port(struct netxen_adapter *adapter, int port)
433int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port) 395int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
434{ 396{
435 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) { 397 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
436 netxen_crb_writelit_adapter(adapter, 398 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447);
437 NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447); 399 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5);
438 netxen_crb_writelit_adapter(adapter,
439 NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5);
440 } 400 }
441 401
442 return 0; 402 return 0;
@@ -459,10 +419,8 @@ static int netxen_niu_macaddr_get(struct netxen_adapter *adapter,
459 if ((phy < 0) || (phy > 3)) 419 if ((phy < 0) || (phy > 3))
460 return -EINVAL; 420 return -EINVAL;
461 421
462 stationhigh = adapter->hw_read_wx(adapter, 422 stationhigh = NXRD32(adapter, NETXEN_NIU_GB_STATION_ADDR_0(phy));
463 NETXEN_NIU_GB_STATION_ADDR_0(phy)); 423 stationlow = NXRD32(adapter, NETXEN_NIU_GB_STATION_ADDR_1(phy));
464 stationlow = adapter->hw_read_wx(adapter,
465 NETXEN_NIU_GB_STATION_ADDR_1(phy));
466 ((__le32 *)val)[1] = cpu_to_le32(stationhigh); 424 ((__le32 *)val)[1] = cpu_to_le32(stationhigh);
467 ((__le32 *)val)[0] = cpu_to_le32(stationlow); 425 ((__le32 *)val)[0] = cpu_to_le32(stationlow);
468 426
@@ -491,14 +449,12 @@ int netxen_niu_macaddr_set(struct netxen_adapter *adapter,
491 temp[0] = temp[1] = 0; 449 temp[0] = temp[1] = 0;
492 memcpy(temp + 2, addr, 2); 450 memcpy(temp + 2, addr, 2);
493 val = le32_to_cpu(*(__le32 *)temp); 451 val = le32_to_cpu(*(__le32 *)temp);
494 if (adapter->hw_write_wx(adapter, 452 if (NXWR32(adapter, NETXEN_NIU_GB_STATION_ADDR_1(phy), val))
495 NETXEN_NIU_GB_STATION_ADDR_1(phy), val))
496 return -EIO; 453 return -EIO;
497 454
498 memcpy(temp, ((u8 *) addr) + 2, sizeof(__le32)); 455 memcpy(temp, ((u8 *) addr) + 2, sizeof(__le32));
499 val = le32_to_cpu(*(__le32 *)temp); 456 val = le32_to_cpu(*(__le32 *)temp);
500 if (adapter->hw_write_wx(adapter, 457 if (NXWR32(adapter, NETXEN_NIU_GB_STATION_ADDR_0(phy), val))
501 NETXEN_NIU_GB_STATION_ADDR_0(phy), val))
502 return -2; 458 return -2;
503 459
504 netxen_niu_macaddr_get(adapter, 460 netxen_niu_macaddr_get(adapter,
@@ -529,8 +485,7 @@ int netxen_niu_disable_gbe_port(struct netxen_adapter *adapter)
529 return -EINVAL; 485 return -EINVAL;
530 mac_cfg0 = 0; 486 mac_cfg0 = 0;
531 netxen_gb_soft_reset(mac_cfg0); 487 netxen_gb_soft_reset(mac_cfg0);
532 if (adapter->hw_write_wx(adapter, 488 if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), mac_cfg0))
533 NETXEN_NIU_GB_MAC_CONFIG_0(port), mac_cfg0))
534 return -EIO; 489 return -EIO;
535 return 0; 490 return 0;
536} 491}
@@ -548,8 +503,8 @@ int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
548 return -EINVAL; 503 return -EINVAL;
549 504
550 mac_cfg = 0; 505 mac_cfg = 0;
551 if (adapter->hw_write_wx(adapter, 506 if (NXWR32(adapter,
552 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg)) 507 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg))
553 return -EIO; 508 return -EIO;
554 return 0; 509 return 0;
555} 510}
@@ -565,7 +520,7 @@ int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter,
565 return -EINVAL; 520 return -EINVAL;
566 521
567 /* save previous contents */ 522 /* save previous contents */
568 reg = adapter->hw_read_wx(adapter, NETXEN_NIU_GB_DROP_WRONGADDR); 523 reg = NXRD32(adapter, NETXEN_NIU_GB_DROP_WRONGADDR);
569 if (mode == NETXEN_NIU_PROMISC_MODE) { 524 if (mode == NETXEN_NIU_PROMISC_MODE) {
570 switch (port) { 525 switch (port) {
571 case 0: 526 case 0:
@@ -601,7 +556,7 @@ int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter,
601 return -EIO; 556 return -EIO;
602 } 557 }
603 } 558 }
604 if (adapter->hw_write_wx(adapter, NETXEN_NIU_GB_DROP_WRONGADDR, reg)) 559 if (NXWR32(adapter, NETXEN_NIU_GB_DROP_WRONGADDR, reg))
605 return -EIO; 560 return -EIO;
606 return 0; 561 return 0;
607} 562}
@@ -628,28 +583,24 @@ int netxen_niu_xg_macaddr_set(struct netxen_adapter *adapter,
628 case 0: 583 case 0:
629 memcpy(temp + 2, addr, 2); 584 memcpy(temp + 2, addr, 2);
630 val = le32_to_cpu(*(__le32 *)temp); 585 val = le32_to_cpu(*(__le32 *)temp);
631 if (adapter->hw_write_wx(adapter, 586 if (NXWR32(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_1, val))
632 NETXEN_NIU_XGE_STATION_ADDR_0_1, val))
633 return -EIO; 587 return -EIO;
634 588
635 memcpy(&temp, ((u8 *) addr) + 2, sizeof(__le32)); 589 memcpy(&temp, ((u8 *) addr) + 2, sizeof(__le32));
636 val = le32_to_cpu(*(__le32 *)temp); 590 val = le32_to_cpu(*(__le32 *)temp);
637 if (adapter->hw_write_wx(adapter, 591 if (NXWR32(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_HI, val))
638 NETXEN_NIU_XGE_STATION_ADDR_0_HI, val))
639 return -EIO; 592 return -EIO;
640 break; 593 break;
641 594
642 case 1: 595 case 1:
643 memcpy(temp + 2, addr, 2); 596 memcpy(temp + 2, addr, 2);
644 val = le32_to_cpu(*(__le32 *)temp); 597 val = le32_to_cpu(*(__le32 *)temp);
645 if (adapter->hw_write_wx(adapter, 598 if (NXWR32(adapter, NETXEN_NIU_XG1_STATION_ADDR_0_1, val))
646 NETXEN_NIU_XG1_STATION_ADDR_0_1, val))
647 return -EIO; 599 return -EIO;
648 600
649 memcpy(&temp, ((u8 *) addr) + 2, sizeof(__le32)); 601 memcpy(&temp, ((u8 *) addr) + 2, sizeof(__le32));
650 val = le32_to_cpu(*(__le32 *)temp); 602 val = le32_to_cpu(*(__le32 *)temp);
651 if (adapter->hw_write_wx(adapter, 603 if (NXWR32(adapter, NETXEN_NIU_XG1_STATION_ADDR_0_HI, val))
652 NETXEN_NIU_XG1_STATION_ADDR_0_HI, val))
653 return -EIO; 604 return -EIO;
654 break; 605 break;
655 606
@@ -670,8 +621,7 @@ int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter,
670 if (port > NETXEN_NIU_MAX_XG_PORTS) 621 if (port > NETXEN_NIU_MAX_XG_PORTS)
671 return -EINVAL; 622 return -EINVAL;
672 623
673 reg = adapter->hw_read_wx(adapter, 624 reg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
674 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
675 if (mode == NETXEN_NIU_PROMISC_MODE) 625 if (mode == NETXEN_NIU_PROMISC_MODE)
676 reg = (reg | 0x2000UL); 626 reg = (reg | 0x2000UL);
677 else 627 else
@@ -682,8 +632,7 @@ int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter,
682 else 632 else
683 reg = (reg & ~0x1000UL); 633 reg = (reg & ~0x1000UL);
684 634
685 netxen_crb_writelit_adapter(adapter, 635 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
686 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
687 636
688 return 0; 637 return 0;
689} 638}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-02 07:20:33 -0500