aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net
diff options
context:
space:
mode:
authorAuke Kok <auke-jan.h.kok@intel.com>2006-06-27 12:08:22 -0400
committerAuke Kok <juke-jan.h.kok@intel.com>2006-06-27 12:08:22 -0400
commitcd94dd0b648ceb64ca5e41d9ccfa99c1e30e92ef (patch)
tree48144ae7c119c5cc7e61d42c670609540c3c7e9d /drivers/net
parentd37ea5d56293b7a883d2a993df5d8b9fb660ed3b (diff)
e1000: integrate ich8 support into driver
This hooks up the ich8 structure into the driver itself. Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/e1000/e1000.h1
-rw-r--r--drivers/net/e1000/e1000_ethtool.c80
-rw-r--r--drivers/net/e1000/e1000_hw.c654
-rw-r--r--drivers/net/e1000/e1000_main.c120
4 files changed, 725 insertions, 130 deletions
diff --git a/drivers/net/e1000/e1000.h b/drivers/net/e1000/e1000.h
index dbdaa332cac6..323a2683417f 100644
--- a/drivers/net/e1000/e1000.h
+++ b/drivers/net/e1000/e1000.h
@@ -143,6 +143,7 @@ struct e1000_adapter;
143 143
144#define AUTO_ALL_MODES 0 144#define AUTO_ALL_MODES 0
145#define E1000_EEPROM_82544_APM 0x0004 145#define E1000_EEPROM_82544_APM 0x0004
146#define E1000_EEPROM_ICH8_APME 0x0004
146#define E1000_EEPROM_APME 0x0400 147#define E1000_EEPROM_APME 0x0400
147 148
148#ifndef E1000_MASTER_SLAVE 149#ifndef E1000_MASTER_SLAVE
diff --git a/drivers/net/e1000/e1000_ethtool.c b/drivers/net/e1000/e1000_ethtool.c
index 060915532923..3a0b847fac31 100644
--- a/drivers/net/e1000/e1000_ethtool.c
+++ b/drivers/net/e1000/e1000_ethtool.c
@@ -109,7 +109,8 @@ e1000_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
109 SUPPORTED_1000baseT_Full| 109 SUPPORTED_1000baseT_Full|
110 SUPPORTED_Autoneg | 110 SUPPORTED_Autoneg |
111 SUPPORTED_TP); 111 SUPPORTED_TP);
112 112 if (hw->phy_type == e1000_phy_ife)
113 ecmd->supported &= ~SUPPORTED_1000baseT_Full;
113 ecmd->advertising = ADVERTISED_TP; 114 ecmd->advertising = ADVERTISED_TP;
114 115
115 if (hw->autoneg == 1) { 116 if (hw->autoneg == 1) {
@@ -573,6 +574,7 @@ e1000_get_drvinfo(struct net_device *netdev,
573 case e1000_82572: 574 case e1000_82572:
574 case e1000_82573: 575 case e1000_82573:
575 case e1000_80003es2lan: 576 case e1000_80003es2lan:
577 case e1000_ich8lan:
576 sprintf(firmware_version, "%d.%d-%d", 578 sprintf(firmware_version, "%d.%d-%d",
577 (eeprom_data & 0xF000) >> 12, 579 (eeprom_data & 0xF000) >> 12,
578 (eeprom_data & 0x0FF0) >> 4, 580 (eeprom_data & 0x0FF0) >> 4,
@@ -757,6 +759,7 @@ e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data)
757 toggle = 0x7FFFF3FF; 759 toggle = 0x7FFFF3FF;
758 break; 760 break;
759 case e1000_82573: 761 case e1000_82573:
762 case e1000_ich8lan:
760 toggle = 0x7FFFF033; 763 toggle = 0x7FFFF033;
761 break; 764 break;
762 default: 765 default:
@@ -776,11 +779,12 @@ e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data)
776 } 779 }
777 /* restore previous status */ 780 /* restore previous status */
778 E1000_WRITE_REG(&adapter->hw, STATUS, before); 781 E1000_WRITE_REG(&adapter->hw, STATUS, before);
779 782 if (adapter->hw.mac_type != e1000_ich8lan) {
780 REG_PATTERN_TEST(FCAL, 0xFFFFFFFF, 0xFFFFFFFF); 783 REG_PATTERN_TEST(FCAL, 0xFFFFFFFF, 0xFFFFFFFF);
781 REG_PATTERN_TEST(FCAH, 0x0000FFFF, 0xFFFFFFFF); 784 REG_PATTERN_TEST(FCAH, 0x0000FFFF, 0xFFFFFFFF);
782 REG_PATTERN_TEST(FCT, 0x0000FFFF, 0xFFFFFFFF); 785 REG_PATTERN_TEST(FCT, 0x0000FFFF, 0xFFFFFFFF);
783 REG_PATTERN_TEST(VET, 0x0000FFFF, 0xFFFFFFFF); 786 REG_PATTERN_TEST(VET, 0x0000FFFF, 0xFFFFFFFF);
787 }
784 REG_PATTERN_TEST(RDTR, 0x0000FFFF, 0xFFFFFFFF); 788 REG_PATTERN_TEST(RDTR, 0x0000FFFF, 0xFFFFFFFF);
785 REG_PATTERN_TEST(RDBAH, 0xFFFFFFFF, 0xFFFFFFFF); 789 REG_PATTERN_TEST(RDBAH, 0xFFFFFFFF, 0xFFFFFFFF);
786 REG_PATTERN_TEST(RDLEN, 0x000FFF80, 0x000FFFFF); 790 REG_PATTERN_TEST(RDLEN, 0x000FFF80, 0x000FFFFF);
@@ -793,20 +797,22 @@ e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data)
793 REG_PATTERN_TEST(TDLEN, 0x000FFF80, 0x000FFFFF); 797 REG_PATTERN_TEST(TDLEN, 0x000FFF80, 0x000FFFFF);
794 798
795 REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x00000000); 799 REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x00000000);
796 REG_SET_AND_CHECK(RCTL, 0x06DFB3FE, 0x003FFFFB); 800 before = (adapter->hw.mac_type == e1000_ich8lan ?
801 0x06C3B33E : 0x06DFB3FE);
802 REG_SET_AND_CHECK(RCTL, before, 0x003FFFFB);
797 REG_SET_AND_CHECK(TCTL, 0xFFFFFFFF, 0x00000000); 803 REG_SET_AND_CHECK(TCTL, 0xFFFFFFFF, 0x00000000);
798 804
799 if (adapter->hw.mac_type >= e1000_82543) { 805 if (adapter->hw.mac_type >= e1000_82543) {
800 806
801 REG_SET_AND_CHECK(RCTL, 0x06DFB3FE, 0xFFFFFFFF); 807 REG_SET_AND_CHECK(RCTL, before, 0xFFFFFFFF);
802 REG_PATTERN_TEST(RDBAL, 0xFFFFFFF0, 0xFFFFFFFF); 808 REG_PATTERN_TEST(RDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
803 REG_PATTERN_TEST(TXCW, 0xC000FFFF, 0x0000FFFF); 809 if (adapter->hw.mac_type != e1000_ich8lan)
810 REG_PATTERN_TEST(TXCW, 0xC000FFFF, 0x0000FFFF);
804 REG_PATTERN_TEST(TDBAL, 0xFFFFFFF0, 0xFFFFFFFF); 811 REG_PATTERN_TEST(TDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
805 REG_PATTERN_TEST(TIDV, 0x0000FFFF, 0x0000FFFF); 812 REG_PATTERN_TEST(TIDV, 0x0000FFFF, 0x0000FFFF);
806 813 value = (adapter->hw.mac_type == e1000_ich8lan ?
807 for (i = 0; i < E1000_RAR_ENTRIES; i++) { 814 E1000_RAR_ENTRIES_ICH8LAN : E1000_RAR_ENTRIES);
808 REG_PATTERN_TEST(RA + ((i << 1) << 2), 0xFFFFFFFF, 815 for (i = 0; i < value; i++) {
809 0xFFFFFFFF);
810 REG_PATTERN_TEST(RA + (((i << 1) + 1) << 2), 0x8003FFFF, 816 REG_PATTERN_TEST(RA + (((i << 1) + 1) << 2), 0x8003FFFF,
811 0xFFFFFFFF); 817 0xFFFFFFFF);
812 } 818 }
@@ -820,7 +826,9 @@ e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data)
820 826
821 } 827 }
822 828
823 for (i = 0; i < E1000_MC_TBL_SIZE; i++) 829 value = (adapter->hw.mac_type == e1000_ich8lan ?
830 E1000_MC_TBL_SIZE_ICH8LAN : E1000_MC_TBL_SIZE);
831 for (i = 0; i < value; i++)
824 REG_PATTERN_TEST(MTA + (i << 2), 0xFFFFFFFF, 0xFFFFFFFF); 832 REG_PATTERN_TEST(MTA + (i << 2), 0xFFFFFFFF, 0xFFFFFFFF);
825 833
826 *data = 0; 834 *data = 0;
@@ -892,6 +900,8 @@ e1000_intr_test(struct e1000_adapter *adapter, uint64_t *data)
892 /* Test each interrupt */ 900 /* Test each interrupt */
893 for (; i < 10; i++) { 901 for (; i < 10; i++) {
894 902
903 if (adapter->hw.mac_type == e1000_ich8lan && i == 8)
904 continue;
895 /* Interrupt to test */ 905 /* Interrupt to test */
896 mask = 1 << i; 906 mask = 1 << i;
897 907
@@ -1251,16 +1261,31 @@ e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
1251 GG82563_PHY_KMRN_MODE_CTRL, 1261 GG82563_PHY_KMRN_MODE_CTRL,
1252 0x1CC); 1262 0x1CC);
1253 } 1263 }
1254 /* force 1000, set loopback */
1255 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x4140);
1256 1264
1257 /* Now set up the MAC to the same speed/duplex as the PHY. */
1258 ctrl_reg = E1000_READ_REG(&adapter->hw, CTRL); 1265 ctrl_reg = E1000_READ_REG(&adapter->hw, CTRL);
1259 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 1266
1260 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 1267 if (adapter->hw.phy_type == e1000_phy_ife) {
1261 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 1268 /* force 100, set loopback */
1262 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */ 1269 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x6100);
1263 E1000_CTRL_FD); /* Force Duplex to FULL */ 1270
1271 /* Now set up the MAC to the same speed/duplex as the PHY. */
1272 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1273 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1274 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1275 E1000_CTRL_SPD_100 |/* Force Speed to 100 */
1276 E1000_CTRL_FD); /* Force Duplex to FULL */
1277 } else {
1278 /* force 1000, set loopback */
1279 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x4140);
1280
1281 /* Now set up the MAC to the same speed/duplex as the PHY. */
1282 ctrl_reg = E1000_READ_REG(&adapter->hw, CTRL);
1283 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1284 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1285 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1286 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1287 E1000_CTRL_FD); /* Force Duplex to FULL */
1288 }
1264 1289
1265 if (adapter->hw.media_type == e1000_media_type_copper && 1290 if (adapter->hw.media_type == e1000_media_type_copper &&
1266 adapter->hw.phy_type == e1000_phy_m88) { 1291 adapter->hw.phy_type == e1000_phy_m88) {
@@ -1320,6 +1345,7 @@ e1000_set_phy_loopback(struct e1000_adapter *adapter)
1320 case e1000_82572: 1345 case e1000_82572:
1321 case e1000_82573: 1346 case e1000_82573:
1322 case e1000_80003es2lan: 1347 case e1000_80003es2lan:
1348 case e1000_ich8lan:
1323 return e1000_integrated_phy_loopback(adapter); 1349 return e1000_integrated_phy_loopback(adapter);
1324 break; 1350 break;
1325 1351
@@ -1786,6 +1812,16 @@ e1000_phys_id(struct net_device *netdev, uint32_t data)
1786 mod_timer(&adapter->blink_timer, jiffies); 1812 mod_timer(&adapter->blink_timer, jiffies);
1787 msleep_interruptible(data * 1000); 1813 msleep_interruptible(data * 1000);
1788 del_timer_sync(&adapter->blink_timer); 1814 del_timer_sync(&adapter->blink_timer);
1815 } else if (adapter->hw.phy_type == e1000_phy_ife) {
1816 if (!adapter->blink_timer.function) {
1817 init_timer(&adapter->blink_timer);
1818 adapter->blink_timer.function = e1000_led_blink_callback;
1819 adapter->blink_timer.data = (unsigned long) adapter;
1820 }
1821 mod_timer(&adapter->blink_timer, jiffies);
1822 msleep_interruptible(data * 1000);
1823 del_timer_sync(&adapter->blink_timer);
1824 e1000_write_phy_reg(&(adapter->hw), IFE_PHY_SPECIAL_CONTROL_LED, 0);
1789 } else { 1825 } else {
1790 e1000_blink_led_start(&adapter->hw); 1826 e1000_blink_led_start(&adapter->hw);
1791 msleep_interruptible(data * 1000); 1827 msleep_interruptible(data * 1000);
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index a3f5ccdfafc6..583518ae49ce 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -101,7 +101,8 @@ static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset,
101 101
102#define E1000_WRITE_REG_IO(a, reg, val) \ 102#define E1000_WRITE_REG_IO(a, reg, val) \
103 e1000_write_reg_io((a), E1000_##reg, val) 103 e1000_write_reg_io((a), E1000_##reg, val)
104static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw); 104static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
105 uint16_t duplex);
105static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw); 106static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
106 107
107/* IGP cable length table */ 108/* IGP cable length table */
@@ -156,6 +157,14 @@ e1000_set_phy_type(struct e1000_hw *hw)
156 hw->phy_type = e1000_phy_igp; 157 hw->phy_type = e1000_phy_igp;
157 break; 158 break;
158 } 159 }
160 case IGP03E1000_E_PHY_ID:
161 hw->phy_type = e1000_phy_igp_3;
162 break;
163 case IFE_E_PHY_ID:
164 case IFE_PLUS_E_PHY_ID:
165 case IFE_C_E_PHY_ID:
166 hw->phy_type = e1000_phy_ife;
167 break;
159 case GG82563_E_PHY_ID: 168 case GG82563_E_PHY_ID:
160 if (hw->mac_type == e1000_80003es2lan) { 169 if (hw->mac_type == e1000_80003es2lan) {
161 hw->phy_type = e1000_phy_gg82563; 170 hw->phy_type = e1000_phy_gg82563;
@@ -332,6 +341,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
332 break; 341 break;
333 case E1000_DEV_ID_82541EI: 342 case E1000_DEV_ID_82541EI:
334 case E1000_DEV_ID_82541EI_MOBILE: 343 case E1000_DEV_ID_82541EI_MOBILE:
344 case E1000_DEV_ID_82541ER_LOM:
335 hw->mac_type = e1000_82541; 345 hw->mac_type = e1000_82541;
336 break; 346 break;
337 case E1000_DEV_ID_82541ER: 347 case E1000_DEV_ID_82541ER:
@@ -341,6 +351,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
341 hw->mac_type = e1000_82541_rev_2; 351 hw->mac_type = e1000_82541_rev_2;
342 break; 352 break;
343 case E1000_DEV_ID_82547EI: 353 case E1000_DEV_ID_82547EI:
354 case E1000_DEV_ID_82547EI_MOBILE:
344 hw->mac_type = e1000_82547; 355 hw->mac_type = e1000_82547;
345 break; 356 break;
346 case E1000_DEV_ID_82547GI: 357 case E1000_DEV_ID_82547GI:
@@ -354,6 +365,7 @@ e1000_set_mac_type(struct e1000_hw *hw)
354 case E1000_DEV_ID_82572EI_COPPER: 365 case E1000_DEV_ID_82572EI_COPPER:
355 case E1000_DEV_ID_82572EI_FIBER: 366 case E1000_DEV_ID_82572EI_FIBER:
356 case E1000_DEV_ID_82572EI_SERDES: 367 case E1000_DEV_ID_82572EI_SERDES:
368 case E1000_DEV_ID_82572EI:
357 hw->mac_type = e1000_82572; 369 hw->mac_type = e1000_82572;
358 break; 370 break;
359 case E1000_DEV_ID_82573E: 371 case E1000_DEV_ID_82573E:
@@ -361,16 +373,29 @@ e1000_set_mac_type(struct e1000_hw *hw)
361 case E1000_DEV_ID_82573L: 373 case E1000_DEV_ID_82573L:
362 hw->mac_type = e1000_82573; 374 hw->mac_type = e1000_82573;
363 break; 375 break;
376 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
377 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
364 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 378 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
365 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 379 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
366 hw->mac_type = e1000_80003es2lan; 380 hw->mac_type = e1000_80003es2lan;
367 break; 381 break;
382 case E1000_DEV_ID_ICH8_IGP_M_AMT:
383 case E1000_DEV_ID_ICH8_IGP_AMT:
384 case E1000_DEV_ID_ICH8_IGP_C:
385 case E1000_DEV_ID_ICH8_IFE:
386 case E1000_DEV_ID_ICH8_IGP_M:
387 hw->mac_type = e1000_ich8lan;
388 break;
368 default: 389 default:
369 /* Should never have loaded on this device */ 390 /* Should never have loaded on this device */
370 return -E1000_ERR_MAC_TYPE; 391 return -E1000_ERR_MAC_TYPE;
371 } 392 }
372 393
373 switch(hw->mac_type) { 394 switch(hw->mac_type) {
395 case e1000_ich8lan:
396 hw->swfwhw_semaphore_present = TRUE;
397 hw->asf_firmware_present = TRUE;
398 break;
374 case e1000_80003es2lan: 399 case e1000_80003es2lan:
375 hw->swfw_sync_present = TRUE; 400 hw->swfw_sync_present = TRUE;
376 /* fall through */ 401 /* fall through */
@@ -423,6 +448,7 @@ e1000_set_media_type(struct e1000_hw *hw)
423 case e1000_82542_rev2_1: 448 case e1000_82542_rev2_1:
424 hw->media_type = e1000_media_type_fiber; 449 hw->media_type = e1000_media_type_fiber;
425 break; 450 break;
451 case e1000_ich8lan:
426 case e1000_82573: 452 case e1000_82573:
427 /* The STATUS_TBIMODE bit is reserved or reused for the this 453 /* The STATUS_TBIMODE bit is reserved or reused for the this
428 * device. 454 * device.
@@ -527,6 +553,14 @@ e1000_reset_hw(struct e1000_hw *hw)
527 } while(timeout); 553 } while(timeout);
528 } 554 }
529 555
556 /* Workaround for ICH8 bit corruption issue in FIFO memory */
557 if (hw->mac_type == e1000_ich8lan) {
558 /* Set Tx and Rx buffer allocation to 8k apiece. */
559 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
560 /* Set Packet Buffer Size to 16k. */
561 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
562 }
563
530 /* Issue a global reset to the MAC. This will reset the chip's 564 /* Issue a global reset to the MAC. This will reset the chip's
531 * transmit, receive, DMA, and link units. It will not effect 565 * transmit, receive, DMA, and link units. It will not effect
532 * the current PCI configuration. The global reset bit is self- 566 * the current PCI configuration. The global reset bit is self-
@@ -550,6 +584,20 @@ e1000_reset_hw(struct e1000_hw *hw)
550 /* Reset is performed on a shadow of the control register */ 584 /* Reset is performed on a shadow of the control register */
551 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); 585 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
552 break; 586 break;
587 case e1000_ich8lan:
588 if (!hw->phy_reset_disable &&
589 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
590 /* e1000_ich8lan PHY HW reset requires MAC CORE reset
591 * at the same time to make sure the interface between
592 * MAC and the external PHY is reset.
593 */
594 ctrl |= E1000_CTRL_PHY_RST;
595 }
596
597 e1000_get_software_flag(hw);
598 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
599 msec_delay(5);
600 break;
553 default: 601 default:
554 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 602 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
555 break; 603 break;
@@ -591,6 +639,7 @@ e1000_reset_hw(struct e1000_hw *hw)
591 /* fall through */ 639 /* fall through */
592 case e1000_82571: 640 case e1000_82571:
593 case e1000_82572: 641 case e1000_82572:
642 case e1000_ich8lan:
594 case e1000_80003es2lan: 643 case e1000_80003es2lan:
595 ret_val = e1000_get_auto_rd_done(hw); 644 ret_val = e1000_get_auto_rd_done(hw);
596 if(ret_val) 645 if(ret_val)
@@ -633,6 +682,12 @@ e1000_reset_hw(struct e1000_hw *hw)
633 e1000_pci_set_mwi(hw); 682 e1000_pci_set_mwi(hw);
634 } 683 }
635 684
685 if (hw->mac_type == e1000_ich8lan) {
686 uint32_t kab = E1000_READ_REG(hw, KABGTXD);
687 kab |= E1000_KABGTXD_BGSQLBIAS;
688 E1000_WRITE_REG(hw, KABGTXD, kab);
689 }
690
636 return E1000_SUCCESS; 691 return E1000_SUCCESS;
637} 692}
638 693
@@ -675,9 +730,12 @@ e1000_init_hw(struct e1000_hw *hw)
675 730
676 /* Disabling VLAN filtering. */ 731 /* Disabling VLAN filtering. */
677 DEBUGOUT("Initializing the IEEE VLAN\n"); 732 DEBUGOUT("Initializing the IEEE VLAN\n");
678 if (hw->mac_type < e1000_82545_rev_3) 733 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
679 E1000_WRITE_REG(hw, VET, 0); 734 if (hw->mac_type != e1000_ich8lan) {
680 e1000_clear_vfta(hw); 735 if (hw->mac_type < e1000_82545_rev_3)
736 E1000_WRITE_REG(hw, VET, 0);
737 e1000_clear_vfta(hw);
738 }
681 739
682 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 740 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
683 if(hw->mac_type == e1000_82542_rev2_0) { 741 if(hw->mac_type == e1000_82542_rev2_0) {
@@ -705,6 +763,8 @@ e1000_init_hw(struct e1000_hw *hw)
705 /* Zero out the Multicast HASH table */ 763 /* Zero out the Multicast HASH table */
706 DEBUGOUT("Zeroing the MTA\n"); 764 DEBUGOUT("Zeroing the MTA\n");
707 mta_size = E1000_MC_TBL_SIZE; 765 mta_size = E1000_MC_TBL_SIZE;
766 if (hw->mac_type == e1000_ich8lan)
767 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
708 for(i = 0; i < mta_size; i++) { 768 for(i = 0; i < mta_size; i++) {
709 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 769 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
710 /* use write flush to prevent Memory Write Block (MWB) from 770 /* use write flush to prevent Memory Write Block (MWB) from
@@ -748,6 +808,10 @@ e1000_init_hw(struct e1000_hw *hw)
748 break; 808 break;
749 } 809 }
750 810
811 /* More time needed for PHY to initialize */
812 if (hw->mac_type == e1000_ich8lan)
813 msec_delay(15);
814
751 /* Call a subroutine to configure the link and setup flow control. */ 815 /* Call a subroutine to configure the link and setup flow control. */
752 ret_val = e1000_setup_link(hw); 816 ret_val = e1000_setup_link(hw);
753 817
@@ -761,6 +825,7 @@ e1000_init_hw(struct e1000_hw *hw)
761 case e1000_82571: 825 case e1000_82571:
762 case e1000_82572: 826 case e1000_82572:
763 case e1000_82573: 827 case e1000_82573:
828 case e1000_ich8lan:
764 case e1000_80003es2lan: 829 case e1000_80003es2lan:
765 ctrl |= E1000_TXDCTL_COUNT_DESC; 830 ctrl |= E1000_TXDCTL_COUNT_DESC;
766 break; 831 break;
@@ -799,6 +864,7 @@ e1000_init_hw(struct e1000_hw *hw)
799 /* Fall through */ 864 /* Fall through */
800 case e1000_82571: 865 case e1000_82571:
801 case e1000_82572: 866 case e1000_82572:
867 case e1000_ich8lan:
802 ctrl = E1000_READ_REG(hw, TXDCTL1); 868 ctrl = E1000_READ_REG(hw, TXDCTL1);
803 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 869 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
804 if(hw->mac_type >= e1000_82571) 870 if(hw->mac_type >= e1000_82571)
@@ -822,6 +888,11 @@ e1000_init_hw(struct e1000_hw *hw)
822 */ 888 */
823 e1000_clear_hw_cntrs(hw); 889 e1000_clear_hw_cntrs(hw);
824 890
891 /* ICH8 No-snoop bits are opposite polarity.
892 * Set to snoop by default after reset. */
893 if (hw->mac_type == e1000_ich8lan)
894 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
895
825 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 896 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
826 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 897 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
827 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 898 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
@@ -909,6 +980,7 @@ e1000_setup_link(struct e1000_hw *hw)
909 */ 980 */
910 if (hw->fc == e1000_fc_default) { 981 if (hw->fc == e1000_fc_default) {
911 switch (hw->mac_type) { 982 switch (hw->mac_type) {
983 case e1000_ich8lan:
912 case e1000_82573: 984 case e1000_82573:
913 hw->fc = e1000_fc_full; 985 hw->fc = e1000_fc_full;
914 break; 986 break;
@@ -975,9 +1047,12 @@ e1000_setup_link(struct e1000_hw *hw)
975 */ 1047 */
976 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 1048 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
977 1049
978 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1050 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
979 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1051 if (hw->mac_type != e1000_ich8lan) {
980 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1052 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1053 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1054 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1055 }
981 1056
982 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 1057 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
983 1058
@@ -1241,12 +1316,13 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw)
1241 1316
1242 /* Wait 10ms for MAC to configure PHY from eeprom settings */ 1317 /* Wait 10ms for MAC to configure PHY from eeprom settings */
1243 msec_delay(15); 1318 msec_delay(15);
1244 1319 if (hw->mac_type != e1000_ich8lan) {
1245 /* Configure activity LED after PHY reset */ 1320 /* Configure activity LED after PHY reset */
1246 led_ctrl = E1000_READ_REG(hw, LEDCTL); 1321 led_ctrl = E1000_READ_REG(hw, LEDCTL);
1247 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1322 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1248 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1323 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1249 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 1324 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1325 }
1250 1326
1251 /* disable lplu d3 during driver init */ 1327 /* disable lplu d3 during driver init */
1252 ret_val = e1000_set_d3_lplu_state(hw, FALSE); 1328 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
@@ -1482,8 +1558,7 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1482 if (ret_val) 1558 if (ret_val)
1483 return ret_val; 1559 return ret_val;
1484 1560
1485 /* Enable Pass False Carrier on the PHY */ 1561 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1486 phy_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1487 1562
1488 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1563 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1489 phy_data); 1564 phy_data);
@@ -1636,6 +1711,10 @@ e1000_copper_link_autoneg(struct e1000_hw *hw)
1636 if(hw->autoneg_advertised == 0) 1711 if(hw->autoneg_advertised == 0)
1637 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 1712 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1638 1713
1714 /* IFE phy only supports 10/100 */
1715 if (hw->phy_type == e1000_phy_ife)
1716 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1717
1639 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1718 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1640 ret_val = e1000_phy_setup_autoneg(hw); 1719 ret_val = e1000_phy_setup_autoneg(hw);
1641 if(ret_val) { 1720 if(ret_val) {
@@ -1733,6 +1812,26 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1733 1812
1734 DEBUGFUNC("e1000_setup_copper_link"); 1813 DEBUGFUNC("e1000_setup_copper_link");
1735 1814
1815 switch (hw->mac_type) {
1816 case e1000_80003es2lan:
1817 case e1000_ich8lan:
1818 /* Set the mac to wait the maximum time between each
1819 * iteration and increase the max iterations when
1820 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
1821 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1822 if (ret_val)
1823 return ret_val;
1824 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
1825 if (ret_val)
1826 return ret_val;
1827 reg_data |= 0x3F;
1828 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1829 if (ret_val)
1830 return ret_val;
1831 default:
1832 break;
1833 }
1834
1736 /* Check if it is a valid PHY and set PHY mode if necessary. */ 1835 /* Check if it is a valid PHY and set PHY mode if necessary. */
1737 ret_val = e1000_copper_link_preconfig(hw); 1836 ret_val = e1000_copper_link_preconfig(hw);
1738 if(ret_val) 1837 if(ret_val)
@@ -1740,10 +1839,8 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1740 1839
1741 switch (hw->mac_type) { 1840 switch (hw->mac_type) {
1742 case e1000_80003es2lan: 1841 case e1000_80003es2lan:
1743 ret_val = e1000_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL, 1842 /* Kumeran registers are written-only */
1744 &reg_data); 1843 reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
1745 if (ret_val)
1746 return ret_val;
1747 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 1844 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
1748 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL, 1845 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1749 reg_data); 1846 reg_data);
@@ -1755,6 +1852,7 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1755 } 1852 }
1756 1853
1757 if (hw->phy_type == e1000_phy_igp || 1854 if (hw->phy_type == e1000_phy_igp ||
1855 hw->phy_type == e1000_phy_igp_3 ||
1758 hw->phy_type == e1000_phy_igp_2) { 1856 hw->phy_type == e1000_phy_igp_2) {
1759 ret_val = e1000_copper_link_igp_setup(hw); 1857 ret_val = e1000_copper_link_igp_setup(hw);
1760 if(ret_val) 1858 if(ret_val)
@@ -1819,7 +1917,7 @@ e1000_setup_copper_link(struct e1000_hw *hw)
1819* hw - Struct containing variables accessed by shared code 1917* hw - Struct containing variables accessed by shared code
1820******************************************************************************/ 1918******************************************************************************/
1821static int32_t 1919static int32_t
1822e1000_configure_kmrn_for_10_100(struct e1000_hw *hw) 1920e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
1823{ 1921{
1824 int32_t ret_val = E1000_SUCCESS; 1922 int32_t ret_val = E1000_SUCCESS;
1825 uint32_t tipg; 1923 uint32_t tipg;
@@ -1839,6 +1937,18 @@ e1000_configure_kmrn_for_10_100(struct e1000_hw *hw)
1839 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 1937 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
1840 E1000_WRITE_REG(hw, TIPG, tipg); 1938 E1000_WRITE_REG(hw, TIPG, tipg);
1841 1939
1940 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1941
1942 if (ret_val)
1943 return ret_val;
1944
1945 if (duplex == HALF_DUPLEX)
1946 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1947 else
1948 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1949
1950 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1951
1842 return ret_val; 1952 return ret_val;
1843} 1953}
1844 1954
@@ -1863,6 +1973,14 @@ e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
1863 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1973 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1864 E1000_WRITE_REG(hw, TIPG, tipg); 1974 E1000_WRITE_REG(hw, TIPG, tipg);
1865 1975
1976 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1977
1978 if (ret_val)
1979 return ret_val;
1980
1981 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1982 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1983
1866 return ret_val; 1984 return ret_val;
1867} 1985}
1868 1986
@@ -1885,10 +2003,13 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
1885 if(ret_val) 2003 if(ret_val)
1886 return ret_val; 2004 return ret_val;
1887 2005
1888 /* Read the MII 1000Base-T Control Register (Address 9). */ 2006 if (hw->phy_type != e1000_phy_ife) {
1889 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); 2007 /* Read the MII 1000Base-T Control Register (Address 9). */
1890 if(ret_val) 2008 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1891 return ret_val; 2009 if (ret_val)
2010 return ret_val;
2011 } else
2012 mii_1000t_ctrl_reg=0;
1892 2013
1893 /* Need to parse both autoneg_advertised and fc and set up 2014 /* Need to parse both autoneg_advertised and fc and set up
1894 * the appropriate PHY registers. First we will parse for 2015 * the appropriate PHY registers. First we will parse for
@@ -1939,6 +2060,9 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
1939 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) { 2060 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1940 DEBUGOUT("Advertise 1000mb Full duplex\n"); 2061 DEBUGOUT("Advertise 1000mb Full duplex\n");
1941 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 2062 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
2063 if (hw->phy_type == e1000_phy_ife) {
2064 DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
2065 }
1942 } 2066 }
1943 2067
1944 /* Check for a software override of the flow control settings, and 2068 /* Check for a software override of the flow control settings, and
@@ -2000,9 +2124,11 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
2000 2124
2001 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 2125 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
2002 2126
2003 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); 2127 if (hw->phy_type != e1000_phy_ife) {
2004 if(ret_val) 2128 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
2005 return ret_val; 2129 if (ret_val)
2130 return ret_val;
2131 }
2006 2132
2007 return E1000_SUCCESS; 2133 return E1000_SUCCESS;
2008} 2134}
@@ -2105,6 +2231,18 @@ e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2105 2231
2106 /* Need to reset the PHY or these changes will be ignored */ 2232 /* Need to reset the PHY or these changes will be ignored */
2107 mii_ctrl_reg |= MII_CR_RESET; 2233 mii_ctrl_reg |= MII_CR_RESET;
2234 /* Disable MDI-X support for 10/100 */
2235 } else if (hw->phy_type == e1000_phy_ife) {
2236 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
2237 if (ret_val)
2238 return ret_val;
2239
2240 phy_data &= ~IFE_PMC_AUTO_MDIX;
2241 phy_data &= ~IFE_PMC_FORCE_MDIX;
2242
2243 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2244 if (ret_val)
2245 return ret_val;
2108 } else { 2246 } else {
2109 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 2247 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
2110 * forced whenever speed or duplex are forced. 2248 * forced whenever speed or duplex are forced.
@@ -2909,7 +3047,13 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
2909 if (*speed == SPEED_1000) 3047 if (*speed == SPEED_1000)
2910 ret_val = e1000_configure_kmrn_for_1000(hw); 3048 ret_val = e1000_configure_kmrn_for_1000(hw);
2911 else 3049 else
2912 ret_val = e1000_configure_kmrn_for_10_100(hw); 3050 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3051 if (ret_val)
3052 return ret_val;
3053 }
3054
3055 if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
3056 ret_val = e1000_kumeran_lock_loss_workaround(hw);
2913 if (ret_val) 3057 if (ret_val)
2914 return ret_val; 3058 return ret_val;
2915 } 3059 }
@@ -3099,6 +3243,9 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3099 3243
3100 DEBUGFUNC("e1000_swfw_sync_acquire"); 3244 DEBUGFUNC("e1000_swfw_sync_acquire");
3101 3245
3246 if (hw->swfwhw_semaphore_present)
3247 return e1000_get_software_flag(hw);
3248
3102 if (!hw->swfw_sync_present) 3249 if (!hw->swfw_sync_present)
3103 return e1000_get_hw_eeprom_semaphore(hw); 3250 return e1000_get_hw_eeprom_semaphore(hw);
3104 3251
@@ -3138,6 +3285,11 @@ e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
3138 3285
3139 DEBUGFUNC("e1000_swfw_sync_release"); 3286 DEBUGFUNC("e1000_swfw_sync_release");
3140 3287
3288 if (hw->swfwhw_semaphore_present) {
3289 e1000_release_software_flag(hw);
3290 return;
3291 }
3292
3141 if (!hw->swfw_sync_present) { 3293 if (!hw->swfw_sync_present) {
3142 e1000_put_hw_eeprom_semaphore(hw); 3294 e1000_put_hw_eeprom_semaphore(hw);
3143 return; 3295 return;
@@ -3180,7 +3332,8 @@ e1000_read_phy_reg(struct e1000_hw *hw,
3180 if (e1000_swfw_sync_acquire(hw, swfw)) 3332 if (e1000_swfw_sync_acquire(hw, swfw))
3181 return -E1000_ERR_SWFW_SYNC; 3333 return -E1000_ERR_SWFW_SYNC;
3182 3334
3183 if((hw->phy_type == e1000_phy_igp || 3335 if ((hw->phy_type == e1000_phy_igp ||
3336 hw->phy_type == e1000_phy_igp_3 ||
3184 hw->phy_type == e1000_phy_igp_2) && 3337 hw->phy_type == e1000_phy_igp_2) &&
3185 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 3338 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3186 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 3339 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
@@ -3319,7 +3472,8 @@ e1000_write_phy_reg(struct e1000_hw *hw,
3319 if (e1000_swfw_sync_acquire(hw, swfw)) 3472 if (e1000_swfw_sync_acquire(hw, swfw))
3320 return -E1000_ERR_SWFW_SYNC; 3473 return -E1000_ERR_SWFW_SYNC;
3321 3474
3322 if((hw->phy_type == e1000_phy_igp || 3475 if ((hw->phy_type == e1000_phy_igp ||
3476 hw->phy_type == e1000_phy_igp_3 ||
3323 hw->phy_type == e1000_phy_igp_2) && 3477 hw->phy_type == e1000_phy_igp_2) &&
3324 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 3478 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3325 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 3479 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
@@ -3534,7 +3688,7 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3534 E1000_WRITE_FLUSH(hw); 3688 E1000_WRITE_FLUSH(hw);
3535 3689
3536 if (hw->mac_type >= e1000_82571) 3690 if (hw->mac_type >= e1000_82571)
3537 msec_delay(10); 3691 msec_delay_irq(10);
3538 e1000_swfw_sync_release(hw, swfw); 3692 e1000_swfw_sync_release(hw, swfw);
3539 } else { 3693 } else {
3540 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 3694 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
@@ -3564,6 +3718,12 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
3564 ret_val = e1000_get_phy_cfg_done(hw); 3718 ret_val = e1000_get_phy_cfg_done(hw);
3565 e1000_release_software_semaphore(hw); 3719 e1000_release_software_semaphore(hw);
3566 3720
3721 if ((hw->mac_type == e1000_ich8lan) &&
3722 (hw->phy_type == e1000_phy_igp_3)) {
3723 ret_val = e1000_init_lcd_from_nvm(hw);
3724 if (ret_val)
3725 return ret_val;
3726 }
3567 return ret_val; 3727 return ret_val;
3568} 3728}
3569 3729
@@ -3592,9 +3752,11 @@ e1000_phy_reset(struct e1000_hw *hw)
3592 case e1000_82541_rev_2: 3752 case e1000_82541_rev_2:
3593 case e1000_82571: 3753 case e1000_82571:
3594 case e1000_82572: 3754 case e1000_82572:
3755 case e1000_ich8lan:
3595 ret_val = e1000_phy_hw_reset(hw); 3756 ret_val = e1000_phy_hw_reset(hw);
3596 if(ret_val) 3757 if(ret_val)
3597 return ret_val; 3758 return ret_val;
3759
3598 break; 3760 break;
3599 default: 3761 default:
3600 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 3762 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
@@ -3742,8 +3904,8 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
3742 /* The 82571 firmware may still be configuring the PHY. In this 3904 /* The 82571 firmware may still be configuring the PHY. In this
3743 * case, we cannot access the PHY until the configuration is done. So 3905 * case, we cannot access the PHY until the configuration is done. So
3744 * we explicitly set the PHY values. */ 3906 * we explicitly set the PHY values. */
3745 if(hw->mac_type == e1000_82571 || 3907 if (hw->mac_type == e1000_82571 ||
3746 hw->mac_type == e1000_82572) { 3908 hw->mac_type == e1000_82572) {
3747 hw->phy_id = IGP01E1000_I_PHY_ID; 3909 hw->phy_id = IGP01E1000_I_PHY_ID;
3748 hw->phy_type = e1000_phy_igp_2; 3910 hw->phy_type = e1000_phy_igp_2;
3749 return E1000_SUCCESS; 3911 return E1000_SUCCESS;
@@ -3760,7 +3922,7 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
3760 3922
3761 /* Read the PHY ID Registers to identify which PHY is onboard. */ 3923 /* Read the PHY ID Registers to identify which PHY is onboard. */
3762 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); 3924 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
3763 if(ret_val) 3925 if (ret_val)
3764 return ret_val; 3926 return ret_val;
3765 3927
3766 hw->phy_id = (uint32_t) (phy_id_high << 16); 3928 hw->phy_id = (uint32_t) (phy_id_high << 16);
@@ -3798,6 +3960,12 @@ e1000_detect_gig_phy(struct e1000_hw *hw)
3798 case e1000_80003es2lan: 3960 case e1000_80003es2lan:
3799 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE; 3961 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
3800 break; 3962 break;
3963 case e1000_ich8lan:
3964 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
3965 if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
3966 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
3967 if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
3968 break;
3801 default: 3969 default:
3802 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); 3970 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
3803 return -E1000_ERR_CONFIG; 3971 return -E1000_ERR_CONFIG;
@@ -4074,9 +4242,12 @@ e1000_phy_get_info(struct e1000_hw *hw,
4074 return -E1000_ERR_CONFIG; 4242 return -E1000_ERR_CONFIG;
4075 } 4243 }
4076 4244
4077 if(hw->phy_type == e1000_phy_igp || 4245 if (hw->phy_type == e1000_phy_igp ||
4246 hw->phy_type == e1000_phy_igp_3 ||
4078 hw->phy_type == e1000_phy_igp_2) 4247 hw->phy_type == e1000_phy_igp_2)
4079 return e1000_phy_igp_get_info(hw, phy_info); 4248 return e1000_phy_igp_get_info(hw, phy_info);
4249 else if (hw->phy_type == e1000_phy_ife)
4250 return e1000_phy_ife_get_info(hw, phy_info);
4080 else 4251 else
4081 return e1000_phy_m88_get_info(hw, phy_info); 4252 return e1000_phy_m88_get_info(hw, phy_info);
4082} 4253}
@@ -4225,6 +4396,35 @@ e1000_init_eeprom_params(struct e1000_hw *hw)
4225 eeprom->use_eerd = TRUE; 4396 eeprom->use_eerd = TRUE;
4226 eeprom->use_eewr = FALSE; 4397 eeprom->use_eewr = FALSE;
4227 break; 4398 break;
4399 case e1000_ich8lan:
4400 {
4401 int32_t i = 0;
4402 uint32_t flash_size = E1000_READ_ICH8_REG(hw, ICH8_FLASH_GFPREG);
4403
4404 eeprom->type = e1000_eeprom_ich8;
4405 eeprom->use_eerd = FALSE;
4406 eeprom->use_eewr = FALSE;
4407 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
4408
4409 /* Zero the shadow RAM structure. But don't load it from NVM
4410 * so as to save time for driver init */
4411 if (hw->eeprom_shadow_ram != NULL) {
4412 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4413 hw->eeprom_shadow_ram[i].modified = FALSE;
4414 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
4415 }
4416 }
4417
4418 hw->flash_base_addr = (flash_size & ICH8_GFPREG_BASE_MASK) *
4419 ICH8_FLASH_SECTOR_SIZE;
4420
4421 hw->flash_bank_size = ((flash_size >> 16) & ICH8_GFPREG_BASE_MASK) + 1;
4422 hw->flash_bank_size -= (flash_size & ICH8_GFPREG_BASE_MASK);
4423 hw->flash_bank_size *= ICH8_FLASH_SECTOR_SIZE;
4424 hw->flash_bank_size /= 2 * sizeof(uint16_t);
4425
4426 break;
4427 }
4228 default: 4428 default:
4229 break; 4429 break;
4230 } 4430 }
@@ -4645,7 +4845,10 @@ e1000_read_eeprom(struct e1000_hw *hw,
4645 return ret_val; 4845 return ret_val;
4646 } 4846 }
4647 4847
4648 if(eeprom->type == e1000_eeprom_spi) { 4848 if (eeprom->type == e1000_eeprom_ich8)
4849 return e1000_read_eeprom_ich8(hw, offset, words, data);
4850
4851 if (eeprom->type == e1000_eeprom_spi) {
4649 uint16_t word_in; 4852 uint16_t word_in;
4650 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 4853 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
4651 4854
@@ -4812,7 +5015,10 @@ e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
4812 5015
4813 DEBUGFUNC("e1000_is_onboard_nvm_eeprom"); 5016 DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
4814 5017
4815 if(hw->mac_type == e1000_82573) { 5018 if (hw->mac_type == e1000_ich8lan)
5019 return FALSE;
5020
5021 if (hw->mac_type == e1000_82573) {
4816 eecd = E1000_READ_REG(hw, EECD); 5022 eecd = E1000_READ_REG(hw, EECD);
4817 5023
4818 /* Isolate bits 15 & 16 */ 5024 /* Isolate bits 15 & 16 */
@@ -4862,8 +5068,22 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
4862 } 5068 }
4863 } 5069 }
4864 5070
4865 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 5071 if (hw->mac_type == e1000_ich8lan) {
4866 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 5072 /* Drivers must allocate the shadow ram structure for the
5073 * EEPROM checksum to be updated. Otherwise, this bit as well
5074 * as the checksum must both be set correctly for this
5075 * validation to pass.
5076 */
5077 e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
5078 if ((eeprom_data & 0x40) == 0) {
5079 eeprom_data |= 0x40;
5080 e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
5081 e1000_update_eeprom_checksum(hw);
5082 }
5083 }
5084
5085 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
5086 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
4867 DEBUGOUT("EEPROM Read Error\n"); 5087 DEBUGOUT("EEPROM Read Error\n");
4868 return -E1000_ERR_EEPROM; 5088 return -E1000_ERR_EEPROM;
4869 } 5089 }
@@ -4889,6 +5109,7 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw)
4889int32_t 5109int32_t
4890e1000_update_eeprom_checksum(struct e1000_hw *hw) 5110e1000_update_eeprom_checksum(struct e1000_hw *hw)
4891{ 5111{
5112 uint32_t ctrl_ext;
4892 uint16_t checksum = 0; 5113 uint16_t checksum = 0;
4893 uint16_t i, eeprom_data; 5114 uint16_t i, eeprom_data;
4894 5115
@@ -4907,6 +5128,14 @@ e1000_update_eeprom_checksum(struct e1000_hw *hw)
4907 return -E1000_ERR_EEPROM; 5128 return -E1000_ERR_EEPROM;
4908 } else if (hw->eeprom.type == e1000_eeprom_flash) { 5129 } else if (hw->eeprom.type == e1000_eeprom_flash) {
4909 e1000_commit_shadow_ram(hw); 5130 e1000_commit_shadow_ram(hw);
5131 } else if (hw->eeprom.type == e1000_eeprom_ich8) {
5132 e1000_commit_shadow_ram(hw);
5133 /* Reload the EEPROM, or else modifications will not appear
5134 * until after next adapter reset. */
5135 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5136 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5137 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5138 msec_delay(10);
4910 } 5139 }
4911 return E1000_SUCCESS; 5140 return E1000_SUCCESS;
4912} 5141}
@@ -4946,6 +5175,9 @@ e1000_write_eeprom(struct e1000_hw *hw,
4946 if(eeprom->use_eewr == TRUE) 5175 if(eeprom->use_eewr == TRUE)
4947 return e1000_write_eeprom_eewr(hw, offset, words, data); 5176 return e1000_write_eeprom_eewr(hw, offset, words, data);
4948 5177
5178 if (eeprom->type == e1000_eeprom_ich8)
5179 return e1000_write_eeprom_ich8(hw, offset, words, data);
5180
4949 /* Prepare the EEPROM for writing */ 5181 /* Prepare the EEPROM for writing */
4950 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 5182 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4951 return -E1000_ERR_EEPROM; 5183 return -E1000_ERR_EEPROM;
@@ -5133,11 +5365,17 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
5133 uint32_t flop = 0; 5365 uint32_t flop = 0;
5134 uint32_t i = 0; 5366 uint32_t i = 0;
5135 int32_t error = E1000_SUCCESS; 5367 int32_t error = E1000_SUCCESS;
5136 5368 uint32_t old_bank_offset = 0;
5137 /* The flop register will be used to determine if flash type is STM */ 5369 uint32_t new_bank_offset = 0;
5138 flop = E1000_READ_REG(hw, FLOP); 5370 uint32_t sector_retries = 0;
5371 uint8_t low_byte = 0;
5372 uint8_t high_byte = 0;
5373 uint8_t temp_byte = 0;
5374 boolean_t sector_write_failed = FALSE;
5139 5375
5140 if (hw->mac_type == e1000_82573) { 5376 if (hw->mac_type == e1000_82573) {
5377 /* The flop register will be used to determine if flash type is STM */
5378 flop = E1000_READ_REG(hw, FLOP);
5141 for (i=0; i < attempts; i++) { 5379 for (i=0; i < attempts; i++) {
5142 eecd = E1000_READ_REG(hw, EECD); 5380 eecd = E1000_READ_REG(hw, EECD);
5143 if ((eecd & E1000_EECD_FLUPD) == 0) { 5381 if ((eecd & E1000_EECD_FLUPD) == 0) {
@@ -5171,6 +5409,106 @@ e1000_commit_shadow_ram(struct e1000_hw *hw)
5171 } 5409 }
5172 } 5410 }
5173 5411
5412 if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) {
5413 /* We're writing to the opposite bank so if we're on bank 1,
5414 * write to bank 0 etc. We also need to erase the segment that
5415 * is going to be written */
5416 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
5417 new_bank_offset = hw->flash_bank_size * 2;
5418 old_bank_offset = 0;
5419 e1000_erase_ich8_4k_segment(hw, 1);
5420 } else {
5421 old_bank_offset = hw->flash_bank_size * 2;
5422 new_bank_offset = 0;
5423 e1000_erase_ich8_4k_segment(hw, 0);
5424 }
5425
5426 do {
5427 sector_write_failed = FALSE;
5428 /* Loop for every byte in the shadow RAM,
5429 * which is in units of words. */
5430 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5431 /* Determine whether to write the value stored
5432 * in the other NVM bank or a modified value stored
5433 * in the shadow RAM */
5434 if (hw->eeprom_shadow_ram[i].modified == TRUE) {
5435 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
5436 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5437 &temp_byte);
5438 udelay(100);
5439 error = e1000_verify_write_ich8_byte(hw,
5440 (i << 1) + new_bank_offset,
5441 low_byte);
5442 if (error != E1000_SUCCESS)
5443 sector_write_failed = TRUE;
5444 high_byte =
5445 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5446 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5447 &temp_byte);
5448 udelay(100);
5449 } else {
5450 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5451 &low_byte);
5452 udelay(100);
5453 error = e1000_verify_write_ich8_byte(hw,
5454 (i << 1) + new_bank_offset, low_byte);
5455 if (error != E1000_SUCCESS)
5456 sector_write_failed = TRUE;
5457 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5458 &high_byte);
5459 }
5460
5461 /* If the word is 0x13, then make sure the signature bits
5462 * (15:14) are 11b until the commit has completed.
5463 * This will allow us to write 10b which indicates the
5464 * signature is valid. We want to do this after the write
5465 * has completed so that we don't mark the segment valid
5466 * while the write is still in progress */
5467 if (i == E1000_ICH8_NVM_SIG_WORD)
5468 high_byte = E1000_ICH8_NVM_SIG_MASK | high_byte;
5469
5470 error = e1000_verify_write_ich8_byte(hw,
5471 (i << 1) + new_bank_offset + 1, high_byte);
5472 if (error != E1000_SUCCESS)
5473 sector_write_failed = TRUE;
5474
5475 if (sector_write_failed == FALSE) {
5476 /* Clear the now not used entry in the cache */
5477 hw->eeprom_shadow_ram[i].modified = FALSE;
5478 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
5479 }
5480 }
5481
5482 /* Don't bother writing the segment valid bits if sector
5483 * programming failed. */
5484 if (sector_write_failed == FALSE) {
5485 /* Finally validate the new segment by setting bit 15:14
5486 * to 10b in word 0x13 , this can be done without an
5487 * erase as well since these bits are 11 to start with
5488 * and we need to change bit 14 to 0b */
5489 e1000_read_ich8_byte(hw,
5490 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5491 &high_byte);
5492 high_byte &= 0xBF;
5493 error = e1000_verify_write_ich8_byte(hw,
5494 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5495 high_byte);
5496 if (error != E1000_SUCCESS)
5497 sector_write_failed = TRUE;
5498
5499 /* And invalidate the previously valid segment by setting
5500 * its signature word (0x13) high_byte to 0b. This can be
5501 * done without an erase because flash erase sets all bits
5502 * to 1's. We can write 1's to 0's without an erase */
5503 error = e1000_verify_write_ich8_byte(hw,
5504 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + old_bank_offset,
5505 0);
5506 if (error != E1000_SUCCESS)
5507 sector_write_failed = TRUE;
5508 }
5509 } while (++sector_retries < 10 && sector_write_failed == TRUE);
5510 }
5511
5174 return error; 5512 return error;
5175} 5513}
5176 5514
@@ -5278,6 +5616,9 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
5278 * the other port. */ 5616 * the other port. */
5279 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) 5617 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5280 rar_num -= 1; 5618 rar_num -= 1;
5619 if (hw->mac_type == e1000_ich8lan)
5620 rar_num = E1000_RAR_ENTRIES_ICH8LAN;
5621
5281 /* Zero out the other 15 receive addresses. */ 5622 /* Zero out the other 15 receive addresses. */
5282 DEBUGOUT("Clearing RAR[1-15]\n"); 5623 DEBUGOUT("Clearing RAR[1-15]\n");
5283 for(i = 1; i < rar_num; i++) { 5624 for(i = 1; i < rar_num; i++) {
@@ -5288,7 +5629,6 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
5288 } 5629 }
5289} 5630}
5290 5631
5291#if 0
5292/****************************************************************************** 5632/******************************************************************************
5293 * Updates the MAC's list of multicast addresses. 5633 * Updates the MAC's list of multicast addresses.
5294 * 5634 *
@@ -5323,6 +5663,8 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
5323 /* Clear RAR[1-15] */ 5663 /* Clear RAR[1-15] */
5324 DEBUGOUT(" Clearing RAR[1-15]\n"); 5664 DEBUGOUT(" Clearing RAR[1-15]\n");
5325 num_rar_entry = E1000_RAR_ENTRIES; 5665 num_rar_entry = E1000_RAR_ENTRIES;
5666 if (hw->mac_type == e1000_ich8lan)
5667 num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN;
5326 /* Reserve a spot for the Locally Administered Address to work around 5668 /* Reserve a spot for the Locally Administered Address to work around
5327 * an 82571 issue in which a reset on one port will reload the MAC on 5669 * an 82571 issue in which a reset on one port will reload the MAC on
5328 * the other port. */ 5670 * the other port. */
@@ -5339,6 +5681,8 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
5339 /* Clear the MTA */ 5681 /* Clear the MTA */
5340 DEBUGOUT(" Clearing MTA\n"); 5682 DEBUGOUT(" Clearing MTA\n");
5341 num_mta_entry = E1000_NUM_MTA_REGISTERS; 5683 num_mta_entry = E1000_NUM_MTA_REGISTERS;
5684 if (hw->mac_type == e1000_ich8lan)
5685 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN;
5342 for(i = 0; i < num_mta_entry; i++) { 5686 for(i = 0; i < num_mta_entry; i++) {
5343 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 5687 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
5344 E1000_WRITE_FLUSH(hw); 5688 E1000_WRITE_FLUSH(hw);
@@ -5375,7 +5719,6 @@ e1000_mc_addr_list_update(struct e1000_hw *hw,
5375 } 5719 }
5376 DEBUGOUT("MC Update Complete\n"); 5720 DEBUGOUT("MC Update Complete\n");
5377} 5721}
5378#endif /* 0 */
5379 5722
5380/****************************************************************************** 5723/******************************************************************************
5381 * Hashes an address to determine its location in the multicast table 5724 * Hashes an address to determine its location in the multicast table
@@ -5398,24 +5741,46 @@ e1000_hash_mc_addr(struct e1000_hw *hw,
5398 * LSB MSB 5741 * LSB MSB
5399 */ 5742 */
5400 case 0: 5743 case 0:
5401 /* [47:36] i.e. 0x563 for above example address */ 5744 if (hw->mac_type == e1000_ich8lan) {
5402 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); 5745 /* [47:38] i.e. 0x158 for above example address */
5746 hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2));
5747 } else {
5748 /* [47:36] i.e. 0x563 for above example address */
5749 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5750 }
5403 break; 5751 break;
5404 case 1: 5752 case 1:
5405 /* [46:35] i.e. 0xAC6 for above example address */ 5753 if (hw->mac_type == e1000_ich8lan) {
5406 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5)); 5754 /* [46:37] i.e. 0x2B1 for above example address */
5755 hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3));
5756 } else {
5757 /* [46:35] i.e. 0xAC6 for above example address */
5758 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
5759 }
5407 break; 5760 break;
5408 case 2: 5761 case 2:
5409 /* [45:34] i.e. 0x5D8 for above example address */ 5762 if (hw->mac_type == e1000_ich8lan) {
5410 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); 5763 /*[45:36] i.e. 0x163 for above example address */
5764 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5765 } else {
5766 /* [45:34] i.e. 0x5D8 for above example address */
5767 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5768 }
5411 break; 5769 break;
5412 case 3: 5770 case 3:
5413 /* [43:32] i.e. 0x634 for above example address */ 5771 if (hw->mac_type == e1000_ich8lan) {
5414 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8)); 5772 /* [43:34] i.e. 0x18D for above example address */
5773 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5774 } else {
5775 /* [43:32] i.e. 0x634 for above example address */
5776 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
5777 }
5415 break; 5778 break;
5416 } 5779 }
5417 5780
5418 hash_value &= 0xFFF; 5781 hash_value &= 0xFFF;
5782 if (hw->mac_type == e1000_ich8lan)
5783 hash_value &= 0x3FF;
5419 5784
5420 return hash_value; 5785 return hash_value;
5421} 5786}
@@ -5443,6 +5808,8 @@ e1000_mta_set(struct e1000_hw *hw,
5443 * register are determined by the lower 5 bits of the value. 5808 * register are determined by the lower 5 bits of the value.
5444 */ 5809 */
5445 hash_reg = (hash_value >> 5) & 0x7F; 5810 hash_reg = (hash_value >> 5) & 0x7F;
5811 if (hw->mac_type == e1000_ich8lan)
5812 hash_reg &= 0x1F;
5446 hash_bit = hash_value & 0x1F; 5813 hash_bit = hash_value & 0x1F;
5447 5814
5448 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); 5815 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
@@ -5537,7 +5904,10 @@ e1000_write_vfta(struct e1000_hw *hw,
5537{ 5904{
5538 uint32_t temp; 5905 uint32_t temp;
5539 5906
5540 if((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { 5907 if (hw->mac_type == e1000_ich8lan)
5908 return;
5909
5910 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
5541 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); 5911 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
5542 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 5912 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
5543 E1000_WRITE_FLUSH(hw); 5913 E1000_WRITE_FLUSH(hw);
@@ -5562,6 +5932,9 @@ e1000_clear_vfta(struct e1000_hw *hw)
5562 uint32_t vfta_offset = 0; 5932 uint32_t vfta_offset = 0;
5563 uint32_t vfta_bit_in_reg = 0; 5933 uint32_t vfta_bit_in_reg = 0;
5564 5934
5935 if (hw->mac_type == e1000_ich8lan)
5936 return;
5937
5565 if (hw->mac_type == e1000_82573) { 5938 if (hw->mac_type == e1000_82573) {
5566 if (hw->mng_cookie.vlan_id != 0) { 5939 if (hw->mng_cookie.vlan_id != 0) {
5567 /* The VFTA is a 4096b bit-field, each identifying a single VLAN 5940 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
@@ -5611,9 +5984,18 @@ e1000_id_led_init(struct e1000_hw * hw)
5611 DEBUGOUT("EEPROM Read Error\n"); 5984 DEBUGOUT("EEPROM Read Error\n");
5612 return -E1000_ERR_EEPROM; 5985 return -E1000_ERR_EEPROM;
5613 } 5986 }
5614 if((eeprom_data== ID_LED_RESERVED_0000) || 5987
5615 (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT; 5988 if ((hw->mac_type == e1000_82573) &&
5616 for(i = 0; i < 4; i++) { 5989 (eeprom_data == ID_LED_RESERVED_82573))
5990 eeprom_data = ID_LED_DEFAULT_82573;
5991 else if ((eeprom_data == ID_LED_RESERVED_0000) ||
5992 (eeprom_data == ID_LED_RESERVED_FFFF)) {
5993 if (hw->mac_type == e1000_ich8lan)
5994 eeprom_data = ID_LED_DEFAULT_ICH8LAN;
5995 else
5996 eeprom_data = ID_LED_DEFAULT;
5997 }
5998 for (i = 0; i < 4; i++) {
5617 temp = (eeprom_data >> (i << 2)) & led_mask; 5999 temp = (eeprom_data >> (i << 2)) & led_mask;
5618 switch(temp) { 6000 switch(temp) {
5619 case ID_LED_ON1_DEF2: 6001 case ID_LED_ON1_DEF2:
@@ -5776,6 +6158,10 @@ e1000_cleanup_led(struct e1000_hw *hw)
5776 return ret_val; 6158 return ret_val;
5777 /* Fall Through */ 6159 /* Fall Through */
5778 default: 6160 default:
6161 if (hw->phy_type == e1000_phy_ife) {
6162 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
6163 break;
6164 }
5779 /* Restore LEDCTL settings */ 6165 /* Restore LEDCTL settings */
5780 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default); 6166 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
5781 break; 6167 break;
@@ -5820,7 +6206,10 @@ e1000_led_on(struct e1000_hw *hw)
5820 /* Clear SW Defineable Pin 0 to turn on the LED */ 6206 /* Clear SW Defineable Pin 0 to turn on the LED */
5821 ctrl &= ~E1000_CTRL_SWDPIN0; 6207 ctrl &= ~E1000_CTRL_SWDPIN0;
5822 ctrl |= E1000_CTRL_SWDPIO0; 6208 ctrl |= E1000_CTRL_SWDPIO0;
5823 } else if(hw->media_type == e1000_media_type_copper) { 6209 } else if (hw->phy_type == e1000_phy_ife) {
6210 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6211 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
6212 } else if (hw->media_type == e1000_media_type_copper) {
5824 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2); 6213 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
5825 return E1000_SUCCESS; 6214 return E1000_SUCCESS;
5826 } 6215 }
@@ -5868,7 +6257,10 @@ e1000_led_off(struct e1000_hw *hw)
5868 /* Set SW Defineable Pin 0 to turn off the LED */ 6257 /* Set SW Defineable Pin 0 to turn off the LED */
5869 ctrl |= E1000_CTRL_SWDPIN0; 6258 ctrl |= E1000_CTRL_SWDPIN0;
5870 ctrl |= E1000_CTRL_SWDPIO0; 6259 ctrl |= E1000_CTRL_SWDPIO0;
5871 } else if(hw->media_type == e1000_media_type_copper) { 6260 } else if (hw->phy_type == e1000_phy_ife) {
6261 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6262 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
6263 } else if (hw->media_type == e1000_media_type_copper) {
5872 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); 6264 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
5873 return E1000_SUCCESS; 6265 return E1000_SUCCESS;
5874 } 6266 }
@@ -5906,12 +6298,16 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
5906 temp = E1000_READ_REG(hw, XOFFRXC); 6298 temp = E1000_READ_REG(hw, XOFFRXC);
5907 temp = E1000_READ_REG(hw, XOFFTXC); 6299 temp = E1000_READ_REG(hw, XOFFTXC);
5908 temp = E1000_READ_REG(hw, FCRUC); 6300 temp = E1000_READ_REG(hw, FCRUC);
6301
6302 if (hw->mac_type != e1000_ich8lan) {
5909 temp = E1000_READ_REG(hw, PRC64); 6303 temp = E1000_READ_REG(hw, PRC64);
5910 temp = E1000_READ_REG(hw, PRC127); 6304 temp = E1000_READ_REG(hw, PRC127);
5911 temp = E1000_READ_REG(hw, PRC255); 6305 temp = E1000_READ_REG(hw, PRC255);
5912 temp = E1000_READ_REG(hw, PRC511); 6306 temp = E1000_READ_REG(hw, PRC511);
5913 temp = E1000_READ_REG(hw, PRC1023); 6307 temp = E1000_READ_REG(hw, PRC1023);
5914 temp = E1000_READ_REG(hw, PRC1522); 6308 temp = E1000_READ_REG(hw, PRC1522);
6309 }
6310
5915 temp = E1000_READ_REG(hw, GPRC); 6311 temp = E1000_READ_REG(hw, GPRC);
5916 temp = E1000_READ_REG(hw, BPRC); 6312 temp = E1000_READ_REG(hw, BPRC);
5917 temp = E1000_READ_REG(hw, MPRC); 6313 temp = E1000_READ_REG(hw, MPRC);
@@ -5931,12 +6327,16 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
5931 temp = E1000_READ_REG(hw, TOTH); 6327 temp = E1000_READ_REG(hw, TOTH);
5932 temp = E1000_READ_REG(hw, TPR); 6328 temp = E1000_READ_REG(hw, TPR);
5933 temp = E1000_READ_REG(hw, TPT); 6329 temp = E1000_READ_REG(hw, TPT);
6330
6331 if (hw->mac_type != e1000_ich8lan) {
5934 temp = E1000_READ_REG(hw, PTC64); 6332 temp = E1000_READ_REG(hw, PTC64);
5935 temp = E1000_READ_REG(hw, PTC127); 6333 temp = E1000_READ_REG(hw, PTC127);
5936 temp = E1000_READ_REG(hw, PTC255); 6334 temp = E1000_READ_REG(hw, PTC255);
5937 temp = E1000_READ_REG(hw, PTC511); 6335 temp = E1000_READ_REG(hw, PTC511);
5938 temp = E1000_READ_REG(hw, PTC1023); 6336 temp = E1000_READ_REG(hw, PTC1023);
5939 temp = E1000_READ_REG(hw, PTC1522); 6337 temp = E1000_READ_REG(hw, PTC1522);
6338 }
6339
5940 temp = E1000_READ_REG(hw, MPTC); 6340 temp = E1000_READ_REG(hw, MPTC);
5941 temp = E1000_READ_REG(hw, BPTC); 6341 temp = E1000_READ_REG(hw, BPTC);
5942 6342
@@ -5959,6 +6359,9 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw)
5959 6359
5960 temp = E1000_READ_REG(hw, IAC); 6360 temp = E1000_READ_REG(hw, IAC);
5961 temp = E1000_READ_REG(hw, ICRXOC); 6361 temp = E1000_READ_REG(hw, ICRXOC);
6362
6363 if (hw->mac_type == e1000_ich8lan) return;
6364
5962 temp = E1000_READ_REG(hw, ICRXPTC); 6365 temp = E1000_READ_REG(hw, ICRXPTC);
5963 temp = E1000_READ_REG(hw, ICRXATC); 6366 temp = E1000_READ_REG(hw, ICRXATC);
5964 temp = E1000_READ_REG(hw, ICTXPTC); 6367 temp = E1000_READ_REG(hw, ICTXPTC);
@@ -6139,6 +6542,7 @@ e1000_get_bus_info(struct e1000_hw *hw)
6139 hw->bus_width = e1000_bus_width_pciex_1; 6542 hw->bus_width = e1000_bus_width_pciex_1;
6140 break; 6543 break;
6141 case e1000_82571: 6544 case e1000_82571:
6545 case e1000_ich8lan:
6142 case e1000_80003es2lan: 6546 case e1000_80003es2lan:
6143 hw->bus_type = e1000_bus_type_pci_express; 6547 hw->bus_type = e1000_bus_type_pci_express;
6144 hw->bus_speed = e1000_bus_speed_2500; 6548 hw->bus_speed = e1000_bus_speed_2500;
@@ -6176,8 +6580,6 @@ e1000_get_bus_info(struct e1000_hw *hw)
6176 break; 6580 break;
6177 } 6581 }
6178} 6582}
6179
6180#if 0
6181/****************************************************************************** 6583/******************************************************************************
6182 * Reads a value from one of the devices registers using port I/O (as opposed 6584 * Reads a value from one of the devices registers using port I/O (as opposed
6183 * memory mapped I/O). Only 82544 and newer devices support port I/O. 6585 * memory mapped I/O). Only 82544 and newer devices support port I/O.
@@ -6195,7 +6597,6 @@ e1000_read_reg_io(struct e1000_hw *hw,
6195 e1000_io_write(hw, io_addr, offset); 6597 e1000_io_write(hw, io_addr, offset);
6196 return e1000_io_read(hw, io_data); 6598 return e1000_io_read(hw, io_data);
6197} 6599}
6198#endif /* 0 */
6199 6600
6200/****************************************************************************** 6601/******************************************************************************
6201 * Writes a value to one of the devices registers using port I/O (as opposed to 6602 * Writes a value to one of the devices registers using port I/O (as opposed to
@@ -6240,8 +6641,6 @@ e1000_get_cable_length(struct e1000_hw *hw,
6240{ 6641{
6241 int32_t ret_val; 6642 int32_t ret_val;
6242 uint16_t agc_value = 0; 6643 uint16_t agc_value = 0;
6243 uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6244 uint16_t max_agc = 0;
6245 uint16_t i, phy_data; 6644 uint16_t i, phy_data;
6246 uint16_t cable_length; 6645 uint16_t cable_length;
6247 6646
@@ -6314,6 +6713,8 @@ e1000_get_cable_length(struct e1000_hw *hw,
6314 break; 6713 break;
6315 } 6714 }
6316 } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ 6715 } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
6716 uint16_t cur_agc_value;
6717 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6317 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 6718 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6318 {IGP01E1000_PHY_AGC_A, 6719 {IGP01E1000_PHY_AGC_A,
6319 IGP01E1000_PHY_AGC_B, 6720 IGP01E1000_PHY_AGC_B,
@@ -6326,23 +6727,23 @@ e1000_get_cable_length(struct e1000_hw *hw,
6326 if(ret_val) 6727 if(ret_val)
6327 return ret_val; 6728 return ret_val;
6328 6729
6329 cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; 6730 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
6330 6731
6331 /* Array bound check. */ 6732 /* Value bound check. */
6332 if((cur_agc >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 6733 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
6333 (cur_agc == 0)) 6734 (cur_agc_value == 0))
6334 return -E1000_ERR_PHY; 6735 return -E1000_ERR_PHY;
6335 6736
6336 agc_value += cur_agc; 6737 agc_value += cur_agc_value;
6337 6738
6338 /* Update minimal AGC value. */ 6739 /* Update minimal AGC value. */
6339 if(min_agc > cur_agc) 6740 if (min_agc_value > cur_agc_value)
6340 min_agc = cur_agc; 6741 min_agc_value = cur_agc_value;
6341 } 6742 }
6342 6743
6343 /* Remove the minimal AGC result for length < 50m */ 6744 /* Remove the minimal AGC result for length < 50m */
6344 if(agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { 6745 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
6345 agc_value -= min_agc; 6746 agc_value -= min_agc_value;
6346 6747
6347 /* Get the average length of the remaining 3 channels */ 6748 /* Get the average length of the remaining 3 channels */
6348 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 6749 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
@@ -6358,7 +6759,10 @@ e1000_get_cable_length(struct e1000_hw *hw,
6358 IGP01E1000_AGC_RANGE) : 0; 6759 IGP01E1000_AGC_RANGE) : 0;
6359 *max_length = e1000_igp_cable_length_table[agc_value] + 6760 *max_length = e1000_igp_cable_length_table[agc_value] +
6360 IGP01E1000_AGC_RANGE; 6761 IGP01E1000_AGC_RANGE;
6361 } else if (hw->phy_type == e1000_phy_igp_2) { 6762 } else if (hw->phy_type == e1000_phy_igp_2 ||
6763 hw->phy_type == e1000_phy_igp_3) {
6764 uint16_t cur_agc_index, max_agc_index = 0;
6765 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
6362 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 6766 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6363 {IGP02E1000_PHY_AGC_A, 6767 {IGP02E1000_PHY_AGC_A,
6364 IGP02E1000_PHY_AGC_B, 6768 IGP02E1000_PHY_AGC_B,
@@ -6373,19 +6777,27 @@ e1000_get_cable_length(struct e1000_hw *hw,
6373 /* Getting bits 15:9, which represent the combination of course and 6777 /* Getting bits 15:9, which represent the combination of course and
6374 * fine gain values. The result is a number that can be put into 6778 * fine gain values. The result is a number that can be put into
6375 * the lookup table to obtain the approximate cable length. */ 6779 * the lookup table to obtain the approximate cable length. */
6376 cur_agc = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 6780 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
6377 IGP02E1000_AGC_LENGTH_MASK; 6781 IGP02E1000_AGC_LENGTH_MASK;
6782
6783 /* Array index bound check. */
6784 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
6785 (cur_agc_index == 0))
6786 return -E1000_ERR_PHY;
6378 6787
6379 /* Remove min & max AGC values from calculation. */ 6788 /* Remove min & max AGC values from calculation. */
6380 if (e1000_igp_2_cable_length_table[min_agc] > e1000_igp_2_cable_length_table[cur_agc]) 6789 if (e1000_igp_2_cable_length_table[min_agc_index] >
6381 min_agc = cur_agc; 6790 e1000_igp_2_cable_length_table[cur_agc_index])
6382 if (e1000_igp_2_cable_length_table[max_agc] < e1000_igp_2_cable_length_table[cur_agc]) 6791 min_agc_index = cur_agc_index;
6383 max_agc = cur_agc; 6792 if (e1000_igp_2_cable_length_table[max_agc_index] <
6793 e1000_igp_2_cable_length_table[cur_agc_index])
6794 max_agc_index = cur_agc_index;
6384 6795
6385 agc_value += e1000_igp_2_cable_length_table[cur_agc]; 6796 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
6386 } 6797 }
6387 6798
6388 agc_value -= (e1000_igp_2_cable_length_table[min_agc] + e1000_igp_2_cable_length_table[max_agc]); 6799 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
6800 e1000_igp_2_cable_length_table[max_agc_index]);
6389 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 6801 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
6390 6802
6391 /* Calculate cable length with the error range of +/- 10 meters. */ 6803 /* Calculate cable length with the error range of +/- 10 meters. */
@@ -6431,7 +6843,8 @@ e1000_check_polarity(struct e1000_hw *hw,
6431 return ret_val; 6843 return ret_val;
6432 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >> 6844 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
6433 M88E1000_PSSR_REV_POLARITY_SHIFT; 6845 M88E1000_PSSR_REV_POLARITY_SHIFT;
6434 } else if(hw->phy_type == e1000_phy_igp || 6846 } else if (hw->phy_type == e1000_phy_igp ||
6847 hw->phy_type == e1000_phy_igp_3 ||
6435 hw->phy_type == e1000_phy_igp_2) { 6848 hw->phy_type == e1000_phy_igp_2) {
6436 /* Read the Status register to check the speed */ 6849 /* Read the Status register to check the speed */
6437 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, 6850 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
@@ -6457,6 +6870,13 @@ e1000_check_polarity(struct e1000_hw *hw,
6457 * 100 Mbps this bit is always 0) */ 6870 * 100 Mbps this bit is always 0) */
6458 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED; 6871 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED;
6459 } 6872 }
6873 } else if (hw->phy_type == e1000_phy_ife) {
6874 ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
6875 &phy_data);
6876 if (ret_val)
6877 return ret_val;
6878 *polarity = (phy_data & IFE_PESC_POLARITY_REVERSED) >>
6879 IFE_PESC_POLARITY_REVERSED_SHIFT;
6460 } 6880 }
6461 return E1000_SUCCESS; 6881 return E1000_SUCCESS;
6462} 6882}
@@ -6484,7 +6904,8 @@ e1000_check_downshift(struct e1000_hw *hw)
6484 6904
6485 DEBUGFUNC("e1000_check_downshift"); 6905 DEBUGFUNC("e1000_check_downshift");
6486 6906
6487 if(hw->phy_type == e1000_phy_igp || 6907 if (hw->phy_type == e1000_phy_igp ||
6908 hw->phy_type == e1000_phy_igp_3 ||
6488 hw->phy_type == e1000_phy_igp_2) { 6909 hw->phy_type == e1000_phy_igp_2) {
6489 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 6910 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6490 &phy_data); 6911 &phy_data);
@@ -6501,6 +6922,9 @@ e1000_check_downshift(struct e1000_hw *hw)
6501 6922
6502 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 6923 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
6503 M88E1000_PSSR_DOWNSHIFT_SHIFT; 6924 M88E1000_PSSR_DOWNSHIFT_SHIFT;
6925 } else if (hw->phy_type == e1000_phy_ife) {
6926 /* e1000_phy_ife supports 10/100 speed only */
6927 hw->speed_downgraded = FALSE;
6504 } 6928 }
6505 6929
6506 return E1000_SUCCESS; 6930 return E1000_SUCCESS;
@@ -6545,7 +6969,9 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw,
6545 6969
6546 if(speed == SPEED_1000) { 6970 if(speed == SPEED_1000) {
6547 6971
6548 e1000_get_cable_length(hw, &min_length, &max_length); 6972 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
6973 if (ret_val)
6974 return ret_val;
6549 6975
6550 if((hw->dsp_config_state == e1000_dsp_config_enabled) && 6976 if((hw->dsp_config_state == e1000_dsp_config_enabled) &&
6551 min_length >= e1000_igp_cable_length_50) { 6977 min_length >= e1000_igp_cable_length_50) {
@@ -6753,20 +7179,27 @@ static int32_t
6753e1000_set_d3_lplu_state(struct e1000_hw *hw, 7179e1000_set_d3_lplu_state(struct e1000_hw *hw,
6754 boolean_t active) 7180 boolean_t active)
6755{ 7181{
7182 uint32_t phy_ctrl = 0;
6756 int32_t ret_val; 7183 int32_t ret_val;
6757 uint16_t phy_data; 7184 uint16_t phy_data;
6758 DEBUGFUNC("e1000_set_d3_lplu_state"); 7185 DEBUGFUNC("e1000_set_d3_lplu_state");
6759 7186
6760 if(hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2) 7187 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
7188 && hw->phy_type != e1000_phy_igp_3)
6761 return E1000_SUCCESS; 7189 return E1000_SUCCESS;
6762 7190
6763 /* During driver activity LPLU should not be used or it will attain link 7191 /* During driver activity LPLU should not be used or it will attain link
6764 * from the lowest speeds starting from 10Mbps. The capability is used for 7192 * from the lowest speeds starting from 10Mbps. The capability is used for
6765 * Dx transitions and states */ 7193 * Dx transitions and states */
6766 if(hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) { 7194 if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
6767 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 7195 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
6768 if(ret_val) 7196 if (ret_val)
6769 return ret_val; 7197 return ret_val;
7198 } else if (hw->mac_type == e1000_ich8lan) {
7199 /* MAC writes into PHY register based on the state transition
7200 * and start auto-negotiation. SW driver can overwrite the settings
7201 * in CSR PHY power control E1000_PHY_CTRL register. */
7202 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
6770 } else { 7203 } else {
6771 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 7204 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
6772 if(ret_val) 7205 if(ret_val)
@@ -6781,11 +7214,16 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
6781 if(ret_val) 7214 if(ret_val)
6782 return ret_val; 7215 return ret_val;
6783 } else { 7216 } else {
7217 if (hw->mac_type == e1000_ich8lan) {
7218 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7219 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7220 } else {
6784 phy_data &= ~IGP02E1000_PM_D3_LPLU; 7221 phy_data &= ~IGP02E1000_PM_D3_LPLU;
6785 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 7222 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
6786 phy_data); 7223 phy_data);
6787 if (ret_val) 7224 if (ret_val)
6788 return ret_val; 7225 return ret_val;
7226 }
6789 } 7227 }
6790 7228
6791 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 7229 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
@@ -6821,17 +7259,22 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw,
6821 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 7259 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
6822 7260
6823 if(hw->mac_type == e1000_82541_rev_2 || 7261 if(hw->mac_type == e1000_82541_rev_2 ||
6824 hw->mac_type == e1000_82547_rev_2) { 7262 hw->mac_type == e1000_82547_rev_2) {
6825 phy_data |= IGP01E1000_GMII_FLEX_SPD; 7263 phy_data |= IGP01E1000_GMII_FLEX_SPD;
6826 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); 7264 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
6827 if(ret_val) 7265 if(ret_val)
6828 return ret_val; 7266 return ret_val;
6829 } else { 7267 } else {
7268 if (hw->mac_type == e1000_ich8lan) {
7269 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
7270 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7271 } else {
6830 phy_data |= IGP02E1000_PM_D3_LPLU; 7272 phy_data |= IGP02E1000_PM_D3_LPLU;
6831 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 7273 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
6832 phy_data); 7274 phy_data);
6833 if (ret_val) 7275 if (ret_val)
6834 return ret_val; 7276 return ret_val;
7277 }
6835 } 7278 }
6836 7279
6837 /* When LPLU is enabled we should disable SmartSpeed */ 7280 /* When LPLU is enabled we should disable SmartSpeed */
@@ -6866,6 +7309,7 @@ static int32_t
6866e1000_set_d0_lplu_state(struct e1000_hw *hw, 7309e1000_set_d0_lplu_state(struct e1000_hw *hw,
6867 boolean_t active) 7310 boolean_t active)
6868{ 7311{
7312 uint32_t phy_ctrl = 0;
6869 int32_t ret_val; 7313 int32_t ret_val;
6870 uint16_t phy_data; 7314 uint16_t phy_data;
6871 DEBUGFUNC("e1000_set_d0_lplu_state"); 7315 DEBUGFUNC("e1000_set_d0_lplu_state");
@@ -6873,15 +7317,24 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
6873 if(hw->mac_type <= e1000_82547_rev_2) 7317 if(hw->mac_type <= e1000_82547_rev_2)
6874 return E1000_SUCCESS; 7318 return E1000_SUCCESS;
6875 7319
7320 if (hw->mac_type == e1000_ich8lan) {
7321 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7322 } else {
6876 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 7323 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
6877 if(ret_val) 7324 if(ret_val)
6878 return ret_val; 7325 return ret_val;
7326 }
6879 7327
6880 if (!active) { 7328 if (!active) {
7329 if (hw->mac_type == e1000_ich8lan) {
7330 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7331 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7332 } else {
6881 phy_data &= ~IGP02E1000_PM_D0_LPLU; 7333 phy_data &= ~IGP02E1000_PM_D0_LPLU;
6882 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 7334 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
6883 if (ret_val) 7335 if (ret_val)
6884 return ret_val; 7336 return ret_val;
7337 }
6885 7338
6886 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 7339 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
6887 * Dx states where the power conservation is most important. During 7340 * Dx states where the power conservation is most important. During
@@ -6914,10 +7367,15 @@ e1000_set_d0_lplu_state(struct e1000_hw *hw,
6914 7367
6915 } else { 7368 } else {
6916 7369
7370 if (hw->mac_type == e1000_ich8lan) {
7371 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
7372 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7373 } else {
6917 phy_data |= IGP02E1000_PM_D0_LPLU; 7374 phy_data |= IGP02E1000_PM_D0_LPLU;
6918 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 7375 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
6919 if (ret_val) 7376 if (ret_val)
6920 return ret_val; 7377 return ret_val;
7378 }
6921 7379
6922 /* When LPLU is enabled we should disable SmartSpeed */ 7380 /* When LPLU is enabled we should disable SmartSpeed */
6923 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); 7381 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
@@ -7191,15 +7649,18 @@ e1000_mng_write_commit(
7191 * returns - TRUE when the mode is IAMT or FALSE. 7649 * returns - TRUE when the mode is IAMT or FALSE.
7192 ****************************************************************************/ 7650 ****************************************************************************/
7193boolean_t 7651boolean_t
7194e1000_check_mng_mode( 7652e1000_check_mng_mode(struct e1000_hw *hw)
7195 struct e1000_hw *hw)
7196{ 7653{
7197 uint32_t fwsm; 7654 uint32_t fwsm;
7198 7655
7199 fwsm = E1000_READ_REG(hw, FWSM); 7656 fwsm = E1000_READ_REG(hw, FWSM);
7200 7657
7201 if((fwsm & E1000_FWSM_MODE_MASK) == 7658 if (hw->mac_type == e1000_ich8lan) {
7202 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 7659 if ((fwsm & E1000_FWSM_MODE_MASK) ==
7660 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7661 return TRUE;
7662 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
7663 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7203 return TRUE; 7664 return TRUE;
7204 7665
7205 return FALSE; 7666 return FALSE;
@@ -7439,7 +7900,6 @@ e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7439 E1000_WRITE_REG(hw, CTRL, ctrl); 7900 E1000_WRITE_REG(hw, CTRL, ctrl);
7440} 7901}
7441 7902
7442#if 0
7443/*************************************************************************** 7903/***************************************************************************
7444 * 7904 *
7445 * Enables PCI-Express master access. 7905 * Enables PCI-Express master access.
@@ -7463,7 +7923,6 @@ e1000_enable_pciex_master(struct e1000_hw *hw)
7463 ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE; 7923 ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE;
7464 E1000_WRITE_REG(hw, CTRL, ctrl); 7924 E1000_WRITE_REG(hw, CTRL, ctrl);
7465} 7925}
7466#endif /* 0 */
7467 7926
7468/******************************************************************************* 7927/*******************************************************************************
7469 * 7928 *
@@ -7529,8 +7988,10 @@ e1000_get_auto_rd_done(struct e1000_hw *hw)
7529 case e1000_82572: 7988 case e1000_82572:
7530 case e1000_82573: 7989 case e1000_82573:
7531 case e1000_80003es2lan: 7990 case e1000_80003es2lan:
7532 while(timeout) { 7991 case e1000_ich8lan:
7533 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) break; 7992 while (timeout) {
7993 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
7994 break;
7534 else msec_delay(1); 7995 else msec_delay(1);
7535 timeout--; 7996 timeout--;
7536 } 7997 }
@@ -7570,7 +8031,7 @@ e1000_get_phy_cfg_done(struct e1000_hw *hw)
7570 8031
7571 switch (hw->mac_type) { 8032 switch (hw->mac_type) {
7572 default: 8033 default:
7573 msec_delay(10); 8034 msec_delay_irq(10);
7574 break; 8035 break;
7575 case e1000_80003es2lan: 8036 case e1000_80003es2lan:
7576 /* Separate *_CFG_DONE_* bit for each port */ 8037 /* Separate *_CFG_DONE_* bit for each port */
@@ -7753,6 +8214,13 @@ int32_t
7753e1000_check_phy_reset_block(struct e1000_hw *hw) 8214e1000_check_phy_reset_block(struct e1000_hw *hw)
7754{ 8215{
7755 uint32_t manc = 0; 8216 uint32_t manc = 0;
8217 uint32_t fwsm = 0;
8218
8219 if (hw->mac_type == e1000_ich8lan) {
8220 fwsm = E1000_READ_REG(hw, FWSM);
8221 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
8222 : E1000_BLK_PHY_RESET;
8223 }
7756 8224
7757 if (hw->mac_type > e1000_82547_rev_2) 8225 if (hw->mac_type > e1000_82547_rev_2)
7758 manc = E1000_READ_REG(hw, MANC); 8226 manc = E1000_READ_REG(hw, MANC);
@@ -7779,6 +8247,8 @@ e1000_arc_subsystem_valid(struct e1000_hw *hw)
7779 if((fwsm & E1000_FWSM_MODE_MASK) != 0) 8247 if((fwsm & E1000_FWSM_MODE_MASK) != 0)
7780 return TRUE; 8248 return TRUE;
7781 break; 8249 break;
8250 case e1000_ich8lan:
8251 return TRUE;
7782 default: 8252 default:
7783 break; 8253 break;
7784 } 8254 }
diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c
index cc0c77c4c170..f5c6f08966c7 100644
--- a/drivers/net/e1000/e1000_main.c
+++ b/drivers/net/e1000/e1000_main.c
@@ -366,6 +366,7 @@ e1000_release_hw_control(struct e1000_adapter *adapter)
366{ 366{
367 uint32_t ctrl_ext; 367 uint32_t ctrl_ext;
368 uint32_t swsm; 368 uint32_t swsm;
369 uint32_t extcnf;
369 370
370 /* Let firmware taken over control of h/w */ 371 /* Let firmware taken over control of h/w */
371 switch (adapter->hw.mac_type) { 372 switch (adapter->hw.mac_type) {
@@ -380,6 +381,11 @@ e1000_release_hw_control(struct e1000_adapter *adapter)
380 swsm = E1000_READ_REG(&adapter->hw, SWSM); 381 swsm = E1000_READ_REG(&adapter->hw, SWSM);
381 E1000_WRITE_REG(&adapter->hw, SWSM, 382 E1000_WRITE_REG(&adapter->hw, SWSM,
382 swsm & ~E1000_SWSM_DRV_LOAD); 383 swsm & ~E1000_SWSM_DRV_LOAD);
384 case e1000_ich8lan:
385 extcnf = E1000_READ_REG(&adapter->hw, CTRL_EXT);
386 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
387 extcnf & ~E1000_CTRL_EXT_DRV_LOAD);
388 break;
383 default: 389 default:
384 break; 390 break;
385 } 391 }
@@ -401,6 +407,7 @@ e1000_get_hw_control(struct e1000_adapter *adapter)
401{ 407{
402 uint32_t ctrl_ext; 408 uint32_t ctrl_ext;
403 uint32_t swsm; 409 uint32_t swsm;
410 uint32_t extcnf;
404 /* Let firmware know the driver has taken over */ 411 /* Let firmware know the driver has taken over */
405 switch (adapter->hw.mac_type) { 412 switch (adapter->hw.mac_type) {
406 case e1000_82571: 413 case e1000_82571:
@@ -415,6 +422,11 @@ e1000_get_hw_control(struct e1000_adapter *adapter)
415 E1000_WRITE_REG(&adapter->hw, SWSM, 422 E1000_WRITE_REG(&adapter->hw, SWSM,
416 swsm | E1000_SWSM_DRV_LOAD); 423 swsm | E1000_SWSM_DRV_LOAD);
417 break; 424 break;
425 case e1000_ich8lan:
426 extcnf = E1000_READ_REG(&adapter->hw, EXTCNF_CTRL);
427 E1000_WRITE_REG(&adapter->hw, EXTCNF_CTRL,
428 extcnf | E1000_EXTCNF_CTRL_SWFLAG);
429 break;
418 default: 430 default:
419 break; 431 break;
420 } 432 }
@@ -490,6 +502,7 @@ static void e1000_power_down_phy(struct e1000_adapter *adapter)
490 * (b) AMT is active 502 * (b) AMT is active
491 * (c) SoL/IDER session is active */ 503 * (c) SoL/IDER session is active */
492 if (!adapter->wol && adapter->hw.mac_type >= e1000_82540 && 504 if (!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
505 adapter->hw.mac_type != e1000_ich8lan &&
493 adapter->hw.media_type == e1000_media_type_copper && 506 adapter->hw.media_type == e1000_media_type_copper &&
494 !(E1000_READ_REG(&adapter->hw, MANC) & E1000_MANC_SMBUS_EN) && 507 !(E1000_READ_REG(&adapter->hw, MANC) & E1000_MANC_SMBUS_EN) &&
495 !mng_mode_enabled && 508 !mng_mode_enabled &&
@@ -561,6 +574,9 @@ e1000_reset(struct e1000_adapter *adapter)
561 case e1000_82573: 574 case e1000_82573:
562 pba = E1000_PBA_12K; 575 pba = E1000_PBA_12K;
563 break; 576 break;
577 case e1000_ich8lan:
578 pba = E1000_PBA_8K;
579 break;
564 default: 580 default:
565 pba = E1000_PBA_48K; 581 pba = E1000_PBA_48K;
566 break; 582 break;
@@ -585,6 +601,12 @@ e1000_reset(struct e1000_adapter *adapter)
585 /* Set the FC high water mark to 90% of the FIFO size. 601 /* Set the FC high water mark to 90% of the FIFO size.
586 * Required to clear last 3 LSB */ 602 * Required to clear last 3 LSB */
587 fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8; 603 fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8;
604 /* We can't use 90% on small FIFOs because the remainder
605 * would be less than 1 full frame. In this case, we size
606 * it to allow at least a full frame above the high water
607 * mark. */
608 if (pba < E1000_PBA_16K)
609 fc_high_water_mark = (pba * 1024) - 1600;
588 610
589 adapter->hw.fc_high_water = fc_high_water_mark; 611 adapter->hw.fc_high_water = fc_high_water_mark;
590 adapter->hw.fc_low_water = fc_high_water_mark - 8; 612 adapter->hw.fc_low_water = fc_high_water_mark - 8;
@@ -622,6 +644,8 @@ e1000_reset(struct e1000_adapter *adapter)
622 phy_data); 644 phy_data);
623 } 645 }
624 646
647 if (adapter->hw.mac_type < e1000_ich8lan)
648 /* FIXME: this code is duplicate and wrong for PCI Express */
625 if (adapter->en_mng_pt) { 649 if (adapter->en_mng_pt) {
626 manc = E1000_READ_REG(&adapter->hw, MANC); 650 manc = E1000_READ_REG(&adapter->hw, MANC);
627 manc |= (E1000_MANC_ARP_EN | E1000_MANC_EN_MNG2HOST); 651 manc |= (E1000_MANC_ARP_EN | E1000_MANC_EN_MNG2HOST);
@@ -648,6 +672,7 @@ e1000_probe(struct pci_dev *pdev,
648 struct net_device *netdev; 672 struct net_device *netdev;
649 struct e1000_adapter *adapter; 673 struct e1000_adapter *adapter;
650 unsigned long mmio_start, mmio_len; 674 unsigned long mmio_start, mmio_len;
675 unsigned long flash_start, flash_len;
651 676
652 static int cards_found = 0; 677 static int cards_found = 0;
653 static int e1000_ksp3_port_a = 0; /* global ksp3 port a indication */ 678 static int e1000_ksp3_port_a = 0; /* global ksp3 port a indication */
@@ -657,10 +682,12 @@ e1000_probe(struct pci_dev *pdev,
657 if ((err = pci_enable_device(pdev))) 682 if ((err = pci_enable_device(pdev)))
658 return err; 683 return err;
659 684
660 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) { 685 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)) &&
686 !(err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))) {
661 pci_using_dac = 1; 687 pci_using_dac = 1;
662 } else { 688 } else {
663 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) { 689 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) &&
690 (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) {
664 E1000_ERR("No usable DMA configuration, aborting\n"); 691 E1000_ERR("No usable DMA configuration, aborting\n");
665 return err; 692 return err;
666 } 693 }
@@ -740,6 +767,19 @@ e1000_probe(struct pci_dev *pdev,
740 if ((err = e1000_sw_init(adapter))) 767 if ((err = e1000_sw_init(adapter)))
741 goto err_sw_init; 768 goto err_sw_init;
742 769
770 /* Flash BAR mapping must happen after e1000_sw_init
771 * because it depends on mac_type */
772 if ((adapter->hw.mac_type == e1000_ich8lan) &&
773 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
774 flash_start = pci_resource_start(pdev, 1);
775 flash_len = pci_resource_len(pdev, 1);
776 adapter->hw.flash_address = ioremap(flash_start, flash_len);
777 if (!adapter->hw.flash_address) {
778 err = -EIO;
779 goto err_flashmap;
780 }
781 }
782
743 if ((err = e1000_check_phy_reset_block(&adapter->hw))) 783 if ((err = e1000_check_phy_reset_block(&adapter->hw)))
744 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n"); 784 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
745 785
@@ -758,6 +798,8 @@ e1000_probe(struct pci_dev *pdev,
758 NETIF_F_HW_VLAN_TX | 798 NETIF_F_HW_VLAN_TX |
759 NETIF_F_HW_VLAN_RX | 799 NETIF_F_HW_VLAN_RX |
760 NETIF_F_HW_VLAN_FILTER; 800 NETIF_F_HW_VLAN_FILTER;
801 if (adapter->hw.mac_type == e1000_ich8lan)
802 netdev->features &= ~NETIF_F_HW_VLAN_FILTER;
761 } 803 }
762 804
763#ifdef NETIF_F_TSO 805#ifdef NETIF_F_TSO
@@ -773,11 +815,17 @@ e1000_probe(struct pci_dev *pdev,
773 if (pci_using_dac) 815 if (pci_using_dac)
774 netdev->features |= NETIF_F_HIGHDMA; 816 netdev->features |= NETIF_F_HIGHDMA;
775 817
776 /* hard_start_xmit is safe against parallel locking */
777 netdev->features |= NETIF_F_LLTX; 818 netdev->features |= NETIF_F_LLTX;
778 819
779 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw); 820 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw);
780 821
822 /* initialize eeprom parameters */
823
824 if (e1000_init_eeprom_params(&adapter->hw)) {
825 E1000_ERR("EEPROM initialization failed\n");
826 return -EIO;
827 }
828
781 /* before reading the EEPROM, reset the controller to 829 /* before reading the EEPROM, reset the controller to
782 * put the device in a known good starting state */ 830 * put the device in a known good starting state */
783 831
@@ -845,6 +893,11 @@ e1000_probe(struct pci_dev *pdev,
845 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data); 893 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
846 eeprom_apme_mask = E1000_EEPROM_82544_APM; 894 eeprom_apme_mask = E1000_EEPROM_82544_APM;
847 break; 895 break;
896 case e1000_ich8lan:
897 e1000_read_eeprom(&adapter->hw,
898 EEPROM_INIT_CONTROL1_REG, 1, &eeprom_data);
899 eeprom_apme_mask = E1000_EEPROM_ICH8_APME;
900 break;
848 case e1000_82546: 901 case e1000_82546:
849 case e1000_82546_rev_3: 902 case e1000_82546_rev_3:
850 case e1000_82571: 903 case e1000_82571:
@@ -904,6 +957,9 @@ e1000_probe(struct pci_dev *pdev,
904 return 0; 957 return 0;
905 958
906err_register: 959err_register:
960 if (adapter->hw.flash_address)
961 iounmap(adapter->hw.flash_address);
962err_flashmap:
907err_sw_init: 963err_sw_init:
908err_eeprom: 964err_eeprom:
909 iounmap(adapter->hw.hw_addr); 965 iounmap(adapter->hw.hw_addr);
@@ -937,6 +993,7 @@ e1000_remove(struct pci_dev *pdev)
937 flush_scheduled_work(); 993 flush_scheduled_work();
938 994
939 if (adapter->hw.mac_type >= e1000_82540 && 995 if (adapter->hw.mac_type >= e1000_82540 &&
996 adapter->hw.mac_type != e1000_ich8lan &&
940 adapter->hw.media_type == e1000_media_type_copper) { 997 adapter->hw.media_type == e1000_media_type_copper) {
941 manc = E1000_READ_REG(&adapter->hw, MANC); 998 manc = E1000_READ_REG(&adapter->hw, MANC);
942 if (manc & E1000_MANC_SMBUS_EN) { 999 if (manc & E1000_MANC_SMBUS_EN) {
@@ -965,6 +1022,8 @@ e1000_remove(struct pci_dev *pdev)
965#endif 1022#endif
966 1023
967 iounmap(adapter->hw.hw_addr); 1024 iounmap(adapter->hw.hw_addr);
1025 if (adapter->hw.flash_address)
1026 iounmap(adapter->hw.flash_address);
968 pci_release_regions(pdev); 1027 pci_release_regions(pdev);
969 1028
970 free_netdev(netdev); 1029 free_netdev(netdev);
@@ -1015,13 +1074,6 @@ e1000_sw_init(struct e1000_adapter *adapter)
1015 return -EIO; 1074 return -EIO;
1016 } 1075 }
1017 1076
1018 /* initialize eeprom parameters */
1019
1020 if (e1000_init_eeprom_params(hw)) {
1021 E1000_ERR("EEPROM initialization failed\n");
1022 return -EIO;
1023 }
1024
1025 switch (hw->mac_type) { 1077 switch (hw->mac_type) {
1026 default: 1078 default:
1027 break; 1079 break;
@@ -1257,8 +1309,7 @@ e1000_setup_tx_resources(struct e1000_adapter *adapter,
1257 int size; 1309 int size;
1258 1310
1259 size = sizeof(struct e1000_buffer) * txdr->count; 1311 size = sizeof(struct e1000_buffer) * txdr->count;
1260 1312 txdr->buffer_info = vmalloc(size);
1261 txdr->buffer_info = vmalloc_node(size, pcibus_to_node(pdev->bus));
1262 if (!txdr->buffer_info) { 1313 if (!txdr->buffer_info) {
1263 DPRINTK(PROBE, ERR, 1314 DPRINTK(PROBE, ERR,
1264 "Unable to allocate memory for the transmit descriptor ring\n"); 1315 "Unable to allocate memory for the transmit descriptor ring\n");
@@ -1486,7 +1537,7 @@ e1000_setup_rx_resources(struct e1000_adapter *adapter,
1486 int size, desc_len; 1537 int size, desc_len;
1487 1538
1488 size = sizeof(struct e1000_buffer) * rxdr->count; 1539 size = sizeof(struct e1000_buffer) * rxdr->count;
1489 rxdr->buffer_info = vmalloc_node(size, pcibus_to_node(pdev->bus)); 1540 rxdr->buffer_info = vmalloc(size);
1490 if (!rxdr->buffer_info) { 1541 if (!rxdr->buffer_info) {
1491 DPRINTK(PROBE, ERR, 1542 DPRINTK(PROBE, ERR,
1492 "Unable to allocate memory for the receive descriptor ring\n"); 1543 "Unable to allocate memory for the receive descriptor ring\n");
@@ -2145,6 +2196,12 @@ e1000_set_multi(struct net_device *netdev)
2145 uint32_t rctl; 2196 uint32_t rctl;
2146 uint32_t hash_value; 2197 uint32_t hash_value;
2147 int i, rar_entries = E1000_RAR_ENTRIES; 2198 int i, rar_entries = E1000_RAR_ENTRIES;
2199 int mta_reg_count = (hw->mac_type == e1000_ich8lan) ?
2200 E1000_NUM_MTA_REGISTERS_ICH8LAN :
2201 E1000_NUM_MTA_REGISTERS;
2202
2203 if (adapter->hw.mac_type == e1000_ich8lan)
2204 rar_entries = E1000_RAR_ENTRIES_ICH8LAN;
2148 2205
2149 /* reserve RAR[14] for LAA over-write work-around */ 2206 /* reserve RAR[14] for LAA over-write work-around */
2150 if (adapter->hw.mac_type == e1000_82571) 2207 if (adapter->hw.mac_type == e1000_82571)
@@ -2191,7 +2248,7 @@ e1000_set_multi(struct net_device *netdev)
2191 2248
2192 /* clear the old settings from the multicast hash table */ 2249 /* clear the old settings from the multicast hash table */
2193 2250
2194 for (i = 0; i < E1000_NUM_MTA_REGISTERS; i++) { 2251 for (i = 0; i < mta_reg_count; i++) {
2195 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 2252 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
2196 E1000_WRITE_FLUSH(hw); 2253 E1000_WRITE_FLUSH(hw);
2197 } 2254 }
@@ -2270,8 +2327,16 @@ e1000_watchdog(unsigned long data)
2270 struct net_device *netdev = adapter->netdev; 2327 struct net_device *netdev = adapter->netdev;
2271 struct e1000_tx_ring *txdr = adapter->tx_ring; 2328 struct e1000_tx_ring *txdr = adapter->tx_ring;
2272 uint32_t link, tctl; 2329 uint32_t link, tctl;
2273 2330 int32_t ret_val;
2274 e1000_check_for_link(&adapter->hw); 2331
2332 ret_val = e1000_check_for_link(&adapter->hw);
2333 if ((ret_val == E1000_ERR_PHY) &&
2334 (adapter->hw.phy_type == e1000_phy_igp_3) &&
2335 (E1000_READ_REG(&adapter->hw, CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
2336 /* See e1000_kumeran_lock_loss_workaround() */
2337 DPRINTK(LINK, INFO,
2338 "Gigabit has been disabled, downgrading speed\n");
2339 }
2275 if (adapter->hw.mac_type == e1000_82573) { 2340 if (adapter->hw.mac_type == e1000_82573) {
2276 e1000_enable_tx_pkt_filtering(&adapter->hw); 2341 e1000_enable_tx_pkt_filtering(&adapter->hw);
2277 if (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id) 2342 if (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
@@ -2837,6 +2902,7 @@ e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2837 case e1000_82571: 2902 case e1000_82571:
2838 case e1000_82572: 2903 case e1000_82572:
2839 case e1000_82573: 2904 case e1000_82573:
2905 case e1000_ich8lan:
2840 pull_size = min((unsigned int)4, skb->data_len); 2906 pull_size = min((unsigned int)4, skb->data_len);
2841 if (!__pskb_pull_tail(skb, pull_size)) { 2907 if (!__pskb_pull_tail(skb, pull_size)) {
2842 DPRINTK(DRV, ERR, 2908 DPRINTK(DRV, ERR,
@@ -3021,6 +3087,7 @@ e1000_change_mtu(struct net_device *netdev, int new_mtu)
3021 /* Adapter-specific max frame size limits. */ 3087 /* Adapter-specific max frame size limits. */
3022 switch (adapter->hw.mac_type) { 3088 switch (adapter->hw.mac_type) {
3023 case e1000_undefined ... e1000_82542_rev2_1: 3089 case e1000_undefined ... e1000_82542_rev2_1:
3090 case e1000_ich8lan:
3024 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) { 3091 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
3025 DPRINTK(PROBE, ERR, "Jumbo Frames not supported.\n"); 3092 DPRINTK(PROBE, ERR, "Jumbo Frames not supported.\n");
3026 return -EINVAL; 3093 return -EINVAL;
@@ -3129,12 +3196,15 @@ e1000_update_stats(struct e1000_adapter *adapter)
3129 adapter->stats.bprc += E1000_READ_REG(hw, BPRC); 3196 adapter->stats.bprc += E1000_READ_REG(hw, BPRC);
3130 adapter->stats.mprc += E1000_READ_REG(hw, MPRC); 3197 adapter->stats.mprc += E1000_READ_REG(hw, MPRC);
3131 adapter->stats.roc += E1000_READ_REG(hw, ROC); 3198 adapter->stats.roc += E1000_READ_REG(hw, ROC);
3199
3200 if (adapter->hw.mac_type != e1000_ich8lan) {
3132 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64); 3201 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
3133 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127); 3202 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
3134 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255); 3203 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
3135 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511); 3204 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
3136 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023); 3205 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
3137 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522); 3206 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
3207 }
3138 3208
3139 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS); 3209 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
3140 adapter->stats.mpc += E1000_READ_REG(hw, MPC); 3210 adapter->stats.mpc += E1000_READ_REG(hw, MPC);
@@ -3162,12 +3232,16 @@ e1000_update_stats(struct e1000_adapter *adapter)
3162 adapter->stats.totl += E1000_READ_REG(hw, TOTL); 3232 adapter->stats.totl += E1000_READ_REG(hw, TOTL);
3163 adapter->stats.toth += E1000_READ_REG(hw, TOTH); 3233 adapter->stats.toth += E1000_READ_REG(hw, TOTH);
3164 adapter->stats.tpr += E1000_READ_REG(hw, TPR); 3234 adapter->stats.tpr += E1000_READ_REG(hw, TPR);
3235
3236 if (adapter->hw.mac_type != e1000_ich8lan) {
3165 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64); 3237 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
3166 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127); 3238 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
3167 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255); 3239 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
3168 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511); 3240 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
3169 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023); 3241 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
3170 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522); 3242 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
3243 }
3244
3171 adapter->stats.mptc += E1000_READ_REG(hw, MPTC); 3245 adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
3172 adapter->stats.bptc += E1000_READ_REG(hw, BPTC); 3246 adapter->stats.bptc += E1000_READ_REG(hw, BPTC);
3173 3247
@@ -3189,6 +3263,8 @@ e1000_update_stats(struct e1000_adapter *adapter)
3189 if (hw->mac_type > e1000_82547_rev_2) { 3263 if (hw->mac_type > e1000_82547_rev_2) {
3190 adapter->stats.iac += E1000_READ_REG(hw, IAC); 3264 adapter->stats.iac += E1000_READ_REG(hw, IAC);
3191 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC); 3265 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
3266
3267 if (adapter->hw.mac_type != e1000_ich8lan) {
3192 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC); 3268 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
3193 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC); 3269 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
3194 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC); 3270 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
@@ -3196,6 +3272,7 @@ e1000_update_stats(struct e1000_adapter *adapter)
3196 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC); 3272 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
3197 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC); 3273 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
3198 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC); 3274 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
3275 }
3199 } 3276 }
3200 3277
3201 /* Fill out the OS statistics structure */ 3278 /* Fill out the OS statistics structure */
@@ -4330,18 +4407,21 @@ e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4330 ctrl |= E1000_CTRL_VME; 4407 ctrl |= E1000_CTRL_VME;
4331 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl); 4408 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4332 4409
4410 if (adapter->hw.mac_type != e1000_ich8lan) {
4333 /* enable VLAN receive filtering */ 4411 /* enable VLAN receive filtering */
4334 rctl = E1000_READ_REG(&adapter->hw, RCTL); 4412 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4335 rctl |= E1000_RCTL_VFE; 4413 rctl |= E1000_RCTL_VFE;
4336 rctl &= ~E1000_RCTL_CFIEN; 4414 rctl &= ~E1000_RCTL_CFIEN;
4337 E1000_WRITE_REG(&adapter->hw, RCTL, rctl); 4415 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4338 e1000_update_mng_vlan(adapter); 4416 e1000_update_mng_vlan(adapter);
4417 }
4339 } else { 4418 } else {
4340 /* disable VLAN tag insert/strip */ 4419 /* disable VLAN tag insert/strip */
4341 ctrl = E1000_READ_REG(&adapter->hw, CTRL); 4420 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4342 ctrl &= ~E1000_CTRL_VME; 4421 ctrl &= ~E1000_CTRL_VME;
4343 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl); 4422 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4344 4423
4424 if (adapter->hw.mac_type != e1000_ich8lan) {
4345 /* disable VLAN filtering */ 4425 /* disable VLAN filtering */
4346 rctl = E1000_READ_REG(&adapter->hw, RCTL); 4426 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4347 rctl &= ~E1000_RCTL_VFE; 4427 rctl &= ~E1000_RCTL_VFE;
@@ -4350,6 +4430,7 @@ e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4350 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); 4430 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4351 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 4431 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4352 } 4432 }
4433 }
4353 } 4434 }
4354 4435
4355 e1000_irq_enable(adapter); 4436 e1000_irq_enable(adapter);
@@ -4578,7 +4659,9 @@ e1000_suspend(struct pci_dev *pdev, pm_message_t state)
4578 pci_enable_wake(pdev, PCI_D3cold, 0); 4659 pci_enable_wake(pdev, PCI_D3cold, 0);
4579 } 4660 }
4580 4661
4662 /* FIXME: this code is incorrect for PCI Express */
4581 if (adapter->hw.mac_type >= e1000_82540 && 4663 if (adapter->hw.mac_type >= e1000_82540 &&
4664 adapter->hw.mac_type != e1000_ich8lan &&
4582 adapter->hw.media_type == e1000_media_type_copper) { 4665 adapter->hw.media_type == e1000_media_type_copper) {
4583 manc = E1000_READ_REG(&adapter->hw, MANC); 4666 manc = E1000_READ_REG(&adapter->hw, MANC);
4584 if (manc & E1000_MANC_SMBUS_EN) { 4667 if (manc & E1000_MANC_SMBUS_EN) {
@@ -4589,6 +4672,9 @@ e1000_suspend(struct pci_dev *pdev, pm_message_t state)
4589 } 4672 }
4590 } 4673 }
4591 4674
4675 if (adapter->hw.phy_type == e1000_phy_igp_3)
4676 e1000_phy_powerdown_workaround(&adapter->hw);
4677
4592 /* Release control of h/w to f/w. If f/w is AMT enabled, this 4678 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4593 * would have already happened in close and is redundant. */ 4679 * would have already happened in close and is redundant. */
4594 e1000_release_hw_control(adapter); 4680 e1000_release_hw_control(adapter);
@@ -4624,7 +4710,9 @@ e1000_resume(struct pci_dev *pdev)
4624 4710
4625 netif_device_attach(netdev); 4711 netif_device_attach(netdev);
4626 4712
4713 /* FIXME: this code is incorrect for PCI Express */
4627 if (adapter->hw.mac_type >= e1000_82540 && 4714 if (adapter->hw.mac_type >= e1000_82540 &&
4715 adapter->hw.mac_type != e1000_ich8lan &&
4628 adapter->hw.media_type == e1000_media_type_copper) { 4716 adapter->hw.media_type == e1000_media_type_copper) {
4629 manc = E1000_READ_REG(&adapter->hw, MANC); 4717 manc = E1000_READ_REG(&adapter->hw, MANC);
4630 manc &= ~(E1000_MANC_ARP_EN); 4718 manc &= ~(E1000_MANC_ARP_EN);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-16 03:03:53 -0500