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authorDon Fry <pcnet32@verizon.net>2008-04-29 16:49:58 -0400
committerJeff Garzik <jgarzik@redhat.com>2008-05-06 12:22:39 -0400
commit01935d7d2c544a5dfc8313f79ed164d45115aa33 (patch)
tree9c6d959569403e85df6b84c913f7fa870e31c08d /drivers/net
parenta86e2cbe263c193a70b2e5c5a0c7e53ed39fc0ad (diff)
pcnet32: delete non NAPI code from driver.
Delete the non-napi code from the driver and Kconfig. Tested x86_64. Apply at next open opportunity. Signed-off-by: Don Fry <pcnet32@verizon.net> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/Kconfig14
-rw-r--r--drivers/net/pcnet32.c61
2 files changed, 4 insertions, 71 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index af46341827f2..d27f54a2df77 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1273,20 +1273,6 @@ config PCNET32
1273 To compile this driver as a module, choose M here. The module 1273 To compile this driver as a module, choose M here. The module
1274 will be called pcnet32. 1274 will be called pcnet32.
1275 1275
1276config PCNET32_NAPI
1277 bool "Use RX polling (NAPI)"
1278 depends on PCNET32
1279 help
1280 NAPI is a new driver API designed to reduce CPU and interrupt load
1281 when the driver is receiving lots of packets from the card. It is
1282 still somewhat experimental and thus not yet enabled by default.
1283
1284 If your estimated Rx load is 10kpps or more, or if the card will be
1285 deployed on potentially unfriendly networks (e.g. in a firewall),
1286 then say Y here.
1287
1288 If in doubt, say N.
1289
1290config AMD8111_ETH 1276config AMD8111_ETH
1291 tristate "AMD 8111 (new PCI lance) support" 1277 tristate "AMD 8111 (new PCI lance) support"
1292 depends on NET_PCI && PCI 1278 depends on NET_PCI && PCI
diff --git a/drivers/net/pcnet32.c b/drivers/net/pcnet32.c
index 4eb322e5273d..a1c454dbc164 100644
--- a/drivers/net/pcnet32.c
+++ b/drivers/net/pcnet32.c
@@ -22,12 +22,8 @@
22 *************************************************************************/ 22 *************************************************************************/
23 23
24#define DRV_NAME "pcnet32" 24#define DRV_NAME "pcnet32"
25#ifdef CONFIG_PCNET32_NAPI 25#define DRV_VERSION "1.35"
26#define DRV_VERSION "1.34-NAPI" 26#define DRV_RELDATE "21.Apr.2008"
27#else
28#define DRV_VERSION "1.34"
29#endif
30#define DRV_RELDATE "14.Aug.2007"
31#define PFX DRV_NAME ": " 27#define PFX DRV_NAME ": "
32 28
33static const char *const version = 29static const char *const version =
@@ -445,30 +441,24 @@ static struct pcnet32_access pcnet32_dwio = {
445 441
446static void pcnet32_netif_stop(struct net_device *dev) 442static void pcnet32_netif_stop(struct net_device *dev)
447{ 443{
448#ifdef CONFIG_PCNET32_NAPI
449 struct pcnet32_private *lp = netdev_priv(dev); 444 struct pcnet32_private *lp = netdev_priv(dev);
450#endif 445
451 dev->trans_start = jiffies; 446 dev->trans_start = jiffies;
452#ifdef CONFIG_PCNET32_NAPI
453 napi_disable(&lp->napi); 447 napi_disable(&lp->napi);
454#endif
455 netif_tx_disable(dev); 448 netif_tx_disable(dev);
456} 449}
457 450
458static void pcnet32_netif_start(struct net_device *dev) 451static void pcnet32_netif_start(struct net_device *dev)
459{ 452{
460#ifdef CONFIG_PCNET32_NAPI
461 struct pcnet32_private *lp = netdev_priv(dev); 453 struct pcnet32_private *lp = netdev_priv(dev);
462 ulong ioaddr = dev->base_addr; 454 ulong ioaddr = dev->base_addr;
463 u16 val; 455 u16 val;
464#endif 456
465 netif_wake_queue(dev); 457 netif_wake_queue(dev);
466#ifdef CONFIG_PCNET32_NAPI
467 val = lp->a.read_csr(ioaddr, CSR3); 458 val = lp->a.read_csr(ioaddr, CSR3);
468 val &= 0x00ff; 459 val &= 0x00ff;
469 lp->a.write_csr(ioaddr, CSR3, val); 460 lp->a.write_csr(ioaddr, CSR3, val);
470 napi_enable(&lp->napi); 461 napi_enable(&lp->napi);
471#endif
472} 462}
473 463
474/* 464/*
@@ -911,11 +901,7 @@ static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
911 rc = 1; /* default to fail */ 901 rc = 1; /* default to fail */
912 902
913 if (netif_running(dev)) 903 if (netif_running(dev))
914#ifdef CONFIG_PCNET32_NAPI
915 pcnet32_netif_stop(dev); 904 pcnet32_netif_stop(dev);
916#else
917 pcnet32_close(dev);
918#endif
919 905
920 spin_lock_irqsave(&lp->lock, flags); 906 spin_lock_irqsave(&lp->lock, flags);
921 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */ 907 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
@@ -1046,7 +1032,6 @@ static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
1046 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */ 1032 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
1047 a->write_bcr(ioaddr, 32, (x & ~0x0002)); 1033 a->write_bcr(ioaddr, 32, (x & ~0x0002));
1048 1034
1049#ifdef CONFIG_PCNET32_NAPI
1050 if (netif_running(dev)) { 1035 if (netif_running(dev)) {
1051 pcnet32_netif_start(dev); 1036 pcnet32_netif_start(dev);
1052 pcnet32_restart(dev, CSR0_NORMAL); 1037 pcnet32_restart(dev, CSR0_NORMAL);
@@ -1055,16 +1040,6 @@ static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
1055 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */ 1040 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1056 } 1041 }
1057 spin_unlock_irqrestore(&lp->lock, flags); 1042 spin_unlock_irqrestore(&lp->lock, flags);
1058#else
1059 if (netif_running(dev)) {
1060 spin_unlock_irqrestore(&lp->lock, flags);
1061 pcnet32_open(dev);
1062 } else {
1063 pcnet32_purge_rx_ring(dev);
1064 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1065 spin_unlock_irqrestore(&lp->lock, flags);
1066 }
1067#endif
1068 1043
1069 return (rc); 1044 return (rc);
1070} /* end pcnet32_loopback_test */ 1045} /* end pcnet32_loopback_test */
@@ -1270,11 +1245,7 @@ static void pcnet32_rx_entry(struct net_device *dev,
1270 } 1245 }
1271 dev->stats.rx_bytes += skb->len; 1246 dev->stats.rx_bytes += skb->len;
1272 skb->protocol = eth_type_trans(skb, dev); 1247 skb->protocol = eth_type_trans(skb, dev);
1273#ifdef CONFIG_PCNET32_NAPI
1274 netif_receive_skb(skb); 1248 netif_receive_skb(skb);
1275#else
1276 netif_rx(skb);
1277#endif
1278 dev->last_rx = jiffies; 1249 dev->last_rx = jiffies;
1279 dev->stats.rx_packets++; 1250 dev->stats.rx_packets++;
1280 return; 1251 return;
@@ -1403,7 +1374,6 @@ static int pcnet32_tx(struct net_device *dev)
1403 return must_restart; 1374 return must_restart;
1404} 1375}
1405 1376
1406#ifdef CONFIG_PCNET32_NAPI
1407static int pcnet32_poll(struct napi_struct *napi, int budget) 1377static int pcnet32_poll(struct napi_struct *napi, int budget)
1408{ 1378{
1409 struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi); 1379 struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
@@ -1442,7 +1412,6 @@ static int pcnet32_poll(struct napi_struct *napi, int budget)
1442 } 1412 }
1443 return work_done; 1413 return work_done;
1444} 1414}
1445#endif
1446 1415
1447#define PCNET32_REGS_PER_PHY 32 1416#define PCNET32_REGS_PER_PHY 32
1448#define PCNET32_MAX_PHYS 32 1417#define PCNET32_MAX_PHYS 32
@@ -1864,9 +1833,7 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1864 /* napi.weight is used in both the napi and non-napi cases */ 1833 /* napi.weight is used in both the napi and non-napi cases */
1865 lp->napi.weight = lp->rx_ring_size / 2; 1834 lp->napi.weight = lp->rx_ring_size / 2;
1866 1835
1867#ifdef CONFIG_PCNET32_NAPI
1868 netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2); 1836 netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
1869#endif
1870 1837
1871 if (fdx && !(lp->options & PCNET32_PORT_ASEL) && 1838 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1872 ((cards_found >= MAX_UNITS) || full_duplex[cards_found])) 1839 ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
@@ -2297,9 +2264,7 @@ static int pcnet32_open(struct net_device *dev)
2297 goto err_free_ring; 2264 goto err_free_ring;
2298 } 2265 }
2299 2266
2300#ifdef CONFIG_PCNET32_NAPI
2301 napi_enable(&lp->napi); 2267 napi_enable(&lp->napi);
2302#endif
2303 2268
2304 /* Re-initialize the PCNET32, and start it when done. */ 2269 /* Re-initialize the PCNET32, and start it when done. */
2305 lp->a.write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff)); 2270 lp->a.write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
@@ -2623,7 +2588,6 @@ pcnet32_interrupt(int irq, void *dev_id)
2623 dev->name, csr0); 2588 dev->name, csr0);
2624 /* unlike for the lance, there is no restart needed */ 2589 /* unlike for the lance, there is no restart needed */
2625 } 2590 }
2626#ifdef CONFIG_PCNET32_NAPI
2627 if (netif_rx_schedule_prep(dev, &lp->napi)) { 2591 if (netif_rx_schedule_prep(dev, &lp->napi)) {
2628 u16 val; 2592 u16 val;
2629 /* set interrupt masks */ 2593 /* set interrupt masks */
@@ -2634,24 +2598,9 @@ pcnet32_interrupt(int irq, void *dev_id)
2634 __netif_rx_schedule(dev, &lp->napi); 2598 __netif_rx_schedule(dev, &lp->napi);
2635 break; 2599 break;
2636 } 2600 }
2637#else
2638 pcnet32_rx(dev, lp->napi.weight);
2639 if (pcnet32_tx(dev)) {
2640 /* reset the chip to clear the error condition, then restart */
2641 lp->a.reset(ioaddr);
2642 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2643 pcnet32_restart(dev, CSR0_START);
2644 netif_wake_queue(dev);
2645 }
2646#endif
2647 csr0 = lp->a.read_csr(ioaddr, CSR0); 2601 csr0 = lp->a.read_csr(ioaddr, CSR0);
2648 } 2602 }
2649 2603
2650#ifndef CONFIG_PCNET32_NAPI
2651 /* Set interrupt enable. */
2652 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
2653#endif
2654
2655 if (netif_msg_intr(lp)) 2604 if (netif_msg_intr(lp))
2656 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n", 2605 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
2657 dev->name, lp->a.read_csr(ioaddr, CSR0)); 2606 dev->name, lp->a.read_csr(ioaddr, CSR0));
@@ -2670,9 +2619,7 @@ static int pcnet32_close(struct net_device *dev)
2670 del_timer_sync(&lp->watchdog_timer); 2619 del_timer_sync(&lp->watchdog_timer);
2671 2620
2672 netif_stop_queue(dev); 2621 netif_stop_queue(dev);
2673#ifdef CONFIG_PCNET32_NAPI
2674 napi_disable(&lp->napi); 2622 napi_disable(&lp->napi);
2675#endif
2676 2623
2677 spin_lock_irqsave(&lp->lock, flags); 2624 spin_lock_irqsave(&lp->lock, flags);
2678 2625