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authorDavid S. Miller <davem@davemloft.net>2005-05-19 01:49:26 -0400
committerDavid S. Miller <davem@davemloft.net>2005-05-19 01:49:26 -0400
commit15f9850d3c2d46f5851a424d2990a18b5bb5ebfd (patch)
treea96514f0f797e0a315e12450279d103a888d1083 /drivers/net
parentfac9b83ea79aa3112ed245d9a4fc2a5c3ec2b7ec (diff)
[TG3]: Set minimal hw interrupt mitigation.
Even though we do software interrupt mitigation via NAPI, it still helps to have some minimal hw assisted mitigation. This helps, particularly, on systems where register I/O overhead is much greater than the CPU horsepower. For example, it helps on NUMA systems. In such cases the PIO overhead to disable interrupts for NAPI accounts for the majority of the packet processing cost. The CPU is fast enough such that only a single packet is processed by each NAPI poll call. Thanks to Michael Chan for reviewing this patch. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/tg3.c72
-rw-r--r--drivers/net/tg3.h6
2 files changed, 64 insertions, 14 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 488b8c65252d..3df5b78d2693 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -2507,7 +2507,7 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2507 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { 2507 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2508 if (netif_carrier_ok(tp->dev)) { 2508 if (netif_carrier_ok(tp->dev)) {
2509 tw32(HOSTCC_STAT_COAL_TICKS, 2509 tw32(HOSTCC_STAT_COAL_TICKS,
2510 DEFAULT_STAT_COAL_TICKS); 2510 tp->coal.stats_block_coalesce_usecs);
2511 } else { 2511 } else {
2512 tw32(HOSTCC_STAT_COAL_TICKS, 0); 2512 tw32(HOSTCC_STAT_COAL_TICKS, 0);
2513 } 2513 }
@@ -5094,6 +5094,27 @@ static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5094} 5094}
5095 5095
5096static void __tg3_set_rx_mode(struct net_device *); 5096static void __tg3_set_rx_mode(struct net_device *);
5097static void tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
5098{
5099 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5100 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5101 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5102 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5103 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5104 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5105 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5106 }
5107 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5108 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5109 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5110 u32 val = ec->stats_block_coalesce_usecs;
5111
5112 if (!netif_carrier_ok(tp->dev))
5113 val = 0;
5114
5115 tw32(HOSTCC_STAT_COAL_TICKS, val);
5116 }
5117}
5097 5118
5098/* tp->lock is held. */ 5119/* tp->lock is held. */
5099static int tg3_reset_hw(struct tg3 *tp) 5120static int tg3_reset_hw(struct tg3 *tp)
@@ -5416,16 +5437,7 @@ static int tg3_reset_hw(struct tg3 *tp)
5416 udelay(10); 5437 udelay(10);
5417 } 5438 }
5418 5439
5419 tw32(HOSTCC_RXCOL_TICKS, 0); 5440 tg3_set_coalesce(tp, &tp->coal);
5420 tw32(HOSTCC_TXCOL_TICKS, LOW_TXCOL_TICKS);
5421 tw32(HOSTCC_RXMAX_FRAMES, 1);
5422 tw32(HOSTCC_TXMAX_FRAMES, LOW_RXMAX_FRAMES);
5423 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5424 tw32(HOSTCC_RXCOAL_TICK_INT, 0);
5425 tw32(HOSTCC_TXCOAL_TICK_INT, 0);
5426 }
5427 tw32(HOSTCC_RXCOAL_MAXF_INT, 1);
5428 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
5429 5441
5430 /* set status block DMA address */ 5442 /* set status block DMA address */
5431 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, 5443 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
@@ -5438,8 +5450,6 @@ static int tg3_reset_hw(struct tg3 *tp)
5438 * the tg3_periodic_fetch_stats call there, and 5450 * the tg3_periodic_fetch_stats call there, and
5439 * tg3_get_stats to see how this works for 5705/5750 chips. 5451 * tg3_get_stats to see how this works for 5705/5750 chips.
5440 */ 5452 */
5441 tw32(HOSTCC_STAT_COAL_TICKS,
5442 DEFAULT_STAT_COAL_TICKS);
5443 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, 5453 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5444 ((u64) tp->stats_mapping >> 32)); 5454 ((u64) tp->stats_mapping >> 32));
5445 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, 5455 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
@@ -7284,6 +7294,14 @@ static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
7284} 7294}
7285#endif 7295#endif
7286 7296
7297static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
7298{
7299 struct tg3 *tp = netdev_priv(dev);
7300
7301 memcpy(ec, &tp->coal, sizeof(*ec));
7302 return 0;
7303}
7304
7287static struct ethtool_ops tg3_ethtool_ops = { 7305static struct ethtool_ops tg3_ethtool_ops = {
7288 .get_settings = tg3_get_settings, 7306 .get_settings = tg3_get_settings,
7289 .set_settings = tg3_set_settings, 7307 .set_settings = tg3_set_settings,
@@ -7316,6 +7334,7 @@ static struct ethtool_ops tg3_ethtool_ops = {
7316 .get_strings = tg3_get_strings, 7334 .get_strings = tg3_get_strings,
7317 .get_stats_count = tg3_get_stats_count, 7335 .get_stats_count = tg3_get_stats_count,
7318 .get_ethtool_stats = tg3_get_ethtool_stats, 7336 .get_ethtool_stats = tg3_get_ethtool_stats,
7337 .get_coalesce = tg3_get_coalesce,
7319}; 7338};
7320 7339
7321static void __devinit tg3_get_eeprom_size(struct tg3 *tp) 7340static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
@@ -9096,6 +9115,31 @@ static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp)
9096 return peer; 9115 return peer;
9097} 9116}
9098 9117
9118static void __devinit tg3_init_coal(struct tg3 *tp)
9119{
9120 struct ethtool_coalesce *ec = &tp->coal;
9121
9122 memset(ec, 0, sizeof(*ec));
9123 ec->cmd = ETHTOOL_GCOALESCE;
9124 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
9125 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
9126 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
9127 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
9128 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
9129 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
9130 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
9131 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
9132 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
9133
9134 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
9135 HOSTCC_MODE_CLRTICK_TXBD)) {
9136 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
9137 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
9138 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
9139 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
9140 }
9141}
9142
9099static int __devinit tg3_init_one(struct pci_dev *pdev, 9143static int __devinit tg3_init_one(struct pci_dev *pdev,
9100 const struct pci_device_id *ent) 9144 const struct pci_device_id *ent)
9101{ 9145{
@@ -9341,6 +9385,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
9341 /* flow control autonegotiation is default behavior */ 9385 /* flow control autonegotiation is default behavior */
9342 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; 9386 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9343 9387
9388 tg3_init_coal(tp);
9389
9344 err = register_netdev(dev); 9390 err = register_netdev(dev);
9345 if (err) { 9391 if (err) {
9346 printk(KERN_ERR PFX "Cannot register net device, " 9392 printk(KERN_ERR PFX "Cannot register net device, "
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 44c65160a20f..993f84c93dc4 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -876,10 +876,12 @@
876#define HOSTCC_STATUS_ERROR_ATTN 0x00000004 876#define HOSTCC_STATUS_ERROR_ATTN 0x00000004
877#define HOSTCC_RXCOL_TICKS 0x00003c08 877#define HOSTCC_RXCOL_TICKS 0x00003c08
878#define LOW_RXCOL_TICKS 0x00000032 878#define LOW_RXCOL_TICKS 0x00000032
879#define LOW_RXCOL_TICKS_CLRTCKS 0x00000014
879#define DEFAULT_RXCOL_TICKS 0x00000048 880#define DEFAULT_RXCOL_TICKS 0x00000048
880#define HIGH_RXCOL_TICKS 0x00000096 881#define HIGH_RXCOL_TICKS 0x00000096
881#define HOSTCC_TXCOL_TICKS 0x00003c0c 882#define HOSTCC_TXCOL_TICKS 0x00003c0c
882#define LOW_TXCOL_TICKS 0x00000096 883#define LOW_TXCOL_TICKS 0x00000096
884#define LOW_TXCOL_TICKS_CLRTCKS 0x00000048
883#define DEFAULT_TXCOL_TICKS 0x0000012c 885#define DEFAULT_TXCOL_TICKS 0x0000012c
884#define HIGH_TXCOL_TICKS 0x00000145 886#define HIGH_TXCOL_TICKS 0x00000145
885#define HOSTCC_RXMAX_FRAMES 0x00003c10 887#define HOSTCC_RXMAX_FRAMES 0x00003c10
@@ -892,8 +894,10 @@
892#define HIGH_TXMAX_FRAMES 0x00000052 894#define HIGH_TXMAX_FRAMES 0x00000052
893#define HOSTCC_RXCOAL_TICK_INT 0x00003c18 895#define HOSTCC_RXCOAL_TICK_INT 0x00003c18
894#define DEFAULT_RXCOAL_TICK_INT 0x00000019 896#define DEFAULT_RXCOAL_TICK_INT 0x00000019
897#define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
895#define HOSTCC_TXCOAL_TICK_INT 0x00003c1c 898#define HOSTCC_TXCOAL_TICK_INT 0x00003c1c
896#define DEFAULT_TXCOAL_TICK_INT 0x00000019 899#define DEFAULT_TXCOAL_TICK_INT 0x00000019
900#define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
897#define HOSTCC_RXCOAL_MAXF_INT 0x00003c20 901#define HOSTCC_RXCOAL_MAXF_INT 0x00003c20
898#define DEFAULT_RXCOAL_MAXF_INT 0x00000005 902#define DEFAULT_RXCOAL_MAXF_INT 0x00000005
899#define HOSTCC_TXCOAL_MAXF_INT 0x00003c24 903#define HOSTCC_TXCOAL_MAXF_INT 0x00003c24
@@ -2227,7 +2231,7 @@ struct tg3 {
2227 2231
2228#define SST_25VF0X0_PAGE_SIZE 4098 2232#define SST_25VF0X0_PAGE_SIZE 4098
2229 2233
2230 2234 struct ethtool_coalesce coal;
2231}; 2235};
2232 2236
2233#endif /* !(_T3_H) */ 2237#endif /* !(_T3_H) */