diff options
author | Stefan Roese <sr@denx.de> | 2008-04-21 20:46:42 -0400 |
---|---|---|
committer | Jeff Garzik <jgarzik@redhat.com> | 2008-04-25 02:08:06 -0400 |
commit | afd1dee896e8b1cbd24258ac673aeccd803ff582 (patch) | |
tree | 50c27c031cf6b6011d38a53c340e4a3f49769418 /drivers/net | |
parent | f34ebab68a8e3c80ff4364f4c61734faec5161d4 (diff) |
ibm_newemac: Add support for 460EX/GT-type MAL rx-channel handling
On some 4xx PPC's (e.g. 460EX/GT), the rx channel number is a multiple
of 8 (e.g. 8 for EMAC1, 16 for EMAC2), but enabling in MAL_RXCASR needs
the divided by 8 value for the bitmask.
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/net')
-rw-r--r-- | drivers/net/ibm_newemac/mal.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/net/ibm_newemac/mal.c b/drivers/net/ibm_newemac/mal.c index 6869f08c9dcb..fb9c9eb114f4 100644 --- a/drivers/net/ibm_newemac/mal.c +++ b/drivers/net/ibm_newemac/mal.c | |||
@@ -136,6 +136,14 @@ void mal_enable_rx_channel(struct mal_instance *mal, int channel) | |||
136 | { | 136 | { |
137 | unsigned long flags; | 137 | unsigned long flags; |
138 | 138 | ||
139 | /* | ||
140 | * On some 4xx PPC's (e.g. 460EX/GT), the rx channel is a multiple | ||
141 | * of 8, but enabling in MAL_RXCASR needs the divided by 8 value | ||
142 | * for the bitmask | ||
143 | */ | ||
144 | if (!(channel % 8)) | ||
145 | channel >>= 3; | ||
146 | |||
139 | spin_lock_irqsave(&mal->lock, flags); | 147 | spin_lock_irqsave(&mal->lock, flags); |
140 | 148 | ||
141 | MAL_DBG(mal, "enable_rx(%d)" NL, channel); | 149 | MAL_DBG(mal, "enable_rx(%d)" NL, channel); |
@@ -148,6 +156,14 @@ void mal_enable_rx_channel(struct mal_instance *mal, int channel) | |||
148 | 156 | ||
149 | void mal_disable_rx_channel(struct mal_instance *mal, int channel) | 157 | void mal_disable_rx_channel(struct mal_instance *mal, int channel) |
150 | { | 158 | { |
159 | /* | ||
160 | * On some 4xx PPC's (e.g. 460EX/GT), the rx channel is a multiple | ||
161 | * of 8, but enabling in MAL_RXCASR needs the divided by 8 value | ||
162 | * for the bitmask | ||
163 | */ | ||
164 | if (!(channel % 8)) | ||
165 | channel >>= 3; | ||
166 | |||
151 | set_mal_dcrn(mal, MAL_RXCARR, MAL_CHAN_MASK(channel)); | 167 | set_mal_dcrn(mal, MAL_RXCARR, MAL_CHAN_MASK(channel)); |
152 | 168 | ||
153 | MAL_DBG(mal, "disable_rx(%d)" NL, channel); | 169 | MAL_DBG(mal, "disable_rx(%d)" NL, channel); |