diff options
author | Paul Mackerras <paulus@samba.org> | 2008-03-13 00:26:33 -0400 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2008-03-13 00:26:33 -0400 |
commit | bed04a4413376265746053be2a9cfbfc80c98ec9 (patch) | |
tree | 8f582294a655f70496cd08aedeb86de31dbad140 /drivers/net | |
parent | e37c772e36a7943b2e0bd8f48312e78474c0df15 (diff) | |
parent | c463be3520065ef8c05e3cbdf946c69604e91ceb (diff) |
Merge branch 'linux-2.6'
Diffstat (limited to 'drivers/net')
70 files changed, 3018 insertions, 1535 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index f337800076c0..fe7b5ec09708 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig | |||
@@ -90,6 +90,11 @@ config MACVLAN | |||
90 | This allows one to create virtual interfaces that map packets to | 90 | This allows one to create virtual interfaces that map packets to |
91 | or from specific MAC addresses to a particular interface. | 91 | or from specific MAC addresses to a particular interface. |
92 | 92 | ||
93 | Macvlan devices can be added using the "ip" command from the | ||
94 | iproute2 package starting with the iproute2-2.6.23 release: | ||
95 | |||
96 | "ip link add link <real dev> [ address MAC ] [ NAME ] type macvlan" | ||
97 | |||
93 | To compile this driver as a module, choose M here: the module | 98 | To compile this driver as a module, choose M here: the module |
94 | will be called macvlan. | 99 | will be called macvlan. |
95 | 100 | ||
@@ -2361,14 +2366,15 @@ config GELIC_NET | |||
2361 | module will be called ps3_gelic. | 2366 | module will be called ps3_gelic. |
2362 | 2367 | ||
2363 | config GELIC_WIRELESS | 2368 | config GELIC_WIRELESS |
2364 | bool "PS3 Wireless support" | 2369 | bool "PS3 Wireless support" |
2365 | depends on GELIC_NET | 2370 | depends on GELIC_NET |
2366 | help | 2371 | select WIRELESS_EXT |
2367 | This option adds the support for the wireless feature of PS3. | 2372 | help |
2368 | If you have the wireless-less model of PS3 or have no plan to | 2373 | This option adds the support for the wireless feature of PS3. |
2369 | use wireless feature, disabling this option saves memory. As | 2374 | If you have the wireless-less model of PS3 or have no plan to |
2370 | the driver automatically distinguishes the models, you can | 2375 | use wireless feature, disabling this option saves memory. As |
2371 | safely enable this option even if you have a wireless-less model. | 2376 | the driver automatically distinguishes the models, you can |
2377 | safely enable this option even if you have a wireless-less model. | ||
2372 | 2378 | ||
2373 | config GIANFAR | 2379 | config GIANFAR |
2374 | tristate "Gianfar Ethernet" | 2380 | tristate "Gianfar Ethernet" |
@@ -2513,7 +2519,7 @@ config CHELSIO_T3 | |||
2513 | 2519 | ||
2514 | config EHEA | 2520 | config EHEA |
2515 | tristate "eHEA Ethernet support" | 2521 | tristate "eHEA Ethernet support" |
2516 | depends on IBMEBUS && INET | 2522 | depends on IBMEBUS && INET && SPARSEMEM |
2517 | select INET_LRO | 2523 | select INET_LRO |
2518 | ---help--- | 2524 | ---help--- |
2519 | This driver supports the IBM pSeries eHEA ethernet adapter. | 2525 | This driver supports the IBM pSeries eHEA ethernet adapter. |
diff --git a/drivers/net/ac3200.c b/drivers/net/ac3200.c index 5136d94923aa..b1448637107f 100644 --- a/drivers/net/ac3200.c +++ b/drivers/net/ac3200.c | |||
@@ -369,7 +369,7 @@ MODULE_PARM_DESC(mem, "Memory base address(es)"); | |||
369 | MODULE_DESCRIPTION("Ansel AC3200 EISA ethernet driver"); | 369 | MODULE_DESCRIPTION("Ansel AC3200 EISA ethernet driver"); |
370 | MODULE_LICENSE("GPL"); | 370 | MODULE_LICENSE("GPL"); |
371 | 371 | ||
372 | int __init init_module(void) | 372 | static int __init ac3200_module_init(void) |
373 | { | 373 | { |
374 | struct net_device *dev; | 374 | struct net_device *dev; |
375 | int this_dev, found = 0; | 375 | int this_dev, found = 0; |
@@ -404,8 +404,7 @@ static void cleanup_card(struct net_device *dev) | |||
404 | iounmap(ei_status.mem); | 404 | iounmap(ei_status.mem); |
405 | } | 405 | } |
406 | 406 | ||
407 | void __exit | 407 | static void __exit ac3200_module_exit(void) |
408 | cleanup_module(void) | ||
409 | { | 408 | { |
410 | int this_dev; | 409 | int this_dev; |
411 | 410 | ||
@@ -418,4 +417,6 @@ cleanup_module(void) | |||
418 | } | 417 | } |
419 | } | 418 | } |
420 | } | 419 | } |
420 | module_init(ac3200_module_init); | ||
421 | module_exit(ac3200_module_exit); | ||
421 | #endif /* MODULE */ | 422 | #endif /* MODULE */ |
diff --git a/drivers/net/apne.c b/drivers/net/apne.c index c12cbdf368b1..47a8275d3962 100644 --- a/drivers/net/apne.c +++ b/drivers/net/apne.c | |||
@@ -569,7 +569,7 @@ static irqreturn_t apne_interrupt(int irq, void *dev_id) | |||
569 | #ifdef MODULE | 569 | #ifdef MODULE |
570 | static struct net_device *apne_dev; | 570 | static struct net_device *apne_dev; |
571 | 571 | ||
572 | int __init init_module(void) | 572 | static int __init apne_module_init(void) |
573 | { | 573 | { |
574 | apne_dev = apne_probe(-1); | 574 | apne_dev = apne_probe(-1); |
575 | if (IS_ERR(apne_dev)) | 575 | if (IS_ERR(apne_dev)) |
@@ -577,7 +577,7 @@ int __init init_module(void) | |||
577 | return 0; | 577 | return 0; |
578 | } | 578 | } |
579 | 579 | ||
580 | void __exit cleanup_module(void) | 580 | static void __exit apne_module_exit(void) |
581 | { | 581 | { |
582 | unregister_netdev(apne_dev); | 582 | unregister_netdev(apne_dev); |
583 | 583 | ||
@@ -591,7 +591,8 @@ void __exit cleanup_module(void) | |||
591 | 591 | ||
592 | free_netdev(apne_dev); | 592 | free_netdev(apne_dev); |
593 | } | 593 | } |
594 | 594 | module_init(apne_module_init); | |
595 | module_exit(apne_module_exit); | ||
595 | #endif | 596 | #endif |
596 | 597 | ||
597 | static int init_pcmcia(void) | 598 | static int init_pcmcia(void) |
diff --git a/drivers/net/appletalk/ltpc.c b/drivers/net/appletalk/ltpc.c index 6ab2c2d4d673..fef5560bc7a2 100644 --- a/drivers/net/appletalk/ltpc.c +++ b/drivers/net/appletalk/ltpc.c | |||
@@ -1252,7 +1252,7 @@ module_param(irq, int, 0); | |||
1252 | module_param(dma, int, 0); | 1252 | module_param(dma, int, 0); |
1253 | 1253 | ||
1254 | 1254 | ||
1255 | int __init init_module(void) | 1255 | static int __init ltpc_module_init(void) |
1256 | { | 1256 | { |
1257 | if(io == 0) | 1257 | if(io == 0) |
1258 | printk(KERN_NOTICE | 1258 | printk(KERN_NOTICE |
@@ -1263,6 +1263,7 @@ int __init init_module(void) | |||
1263 | return PTR_ERR(dev_ltpc); | 1263 | return PTR_ERR(dev_ltpc); |
1264 | return 0; | 1264 | return 0; |
1265 | } | 1265 | } |
1266 | module_init(ltpc_module_init); | ||
1266 | #endif | 1267 | #endif |
1267 | 1268 | ||
1268 | static void __exit ltpc_cleanup(void) | 1269 | static void __exit ltpc_cleanup(void) |
diff --git a/drivers/net/arcnet/capmode.c b/drivers/net/arcnet/capmode.c index cc4610db6395..02cb8f1c1148 100644 --- a/drivers/net/arcnet/capmode.c +++ b/drivers/net/arcnet/capmode.c | |||
@@ -80,17 +80,19 @@ void arcnet_cap_init(void) | |||
80 | 80 | ||
81 | #ifdef MODULE | 81 | #ifdef MODULE |
82 | 82 | ||
83 | int __init init_module(void) | 83 | static int __init capmode_module_init(void) |
84 | { | 84 | { |
85 | printk(VERSION); | 85 | printk(VERSION); |
86 | arcnet_cap_init(); | 86 | arcnet_cap_init(); |
87 | return 0; | 87 | return 0; |
88 | } | 88 | } |
89 | 89 | ||
90 | void cleanup_module(void) | 90 | static void __exit capmode_module_exit(void) |
91 | { | 91 | { |
92 | arcnet_unregister_proto(&capmode_proto); | 92 | arcnet_unregister_proto(&capmode_proto); |
93 | } | 93 | } |
94 | module_init(capmode_module_init); | ||
95 | module_exit(capmode_module_exit); | ||
94 | 96 | ||
95 | MODULE_LICENSE("GPL"); | 97 | MODULE_LICENSE("GPL"); |
96 | #endif /* MODULE */ | 98 | #endif /* MODULE */ |
diff --git a/drivers/net/atarilance.c b/drivers/net/atarilance.c index b74dbeef8050..13c293b286de 100644 --- a/drivers/net/atarilance.c +++ b/drivers/net/atarilance.c | |||
@@ -336,8 +336,6 @@ struct lance_addr { | |||
336 | 336 | ||
337 | /***************************** Prototypes *****************************/ | 337 | /***************************** Prototypes *****************************/ |
338 | 338 | ||
339 | static int addr_accessible( volatile void *regp, int wordflag, int | ||
340 | writeflag ); | ||
341 | static unsigned long lance_probe1( struct net_device *dev, struct lance_addr | 339 | static unsigned long lance_probe1( struct net_device *dev, struct lance_addr |
342 | *init_rec ); | 340 | *init_rec ); |
343 | static int lance_open( struct net_device *dev ); | 341 | static int lance_open( struct net_device *dev ); |
@@ -406,7 +404,8 @@ struct net_device * __init atarilance_probe(int unit) | |||
406 | 404 | ||
407 | /* Derived from hwreg_present() in atari/config.c: */ | 405 | /* Derived from hwreg_present() in atari/config.c: */ |
408 | 406 | ||
409 | static int __init addr_accessible( volatile void *regp, int wordflag, int writeflag ) | 407 | static noinline int __init addr_accessible(volatile void *regp, int wordflag, |
408 | int writeflag) | ||
410 | { | 409 | { |
411 | int ret; | 410 | int ret; |
412 | long flags; | 411 | long flags; |
diff --git a/drivers/net/bnx2x.c b/drivers/net/bnx2x.c index afc7f34b1dcf..8af142ccf373 100644 --- a/drivers/net/bnx2x.c +++ b/drivers/net/bnx2x.c | |||
@@ -1,6 +1,6 @@ | |||
1 | /* bnx2x.c: Broadcom Everest network driver. | 1 | /* bnx2x.c: Broadcom Everest network driver. |
2 | * | 2 | * |
3 | * Copyright (c) 2007 Broadcom Corporation | 3 | * Copyright (c) 2007-2008 Broadcom Corporation |
4 | * | 4 | * |
5 | * This program is free software; you can redistribute it and/or modify | 5 | * This program is free software; you can redistribute it and/or modify |
6 | * it under the terms of the GNU General Public License as published by | 6 | * it under the terms of the GNU General Public License as published by |
@@ -10,13 +10,13 @@ | |||
10 | * Based on code from Michael Chan's bnx2 driver | 10 | * Based on code from Michael Chan's bnx2 driver |
11 | * UDP CSUM errata workaround by Arik Gendelman | 11 | * UDP CSUM errata workaround by Arik Gendelman |
12 | * Slowpath rework by Vladislav Zolotarov | 12 | * Slowpath rework by Vladislav Zolotarov |
13 | * Statistics and Link managment by Yitchak Gertner | 13 | * Statistics and Link management by Yitchak Gertner |
14 | * | 14 | * |
15 | */ | 15 | */ |
16 | 16 | ||
17 | /* define this to make the driver freeze on error | 17 | /* define this to make the driver freeze on error |
18 | * to allow getting debug info | 18 | * to allow getting debug info |
19 | * (you will need to reboot afterwords) | 19 | * (you will need to reboot afterwards) |
20 | */ | 20 | */ |
21 | /*#define BNX2X_STOP_ON_ERROR*/ | 21 | /*#define BNX2X_STOP_ON_ERROR*/ |
22 | 22 | ||
@@ -63,22 +63,21 @@ | |||
63 | #include "bnx2x.h" | 63 | #include "bnx2x.h" |
64 | #include "bnx2x_init.h" | 64 | #include "bnx2x_init.h" |
65 | 65 | ||
66 | #define DRV_MODULE_VERSION "0.40.15" | 66 | #define DRV_MODULE_VERSION "1.40.22" |
67 | #define DRV_MODULE_RELDATE "$DateTime: 2007/11/15 07:28:37 $" | 67 | #define DRV_MODULE_RELDATE "2007/11/27" |
68 | #define BNX2X_BC_VER 0x040009 | 68 | #define BNX2X_BC_VER 0x040200 |
69 | 69 | ||
70 | /* Time in jiffies before concluding the transmitter is hung. */ | 70 | /* Time in jiffies before concluding the transmitter is hung. */ |
71 | #define TX_TIMEOUT (5*HZ) | 71 | #define TX_TIMEOUT (5*HZ) |
72 | 72 | ||
73 | static char version[] __devinitdata = | 73 | static char version[] __devinitdata = |
74 | "Broadcom NetXtreme II 577xx 10Gigabit Ethernet Driver " | 74 | "Broadcom NetXtreme II 5771X 10Gigabit Ethernet Driver " |
75 | DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; | 75 | DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; |
76 | 76 | ||
77 | MODULE_AUTHOR("Eliezer Tamir <eliezert@broadcom.com>"); | 77 | MODULE_AUTHOR("Eliezer Tamir <eliezert@broadcom.com>"); |
78 | MODULE_DESCRIPTION("Broadcom NetXtreme II BCM57710 Driver"); | 78 | MODULE_DESCRIPTION("Broadcom NetXtreme II BCM57710 Driver"); |
79 | MODULE_LICENSE("GPL"); | 79 | MODULE_LICENSE("GPL"); |
80 | MODULE_VERSION(DRV_MODULE_VERSION); | 80 | MODULE_VERSION(DRV_MODULE_VERSION); |
81 | MODULE_INFO(cvs_version, "$Revision: #356 $"); | ||
82 | 81 | ||
83 | static int use_inta; | 82 | static int use_inta; |
84 | static int poll; | 83 | static int poll; |
@@ -94,8 +93,8 @@ module_param(debug, int, 0); | |||
94 | MODULE_PARM_DESC(use_inta, "use INT#A instead of MSI-X"); | 93 | MODULE_PARM_DESC(use_inta, "use INT#A instead of MSI-X"); |
95 | MODULE_PARM_DESC(poll, "use polling (for debug)"); | 94 | MODULE_PARM_DESC(poll, "use polling (for debug)"); |
96 | MODULE_PARM_DESC(onefunc, "enable only first function"); | 95 | MODULE_PARM_DESC(onefunc, "enable only first function"); |
97 | MODULE_PARM_DESC(nomcp, "ignore managment CPU (Implies onefunc)"); | 96 | MODULE_PARM_DESC(nomcp, "ignore management CPU (Implies onefunc)"); |
98 | MODULE_PARM_DESC(debug, "defualt debug msglevel"); | 97 | MODULE_PARM_DESC(debug, "default debug msglevel"); |
99 | 98 | ||
100 | #ifdef BNX2X_MULTI | 99 | #ifdef BNX2X_MULTI |
101 | module_param(use_multi, int, 0); | 100 | module_param(use_multi, int, 0); |
@@ -298,8 +297,7 @@ static void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) | |||
298 | 297 | ||
299 | static int bnx2x_mc_assert(struct bnx2x *bp) | 298 | static int bnx2x_mc_assert(struct bnx2x *bp) |
300 | { | 299 | { |
301 | int i, j; | 300 | int i, j, rc = 0; |
302 | int rc = 0; | ||
303 | char last_idx; | 301 | char last_idx; |
304 | const char storm[] = {"XTCU"}; | 302 | const char storm[] = {"XTCU"}; |
305 | const u32 intmem_base[] = { | 303 | const u32 intmem_base[] = { |
@@ -313,8 +311,9 @@ static int bnx2x_mc_assert(struct bnx2x *bp) | |||
313 | for (i = 0; i < 4; i++) { | 311 | for (i = 0; i < 4; i++) { |
314 | last_idx = REG_RD8(bp, XSTORM_ASSERT_LIST_INDEX_OFFSET + | 312 | last_idx = REG_RD8(bp, XSTORM_ASSERT_LIST_INDEX_OFFSET + |
315 | intmem_base[i]); | 313 | intmem_base[i]); |
316 | BNX2X_ERR("DATA %cSTORM_ASSERT_LIST_INDEX 0x%x\n", | 314 | if (last_idx) |
317 | storm[i], last_idx); | 315 | BNX2X_LOG("DATA %cSTORM_ASSERT_LIST_INDEX 0x%x\n", |
316 | storm[i], last_idx); | ||
318 | 317 | ||
319 | /* print the asserts */ | 318 | /* print the asserts */ |
320 | for (j = 0; j < STROM_ASSERT_ARRAY_SIZE; j++) { | 319 | for (j = 0; j < STROM_ASSERT_ARRAY_SIZE; j++) { |
@@ -330,7 +329,7 @@ static int bnx2x_mc_assert(struct bnx2x *bp) | |||
330 | intmem_base[i]); | 329 | intmem_base[i]); |
331 | 330 | ||
332 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { | 331 | if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { |
333 | BNX2X_ERR("DATA %cSTORM_ASSERT_INDEX 0x%x =" | 332 | BNX2X_LOG("DATA %cSTORM_ASSERT_INDEX 0x%x =" |
334 | " 0x%08x 0x%08x 0x%08x 0x%08x\n", | 333 | " 0x%08x 0x%08x 0x%08x 0x%08x\n", |
335 | storm[i], j, row3, row2, row1, row0); | 334 | storm[i], j, row3, row2, row1, row0); |
336 | rc++; | 335 | rc++; |
@@ -341,6 +340,7 @@ static int bnx2x_mc_assert(struct bnx2x *bp) | |||
341 | } | 340 | } |
342 | return rc; | 341 | return rc; |
343 | } | 342 | } |
343 | |||
344 | static void bnx2x_fw_dump(struct bnx2x *bp) | 344 | static void bnx2x_fw_dump(struct bnx2x *bp) |
345 | { | 345 | { |
346 | u32 mark, offset; | 346 | u32 mark, offset; |
@@ -348,21 +348,22 @@ static void bnx2x_fw_dump(struct bnx2x *bp) | |||
348 | int word; | 348 | int word; |
349 | 349 | ||
350 | mark = REG_RD(bp, MCP_REG_MCPR_SCRATCH + 0xf104); | 350 | mark = REG_RD(bp, MCP_REG_MCPR_SCRATCH + 0xf104); |
351 | printk(KERN_ERR PFX "begin fw dump (mark 0x%x)\n", mark); | 351 | mark = ((mark + 0x3) & ~0x3); |
352 | printk(KERN_ERR PFX "begin fw dump (mark 0x%x)\n" KERN_ERR, mark); | ||
352 | 353 | ||
353 | for (offset = mark - 0x08000000; offset <= 0xF900; offset += 0x8*4) { | 354 | for (offset = mark - 0x08000000; offset <= 0xF900; offset += 0x8*4) { |
354 | for (word = 0; word < 8; word++) | 355 | for (word = 0; word < 8; word++) |
355 | data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH + | 356 | data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH + |
356 | offset + 4*word)); | 357 | offset + 4*word)); |
357 | data[8] = 0x0; | 358 | data[8] = 0x0; |
358 | printk(KERN_ERR PFX "%s", (char *)data); | 359 | printk(KERN_CONT "%s", (char *)data); |
359 | } | 360 | } |
360 | for (offset = 0xF108; offset <= mark - 0x08000000; offset += 0x8*4) { | 361 | for (offset = 0xF108; offset <= mark - 0x08000000; offset += 0x8*4) { |
361 | for (word = 0; word < 8; word++) | 362 | for (word = 0; word < 8; word++) |
362 | data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH + | 363 | data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH + |
363 | offset + 4*word)); | 364 | offset + 4*word)); |
364 | data[8] = 0x0; | 365 | data[8] = 0x0; |
365 | printk(KERN_ERR PFX "%s", (char *)data); | 366 | printk(KERN_CONT "%s", (char *)data); |
366 | } | 367 | } |
367 | printk("\n" KERN_ERR PFX "end of fw dump\n"); | 368 | printk("\n" KERN_ERR PFX "end of fw dump\n"); |
368 | } | 369 | } |
@@ -427,10 +428,10 @@ static void bnx2x_panic_dump(struct bnx2x *bp) | |||
427 | } | 428 | } |
428 | } | 429 | } |
429 | 430 | ||
430 | BNX2X_ERR("def_c_idx(%u) def_u_idx(%u) def_t_idx(%u)" | 431 | BNX2X_ERR("def_c_idx(%u) def_u_idx(%u) def_x_idx(%u)" |
431 | " def_x_idx(%u) def_att_idx(%u) attn_state(%u)" | 432 | " def_t_idx(%u) def_att_idx(%u) attn_state(%u)" |
432 | " spq_prod_idx(%u)\n", | 433 | " spq_prod_idx(%u)\n", |
433 | bp->def_c_idx, bp->def_u_idx, bp->def_t_idx, bp->def_x_idx, | 434 | bp->def_c_idx, bp->def_u_idx, bp->def_x_idx, bp->def_t_idx, |
434 | bp->def_att_idx, bp->attn_state, bp->spq_prod_idx); | 435 | bp->def_att_idx, bp->attn_state, bp->spq_prod_idx); |
435 | 436 | ||
436 | 437 | ||
@@ -441,7 +442,7 @@ static void bnx2x_panic_dump(struct bnx2x *bp) | |||
441 | DP(BNX2X_MSG_STATS, "stats_state - DISABLE\n"); | 442 | DP(BNX2X_MSG_STATS, "stats_state - DISABLE\n"); |
442 | } | 443 | } |
443 | 444 | ||
444 | static void bnx2x_enable_int(struct bnx2x *bp) | 445 | static void bnx2x_int_enable(struct bnx2x *bp) |
445 | { | 446 | { |
446 | int port = bp->port; | 447 | int port = bp->port; |
447 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; | 448 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
@@ -454,18 +455,26 @@ static void bnx2x_enable_int(struct bnx2x *bp) | |||
454 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | 455 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); |
455 | } else { | 456 | } else { |
456 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | | 457 | val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | |
458 | HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | | ||
457 | HC_CONFIG_0_REG_INT_LINE_EN_0 | | 459 | HC_CONFIG_0_REG_INT_LINE_EN_0 | |
458 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); | 460 | HC_CONFIG_0_REG_ATTN_BIT_EN_0); |
461 | |||
462 | /* Errata A0.158 workaround */ | ||
463 | DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) MSI-X %d\n", | ||
464 | val, port, addr, msix); | ||
465 | |||
466 | REG_WR(bp, addr, val); | ||
467 | |||
459 | val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; | 468 | val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; |
460 | } | 469 | } |
461 | 470 | ||
462 | DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) msi %d\n", | 471 | DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) MSI-X %d\n", |
463 | val, port, addr, msix); | 472 | val, port, addr, msix); |
464 | 473 | ||
465 | REG_WR(bp, addr, val); | 474 | REG_WR(bp, addr, val); |
466 | } | 475 | } |
467 | 476 | ||
468 | static void bnx2x_disable_int(struct bnx2x *bp) | 477 | static void bnx2x_int_disable(struct bnx2x *bp) |
469 | { | 478 | { |
470 | int port = bp->port; | 479 | int port = bp->port; |
471 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; | 480 | u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; |
@@ -484,15 +493,15 @@ static void bnx2x_disable_int(struct bnx2x *bp) | |||
484 | BNX2X_ERR("BUG! proper val not read from IGU!\n"); | 493 | BNX2X_ERR("BUG! proper val not read from IGU!\n"); |
485 | } | 494 | } |
486 | 495 | ||
487 | static void bnx2x_disable_int_sync(struct bnx2x *bp) | 496 | static void bnx2x_int_disable_sync(struct bnx2x *bp) |
488 | { | 497 | { |
489 | 498 | ||
490 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; | 499 | int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; |
491 | int i; | 500 | int i; |
492 | 501 | ||
493 | atomic_inc(&bp->intr_sem); | 502 | atomic_inc(&bp->intr_sem); |
494 | /* prevent the HW from sending interrupts*/ | 503 | /* prevent the HW from sending interrupts */ |
495 | bnx2x_disable_int(bp); | 504 | bnx2x_int_disable(bp); |
496 | 505 | ||
497 | /* make sure all ISRs are done */ | 506 | /* make sure all ISRs are done */ |
498 | if (msix) { | 507 | if (msix) { |
@@ -775,6 +784,7 @@ static void bnx2x_sp_event(struct bnx2x_fastpath *fp, | |||
775 | mb(); /* force bnx2x_wait_ramrod to see the change */ | 784 | mb(); /* force bnx2x_wait_ramrod to see the change */ |
776 | return; | 785 | return; |
777 | } | 786 | } |
787 | |||
778 | switch (command | bp->state) { | 788 | switch (command | bp->state) { |
779 | case (RAMROD_CMD_ID_ETH_PORT_SETUP | BNX2X_STATE_OPENING_WAIT4_PORT): | 789 | case (RAMROD_CMD_ID_ETH_PORT_SETUP | BNX2X_STATE_OPENING_WAIT4_PORT): |
780 | DP(NETIF_MSG_IFUP, "got setup ramrod\n"); | 790 | DP(NETIF_MSG_IFUP, "got setup ramrod\n"); |
@@ -787,20 +797,20 @@ static void bnx2x_sp_event(struct bnx2x_fastpath *fp, | |||
787 | fp->state = BNX2X_FP_STATE_HALTED; | 797 | fp->state = BNX2X_FP_STATE_HALTED; |
788 | break; | 798 | break; |
789 | 799 | ||
790 | case (RAMROD_CMD_ID_ETH_PORT_DEL | BNX2X_STATE_CLOSING_WAIT4_DELETE): | ||
791 | DP(NETIF_MSG_IFDOWN, "got delete ramrod\n"); | ||
792 | bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD; | ||
793 | break; | ||
794 | |||
795 | case (RAMROD_CMD_ID_ETH_CFC_DEL | BNX2X_STATE_CLOSING_WAIT4_HALT): | 800 | case (RAMROD_CMD_ID_ETH_CFC_DEL | BNX2X_STATE_CLOSING_WAIT4_HALT): |
796 | DP(NETIF_MSG_IFDOWN, "got delete ramrod for MULTI[%d]\n", cid); | 801 | DP(NETIF_MSG_IFDOWN, "got delete ramrod for MULTI[%d]\n", |
797 | bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_DELETED; | 802 | cid); |
803 | bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_CLOSED; | ||
798 | break; | 804 | break; |
799 | 805 | ||
800 | case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN): | 806 | case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN): |
801 | DP(NETIF_MSG_IFUP, "got set mac ramrod\n"); | 807 | DP(NETIF_MSG_IFUP, "got set mac ramrod\n"); |
802 | break; | 808 | break; |
803 | 809 | ||
810 | case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_CLOSING_WAIT4_HALT): | ||
811 | DP(NETIF_MSG_IFUP, "got (un)set mac ramrod\n"); | ||
812 | break; | ||
813 | |||
804 | default: | 814 | default: |
805 | BNX2X_ERR("unexpected ramrod (%d) state is %x\n", | 815 | BNX2X_ERR("unexpected ramrod (%d) state is %x\n", |
806 | command, bp->state); | 816 | command, bp->state); |
@@ -1179,12 +1189,175 @@ static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits) | |||
1179 | return val; | 1189 | return val; |
1180 | } | 1190 | } |
1181 | 1191 | ||
1192 | static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource) | ||
1193 | { | ||
1194 | u32 cnt; | ||
1195 | u32 lock_status; | ||
1196 | u32 resource_bit = (1 << resource); | ||
1197 | u8 func = bp->port; | ||
1198 | |||
1199 | /* Validating that the resource is within range */ | ||
1200 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | ||
1201 | DP(NETIF_MSG_HW, | ||
1202 | "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", | ||
1203 | resource, HW_LOCK_MAX_RESOURCE_VALUE); | ||
1204 | return -EINVAL; | ||
1205 | } | ||
1206 | |||
1207 | /* Validating that the resource is not already taken */ | ||
1208 | lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + func*8); | ||
1209 | if (lock_status & resource_bit) { | ||
1210 | DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", | ||
1211 | lock_status, resource_bit); | ||
1212 | return -EEXIST; | ||
1213 | } | ||
1214 | |||
1215 | /* Try for 1 second every 5ms */ | ||
1216 | for (cnt = 0; cnt < 200; cnt++) { | ||
1217 | /* Try to acquire the lock */ | ||
1218 | REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + func*8 + 4, | ||
1219 | resource_bit); | ||
1220 | lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + func*8); | ||
1221 | if (lock_status & resource_bit) | ||
1222 | return 0; | ||
1223 | |||
1224 | msleep(5); | ||
1225 | } | ||
1226 | DP(NETIF_MSG_HW, "Timeout\n"); | ||
1227 | return -EAGAIN; | ||
1228 | } | ||
1229 | |||
1230 | static int bnx2x_hw_unlock(struct bnx2x *bp, u32 resource) | ||
1231 | { | ||
1232 | u32 lock_status; | ||
1233 | u32 resource_bit = (1 << resource); | ||
1234 | u8 func = bp->port; | ||
1235 | |||
1236 | /* Validating that the resource is within range */ | ||
1237 | if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { | ||
1238 | DP(NETIF_MSG_HW, | ||
1239 | "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", | ||
1240 | resource, HW_LOCK_MAX_RESOURCE_VALUE); | ||
1241 | return -EINVAL; | ||
1242 | } | ||
1243 | |||
1244 | /* Validating that the resource is currently taken */ | ||
1245 | lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + func*8); | ||
1246 | if (!(lock_status & resource_bit)) { | ||
1247 | DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", | ||
1248 | lock_status, resource_bit); | ||
1249 | return -EFAULT; | ||
1250 | } | ||
1251 | |||
1252 | REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + func*8, resource_bit); | ||
1253 | return 0; | ||
1254 | } | ||
1255 | |||
1256 | static int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode) | ||
1257 | { | ||
1258 | /* The GPIO should be swapped if swap register is set and active */ | ||
1259 | int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && | ||
1260 | REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ bp->port; | ||
1261 | int gpio_shift = gpio_num + | ||
1262 | (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0); | ||
1263 | u32 gpio_mask = (1 << gpio_shift); | ||
1264 | u32 gpio_reg; | ||
1265 | |||
1266 | if (gpio_num > MISC_REGISTERS_GPIO_3) { | ||
1267 | BNX2X_ERR("Invalid GPIO %d\n", gpio_num); | ||
1268 | return -EINVAL; | ||
1269 | } | ||
1270 | |||
1271 | bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); | ||
1272 | /* read GPIO and mask except the float bits */ | ||
1273 | gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); | ||
1274 | |||
1275 | switch (mode) { | ||
1276 | case MISC_REGISTERS_GPIO_OUTPUT_LOW: | ||
1277 | DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n", | ||
1278 | gpio_num, gpio_shift); | ||
1279 | /* clear FLOAT and set CLR */ | ||
1280 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | ||
1281 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); | ||
1282 | break; | ||
1283 | |||
1284 | case MISC_REGISTERS_GPIO_OUTPUT_HIGH: | ||
1285 | DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n", | ||
1286 | gpio_num, gpio_shift); | ||
1287 | /* clear FLOAT and set SET */ | ||
1288 | gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | ||
1289 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); | ||
1290 | break; | ||
1291 | |||
1292 | case MISC_REGISTERS_GPIO_INPUT_HI_Z : | ||
1293 | DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n", | ||
1294 | gpio_num, gpio_shift); | ||
1295 | /* set FLOAT */ | ||
1296 | gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); | ||
1297 | break; | ||
1298 | |||
1299 | default: | ||
1300 | break; | ||
1301 | } | ||
1302 | |||
1303 | REG_WR(bp, MISC_REG_GPIO, gpio_reg); | ||
1304 | bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_GPIO); | ||
1305 | |||
1306 | return 0; | ||
1307 | } | ||
1308 | |||
1309 | static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode) | ||
1310 | { | ||
1311 | u32 spio_mask = (1 << spio_num); | ||
1312 | u32 spio_reg; | ||
1313 | |||
1314 | if ((spio_num < MISC_REGISTERS_SPIO_4) || | ||
1315 | (spio_num > MISC_REGISTERS_SPIO_7)) { | ||
1316 | BNX2X_ERR("Invalid SPIO %d\n", spio_num); | ||
1317 | return -EINVAL; | ||
1318 | } | ||
1319 | |||
1320 | bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); | ||
1321 | /* read SPIO and mask except the float bits */ | ||
1322 | spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT); | ||
1323 | |||
1324 | switch (mode) { | ||
1325 | case MISC_REGISTERS_SPIO_OUTPUT_LOW : | ||
1326 | DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num); | ||
1327 | /* clear FLOAT and set CLR */ | ||
1328 | spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); | ||
1329 | spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS); | ||
1330 | break; | ||
1331 | |||
1332 | case MISC_REGISTERS_SPIO_OUTPUT_HIGH : | ||
1333 | DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num); | ||
1334 | /* clear FLOAT and set SET */ | ||
1335 | spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); | ||
1336 | spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS); | ||
1337 | break; | ||
1338 | |||
1339 | case MISC_REGISTERS_SPIO_INPUT_HI_Z: | ||
1340 | DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num); | ||
1341 | /* set FLOAT */ | ||
1342 | spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); | ||
1343 | break; | ||
1344 | |||
1345 | default: | ||
1346 | break; | ||
1347 | } | ||
1348 | |||
1349 | REG_WR(bp, MISC_REG_SPIO, spio_reg); | ||
1350 | bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_SPIO); | ||
1351 | |||
1352 | return 0; | ||
1353 | } | ||
1354 | |||
1182 | static int bnx2x_mdio22_write(struct bnx2x *bp, u32 reg, u32 val) | 1355 | static int bnx2x_mdio22_write(struct bnx2x *bp, u32 reg, u32 val) |
1183 | { | 1356 | { |
1184 | int rc; | ||
1185 | u32 tmp, i; | ||
1186 | int port = bp->port; | 1357 | int port = bp->port; |
1187 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | 1358 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; |
1359 | u32 tmp; | ||
1360 | int i, rc; | ||
1188 | 1361 | ||
1189 | /* DP(NETIF_MSG_HW, "phy_addr 0x%x reg 0x%x val 0x%08x\n", | 1362 | /* DP(NETIF_MSG_HW, "phy_addr 0x%x reg 0x%x val 0x%08x\n", |
1190 | bp->phy_addr, reg, val); */ | 1363 | bp->phy_addr, reg, val); */ |
@@ -1236,8 +1409,8 @@ static int bnx2x_mdio22_read(struct bnx2x *bp, u32 reg, u32 *ret_val) | |||
1236 | { | 1409 | { |
1237 | int port = bp->port; | 1410 | int port = bp->port; |
1238 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | 1411 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; |
1239 | u32 val, i; | 1412 | u32 val; |
1240 | int rc; | 1413 | int i, rc; |
1241 | 1414 | ||
1242 | if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) { | 1415 | if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) { |
1243 | 1416 | ||
@@ -1286,58 +1459,54 @@ static int bnx2x_mdio22_read(struct bnx2x *bp, u32 reg, u32 *ret_val) | |||
1286 | return rc; | 1459 | return rc; |
1287 | } | 1460 | } |
1288 | 1461 | ||
1289 | static int bnx2x_mdio45_write(struct bnx2x *bp, u32 reg, u32 addr, u32 val) | 1462 | static int bnx2x_mdio45_ctrl_write(struct bnx2x *bp, u32 mdio_ctrl, |
1463 | u32 phy_addr, u32 reg, u32 addr, u32 val) | ||
1290 | { | 1464 | { |
1291 | int rc = 0; | 1465 | u32 tmp; |
1292 | u32 tmp, i; | 1466 | int i, rc = 0; |
1293 | int port = bp->port; | ||
1294 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | ||
1295 | |||
1296 | if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) { | ||
1297 | |||
1298 | tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); | ||
1299 | tmp &= ~EMAC_MDIO_MODE_AUTO_POLL; | ||
1300 | EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, tmp); | ||
1301 | REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); | ||
1302 | udelay(40); | ||
1303 | } | ||
1304 | 1467 | ||
1305 | /* set clause 45 mode */ | 1468 | /* set clause 45 mode, slow down the MDIO clock to 2.5MHz |
1306 | tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); | 1469 | * (a value of 49==0x31) and make sure that the AUTO poll is off |
1307 | tmp |= EMAC_MDIO_MODE_CLAUSE_45; | 1470 | */ |
1308 | EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, tmp); | 1471 | tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); |
1472 | tmp &= ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT); | ||
1473 | tmp |= (EMAC_MDIO_MODE_CLAUSE_45 | | ||
1474 | (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT)); | ||
1475 | REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp); | ||
1476 | REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); | ||
1477 | udelay(40); | ||
1309 | 1478 | ||
1310 | /* address */ | 1479 | /* address */ |
1311 | tmp = ((bp->phy_addr << 21) | (reg << 16) | addr | | 1480 | tmp = ((phy_addr << 21) | (reg << 16) | addr | |
1312 | EMAC_MDIO_COMM_COMMAND_ADDRESS | | 1481 | EMAC_MDIO_COMM_COMMAND_ADDRESS | |
1313 | EMAC_MDIO_COMM_START_BUSY); | 1482 | EMAC_MDIO_COMM_START_BUSY); |
1314 | EMAC_WR(EMAC_REG_EMAC_MDIO_COMM, tmp); | 1483 | REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); |
1315 | 1484 | ||
1316 | for (i = 0; i < 50; i++) { | 1485 | for (i = 0; i < 50; i++) { |
1317 | udelay(10); | 1486 | udelay(10); |
1318 | 1487 | ||
1319 | tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM); | 1488 | tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); |
1320 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { | 1489 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { |
1321 | udelay(5); | 1490 | udelay(5); |
1322 | break; | 1491 | break; |
1323 | } | 1492 | } |
1324 | } | 1493 | } |
1325 | |||
1326 | if (tmp & EMAC_MDIO_COMM_START_BUSY) { | 1494 | if (tmp & EMAC_MDIO_COMM_START_BUSY) { |
1327 | BNX2X_ERR("write phy register failed\n"); | 1495 | BNX2X_ERR("write phy register failed\n"); |
1328 | 1496 | ||
1329 | rc = -EBUSY; | 1497 | rc = -EBUSY; |
1498 | |||
1330 | } else { | 1499 | } else { |
1331 | /* data */ | 1500 | /* data */ |
1332 | tmp = ((bp->phy_addr << 21) | (reg << 16) | val | | 1501 | tmp = ((phy_addr << 21) | (reg << 16) | val | |
1333 | EMAC_MDIO_COMM_COMMAND_WRITE_45 | | 1502 | EMAC_MDIO_COMM_COMMAND_WRITE_45 | |
1334 | EMAC_MDIO_COMM_START_BUSY); | 1503 | EMAC_MDIO_COMM_START_BUSY); |
1335 | EMAC_WR(EMAC_REG_EMAC_MDIO_COMM, tmp); | 1504 | REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); |
1336 | 1505 | ||
1337 | for (i = 0; i < 50; i++) { | 1506 | for (i = 0; i < 50; i++) { |
1338 | udelay(10); | 1507 | udelay(10); |
1339 | 1508 | ||
1340 | tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM); | 1509 | tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); |
1341 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { | 1510 | if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { |
1342 | udelay(5); | 1511 | udelay(5); |
1343 | break; | 1512 | break; |
@@ -1351,75 +1520,78 @@ static int bnx2x_mdio45_write(struct bnx2x *bp, u32 reg, u32 addr, u32 val) | |||
1351 | } | 1520 | } |
1352 | } | 1521 | } |
1353 | 1522 | ||
1354 | /* unset clause 45 mode */ | 1523 | /* unset clause 45 mode, set the MDIO clock to a faster value |
1355 | tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); | 1524 | * (0x13 => 6.25Mhz) and restore the AUTO poll if needed |
1356 | tmp &= ~EMAC_MDIO_MODE_CLAUSE_45; | 1525 | */ |
1357 | EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, tmp); | 1526 | tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); |
1358 | 1527 | tmp &= ~(EMAC_MDIO_MODE_CLAUSE_45 | EMAC_MDIO_MODE_CLOCK_CNT); | |
1359 | if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) { | 1528 | tmp |= (0x13 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT); |
1360 | 1529 | if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) | |
1361 | tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); | ||
1362 | tmp |= EMAC_MDIO_MODE_AUTO_POLL; | 1530 | tmp |= EMAC_MDIO_MODE_AUTO_POLL; |
1363 | EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, tmp); | 1531 | REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp); |
1364 | } | ||
1365 | 1532 | ||
1366 | return rc; | 1533 | return rc; |
1367 | } | 1534 | } |
1368 | 1535 | ||
1369 | static int bnx2x_mdio45_read(struct bnx2x *bp, u32 reg, u32 addr, | 1536 | static int bnx2x_mdio45_write(struct bnx2x *bp, u32 phy_addr, u32 reg, |
1370 | u32 *ret_val) | 1537 | u32 addr, u32 val) |
1371 | { | 1538 | { |
1372 | int port = bp->port; | 1539 | u32 emac_base = bp->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; |
1373 | u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | ||
1374 | u32 val, i; | ||
1375 | int rc = 0; | ||
1376 | 1540 | ||
1377 | if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) { | 1541 | return bnx2x_mdio45_ctrl_write(bp, emac_base, phy_addr, |
1542 | reg, addr, val); | ||
1543 | } | ||
1378 | 1544 | ||
1379 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); | 1545 | static int bnx2x_mdio45_ctrl_read(struct bnx2x *bp, u32 mdio_ctrl, |
1380 | val &= ~EMAC_MDIO_MODE_AUTO_POLL; | 1546 | u32 phy_addr, u32 reg, u32 addr, |
1381 | EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, val); | 1547 | u32 *ret_val) |
1382 | REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); | 1548 | { |
1383 | udelay(40); | 1549 | u32 val; |
1384 | } | 1550 | int i, rc = 0; |
1385 | 1551 | ||
1386 | /* set clause 45 mode */ | 1552 | /* set clause 45 mode, slow down the MDIO clock to 2.5MHz |
1387 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); | 1553 | * (a value of 49==0x31) and make sure that the AUTO poll is off |
1388 | val |= EMAC_MDIO_MODE_CLAUSE_45; | 1554 | */ |
1389 | EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, val); | 1555 | val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); |
1556 | val &= ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT); | ||
1557 | val |= (EMAC_MDIO_MODE_CLAUSE_45 | | ||
1558 | (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT)); | ||
1559 | REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val); | ||
1560 | REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); | ||
1561 | udelay(40); | ||
1390 | 1562 | ||
1391 | /* address */ | 1563 | /* address */ |
1392 | val = ((bp->phy_addr << 21) | (reg << 16) | addr | | 1564 | val = ((phy_addr << 21) | (reg << 16) | addr | |
1393 | EMAC_MDIO_COMM_COMMAND_ADDRESS | | 1565 | EMAC_MDIO_COMM_COMMAND_ADDRESS | |
1394 | EMAC_MDIO_COMM_START_BUSY); | 1566 | EMAC_MDIO_COMM_START_BUSY); |
1395 | EMAC_WR(EMAC_REG_EMAC_MDIO_COMM, val); | 1567 | REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); |
1396 | 1568 | ||
1397 | for (i = 0; i < 50; i++) { | 1569 | for (i = 0; i < 50; i++) { |
1398 | udelay(10); | 1570 | udelay(10); |
1399 | 1571 | ||
1400 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM); | 1572 | val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); |
1401 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { | 1573 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { |
1402 | udelay(5); | 1574 | udelay(5); |
1403 | break; | 1575 | break; |
1404 | } | 1576 | } |
1405 | } | 1577 | } |
1406 | |||
1407 | if (val & EMAC_MDIO_COMM_START_BUSY) { | 1578 | if (val & EMAC_MDIO_COMM_START_BUSY) { |
1408 | BNX2X_ERR("read phy register failed\n"); | 1579 | BNX2X_ERR("read phy register failed\n"); |
1409 | 1580 | ||
1410 | *ret_val = 0; | 1581 | *ret_val = 0; |
1411 | rc = -EBUSY; | 1582 | rc = -EBUSY; |
1583 | |||
1412 | } else { | 1584 | } else { |
1413 | /* data */ | 1585 | /* data */ |
1414 | val = ((bp->phy_addr << 21) | (reg << 16) | | 1586 | val = ((phy_addr << 21) | (reg << 16) | |
1415 | EMAC_MDIO_COMM_COMMAND_READ_45 | | 1587 | EMAC_MDIO_COMM_COMMAND_READ_45 | |
1416 | EMAC_MDIO_COMM_START_BUSY); | 1588 | EMAC_MDIO_COMM_START_BUSY); |
1417 | EMAC_WR(EMAC_REG_EMAC_MDIO_COMM, val); | 1589 | REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); |
1418 | 1590 | ||
1419 | for (i = 0; i < 50; i++) { | 1591 | for (i = 0; i < 50; i++) { |
1420 | udelay(10); | 1592 | udelay(10); |
1421 | 1593 | ||
1422 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM); | 1594 | val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); |
1423 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { | 1595 | if (!(val & EMAC_MDIO_COMM_START_BUSY)) { |
1424 | val &= EMAC_MDIO_COMM_DATA; | 1596 | val &= EMAC_MDIO_COMM_DATA; |
1425 | break; | 1597 | break; |
@@ -1436,31 +1608,39 @@ static int bnx2x_mdio45_read(struct bnx2x *bp, u32 reg, u32 addr, | |||
1436 | *ret_val = val; | 1608 | *ret_val = val; |
1437 | } | 1609 | } |
1438 | 1610 | ||
1439 | /* unset clause 45 mode */ | 1611 | /* unset clause 45 mode, set the MDIO clock to a faster value |
1440 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); | 1612 | * (0x13 => 6.25Mhz) and restore the AUTO poll if needed |
1441 | val &= ~EMAC_MDIO_MODE_CLAUSE_45; | 1613 | */ |
1442 | EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, val); | 1614 | val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); |
1443 | 1615 | val &= ~(EMAC_MDIO_MODE_CLAUSE_45 | EMAC_MDIO_MODE_CLOCK_CNT); | |
1444 | if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) { | 1616 | val |= (0x13 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT); |
1445 | 1617 | if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) | |
1446 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); | ||
1447 | val |= EMAC_MDIO_MODE_AUTO_POLL; | 1618 | val |= EMAC_MDIO_MODE_AUTO_POLL; |
1448 | EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, val); | 1619 | REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val); |
1449 | } | ||
1450 | 1620 | ||
1451 | return rc; | 1621 | return rc; |
1452 | } | 1622 | } |
1453 | 1623 | ||
1454 | static int bnx2x_mdio45_vwrite(struct bnx2x *bp, u32 reg, u32 addr, u32 val) | 1624 | static int bnx2x_mdio45_read(struct bnx2x *bp, u32 phy_addr, u32 reg, |
1625 | u32 addr, u32 *ret_val) | ||
1626 | { | ||
1627 | u32 emac_base = bp->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; | ||
1628 | |||
1629 | return bnx2x_mdio45_ctrl_read(bp, emac_base, phy_addr, | ||
1630 | reg, addr, ret_val); | ||
1631 | } | ||
1632 | |||
1633 | static int bnx2x_mdio45_vwrite(struct bnx2x *bp, u32 phy_addr, u32 reg, | ||
1634 | u32 addr, u32 val) | ||
1455 | { | 1635 | { |
1456 | int i; | 1636 | int i; |
1457 | u32 rd_val; | 1637 | u32 rd_val; |
1458 | 1638 | ||
1459 | might_sleep(); | 1639 | might_sleep(); |
1460 | for (i = 0; i < 10; i++) { | 1640 | for (i = 0; i < 10; i++) { |
1461 | bnx2x_mdio45_write(bp, reg, addr, val); | 1641 | bnx2x_mdio45_write(bp, phy_addr, reg, addr, val); |
1462 | msleep(5); | 1642 | msleep(5); |
1463 | bnx2x_mdio45_read(bp, reg, addr, &rd_val); | 1643 | bnx2x_mdio45_read(bp, phy_addr, reg, addr, &rd_val); |
1464 | /* if the read value is not the same as the value we wrote, | 1644 | /* if the read value is not the same as the value we wrote, |
1465 | we should write it again */ | 1645 | we should write it again */ |
1466 | if (rd_val == val) | 1646 | if (rd_val == val) |
@@ -1471,18 +1651,81 @@ static int bnx2x_mdio45_vwrite(struct bnx2x *bp, u32 reg, u32 addr, u32 val) | |||
1471 | } | 1651 | } |
1472 | 1652 | ||
1473 | /* | 1653 | /* |
1474 | * link managment | 1654 | * link management |
1475 | */ | 1655 | */ |
1476 | 1656 | ||
1657 | static void bnx2x_pause_resolve(struct bnx2x *bp, u32 pause_result) | ||
1658 | { | ||
1659 | switch (pause_result) { /* ASYM P ASYM P */ | ||
1660 | case 0xb: /* 1 0 1 1 */ | ||
1661 | bp->flow_ctrl = FLOW_CTRL_TX; | ||
1662 | break; | ||
1663 | |||
1664 | case 0xe: /* 1 1 1 0 */ | ||
1665 | bp->flow_ctrl = FLOW_CTRL_RX; | ||
1666 | break; | ||
1667 | |||
1668 | case 0x5: /* 0 1 0 1 */ | ||
1669 | case 0x7: /* 0 1 1 1 */ | ||
1670 | case 0xd: /* 1 1 0 1 */ | ||
1671 | case 0xf: /* 1 1 1 1 */ | ||
1672 | bp->flow_ctrl = FLOW_CTRL_BOTH; | ||
1673 | break; | ||
1674 | |||
1675 | default: | ||
1676 | break; | ||
1677 | } | ||
1678 | } | ||
1679 | |||
1680 | static u8 bnx2x_ext_phy_resove_fc(struct bnx2x *bp) | ||
1681 | { | ||
1682 | u32 ext_phy_addr; | ||
1683 | u32 ld_pause; /* local */ | ||
1684 | u32 lp_pause; /* link partner */ | ||
1685 | u32 an_complete; /* AN complete */ | ||
1686 | u32 pause_result; | ||
1687 | u8 ret = 0; | ||
1688 | |||
1689 | ext_phy_addr = ((bp->ext_phy_config & | ||
1690 | PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> | ||
1691 | PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); | ||
1692 | |||
1693 | /* read twice */ | ||
1694 | bnx2x_mdio45_read(bp, ext_phy_addr, | ||
1695 | EXT_PHY_KR_AUTO_NEG_DEVAD, | ||
1696 | EXT_PHY_KR_STATUS, &an_complete); | ||
1697 | bnx2x_mdio45_read(bp, ext_phy_addr, | ||
1698 | EXT_PHY_KR_AUTO_NEG_DEVAD, | ||
1699 | EXT_PHY_KR_STATUS, &an_complete); | ||
1700 | |||
1701 | if (an_complete & EXT_PHY_KR_AUTO_NEG_COMPLETE) { | ||
1702 | ret = 1; | ||
1703 | bnx2x_mdio45_read(bp, ext_phy_addr, | ||
1704 | EXT_PHY_KR_AUTO_NEG_DEVAD, | ||
1705 | EXT_PHY_KR_AUTO_NEG_ADVERT, &ld_pause); | ||
1706 | bnx2x_mdio45_read(bp, ext_phy_addr, | ||
1707 | EXT_PHY_KR_AUTO_NEG_DEVAD, | ||
1708 | EXT_PHY_KR_LP_AUTO_NEG, &lp_pause); | ||
1709 | pause_result = (ld_pause & | ||
1710 | EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_MASK) >> 8; | ||
1711 | pause_result |= (lp_pause & | ||
1712 | EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_MASK) >> 10; | ||
1713 | DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x \n", | ||
1714 | pause_result); | ||
1715 | bnx2x_pause_resolve(bp, pause_result); | ||
1716 | } | ||
1717 | return ret; | ||
1718 | } | ||
1719 | |||
1477 | static void bnx2x_flow_ctrl_resolve(struct bnx2x *bp, u32 gp_status) | 1720 | static void bnx2x_flow_ctrl_resolve(struct bnx2x *bp, u32 gp_status) |
1478 | { | 1721 | { |
1479 | u32 ld_pause; /* local driver */ | 1722 | u32 ld_pause; /* local driver */ |
1480 | u32 lp_pause; /* link partner */ | 1723 | u32 lp_pause; /* link partner */ |
1481 | u32 pause_result; | 1724 | u32 pause_result; |
1482 | 1725 | ||
1483 | bp->flow_ctrl = 0; | 1726 | bp->flow_ctrl = 0; |
1484 | 1727 | ||
1485 | /* reolve from gp_status in case of AN complete and not sgmii */ | 1728 | /* resolve from gp_status in case of AN complete and not sgmii */ |
1486 | if ((bp->req_autoneg & AUTONEG_FLOW_CTRL) && | 1729 | if ((bp->req_autoneg & AUTONEG_FLOW_CTRL) && |
1487 | (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) && | 1730 | (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) && |
1488 | (!(bp->phy_flags & PHY_SGMII_FLAG)) && | 1731 | (!(bp->phy_flags & PHY_SGMII_FLAG)) && |
@@ -1499,45 +1742,57 @@ static void bnx2x_flow_ctrl_resolve(struct bnx2x *bp, u32 gp_status) | |||
1499 | pause_result |= (lp_pause & | 1742 | pause_result |= (lp_pause & |
1500 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; | 1743 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; |
1501 | DP(NETIF_MSG_LINK, "pause_result 0x%x\n", pause_result); | 1744 | DP(NETIF_MSG_LINK, "pause_result 0x%x\n", pause_result); |
1745 | bnx2x_pause_resolve(bp, pause_result); | ||
1746 | } else if (!(bp->req_autoneg & AUTONEG_FLOW_CTRL) || | ||
1747 | !(bnx2x_ext_phy_resove_fc(bp))) { | ||
1748 | /* forced speed */ | ||
1749 | if (bp->req_autoneg & AUTONEG_FLOW_CTRL) { | ||
1750 | switch (bp->req_flow_ctrl) { | ||
1751 | case FLOW_CTRL_AUTO: | ||
1752 | if (bp->dev->mtu <= 4500) | ||
1753 | bp->flow_ctrl = FLOW_CTRL_BOTH; | ||
1754 | else | ||
1755 | bp->flow_ctrl = FLOW_CTRL_TX; | ||
1756 | break; | ||
1502 | 1757 | ||
1503 | switch (pause_result) { /* ASYM P ASYM P */ | 1758 | case FLOW_CTRL_TX: |
1504 | case 0xb: /* 1 0 1 1 */ | 1759 | bp->flow_ctrl = FLOW_CTRL_TX; |
1505 | bp->flow_ctrl = FLOW_CTRL_TX; | 1760 | break; |
1506 | break; | ||
1507 | |||
1508 | case 0xe: /* 1 1 1 0 */ | ||
1509 | bp->flow_ctrl = FLOW_CTRL_RX; | ||
1510 | break; | ||
1511 | 1761 | ||
1512 | case 0x5: /* 0 1 0 1 */ | 1762 | case FLOW_CTRL_RX: |
1513 | case 0x7: /* 0 1 1 1 */ | 1763 | if (bp->dev->mtu <= 4500) |
1514 | case 0xd: /* 1 1 0 1 */ | 1764 | bp->flow_ctrl = FLOW_CTRL_RX; |
1515 | case 0xf: /* 1 1 1 1 */ | 1765 | break; |
1516 | bp->flow_ctrl = FLOW_CTRL_BOTH; | ||
1517 | break; | ||
1518 | 1766 | ||
1519 | default: | 1767 | case FLOW_CTRL_BOTH: |
1520 | break; | 1768 | if (bp->dev->mtu <= 4500) |
1521 | } | 1769 | bp->flow_ctrl = FLOW_CTRL_BOTH; |
1770 | else | ||
1771 | bp->flow_ctrl = FLOW_CTRL_TX; | ||
1772 | break; | ||
1522 | 1773 | ||
1523 | } else { /* forced mode */ | 1774 | case FLOW_CTRL_NONE: |
1524 | switch (bp->req_flow_ctrl) { | 1775 | default: |
1525 | case FLOW_CTRL_AUTO: | 1776 | break; |
1526 | if (bp->dev->mtu <= 4500) | 1777 | } |
1527 | bp->flow_ctrl = FLOW_CTRL_BOTH; | 1778 | } else { /* forced mode */ |
1528 | else | 1779 | switch (bp->req_flow_ctrl) { |
1529 | bp->flow_ctrl = FLOW_CTRL_TX; | 1780 | case FLOW_CTRL_AUTO: |
1530 | break; | 1781 | DP(NETIF_MSG_LINK, "req_flow_ctrl 0x%x while" |
1782 | " req_autoneg 0x%x\n", | ||
1783 | bp->req_flow_ctrl, bp->req_autoneg); | ||
1784 | break; | ||
1531 | 1785 | ||
1532 | case FLOW_CTRL_TX: | 1786 | case FLOW_CTRL_TX: |
1533 | case FLOW_CTRL_RX: | 1787 | case FLOW_CTRL_RX: |
1534 | case FLOW_CTRL_BOTH: | 1788 | case FLOW_CTRL_BOTH: |
1535 | bp->flow_ctrl = bp->req_flow_ctrl; | 1789 | bp->flow_ctrl = bp->req_flow_ctrl; |
1536 | break; | 1790 | break; |
1537 | 1791 | ||
1538 | case FLOW_CTRL_NONE: | 1792 | case FLOW_CTRL_NONE: |
1539 | default: | 1793 | default: |
1540 | break; | 1794 | break; |
1795 | } | ||
1541 | } | 1796 | } |
1542 | } | 1797 | } |
1543 | DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", bp->flow_ctrl); | 1798 | DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", bp->flow_ctrl); |
@@ -1548,9 +1803,9 @@ static void bnx2x_link_settings_status(struct bnx2x *bp, u32 gp_status) | |||
1548 | bp->link_status = 0; | 1803 | bp->link_status = 0; |
1549 | 1804 | ||
1550 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) { | 1805 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) { |
1551 | DP(NETIF_MSG_LINK, "link up\n"); | 1806 | DP(NETIF_MSG_LINK, "phy link up\n"); |
1552 | 1807 | ||
1553 | bp->link_up = 1; | 1808 | bp->phy_link_up = 1; |
1554 | bp->link_status |= LINK_STATUS_LINK_UP; | 1809 | bp->link_status |= LINK_STATUS_LINK_UP; |
1555 | 1810 | ||
1556 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) | 1811 | if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) |
@@ -1659,20 +1914,20 @@ static void bnx2x_link_settings_status(struct bnx2x *bp, u32 gp_status) | |||
1659 | bp->link_status |= LINK_STATUS_RX_FLOW_CONTROL_ENABLED; | 1914 | bp->link_status |= LINK_STATUS_RX_FLOW_CONTROL_ENABLED; |
1660 | 1915 | ||
1661 | } else { /* link_down */ | 1916 | } else { /* link_down */ |
1662 | DP(NETIF_MSG_LINK, "link down\n"); | 1917 | DP(NETIF_MSG_LINK, "phy link down\n"); |
1663 | 1918 | ||
1664 | bp->link_up = 0; | 1919 | bp->phy_link_up = 0; |
1665 | 1920 | ||
1666 | bp->line_speed = 0; | 1921 | bp->line_speed = 0; |
1667 | bp->duplex = DUPLEX_FULL; | 1922 | bp->duplex = DUPLEX_FULL; |
1668 | bp->flow_ctrl = 0; | 1923 | bp->flow_ctrl = 0; |
1669 | } | 1924 | } |
1670 | 1925 | ||
1671 | DP(NETIF_MSG_LINK, "gp_status 0x%x link_up %d\n" | 1926 | DP(NETIF_MSG_LINK, "gp_status 0x%x phy_link_up %d\n" |
1672 | DP_LEVEL " line_speed %d duplex %d flow_ctrl 0x%x" | 1927 | DP_LEVEL " line_speed %d duplex %d flow_ctrl 0x%x" |
1673 | " link_status 0x%x\n", | 1928 | " link_status 0x%x\n", |
1674 | gp_status, bp->link_up, bp->line_speed, bp->duplex, bp->flow_ctrl, | 1929 | gp_status, bp->phy_link_up, bp->line_speed, bp->duplex, |
1675 | bp->link_status); | 1930 | bp->flow_ctrl, bp->link_status); |
1676 | } | 1931 | } |
1677 | 1932 | ||
1678 | static void bnx2x_link_int_ack(struct bnx2x *bp, int is_10g) | 1933 | static void bnx2x_link_int_ack(struct bnx2x *bp, int is_10g) |
@@ -1680,40 +1935,40 @@ static void bnx2x_link_int_ack(struct bnx2x *bp, int is_10g) | |||
1680 | int port = bp->port; | 1935 | int port = bp->port; |
1681 | 1936 | ||
1682 | /* first reset all status | 1937 | /* first reset all status |
1683 | * we asume only one line will be change at a time */ | 1938 | * we assume only one line will be change at a time */ |
1684 | bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, | 1939 | bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, |
1685 | (NIG_XGXS0_LINK_STATUS | | 1940 | (NIG_STATUS_XGXS0_LINK10G | |
1686 | NIG_SERDES0_LINK_STATUS | | 1941 | NIG_STATUS_XGXS0_LINK_STATUS | |
1687 | NIG_STATUS_INTERRUPT_XGXS0_LINK10G)); | 1942 | NIG_STATUS_SERDES0_LINK_STATUS)); |
1688 | if (bp->link_up) { | 1943 | if (bp->phy_link_up) { |
1689 | if (is_10g) { | 1944 | if (is_10g) { |
1690 | /* Disable the 10G link interrupt | 1945 | /* Disable the 10G link interrupt |
1691 | * by writing 1 to the status register | 1946 | * by writing 1 to the status register |
1692 | */ | 1947 | */ |
1693 | DP(NETIF_MSG_LINK, "10G XGXS link up\n"); | 1948 | DP(NETIF_MSG_LINK, "10G XGXS phy link up\n"); |
1694 | bnx2x_bits_en(bp, | 1949 | bnx2x_bits_en(bp, |
1695 | NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, | 1950 | NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, |
1696 | NIG_STATUS_INTERRUPT_XGXS0_LINK10G); | 1951 | NIG_STATUS_XGXS0_LINK10G); |
1697 | 1952 | ||
1698 | } else if (bp->phy_flags & PHY_XGXS_FLAG) { | 1953 | } else if (bp->phy_flags & PHY_XGXS_FLAG) { |
1699 | /* Disable the link interrupt | 1954 | /* Disable the link interrupt |
1700 | * by writing 1 to the relevant lane | 1955 | * by writing 1 to the relevant lane |
1701 | * in the status register | 1956 | * in the status register |
1702 | */ | 1957 | */ |
1703 | DP(NETIF_MSG_LINK, "1G XGXS link up\n"); | 1958 | DP(NETIF_MSG_LINK, "1G XGXS phy link up\n"); |
1704 | bnx2x_bits_en(bp, | 1959 | bnx2x_bits_en(bp, |
1705 | NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, | 1960 | NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, |
1706 | ((1 << bp->ser_lane) << | 1961 | ((1 << bp->ser_lane) << |
1707 | NIG_XGXS0_LINK_STATUS_SIZE)); | 1962 | NIG_STATUS_XGXS0_LINK_STATUS_SIZE)); |
1708 | 1963 | ||
1709 | } else { /* SerDes */ | 1964 | } else { /* SerDes */ |
1710 | DP(NETIF_MSG_LINK, "SerDes link up\n"); | 1965 | DP(NETIF_MSG_LINK, "SerDes phy link up\n"); |
1711 | /* Disable the link interrupt | 1966 | /* Disable the link interrupt |
1712 | * by writing 1 to the status register | 1967 | * by writing 1 to the status register |
1713 | */ | 1968 | */ |
1714 | bnx2x_bits_en(bp, | 1969 | bnx2x_bits_en(bp, |
1715 | NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, | 1970 | NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, |
1716 | NIG_SERDES0_LINK_STATUS); | 1971 | NIG_STATUS_SERDES0_LINK_STATUS); |
1717 | } | 1972 | } |
1718 | 1973 | ||
1719 | } else { /* link_down */ | 1974 | } else { /* link_down */ |
@@ -1724,91 +1979,182 @@ static int bnx2x_ext_phy_is_link_up(struct bnx2x *bp) | |||
1724 | { | 1979 | { |
1725 | u32 ext_phy_type; | 1980 | u32 ext_phy_type; |
1726 | u32 ext_phy_addr; | 1981 | u32 ext_phy_addr; |
1727 | u32 local_phy; | 1982 | u32 val1 = 0, val2; |
1728 | u32 val = 0; | ||
1729 | u32 rx_sd, pcs_status; | 1983 | u32 rx_sd, pcs_status; |
1730 | 1984 | ||
1731 | if (bp->phy_flags & PHY_XGXS_FLAG) { | 1985 | if (bp->phy_flags & PHY_XGXS_FLAG) { |
1732 | local_phy = bp->phy_addr; | ||
1733 | ext_phy_addr = ((bp->ext_phy_config & | 1986 | ext_phy_addr = ((bp->ext_phy_config & |
1734 | PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> | 1987 | PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> |
1735 | PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); | 1988 | PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); |
1736 | bp->phy_addr = (u8)ext_phy_addr; | ||
1737 | 1989 | ||
1738 | ext_phy_type = XGXS_EXT_PHY_TYPE(bp); | 1990 | ext_phy_type = XGXS_EXT_PHY_TYPE(bp); |
1739 | switch (ext_phy_type) { | 1991 | switch (ext_phy_type) { |
1740 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: | 1992 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: |
1741 | DP(NETIF_MSG_LINK, "XGXS Direct\n"); | 1993 | DP(NETIF_MSG_LINK, "XGXS Direct\n"); |
1742 | val = 1; | 1994 | val1 = 1; |
1743 | break; | 1995 | break; |
1744 | 1996 | ||
1745 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: | 1997 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: |
1746 | DP(NETIF_MSG_LINK, "XGXS 8705\n"); | 1998 | DP(NETIF_MSG_LINK, "XGXS 8705\n"); |
1747 | bnx2x_mdio45_read(bp, EXT_PHY_OPT_WIS_DEVAD, | 1999 | bnx2x_mdio45_read(bp, ext_phy_addr, |
1748 | EXT_PHY_OPT_LASI_STATUS, &val); | 2000 | EXT_PHY_OPT_WIS_DEVAD, |
1749 | DP(NETIF_MSG_LINK, "8705 LASI status is %d\n", val); | 2001 | EXT_PHY_OPT_LASI_STATUS, &val1); |
1750 | 2002 | DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); | |
1751 | bnx2x_mdio45_read(bp, EXT_PHY_OPT_WIS_DEVAD, | 2003 | |
1752 | EXT_PHY_OPT_LASI_STATUS, &val); | 2004 | bnx2x_mdio45_read(bp, ext_phy_addr, |
1753 | DP(NETIF_MSG_LINK, "8705 LASI status is %d\n", val); | 2005 | EXT_PHY_OPT_WIS_DEVAD, |
1754 | 2006 | EXT_PHY_OPT_LASI_STATUS, &val1); | |
1755 | bnx2x_mdio45_read(bp, EXT_PHY_OPT_PMA_PMD_DEVAD, | 2007 | DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); |
2008 | |||
2009 | bnx2x_mdio45_read(bp, ext_phy_addr, | ||
2010 | EXT_PHY_OPT_PMA_PMD_DEVAD, | ||
1756 | EXT_PHY_OPT_PMD_RX_SD, &rx_sd); | 2011 | EXT_PHY_OPT_PMD_RX_SD, &rx_sd); |
1757 | val = (rx_sd & 0x1); | 2012 | DP(NETIF_MSG_LINK, "8705 rx_sd 0x%x\n", rx_sd); |
2013 | val1 = (rx_sd & 0x1); | ||
1758 | break; | 2014 | break; |
1759 | 2015 | ||
1760 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: | 2016 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: |
1761 | DP(NETIF_MSG_LINK, "XGXS 8706\n"); | 2017 | DP(NETIF_MSG_LINK, "XGXS 8706\n"); |
1762 | bnx2x_mdio45_read(bp, EXT_PHY_OPT_PMA_PMD_DEVAD, | 2018 | bnx2x_mdio45_read(bp, ext_phy_addr, |
1763 | EXT_PHY_OPT_LASI_STATUS, &val); | 2019 | EXT_PHY_OPT_PMA_PMD_DEVAD, |
1764 | DP(NETIF_MSG_LINK, "8706 LASI status is %d\n", val); | 2020 | EXT_PHY_OPT_LASI_STATUS, &val1); |
1765 | 2021 | DP(NETIF_MSG_LINK, "8706 LASI status 0x%x\n", val1); | |
1766 | bnx2x_mdio45_read(bp, EXT_PHY_OPT_PMA_PMD_DEVAD, | 2022 | |
1767 | EXT_PHY_OPT_LASI_STATUS, &val); | 2023 | bnx2x_mdio45_read(bp, ext_phy_addr, |
1768 | DP(NETIF_MSG_LINK, "8706 LASI status is %d\n", val); | 2024 | EXT_PHY_OPT_PMA_PMD_DEVAD, |
1769 | 2025 | EXT_PHY_OPT_LASI_STATUS, &val1); | |
1770 | bnx2x_mdio45_read(bp, EXT_PHY_OPT_PMA_PMD_DEVAD, | 2026 | DP(NETIF_MSG_LINK, "8706 LASI status 0x%x\n", val1); |
2027 | |||
2028 | bnx2x_mdio45_read(bp, ext_phy_addr, | ||
2029 | EXT_PHY_OPT_PMA_PMD_DEVAD, | ||
1771 | EXT_PHY_OPT_PMD_RX_SD, &rx_sd); | 2030 | EXT_PHY_OPT_PMD_RX_SD, &rx_sd); |
1772 | bnx2x_mdio45_read(bp, EXT_PHY_OPT_PCS_DEVAD, | 2031 | bnx2x_mdio45_read(bp, ext_phy_addr, |
1773 | EXT_PHY_OPT_PCS_STATUS, &pcs_status); | 2032 | EXT_PHY_OPT_PCS_DEVAD, |
2033 | EXT_PHY_OPT_PCS_STATUS, &pcs_status); | ||
2034 | bnx2x_mdio45_read(bp, ext_phy_addr, | ||
2035 | EXT_PHY_AUTO_NEG_DEVAD, | ||
2036 | EXT_PHY_OPT_AN_LINK_STATUS, &val2); | ||
2037 | |||
1774 | DP(NETIF_MSG_LINK, "8706 rx_sd 0x%x" | 2038 | DP(NETIF_MSG_LINK, "8706 rx_sd 0x%x" |
1775 | " pcs_status 0x%x\n", rx_sd, pcs_status); | 2039 | " pcs_status 0x%x 1Gbps link_status 0x%x 0x%x\n", |
1776 | /* link is up if both bit 0 of pmd_rx and | 2040 | rx_sd, pcs_status, val2, (val2 & (1<<1))); |
1777 | * bit 0 of pcs_status are set | 2041 | /* link is up if both bit 0 of pmd_rx_sd and |
2042 | * bit 0 of pcs_status are set, or if the autoneg bit | ||
2043 | 1 is set | ||
1778 | */ | 2044 | */ |
1779 | val = (rx_sd & pcs_status); | 2045 | val1 = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1))); |
2046 | break; | ||
2047 | |||
2048 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: | ||
2049 | bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO); | ||
2050 | |||
2051 | /* clear the interrupt LASI status register */ | ||
2052 | bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0, | ||
2053 | ext_phy_addr, | ||
2054 | EXT_PHY_KR_PCS_DEVAD, | ||
2055 | EXT_PHY_KR_LASI_STATUS, &val2); | ||
2056 | bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0, | ||
2057 | ext_phy_addr, | ||
2058 | EXT_PHY_KR_PCS_DEVAD, | ||
2059 | EXT_PHY_KR_LASI_STATUS, &val1); | ||
2060 | DP(NETIF_MSG_LINK, "KR LASI status 0x%x->0x%x\n", | ||
2061 | val2, val1); | ||
2062 | /* Check the LASI */ | ||
2063 | bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0, | ||
2064 | ext_phy_addr, | ||
2065 | EXT_PHY_KR_PMA_PMD_DEVAD, | ||
2066 | 0x9003, &val2); | ||
2067 | bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0, | ||
2068 | ext_phy_addr, | ||
2069 | EXT_PHY_KR_PMA_PMD_DEVAD, | ||
2070 | 0x9003, &val1); | ||
2071 | DP(NETIF_MSG_LINK, "KR 0x9003 0x%x->0x%x\n", | ||
2072 | val2, val1); | ||
2073 | /* Check the link status */ | ||
2074 | bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0, | ||
2075 | ext_phy_addr, | ||
2076 | EXT_PHY_KR_PCS_DEVAD, | ||
2077 | EXT_PHY_KR_PCS_STATUS, &val2); | ||
2078 | DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2); | ||
2079 | /* Check the link status on 1.1.2 */ | ||
2080 | bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0, | ||
2081 | ext_phy_addr, | ||
2082 | EXT_PHY_OPT_PMA_PMD_DEVAD, | ||
2083 | EXT_PHY_KR_STATUS, &val2); | ||
2084 | bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0, | ||
2085 | ext_phy_addr, | ||
2086 | EXT_PHY_OPT_PMA_PMD_DEVAD, | ||
2087 | EXT_PHY_KR_STATUS, &val1); | ||
2088 | DP(NETIF_MSG_LINK, | ||
2089 | "KR PMA status 0x%x->0x%x\n", val2, val1); | ||
2090 | val1 = ((val1 & 4) == 4); | ||
2091 | /* If 1G was requested assume the link is up */ | ||
2092 | if (!(bp->req_autoneg & AUTONEG_SPEED) && | ||
2093 | (bp->req_line_speed == SPEED_1000)) | ||
2094 | val1 = 1; | ||
2095 | bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_8072_MDIO); | ||
2096 | break; | ||
2097 | |||
2098 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: | ||
2099 | bnx2x_mdio45_read(bp, ext_phy_addr, | ||
2100 | EXT_PHY_OPT_PMA_PMD_DEVAD, | ||
2101 | EXT_PHY_OPT_LASI_STATUS, &val2); | ||
2102 | bnx2x_mdio45_read(bp, ext_phy_addr, | ||
2103 | EXT_PHY_OPT_PMA_PMD_DEVAD, | ||
2104 | EXT_PHY_OPT_LASI_STATUS, &val1); | ||
2105 | DP(NETIF_MSG_LINK, | ||
2106 | "10G-base-T LASI status 0x%x->0x%x\n", val2, val1); | ||
2107 | bnx2x_mdio45_read(bp, ext_phy_addr, | ||
2108 | EXT_PHY_OPT_PMA_PMD_DEVAD, | ||
2109 | EXT_PHY_KR_STATUS, &val2); | ||
2110 | bnx2x_mdio45_read(bp, ext_phy_addr, | ||
2111 | EXT_PHY_OPT_PMA_PMD_DEVAD, | ||
2112 | EXT_PHY_KR_STATUS, &val1); | ||
2113 | DP(NETIF_MSG_LINK, | ||
2114 | "10G-base-T PMA status 0x%x->0x%x\n", val2, val1); | ||
2115 | val1 = ((val1 & 4) == 4); | ||
2116 | /* if link is up | ||
2117 | * print the AN outcome of the SFX7101 PHY | ||
2118 | */ | ||
2119 | if (val1) { | ||
2120 | bnx2x_mdio45_read(bp, ext_phy_addr, | ||
2121 | EXT_PHY_KR_AUTO_NEG_DEVAD, | ||
2122 | 0x21, &val2); | ||
2123 | DP(NETIF_MSG_LINK, | ||
2124 | "SFX7101 AN status 0x%x->%s\n", val2, | ||
2125 | (val2 & (1<<14)) ? "Master" : "Slave"); | ||
2126 | } | ||
1780 | break; | 2127 | break; |
1781 | 2128 | ||
1782 | default: | 2129 | default: |
1783 | DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n", | 2130 | DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n", |
1784 | bp->ext_phy_config); | 2131 | bp->ext_phy_config); |
1785 | val = 0; | 2132 | val1 = 0; |
1786 | break; | 2133 | break; |
1787 | } | 2134 | } |
1788 | bp->phy_addr = local_phy; | ||
1789 | 2135 | ||
1790 | } else { /* SerDes */ | 2136 | } else { /* SerDes */ |
1791 | ext_phy_type = SERDES_EXT_PHY_TYPE(bp); | 2137 | ext_phy_type = SERDES_EXT_PHY_TYPE(bp); |
1792 | switch (ext_phy_type) { | 2138 | switch (ext_phy_type) { |
1793 | case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT: | 2139 | case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT: |
1794 | DP(NETIF_MSG_LINK, "SerDes Direct\n"); | 2140 | DP(NETIF_MSG_LINK, "SerDes Direct\n"); |
1795 | val = 1; | 2141 | val1 = 1; |
1796 | break; | 2142 | break; |
1797 | 2143 | ||
1798 | case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482: | 2144 | case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482: |
1799 | DP(NETIF_MSG_LINK, "SerDes 5482\n"); | 2145 | DP(NETIF_MSG_LINK, "SerDes 5482\n"); |
1800 | val = 1; | 2146 | val1 = 1; |
1801 | break; | 2147 | break; |
1802 | 2148 | ||
1803 | default: | 2149 | default: |
1804 | DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n", | 2150 | DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n", |
1805 | bp->ext_phy_config); | 2151 | bp->ext_phy_config); |
1806 | val = 0; | 2152 | val1 = 0; |
1807 | break; | 2153 | break; |
1808 | } | 2154 | } |
1809 | } | 2155 | } |
1810 | 2156 | ||
1811 | return val; | 2157 | return val1; |
1812 | } | 2158 | } |
1813 | 2159 | ||
1814 | static void bnx2x_bmac_enable(struct bnx2x *bp, int is_lb) | 2160 | static void bnx2x_bmac_enable(struct bnx2x *bp, int is_lb) |
@@ -1819,7 +2165,7 @@ static void bnx2x_bmac_enable(struct bnx2x *bp, int is_lb) | |||
1819 | u32 wb_write[2]; | 2165 | u32 wb_write[2]; |
1820 | u32 val; | 2166 | u32 val; |
1821 | 2167 | ||
1822 | DP(NETIF_MSG_LINK, "enableing BigMAC\n"); | 2168 | DP(NETIF_MSG_LINK, "enabling BigMAC\n"); |
1823 | /* reset and unreset the BigMac */ | 2169 | /* reset and unreset the BigMac */ |
1824 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | 2170 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
1825 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); | 2171 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); |
@@ -1933,6 +2279,35 @@ static void bnx2x_bmac_enable(struct bnx2x *bp, int is_lb) | |||
1933 | bp->stats_state = STATS_STATE_ENABLE; | 2279 | bp->stats_state = STATS_STATE_ENABLE; |
1934 | } | 2280 | } |
1935 | 2281 | ||
2282 | static void bnx2x_bmac_rx_disable(struct bnx2x *bp) | ||
2283 | { | ||
2284 | int port = bp->port; | ||
2285 | u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : | ||
2286 | NIG_REG_INGRESS_BMAC0_MEM; | ||
2287 | u32 wb_write[2]; | ||
2288 | |||
2289 | /* Only if the bmac is out of reset */ | ||
2290 | if (REG_RD(bp, MISC_REG_RESET_REG_2) & | ||
2291 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)) { | ||
2292 | /* Clear Rx Enable bit in BMAC_CONTROL register */ | ||
2293 | #ifdef BNX2X_DMAE_RD | ||
2294 | bnx2x_read_dmae(bp, bmac_addr + | ||
2295 | BIGMAC_REGISTER_BMAC_CONTROL, 2); | ||
2296 | wb_write[0] = *bnx2x_sp(bp, wb_data[0]); | ||
2297 | wb_write[1] = *bnx2x_sp(bp, wb_data[1]); | ||
2298 | #else | ||
2299 | wb_write[0] = REG_RD(bp, | ||
2300 | bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL); | ||
2301 | wb_write[1] = REG_RD(bp, | ||
2302 | bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL + 4); | ||
2303 | #endif | ||
2304 | wb_write[0] &= ~BMAC_CONTROL_RX_ENABLE; | ||
2305 | REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, | ||
2306 | wb_write, 2); | ||
2307 | msleep(1); | ||
2308 | } | ||
2309 | } | ||
2310 | |||
1936 | static void bnx2x_emac_enable(struct bnx2x *bp) | 2311 | static void bnx2x_emac_enable(struct bnx2x *bp) |
1937 | { | 2312 | { |
1938 | int port = bp->port; | 2313 | int port = bp->port; |
@@ -1940,7 +2315,7 @@ static void bnx2x_emac_enable(struct bnx2x *bp) | |||
1940 | u32 val; | 2315 | u32 val; |
1941 | int timeout; | 2316 | int timeout; |
1942 | 2317 | ||
1943 | DP(NETIF_MSG_LINK, "enableing EMAC\n"); | 2318 | DP(NETIF_MSG_LINK, "enabling EMAC\n"); |
1944 | /* reset and unreset the emac core */ | 2319 | /* reset and unreset the emac core */ |
1945 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | 2320 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
1946 | (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); | 2321 | (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); |
@@ -2033,7 +2408,7 @@ static void bnx2x_emac_enable(struct bnx2x *bp) | |||
2033 | EMAC_TX_MODE_EXT_PAUSE_EN); | 2408 | EMAC_TX_MODE_EXT_PAUSE_EN); |
2034 | } | 2409 | } |
2035 | 2410 | ||
2036 | /* KEEP_VLAN_TAG, promiscous */ | 2411 | /* KEEP_VLAN_TAG, promiscuous */ |
2037 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); | 2412 | val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); |
2038 | val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; | 2413 | val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; |
2039 | EMAC_WR(EMAC_REG_EMAC_RX_MODE, val); | 2414 | EMAC_WR(EMAC_REG_EMAC_RX_MODE, val); |
@@ -2161,7 +2536,6 @@ static void bnx2x_pbf_update(struct bnx2x *bp) | |||
2161 | u32 count = 1000; | 2536 | u32 count = 1000; |
2162 | u32 pause = 0; | 2537 | u32 pause = 0; |
2163 | 2538 | ||
2164 | |||
2165 | /* disable port */ | 2539 | /* disable port */ |
2166 | REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); | 2540 | REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); |
2167 | 2541 | ||
@@ -2232,7 +2606,7 @@ static void bnx2x_pbf_update(struct bnx2x *bp) | |||
2232 | static void bnx2x_update_mng(struct bnx2x *bp) | 2606 | static void bnx2x_update_mng(struct bnx2x *bp) |
2233 | { | 2607 | { |
2234 | if (!nomcp) | 2608 | if (!nomcp) |
2235 | SHMEM_WR(bp, drv_fw_mb[bp->port].link_status, | 2609 | SHMEM_WR(bp, port_mb[bp->port].link_status, |
2236 | bp->link_status); | 2610 | bp->link_status); |
2237 | } | 2611 | } |
2238 | 2612 | ||
@@ -2294,19 +2668,19 @@ static void bnx2x_link_down(struct bnx2x *bp) | |||
2294 | DP(BNX2X_MSG_STATS, "stats_state - STOP\n"); | 2668 | DP(BNX2X_MSG_STATS, "stats_state - STOP\n"); |
2295 | } | 2669 | } |
2296 | 2670 | ||
2297 | /* indicate link down */ | 2671 | /* indicate no mac active */ |
2298 | bp->phy_flags &= ~(PHY_BMAC_FLAG | PHY_EMAC_FLAG); | 2672 | bp->phy_flags &= ~(PHY_BMAC_FLAG | PHY_EMAC_FLAG); |
2299 | 2673 | ||
2300 | /* reset BigMac */ | 2674 | /* update shared memory */ |
2301 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | 2675 | bnx2x_update_mng(bp); |
2302 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); | ||
2303 | 2676 | ||
2304 | /* ignore drain flag interrupt */ | ||
2305 | /* activate nig drain */ | 2677 | /* activate nig drain */ |
2306 | NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); | 2678 | NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); |
2307 | 2679 | ||
2308 | /* update shared memory */ | 2680 | /* reset BigMac */ |
2309 | bnx2x_update_mng(bp); | 2681 | bnx2x_bmac_rx_disable(bp); |
2682 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, | ||
2683 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); | ||
2310 | 2684 | ||
2311 | /* indicate link down */ | 2685 | /* indicate link down */ |
2312 | bnx2x_link_report(bp); | 2686 | bnx2x_link_report(bp); |
@@ -2317,14 +2691,15 @@ static void bnx2x_init_mac_stats(struct bnx2x *bp); | |||
2317 | /* This function is called upon link interrupt */ | 2691 | /* This function is called upon link interrupt */ |
2318 | static void bnx2x_link_update(struct bnx2x *bp) | 2692 | static void bnx2x_link_update(struct bnx2x *bp) |
2319 | { | 2693 | { |
2320 | u32 gp_status; | ||
2321 | int port = bp->port; | 2694 | int port = bp->port; |
2322 | int i; | 2695 | int i; |
2696 | u32 gp_status; | ||
2323 | int link_10g; | 2697 | int link_10g; |
2324 | 2698 | ||
2325 | DP(NETIF_MSG_LINK, "port %x, is xgxs %x, stat_mask 0x%x," | 2699 | DP(NETIF_MSG_LINK, "port %x, %s, int_status 0x%x," |
2326 | " int_mask 0x%x, saved_mask 0x%x, MI_INT %x, SERDES_LINK %x," | 2700 | " int_mask 0x%x, saved_mask 0x%x, MI_INT %x, SERDES_LINK %x," |
2327 | " 10G %x, XGXS_LINK %x\n", port, (bp->phy_flags & PHY_XGXS_FLAG), | 2701 | " 10G %x, XGXS_LINK %x\n", port, |
2702 | (bp->phy_flags & PHY_XGXS_FLAG)? "XGXS":"SerDes", | ||
2328 | REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4), | 2703 | REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4), |
2329 | REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), bp->nig_mask, | 2704 | REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), bp->nig_mask, |
2330 | REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), | 2705 | REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), |
@@ -2336,7 +2711,7 @@ static void bnx2x_link_update(struct bnx2x *bp) | |||
2336 | might_sleep(); | 2711 | might_sleep(); |
2337 | MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_GP_STATUS); | 2712 | MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_GP_STATUS); |
2338 | /* avoid fast toggling */ | 2713 | /* avoid fast toggling */ |
2339 | for (i = 0 ; i < 10 ; i++) { | 2714 | for (i = 0; i < 10; i++) { |
2340 | msleep(10); | 2715 | msleep(10); |
2341 | bnx2x_mdio22_read(bp, MDIO_GP_STATUS_TOP_AN_STATUS1, | 2716 | bnx2x_mdio22_read(bp, MDIO_GP_STATUS_TOP_AN_STATUS1, |
2342 | &gp_status); | 2717 | &gp_status); |
@@ -2351,7 +2726,8 @@ static void bnx2x_link_update(struct bnx2x *bp) | |||
2351 | bnx2x_link_int_ack(bp, link_10g); | 2726 | bnx2x_link_int_ack(bp, link_10g); |
2352 | 2727 | ||
2353 | /* link is up only if both local phy and external phy are up */ | 2728 | /* link is up only if both local phy and external phy are up */ |
2354 | if (bp->link_up && bnx2x_ext_phy_is_link_up(bp)) { | 2729 | bp->link_up = (bp->phy_link_up && bnx2x_ext_phy_is_link_up(bp)); |
2730 | if (bp->link_up) { | ||
2355 | if (link_10g) { | 2731 | if (link_10g) { |
2356 | bnx2x_bmac_enable(bp, 0); | 2732 | bnx2x_bmac_enable(bp, 0); |
2357 | bnx2x_leds_set(bp, SPEED_10000); | 2733 | bnx2x_leds_set(bp, SPEED_10000); |
@@ -2427,7 +2803,9 @@ static void bnx2x_reset_unicore(struct bnx2x *bp) | |||
2427 | } | 2803 | } |
2428 | } | 2804 | } |
2429 | 2805 | ||
2430 | BNX2X_ERR("BUG! unicore is still in reset!\n"); | 2806 | BNX2X_ERR("BUG! %s (0x%x) is still in reset!\n", |
2807 | (bp->phy_flags & PHY_XGXS_FLAG)? "XGXS":"SerDes", | ||
2808 | bp->phy_addr); | ||
2431 | } | 2809 | } |
2432 | 2810 | ||
2433 | static void bnx2x_set_swap_lanes(struct bnx2x *bp) | 2811 | static void bnx2x_set_swap_lanes(struct bnx2x *bp) |
@@ -2475,12 +2853,12 @@ static void bnx2x_set_parallel_detection(struct bnx2x *bp) | |||
2475 | MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_10G_PARALLEL_DETECT); | 2853 | MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_10G_PARALLEL_DETECT); |
2476 | 2854 | ||
2477 | bnx2x_mdio22_write(bp, | 2855 | bnx2x_mdio22_write(bp, |
2478 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, | 2856 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, |
2479 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); | 2857 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); |
2480 | 2858 | ||
2481 | bnx2x_mdio22_read(bp, | 2859 | bnx2x_mdio22_read(bp, |
2482 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, | 2860 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, |
2483 | &control2); | 2861 | &control2); |
2484 | 2862 | ||
2485 | if (bp->autoneg & AUTONEG_PARALLEL) { | 2863 | if (bp->autoneg & AUTONEG_PARALLEL) { |
2486 | control2 |= | 2864 | control2 |= |
@@ -2490,8 +2868,14 @@ static void bnx2x_set_parallel_detection(struct bnx2x *bp) | |||
2490 | ~MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN; | 2868 | ~MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN; |
2491 | } | 2869 | } |
2492 | bnx2x_mdio22_write(bp, | 2870 | bnx2x_mdio22_write(bp, |
2493 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, | 2871 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, |
2494 | control2); | 2872 | control2); |
2873 | |||
2874 | /* Disable parallel detection of HiG */ | ||
2875 | MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_XGXS_BLOCK2); | ||
2876 | bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_UNICORE_MODE_10G, | ||
2877 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS | | ||
2878 | MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS); | ||
2495 | } | 2879 | } |
2496 | } | 2880 | } |
2497 | 2881 | ||
@@ -2625,7 +3009,7 @@ static void bnx2x_set_brcm_cl37_advertisment(struct bnx2x *bp) | |||
2625 | MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_OVER_1G); | 3009 | MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_OVER_1G); |
2626 | 3010 | ||
2627 | /* set extended capabilities */ | 3011 | /* set extended capabilities */ |
2628 | if (bp->advertising & ADVERTISED_2500baseT_Full) | 3012 | if (bp->advertising & ADVERTISED_2500baseX_Full) |
2629 | val |= MDIO_OVER_1G_UP1_2_5G; | 3013 | val |= MDIO_OVER_1G_UP1_2_5G; |
2630 | if (bp->advertising & ADVERTISED_10000baseT_Full) | 3014 | if (bp->advertising & ADVERTISED_10000baseT_Full) |
2631 | val |= MDIO_OVER_1G_UP1_10G; | 3015 | val |= MDIO_OVER_1G_UP1_10G; |
@@ -2641,20 +3025,91 @@ static void bnx2x_set_ieee_aneg_advertisment(struct bnx2x *bp) | |||
2641 | /* for AN, we are always publishing full duplex */ | 3025 | /* for AN, we are always publishing full duplex */ |
2642 | an_adv = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; | 3026 | an_adv = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; |
2643 | 3027 | ||
2644 | /* set pause */ | 3028 | /* resolve pause mode and advertisement |
2645 | switch (bp->pause_mode) { | 3029 | * Please refer to Table 28B-3 of the 802.3ab-1999 spec */ |
2646 | case PAUSE_SYMMETRIC: | 3030 | if (bp->req_autoneg & AUTONEG_FLOW_CTRL) { |
2647 | an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC; | 3031 | switch (bp->req_flow_ctrl) { |
2648 | break; | 3032 | case FLOW_CTRL_AUTO: |
2649 | case PAUSE_ASYMMETRIC: | 3033 | if (bp->dev->mtu <= 4500) { |
2650 | an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; | 3034 | an_adv |= |
2651 | break; | 3035 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; |
2652 | case PAUSE_BOTH: | 3036 | bp->advertising |= (ADVERTISED_Pause | |
2653 | an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | 3037 | ADVERTISED_Asym_Pause); |
2654 | break; | 3038 | } else { |
2655 | case PAUSE_NONE: | 3039 | an_adv |= |
2656 | an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; | 3040 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; |
2657 | break; | 3041 | bp->advertising |= ADVERTISED_Asym_Pause; |
3042 | } | ||
3043 | break; | ||
3044 | |||
3045 | case FLOW_CTRL_TX: | ||
3046 | an_adv |= | ||
3047 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; | ||
3048 | bp->advertising |= ADVERTISED_Asym_Pause; | ||
3049 | break; | ||
3050 | |||
3051 | case FLOW_CTRL_RX: | ||
3052 | if (bp->dev->mtu <= 4500) { | ||
3053 | an_adv |= | ||
3054 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | ||
3055 | bp->advertising |= (ADVERTISED_Pause | | ||
3056 | ADVERTISED_Asym_Pause); | ||
3057 | } else { | ||
3058 | an_adv |= | ||
3059 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; | ||
3060 | bp->advertising &= ~(ADVERTISED_Pause | | ||
3061 | ADVERTISED_Asym_Pause); | ||
3062 | } | ||
3063 | break; | ||
3064 | |||
3065 | case FLOW_CTRL_BOTH: | ||
3066 | if (bp->dev->mtu <= 4500) { | ||
3067 | an_adv |= | ||
3068 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | ||
3069 | bp->advertising |= (ADVERTISED_Pause | | ||
3070 | ADVERTISED_Asym_Pause); | ||
3071 | } else { | ||
3072 | an_adv |= | ||
3073 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; | ||
3074 | bp->advertising |= ADVERTISED_Asym_Pause; | ||
3075 | } | ||
3076 | break; | ||
3077 | |||
3078 | case FLOW_CTRL_NONE: | ||
3079 | default: | ||
3080 | an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; | ||
3081 | bp->advertising &= ~(ADVERTISED_Pause | | ||
3082 | ADVERTISED_Asym_Pause); | ||
3083 | break; | ||
3084 | } | ||
3085 | } else { /* forced mode */ | ||
3086 | switch (bp->req_flow_ctrl) { | ||
3087 | case FLOW_CTRL_AUTO: | ||
3088 | DP(NETIF_MSG_LINK, "req_flow_ctrl 0x%x while" | ||
3089 | " req_autoneg 0x%x\n", | ||
3090 | bp->req_flow_ctrl, bp->req_autoneg); | ||
3091 | break; | ||
3092 | |||
3093 | case FLOW_CTRL_TX: | ||
3094 | an_adv |= | ||
3095 | MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; | ||
3096 | bp->advertising |= ADVERTISED_Asym_Pause; | ||
3097 | break; | ||
3098 | |||
3099 | case FLOW_CTRL_RX: | ||
3100 | case FLOW_CTRL_BOTH: | ||
3101 | an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; | ||
3102 | bp->advertising |= (ADVERTISED_Pause | | ||
3103 | ADVERTISED_Asym_Pause); | ||
3104 | break; | ||
3105 | |||
3106 | case FLOW_CTRL_NONE: | ||
3107 | default: | ||
3108 | an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; | ||
3109 | bp->advertising &= ~(ADVERTISED_Pause | | ||
3110 | ADVERTISED_Asym_Pause); | ||
3111 | break; | ||
3112 | } | ||
2658 | } | 3113 | } |
2659 | 3114 | ||
2660 | MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0); | 3115 | MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0); |
@@ -2752,47 +3207,162 @@ static void bnx2x_initialize_sgmii_process(struct bnx2x *bp) | |||
2752 | static void bnx2x_link_int_enable(struct bnx2x *bp) | 3207 | static void bnx2x_link_int_enable(struct bnx2x *bp) |
2753 | { | 3208 | { |
2754 | int port = bp->port; | 3209 | int port = bp->port; |
3210 | u32 ext_phy_type; | ||
3211 | u32 mask; | ||
2755 | 3212 | ||
2756 | /* setting the status to report on link up | 3213 | /* setting the status to report on link up |
2757 | for either XGXS or SerDes */ | 3214 | for either XGXS or SerDes */ |
2758 | bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, | 3215 | bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, |
2759 | (NIG_XGXS0_LINK_STATUS | | 3216 | (NIG_STATUS_XGXS0_LINK10G | |
2760 | NIG_STATUS_INTERRUPT_XGXS0_LINK10G | | 3217 | NIG_STATUS_XGXS0_LINK_STATUS | |
2761 | NIG_SERDES0_LINK_STATUS)); | 3218 | NIG_STATUS_SERDES0_LINK_STATUS)); |
2762 | 3219 | ||
2763 | if (bp->phy_flags & PHY_XGXS_FLAG) { | 3220 | if (bp->phy_flags & PHY_XGXS_FLAG) { |
2764 | /* TBD - | 3221 | mask = (NIG_MASK_XGXS0_LINK10G | |
2765 | * in force mode (not AN) we can enable just the relevant | 3222 | NIG_MASK_XGXS0_LINK_STATUS); |
2766 | * interrupt | 3223 | DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n"); |
2767 | * Even in AN we might enable only one according to the AN | 3224 | ext_phy_type = XGXS_EXT_PHY_TYPE(bp); |
2768 | * speed mask | 3225 | if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && |
2769 | */ | 3226 | (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && |
2770 | bnx2x_bits_en(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, | 3227 | (ext_phy_type != |
2771 | (NIG_MASK_XGXS0_LINK_STATUS | | 3228 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) { |
2772 | NIG_MASK_XGXS0_LINK10G)); | 3229 | mask |= NIG_MASK_MI_INT; |
2773 | DP(NETIF_MSG_LINK, "enable XGXS interrupt\n"); | 3230 | DP(NETIF_MSG_LINK, "enabled external phy int\n"); |
3231 | } | ||
2774 | 3232 | ||
2775 | } else { /* SerDes */ | 3233 | } else { /* SerDes */ |
2776 | bnx2x_bits_en(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, | 3234 | mask = NIG_MASK_SERDES0_LINK_STATUS; |
2777 | NIG_MASK_SERDES0_LINK_STATUS); | 3235 | DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n"); |
2778 | DP(NETIF_MSG_LINK, "enable SerDes interrupt\n"); | 3236 | ext_phy_type = SERDES_EXT_PHY_TYPE(bp); |
3237 | if ((ext_phy_type != | ||
3238 | PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) && | ||
3239 | (ext_phy_type != | ||
3240 | PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN)) { | ||
3241 | mask |= NIG_MASK_MI_INT; | ||
3242 | DP(NETIF_MSG_LINK, "enabled external phy int\n"); | ||
3243 | } | ||
2779 | } | 3244 | } |
3245 | bnx2x_bits_en(bp, | ||
3246 | NIG_REG_MASK_INTERRUPT_PORT0 + port*4, | ||
3247 | mask); | ||
3248 | DP(NETIF_MSG_LINK, "port %x, %s, int_status 0x%x," | ||
3249 | " int_mask 0x%x, MI_INT %x, SERDES_LINK %x," | ||
3250 | " 10G %x, XGXS_LINK %x\n", port, | ||
3251 | (bp->phy_flags & PHY_XGXS_FLAG)? "XGXS":"SerDes", | ||
3252 | REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4), | ||
3253 | REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), | ||
3254 | REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), | ||
3255 | REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c), | ||
3256 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), | ||
3257 | REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68) | ||
3258 | ); | ||
3259 | } | ||
3260 | |||
3261 | static void bnx2x_bcm8072_external_rom_boot(struct bnx2x *bp) | ||
3262 | { | ||
3263 | u32 ext_phy_addr = ((bp->ext_phy_config & | ||
3264 | PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> | ||
3265 | PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); | ||
3266 | u32 fw_ver1, fw_ver2; | ||
3267 | |||
3268 | /* Need to wait 200ms after reset */ | ||
3269 | msleep(200); | ||
3270 | /* Boot port from external ROM | ||
3271 | * Set ser_boot_ctl bit in the MISC_CTRL1 register | ||
3272 | */ | ||
3273 | bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr, | ||
3274 | EXT_PHY_KR_PMA_PMD_DEVAD, | ||
3275 | EXT_PHY_KR_MISC_CTRL1, 0x0001); | ||
3276 | |||
3277 | /* Reset internal microprocessor */ | ||
3278 | bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr, | ||
3279 | EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_GEN_CTRL, | ||
3280 | EXT_PHY_KR_ROM_RESET_INTERNAL_MP); | ||
3281 | /* set micro reset = 0 */ | ||
3282 | bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr, | ||
3283 | EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_GEN_CTRL, | ||
3284 | EXT_PHY_KR_ROM_MICRO_RESET); | ||
3285 | /* Reset internal microprocessor */ | ||
3286 | bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr, | ||
3287 | EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_GEN_CTRL, | ||
3288 | EXT_PHY_KR_ROM_RESET_INTERNAL_MP); | ||
3289 | /* wait for 100ms for code download via SPI port */ | ||
3290 | msleep(100); | ||
3291 | |||
3292 | /* Clear ser_boot_ctl bit */ | ||
3293 | bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr, | ||
3294 | EXT_PHY_KR_PMA_PMD_DEVAD, | ||
3295 | EXT_PHY_KR_MISC_CTRL1, 0x0000); | ||
3296 | /* Wait 100ms */ | ||
3297 | msleep(100); | ||
3298 | |||
3299 | /* Print the PHY FW version */ | ||
3300 | bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0, ext_phy_addr, | ||
3301 | EXT_PHY_KR_PMA_PMD_DEVAD, | ||
3302 | 0xca19, &fw_ver1); | ||
3303 | bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0, ext_phy_addr, | ||
3304 | EXT_PHY_KR_PMA_PMD_DEVAD, | ||
3305 | 0xca1a, &fw_ver2); | ||
3306 | DP(NETIF_MSG_LINK, | ||
3307 | "8072 FW version 0x%x:0x%x\n", fw_ver1, fw_ver2); | ||
3308 | } | ||
3309 | |||
3310 | static void bnx2x_bcm8072_force_10G(struct bnx2x *bp) | ||
3311 | { | ||
3312 | u32 ext_phy_addr = ((bp->ext_phy_config & | ||
3313 | PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> | ||
3314 | PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); | ||
3315 | |||
3316 | /* Force KR or KX */ | ||
3317 | bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr, | ||
3318 | EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_CTRL, | ||
3319 | 0x2040); | ||
3320 | bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr, | ||
3321 | EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_CTRL2, | ||
3322 | 0x000b); | ||
3323 | bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr, | ||
3324 | EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_PMD_CTRL, | ||
3325 | 0x0000); | ||
3326 | bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr, | ||
3327 | EXT_PHY_KR_AUTO_NEG_DEVAD, EXT_PHY_KR_CTRL, | ||
3328 | 0x0000); | ||
2780 | } | 3329 | } |
2781 | 3330 | ||
2782 | static void bnx2x_ext_phy_init(struct bnx2x *bp) | 3331 | static void bnx2x_ext_phy_init(struct bnx2x *bp) |
2783 | { | 3332 | { |
2784 | int port = bp->port; | ||
2785 | u32 ext_phy_type; | 3333 | u32 ext_phy_type; |
2786 | u32 ext_phy_addr; | 3334 | u32 ext_phy_addr; |
2787 | u32 local_phy; | 3335 | u32 cnt; |
3336 | u32 ctrl; | ||
3337 | u32 val = 0; | ||
2788 | 3338 | ||
2789 | if (bp->phy_flags & PHY_XGXS_FLAG) { | 3339 | if (bp->phy_flags & PHY_XGXS_FLAG) { |
2790 | local_phy = bp->phy_addr; | ||
2791 | ext_phy_addr = ((bp->ext_phy_config & | 3340 | ext_phy_addr = ((bp->ext_phy_config & |
2792 | PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> | 3341 | PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> |
2793 | PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); | 3342 | PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); |
2794 | 3343 | ||
2795 | ext_phy_type = XGXS_EXT_PHY_TYPE(bp); | 3344 | ext_phy_type = XGXS_EXT_PHY_TYPE(bp); |
3345 | /* Make sure that the soft reset is off (expect for the 8072: | ||
3346 | * due to the lock, it will be done inside the specific | ||
3347 | * handling) | ||
3348 | */ | ||
3349 | if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && | ||
3350 | (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && | ||
3351 | (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) && | ||
3352 | (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072)) { | ||
3353 | /* Wait for soft reset to get cleared upto 1 sec */ | ||
3354 | for (cnt = 0; cnt < 1000; cnt++) { | ||
3355 | bnx2x_mdio45_read(bp, ext_phy_addr, | ||
3356 | EXT_PHY_OPT_PMA_PMD_DEVAD, | ||
3357 | EXT_PHY_OPT_CNTL, &ctrl); | ||
3358 | if (!(ctrl & (1<<15))) | ||
3359 | break; | ||
3360 | msleep(1); | ||
3361 | } | ||
3362 | DP(NETIF_MSG_LINK, | ||
3363 | "control reg 0x%x (after %d ms)\n", ctrl, cnt); | ||
3364 | } | ||
3365 | |||
2796 | switch (ext_phy_type) { | 3366 | switch (ext_phy_type) { |
2797 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: | 3367 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: |
2798 | DP(NETIF_MSG_LINK, "XGXS Direct\n"); | 3368 | DP(NETIF_MSG_LINK, "XGXS Direct\n"); |
@@ -2800,49 +3370,235 @@ static void bnx2x_ext_phy_init(struct bnx2x *bp) | |||
2800 | 3370 | ||
2801 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: | 3371 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: |
2802 | DP(NETIF_MSG_LINK, "XGXS 8705\n"); | 3372 | DP(NETIF_MSG_LINK, "XGXS 8705\n"); |
2803 | bnx2x_bits_en(bp, | ||
2804 | NIG_REG_MASK_INTERRUPT_PORT0 + port*4, | ||
2805 | NIG_MASK_MI_INT); | ||
2806 | DP(NETIF_MSG_LINK, "enabled extenal phy int\n"); | ||
2807 | 3373 | ||
2808 | bp->phy_addr = ext_phy_type; | 3374 | bnx2x_mdio45_vwrite(bp, ext_phy_addr, |
2809 | bnx2x_mdio45_vwrite(bp, EXT_PHY_OPT_PMA_PMD_DEVAD, | 3375 | EXT_PHY_OPT_PMA_PMD_DEVAD, |
2810 | EXT_PHY_OPT_PMD_MISC_CNTL, | 3376 | EXT_PHY_OPT_PMD_MISC_CNTL, |
2811 | 0x8288); | 3377 | 0x8288); |
2812 | bnx2x_mdio45_vwrite(bp, EXT_PHY_OPT_PMA_PMD_DEVAD, | 3378 | bnx2x_mdio45_vwrite(bp, ext_phy_addr, |
3379 | EXT_PHY_OPT_PMA_PMD_DEVAD, | ||
2813 | EXT_PHY_OPT_PHY_IDENTIFIER, | 3380 | EXT_PHY_OPT_PHY_IDENTIFIER, |
2814 | 0x7fbf); | 3381 | 0x7fbf); |
2815 | bnx2x_mdio45_vwrite(bp, EXT_PHY_OPT_PMA_PMD_DEVAD, | 3382 | bnx2x_mdio45_vwrite(bp, ext_phy_addr, |
3383 | EXT_PHY_OPT_PMA_PMD_DEVAD, | ||
2816 | EXT_PHY_OPT_CMU_PLL_BYPASS, | 3384 | EXT_PHY_OPT_CMU_PLL_BYPASS, |
2817 | 0x0100); | 3385 | 0x0100); |
2818 | bnx2x_mdio45_vwrite(bp, EXT_PHY_OPT_WIS_DEVAD, | 3386 | bnx2x_mdio45_vwrite(bp, ext_phy_addr, |
3387 | EXT_PHY_OPT_WIS_DEVAD, | ||
2819 | EXT_PHY_OPT_LASI_CNTL, 0x1); | 3388 | EXT_PHY_OPT_LASI_CNTL, 0x1); |
2820 | break; | 3389 | break; |
2821 | 3390 | ||
2822 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: | 3391 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: |
2823 | DP(NETIF_MSG_LINK, "XGXS 8706\n"); | 3392 | DP(NETIF_MSG_LINK, "XGXS 8706\n"); |
2824 | bnx2x_bits_en(bp, | 3393 | |
2825 | NIG_REG_MASK_INTERRUPT_PORT0 + port*4, | 3394 | if (!(bp->req_autoneg & AUTONEG_SPEED)) { |
2826 | NIG_MASK_MI_INT); | 3395 | /* Force speed */ |
2827 | DP(NETIF_MSG_LINK, "enabled extenal phy int\n"); | 3396 | if (bp->req_line_speed == SPEED_10000) { |
2828 | 3397 | DP(NETIF_MSG_LINK, | |
2829 | bp->phy_addr = ext_phy_type; | 3398 | "XGXS 8706 force 10Gbps\n"); |
2830 | bnx2x_mdio45_vwrite(bp, EXT_PHY_OPT_PMA_PMD_DEVAD, | 3399 | bnx2x_mdio45_vwrite(bp, ext_phy_addr, |
2831 | EXT_PHY_OPT_PMD_DIGITAL_CNT, | 3400 | EXT_PHY_OPT_PMA_PMD_DEVAD, |
2832 | 0x400); | 3401 | EXT_PHY_OPT_PMD_DIGITAL_CNT, |
2833 | bnx2x_mdio45_vwrite(bp, EXT_PHY_OPT_PMA_PMD_DEVAD, | 3402 | 0x400); |
3403 | } else { | ||
3404 | /* Force 1Gbps */ | ||
3405 | DP(NETIF_MSG_LINK, | ||
3406 | "XGXS 8706 force 1Gbps\n"); | ||
3407 | |||
3408 | bnx2x_mdio45_vwrite(bp, ext_phy_addr, | ||
3409 | EXT_PHY_OPT_PMA_PMD_DEVAD, | ||
3410 | EXT_PHY_OPT_CNTL, | ||
3411 | 0x0040); | ||
3412 | |||
3413 | bnx2x_mdio45_vwrite(bp, ext_phy_addr, | ||
3414 | EXT_PHY_OPT_PMA_PMD_DEVAD, | ||
3415 | EXT_PHY_OPT_CNTL2, | ||
3416 | 0x000D); | ||
3417 | } | ||
3418 | |||
3419 | /* Enable LASI */ | ||
3420 | bnx2x_mdio45_vwrite(bp, ext_phy_addr, | ||
3421 | EXT_PHY_OPT_PMA_PMD_DEVAD, | ||
3422 | EXT_PHY_OPT_LASI_CNTL, | ||
3423 | 0x1); | ||
3424 | } else { | ||
3425 | /* AUTONEG */ | ||
3426 | /* Allow CL37 through CL73 */ | ||
3427 | DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n"); | ||
3428 | bnx2x_mdio45_vwrite(bp, ext_phy_addr, | ||
3429 | EXT_PHY_AUTO_NEG_DEVAD, | ||
3430 | EXT_PHY_OPT_AN_CL37_CL73, | ||
3431 | 0x040c); | ||
3432 | |||
3433 | /* Enable Full-Duplex advertisment on CL37 */ | ||
3434 | bnx2x_mdio45_vwrite(bp, ext_phy_addr, | ||
3435 | EXT_PHY_AUTO_NEG_DEVAD, | ||
3436 | EXT_PHY_OPT_AN_CL37_FD, | ||
3437 | 0x0020); | ||
3438 | /* Enable CL37 AN */ | ||
3439 | bnx2x_mdio45_vwrite(bp, ext_phy_addr, | ||
3440 | EXT_PHY_AUTO_NEG_DEVAD, | ||
3441 | EXT_PHY_OPT_AN_CL37_AN, | ||
3442 | 0x1000); | ||
3443 | /* Advertise 10G/1G support */ | ||
3444 | if (bp->advertising & | ||
3445 | ADVERTISED_1000baseT_Full) | ||
3446 | val = (1<<5); | ||
3447 | if (bp->advertising & | ||
3448 | ADVERTISED_10000baseT_Full) | ||
3449 | val |= (1<<7); | ||
3450 | |||
3451 | bnx2x_mdio45_vwrite(bp, ext_phy_addr, | ||
3452 | EXT_PHY_AUTO_NEG_DEVAD, | ||
3453 | EXT_PHY_OPT_AN_ADV, val); | ||
3454 | /* Enable LASI */ | ||
3455 | bnx2x_mdio45_vwrite(bp, ext_phy_addr, | ||
3456 | EXT_PHY_OPT_PMA_PMD_DEVAD, | ||
3457 | EXT_PHY_OPT_LASI_CNTL, | ||
3458 | 0x1); | ||
3459 | |||
3460 | /* Enable clause 73 AN */ | ||
3461 | bnx2x_mdio45_write(bp, ext_phy_addr, | ||
3462 | EXT_PHY_AUTO_NEG_DEVAD, | ||
3463 | EXT_PHY_OPT_CNTL, | ||
3464 | 0x1200); | ||
3465 | } | ||
3466 | break; | ||
3467 | |||
3468 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: | ||
3469 | bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO); | ||
3470 | /* Wait for soft reset to get cleared upto 1 sec */ | ||
3471 | for (cnt = 0; cnt < 1000; cnt++) { | ||
3472 | bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0, | ||
3473 | ext_phy_addr, | ||
3474 | EXT_PHY_OPT_PMA_PMD_DEVAD, | ||
3475 | EXT_PHY_OPT_CNTL, &ctrl); | ||
3476 | if (!(ctrl & (1<<15))) | ||
3477 | break; | ||
3478 | msleep(1); | ||
3479 | } | ||
3480 | DP(NETIF_MSG_LINK, | ||
3481 | "8072 control reg 0x%x (after %d ms)\n", | ||
3482 | ctrl, cnt); | ||
3483 | |||
3484 | bnx2x_bcm8072_external_rom_boot(bp); | ||
3485 | DP(NETIF_MSG_LINK, "Finshed loading 8072 KR ROM\n"); | ||
3486 | |||
3487 | /* enable LASI */ | ||
3488 | bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, | ||
3489 | ext_phy_addr, | ||
3490 | EXT_PHY_KR_PMA_PMD_DEVAD, | ||
3491 | 0x9000, 0x0400); | ||
3492 | bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, | ||
3493 | ext_phy_addr, | ||
3494 | EXT_PHY_KR_PMA_PMD_DEVAD, | ||
3495 | EXT_PHY_KR_LASI_CNTL, 0x0004); | ||
3496 | |||
3497 | /* If this is forced speed, set to KR or KX | ||
3498 | * (all other are not supported) | ||
3499 | */ | ||
3500 | if (!(bp->req_autoneg & AUTONEG_SPEED)) { | ||
3501 | if (bp->req_line_speed == SPEED_10000) { | ||
3502 | bnx2x_bcm8072_force_10G(bp); | ||
3503 | DP(NETIF_MSG_LINK, | ||
3504 | "Forced speed 10G on 8072\n"); | ||
3505 | /* unlock */ | ||
3506 | bnx2x_hw_unlock(bp, | ||
3507 | HW_LOCK_RESOURCE_8072_MDIO); | ||
3508 | break; | ||
3509 | } else | ||
3510 | val = (1<<5); | ||
3511 | } else { | ||
3512 | |||
3513 | /* Advertise 10G/1G support */ | ||
3514 | if (bp->advertising & | ||
3515 | ADVERTISED_1000baseT_Full) | ||
3516 | val = (1<<5); | ||
3517 | if (bp->advertising & | ||
3518 | ADVERTISED_10000baseT_Full) | ||
3519 | val |= (1<<7); | ||
3520 | } | ||
3521 | bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, | ||
3522 | ext_phy_addr, | ||
3523 | EXT_PHY_KR_AUTO_NEG_DEVAD, | ||
3524 | 0x11, val); | ||
3525 | /* Add support for CL37 ( passive mode ) I */ | ||
3526 | bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, | ||
3527 | ext_phy_addr, | ||
3528 | EXT_PHY_KR_AUTO_NEG_DEVAD, | ||
3529 | 0x8370, 0x040c); | ||
3530 | /* Add support for CL37 ( passive mode ) II */ | ||
3531 | bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, | ||
3532 | ext_phy_addr, | ||
3533 | EXT_PHY_KR_AUTO_NEG_DEVAD, | ||
3534 | 0xffe4, 0x20); | ||
3535 | /* Add support for CL37 ( passive mode ) III */ | ||
3536 | bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, | ||
3537 | ext_phy_addr, | ||
3538 | EXT_PHY_KR_AUTO_NEG_DEVAD, | ||
3539 | 0xffe0, 0x1000); | ||
3540 | /* Restart autoneg */ | ||
3541 | msleep(500); | ||
3542 | bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, | ||
3543 | ext_phy_addr, | ||
3544 | EXT_PHY_KR_AUTO_NEG_DEVAD, | ||
3545 | EXT_PHY_KR_CTRL, 0x1200); | ||
3546 | DP(NETIF_MSG_LINK, "8072 Autoneg Restart: " | ||
3547 | "1G %ssupported 10G %ssupported\n", | ||
3548 | (val & (1<<5)) ? "" : "not ", | ||
3549 | (val & (1<<7)) ? "" : "not "); | ||
3550 | |||
3551 | /* unlock */ | ||
3552 | bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_8072_MDIO); | ||
3553 | break; | ||
3554 | |||
3555 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: | ||
3556 | DP(NETIF_MSG_LINK, | ||
3557 | "Setting the SFX7101 LASI indication\n"); | ||
3558 | bnx2x_mdio45_vwrite(bp, ext_phy_addr, | ||
3559 | EXT_PHY_OPT_PMA_PMD_DEVAD, | ||
2834 | EXT_PHY_OPT_LASI_CNTL, 0x1); | 3560 | EXT_PHY_OPT_LASI_CNTL, 0x1); |
3561 | DP(NETIF_MSG_LINK, | ||
3562 | "Setting the SFX7101 LED to blink on traffic\n"); | ||
3563 | bnx2x_mdio45_vwrite(bp, ext_phy_addr, | ||
3564 | EXT_PHY_OPT_PMA_PMD_DEVAD, | ||
3565 | 0xC007, (1<<3)); | ||
3566 | |||
3567 | /* read modify write pause advertizing */ | ||
3568 | bnx2x_mdio45_read(bp, ext_phy_addr, | ||
3569 | EXT_PHY_KR_AUTO_NEG_DEVAD, | ||
3570 | EXT_PHY_KR_AUTO_NEG_ADVERT, &val); | ||
3571 | val &= ~EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_BOTH; | ||
3572 | /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ | ||
3573 | if (bp->advertising & ADVERTISED_Pause) | ||
3574 | val |= EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE; | ||
3575 | |||
3576 | if (bp->advertising & ADVERTISED_Asym_Pause) { | ||
3577 | val |= | ||
3578 | EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_ASYMMETRIC; | ||
3579 | } | ||
3580 | DP(NETIF_MSG_LINK, "SFX7101 AN advertize 0x%x\n", val); | ||
3581 | bnx2x_mdio45_vwrite(bp, ext_phy_addr, | ||
3582 | EXT_PHY_KR_AUTO_NEG_DEVAD, | ||
3583 | EXT_PHY_KR_AUTO_NEG_ADVERT, val); | ||
3584 | /* Restart autoneg */ | ||
3585 | bnx2x_mdio45_read(bp, ext_phy_addr, | ||
3586 | EXT_PHY_KR_AUTO_NEG_DEVAD, | ||
3587 | EXT_PHY_KR_CTRL, &val); | ||
3588 | val |= 0x200; | ||
3589 | bnx2x_mdio45_write(bp, ext_phy_addr, | ||
3590 | EXT_PHY_KR_AUTO_NEG_DEVAD, | ||
3591 | EXT_PHY_KR_CTRL, val); | ||
2835 | break; | 3592 | break; |
2836 | 3593 | ||
2837 | default: | 3594 | default: |
2838 | DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n", | 3595 | BNX2X_ERR("BAD XGXS ext_phy_config 0x%x\n", |
2839 | bp->ext_phy_config); | 3596 | bp->ext_phy_config); |
2840 | break; | 3597 | break; |
2841 | } | 3598 | } |
2842 | bp->phy_addr = local_phy; | ||
2843 | 3599 | ||
2844 | } else { /* SerDes */ | 3600 | } else { /* SerDes */ |
2845 | /* ext_phy_addr = ((bp->ext_phy_config & | 3601 | /* ext_phy_addr = ((bp->ext_phy_config & |
2846 | PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK) >> | 3602 | PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK) >> |
2847 | PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT); | 3603 | PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT); |
2848 | */ | 3604 | */ |
@@ -2854,10 +3610,6 @@ static void bnx2x_ext_phy_init(struct bnx2x *bp) | |||
2854 | 3610 | ||
2855 | case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482: | 3611 | case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482: |
2856 | DP(NETIF_MSG_LINK, "SerDes 5482\n"); | 3612 | DP(NETIF_MSG_LINK, "SerDes 5482\n"); |
2857 | bnx2x_bits_en(bp, | ||
2858 | NIG_REG_MASK_INTERRUPT_PORT0 + port*4, | ||
2859 | NIG_MASK_MI_INT); | ||
2860 | DP(NETIF_MSG_LINK, "enabled extenal phy int\n"); | ||
2861 | break; | 3613 | break; |
2862 | 3614 | ||
2863 | default: | 3615 | default: |
@@ -2871,8 +3623,22 @@ static void bnx2x_ext_phy_init(struct bnx2x *bp) | |||
2871 | static void bnx2x_ext_phy_reset(struct bnx2x *bp) | 3623 | static void bnx2x_ext_phy_reset(struct bnx2x *bp) |
2872 | { | 3624 | { |
2873 | u32 ext_phy_type; | 3625 | u32 ext_phy_type; |
2874 | u32 ext_phy_addr; | 3626 | u32 ext_phy_addr = ((bp->ext_phy_config & |
2875 | u32 local_phy; | 3627 | PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> |
3628 | PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); | ||
3629 | u32 board = (bp->board & SHARED_HW_CFG_BOARD_TYPE_MASK); | ||
3630 | |||
3631 | /* The PHY reset is controled by GPIO 1 | ||
3632 | * Give it 1ms of reset pulse | ||
3633 | */ | ||
3634 | if ((board != SHARED_HW_CFG_BOARD_TYPE_BCM957710T1002G) && | ||
3635 | (board != SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G)) { | ||
3636 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, | ||
3637 | MISC_REGISTERS_GPIO_OUTPUT_LOW); | ||
3638 | msleep(1); | ||
3639 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, | ||
3640 | MISC_REGISTERS_GPIO_OUTPUT_HIGH); | ||
3641 | } | ||
2876 | 3642 | ||
2877 | if (bp->phy_flags & PHY_XGXS_FLAG) { | 3643 | if (bp->phy_flags & PHY_XGXS_FLAG) { |
2878 | ext_phy_type = XGXS_EXT_PHY_TYPE(bp); | 3644 | ext_phy_type = XGXS_EXT_PHY_TYPE(bp); |
@@ -2883,15 +3649,24 @@ static void bnx2x_ext_phy_reset(struct bnx2x *bp) | |||
2883 | 3649 | ||
2884 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: | 3650 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: |
2885 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: | 3651 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: |
2886 | DP(NETIF_MSG_LINK, "XGXS 8705/6\n"); | 3652 | DP(NETIF_MSG_LINK, "XGXS 8705/8706\n"); |
2887 | local_phy = bp->phy_addr; | 3653 | bnx2x_mdio45_write(bp, ext_phy_addr, |
2888 | ext_phy_addr = ((bp->ext_phy_config & | 3654 | EXT_PHY_OPT_PMA_PMD_DEVAD, |
2889 | PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> | ||
2890 | PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT); | ||
2891 | bp->phy_addr = (u8)ext_phy_addr; | ||
2892 | bnx2x_mdio45_write(bp, EXT_PHY_OPT_PMA_PMD_DEVAD, | ||
2893 | EXT_PHY_OPT_CNTL, 0xa040); | 3655 | EXT_PHY_OPT_CNTL, 0xa040); |
2894 | bp->phy_addr = local_phy; | 3656 | break; |
3657 | |||
3658 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: | ||
3659 | DP(NETIF_MSG_LINK, "XGXS 8072\n"); | ||
3660 | bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO); | ||
3661 | bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, | ||
3662 | ext_phy_addr, | ||
3663 | EXT_PHY_KR_PMA_PMD_DEVAD, | ||
3664 | 0, 1<<15); | ||
3665 | bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_8072_MDIO); | ||
3666 | break; | ||
3667 | |||
3668 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: | ||
3669 | DP(NETIF_MSG_LINK, "XGXS SFX7101\n"); | ||
2895 | break; | 3670 | break; |
2896 | 3671 | ||
2897 | default: | 3672 | default: |
@@ -2930,6 +3705,7 @@ static void bnx2x_link_initialize(struct bnx2x *bp) | |||
2930 | NIG_MASK_SERDES0_LINK_STATUS | | 3705 | NIG_MASK_SERDES0_LINK_STATUS | |
2931 | NIG_MASK_MI_INT)); | 3706 | NIG_MASK_MI_INT)); |
2932 | 3707 | ||
3708 | /* Activate the external PHY */ | ||
2933 | bnx2x_ext_phy_reset(bp); | 3709 | bnx2x_ext_phy_reset(bp); |
2934 | 3710 | ||
2935 | bnx2x_set_aer_mmd(bp); | 3711 | bnx2x_set_aer_mmd(bp); |
@@ -2994,13 +3770,13 @@ static void bnx2x_link_initialize(struct bnx2x *bp) | |||
2994 | /* AN enabled */ | 3770 | /* AN enabled */ |
2995 | bnx2x_set_brcm_cl37_advertisment(bp); | 3771 | bnx2x_set_brcm_cl37_advertisment(bp); |
2996 | 3772 | ||
2997 | /* program duplex & pause advertisment (for aneg) */ | 3773 | /* program duplex & pause advertisement (for aneg) */ |
2998 | bnx2x_set_ieee_aneg_advertisment(bp); | 3774 | bnx2x_set_ieee_aneg_advertisment(bp); |
2999 | 3775 | ||
3000 | /* enable autoneg */ | 3776 | /* enable autoneg */ |
3001 | bnx2x_set_autoneg(bp); | 3777 | bnx2x_set_autoneg(bp); |
3002 | 3778 | ||
3003 | /* enalbe and restart AN */ | 3779 | /* enable and restart AN */ |
3004 | bnx2x_restart_autoneg(bp); | 3780 | bnx2x_restart_autoneg(bp); |
3005 | } | 3781 | } |
3006 | 3782 | ||
@@ -3010,11 +3786,11 @@ static void bnx2x_link_initialize(struct bnx2x *bp) | |||
3010 | bnx2x_initialize_sgmii_process(bp); | 3786 | bnx2x_initialize_sgmii_process(bp); |
3011 | } | 3787 | } |
3012 | 3788 | ||
3013 | /* enable the interrupt */ | ||
3014 | bnx2x_link_int_enable(bp); | ||
3015 | |||
3016 | /* init ext phy and enable link state int */ | 3789 | /* init ext phy and enable link state int */ |
3017 | bnx2x_ext_phy_init(bp); | 3790 | bnx2x_ext_phy_init(bp); |
3791 | |||
3792 | /* enable the interrupt */ | ||
3793 | bnx2x_link_int_enable(bp); | ||
3018 | } | 3794 | } |
3019 | 3795 | ||
3020 | static void bnx2x_phy_deassert(struct bnx2x *bp) | 3796 | static void bnx2x_phy_deassert(struct bnx2x *bp) |
@@ -3073,6 +3849,11 @@ static int bnx2x_phy_init(struct bnx2x *bp) | |||
3073 | static void bnx2x_link_reset(struct bnx2x *bp) | 3849 | static void bnx2x_link_reset(struct bnx2x *bp) |
3074 | { | 3850 | { |
3075 | int port = bp->port; | 3851 | int port = bp->port; |
3852 | u32 board = (bp->board & SHARED_HW_CFG_BOARD_TYPE_MASK); | ||
3853 | |||
3854 | /* update shared memory */ | ||
3855 | bp->link_status = 0; | ||
3856 | bnx2x_update_mng(bp); | ||
3076 | 3857 | ||
3077 | /* disable attentions */ | 3858 | /* disable attentions */ |
3078 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, | 3859 | bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, |
@@ -3081,21 +3862,45 @@ static void bnx2x_link_reset(struct bnx2x *bp) | |||
3081 | NIG_MASK_SERDES0_LINK_STATUS | | 3862 | NIG_MASK_SERDES0_LINK_STATUS | |
3082 | NIG_MASK_MI_INT)); | 3863 | NIG_MASK_MI_INT)); |
3083 | 3864 | ||
3084 | bnx2x_ext_phy_reset(bp); | 3865 | /* activate nig drain */ |
3866 | NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); | ||
3867 | |||
3868 | /* disable nig egress interface */ | ||
3869 | NIG_WR(NIG_REG_BMAC0_OUT_EN + port*4, 0); | ||
3870 | NIG_WR(NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); | ||
3871 | |||
3872 | /* Stop BigMac rx */ | ||
3873 | bnx2x_bmac_rx_disable(bp); | ||
3874 | |||
3875 | /* disable emac */ | ||
3876 | NIG_WR(NIG_REG_NIG_EMAC0_EN + port*4, 0); | ||
3877 | |||
3878 | msleep(10); | ||
3879 | |||
3880 | /* The PHY reset is controled by GPIO 1 | ||
3881 | * Hold it as output low | ||
3882 | */ | ||
3883 | if ((board != SHARED_HW_CFG_BOARD_TYPE_BCM957710T1002G) && | ||
3884 | (board != SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G)) { | ||
3885 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, | ||
3886 | MISC_REGISTERS_GPIO_OUTPUT_LOW); | ||
3887 | DP(NETIF_MSG_LINK, "reset external PHY\n"); | ||
3888 | } | ||
3085 | 3889 | ||
3086 | /* reset the SerDes/XGXS */ | 3890 | /* reset the SerDes/XGXS */ |
3087 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, | 3891 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, |
3088 | (0x1ff << (port*16))); | 3892 | (0x1ff << (port*16))); |
3089 | 3893 | ||
3090 | /* reset EMAC / BMAC and disable NIG interfaces */ | 3894 | /* reset BigMac */ |
3091 | NIG_WR(NIG_REG_BMAC0_IN_EN + port*4, 0); | 3895 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, |
3092 | NIG_WR(NIG_REG_BMAC0_OUT_EN + port*4, 0); | 3896 | (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); |
3093 | 3897 | ||
3094 | NIG_WR(NIG_REG_NIG_EMAC0_EN + port*4, 0); | 3898 | /* disable nig ingress interface */ |
3899 | NIG_WR(NIG_REG_BMAC0_IN_EN + port*4, 0); | ||
3095 | NIG_WR(NIG_REG_EMAC0_IN_EN + port*4, 0); | 3900 | NIG_WR(NIG_REG_EMAC0_IN_EN + port*4, 0); |
3096 | NIG_WR(NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); | ||
3097 | 3901 | ||
3098 | NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); | 3902 | /* set link down */ |
3903 | bp->link_up = 0; | ||
3099 | } | 3904 | } |
3100 | 3905 | ||
3101 | #ifdef BNX2X_XGXS_LB | 3906 | #ifdef BNX2X_XGXS_LB |
@@ -3158,7 +3963,7 @@ static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, | |||
3158 | int port = bp->port; | 3963 | int port = bp->port; |
3159 | 3964 | ||
3160 | DP(NETIF_MSG_TIMER, | 3965 | DP(NETIF_MSG_TIMER, |
3161 | "spe (%x:%x) command %x hw_cid %x data (%x:%x) left %x\n", | 3966 | "spe (%x:%x) command %d hw_cid %x data (%x:%x) left %x\n", |
3162 | (u32)U64_HI(bp->spq_mapping), (u32)(U64_LO(bp->spq_mapping) + | 3967 | (u32)U64_HI(bp->spq_mapping), (u32)(U64_LO(bp->spq_mapping) + |
3163 | (void *)bp->spq_prod_bd - (void *)bp->spq), command, | 3968 | (void *)bp->spq_prod_bd - (void *)bp->spq), command, |
3164 | HW_CID(bp, cid), data_hi, data_lo, bp->spq_left); | 3969 | HW_CID(bp, cid), data_hi, data_lo, bp->spq_left); |
@@ -3176,6 +3981,7 @@ static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, | |||
3176 | bnx2x_panic(); | 3981 | bnx2x_panic(); |
3177 | return -EBUSY; | 3982 | return -EBUSY; |
3178 | } | 3983 | } |
3984 | |||
3179 | /* CID needs port number to be encoded int it */ | 3985 | /* CID needs port number to be encoded int it */ |
3180 | bp->spq_prod_bd->hdr.conn_and_cmd_data = | 3986 | bp->spq_prod_bd->hdr.conn_and_cmd_data = |
3181 | cpu_to_le32(((command << SPE_HDR_CMD_ID_SHIFT) | | 3987 | cpu_to_le32(((command << SPE_HDR_CMD_ID_SHIFT) | |
@@ -3282,8 +4088,8 @@ static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) | |||
3282 | u32 igu_addr = (IGU_ADDR_ATTN_BITS_SET + IGU_PORT_BASE * port) * 8; | 4088 | u32 igu_addr = (IGU_ADDR_ATTN_BITS_SET + IGU_PORT_BASE * port) * 8; |
3283 | u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : | 4089 | u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : |
3284 | MISC_REG_AEU_MASK_ATTN_FUNC_0; | 4090 | MISC_REG_AEU_MASK_ATTN_FUNC_0; |
3285 | u32 nig_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : | 4091 | u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : |
3286 | NIG_REG_MASK_INTERRUPT_PORT0; | 4092 | NIG_REG_MASK_INTERRUPT_PORT0; |
3287 | 4093 | ||
3288 | if (~bp->aeu_mask & (asserted & 0xff)) | 4094 | if (~bp->aeu_mask & (asserted & 0xff)) |
3289 | BNX2X_ERR("IGU ERROR\n"); | 4095 | BNX2X_ERR("IGU ERROR\n"); |
@@ -3301,15 +4107,11 @@ static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) | |||
3301 | 4107 | ||
3302 | if (asserted & ATTN_HARD_WIRED_MASK) { | 4108 | if (asserted & ATTN_HARD_WIRED_MASK) { |
3303 | if (asserted & ATTN_NIG_FOR_FUNC) { | 4109 | if (asserted & ATTN_NIG_FOR_FUNC) { |
3304 | u32 nig_status_port; | ||
3305 | u32 nig_int_addr = port ? | ||
3306 | NIG_REG_STATUS_INTERRUPT_PORT1 : | ||
3307 | NIG_REG_STATUS_INTERRUPT_PORT0; | ||
3308 | 4110 | ||
3309 | bp->nig_mask = REG_RD(bp, nig_mask_addr); | 4111 | /* save nig interrupt mask */ |
3310 | REG_WR(bp, nig_mask_addr, 0); | 4112 | bp->nig_mask = REG_RD(bp, nig_int_mask_addr); |
4113 | REG_WR(bp, nig_int_mask_addr, 0); | ||
3311 | 4114 | ||
3312 | nig_status_port = REG_RD(bp, nig_int_addr); | ||
3313 | bnx2x_link_update(bp); | 4115 | bnx2x_link_update(bp); |
3314 | 4116 | ||
3315 | /* handle unicore attn? */ | 4117 | /* handle unicore attn? */ |
@@ -3362,15 +4164,132 @@ static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) | |||
3362 | 4164 | ||
3363 | /* now set back the mask */ | 4165 | /* now set back the mask */ |
3364 | if (asserted & ATTN_NIG_FOR_FUNC) | 4166 | if (asserted & ATTN_NIG_FOR_FUNC) |
3365 | REG_WR(bp, nig_mask_addr, bp->nig_mask); | 4167 | REG_WR(bp, nig_int_mask_addr, bp->nig_mask); |
3366 | } | 4168 | } |
3367 | 4169 | ||
3368 | static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) | 4170 | static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) |
3369 | { | 4171 | { |
3370 | int port = bp->port; | 4172 | int port = bp->port; |
3371 | int index; | 4173 | int reg_offset; |
4174 | u32 val; | ||
4175 | |||
4176 | if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { | ||
4177 | |||
4178 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : | ||
4179 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | ||
4180 | |||
4181 | val = REG_RD(bp, reg_offset); | ||
4182 | val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; | ||
4183 | REG_WR(bp, reg_offset, val); | ||
4184 | |||
4185 | BNX2X_ERR("SPIO5 hw attention\n"); | ||
4186 | |||
4187 | switch (bp->board & SHARED_HW_CFG_BOARD_TYPE_MASK) { | ||
4188 | case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G: | ||
4189 | /* Fan failure attention */ | ||
4190 | |||
4191 | /* The PHY reset is controled by GPIO 1 */ | ||
4192 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, | ||
4193 | MISC_REGISTERS_GPIO_OUTPUT_LOW); | ||
4194 | /* Low power mode is controled by GPIO 2 */ | ||
4195 | bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, | ||
4196 | MISC_REGISTERS_GPIO_OUTPUT_LOW); | ||
4197 | /* mark the failure */ | ||
4198 | bp->ext_phy_config &= | ||
4199 | ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; | ||
4200 | bp->ext_phy_config |= | ||
4201 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; | ||
4202 | SHMEM_WR(bp, | ||
4203 | dev_info.port_hw_config[port]. | ||
4204 | external_phy_config, | ||
4205 | bp->ext_phy_config); | ||
4206 | /* log the failure */ | ||
4207 | printk(KERN_ERR PFX "Fan Failure on Network" | ||
4208 | " Controller %s has caused the driver to" | ||
4209 | " shutdown the card to prevent permanent" | ||
4210 | " damage. Please contact Dell Support for" | ||
4211 | " assistance\n", bp->dev->name); | ||
4212 | break; | ||
4213 | |||
4214 | default: | ||
4215 | break; | ||
4216 | } | ||
4217 | } | ||
4218 | } | ||
4219 | |||
4220 | static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) | ||
4221 | { | ||
4222 | u32 val; | ||
4223 | |||
4224 | if (attn & BNX2X_DOORQ_ASSERT) { | ||
4225 | |||
4226 | val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); | ||
4227 | BNX2X_ERR("DB hw attention 0x%x\n", val); | ||
4228 | /* DORQ discard attention */ | ||
4229 | if (val & 0x2) | ||
4230 | BNX2X_ERR("FATAL error from DORQ\n"); | ||
4231 | } | ||
4232 | } | ||
4233 | |||
4234 | static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) | ||
4235 | { | ||
4236 | u32 val; | ||
4237 | |||
4238 | if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { | ||
4239 | |||
4240 | val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); | ||
4241 | BNX2X_ERR("CFC hw attention 0x%x\n", val); | ||
4242 | /* CFC error attention */ | ||
4243 | if (val & 0x2) | ||
4244 | BNX2X_ERR("FATAL error from CFC\n"); | ||
4245 | } | ||
4246 | |||
4247 | if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { | ||
4248 | |||
4249 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); | ||
4250 | BNX2X_ERR("PXP hw attention 0x%x\n", val); | ||
4251 | /* RQ_USDMDP_FIFO_OVERFLOW */ | ||
4252 | if (val & 0x18000) | ||
4253 | BNX2X_ERR("FATAL error from PXP\n"); | ||
4254 | } | ||
4255 | } | ||
4256 | |||
4257 | static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) | ||
4258 | { | ||
4259 | if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { | ||
4260 | |||
4261 | if (attn & BNX2X_MC_ASSERT_BITS) { | ||
4262 | |||
4263 | BNX2X_ERR("MC assert!\n"); | ||
4264 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); | ||
4265 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); | ||
4266 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); | ||
4267 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); | ||
4268 | bnx2x_panic(); | ||
4269 | |||
4270 | } else if (attn & BNX2X_MCP_ASSERT) { | ||
4271 | |||
4272 | BNX2X_ERR("MCP assert!\n"); | ||
4273 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); | ||
4274 | bnx2x_mc_assert(bp); | ||
4275 | |||
4276 | } else | ||
4277 | BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn); | ||
4278 | } | ||
4279 | |||
4280 | if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { | ||
4281 | |||
4282 | REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); | ||
4283 | BNX2X_ERR("LATCHED attention 0x%x (masked)\n", attn); | ||
4284 | } | ||
4285 | } | ||
4286 | |||
4287 | static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) | ||
4288 | { | ||
3372 | struct attn_route attn; | 4289 | struct attn_route attn; |
3373 | struct attn_route group_mask; | 4290 | struct attn_route group_mask; |
4291 | int port = bp->port; | ||
4292 | int index; | ||
3374 | u32 reg_addr; | 4293 | u32 reg_addr; |
3375 | u32 val; | 4294 | u32 val; |
3376 | 4295 | ||
@@ -3391,64 +4310,14 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) | |||
3391 | DP(NETIF_MSG_HW, "group[%d]: %llx\n", index, | 4310 | DP(NETIF_MSG_HW, "group[%d]: %llx\n", index, |
3392 | (unsigned long long)group_mask.sig[0]); | 4311 | (unsigned long long)group_mask.sig[0]); |
3393 | 4312 | ||
3394 | if (attn.sig[3] & group_mask.sig[3] & | 4313 | bnx2x_attn_int_deasserted3(bp, |
3395 | EVEREST_GEN_ATTN_IN_USE_MASK) { | 4314 | attn.sig[3] & group_mask.sig[3]); |
3396 | 4315 | bnx2x_attn_int_deasserted1(bp, | |
3397 | if (attn.sig[3] & BNX2X_MC_ASSERT_BITS) { | 4316 | attn.sig[1] & group_mask.sig[1]); |
3398 | 4317 | bnx2x_attn_int_deasserted2(bp, | |
3399 | BNX2X_ERR("MC assert!\n"); | 4318 | attn.sig[2] & group_mask.sig[2]); |
3400 | bnx2x_panic(); | 4319 | bnx2x_attn_int_deasserted0(bp, |
3401 | 4320 | attn.sig[0] & group_mask.sig[0]); | |
3402 | } else if (attn.sig[3] & BNX2X_MCP_ASSERT) { | ||
3403 | |||
3404 | BNX2X_ERR("MCP assert!\n"); | ||
3405 | REG_WR(bp, | ||
3406 | MISC_REG_AEU_GENERAL_ATTN_11, 0); | ||
3407 | bnx2x_mc_assert(bp); | ||
3408 | |||
3409 | } else { | ||
3410 | BNX2X_ERR("UNKOWEN HW ASSERT!\n"); | ||
3411 | } | ||
3412 | } | ||
3413 | |||
3414 | if (attn.sig[1] & group_mask.sig[1] & | ||
3415 | BNX2X_DOORQ_ASSERT) { | ||
3416 | |||
3417 | val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); | ||
3418 | BNX2X_ERR("DB hw attention 0x%x\n", val); | ||
3419 | /* DORQ discard attention */ | ||
3420 | if (val & 0x2) | ||
3421 | BNX2X_ERR("FATAL error from DORQ\n"); | ||
3422 | } | ||
3423 | |||
3424 | if (attn.sig[2] & group_mask.sig[2] & | ||
3425 | AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { | ||
3426 | |||
3427 | val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); | ||
3428 | BNX2X_ERR("CFC hw attention 0x%x\n", val); | ||
3429 | /* CFC error attention */ | ||
3430 | if (val & 0x2) | ||
3431 | BNX2X_ERR("FATAL error from CFC\n"); | ||
3432 | } | ||
3433 | |||
3434 | if (attn.sig[2] & group_mask.sig[2] & | ||
3435 | AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { | ||
3436 | |||
3437 | val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); | ||
3438 | BNX2X_ERR("PXP hw attention 0x%x\n", val); | ||
3439 | /* RQ_USDMDP_FIFO_OVERFLOW */ | ||
3440 | if (val & 0x18000) | ||
3441 | BNX2X_ERR("FATAL error from PXP\n"); | ||
3442 | } | ||
3443 | |||
3444 | if (attn.sig[3] & group_mask.sig[3] & | ||
3445 | EVEREST_LATCHED_ATTN_IN_USE_MASK) { | ||
3446 | |||
3447 | REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, | ||
3448 | 0x7ff); | ||
3449 | DP(NETIF_MSG_HW, "got latched bits 0x%x\n", | ||
3450 | attn.sig[3]); | ||
3451 | } | ||
3452 | 4321 | ||
3453 | if ((attn.sig[0] & group_mask.sig[0] & | 4322 | if ((attn.sig[0] & group_mask.sig[0] & |
3454 | HW_INTERRUT_ASSERT_SET_0) || | 4323 | HW_INTERRUT_ASSERT_SET_0) || |
@@ -3456,7 +4325,15 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) | |||
3456 | HW_INTERRUT_ASSERT_SET_1) || | 4325 | HW_INTERRUT_ASSERT_SET_1) || |
3457 | (attn.sig[2] & group_mask.sig[2] & | 4326 | (attn.sig[2] & group_mask.sig[2] & |
3458 | HW_INTERRUT_ASSERT_SET_2)) | 4327 | HW_INTERRUT_ASSERT_SET_2)) |
3459 | BNX2X_ERR("FATAL HW block attention\n"); | 4328 | BNX2X_ERR("FATAL HW block attention" |
4329 | " set0 0x%x set1 0x%x" | ||
4330 | " set2 0x%x\n", | ||
4331 | (attn.sig[0] & group_mask.sig[0] & | ||
4332 | HW_INTERRUT_ASSERT_SET_0), | ||
4333 | (attn.sig[1] & group_mask.sig[1] & | ||
4334 | HW_INTERRUT_ASSERT_SET_1), | ||
4335 | (attn.sig[2] & group_mask.sig[2] & | ||
4336 | HW_INTERRUT_ASSERT_SET_2)); | ||
3460 | 4337 | ||
3461 | if ((attn.sig[0] & group_mask.sig[0] & | 4338 | if ((attn.sig[0] & group_mask.sig[0] & |
3462 | HW_PRTY_ASSERT_SET_0) || | 4339 | HW_PRTY_ASSERT_SET_0) || |
@@ -3464,7 +4341,7 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) | |||
3464 | HW_PRTY_ASSERT_SET_1) || | 4341 | HW_PRTY_ASSERT_SET_1) || |
3465 | (attn.sig[2] & group_mask.sig[2] & | 4342 | (attn.sig[2] & group_mask.sig[2] & |
3466 | HW_PRTY_ASSERT_SET_2)) | 4343 | HW_PRTY_ASSERT_SET_2)) |
3467 | BNX2X_ERR("FATAL HW block parity atention\n"); | 4344 | BNX2X_ERR("FATAL HW block parity attention\n"); |
3468 | } | 4345 | } |
3469 | } | 4346 | } |
3470 | 4347 | ||
@@ -3529,7 +4406,7 @@ static void bnx2x_sp_task(struct work_struct *work) | |||
3529 | 4406 | ||
3530 | /* Return here if interrupt is disabled */ | 4407 | /* Return here if interrupt is disabled */ |
3531 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) { | 4408 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) { |
3532 | DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n"); | 4409 | DP(BNX2X_MSG_SP, "called but intr_sem not 0, returning\n"); |
3533 | return; | 4410 | return; |
3534 | } | 4411 | } |
3535 | 4412 | ||
@@ -3539,12 +4416,11 @@ static void bnx2x_sp_task(struct work_struct *work) | |||
3539 | 4416 | ||
3540 | DP(NETIF_MSG_INTR, "got a slowpath interrupt (updated %x)\n", status); | 4417 | DP(NETIF_MSG_INTR, "got a slowpath interrupt (updated %x)\n", status); |
3541 | 4418 | ||
3542 | if (status & 0x1) { | 4419 | /* HW attentions */ |
3543 | /* HW attentions */ | 4420 | if (status & 0x1) |
3544 | bnx2x_attn_int(bp); | 4421 | bnx2x_attn_int(bp); |
3545 | } | ||
3546 | 4422 | ||
3547 | /* CStorm events: query_stats, cfc delete ramrods */ | 4423 | /* CStorm events: query_stats, port delete ramrod */ |
3548 | if (status & 0x2) | 4424 | if (status & 0x2) |
3549 | bp->stat_pending = 0; | 4425 | bp->stat_pending = 0; |
3550 | 4426 | ||
@@ -3558,6 +4434,7 @@ static void bnx2x_sp_task(struct work_struct *work) | |||
3558 | IGU_INT_NOP, 1); | 4434 | IGU_INT_NOP, 1); |
3559 | bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, le16_to_cpu(bp->def_t_idx), | 4435 | bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, le16_to_cpu(bp->def_t_idx), |
3560 | IGU_INT_ENABLE, 1); | 4436 | IGU_INT_ENABLE, 1); |
4437 | |||
3561 | } | 4438 | } |
3562 | 4439 | ||
3563 | static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) | 4440 | static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) |
@@ -3567,11 +4444,11 @@ static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance) | |||
3567 | 4444 | ||
3568 | /* Return here if interrupt is disabled */ | 4445 | /* Return here if interrupt is disabled */ |
3569 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) { | 4446 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) { |
3570 | DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n"); | 4447 | DP(BNX2X_MSG_SP, "called but intr_sem not 0, returning\n"); |
3571 | return IRQ_HANDLED; | 4448 | return IRQ_HANDLED; |
3572 | } | 4449 | } |
3573 | 4450 | ||
3574 | bnx2x_ack_sb(bp, 16, XSTORM_ID, 0, IGU_INT_DISABLE, 0); | 4451 | bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, 0, IGU_INT_DISABLE, 0); |
3575 | 4452 | ||
3576 | #ifdef BNX2X_STOP_ON_ERROR | 4453 | #ifdef BNX2X_STOP_ON_ERROR |
3577 | if (unlikely(bp->panic)) | 4454 | if (unlikely(bp->panic)) |
@@ -3906,7 +4783,7 @@ static void bnx2x_stop_stats(struct bnx2x *bp) | |||
3906 | 4783 | ||
3907 | while (bp->stats_state != STATS_STATE_DISABLE) { | 4784 | while (bp->stats_state != STATS_STATE_DISABLE) { |
3908 | if (!timeout) { | 4785 | if (!timeout) { |
3909 | BNX2X_ERR("timeout wating for stats stop\n"); | 4786 | BNX2X_ERR("timeout waiting for stats stop\n"); |
3910 | break; | 4787 | break; |
3911 | } | 4788 | } |
3912 | timeout--; | 4789 | timeout--; |
@@ -4173,39 +5050,37 @@ static void bnx2x_update_net_stats(struct bnx2x *bp) | |||
4173 | 5050 | ||
4174 | nstats->rx_bytes = bnx2x_hilo(&estats->total_bytes_received_hi); | 5051 | nstats->rx_bytes = bnx2x_hilo(&estats->total_bytes_received_hi); |
4175 | 5052 | ||
4176 | nstats->tx_bytes = | 5053 | nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi); |
4177 | bnx2x_hilo(&estats->total_bytes_transmitted_hi); | ||
4178 | 5054 | ||
4179 | nstats->rx_dropped = estats->checksum_discard + | 5055 | nstats->rx_dropped = estats->checksum_discard + estats->mac_discard; |
4180 | estats->mac_discard; | ||
4181 | nstats->tx_dropped = 0; | 5056 | nstats->tx_dropped = 0; |
4182 | 5057 | ||
4183 | nstats->multicast = | 5058 | nstats->multicast = |
4184 | bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi); | 5059 | bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi); |
4185 | 5060 | ||
4186 | nstats->collisions = | 5061 | nstats->collisions = estats->single_collision_transmit_frames + |
4187 | estats->single_collision_transmit_frames + | 5062 | estats->multiple_collision_transmit_frames + |
4188 | estats->multiple_collision_transmit_frames + | 5063 | estats->late_collision_frames + |
4189 | estats->late_collision_frames + | 5064 | estats->excessive_collision_frames; |
4190 | estats->excessive_collision_frames; | ||
4191 | 5065 | ||
4192 | nstats->rx_length_errors = estats->runt_packets_received + | 5066 | nstats->rx_length_errors = estats->runt_packets_received + |
4193 | estats->jabber_packets_received; | 5067 | estats->jabber_packets_received; |
4194 | nstats->rx_over_errors = estats->no_buff_discard; | 5068 | nstats->rx_over_errors = estats->brb_discard + |
5069 | estats->brb_truncate_discard; | ||
4195 | nstats->rx_crc_errors = estats->crc_receive_errors; | 5070 | nstats->rx_crc_errors = estats->crc_receive_errors; |
4196 | nstats->rx_frame_errors = estats->alignment_errors; | 5071 | nstats->rx_frame_errors = estats->alignment_errors; |
4197 | nstats->rx_fifo_errors = estats->brb_discard + | 5072 | nstats->rx_fifo_errors = estats->no_buff_discard; |
4198 | estats->brb_truncate_discard; | ||
4199 | nstats->rx_missed_errors = estats->xxoverflow_discard; | 5073 | nstats->rx_missed_errors = estats->xxoverflow_discard; |
4200 | 5074 | ||
4201 | nstats->rx_errors = nstats->rx_length_errors + | 5075 | nstats->rx_errors = nstats->rx_length_errors + |
4202 | nstats->rx_over_errors + | 5076 | nstats->rx_over_errors + |
4203 | nstats->rx_crc_errors + | 5077 | nstats->rx_crc_errors + |
4204 | nstats->rx_frame_errors + | 5078 | nstats->rx_frame_errors + |
4205 | nstats->rx_fifo_errors; | 5079 | nstats->rx_fifo_errors + |
5080 | nstats->rx_missed_errors; | ||
4206 | 5081 | ||
4207 | nstats->tx_aborted_errors = estats->late_collision_frames + | 5082 | nstats->tx_aborted_errors = estats->late_collision_frames + |
4208 | estats->excessive_collision_frames; | 5083 | estats->excessive_collision_frames; |
4209 | nstats->tx_carrier_errors = estats->false_carrier_detections; | 5084 | nstats->tx_carrier_errors = estats->false_carrier_detections; |
4210 | nstats->tx_fifo_errors = 0; | 5085 | nstats->tx_fifo_errors = 0; |
4211 | nstats->tx_heartbeat_errors = 0; | 5086 | nstats->tx_heartbeat_errors = 0; |
@@ -4334,7 +5209,7 @@ static void bnx2x_timer(unsigned long data) | |||
4334 | return; | 5209 | return; |
4335 | 5210 | ||
4336 | if (atomic_read(&bp->intr_sem) != 0) | 5211 | if (atomic_read(&bp->intr_sem) != 0) |
4337 | goto bnx2x_restart_timer; | 5212 | goto timer_restart; |
4338 | 5213 | ||
4339 | if (poll) { | 5214 | if (poll) { |
4340 | struct bnx2x_fastpath *fp = &bp->fp[0]; | 5215 | struct bnx2x_fastpath *fp = &bp->fp[0]; |
@@ -4344,7 +5219,7 @@ static void bnx2x_timer(unsigned long data) | |||
4344 | rc = bnx2x_rx_int(fp, 1000); | 5219 | rc = bnx2x_rx_int(fp, 1000); |
4345 | } | 5220 | } |
4346 | 5221 | ||
4347 | if (!nomcp && (bp->bc_ver >= 0x040003)) { | 5222 | if (!nomcp) { |
4348 | int port = bp->port; | 5223 | int port = bp->port; |
4349 | u32 drv_pulse; | 5224 | u32 drv_pulse; |
4350 | u32 mcp_pulse; | 5225 | u32 mcp_pulse; |
@@ -4353,9 +5228,9 @@ static void bnx2x_timer(unsigned long data) | |||
4353 | bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; | 5228 | bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; |
4354 | /* TBD - add SYSTEM_TIME */ | 5229 | /* TBD - add SYSTEM_TIME */ |
4355 | drv_pulse = bp->fw_drv_pulse_wr_seq; | 5230 | drv_pulse = bp->fw_drv_pulse_wr_seq; |
4356 | SHMEM_WR(bp, drv_fw_mb[port].drv_pulse_mb, drv_pulse); | 5231 | SHMEM_WR(bp, func_mb[port].drv_pulse_mb, drv_pulse); |
4357 | 5232 | ||
4358 | mcp_pulse = (SHMEM_RD(bp, drv_fw_mb[port].mcp_pulse_mb) & | 5233 | mcp_pulse = (SHMEM_RD(bp, func_mb[port].mcp_pulse_mb) & |
4359 | MCP_PULSE_SEQ_MASK); | 5234 | MCP_PULSE_SEQ_MASK); |
4360 | /* The delta between driver pulse and mcp response | 5235 | /* The delta between driver pulse and mcp response |
4361 | * should be 1 (before mcp response) or 0 (after mcp response) | 5236 | * should be 1 (before mcp response) or 0 (after mcp response) |
@@ -4369,11 +5244,11 @@ static void bnx2x_timer(unsigned long data) | |||
4369 | } | 5244 | } |
4370 | 5245 | ||
4371 | if (bp->stats_state == STATS_STATE_DISABLE) | 5246 | if (bp->stats_state == STATS_STATE_DISABLE) |
4372 | goto bnx2x_restart_timer; | 5247 | goto timer_restart; |
4373 | 5248 | ||
4374 | bnx2x_update_stats(bp); | 5249 | bnx2x_update_stats(bp); |
4375 | 5250 | ||
4376 | bnx2x_restart_timer: | 5251 | timer_restart: |
4377 | mod_timer(&bp->timer, jiffies + bp->current_interval); | 5252 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
4378 | } | 5253 | } |
4379 | 5254 | ||
@@ -4438,6 +5313,9 @@ static void bnx2x_init_def_sb(struct bnx2x *bp, | |||
4438 | atten_status_block); | 5313 | atten_status_block); |
4439 | def_sb->atten_status_block.status_block_id = id; | 5314 | def_sb->atten_status_block.status_block_id = id; |
4440 | 5315 | ||
5316 | bp->def_att_idx = 0; | ||
5317 | bp->attn_state = 0; | ||
5318 | |||
4441 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : | 5319 | reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : |
4442 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | 5320 | MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); |
4443 | 5321 | ||
@@ -4472,6 +5350,8 @@ static void bnx2x_init_def_sb(struct bnx2x *bp, | |||
4472 | u_def_status_block); | 5350 | u_def_status_block); |
4473 | def_sb->u_def_status_block.status_block_id = id; | 5351 | def_sb->u_def_status_block.status_block_id = id; |
4474 | 5352 | ||
5353 | bp->def_u_idx = 0; | ||
5354 | |||
4475 | REG_WR(bp, BAR_USTRORM_INTMEM + | 5355 | REG_WR(bp, BAR_USTRORM_INTMEM + |
4476 | USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port), U64_LO(section)); | 5356 | USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port), U64_LO(section)); |
4477 | REG_WR(bp, BAR_USTRORM_INTMEM + | 5357 | REG_WR(bp, BAR_USTRORM_INTMEM + |
@@ -4489,6 +5369,8 @@ static void bnx2x_init_def_sb(struct bnx2x *bp, | |||
4489 | c_def_status_block); | 5369 | c_def_status_block); |
4490 | def_sb->c_def_status_block.status_block_id = id; | 5370 | def_sb->c_def_status_block.status_block_id = id; |
4491 | 5371 | ||
5372 | bp->def_c_idx = 0; | ||
5373 | |||
4492 | REG_WR(bp, BAR_CSTRORM_INTMEM + | 5374 | REG_WR(bp, BAR_CSTRORM_INTMEM + |
4493 | CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port), U64_LO(section)); | 5375 | CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port), U64_LO(section)); |
4494 | REG_WR(bp, BAR_CSTRORM_INTMEM + | 5376 | REG_WR(bp, BAR_CSTRORM_INTMEM + |
@@ -4506,6 +5388,8 @@ static void bnx2x_init_def_sb(struct bnx2x *bp, | |||
4506 | t_def_status_block); | 5388 | t_def_status_block); |
4507 | def_sb->t_def_status_block.status_block_id = id; | 5389 | def_sb->t_def_status_block.status_block_id = id; |
4508 | 5390 | ||
5391 | bp->def_t_idx = 0; | ||
5392 | |||
4509 | REG_WR(bp, BAR_TSTRORM_INTMEM + | 5393 | REG_WR(bp, BAR_TSTRORM_INTMEM + |
4510 | TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port), U64_LO(section)); | 5394 | TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port), U64_LO(section)); |
4511 | REG_WR(bp, BAR_TSTRORM_INTMEM + | 5395 | REG_WR(bp, BAR_TSTRORM_INTMEM + |
@@ -4523,6 +5407,8 @@ static void bnx2x_init_def_sb(struct bnx2x *bp, | |||
4523 | x_def_status_block); | 5407 | x_def_status_block); |
4524 | def_sb->x_def_status_block.status_block_id = id; | 5408 | def_sb->x_def_status_block.status_block_id = id; |
4525 | 5409 | ||
5410 | bp->def_x_idx = 0; | ||
5411 | |||
4526 | REG_WR(bp, BAR_XSTRORM_INTMEM + | 5412 | REG_WR(bp, BAR_XSTRORM_INTMEM + |
4527 | XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port), U64_LO(section)); | 5413 | XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port), U64_LO(section)); |
4528 | REG_WR(bp, BAR_XSTRORM_INTMEM + | 5414 | REG_WR(bp, BAR_XSTRORM_INTMEM + |
@@ -4535,6 +5421,8 @@ static void bnx2x_init_def_sb(struct bnx2x *bp, | |||
4535 | REG_WR16(bp, BAR_XSTRORM_INTMEM + | 5421 | REG_WR16(bp, BAR_XSTRORM_INTMEM + |
4536 | XSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index), 0x1); | 5422 | XSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index), 0x1); |
4537 | 5423 | ||
5424 | bp->stat_pending = 0; | ||
5425 | |||
4538 | bnx2x_ack_sb(bp, id, CSTORM_ID, 0, IGU_INT_ENABLE, 0); | 5426 | bnx2x_ack_sb(bp, id, CSTORM_ID, 0, IGU_INT_ENABLE, 0); |
4539 | } | 5427 | } |
4540 | 5428 | ||
@@ -4626,7 +5514,7 @@ static void bnx2x_init_rx_rings(struct bnx2x *bp) | |||
4626 | fp->rx_bd_prod = fp->rx_comp_prod = ring_prod; | 5514 | fp->rx_bd_prod = fp->rx_comp_prod = ring_prod; |
4627 | fp->rx_pkt = fp->rx_calls = 0; | 5515 | fp->rx_pkt = fp->rx_calls = 0; |
4628 | 5516 | ||
4629 | /* Warning! this will genrate an interrupt (to the TSTORM) */ | 5517 | /* Warning! this will generate an interrupt (to the TSTORM) */ |
4630 | /* must only be done when chip is initialized */ | 5518 | /* must only be done when chip is initialized */ |
4631 | REG_WR(bp, BAR_TSTRORM_INTMEM + | 5519 | REG_WR(bp, BAR_TSTRORM_INTMEM + |
4632 | TSTORM_RCQ_PROD_OFFSET(port, j), ring_prod); | 5520 | TSTORM_RCQ_PROD_OFFSET(port, j), ring_prod); |
@@ -4678,7 +5566,6 @@ static void bnx2x_init_sp_ring(struct bnx2x *bp) | |||
4678 | 5566 | ||
4679 | bp->spq_left = MAX_SPQ_PENDING; | 5567 | bp->spq_left = MAX_SPQ_PENDING; |
4680 | bp->spq_prod_idx = 0; | 5568 | bp->spq_prod_idx = 0; |
4681 | bp->dsb_sp_prod_idx = 0; | ||
4682 | bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; | 5569 | bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; |
4683 | bp->spq_prod_bd = bp->spq; | 5570 | bp->spq_prod_bd = bp->spq; |
4684 | bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; | 5571 | bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; |
@@ -4755,6 +5642,42 @@ static void bnx2x_init_ind_table(struct bnx2x *bp) | |||
4755 | REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); | 5642 | REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); |
4756 | } | 5643 | } |
4757 | 5644 | ||
5645 | static void bnx2x_set_client_config(struct bnx2x *bp) | ||
5646 | { | ||
5647 | #ifdef BCM_VLAN | ||
5648 | int mode = bp->rx_mode; | ||
5649 | #endif | ||
5650 | int i, port = bp->port; | ||
5651 | struct tstorm_eth_client_config tstorm_client = {0}; | ||
5652 | |||
5653 | tstorm_client.mtu = bp->dev->mtu; | ||
5654 | tstorm_client.statistics_counter_id = 0; | ||
5655 | tstorm_client.config_flags = | ||
5656 | TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE; | ||
5657 | #ifdef BCM_VLAN | ||
5658 | if (mode && bp->vlgrp) { | ||
5659 | tstorm_client.config_flags |= | ||
5660 | TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE; | ||
5661 | DP(NETIF_MSG_IFUP, "vlan removal enabled\n"); | ||
5662 | } | ||
5663 | #endif | ||
5664 | if (mode != BNX2X_RX_MODE_PROMISC) | ||
5665 | tstorm_client.drop_flags = | ||
5666 | TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR; | ||
5667 | |||
5668 | for_each_queue(bp, i) { | ||
5669 | REG_WR(bp, BAR_TSTRORM_INTMEM + | ||
5670 | TSTORM_CLIENT_CONFIG_OFFSET(port, i), | ||
5671 | ((u32 *)&tstorm_client)[0]); | ||
5672 | REG_WR(bp, BAR_TSTRORM_INTMEM + | ||
5673 | TSTORM_CLIENT_CONFIG_OFFSET(port, i) + 4, | ||
5674 | ((u32 *)&tstorm_client)[1]); | ||
5675 | } | ||
5676 | |||
5677 | /* DP(NETIF_MSG_IFUP, "tstorm_client: 0x%08x 0x%08x\n", | ||
5678 | ((u32 *)&tstorm_client)[0], ((u32 *)&tstorm_client)[1]); */ | ||
5679 | } | ||
5680 | |||
4758 | static void bnx2x_set_storm_rx_mode(struct bnx2x *bp) | 5681 | static void bnx2x_set_storm_rx_mode(struct bnx2x *bp) |
4759 | { | 5682 | { |
4760 | int mode = bp->rx_mode; | 5683 | int mode = bp->rx_mode; |
@@ -4794,41 +5717,9 @@ static void bnx2x_set_storm_rx_mode(struct bnx2x *bp) | |||
4794 | /* DP(NETIF_MSG_IFUP, "tstorm_mac_filter[%d]: 0x%08x\n", i, | 5717 | /* DP(NETIF_MSG_IFUP, "tstorm_mac_filter[%d]: 0x%08x\n", i, |
4795 | ((u32 *)&tstorm_mac_filter)[i]); */ | 5718 | ((u32 *)&tstorm_mac_filter)[i]); */ |
4796 | } | 5719 | } |
4797 | } | ||
4798 | 5720 | ||
4799 | static void bnx2x_set_client_config(struct bnx2x *bp, int client_id) | 5721 | if (mode != BNX2X_RX_MODE_NONE) |
4800 | { | 5722 | bnx2x_set_client_config(bp); |
4801 | #ifdef BCM_VLAN | ||
4802 | int mode = bp->rx_mode; | ||
4803 | #endif | ||
4804 | int port = bp->port; | ||
4805 | struct tstorm_eth_client_config tstorm_client = {0}; | ||
4806 | |||
4807 | tstorm_client.mtu = bp->dev->mtu; | ||
4808 | tstorm_client.statistics_counter_id = 0; | ||
4809 | tstorm_client.config_flags = | ||
4810 | TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE; | ||
4811 | #ifdef BCM_VLAN | ||
4812 | if (mode && bp->vlgrp) { | ||
4813 | tstorm_client.config_flags |= | ||
4814 | TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE; | ||
4815 | DP(NETIF_MSG_IFUP, "vlan removal enabled\n"); | ||
4816 | } | ||
4817 | #endif | ||
4818 | tstorm_client.drop_flags = (TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR | | ||
4819 | TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR | | ||
4820 | TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR | | ||
4821 | TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR); | ||
4822 | |||
4823 | REG_WR(bp, BAR_TSTRORM_INTMEM + | ||
4824 | TSTORM_CLIENT_CONFIG_OFFSET(port, client_id), | ||
4825 | ((u32 *)&tstorm_client)[0]); | ||
4826 | REG_WR(bp, BAR_TSTRORM_INTMEM + | ||
4827 | TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) + 4, | ||
4828 | ((u32 *)&tstorm_client)[1]); | ||
4829 | |||
4830 | /* DP(NETIF_MSG_IFUP, "tstorm_client: 0x%08x 0x%08x\n", | ||
4831 | ((u32 *)&tstorm_client)[0], ((u32 *)&tstorm_client)[1]); */ | ||
4832 | } | 5723 | } |
4833 | 5724 | ||
4834 | static void bnx2x_init_internal(struct bnx2x *bp) | 5725 | static void bnx2x_init_internal(struct bnx2x *bp) |
@@ -4836,7 +5727,6 @@ static void bnx2x_init_internal(struct bnx2x *bp) | |||
4836 | int port = bp->port; | 5727 | int port = bp->port; |
4837 | struct tstorm_eth_function_common_config tstorm_config = {0}; | 5728 | struct tstorm_eth_function_common_config tstorm_config = {0}; |
4838 | struct stats_indication_flags stats_flags = {0}; | 5729 | struct stats_indication_flags stats_flags = {0}; |
4839 | int i; | ||
4840 | 5730 | ||
4841 | if (is_multi(bp)) { | 5731 | if (is_multi(bp)) { |
4842 | tstorm_config.config_flags = MULTI_FLAGS; | 5732 | tstorm_config.config_flags = MULTI_FLAGS; |
@@ -4850,13 +5740,9 @@ static void bnx2x_init_internal(struct bnx2x *bp) | |||
4850 | /* DP(NETIF_MSG_IFUP, "tstorm_config: 0x%08x\n", | 5740 | /* DP(NETIF_MSG_IFUP, "tstorm_config: 0x%08x\n", |
4851 | (*(u32 *)&tstorm_config)); */ | 5741 | (*(u32 *)&tstorm_config)); */ |
4852 | 5742 | ||
4853 | bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx untill link is up */ | 5743 | bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx until link is up */ |
4854 | bnx2x_set_storm_rx_mode(bp); | 5744 | bnx2x_set_storm_rx_mode(bp); |
4855 | 5745 | ||
4856 | for_each_queue(bp, i) | ||
4857 | bnx2x_set_client_config(bp, i); | ||
4858 | |||
4859 | |||
4860 | stats_flags.collect_eth = cpu_to_le32(1); | 5746 | stats_flags.collect_eth = cpu_to_le32(1); |
4861 | 5747 | ||
4862 | REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(port), | 5748 | REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(port), |
@@ -4902,7 +5788,7 @@ static void bnx2x_nic_init(struct bnx2x *bp) | |||
4902 | bnx2x_init_internal(bp); | 5788 | bnx2x_init_internal(bp); |
4903 | bnx2x_init_stats(bp); | 5789 | bnx2x_init_stats(bp); |
4904 | bnx2x_init_ind_table(bp); | 5790 | bnx2x_init_ind_table(bp); |
4905 | bnx2x_enable_int(bp); | 5791 | bnx2x_int_enable(bp); |
4906 | 5792 | ||
4907 | } | 5793 | } |
4908 | 5794 | ||
@@ -5265,8 +6151,10 @@ static int bnx2x_function_init(struct bnx2x *bp, int mode) | |||
5265 | if (mode & 0x1) { /* init common */ | 6151 | if (mode & 0x1) { /* init common */ |
5266 | DP(BNX2X_MSG_MCP, "starting common init func %d mode %x\n", | 6152 | DP(BNX2X_MSG_MCP, "starting common init func %d mode %x\n", |
5267 | func, mode); | 6153 | func, mode); |
5268 | REG_WR(bp, MISC_REG_RESET_REG_1, 0xffffffff); | 6154 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, |
5269 | REG_WR(bp, MISC_REG_RESET_REG_2, 0xfffc); | 6155 | 0xffffffff); |
6156 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, | ||
6157 | 0xfffc); | ||
5270 | bnx2x_init_block(bp, MISC_COMMON_START, MISC_COMMON_END); | 6158 | bnx2x_init_block(bp, MISC_COMMON_START, MISC_COMMON_END); |
5271 | 6159 | ||
5272 | REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x100); | 6160 | REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x100); |
@@ -5359,7 +6247,7 @@ static int bnx2x_function_init(struct bnx2x *bp, int mode) | |||
5359 | REG_RD(bp, USEM_REG_PASSIVE_BUFFER + 8); | 6247 | REG_RD(bp, USEM_REG_PASSIVE_BUFFER + 8); |
5360 | #endif | 6248 | #endif |
5361 | bnx2x_init_block(bp, QM_COMMON_START, QM_COMMON_END); | 6249 | bnx2x_init_block(bp, QM_COMMON_START, QM_COMMON_END); |
5362 | /* softrest pulse */ | 6250 | /* soft reset pulse */ |
5363 | REG_WR(bp, QM_REG_SOFT_RESET, 1); | 6251 | REG_WR(bp, QM_REG_SOFT_RESET, 1); |
5364 | REG_WR(bp, QM_REG_SOFT_RESET, 0); | 6252 | REG_WR(bp, QM_REG_SOFT_RESET, 0); |
5365 | 6253 | ||
@@ -5413,7 +6301,7 @@ static int bnx2x_function_init(struct bnx2x *bp, int mode) | |||
5413 | REG_WR(bp, SRC_REG_SOFT_RST, 1); | 6301 | REG_WR(bp, SRC_REG_SOFT_RST, 1); |
5414 | for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4) { | 6302 | for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4) { |
5415 | REG_WR(bp, i, 0xc0cac01a); | 6303 | REG_WR(bp, i, 0xc0cac01a); |
5416 | /* TODO: repleace with something meaningfull */ | 6304 | /* TODO: replace with something meaningful */ |
5417 | } | 6305 | } |
5418 | /* SRCH COMMON comes here */ | 6306 | /* SRCH COMMON comes here */ |
5419 | REG_WR(bp, SRC_REG_SOFT_RST, 0); | 6307 | REG_WR(bp, SRC_REG_SOFT_RST, 0); |
@@ -5486,6 +6374,28 @@ static int bnx2x_function_init(struct bnx2x *bp, int mode) | |||
5486 | enable_blocks_attention(bp); | 6374 | enable_blocks_attention(bp); |
5487 | /* enable_blocks_parity(bp); */ | 6375 | /* enable_blocks_parity(bp); */ |
5488 | 6376 | ||
6377 | switch (bp->board & SHARED_HW_CFG_BOARD_TYPE_MASK) { | ||
6378 | case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G: | ||
6379 | /* Fan failure is indicated by SPIO 5 */ | ||
6380 | bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5, | ||
6381 | MISC_REGISTERS_SPIO_INPUT_HI_Z); | ||
6382 | |||
6383 | /* set to active low mode */ | ||
6384 | val = REG_RD(bp, MISC_REG_SPIO_INT); | ||
6385 | val |= ((1 << MISC_REGISTERS_SPIO_5) << | ||
6386 | MISC_REGISTERS_SPIO_INT_OLD_SET_POS); | ||
6387 | REG_WR(bp, MISC_REG_SPIO_INT, val); | ||
6388 | |||
6389 | /* enable interrupt to signal the IGU */ | ||
6390 | val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); | ||
6391 | val |= (1 << MISC_REGISTERS_SPIO_5); | ||
6392 | REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); | ||
6393 | break; | ||
6394 | |||
6395 | default: | ||
6396 | break; | ||
6397 | } | ||
6398 | |||
5489 | } /* end of common init */ | 6399 | } /* end of common init */ |
5490 | 6400 | ||
5491 | /* per port init */ | 6401 | /* per port init */ |
@@ -5645,9 +6555,21 @@ static int bnx2x_function_init(struct bnx2x *bp, int mode) | |||
5645 | /* Port MCP comes here */ | 6555 | /* Port MCP comes here */ |
5646 | /* Port DMAE comes here */ | 6556 | /* Port DMAE comes here */ |
5647 | 6557 | ||
6558 | switch (bp->board & SHARED_HW_CFG_BOARD_TYPE_MASK) { | ||
6559 | case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G: | ||
6560 | /* add SPIO 5 to group 0 */ | ||
6561 | val = REG_RD(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); | ||
6562 | val |= AEU_INPUTS_ATTN_BITS_SPIO5; | ||
6563 | REG_WR(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, val); | ||
6564 | break; | ||
6565 | |||
6566 | default: | ||
6567 | break; | ||
6568 | } | ||
6569 | |||
5648 | bnx2x_link_reset(bp); | 6570 | bnx2x_link_reset(bp); |
5649 | 6571 | ||
5650 | /* Reset pciex errors for debug */ | 6572 | /* Reset PCIE errors for debug */ |
5651 | REG_WR(bp, 0x2114, 0xffffffff); | 6573 | REG_WR(bp, 0x2114, 0xffffffff); |
5652 | REG_WR(bp, 0x2120, 0xffffffff); | 6574 | REG_WR(bp, 0x2120, 0xffffffff); |
5653 | REG_WR(bp, 0x2814, 0xffffffff); | 6575 | REG_WR(bp, 0x2814, 0xffffffff); |
@@ -5669,9 +6591,9 @@ static int bnx2x_function_init(struct bnx2x *bp, int mode) | |||
5669 | port = bp->port; | 6591 | port = bp->port; |
5670 | 6592 | ||
5671 | bp->fw_drv_pulse_wr_seq = | 6593 | bp->fw_drv_pulse_wr_seq = |
5672 | (SHMEM_RD(bp, drv_fw_mb[port].drv_pulse_mb) & | 6594 | (SHMEM_RD(bp, func_mb[port].drv_pulse_mb) & |
5673 | DRV_PULSE_SEQ_MASK); | 6595 | DRV_PULSE_SEQ_MASK); |
5674 | bp->fw_mb = SHMEM_RD(bp, drv_fw_mb[port].fw_mb_param); | 6596 | bp->fw_mb = SHMEM_RD(bp, func_mb[port].fw_mb_param); |
5675 | DP(BNX2X_MSG_MCP, "drv_pulse 0x%x fw_mb 0x%x\n", | 6597 | DP(BNX2X_MSG_MCP, "drv_pulse 0x%x fw_mb 0x%x\n", |
5676 | bp->fw_drv_pulse_wr_seq, bp->fw_mb); | 6598 | bp->fw_drv_pulse_wr_seq, bp->fw_mb); |
5677 | } else { | 6599 | } else { |
@@ -5681,16 +6603,15 @@ static int bnx2x_function_init(struct bnx2x *bp, int mode) | |||
5681 | return 0; | 6603 | return 0; |
5682 | } | 6604 | } |
5683 | 6605 | ||
5684 | 6606 | /* send the MCP a request, block until there is a reply */ | |
5685 | /* send the MCP a request, block untill there is a reply */ | ||
5686 | static u32 bnx2x_fw_command(struct bnx2x *bp, u32 command) | 6607 | static u32 bnx2x_fw_command(struct bnx2x *bp, u32 command) |
5687 | { | 6608 | { |
5688 | u32 rc = 0; | ||
5689 | u32 seq = ++bp->fw_seq; | ||
5690 | int port = bp->port; | 6609 | int port = bp->port; |
6610 | u32 seq = ++bp->fw_seq; | ||
6611 | u32 rc = 0; | ||
5691 | 6612 | ||
5692 | SHMEM_WR(bp, drv_fw_mb[port].drv_mb_header, command|seq); | 6613 | SHMEM_WR(bp, func_mb[port].drv_mb_header, (command | seq)); |
5693 | DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", command|seq); | 6614 | DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq)); |
5694 | 6615 | ||
5695 | /* let the FW do it's magic ... */ | 6616 | /* let the FW do it's magic ... */ |
5696 | msleep(100); /* TBD */ | 6617 | msleep(100); /* TBD */ |
@@ -5698,19 +6619,20 @@ static u32 bnx2x_fw_command(struct bnx2x *bp, u32 command) | |||
5698 | if (CHIP_REV_IS_SLOW(bp)) | 6619 | if (CHIP_REV_IS_SLOW(bp)) |
5699 | msleep(900); | 6620 | msleep(900); |
5700 | 6621 | ||
5701 | rc = SHMEM_RD(bp, drv_fw_mb[port].fw_mb_header); | 6622 | rc = SHMEM_RD(bp, func_mb[port].fw_mb_header); |
5702 | |||
5703 | DP(BNX2X_MSG_MCP, "read (%x) seq is (%x) from FW MB\n", rc, seq); | 6623 | DP(BNX2X_MSG_MCP, "read (%x) seq is (%x) from FW MB\n", rc, seq); |
5704 | 6624 | ||
5705 | /* is this a reply to our command? */ | 6625 | /* is this a reply to our command? */ |
5706 | if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) { | 6626 | if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) { |
5707 | rc &= FW_MSG_CODE_MASK; | 6627 | rc &= FW_MSG_CODE_MASK; |
6628 | |||
5708 | } else { | 6629 | } else { |
5709 | /* FW BUG! */ | 6630 | /* FW BUG! */ |
5710 | BNX2X_ERR("FW failed to respond!\n"); | 6631 | BNX2X_ERR("FW failed to respond!\n"); |
5711 | bnx2x_fw_dump(bp); | 6632 | bnx2x_fw_dump(bp); |
5712 | rc = 0; | 6633 | rc = 0; |
5713 | } | 6634 | } |
6635 | |||
5714 | return rc; | 6636 | return rc; |
5715 | } | 6637 | } |
5716 | 6638 | ||
@@ -5869,7 +6791,7 @@ static int bnx2x_alloc_mem(struct bnx2x *bp) | |||
5869 | for (i = 0; i < 16*1024; i += 64) | 6791 | for (i = 0; i < 16*1024; i += 64) |
5870 | * (u64 *)((char *)bp->t2 + i + 56) = bp->t2_mapping + i + 64; | 6792 | * (u64 *)((char *)bp->t2 + i + 56) = bp->t2_mapping + i + 64; |
5871 | 6793 | ||
5872 | /* now sixup the last line in the block to point to the next block */ | 6794 | /* now fixup the last line in the block to point to the next block */ |
5873 | *(u64 *)((char *)bp->t2 + 1024*16-8) = bp->t2_mapping; | 6795 | *(u64 *)((char *)bp->t2 + 1024*16-8) = bp->t2_mapping; |
5874 | 6796 | ||
5875 | /* Timer block array (MAX_CONN*8) phys uncached for now 1024 conns */ | 6797 | /* Timer block array (MAX_CONN*8) phys uncached for now 1024 conns */ |
@@ -5950,22 +6872,19 @@ static void bnx2x_free_msix_irqs(struct bnx2x *bp) | |||
5950 | int i; | 6872 | int i; |
5951 | 6873 | ||
5952 | free_irq(bp->msix_table[0].vector, bp->dev); | 6874 | free_irq(bp->msix_table[0].vector, bp->dev); |
5953 | DP(NETIF_MSG_IFDOWN, "rleased sp irq (%d)\n", | 6875 | DP(NETIF_MSG_IFDOWN, "released sp irq (%d)\n", |
5954 | bp->msix_table[0].vector); | 6876 | bp->msix_table[0].vector); |
5955 | 6877 | ||
5956 | for_each_queue(bp, i) { | 6878 | for_each_queue(bp, i) { |
5957 | DP(NETIF_MSG_IFDOWN, "about to rlease fp #%d->%d irq " | 6879 | DP(NETIF_MSG_IFDOWN, "about to release fp #%d->%d irq " |
5958 | "state(%x)\n", i, bp->msix_table[i + 1].vector, | 6880 | "state(%x)\n", i, bp->msix_table[i + 1].vector, |
5959 | bnx2x_fp(bp, i, state)); | 6881 | bnx2x_fp(bp, i, state)); |
5960 | 6882 | ||
5961 | if (bnx2x_fp(bp, i, state) != BNX2X_FP_STATE_CLOSED) { | 6883 | if (bnx2x_fp(bp, i, state) != BNX2X_FP_STATE_CLOSED) |
5962 | 6884 | BNX2X_ERR("IRQ of fp #%d being freed while " | |
5963 | free_irq(bp->msix_table[i + 1].vector, &bp->fp[i]); | 6885 | "state != closed\n", i); |
5964 | bnx2x_fp(bp, i, state) = BNX2X_FP_STATE_CLOSED; | ||
5965 | |||
5966 | } else | ||
5967 | DP(NETIF_MSG_IFDOWN, "irq not freed\n"); | ||
5968 | 6886 | ||
6887 | free_irq(bp->msix_table[i + 1].vector, &bp->fp[i]); | ||
5969 | } | 6888 | } |
5970 | 6889 | ||
5971 | } | 6890 | } |
@@ -5995,7 +6914,7 @@ static int bnx2x_enable_msix(struct bnx2x *bp) | |||
5995 | 6914 | ||
5996 | if (pci_enable_msix(bp->pdev, &bp->msix_table[0], | 6915 | if (pci_enable_msix(bp->pdev, &bp->msix_table[0], |
5997 | bp->num_queues + 1)){ | 6916 | bp->num_queues + 1)){ |
5998 | BNX2X_ERR("failed to enable msix\n"); | 6917 | BNX2X_LOG("failed to enable MSI-X\n"); |
5999 | return -1; | 6918 | return -1; |
6000 | 6919 | ||
6001 | } | 6920 | } |
@@ -6010,11 +6929,8 @@ static int bnx2x_enable_msix(struct bnx2x *bp) | |||
6010 | static int bnx2x_req_msix_irqs(struct bnx2x *bp) | 6929 | static int bnx2x_req_msix_irqs(struct bnx2x *bp) |
6011 | { | 6930 | { |
6012 | 6931 | ||
6013 | |||
6014 | int i, rc; | 6932 | int i, rc; |
6015 | 6933 | ||
6016 | DP(NETIF_MSG_IFUP, "about to request sp irq\n"); | ||
6017 | |||
6018 | rc = request_irq(bp->msix_table[0].vector, bnx2x_msix_sp_int, 0, | 6934 | rc = request_irq(bp->msix_table[0].vector, bnx2x_msix_sp_int, 0, |
6019 | bp->dev->name, bp->dev); | 6935 | bp->dev->name, bp->dev); |
6020 | 6936 | ||
@@ -6029,7 +6945,8 @@ static int bnx2x_req_msix_irqs(struct bnx2x *bp) | |||
6029 | bp->dev->name, &bp->fp[i]); | 6945 | bp->dev->name, &bp->fp[i]); |
6030 | 6946 | ||
6031 | if (rc) { | 6947 | if (rc) { |
6032 | BNX2X_ERR("request fp #%d irq failed\n", i); | 6948 | BNX2X_ERR("request fp #%d irq failed " |
6949 | "rc %d\n", i, rc); | ||
6033 | bnx2x_free_msix_irqs(bp); | 6950 | bnx2x_free_msix_irqs(bp); |
6034 | return -EBUSY; | 6951 | return -EBUSY; |
6035 | } | 6952 | } |
@@ -6109,8 +7026,8 @@ static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx, | |||
6109 | /* can take a while if any port is running */ | 7026 | /* can take a while if any port is running */ |
6110 | int timeout = 500; | 7027 | int timeout = 500; |
6111 | 7028 | ||
6112 | /* DP("waiting for state to become %d on IDX [%d]\n", | 7029 | DP(NETIF_MSG_IFUP, "%s for state to become %x on IDX [%d]\n", |
6113 | state, sb_idx); */ | 7030 | poll ? "polling" : "waiting", state, idx); |
6114 | 7031 | ||
6115 | might_sleep(); | 7032 | might_sleep(); |
6116 | 7033 | ||
@@ -6128,7 +7045,7 @@ static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx, | |||
6128 | 7045 | ||
6129 | mb(); /* state is changed by bnx2x_sp_event()*/ | 7046 | mb(); /* state is changed by bnx2x_sp_event()*/ |
6130 | 7047 | ||
6131 | if (*state_p != state) | 7048 | if (*state_p == state) |
6132 | return 0; | 7049 | return 0; |
6133 | 7050 | ||
6134 | timeout--; | 7051 | timeout--; |
@@ -6136,17 +7053,17 @@ static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx, | |||
6136 | 7053 | ||
6137 | } | 7054 | } |
6138 | 7055 | ||
6139 | |||
6140 | /* timeout! */ | 7056 | /* timeout! */ |
6141 | BNX2X_ERR("timeout waiting for ramrod %d on %d\n", state, idx); | 7057 | BNX2X_ERR("timeout %s for state %x on IDX [%d]\n", |
6142 | return -EBUSY; | 7058 | poll ? "polling" : "waiting", state, idx); |
6143 | 7059 | ||
7060 | return -EBUSY; | ||
6144 | } | 7061 | } |
6145 | 7062 | ||
6146 | static int bnx2x_setup_leading(struct bnx2x *bp) | 7063 | static int bnx2x_setup_leading(struct bnx2x *bp) |
6147 | { | 7064 | { |
6148 | 7065 | ||
6149 | /* reset IGU staae */ | 7066 | /* reset IGU state */ |
6150 | bnx2x_ack_sb(bp, DEF_SB_ID, CSTORM_ID, 0, IGU_INT_ENABLE, 0); | 7067 | bnx2x_ack_sb(bp, DEF_SB_ID, CSTORM_ID, 0, IGU_INT_ENABLE, 0); |
6151 | 7068 | ||
6152 | /* SETUP ramrod */ | 7069 | /* SETUP ramrod */ |
@@ -6162,12 +7079,13 @@ static int bnx2x_setup_multi(struct bnx2x *bp, int index) | |||
6162 | /* reset IGU state */ | 7079 | /* reset IGU state */ |
6163 | bnx2x_ack_sb(bp, index, CSTORM_ID, 0, IGU_INT_ENABLE, 0); | 7080 | bnx2x_ack_sb(bp, index, CSTORM_ID, 0, IGU_INT_ENABLE, 0); |
6164 | 7081 | ||
7082 | /* SETUP ramrod */ | ||
6165 | bp->fp[index].state = BNX2X_FP_STATE_OPENING; | 7083 | bp->fp[index].state = BNX2X_FP_STATE_OPENING; |
6166 | bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CLIENT_SETUP, index, 0, index, 0); | 7084 | bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CLIENT_SETUP, index, 0, index, 0); |
6167 | 7085 | ||
6168 | /* Wait for completion */ | 7086 | /* Wait for completion */ |
6169 | return bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_OPEN, index, | 7087 | return bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_OPEN, index, |
6170 | &(bp->fp[index].state), 1); | 7088 | &(bp->fp[index].state), 0); |
6171 | 7089 | ||
6172 | } | 7090 | } |
6173 | 7091 | ||
@@ -6177,8 +7095,8 @@ static void bnx2x_set_rx_mode(struct net_device *dev); | |||
6177 | 7095 | ||
6178 | static int bnx2x_nic_load(struct bnx2x *bp, int req_irq) | 7096 | static int bnx2x_nic_load(struct bnx2x *bp, int req_irq) |
6179 | { | 7097 | { |
6180 | int rc; | 7098 | u32 load_code; |
6181 | int i = 0; | 7099 | int i; |
6182 | 7100 | ||
6183 | bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD; | 7101 | bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD; |
6184 | 7102 | ||
@@ -6188,26 +7106,28 @@ static int bnx2x_nic_load(struct bnx2x *bp, int req_irq) | |||
6188 | initialized, otherwise - not. | 7106 | initialized, otherwise - not. |
6189 | */ | 7107 | */ |
6190 | if (!nomcp) { | 7108 | if (!nomcp) { |
6191 | rc = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ); | 7109 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ); |
6192 | if (rc == FW_MSG_CODE_DRV_LOAD_REFUSED) { | 7110 | if (!load_code) { |
7111 | BNX2X_ERR("MCP response failure, unloading\n"); | ||
7112 | return -EBUSY; | ||
7113 | } | ||
7114 | if (load_code == FW_MSG_CODE_DRV_LOAD_REFUSED) { | ||
7115 | BNX2X_ERR("MCP refused load request, unloading\n"); | ||
6193 | return -EBUSY; /* other port in diagnostic mode */ | 7116 | return -EBUSY; /* other port in diagnostic mode */ |
6194 | } | 7117 | } |
6195 | } else { | 7118 | } else { |
6196 | rc = FW_MSG_CODE_DRV_LOAD_COMMON; | 7119 | load_code = FW_MSG_CODE_DRV_LOAD_COMMON; |
6197 | } | 7120 | } |
6198 | 7121 | ||
6199 | DP(NETIF_MSG_IFUP, "set number of queues to %d\n", bp->num_queues); | ||
6200 | |||
6201 | /* if we can't use msix we only need one fp, | 7122 | /* if we can't use msix we only need one fp, |
6202 | * so try to enable msix with the requested number of fp's | 7123 | * so try to enable msix with the requested number of fp's |
6203 | * and fallback to inta with one fp | 7124 | * and fallback to inta with one fp |
6204 | */ | 7125 | */ |
6205 | if (req_irq) { | 7126 | if (req_irq) { |
6206 | |||
6207 | if (use_inta) { | 7127 | if (use_inta) { |
6208 | bp->num_queues = 1; | 7128 | bp->num_queues = 1; |
6209 | } else { | 7129 | } else { |
6210 | if (use_multi > 1 && use_multi <= 16) | 7130 | if ((use_multi > 1) && (use_multi <= 16)) |
6211 | /* user requested number */ | 7131 | /* user requested number */ |
6212 | bp->num_queues = use_multi; | 7132 | bp->num_queues = use_multi; |
6213 | else if (use_multi == 1) | 7133 | else if (use_multi == 1) |
@@ -6216,15 +7136,17 @@ static int bnx2x_nic_load(struct bnx2x *bp, int req_irq) | |||
6216 | bp->num_queues = 1; | 7136 | bp->num_queues = 1; |
6217 | 7137 | ||
6218 | if (bnx2x_enable_msix(bp)) { | 7138 | if (bnx2x_enable_msix(bp)) { |
6219 | /* faild to enable msix */ | 7139 | /* failed to enable msix */ |
6220 | bp->num_queues = 1; | 7140 | bp->num_queues = 1; |
6221 | if (use_multi) | 7141 | if (use_multi) |
6222 | BNX2X_ERR("Muti requested but failed" | 7142 | BNX2X_ERR("Multi requested but failed" |
6223 | " to enable MSI-X\n"); | 7143 | " to enable MSI-X\n"); |
6224 | } | 7144 | } |
6225 | } | 7145 | } |
6226 | } | 7146 | } |
6227 | 7147 | ||
7148 | DP(NETIF_MSG_IFUP, "set number of queues to %d\n", bp->num_queues); | ||
7149 | |||
6228 | if (bnx2x_alloc_mem(bp)) | 7150 | if (bnx2x_alloc_mem(bp)) |
6229 | return -ENOMEM; | 7151 | return -ENOMEM; |
6230 | 7152 | ||
@@ -6232,13 +7154,13 @@ static int bnx2x_nic_load(struct bnx2x *bp, int req_irq) | |||
6232 | if (bp->flags & USING_MSIX_FLAG) { | 7154 | if (bp->flags & USING_MSIX_FLAG) { |
6233 | if (bnx2x_req_msix_irqs(bp)) { | 7155 | if (bnx2x_req_msix_irqs(bp)) { |
6234 | pci_disable_msix(bp->pdev); | 7156 | pci_disable_msix(bp->pdev); |
6235 | goto out_error; | 7157 | goto load_error; |
6236 | } | 7158 | } |
6237 | 7159 | ||
6238 | } else { | 7160 | } else { |
6239 | if (bnx2x_req_irq(bp)) { | 7161 | if (bnx2x_req_irq(bp)) { |
6240 | BNX2X_ERR("IRQ request failed, aborting\n"); | 7162 | BNX2X_ERR("IRQ request failed, aborting\n"); |
6241 | goto out_error; | 7163 | goto load_error; |
6242 | } | 7164 | } |
6243 | } | 7165 | } |
6244 | } | 7166 | } |
@@ -6249,31 +7171,25 @@ static int bnx2x_nic_load(struct bnx2x *bp, int req_irq) | |||
6249 | 7171 | ||
6250 | 7172 | ||
6251 | /* Initialize HW */ | 7173 | /* Initialize HW */ |
6252 | if (bnx2x_function_init(bp, (rc == FW_MSG_CODE_DRV_LOAD_COMMON))) { | 7174 | if (bnx2x_function_init(bp, |
7175 | (load_code == FW_MSG_CODE_DRV_LOAD_COMMON))) { | ||
6253 | BNX2X_ERR("HW init failed, aborting\n"); | 7176 | BNX2X_ERR("HW init failed, aborting\n"); |
6254 | goto out_error; | 7177 | goto load_error; |
6255 | } | 7178 | } |
6256 | 7179 | ||
6257 | 7180 | ||
6258 | atomic_set(&bp->intr_sem, 0); | 7181 | atomic_set(&bp->intr_sem, 0); |
6259 | 7182 | ||
6260 | /* Reenable SP tasklet */ | ||
6261 | /*if (bp->sp_task_en) { */ | ||
6262 | /* tasklet_enable(&bp->sp_task);*/ | ||
6263 | /*} else { */ | ||
6264 | /* bp->sp_task_en = 1; */ | ||
6265 | /*} */ | ||
6266 | 7183 | ||
6267 | /* Setup NIC internals and enable interrupts */ | 7184 | /* Setup NIC internals and enable interrupts */ |
6268 | bnx2x_nic_init(bp); | 7185 | bnx2x_nic_init(bp); |
6269 | 7186 | ||
6270 | /* Send LOAD_DONE command to MCP */ | 7187 | /* Send LOAD_DONE command to MCP */ |
6271 | if (!nomcp) { | 7188 | if (!nomcp) { |
6272 | rc = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE); | 7189 | load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE); |
6273 | DP(NETIF_MSG_IFUP, "rc = 0x%x\n", rc); | 7190 | if (!load_code) { |
6274 | if (!rc) { | ||
6275 | BNX2X_ERR("MCP response failure, unloading\n"); | 7191 | BNX2X_ERR("MCP response failure, unloading\n"); |
6276 | goto int_disable; | 7192 | goto load_int_disable; |
6277 | } | 7193 | } |
6278 | } | 7194 | } |
6279 | 7195 | ||
@@ -6285,11 +7201,11 @@ static int bnx2x_nic_load(struct bnx2x *bp, int req_irq) | |||
6285 | napi_enable(&bnx2x_fp(bp, i, napi)); | 7201 | napi_enable(&bnx2x_fp(bp, i, napi)); |
6286 | 7202 | ||
6287 | if (bnx2x_setup_leading(bp)) | 7203 | if (bnx2x_setup_leading(bp)) |
6288 | goto stop_netif; | 7204 | goto load_stop_netif; |
6289 | 7205 | ||
6290 | for_each_nondefault_queue(bp, i) | 7206 | for_each_nondefault_queue(bp, i) |
6291 | if (bnx2x_setup_multi(bp, i)) | 7207 | if (bnx2x_setup_multi(bp, i)) |
6292 | goto stop_netif; | 7208 | goto load_stop_netif; |
6293 | 7209 | ||
6294 | bnx2x_set_mac_addr(bp); | 7210 | bnx2x_set_mac_addr(bp); |
6295 | 7211 | ||
@@ -6313,42 +7229,24 @@ static int bnx2x_nic_load(struct bnx2x *bp, int req_irq) | |||
6313 | 7229 | ||
6314 | return 0; | 7230 | return 0; |
6315 | 7231 | ||
6316 | stop_netif: | 7232 | load_stop_netif: |
6317 | for_each_queue(bp, i) | 7233 | for_each_queue(bp, i) |
6318 | napi_disable(&bnx2x_fp(bp, i, napi)); | 7234 | napi_disable(&bnx2x_fp(bp, i, napi)); |
6319 | 7235 | ||
6320 | int_disable: | 7236 | load_int_disable: |
6321 | bnx2x_disable_int_sync(bp); | 7237 | bnx2x_int_disable_sync(bp); |
6322 | 7238 | ||
6323 | bnx2x_free_skbs(bp); | 7239 | bnx2x_free_skbs(bp); |
6324 | bnx2x_free_irq(bp); | 7240 | bnx2x_free_irq(bp); |
6325 | 7241 | ||
6326 | out_error: | 7242 | load_error: |
6327 | bnx2x_free_mem(bp); | 7243 | bnx2x_free_mem(bp); |
6328 | 7244 | ||
6329 | /* TBD we really need to reset the chip | 7245 | /* TBD we really need to reset the chip |
6330 | if we want to recover from this */ | 7246 | if we want to recover from this */ |
6331 | return rc; | 7247 | return -EBUSY; |
6332 | } | 7248 | } |
6333 | 7249 | ||
6334 | static void bnx2x_netif_stop(struct bnx2x *bp) | ||
6335 | { | ||
6336 | int i; | ||
6337 | |||
6338 | bp->rx_mode = BNX2X_RX_MODE_NONE; | ||
6339 | bnx2x_set_storm_rx_mode(bp); | ||
6340 | |||
6341 | bnx2x_disable_int_sync(bp); | ||
6342 | bnx2x_link_reset(bp); | ||
6343 | |||
6344 | for_each_queue(bp, i) | ||
6345 | napi_disable(&bnx2x_fp(bp, i, napi)); | ||
6346 | |||
6347 | if (netif_running(bp->dev)) { | ||
6348 | netif_tx_disable(bp->dev); | ||
6349 | bp->dev->trans_start = jiffies; /* prevent tx timeout */ | ||
6350 | } | ||
6351 | } | ||
6352 | 7250 | ||
6353 | static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code) | 7251 | static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code) |
6354 | { | 7252 | { |
@@ -6401,20 +7299,20 @@ static int bnx2x_stop_multi(struct bnx2x *bp, int index) | |||
6401 | 7299 | ||
6402 | int rc; | 7300 | int rc; |
6403 | 7301 | ||
6404 | /* halt the connnection */ | 7302 | /* halt the connection */ |
6405 | bp->fp[index].state = BNX2X_FP_STATE_HALTING; | 7303 | bp->fp[index].state = BNX2X_FP_STATE_HALTING; |
6406 | bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, index, 0, 0, 0); | 7304 | bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, index, 0, 0, 0); |
6407 | 7305 | ||
6408 | 7306 | ||
6409 | rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, index, | 7307 | rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, index, |
6410 | &(bp->fp[index].state), 1); | 7308 | &(bp->fp[index].state), 1); |
6411 | if (rc) /* timout */ | 7309 | if (rc) /* timeout */ |
6412 | return rc; | 7310 | return rc; |
6413 | 7311 | ||
6414 | /* delete cfc entry */ | 7312 | /* delete cfc entry */ |
6415 | bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CFC_DEL, index, 0, 0, 1); | 7313 | bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CFC_DEL, index, 0, 0, 1); |
6416 | 7314 | ||
6417 | return bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_DELETED, index, | 7315 | return bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_CLOSED, index, |
6418 | &(bp->fp[index].state), 1); | 7316 | &(bp->fp[index].state), 1); |
6419 | 7317 | ||
6420 | } | 7318 | } |
@@ -6422,8 +7320,8 @@ static int bnx2x_stop_multi(struct bnx2x *bp, int index) | |||
6422 | 7320 | ||
6423 | static void bnx2x_stop_leading(struct bnx2x *bp) | 7321 | static void bnx2x_stop_leading(struct bnx2x *bp) |
6424 | { | 7322 | { |
6425 | 7323 | u16 dsb_sp_prod_idx; | |
6426 | /* if the other port is hadling traffic, | 7324 | /* if the other port is handling traffic, |
6427 | this can take a lot of time */ | 7325 | this can take a lot of time */ |
6428 | int timeout = 500; | 7326 | int timeout = 500; |
6429 | 7327 | ||
@@ -6437,52 +7335,71 @@ static void bnx2x_stop_leading(struct bnx2x *bp) | |||
6437 | &(bp->fp[0].state), 1)) | 7335 | &(bp->fp[0].state), 1)) |
6438 | return; | 7336 | return; |
6439 | 7337 | ||
6440 | bp->dsb_sp_prod_idx = *bp->dsb_sp_prod; | 7338 | dsb_sp_prod_idx = *bp->dsb_sp_prod; |
6441 | 7339 | ||
6442 | /* Send CFC_DELETE ramrod */ | 7340 | /* Send PORT_DELETE ramrod */ |
6443 | bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_PORT_DEL, 0, 0, 0, 1); | 7341 | bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_PORT_DEL, 0, 0, 0, 1); |
6444 | 7342 | ||
6445 | /* | 7343 | /* Wait for completion to arrive on default status block |
6446 | Wait for completion. | ||
6447 | we are going to reset the chip anyway | 7344 | we are going to reset the chip anyway |
6448 | so there is not much to do if this times out | 7345 | so there is not much to do if this times out |
6449 | */ | 7346 | */ |
6450 | while (bp->dsb_sp_prod_idx == *bp->dsb_sp_prod && timeout) { | 7347 | while ((dsb_sp_prod_idx == *bp->dsb_sp_prod) && timeout) { |
6451 | timeout--; | 7348 | timeout--; |
6452 | msleep(1); | 7349 | msleep(1); |
6453 | } | 7350 | } |
6454 | 7351 | if (!timeout) { | |
7352 | DP(NETIF_MSG_IFDOWN, "timeout polling for completion " | ||
7353 | "dsb_sp_prod 0x%x != dsb_sp_prod_idx 0x%x\n", | ||
7354 | *bp->dsb_sp_prod, dsb_sp_prod_idx); | ||
7355 | } | ||
7356 | bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD; | ||
7357 | bp->fp[0].state = BNX2X_FP_STATE_CLOSED; | ||
6455 | } | 7358 | } |
6456 | 7359 | ||
6457 | static int bnx2x_nic_unload(struct bnx2x *bp, int fre_irq) | 7360 | |
7361 | static int bnx2x_nic_unload(struct bnx2x *bp, int free_irq) | ||
6458 | { | 7362 | { |
6459 | u32 reset_code = 0; | 7363 | u32 reset_code = 0; |
6460 | int rc; | 7364 | int i, timeout; |
6461 | int i; | ||
6462 | 7365 | ||
6463 | bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT; | 7366 | bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT; |
6464 | 7367 | ||
6465 | /* Calling flush_scheduled_work() may deadlock because | 7368 | del_timer_sync(&bp->timer); |
6466 | * linkwatch_event() may be on the workqueue and it will try to get | ||
6467 | * the rtnl_lock which we are holding. | ||
6468 | */ | ||
6469 | 7369 | ||
6470 | while (bp->in_reset_task) | 7370 | bp->rx_mode = BNX2X_RX_MODE_NONE; |
6471 | msleep(1); | 7371 | bnx2x_set_storm_rx_mode(bp); |
6472 | 7372 | ||
6473 | /* Delete the timer: do it before disabling interrupts, as it | 7373 | if (netif_running(bp->dev)) { |
6474 | may be stil STAT_QUERY ramrod pending after stopping the timer */ | 7374 | netif_tx_disable(bp->dev); |
6475 | del_timer_sync(&bp->timer); | 7375 | bp->dev->trans_start = jiffies; /* prevent tx timeout */ |
7376 | } | ||
7377 | |||
7378 | /* Wait until all fast path tasks complete */ | ||
7379 | for_each_queue(bp, i) { | ||
7380 | struct bnx2x_fastpath *fp = &bp->fp[i]; | ||
7381 | |||
7382 | timeout = 1000; | ||
7383 | while (bnx2x_has_work(fp) && (timeout--)) | ||
7384 | msleep(1); | ||
7385 | if (!timeout) | ||
7386 | BNX2X_ERR("timeout waiting for queue[%d]\n", i); | ||
7387 | } | ||
6476 | 7388 | ||
6477 | /* Wait until stat ramrod returns and all SP tasks complete */ | 7389 | /* Wait until stat ramrod returns and all SP tasks complete */ |
6478 | while (bp->stat_pending && (bp->spq_left != MAX_SPQ_PENDING)) | 7390 | timeout = 1000; |
7391 | while ((bp->stat_pending || (bp->spq_left != MAX_SPQ_PENDING)) && | ||
7392 | (timeout--)) | ||
6479 | msleep(1); | 7393 | msleep(1); |
6480 | 7394 | ||
6481 | /* Stop fast path, disable MAC, disable interrupts, disable napi */ | 7395 | for_each_queue(bp, i) |
6482 | bnx2x_netif_stop(bp); | 7396 | napi_disable(&bnx2x_fp(bp, i, napi)); |
7397 | /* Disable interrupts after Tx and Rx are disabled on stack level */ | ||
7398 | bnx2x_int_disable_sync(bp); | ||
6483 | 7399 | ||
6484 | if (bp->flags & NO_WOL_FLAG) | 7400 | if (bp->flags & NO_WOL_FLAG) |
6485 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; | 7401 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; |
7402 | |||
6486 | else if (bp->wol) { | 7403 | else if (bp->wol) { |
6487 | u32 emac_base = bp->port ? GRCBASE_EMAC0 : GRCBASE_EMAC1; | 7404 | u32 emac_base = bp->port ? GRCBASE_EMAC0 : GRCBASE_EMAC1; |
6488 | u8 *mac_addr = bp->dev->dev_addr; | 7405 | u8 *mac_addr = bp->dev->dev_addr; |
@@ -6499,28 +7416,37 @@ static int bnx2x_nic_unload(struct bnx2x *bp, int fre_irq) | |||
6499 | EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + 4, val); | 7416 | EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + 4, val); |
6500 | 7417 | ||
6501 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; | 7418 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; |
7419 | |||
6502 | } else | 7420 | } else |
6503 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | 7421 | reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; |
6504 | 7422 | ||
7423 | /* Close multi and leading connections */ | ||
6505 | for_each_nondefault_queue(bp, i) | 7424 | for_each_nondefault_queue(bp, i) |
6506 | if (bnx2x_stop_multi(bp, i)) | 7425 | if (bnx2x_stop_multi(bp, i)) |
6507 | goto error; | 7426 | goto unload_error; |
6508 | |||
6509 | 7427 | ||
6510 | bnx2x_stop_leading(bp); | 7428 | bnx2x_stop_leading(bp); |
7429 | if ((bp->state != BNX2X_STATE_CLOSING_WAIT4_UNLOAD) || | ||
7430 | (bp->fp[0].state != BNX2X_FP_STATE_CLOSED)) { | ||
7431 | DP(NETIF_MSG_IFDOWN, "failed to close leading properly!" | ||
7432 | "state 0x%x fp[0].state 0x%x", | ||
7433 | bp->state, bp->fp[0].state); | ||
7434 | } | ||
7435 | |||
7436 | unload_error: | ||
7437 | bnx2x_link_reset(bp); | ||
6511 | 7438 | ||
6512 | error: | ||
6513 | if (!nomcp) | 7439 | if (!nomcp) |
6514 | rc = bnx2x_fw_command(bp, reset_code); | 7440 | reset_code = bnx2x_fw_command(bp, reset_code); |
6515 | else | 7441 | else |
6516 | rc = FW_MSG_CODE_DRV_UNLOAD_COMMON; | 7442 | reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON; |
6517 | 7443 | ||
6518 | /* Release IRQs */ | 7444 | /* Release IRQs */ |
6519 | if (fre_irq) | 7445 | if (free_irq) |
6520 | bnx2x_free_irq(bp); | 7446 | bnx2x_free_irq(bp); |
6521 | 7447 | ||
6522 | /* Reset the chip */ | 7448 | /* Reset the chip */ |
6523 | bnx2x_reset_chip(bp, rc); | 7449 | bnx2x_reset_chip(bp, reset_code); |
6524 | 7450 | ||
6525 | /* Report UNLOAD_DONE to MCP */ | 7451 | /* Report UNLOAD_DONE to MCP */ |
6526 | if (!nomcp) | 7452 | if (!nomcp) |
@@ -6531,8 +7457,7 @@ error: | |||
6531 | bnx2x_free_mem(bp); | 7457 | bnx2x_free_mem(bp); |
6532 | 7458 | ||
6533 | bp->state = BNX2X_STATE_CLOSED; | 7459 | bp->state = BNX2X_STATE_CLOSED; |
6534 | /* Set link down */ | 7460 | |
6535 | bp->link_up = 0; | ||
6536 | netif_carrier_off(bp->dev); | 7461 | netif_carrier_off(bp->dev); |
6537 | 7462 | ||
6538 | return 0; | 7463 | return 0; |
@@ -6568,7 +7493,7 @@ static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg) | |||
6568 | SUPPORTED_100baseT_Half | | 7493 | SUPPORTED_100baseT_Half | |
6569 | SUPPORTED_100baseT_Full | | 7494 | SUPPORTED_100baseT_Full | |
6570 | SUPPORTED_1000baseT_Full | | 7495 | SUPPORTED_1000baseT_Full | |
6571 | SUPPORTED_2500baseT_Full | | 7496 | SUPPORTED_2500baseX_Full | |
6572 | SUPPORTED_TP | SUPPORTED_FIBRE | | 7497 | SUPPORTED_TP | SUPPORTED_FIBRE | |
6573 | SUPPORTED_Autoneg | | 7498 | SUPPORTED_Autoneg | |
6574 | SUPPORTED_Pause | | 7499 | SUPPORTED_Pause | |
@@ -6581,10 +7506,10 @@ static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg) | |||
6581 | 7506 | ||
6582 | bp->phy_flags |= PHY_SGMII_FLAG; | 7507 | bp->phy_flags |= PHY_SGMII_FLAG; |
6583 | 7508 | ||
6584 | bp->supported |= (/* SUPPORTED_10baseT_Half | | 7509 | bp->supported |= (SUPPORTED_10baseT_Half | |
6585 | SUPPORTED_10baseT_Full | | 7510 | SUPPORTED_10baseT_Full | |
6586 | SUPPORTED_100baseT_Half | | 7511 | SUPPORTED_100baseT_Half | |
6587 | SUPPORTED_100baseT_Full |*/ | 7512 | SUPPORTED_100baseT_Full | |
6588 | SUPPORTED_1000baseT_Full | | 7513 | SUPPORTED_1000baseT_Full | |
6589 | SUPPORTED_TP | SUPPORTED_FIBRE | | 7514 | SUPPORTED_TP | SUPPORTED_FIBRE | |
6590 | SUPPORTED_Autoneg | | 7515 | SUPPORTED_Autoneg | |
@@ -6620,7 +7545,7 @@ static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg) | |||
6620 | SUPPORTED_100baseT_Half | | 7545 | SUPPORTED_100baseT_Half | |
6621 | SUPPORTED_100baseT_Full | | 7546 | SUPPORTED_100baseT_Full | |
6622 | SUPPORTED_1000baseT_Full | | 7547 | SUPPORTED_1000baseT_Full | |
6623 | SUPPORTED_2500baseT_Full | | 7548 | SUPPORTED_2500baseX_Full | |
6624 | SUPPORTED_10000baseT_Full | | 7549 | SUPPORTED_10000baseT_Full | |
6625 | SUPPORTED_TP | SUPPORTED_FIBRE | | 7550 | SUPPORTED_TP | SUPPORTED_FIBRE | |
6626 | SUPPORTED_Autoneg | | 7551 | SUPPORTED_Autoneg | |
@@ -6629,12 +7554,46 @@ static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg) | |||
6629 | break; | 7554 | break; |
6630 | 7555 | ||
6631 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: | 7556 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: |
7557 | BNX2X_DEV_INFO("ext_phy_type 0x%x (8705)\n", | ||
7558 | ext_phy_type); | ||
7559 | |||
7560 | bp->supported |= (SUPPORTED_10000baseT_Full | | ||
7561 | SUPPORTED_FIBRE | | ||
7562 | SUPPORTED_Pause | | ||
7563 | SUPPORTED_Asym_Pause); | ||
7564 | break; | ||
7565 | |||
6632 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: | 7566 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: |
6633 | BNX2X_DEV_INFO("ext_phy_type 0x%x (8705/6)\n", | 7567 | BNX2X_DEV_INFO("ext_phy_type 0x%x (8706)\n", |
7568 | ext_phy_type); | ||
7569 | |||
7570 | bp->supported |= (SUPPORTED_10000baseT_Full | | ||
7571 | SUPPORTED_1000baseT_Full | | ||
7572 | SUPPORTED_Autoneg | | ||
7573 | SUPPORTED_FIBRE | | ||
7574 | SUPPORTED_Pause | | ||
7575 | SUPPORTED_Asym_Pause); | ||
7576 | break; | ||
7577 | |||
7578 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: | ||
7579 | BNX2X_DEV_INFO("ext_phy_type 0x%x (8072)\n", | ||
6634 | ext_phy_type); | 7580 | ext_phy_type); |
6635 | 7581 | ||
6636 | bp->supported |= (SUPPORTED_10000baseT_Full | | 7582 | bp->supported |= (SUPPORTED_10000baseT_Full | |
7583 | SUPPORTED_1000baseT_Full | | ||
6637 | SUPPORTED_FIBRE | | 7584 | SUPPORTED_FIBRE | |
7585 | SUPPORTED_Autoneg | | ||
7586 | SUPPORTED_Pause | | ||
7587 | SUPPORTED_Asym_Pause); | ||
7588 | break; | ||
7589 | |||
7590 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: | ||
7591 | BNX2X_DEV_INFO("ext_phy_type 0x%x (SFX7101)\n", | ||
7592 | ext_phy_type); | ||
7593 | |||
7594 | bp->supported |= (SUPPORTED_10000baseT_Full | | ||
7595 | SUPPORTED_TP | | ||
7596 | SUPPORTED_Autoneg | | ||
6638 | SUPPORTED_Pause | | 7597 | SUPPORTED_Pause | |
6639 | SUPPORTED_Asym_Pause); | 7598 | SUPPORTED_Asym_Pause); |
6640 | break; | 7599 | break; |
@@ -6691,7 +7650,7 @@ static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg) | |||
6691 | SUPPORTED_1000baseT_Full); | 7650 | SUPPORTED_1000baseT_Full); |
6692 | 7651 | ||
6693 | if (!(bp->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) | 7652 | if (!(bp->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) |
6694 | bp->supported &= ~SUPPORTED_2500baseT_Full; | 7653 | bp->supported &= ~SUPPORTED_2500baseX_Full; |
6695 | 7654 | ||
6696 | if (!(bp->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) | 7655 | if (!(bp->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) |
6697 | bp->supported &= ~SUPPORTED_10000baseT_Full; | 7656 | bp->supported &= ~SUPPORTED_10000baseT_Full; |
@@ -6711,13 +7670,8 @@ static void bnx2x_link_settings_requested(struct bnx2x *bp) | |||
6711 | bp->req_line_speed = 0; | 7670 | bp->req_line_speed = 0; |
6712 | bp->advertising = bp->supported; | 7671 | bp->advertising = bp->supported; |
6713 | } else { | 7672 | } else { |
6714 | u32 ext_phy_type; | 7673 | if (XGXS_EXT_PHY_TYPE(bp) == |
6715 | 7674 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) { | |
6716 | ext_phy_type = XGXS_EXT_PHY_TYPE(bp); | ||
6717 | if ((ext_phy_type == | ||
6718 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) || | ||
6719 | (ext_phy_type == | ||
6720 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706)) { | ||
6721 | /* force 10G, no AN */ | 7675 | /* force 10G, no AN */ |
6722 | bp->req_line_speed = SPEED_10000; | 7676 | bp->req_line_speed = SPEED_10000; |
6723 | bp->advertising = | 7677 | bp->advertising = |
@@ -6734,8 +7688,7 @@ static void bnx2x_link_settings_requested(struct bnx2x *bp) | |||
6734 | break; | 7688 | break; |
6735 | 7689 | ||
6736 | case PORT_FEATURE_LINK_SPEED_10M_FULL: | 7690 | case PORT_FEATURE_LINK_SPEED_10M_FULL: |
6737 | if (bp->speed_cap_mask & | 7691 | if (bp->supported & SUPPORTED_10baseT_Full) { |
6738 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) { | ||
6739 | bp->req_line_speed = SPEED_10; | 7692 | bp->req_line_speed = SPEED_10; |
6740 | bp->advertising = (ADVERTISED_10baseT_Full | | 7693 | bp->advertising = (ADVERTISED_10baseT_Full | |
6741 | ADVERTISED_TP); | 7694 | ADVERTISED_TP); |
@@ -6749,8 +7702,7 @@ static void bnx2x_link_settings_requested(struct bnx2x *bp) | |||
6749 | break; | 7702 | break; |
6750 | 7703 | ||
6751 | case PORT_FEATURE_LINK_SPEED_10M_HALF: | 7704 | case PORT_FEATURE_LINK_SPEED_10M_HALF: |
6752 | if (bp->speed_cap_mask & | 7705 | if (bp->supported & SUPPORTED_10baseT_Half) { |
6753 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) { | ||
6754 | bp->req_line_speed = SPEED_10; | 7706 | bp->req_line_speed = SPEED_10; |
6755 | bp->req_duplex = DUPLEX_HALF; | 7707 | bp->req_duplex = DUPLEX_HALF; |
6756 | bp->advertising = (ADVERTISED_10baseT_Half | | 7708 | bp->advertising = (ADVERTISED_10baseT_Half | |
@@ -6765,8 +7717,7 @@ static void bnx2x_link_settings_requested(struct bnx2x *bp) | |||
6765 | break; | 7717 | break; |
6766 | 7718 | ||
6767 | case PORT_FEATURE_LINK_SPEED_100M_FULL: | 7719 | case PORT_FEATURE_LINK_SPEED_100M_FULL: |
6768 | if (bp->speed_cap_mask & | 7720 | if (bp->supported & SUPPORTED_100baseT_Full) { |
6769 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { | ||
6770 | bp->req_line_speed = SPEED_100; | 7721 | bp->req_line_speed = SPEED_100; |
6771 | bp->advertising = (ADVERTISED_100baseT_Full | | 7722 | bp->advertising = (ADVERTISED_100baseT_Full | |
6772 | ADVERTISED_TP); | 7723 | ADVERTISED_TP); |
@@ -6780,8 +7731,7 @@ static void bnx2x_link_settings_requested(struct bnx2x *bp) | |||
6780 | break; | 7731 | break; |
6781 | 7732 | ||
6782 | case PORT_FEATURE_LINK_SPEED_100M_HALF: | 7733 | case PORT_FEATURE_LINK_SPEED_100M_HALF: |
6783 | if (bp->speed_cap_mask & | 7734 | if (bp->supported & SUPPORTED_100baseT_Half) { |
6784 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { | ||
6785 | bp->req_line_speed = SPEED_100; | 7735 | bp->req_line_speed = SPEED_100; |
6786 | bp->req_duplex = DUPLEX_HALF; | 7736 | bp->req_duplex = DUPLEX_HALF; |
6787 | bp->advertising = (ADVERTISED_100baseT_Half | | 7737 | bp->advertising = (ADVERTISED_100baseT_Half | |
@@ -6796,8 +7746,7 @@ static void bnx2x_link_settings_requested(struct bnx2x *bp) | |||
6796 | break; | 7746 | break; |
6797 | 7747 | ||
6798 | case PORT_FEATURE_LINK_SPEED_1G: | 7748 | case PORT_FEATURE_LINK_SPEED_1G: |
6799 | if (bp->speed_cap_mask & | 7749 | if (bp->supported & SUPPORTED_1000baseT_Full) { |
6800 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) { | ||
6801 | bp->req_line_speed = SPEED_1000; | 7750 | bp->req_line_speed = SPEED_1000; |
6802 | bp->advertising = (ADVERTISED_1000baseT_Full | | 7751 | bp->advertising = (ADVERTISED_1000baseT_Full | |
6803 | ADVERTISED_TP); | 7752 | ADVERTISED_TP); |
@@ -6811,10 +7760,9 @@ static void bnx2x_link_settings_requested(struct bnx2x *bp) | |||
6811 | break; | 7760 | break; |
6812 | 7761 | ||
6813 | case PORT_FEATURE_LINK_SPEED_2_5G: | 7762 | case PORT_FEATURE_LINK_SPEED_2_5G: |
6814 | if (bp->speed_cap_mask & | 7763 | if (bp->supported & SUPPORTED_2500baseX_Full) { |
6815 | PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) { | ||
6816 | bp->req_line_speed = SPEED_2500; | 7764 | bp->req_line_speed = SPEED_2500; |
6817 | bp->advertising = (ADVERTISED_2500baseT_Full | | 7765 | bp->advertising = (ADVERTISED_2500baseX_Full | |
6818 | ADVERTISED_TP); | 7766 | ADVERTISED_TP); |
6819 | } else { | 7767 | } else { |
6820 | BNX2X_ERR("NVRAM config error. " | 7768 | BNX2X_ERR("NVRAM config error. " |
@@ -6828,15 +7776,7 @@ static void bnx2x_link_settings_requested(struct bnx2x *bp) | |||
6828 | case PORT_FEATURE_LINK_SPEED_10G_CX4: | 7776 | case PORT_FEATURE_LINK_SPEED_10G_CX4: |
6829 | case PORT_FEATURE_LINK_SPEED_10G_KX4: | 7777 | case PORT_FEATURE_LINK_SPEED_10G_KX4: |
6830 | case PORT_FEATURE_LINK_SPEED_10G_KR: | 7778 | case PORT_FEATURE_LINK_SPEED_10G_KR: |
6831 | if (!(bp->phy_flags & PHY_XGXS_FLAG)) { | 7779 | if (bp->supported & SUPPORTED_10000baseT_Full) { |
6832 | BNX2X_ERR("NVRAM config error. " | ||
6833 | "Invalid link_config 0x%x" | ||
6834 | " phy_flags 0x%x\n", | ||
6835 | bp->link_config, bp->phy_flags); | ||
6836 | return; | ||
6837 | } | ||
6838 | if (bp->speed_cap_mask & | ||
6839 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) { | ||
6840 | bp->req_line_speed = SPEED_10000; | 7780 | bp->req_line_speed = SPEED_10000; |
6841 | bp->advertising = (ADVERTISED_10000baseT_Full | | 7781 | bp->advertising = (ADVERTISED_10000baseT_Full | |
6842 | ADVERTISED_FIBRE); | 7782 | ADVERTISED_FIBRE); |
@@ -6863,43 +7803,13 @@ static void bnx2x_link_settings_requested(struct bnx2x *bp) | |||
6863 | 7803 | ||
6864 | bp->req_flow_ctrl = (bp->link_config & | 7804 | bp->req_flow_ctrl = (bp->link_config & |
6865 | PORT_FEATURE_FLOW_CONTROL_MASK); | 7805 | PORT_FEATURE_FLOW_CONTROL_MASK); |
6866 | /* Please refer to Table 28B-3 of the 802.3ab-1999 spec */ | 7806 | if ((bp->req_flow_ctrl == FLOW_CTRL_AUTO) && |
6867 | switch (bp->req_flow_ctrl) { | 7807 | (bp->supported & SUPPORTED_Autoneg)) |
6868 | case FLOW_CTRL_AUTO: | ||
6869 | bp->req_autoneg |= AUTONEG_FLOW_CTRL; | 7808 | bp->req_autoneg |= AUTONEG_FLOW_CTRL; |
6870 | if (bp->dev->mtu <= 4500) { | ||
6871 | bp->pause_mode = PAUSE_BOTH; | ||
6872 | bp->advertising |= (ADVERTISED_Pause | | ||
6873 | ADVERTISED_Asym_Pause); | ||
6874 | } else { | ||
6875 | bp->pause_mode = PAUSE_ASYMMETRIC; | ||
6876 | bp->advertising |= ADVERTISED_Asym_Pause; | ||
6877 | } | ||
6878 | break; | ||
6879 | |||
6880 | case FLOW_CTRL_TX: | ||
6881 | bp->pause_mode = PAUSE_ASYMMETRIC; | ||
6882 | bp->advertising |= ADVERTISED_Asym_Pause; | ||
6883 | break; | ||
6884 | |||
6885 | case FLOW_CTRL_RX: | ||
6886 | case FLOW_CTRL_BOTH: | ||
6887 | bp->pause_mode = PAUSE_BOTH; | ||
6888 | bp->advertising |= (ADVERTISED_Pause | | ||
6889 | ADVERTISED_Asym_Pause); | ||
6890 | break; | ||
6891 | 7809 | ||
6892 | case FLOW_CTRL_NONE: | 7810 | BNX2X_DEV_INFO("req_autoneg 0x%x req_flow_ctrl 0x%x" |
6893 | default: | 7811 | " advertising 0x%x\n", |
6894 | bp->pause_mode = PAUSE_NONE; | 7812 | bp->req_autoneg, bp->req_flow_ctrl, bp->advertising); |
6895 | bp->advertising &= ~(ADVERTISED_Pause | | ||
6896 | ADVERTISED_Asym_Pause); | ||
6897 | break; | ||
6898 | } | ||
6899 | BNX2X_DEV_INFO("req_autoneg 0x%x req_flow_ctrl 0x%x\n" | ||
6900 | KERN_INFO " pause_mode %d advertising 0x%x\n", | ||
6901 | bp->req_autoneg, bp->req_flow_ctrl, | ||
6902 | bp->pause_mode, bp->advertising); | ||
6903 | } | 7813 | } |
6904 | 7814 | ||
6905 | static void bnx2x_get_hwinfo(struct bnx2x *bp) | 7815 | static void bnx2x_get_hwinfo(struct bnx2x *bp) |
@@ -6933,15 +7843,15 @@ static void bnx2x_get_hwinfo(struct bnx2x *bp) | |||
6933 | val = SHMEM_RD(bp, validity_map[port]); | 7843 | val = SHMEM_RD(bp, validity_map[port]); |
6934 | if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) | 7844 | if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) |
6935 | != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) | 7845 | != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) |
6936 | BNX2X_ERR("MCP validity signature bad\n"); | 7846 | BNX2X_ERR("BAD MCP validity signature\n"); |
6937 | 7847 | ||
6938 | bp->fw_seq = (SHMEM_RD(bp, drv_fw_mb[port].drv_mb_header) & | 7848 | bp->fw_seq = (SHMEM_RD(bp, func_mb[port].drv_mb_header) & |
6939 | DRV_MSG_SEQ_NUMBER_MASK); | 7849 | DRV_MSG_SEQ_NUMBER_MASK); |
6940 | 7850 | ||
6941 | bp->hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); | 7851 | bp->hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); |
6942 | 7852 | bp->board = SHMEM_RD(bp, dev_info.shared_hw_config.board); | |
6943 | bp->serdes_config = | 7853 | bp->serdes_config = |
6944 | SHMEM_RD(bp, dev_info.port_hw_config[bp->port].serdes_config); | 7854 | SHMEM_RD(bp, dev_info.port_hw_config[port].serdes_config); |
6945 | bp->lane_config = | 7855 | bp->lane_config = |
6946 | SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); | 7856 | SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); |
6947 | bp->ext_phy_config = | 7857 | bp->ext_phy_config = |
@@ -6954,13 +7864,13 @@ static void bnx2x_get_hwinfo(struct bnx2x *bp) | |||
6954 | bp->link_config = | 7864 | bp->link_config = |
6955 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); | 7865 | SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); |
6956 | 7866 | ||
6957 | BNX2X_DEV_INFO("hw_config (%08x) serdes_config (%08x)\n" | 7867 | BNX2X_DEV_INFO("hw_config (%08x) board (%08x) serdes_config (%08x)\n" |
6958 | KERN_INFO " lane_config (%08x) ext_phy_config (%08x)\n" | 7868 | KERN_INFO " lane_config (%08x) ext_phy_config (%08x)\n" |
6959 | KERN_INFO " speed_cap_mask (%08x) link_config (%08x)" | 7869 | KERN_INFO " speed_cap_mask (%08x) link_config (%08x)" |
6960 | " fw_seq (%08x)\n", | 7870 | " fw_seq (%08x)\n", |
6961 | bp->hw_config, bp->serdes_config, bp->lane_config, | 7871 | bp->hw_config, bp->board, bp->serdes_config, |
6962 | bp->ext_phy_config, bp->speed_cap_mask, | 7872 | bp->lane_config, bp->ext_phy_config, |
6963 | bp->link_config, bp->fw_seq); | 7873 | bp->speed_cap_mask, bp->link_config, bp->fw_seq); |
6964 | 7874 | ||
6965 | switch_cfg = (bp->link_config & PORT_FEATURE_CONNECTED_SWITCH_MASK); | 7875 | switch_cfg = (bp->link_config & PORT_FEATURE_CONNECTED_SWITCH_MASK); |
6966 | bnx2x_link_settings_supported(bp, switch_cfg); | 7876 | bnx2x_link_settings_supported(bp, switch_cfg); |
@@ -7014,14 +7924,8 @@ static void bnx2x_get_hwinfo(struct bnx2x *bp) | |||
7014 | return; | 7924 | return; |
7015 | 7925 | ||
7016 | set_mac: /* only supposed to happen on emulation/FPGA */ | 7926 | set_mac: /* only supposed to happen on emulation/FPGA */ |
7017 | BNX2X_ERR("warning constant MAC workaround active\n"); | 7927 | BNX2X_ERR("warning rendom MAC workaround active\n"); |
7018 | bp->dev->dev_addr[0] = 0; | 7928 | random_ether_addr(bp->dev->dev_addr); |
7019 | bp->dev->dev_addr[1] = 0x50; | ||
7020 | bp->dev->dev_addr[2] = 0xc2; | ||
7021 | bp->dev->dev_addr[3] = 0x2c; | ||
7022 | bp->dev->dev_addr[4] = 0x71; | ||
7023 | bp->dev->dev_addr[5] = port ? 0x0d : 0x0e; | ||
7024 | |||
7025 | memcpy(bp->dev->perm_addr, bp->dev->dev_addr, 6); | 7929 | memcpy(bp->dev->perm_addr, bp->dev->dev_addr, 6); |
7026 | 7930 | ||
7027 | } | 7931 | } |
@@ -7048,19 +7952,34 @@ static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |||
7048 | } | 7952 | } |
7049 | 7953 | ||
7050 | if (bp->phy_flags & PHY_XGXS_FLAG) { | 7954 | if (bp->phy_flags & PHY_XGXS_FLAG) { |
7051 | cmd->port = PORT_FIBRE; | 7955 | u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp); |
7052 | } else { | 7956 | |
7957 | switch (ext_phy_type) { | ||
7958 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: | ||
7959 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: | ||
7960 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: | ||
7961 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: | ||
7962 | cmd->port = PORT_FIBRE; | ||
7963 | break; | ||
7964 | |||
7965 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: | ||
7966 | cmd->port = PORT_TP; | ||
7967 | break; | ||
7968 | |||
7969 | default: | ||
7970 | DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n", | ||
7971 | bp->ext_phy_config); | ||
7972 | } | ||
7973 | } else | ||
7053 | cmd->port = PORT_TP; | 7974 | cmd->port = PORT_TP; |
7054 | } | ||
7055 | 7975 | ||
7056 | cmd->phy_address = bp->phy_addr; | 7976 | cmd->phy_address = bp->phy_addr; |
7057 | cmd->transceiver = XCVR_INTERNAL; | 7977 | cmd->transceiver = XCVR_INTERNAL; |
7058 | 7978 | ||
7059 | if (bp->req_autoneg & AUTONEG_SPEED) { | 7979 | if (bp->req_autoneg & AUTONEG_SPEED) |
7060 | cmd->autoneg = AUTONEG_ENABLE; | 7980 | cmd->autoneg = AUTONEG_ENABLE; |
7061 | } else { | 7981 | else |
7062 | cmd->autoneg = AUTONEG_DISABLE; | 7982 | cmd->autoneg = AUTONEG_DISABLE; |
7063 | } | ||
7064 | 7983 | ||
7065 | cmd->maxtxpkt = 0; | 7984 | cmd->maxtxpkt = 0; |
7066 | cmd->maxrxpkt = 0; | 7985 | cmd->maxrxpkt = 0; |
@@ -7091,8 +8010,10 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |||
7091 | 8010 | ||
7092 | switch (cmd->port) { | 8011 | switch (cmd->port) { |
7093 | case PORT_TP: | 8012 | case PORT_TP: |
7094 | if (!(bp->supported & SUPPORTED_TP)) | 8013 | if (!(bp->supported & SUPPORTED_TP)) { |
8014 | DP(NETIF_MSG_LINK, "TP not supported\n"); | ||
7095 | return -EINVAL; | 8015 | return -EINVAL; |
8016 | } | ||
7096 | 8017 | ||
7097 | if (bp->phy_flags & PHY_XGXS_FLAG) { | 8018 | if (bp->phy_flags & PHY_XGXS_FLAG) { |
7098 | bnx2x_link_reset(bp); | 8019 | bnx2x_link_reset(bp); |
@@ -7102,8 +8023,10 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |||
7102 | break; | 8023 | break; |
7103 | 8024 | ||
7104 | case PORT_FIBRE: | 8025 | case PORT_FIBRE: |
7105 | if (!(bp->supported & SUPPORTED_FIBRE)) | 8026 | if (!(bp->supported & SUPPORTED_FIBRE)) { |
8027 | DP(NETIF_MSG_LINK, "FIBRE not supported\n"); | ||
7106 | return -EINVAL; | 8028 | return -EINVAL; |
8029 | } | ||
7107 | 8030 | ||
7108 | if (!(bp->phy_flags & PHY_XGXS_FLAG)) { | 8031 | if (!(bp->phy_flags & PHY_XGXS_FLAG)) { |
7109 | bnx2x_link_reset(bp); | 8032 | bnx2x_link_reset(bp); |
@@ -7113,12 +8036,15 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |||
7113 | break; | 8036 | break; |
7114 | 8037 | ||
7115 | default: | 8038 | default: |
8039 | DP(NETIF_MSG_LINK, "Unknown port type\n"); | ||
7116 | return -EINVAL; | 8040 | return -EINVAL; |
7117 | } | 8041 | } |
7118 | 8042 | ||
7119 | if (cmd->autoneg == AUTONEG_ENABLE) { | 8043 | if (cmd->autoneg == AUTONEG_ENABLE) { |
7120 | if (!(bp->supported & SUPPORTED_Autoneg)) | 8044 | if (!(bp->supported & SUPPORTED_Autoneg)) { |
8045 | DP(NETIF_MSG_LINK, "Aotoneg not supported\n"); | ||
7121 | return -EINVAL; | 8046 | return -EINVAL; |
8047 | } | ||
7122 | 8048 | ||
7123 | /* advertise the requested speed and duplex if supported */ | 8049 | /* advertise the requested speed and duplex if supported */ |
7124 | cmd->advertising &= bp->supported; | 8050 | cmd->advertising &= bp->supported; |
@@ -7133,14 +8059,22 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |||
7133 | switch (cmd->speed) { | 8059 | switch (cmd->speed) { |
7134 | case SPEED_10: | 8060 | case SPEED_10: |
7135 | if (cmd->duplex == DUPLEX_FULL) { | 8061 | if (cmd->duplex == DUPLEX_FULL) { |
7136 | if (!(bp->supported & SUPPORTED_10baseT_Full)) | 8062 | if (!(bp->supported & |
8063 | SUPPORTED_10baseT_Full)) { | ||
8064 | DP(NETIF_MSG_LINK, | ||
8065 | "10M full not supported\n"); | ||
7137 | return -EINVAL; | 8066 | return -EINVAL; |
8067 | } | ||
7138 | 8068 | ||
7139 | advertising = (ADVERTISED_10baseT_Full | | 8069 | advertising = (ADVERTISED_10baseT_Full | |
7140 | ADVERTISED_TP); | 8070 | ADVERTISED_TP); |
7141 | } else { | 8071 | } else { |
7142 | if (!(bp->supported & SUPPORTED_10baseT_Half)) | 8072 | if (!(bp->supported & |
8073 | SUPPORTED_10baseT_Half)) { | ||
8074 | DP(NETIF_MSG_LINK, | ||
8075 | "10M half not supported\n"); | ||
7143 | return -EINVAL; | 8076 | return -EINVAL; |
8077 | } | ||
7144 | 8078 | ||
7145 | advertising = (ADVERTISED_10baseT_Half | | 8079 | advertising = (ADVERTISED_10baseT_Half | |
7146 | ADVERTISED_TP); | 8080 | ADVERTISED_TP); |
@@ -7150,15 +8084,21 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |||
7150 | case SPEED_100: | 8084 | case SPEED_100: |
7151 | if (cmd->duplex == DUPLEX_FULL) { | 8085 | if (cmd->duplex == DUPLEX_FULL) { |
7152 | if (!(bp->supported & | 8086 | if (!(bp->supported & |
7153 | SUPPORTED_100baseT_Full)) | 8087 | SUPPORTED_100baseT_Full)) { |
8088 | DP(NETIF_MSG_LINK, | ||
8089 | "100M full not supported\n"); | ||
7154 | return -EINVAL; | 8090 | return -EINVAL; |
8091 | } | ||
7155 | 8092 | ||
7156 | advertising = (ADVERTISED_100baseT_Full | | 8093 | advertising = (ADVERTISED_100baseT_Full | |
7157 | ADVERTISED_TP); | 8094 | ADVERTISED_TP); |
7158 | } else { | 8095 | } else { |
7159 | if (!(bp->supported & | 8096 | if (!(bp->supported & |
7160 | SUPPORTED_100baseT_Half)) | 8097 | SUPPORTED_100baseT_Half)) { |
8098 | DP(NETIF_MSG_LINK, | ||
8099 | "100M half not supported\n"); | ||
7161 | return -EINVAL; | 8100 | return -EINVAL; |
8101 | } | ||
7162 | 8102 | ||
7163 | advertising = (ADVERTISED_100baseT_Half | | 8103 | advertising = (ADVERTISED_100baseT_Half | |
7164 | ADVERTISED_TP); | 8104 | ADVERTISED_TP); |
@@ -7166,39 +8106,54 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |||
7166 | break; | 8106 | break; |
7167 | 8107 | ||
7168 | case SPEED_1000: | 8108 | case SPEED_1000: |
7169 | if (cmd->duplex != DUPLEX_FULL) | 8109 | if (cmd->duplex != DUPLEX_FULL) { |
8110 | DP(NETIF_MSG_LINK, "1G half not supported\n"); | ||
7170 | return -EINVAL; | 8111 | return -EINVAL; |
8112 | } | ||
7171 | 8113 | ||
7172 | if (!(bp->supported & SUPPORTED_1000baseT_Full)) | 8114 | if (!(bp->supported & SUPPORTED_1000baseT_Full)) { |
8115 | DP(NETIF_MSG_LINK, "1G full not supported\n"); | ||
7173 | return -EINVAL; | 8116 | return -EINVAL; |
8117 | } | ||
7174 | 8118 | ||
7175 | advertising = (ADVERTISED_1000baseT_Full | | 8119 | advertising = (ADVERTISED_1000baseT_Full | |
7176 | ADVERTISED_TP); | 8120 | ADVERTISED_TP); |
7177 | break; | 8121 | break; |
7178 | 8122 | ||
7179 | case SPEED_2500: | 8123 | case SPEED_2500: |
7180 | if (cmd->duplex != DUPLEX_FULL) | 8124 | if (cmd->duplex != DUPLEX_FULL) { |
8125 | DP(NETIF_MSG_LINK, | ||
8126 | "2.5G half not supported\n"); | ||
7181 | return -EINVAL; | 8127 | return -EINVAL; |
8128 | } | ||
7182 | 8129 | ||
7183 | if (!(bp->supported & SUPPORTED_2500baseT_Full)) | 8130 | if (!(bp->supported & SUPPORTED_2500baseX_Full)) { |
8131 | DP(NETIF_MSG_LINK, | ||
8132 | "2.5G full not supported\n"); | ||
7184 | return -EINVAL; | 8133 | return -EINVAL; |
8134 | } | ||
7185 | 8135 | ||
7186 | advertising = (ADVERTISED_2500baseT_Full | | 8136 | advertising = (ADVERTISED_2500baseX_Full | |
7187 | ADVERTISED_TP); | 8137 | ADVERTISED_TP); |
7188 | break; | 8138 | break; |
7189 | 8139 | ||
7190 | case SPEED_10000: | 8140 | case SPEED_10000: |
7191 | if (cmd->duplex != DUPLEX_FULL) | 8141 | if (cmd->duplex != DUPLEX_FULL) { |
8142 | DP(NETIF_MSG_LINK, "10G half not supported\n"); | ||
7192 | return -EINVAL; | 8143 | return -EINVAL; |
8144 | } | ||
7193 | 8145 | ||
7194 | if (!(bp->supported & SUPPORTED_10000baseT_Full)) | 8146 | if (!(bp->supported & SUPPORTED_10000baseT_Full)) { |
8147 | DP(NETIF_MSG_LINK, "10G full not supported\n"); | ||
7195 | return -EINVAL; | 8148 | return -EINVAL; |
8149 | } | ||
7196 | 8150 | ||
7197 | advertising = (ADVERTISED_10000baseT_Full | | 8151 | advertising = (ADVERTISED_10000baseT_Full | |
7198 | ADVERTISED_FIBRE); | 8152 | ADVERTISED_FIBRE); |
7199 | break; | 8153 | break; |
7200 | 8154 | ||
7201 | default: | 8155 | default: |
8156 | DP(NETIF_MSG_LINK, "Unsupported speed\n"); | ||
7202 | return -EINVAL; | 8157 | return -EINVAL; |
7203 | } | 8158 | } |
7204 | 8159 | ||
@@ -7398,8 +8353,7 @@ static void bnx2x_disable_nvram_access(struct bnx2x *bp) | |||
7398 | static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, u32 *ret_val, | 8353 | static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, u32 *ret_val, |
7399 | u32 cmd_flags) | 8354 | u32 cmd_flags) |
7400 | { | 8355 | { |
7401 | int rc; | 8356 | int count, i, rc; |
7402 | int count, i; | ||
7403 | u32 val; | 8357 | u32 val; |
7404 | 8358 | ||
7405 | /* build the command word */ | 8359 | /* build the command word */ |
@@ -7452,13 +8406,13 @@ static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf, | |||
7452 | 8406 | ||
7453 | if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { | 8407 | if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { |
7454 | DP(NETIF_MSG_NVM, | 8408 | DP(NETIF_MSG_NVM, |
7455 | "Invalid paramter: offset 0x%x buf_size 0x%x\n", | 8409 | "Invalid parameter: offset 0x%x buf_size 0x%x\n", |
7456 | offset, buf_size); | 8410 | offset, buf_size); |
7457 | return -EINVAL; | 8411 | return -EINVAL; |
7458 | } | 8412 | } |
7459 | 8413 | ||
7460 | if (offset + buf_size > bp->flash_size) { | 8414 | if (offset + buf_size > bp->flash_size) { |
7461 | DP(NETIF_MSG_NVM, "Invalid paramter: offset (0x%x) +" | 8415 | DP(NETIF_MSG_NVM, "Invalid parameter: offset (0x%x) +" |
7462 | " buf_size (0x%x) > flash_size (0x%x)\n", | 8416 | " buf_size (0x%x) > flash_size (0x%x)\n", |
7463 | offset, buf_size, bp->flash_size); | 8417 | offset, buf_size, bp->flash_size); |
7464 | return -EINVAL; | 8418 | return -EINVAL; |
@@ -7519,8 +8473,7 @@ static int bnx2x_get_eeprom(struct net_device *dev, | |||
7519 | static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, | 8473 | static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, |
7520 | u32 cmd_flags) | 8474 | u32 cmd_flags) |
7521 | { | 8475 | { |
7522 | int rc; | 8476 | int count, i, rc; |
7523 | int count, i; | ||
7524 | 8477 | ||
7525 | /* build the command word */ | 8478 | /* build the command word */ |
7526 | cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR; | 8479 | cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR; |
@@ -7557,7 +8510,7 @@ static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val, | |||
7557 | return rc; | 8510 | return rc; |
7558 | } | 8511 | } |
7559 | 8512 | ||
7560 | #define BYTE_OFFSET(offset) (8 * (offset & 0x03)) | 8513 | #define BYTE_OFFSET(offset) (8 * (offset & 0x03)) |
7561 | 8514 | ||
7562 | static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, | 8515 | static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, |
7563 | int buf_size) | 8516 | int buf_size) |
@@ -7568,7 +8521,7 @@ static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf, | |||
7568 | u32 val; | 8521 | u32 val; |
7569 | 8522 | ||
7570 | if (offset + buf_size > bp->flash_size) { | 8523 | if (offset + buf_size > bp->flash_size) { |
7571 | DP(NETIF_MSG_NVM, "Invalid paramter: offset (0x%x) +" | 8524 | DP(NETIF_MSG_NVM, "Invalid parameter: offset (0x%x) +" |
7572 | " buf_size (0x%x) > flash_size (0x%x)\n", | 8525 | " buf_size (0x%x) > flash_size (0x%x)\n", |
7573 | offset, buf_size, bp->flash_size); | 8526 | offset, buf_size, bp->flash_size); |
7574 | return -EINVAL; | 8527 | return -EINVAL; |
@@ -7621,13 +8574,13 @@ static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf, | |||
7621 | 8574 | ||
7622 | if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { | 8575 | if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { |
7623 | DP(NETIF_MSG_NVM, | 8576 | DP(NETIF_MSG_NVM, |
7624 | "Invalid paramter: offset 0x%x buf_size 0x%x\n", | 8577 | "Invalid parameter: offset 0x%x buf_size 0x%x\n", |
7625 | offset, buf_size); | 8578 | offset, buf_size); |
7626 | return -EINVAL; | 8579 | return -EINVAL; |
7627 | } | 8580 | } |
7628 | 8581 | ||
7629 | if (offset + buf_size > bp->flash_size) { | 8582 | if (offset + buf_size > bp->flash_size) { |
7630 | DP(NETIF_MSG_NVM, "Invalid paramter: offset (0x%x) +" | 8583 | DP(NETIF_MSG_NVM, "Invalid parameter: offset (0x%x) +" |
7631 | " buf_size (0x%x) > flash_size (0x%x)\n", | 8584 | " buf_size (0x%x) > flash_size (0x%x)\n", |
7632 | offset, buf_size, bp->flash_size); | 8585 | offset, buf_size, bp->flash_size); |
7633 | return -EINVAL; | 8586 | return -EINVAL; |
@@ -7788,52 +8741,29 @@ static int bnx2x_set_pauseparam(struct net_device *dev, | |||
7788 | DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n", | 8741 | DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n", |
7789 | epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); | 8742 | epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); |
7790 | 8743 | ||
7791 | bp->req_flow_ctrl = FLOW_CTRL_AUTO; | ||
7792 | if (epause->autoneg) { | 8744 | if (epause->autoneg) { |
7793 | bp->req_autoneg |= AUTONEG_FLOW_CTRL; | 8745 | if (!(bp->supported & SUPPORTED_Autoneg)) { |
7794 | if (bp->dev->mtu <= 4500) { | 8746 | DP(NETIF_MSG_LINK, "Aotoneg not supported\n"); |
7795 | bp->pause_mode = PAUSE_BOTH; | 8747 | return -EINVAL; |
7796 | bp->advertising |= (ADVERTISED_Pause | | ||
7797 | ADVERTISED_Asym_Pause); | ||
7798 | } else { | ||
7799 | bp->pause_mode = PAUSE_ASYMMETRIC; | ||
7800 | bp->advertising |= ADVERTISED_Asym_Pause; | ||
7801 | } | 8748 | } |
7802 | 8749 | ||
7803 | } else { | 8750 | bp->req_autoneg |= AUTONEG_FLOW_CTRL; |
8751 | } else | ||
7804 | bp->req_autoneg &= ~AUTONEG_FLOW_CTRL; | 8752 | bp->req_autoneg &= ~AUTONEG_FLOW_CTRL; |
7805 | 8753 | ||
7806 | if (epause->rx_pause) | 8754 | bp->req_flow_ctrl = FLOW_CTRL_AUTO; |
7807 | bp->req_flow_ctrl |= FLOW_CTRL_RX; | ||
7808 | if (epause->tx_pause) | ||
7809 | bp->req_flow_ctrl |= FLOW_CTRL_TX; | ||
7810 | |||
7811 | switch (bp->req_flow_ctrl) { | ||
7812 | case FLOW_CTRL_AUTO: | ||
7813 | bp->req_flow_ctrl = FLOW_CTRL_NONE; | ||
7814 | bp->pause_mode = PAUSE_NONE; | ||
7815 | bp->advertising &= ~(ADVERTISED_Pause | | ||
7816 | ADVERTISED_Asym_Pause); | ||
7817 | break; | ||
7818 | 8755 | ||
7819 | case FLOW_CTRL_TX: | 8756 | if (epause->rx_pause) |
7820 | bp->pause_mode = PAUSE_ASYMMETRIC; | 8757 | bp->req_flow_ctrl |= FLOW_CTRL_RX; |
7821 | bp->advertising |= ADVERTISED_Asym_Pause; | 8758 | if (epause->tx_pause) |
7822 | break; | 8759 | bp->req_flow_ctrl |= FLOW_CTRL_TX; |
7823 | 8760 | ||
7824 | case FLOW_CTRL_RX: | 8761 | if (!(bp->req_autoneg & AUTONEG_FLOW_CTRL) && |
7825 | case FLOW_CTRL_BOTH: | 8762 | (bp->req_flow_ctrl == FLOW_CTRL_AUTO)) |
7826 | bp->pause_mode = PAUSE_BOTH; | 8763 | bp->req_flow_ctrl = FLOW_CTRL_NONE; |
7827 | bp->advertising |= (ADVERTISED_Pause | | ||
7828 | ADVERTISED_Asym_Pause); | ||
7829 | break; | ||
7830 | } | ||
7831 | } | ||
7832 | 8764 | ||
7833 | DP(NETIF_MSG_LINK, "req_autoneg 0x%x req_flow_ctrl 0x%x\n" | 8765 | DP(NETIF_MSG_LINK, "req_autoneg 0x%x req_flow_ctrl 0x%x\n", |
7834 | DP_LEVEL " pause_mode %d advertising 0x%x\n", | 8766 | bp->req_autoneg, bp->req_flow_ctrl); |
7835 | bp->req_autoneg, bp->req_flow_ctrl, bp->pause_mode, | ||
7836 | bp->advertising); | ||
7837 | 8767 | ||
7838 | bnx2x_stop_stats(bp); | 8768 | bnx2x_stop_stats(bp); |
7839 | bnx2x_link_initialize(bp); | 8769 | bnx2x_link_initialize(bp); |
@@ -7906,81 +8836,87 @@ static void bnx2x_self_test(struct net_device *dev, | |||
7906 | static struct { | 8836 | static struct { |
7907 | char string[ETH_GSTRING_LEN]; | 8837 | char string[ETH_GSTRING_LEN]; |
7908 | } bnx2x_stats_str_arr[BNX2X_NUM_STATS] = { | 8838 | } bnx2x_stats_str_arr[BNX2X_NUM_STATS] = { |
7909 | { "rx_bytes"}, /* 0 */ | 8839 | { "rx_bytes"}, |
7910 | { "rx_error_bytes"}, /* 1 */ | 8840 | { "rx_error_bytes"}, |
7911 | { "tx_bytes"}, /* 2 */ | 8841 | { "tx_bytes"}, |
7912 | { "tx_error_bytes"}, /* 3 */ | 8842 | { "tx_error_bytes"}, |
7913 | { "rx_ucast_packets"}, /* 4 */ | 8843 | { "rx_ucast_packets"}, |
7914 | { "rx_mcast_packets"}, /* 5 */ | 8844 | { "rx_mcast_packets"}, |
7915 | { "rx_bcast_packets"}, /* 6 */ | 8845 | { "rx_bcast_packets"}, |
7916 | { "tx_ucast_packets"}, /* 7 */ | 8846 | { "tx_ucast_packets"}, |
7917 | { "tx_mcast_packets"}, /* 8 */ | 8847 | { "tx_mcast_packets"}, |
7918 | { "tx_bcast_packets"}, /* 9 */ | 8848 | { "tx_bcast_packets"}, |
7919 | { "tx_mac_errors"}, /* 10 */ | 8849 | { "tx_mac_errors"}, /* 10 */ |
7920 | { "tx_carrier_errors"}, /* 11 */ | 8850 | { "tx_carrier_errors"}, |
7921 | { "rx_crc_errors"}, /* 12 */ | 8851 | { "rx_crc_errors"}, |
7922 | { "rx_align_errors"}, /* 13 */ | 8852 | { "rx_align_errors"}, |
7923 | { "tx_single_collisions"}, /* 14 */ | 8853 | { "tx_single_collisions"}, |
7924 | { "tx_multi_collisions"}, /* 15 */ | 8854 | { "tx_multi_collisions"}, |
7925 | { "tx_deferred"}, /* 16 */ | 8855 | { "tx_deferred"}, |
7926 | { "tx_excess_collisions"}, /* 17 */ | 8856 | { "tx_excess_collisions"}, |
7927 | { "tx_late_collisions"}, /* 18 */ | 8857 | { "tx_late_collisions"}, |
7928 | { "tx_total_collisions"}, /* 19 */ | 8858 | { "tx_total_collisions"}, |
7929 | { "rx_fragments"}, /* 20 */ | 8859 | { "rx_fragments"}, /* 20 */ |
7930 | { "rx_jabbers"}, /* 21 */ | 8860 | { "rx_jabbers"}, |
7931 | { "rx_undersize_packets"}, /* 22 */ | 8861 | { "rx_undersize_packets"}, |
7932 | { "rx_oversize_packets"}, /* 23 */ | 8862 | { "rx_oversize_packets"}, |
7933 | { "rx_xon_frames"}, /* 24 */ | 8863 | { "rx_xon_frames"}, |
7934 | { "rx_xoff_frames"}, /* 25 */ | 8864 | { "rx_xoff_frames"}, |
7935 | { "tx_xon_frames"}, /* 26 */ | 8865 | { "tx_xon_frames"}, |
7936 | { "tx_xoff_frames"}, /* 27 */ | 8866 | { "tx_xoff_frames"}, |
7937 | { "rx_mac_ctrl_frames"}, /* 28 */ | 8867 | { "rx_mac_ctrl_frames"}, |
7938 | { "rx_filtered_packets"}, /* 29 */ | 8868 | { "rx_filtered_packets"}, |
7939 | { "rx_discards"}, /* 30 */ | 8869 | { "rx_discards"}, /* 30 */ |
8870 | { "brb_discard"}, | ||
8871 | { "brb_truncate"}, | ||
8872 | { "xxoverflow"} | ||
7940 | }; | 8873 | }; |
7941 | 8874 | ||
7942 | #define STATS_OFFSET32(offset_name) \ | 8875 | #define STATS_OFFSET32(offset_name) \ |
7943 | (offsetof(struct bnx2x_eth_stats, offset_name) / 4) | 8876 | (offsetof(struct bnx2x_eth_stats, offset_name) / 4) |
7944 | 8877 | ||
7945 | static unsigned long bnx2x_stats_offset_arr[BNX2X_NUM_STATS] = { | 8878 | static unsigned long bnx2x_stats_offset_arr[BNX2X_NUM_STATS] = { |
7946 | STATS_OFFSET32(total_bytes_received_hi), /* 0 */ | 8879 | STATS_OFFSET32(total_bytes_received_hi), |
7947 | STATS_OFFSET32(stat_IfHCInBadOctets_hi), /* 1 */ | 8880 | STATS_OFFSET32(stat_IfHCInBadOctets_hi), |
7948 | STATS_OFFSET32(total_bytes_transmitted_hi), /* 2 */ | 8881 | STATS_OFFSET32(total_bytes_transmitted_hi), |
7949 | STATS_OFFSET32(stat_IfHCOutBadOctets_hi), /* 3 */ | 8882 | STATS_OFFSET32(stat_IfHCOutBadOctets_hi), |
7950 | STATS_OFFSET32(total_unicast_packets_received_hi), /* 4 */ | 8883 | STATS_OFFSET32(total_unicast_packets_received_hi), |
7951 | STATS_OFFSET32(total_multicast_packets_received_hi), /* 5 */ | 8884 | STATS_OFFSET32(total_multicast_packets_received_hi), |
7952 | STATS_OFFSET32(total_broadcast_packets_received_hi), /* 6 */ | 8885 | STATS_OFFSET32(total_broadcast_packets_received_hi), |
7953 | STATS_OFFSET32(total_unicast_packets_transmitted_hi), /* 7 */ | 8886 | STATS_OFFSET32(total_unicast_packets_transmitted_hi), |
7954 | STATS_OFFSET32(total_multicast_packets_transmitted_hi), /* 8 */ | 8887 | STATS_OFFSET32(total_multicast_packets_transmitted_hi), |
7955 | STATS_OFFSET32(total_broadcast_packets_transmitted_hi), /* 9 */ | 8888 | STATS_OFFSET32(total_broadcast_packets_transmitted_hi), |
7956 | STATS_OFFSET32(stat_Dot3statsInternalMacTransmitErrors), /* 10 */ | 8889 | STATS_OFFSET32(stat_Dot3statsInternalMacTransmitErrors), /* 10 */ |
7957 | STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors), /* 11 */ | 8890 | STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors), |
7958 | STATS_OFFSET32(crc_receive_errors), /* 12 */ | 8891 | STATS_OFFSET32(crc_receive_errors), |
7959 | STATS_OFFSET32(alignment_errors), /* 13 */ | 8892 | STATS_OFFSET32(alignment_errors), |
7960 | STATS_OFFSET32(single_collision_transmit_frames), /* 14 */ | 8893 | STATS_OFFSET32(single_collision_transmit_frames), |
7961 | STATS_OFFSET32(multiple_collision_transmit_frames), /* 15 */ | 8894 | STATS_OFFSET32(multiple_collision_transmit_frames), |
7962 | STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions), /* 16 */ | 8895 | STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions), |
7963 | STATS_OFFSET32(excessive_collision_frames), /* 17 */ | 8896 | STATS_OFFSET32(excessive_collision_frames), |
7964 | STATS_OFFSET32(late_collision_frames), /* 18 */ | 8897 | STATS_OFFSET32(late_collision_frames), |
7965 | STATS_OFFSET32(number_of_bugs_found_in_stats_spec), /* 19 */ | 8898 | STATS_OFFSET32(number_of_bugs_found_in_stats_spec), |
7966 | STATS_OFFSET32(runt_packets_received), /* 20 */ | 8899 | STATS_OFFSET32(runt_packets_received), /* 20 */ |
7967 | STATS_OFFSET32(jabber_packets_received), /* 21 */ | 8900 | STATS_OFFSET32(jabber_packets_received), |
7968 | STATS_OFFSET32(error_runt_packets_received), /* 22 */ | 8901 | STATS_OFFSET32(error_runt_packets_received), |
7969 | STATS_OFFSET32(error_jabber_packets_received), /* 23 */ | 8902 | STATS_OFFSET32(error_jabber_packets_received), |
7970 | STATS_OFFSET32(pause_xon_frames_received), /* 24 */ | 8903 | STATS_OFFSET32(pause_xon_frames_received), |
7971 | STATS_OFFSET32(pause_xoff_frames_received), /* 25 */ | 8904 | STATS_OFFSET32(pause_xoff_frames_received), |
7972 | STATS_OFFSET32(pause_xon_frames_transmitted), /* 26 */ | 8905 | STATS_OFFSET32(pause_xon_frames_transmitted), |
7973 | STATS_OFFSET32(pause_xoff_frames_transmitted), /* 27 */ | 8906 | STATS_OFFSET32(pause_xoff_frames_transmitted), |
7974 | STATS_OFFSET32(control_frames_received), /* 28 */ | 8907 | STATS_OFFSET32(control_frames_received), |
7975 | STATS_OFFSET32(mac_filter_discard), /* 29 */ | 8908 | STATS_OFFSET32(mac_filter_discard), |
7976 | STATS_OFFSET32(no_buff_discard), /* 30 */ | 8909 | STATS_OFFSET32(no_buff_discard), /* 30 */ |
8910 | STATS_OFFSET32(brb_discard), | ||
8911 | STATS_OFFSET32(brb_truncate_discard), | ||
8912 | STATS_OFFSET32(xxoverflow_discard) | ||
7977 | }; | 8913 | }; |
7978 | 8914 | ||
7979 | static u8 bnx2x_stats_len_arr[BNX2X_NUM_STATS] = { | 8915 | static u8 bnx2x_stats_len_arr[BNX2X_NUM_STATS] = { |
7980 | 8, 0, 8, 0, 8, 8, 8, 8, 8, 8, | 8916 | 8, 0, 8, 0, 8, 8, 8, 8, 8, 8, |
7981 | 4, 0, 4, 4, 4, 4, 4, 4, 4, 4, | 8917 | 4, 0, 4, 4, 4, 4, 4, 4, 4, 4, |
7982 | 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, | 8918 | 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, |
7983 | 4, | 8919 | 4, 4, 4, 4 |
7984 | }; | 8920 | }; |
7985 | 8921 | ||
7986 | static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) | 8922 | static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf) |
@@ -8138,9 +9074,7 @@ static int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state) | |||
8138 | * net_device service functions | 9074 | * net_device service functions |
8139 | */ | 9075 | */ |
8140 | 9076 | ||
8141 | /* Called with rtnl_lock from vlan functions and also netif_tx_lock | 9077 | /* called with netif_tx_lock from set_multicast */ |
8142 | * from set_multicast. | ||
8143 | */ | ||
8144 | static void bnx2x_set_rx_mode(struct net_device *dev) | 9078 | static void bnx2x_set_rx_mode(struct net_device *dev) |
8145 | { | 9079 | { |
8146 | struct bnx2x *bp = netdev_priv(dev); | 9080 | struct bnx2x *bp = netdev_priv(dev); |
@@ -8314,7 +9248,7 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) | |||
8314 | ETH_TX_BD_ETH_ADDR_TYPE_SHIFT); | 9248 | ETH_TX_BD_ETH_ADDR_TYPE_SHIFT); |
8315 | tx_bd->general_data |= 1; /* header nbd */ | 9249 | tx_bd->general_data |= 1; /* header nbd */ |
8316 | 9250 | ||
8317 | /* remeber the first bd of the packet */ | 9251 | /* remember the first bd of the packet */ |
8318 | tx_buf->first_bd = bd_prod; | 9252 | tx_buf->first_bd = bd_prod; |
8319 | 9253 | ||
8320 | DP(NETIF_MSG_TX_QUEUED, | 9254 | DP(NETIF_MSG_TX_QUEUED, |
@@ -8334,7 +9268,7 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) | |||
8334 | 9268 | ||
8335 | /* for now NS flag is not used in Linux */ | 9269 | /* for now NS flag is not used in Linux */ |
8336 | pbd->global_data = (len | | 9270 | pbd->global_data = (len | |
8337 | ((skb->protocol == ETH_P_8021Q) << | 9271 | ((skb->protocol == ntohs(ETH_P_8021Q)) << |
8338 | ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT)); | 9272 | ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT)); |
8339 | pbd->ip_hlen = ip_hdrlen(skb) / 2; | 9273 | pbd->ip_hlen = ip_hdrlen(skb) / 2; |
8340 | pbd->total_hlen = cpu_to_le16(len + pbd->ip_hlen); | 9274 | pbd->total_hlen = cpu_to_le16(len + pbd->ip_hlen); |
@@ -8343,7 +9277,7 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) | |||
8343 | 9277 | ||
8344 | tx_bd->bd_flags.as_bitfield |= | 9278 | tx_bd->bd_flags.as_bitfield |= |
8345 | ETH_TX_BD_FLAGS_TCP_CSUM; | 9279 | ETH_TX_BD_FLAGS_TCP_CSUM; |
8346 | pbd->tcp_flags = htonl(tcp_flag_word(skb)) & 0xFFFF; | 9280 | pbd->tcp_flags = pbd_tcp_flags(skb); |
8347 | pbd->total_hlen += cpu_to_le16(tcp_hdrlen(skb) / 2); | 9281 | pbd->total_hlen += cpu_to_le16(tcp_hdrlen(skb) / 2); |
8348 | pbd->tcp_pseudo_csum = swab16(th->check); | 9282 | pbd->tcp_pseudo_csum = swab16(th->check); |
8349 | 9283 | ||
@@ -8387,7 +9321,7 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) | |||
8387 | 9321 | ||
8388 | if (skb_shinfo(skb)->gso_size && | 9322 | if (skb_shinfo(skb)->gso_size && |
8389 | (skb->len > (bp->dev->mtu + ETH_HLEN))) { | 9323 | (skb->len > (bp->dev->mtu + ETH_HLEN))) { |
8390 | int hlen = 2 * le32_to_cpu(pbd->total_hlen); | 9324 | int hlen = 2 * le16_to_cpu(pbd->total_hlen); |
8391 | 9325 | ||
8392 | DP(NETIF_MSG_TX_QUEUED, | 9326 | DP(NETIF_MSG_TX_QUEUED, |
8393 | "TSO packet len %d hlen %d total len %d tso size %d\n", | 9327 | "TSO packet len %d hlen %d total len %d tso size %d\n", |
@@ -8427,7 +9361,7 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) | |||
8427 | tx_bd->vlan = cpu_to_le16(pkt_prod); | 9361 | tx_bd->vlan = cpu_to_le16(pkt_prod); |
8428 | /* this marks the bd | 9362 | /* this marks the bd |
8429 | * as one that has no individual mapping | 9363 | * as one that has no individual mapping |
8430 | * the FW ignors this flag in a bd not maked start | 9364 | * the FW ignores this flag in a bd not marked start |
8431 | */ | 9365 | */ |
8432 | tx_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_SW_LSO; | 9366 | tx_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_SW_LSO; |
8433 | DP(NETIF_MSG_TX_QUEUED, | 9367 | DP(NETIF_MSG_TX_QUEUED, |
@@ -8504,9 +9438,11 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) | |||
8504 | 9438 | ||
8505 | DP(NETIF_MSG_TX_QUEUED, "doorbell: nbd %u bd %d\n", nbd, bd_prod); | 9439 | DP(NETIF_MSG_TX_QUEUED, "doorbell: nbd %u bd %d\n", nbd, bd_prod); |
8506 | 9440 | ||
8507 | fp->hw_tx_prods->bds_prod += cpu_to_le16(nbd); | 9441 | fp->hw_tx_prods->bds_prod = |
9442 | cpu_to_le16(le16_to_cpu(fp->hw_tx_prods->bds_prod) + nbd); | ||
8508 | mb(); /* FW restriction: must not reorder writing nbd and packets */ | 9443 | mb(); /* FW restriction: must not reorder writing nbd and packets */ |
8509 | fp->hw_tx_prods->packets_prod += cpu_to_le32(1); | 9444 | fp->hw_tx_prods->packets_prod = |
9445 | cpu_to_le32(le32_to_cpu(fp->hw_tx_prods->packets_prod) + 1); | ||
8510 | DOORBELL(bp, fp_index, 0); | 9446 | DOORBELL(bp, fp_index, 0); |
8511 | 9447 | ||
8512 | mmiowb(); | 9448 | mmiowb(); |
@@ -8525,11 +9461,6 @@ static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) | |||
8525 | return NETDEV_TX_OK; | 9461 | return NETDEV_TX_OK; |
8526 | } | 9462 | } |
8527 | 9463 | ||
8528 | static struct net_device_stats *bnx2x_get_stats(struct net_device *dev) | ||
8529 | { | ||
8530 | return &dev->stats; | ||
8531 | } | ||
8532 | |||
8533 | /* Called with rtnl_lock */ | 9464 | /* Called with rtnl_lock */ |
8534 | static int bnx2x_open(struct net_device *dev) | 9465 | static int bnx2x_open(struct net_device *dev) |
8535 | { | 9466 | { |
@@ -8543,16 +9474,13 @@ static int bnx2x_open(struct net_device *dev) | |||
8543 | /* Called with rtnl_lock */ | 9474 | /* Called with rtnl_lock */ |
8544 | static int bnx2x_close(struct net_device *dev) | 9475 | static int bnx2x_close(struct net_device *dev) |
8545 | { | 9476 | { |
8546 | int rc; | ||
8547 | struct bnx2x *bp = netdev_priv(dev); | 9477 | struct bnx2x *bp = netdev_priv(dev); |
8548 | 9478 | ||
8549 | /* Unload the driver, release IRQs */ | 9479 | /* Unload the driver, release IRQs */ |
8550 | rc = bnx2x_nic_unload(bp, 1); | 9480 | bnx2x_nic_unload(bp, 1); |
8551 | if (rc) { | 9481 | |
8552 | BNX2X_ERR("bnx2x_nic_unload failed: %d\n", rc); | 9482 | if (!CHIP_REV_IS_SLOW(bp)) |
8553 | return rc; | 9483 | bnx2x_set_power_state(bp, PCI_D3hot); |
8554 | } | ||
8555 | bnx2x_set_power_state(bp, PCI_D3hot); | ||
8556 | 9484 | ||
8557 | return 0; | 9485 | return 0; |
8558 | } | 9486 | } |
@@ -8584,7 +9512,7 @@ static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |||
8584 | case SIOCGMIIPHY: | 9512 | case SIOCGMIIPHY: |
8585 | data->phy_id = bp->phy_addr; | 9513 | data->phy_id = bp->phy_addr; |
8586 | 9514 | ||
8587 | /* fallthru */ | 9515 | /* fallthrough */ |
8588 | case SIOCGMIIREG: { | 9516 | case SIOCGMIIREG: { |
8589 | u32 mii_regval; | 9517 | u32 mii_regval; |
8590 | 9518 | ||
@@ -8633,7 +9561,7 @@ static int bnx2x_change_mtu(struct net_device *dev, int new_mtu) | |||
8633 | return -EINVAL; | 9561 | return -EINVAL; |
8634 | 9562 | ||
8635 | /* This does not race with packet allocation | 9563 | /* This does not race with packet allocation |
8636 | * because the actuall alloc size is | 9564 | * because the actual alloc size is |
8637 | * only updated as part of load | 9565 | * only updated as part of load |
8638 | */ | 9566 | */ |
8639 | dev->mtu = new_mtu; | 9567 | dev->mtu = new_mtu; |
@@ -8666,7 +9594,7 @@ static void bnx2x_vlan_rx_register(struct net_device *dev, | |||
8666 | 9594 | ||
8667 | bp->vlgrp = vlgrp; | 9595 | bp->vlgrp = vlgrp; |
8668 | if (netif_running(dev)) | 9596 | if (netif_running(dev)) |
8669 | bnx2x_set_rx_mode(dev); | 9597 | bnx2x_set_client_config(bp); |
8670 | } | 9598 | } |
8671 | #endif | 9599 | #endif |
8672 | 9600 | ||
@@ -8695,14 +9623,18 @@ static void bnx2x_reset_task(struct work_struct *work) | |||
8695 | if (!netif_running(bp->dev)) | 9623 | if (!netif_running(bp->dev)) |
8696 | return; | 9624 | return; |
8697 | 9625 | ||
8698 | bp->in_reset_task = 1; | 9626 | rtnl_lock(); |
8699 | 9627 | ||
8700 | bnx2x_netif_stop(bp); | 9628 | if (bp->state != BNX2X_STATE_OPEN) { |
9629 | DP(NETIF_MSG_TX_ERR, "state is %x, returning\n", bp->state); | ||
9630 | goto reset_task_exit; | ||
9631 | } | ||
8701 | 9632 | ||
8702 | bnx2x_nic_unload(bp, 0); | 9633 | bnx2x_nic_unload(bp, 0); |
8703 | bnx2x_nic_load(bp, 0); | 9634 | bnx2x_nic_load(bp, 0); |
8704 | 9635 | ||
8705 | bp->in_reset_task = 0; | 9636 | reset_task_exit: |
9637 | rtnl_unlock(); | ||
8706 | } | 9638 | } |
8707 | 9639 | ||
8708 | static int __devinit bnx2x_init_board(struct pci_dev *pdev, | 9640 | static int __devinit bnx2x_init_board(struct pci_dev *pdev, |
@@ -8783,8 +9715,6 @@ static int __devinit bnx2x_init_board(struct pci_dev *pdev, | |||
8783 | 9715 | ||
8784 | spin_lock_init(&bp->phy_lock); | 9716 | spin_lock_init(&bp->phy_lock); |
8785 | 9717 | ||
8786 | bp->in_reset_task = 0; | ||
8787 | |||
8788 | INIT_WORK(&bp->reset_task, bnx2x_reset_task); | 9718 | INIT_WORK(&bp->reset_task, bnx2x_reset_task); |
8789 | INIT_WORK(&bp->sp_task, bnx2x_sp_task); | 9719 | INIT_WORK(&bp->sp_task, bnx2x_sp_task); |
8790 | 9720 | ||
@@ -8813,7 +9743,7 @@ static int __devinit bnx2x_init_board(struct pci_dev *pdev, | |||
8813 | bnx2x_get_hwinfo(bp); | 9743 | bnx2x_get_hwinfo(bp); |
8814 | 9744 | ||
8815 | if (CHIP_REV(bp) == CHIP_REV_FPGA) { | 9745 | if (CHIP_REV(bp) == CHIP_REV_FPGA) { |
8816 | printk(KERN_ERR PFX "FPGA detacted. MCP disabled," | 9746 | printk(KERN_ERR PFX "FPGA detected. MCP disabled," |
8817 | " will only init first device\n"); | 9747 | " will only init first device\n"); |
8818 | onefunc = 1; | 9748 | onefunc = 1; |
8819 | nomcp = 1; | 9749 | nomcp = 1; |
@@ -8882,14 +9812,32 @@ err_out: | |||
8882 | return rc; | 9812 | return rc; |
8883 | } | 9813 | } |
8884 | 9814 | ||
9815 | static int __devinit bnx2x_get_pcie_width(struct bnx2x *bp) | ||
9816 | { | ||
9817 | u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL); | ||
9818 | |||
9819 | val = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT; | ||
9820 | return val; | ||
9821 | } | ||
9822 | |||
9823 | /* return value of 1=2.5GHz 2=5GHz */ | ||
9824 | static int __devinit bnx2x_get_pcie_speed(struct bnx2x *bp) | ||
9825 | { | ||
9826 | u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL); | ||
9827 | |||
9828 | val = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT; | ||
9829 | return val; | ||
9830 | } | ||
9831 | |||
8885 | static int __devinit bnx2x_init_one(struct pci_dev *pdev, | 9832 | static int __devinit bnx2x_init_one(struct pci_dev *pdev, |
8886 | const struct pci_device_id *ent) | 9833 | const struct pci_device_id *ent) |
8887 | { | 9834 | { |
8888 | static int version_printed; | 9835 | static int version_printed; |
8889 | struct net_device *dev = NULL; | 9836 | struct net_device *dev = NULL; |
8890 | struct bnx2x *bp; | 9837 | struct bnx2x *bp; |
8891 | int rc, i; | 9838 | int rc; |
8892 | int port = PCI_FUNC(pdev->devfn); | 9839 | int port = PCI_FUNC(pdev->devfn); |
9840 | DECLARE_MAC_BUF(mac); | ||
8893 | 9841 | ||
8894 | if (version_printed++ == 0) | 9842 | if (version_printed++ == 0) |
8895 | printk(KERN_INFO "%s", version); | 9843 | printk(KERN_INFO "%s", version); |
@@ -8906,6 +9854,7 @@ static int __devinit bnx2x_init_one(struct pci_dev *pdev, | |||
8906 | 9854 | ||
8907 | if (port && onefunc) { | 9855 | if (port && onefunc) { |
8908 | printk(KERN_ERR PFX "second function disabled. exiting\n"); | 9856 | printk(KERN_ERR PFX "second function disabled. exiting\n"); |
9857 | free_netdev(dev); | ||
8909 | return 0; | 9858 | return 0; |
8910 | } | 9859 | } |
8911 | 9860 | ||
@@ -8918,7 +9867,6 @@ static int __devinit bnx2x_init_one(struct pci_dev *pdev, | |||
8918 | dev->hard_start_xmit = bnx2x_start_xmit; | 9867 | dev->hard_start_xmit = bnx2x_start_xmit; |
8919 | dev->watchdog_timeo = TX_TIMEOUT; | 9868 | dev->watchdog_timeo = TX_TIMEOUT; |
8920 | 9869 | ||
8921 | dev->get_stats = bnx2x_get_stats; | ||
8922 | dev->ethtool_ops = &bnx2x_ethtool_ops; | 9870 | dev->ethtool_ops = &bnx2x_ethtool_ops; |
8923 | dev->open = bnx2x_open; | 9871 | dev->open = bnx2x_open; |
8924 | dev->stop = bnx2x_close; | 9872 | dev->stop = bnx2x_close; |
@@ -8944,7 +9892,7 @@ static int __devinit bnx2x_init_one(struct pci_dev *pdev, | |||
8944 | 9892 | ||
8945 | rc = register_netdev(dev); | 9893 | rc = register_netdev(dev); |
8946 | if (rc) { | 9894 | if (rc) { |
8947 | printk(KERN_ERR PFX "Cannot register net device\n"); | 9895 | dev_err(&pdev->dev, "Cannot register net device\n"); |
8948 | if (bp->regview) | 9896 | if (bp->regview) |
8949 | iounmap(bp->regview); | 9897 | iounmap(bp->regview); |
8950 | if (bp->doorbells) | 9898 | if (bp->doorbells) |
@@ -8959,32 +9907,30 @@ static int __devinit bnx2x_init_one(struct pci_dev *pdev, | |||
8959 | pci_set_drvdata(pdev, dev); | 9907 | pci_set_drvdata(pdev, dev); |
8960 | 9908 | ||
8961 | bp->name = board_info[ent->driver_data].name; | 9909 | bp->name = board_info[ent->driver_data].name; |
8962 | printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz " | 9910 | printk(KERN_INFO "%s: %s (%c%d) PCI-E x%d %s found at mem %lx," |
8963 | "found at mem %lx, IRQ %d, ", | 9911 | " IRQ %d, ", dev->name, bp->name, |
8964 | dev->name, bp->name, | ||
8965 | ((CHIP_ID(bp) & 0xf000) >> 12) + 'A', | 9912 | ((CHIP_ID(bp) & 0xf000) >> 12) + 'A', |
8966 | ((CHIP_ID(bp) & 0x0ff0) >> 4), | 9913 | ((CHIP_ID(bp) & 0x0ff0) >> 4), |
8967 | ((bp->flags & PCIX_FLAG) ? "-X" : ""), | 9914 | bnx2x_get_pcie_width(bp), |
8968 | ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"), | 9915 | (bnx2x_get_pcie_speed(bp) == 2) ? "5GHz (Gen2)" : "2.5GHz", |
8969 | bp->bus_speed_mhz, | 9916 | dev->base_addr, bp->pdev->irq); |
8970 | dev->base_addr, | 9917 | printk(KERN_CONT "node addr %s\n", print_mac(mac, dev->dev_addr)); |
8971 | bp->pdev->irq); | ||
8972 | |||
8973 | printk("node addr "); | ||
8974 | for (i = 0; i < 6; i++) | ||
8975 | printk("%2.2x", dev->dev_addr[i]); | ||
8976 | printk("\n"); | ||
8977 | |||
8978 | return 0; | 9918 | return 0; |
8979 | } | 9919 | } |
8980 | 9920 | ||
8981 | static void __devexit bnx2x_remove_one(struct pci_dev *pdev) | 9921 | static void __devexit bnx2x_remove_one(struct pci_dev *pdev) |
8982 | { | 9922 | { |
8983 | struct net_device *dev = pci_get_drvdata(pdev); | 9923 | struct net_device *dev = pci_get_drvdata(pdev); |
8984 | struct bnx2x *bp = netdev_priv(dev); | 9924 | struct bnx2x *bp; |
9925 | |||
9926 | if (!dev) { | ||
9927 | /* we get here if init_one() fails */ | ||
9928 | printk(KERN_ERR PFX "BAD net device from bnx2x_init_one\n"); | ||
9929 | return; | ||
9930 | } | ||
9931 | |||
9932 | bp = netdev_priv(dev); | ||
8985 | 9933 | ||
8986 | flush_scheduled_work(); | ||
8987 | /*tasklet_kill(&bp->sp_task);*/ | ||
8988 | unregister_netdev(dev); | 9934 | unregister_netdev(dev); |
8989 | 9935 | ||
8990 | if (bp->regview) | 9936 | if (bp->regview) |
@@ -9002,34 +9948,43 @@ static void __devexit bnx2x_remove_one(struct pci_dev *pdev) | |||
9002 | static int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state) | 9948 | static int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state) |
9003 | { | 9949 | { |
9004 | struct net_device *dev = pci_get_drvdata(pdev); | 9950 | struct net_device *dev = pci_get_drvdata(pdev); |
9005 | struct bnx2x *bp = netdev_priv(dev); | 9951 | struct bnx2x *bp; |
9006 | int rc; | 9952 | |
9953 | if (!dev) | ||
9954 | return 0; | ||
9007 | 9955 | ||
9008 | if (!netif_running(dev)) | 9956 | if (!netif_running(dev)) |
9009 | return 0; | 9957 | return 0; |
9010 | 9958 | ||
9011 | rc = bnx2x_nic_unload(bp, 0); | 9959 | bp = netdev_priv(dev); |
9012 | if (!rc) | 9960 | |
9013 | return rc; | 9961 | bnx2x_nic_unload(bp, 0); |
9014 | 9962 | ||
9015 | netif_device_detach(dev); | 9963 | netif_device_detach(dev); |
9016 | pci_save_state(pdev); | ||
9017 | 9964 | ||
9965 | pci_save_state(pdev); | ||
9018 | bnx2x_set_power_state(bp, pci_choose_state(pdev, state)); | 9966 | bnx2x_set_power_state(bp, pci_choose_state(pdev, state)); |
9967 | |||
9019 | return 0; | 9968 | return 0; |
9020 | } | 9969 | } |
9021 | 9970 | ||
9022 | static int bnx2x_resume(struct pci_dev *pdev) | 9971 | static int bnx2x_resume(struct pci_dev *pdev) |
9023 | { | 9972 | { |
9024 | struct net_device *dev = pci_get_drvdata(pdev); | 9973 | struct net_device *dev = pci_get_drvdata(pdev); |
9025 | struct bnx2x *bp = netdev_priv(dev); | 9974 | struct bnx2x *bp; |
9026 | int rc; | 9975 | int rc; |
9027 | 9976 | ||
9977 | if (!dev) { | ||
9978 | printk(KERN_ERR PFX "BAD net device from bnx2x_init_one\n"); | ||
9979 | return -ENODEV; | ||
9980 | } | ||
9981 | |||
9028 | if (!netif_running(dev)) | 9982 | if (!netif_running(dev)) |
9029 | return 0; | 9983 | return 0; |
9030 | 9984 | ||
9031 | pci_restore_state(pdev); | 9985 | bp = netdev_priv(dev); |
9032 | 9986 | ||
9987 | pci_restore_state(pdev); | ||
9033 | bnx2x_set_power_state(bp, PCI_D0); | 9988 | bnx2x_set_power_state(bp, PCI_D0); |
9034 | netif_device_attach(dev); | 9989 | netif_device_attach(dev); |
9035 | 9990 | ||
diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h index 4f7ae6f77452..4f0c0d31e7c1 100644 --- a/drivers/net/bnx2x.h +++ b/drivers/net/bnx2x.h | |||
@@ -1,6 +1,6 @@ | |||
1 | /* bnx2x.h: Broadcom Everest network driver. | 1 | /* bnx2x.h: Broadcom Everest network driver. |
2 | * | 2 | * |
3 | * Copyright (c) 2007 Broadcom Corporation | 3 | * Copyright (c) 2007-2008 Broadcom Corporation |
4 | * | 4 | * |
5 | * This program is free software; you can redistribute it and/or modify | 5 | * This program is free software; you can redistribute it and/or modify |
6 | * it under the terms of the GNU General Public License as published by | 6 | * it under the terms of the GNU General Public License as published by |
@@ -24,6 +24,8 @@ | |||
24 | #define BNX2X_MSG_STATS 0x20000 /* was: NETIF_MSG_TIMER */ | 24 | #define BNX2X_MSG_STATS 0x20000 /* was: NETIF_MSG_TIMER */ |
25 | #define NETIF_MSG_NVM 0x40000 /* was: NETIF_MSG_HW */ | 25 | #define NETIF_MSG_NVM 0x40000 /* was: NETIF_MSG_HW */ |
26 | #define NETIF_MSG_DMAE 0x80000 /* was: NETIF_MSG_HW */ | 26 | #define NETIF_MSG_DMAE 0x80000 /* was: NETIF_MSG_HW */ |
27 | #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */ | ||
28 | #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */ | ||
27 | 29 | ||
28 | #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */ | 30 | #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */ |
29 | 31 | ||
@@ -40,6 +42,12 @@ | |||
40 | __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \ | 42 | __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \ |
41 | } while (0) | 43 | } while (0) |
42 | 44 | ||
45 | /* for logging (never masked) */ | ||
46 | #define BNX2X_LOG(__fmt, __args...) do { \ | ||
47 | printk(KERN_NOTICE "[%s:%d(%s)]" __fmt, __FUNCTION__, \ | ||
48 | __LINE__, bp->dev?(bp->dev->name):"?", ##__args); \ | ||
49 | } while (0) | ||
50 | |||
43 | /* before we have a dev->name use dev_info() */ | 51 | /* before we have a dev->name use dev_info() */ |
44 | #define BNX2X_DEV_INFO(__fmt, __args...) do { \ | 52 | #define BNX2X_DEV_INFO(__fmt, __args...) do { \ |
45 | if (bp->msglevel & NETIF_MSG_PROBE) \ | 53 | if (bp->msglevel & NETIF_MSG_PROBE) \ |
@@ -423,8 +431,6 @@ struct bnx2x_fastpath { | |||
423 | #define BNX2X_FP_STATE_OPEN 0xa0000 | 431 | #define BNX2X_FP_STATE_OPEN 0xa0000 |
424 | #define BNX2X_FP_STATE_HALTING 0xb0000 | 432 | #define BNX2X_FP_STATE_HALTING 0xb0000 |
425 | #define BNX2X_FP_STATE_HALTED 0xc0000 | 433 | #define BNX2X_FP_STATE_HALTED 0xc0000 |
426 | #define BNX2X_FP_STATE_DELETED 0xd0000 | ||
427 | #define BNX2X_FP_STATE_CLOSE_IRQ 0xe0000 | ||
428 | 434 | ||
429 | int index; | 435 | int index; |
430 | 436 | ||
@@ -505,7 +511,6 @@ struct bnx2x { | |||
505 | struct eth_spe *spq; | 511 | struct eth_spe *spq; |
506 | dma_addr_t spq_mapping; | 512 | dma_addr_t spq_mapping; |
507 | u16 spq_prod_idx; | 513 | u16 spq_prod_idx; |
508 | u16 dsb_sp_prod_idx; | ||
509 | struct eth_spe *spq_prod_bd; | 514 | struct eth_spe *spq_prod_bd; |
510 | struct eth_spe *spq_last_bd; | 515 | struct eth_spe *spq_last_bd; |
511 | u16 *dsb_sp_prod; | 516 | u16 *dsb_sp_prod; |
@@ -517,7 +522,7 @@ struct bnx2x { | |||
517 | */ | 522 | */ |
518 | u8 stat_pending; | 523 | u8 stat_pending; |
519 | 524 | ||
520 | /* End of fileds used in the performance code paths */ | 525 | /* End of fields used in the performance code paths */ |
521 | 526 | ||
522 | int panic; | 527 | int panic; |
523 | int msglevel; | 528 | int msglevel; |
@@ -540,8 +545,6 @@ struct bnx2x { | |||
540 | spinlock_t phy_lock; | 545 | spinlock_t phy_lock; |
541 | 546 | ||
542 | struct work_struct reset_task; | 547 | struct work_struct reset_task; |
543 | u16 in_reset_task; | ||
544 | |||
545 | struct work_struct sp_task; | 548 | struct work_struct sp_task; |
546 | 549 | ||
547 | struct timer_list timer; | 550 | struct timer_list timer; |
@@ -555,7 +558,6 @@ struct bnx2x { | |||
555 | #define CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0) | 558 | #define CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0) |
556 | 559 | ||
557 | #define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000) | 560 | #define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000) |
558 | #define CHIP_NUM_5710 0x57100000 | ||
559 | 561 | ||
560 | #define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000) | 562 | #define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000) |
561 | #define CHIP_REV_Ax 0x00000000 | 563 | #define CHIP_REV_Ax 0x00000000 |
@@ -574,7 +576,8 @@ struct bnx2x { | |||
574 | u32 fw_mb; | 576 | u32 fw_mb; |
575 | 577 | ||
576 | u32 hw_config; | 578 | u32 hw_config; |
577 | u32 serdes_config; | 579 | u32 board; |
580 | u32 serdes_config; | ||
578 | u32 lane_config; | 581 | u32 lane_config; |
579 | u32 ext_phy_config; | 582 | u32 ext_phy_config; |
580 | #define XGXS_EXT_PHY_TYPE(bp) (bp->ext_phy_config & \ | 583 | #define XGXS_EXT_PHY_TYPE(bp) (bp->ext_phy_config & \ |
@@ -595,11 +598,11 @@ struct bnx2x { | |||
595 | u8 tx_lane_swap; | 598 | u8 tx_lane_swap; |
596 | 599 | ||
597 | u8 link_up; | 600 | u8 link_up; |
601 | u8 phy_link_up; | ||
598 | 602 | ||
599 | u32 supported; | 603 | u32 supported; |
600 | /* link settings - missing defines */ | 604 | /* link settings - missing defines */ |
601 | #define SUPPORTED_2500baseT_Full (1 << 15) | 605 | #define SUPPORTED_2500baseT_Full (1 << 15) |
602 | #define SUPPORTED_CX4 (1 << 16) | ||
603 | 606 | ||
604 | u32 phy_flags; | 607 | u32 phy_flags; |
605 | /*#define PHY_SERDES_FLAG 0x1*/ | 608 | /*#define PHY_SERDES_FLAG 0x1*/ |
@@ -644,16 +647,9 @@ struct bnx2x { | |||
644 | #define FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH | 647 | #define FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH |
645 | #define FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE | 648 | #define FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE |
646 | 649 | ||
647 | u32 pause_mode; | ||
648 | #define PAUSE_NONE 0 | ||
649 | #define PAUSE_SYMMETRIC 1 | ||
650 | #define PAUSE_ASYMMETRIC 2 | ||
651 | #define PAUSE_BOTH 3 | ||
652 | |||
653 | u32 advertising; | 650 | u32 advertising; |
654 | /* link settings - missing defines */ | 651 | /* link settings - missing defines */ |
655 | #define ADVERTISED_2500baseT_Full (1 << 15) | 652 | #define ADVERTISED_2500baseT_Full (1 << 15) |
656 | #define ADVERTISED_CX4 (1 << 16) | ||
657 | 653 | ||
658 | u32 link_status; | 654 | u32 link_status; |
659 | u32 line_speed; | 655 | u32 line_speed; |
@@ -667,6 +663,8 @@ struct bnx2x { | |||
667 | #define NVRAM_TIMEOUT_COUNT 30000 | 663 | #define NVRAM_TIMEOUT_COUNT 30000 |
668 | #define NVRAM_PAGE_SIZE 256 | 664 | #define NVRAM_PAGE_SIZE 256 |
669 | 665 | ||
666 | u8 wol; | ||
667 | |||
670 | int rx_ring_size; | 668 | int rx_ring_size; |
671 | 669 | ||
672 | u16 tx_quick_cons_trip_int; | 670 | u16 tx_quick_cons_trip_int; |
@@ -718,9 +716,6 @@ struct bnx2x { | |||
718 | #endif | 716 | #endif |
719 | 717 | ||
720 | char *name; | 718 | char *name; |
721 | u16 bus_speed_mhz; | ||
722 | u8 wol; | ||
723 | u8 pad; | ||
724 | 719 | ||
725 | /* used to synchronize stats collecting */ | 720 | /* used to synchronize stats collecting */ |
726 | int stats_state; | 721 | int stats_state; |
@@ -856,8 +851,8 @@ struct bnx2x { | |||
856 | #define MAX_SPQ_PENDING 8 | 851 | #define MAX_SPQ_PENDING 8 |
857 | 852 | ||
858 | 853 | ||
859 | #define BNX2X_NUM_STATS 31 | 854 | #define BNX2X_NUM_STATS 34 |
860 | #define BNX2X_NUM_TESTS 2 | 855 | #define BNX2X_NUM_TESTS 1 |
861 | 856 | ||
862 | 857 | ||
863 | #define DPM_TRIGER_TYPE 0x40 | 858 | #define DPM_TRIGER_TYPE 0x40 |
@@ -867,6 +862,15 @@ struct bnx2x { | |||
867 | DPM_TRIGER_TYPE); \ | 862 | DPM_TRIGER_TYPE); \ |
868 | } while (0) | 863 | } while (0) |
869 | 864 | ||
865 | /* PCIE link and speed */ | ||
866 | #define PCICFG_LINK_WIDTH 0x1f00000 | ||
867 | #define PCICFG_LINK_WIDTH_SHIFT 20 | ||
868 | #define PCICFG_LINK_SPEED 0xf0000 | ||
869 | #define PCICFG_LINK_SPEED_SHIFT 16 | ||
870 | |||
871 | #define BMAC_CONTROL_RX_ENABLE 2 | ||
872 | |||
873 | #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) | ||
870 | 874 | ||
871 | /* stuff added to make the code fit 80Col */ | 875 | /* stuff added to make the code fit 80Col */ |
872 | 876 | ||
@@ -939,13 +943,13 @@ struct bnx2x { | |||
939 | #define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD | 943 | #define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD |
940 | #define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD | 944 | #define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD |
941 | 945 | ||
942 | #define NIG_STATUS_INTERRUPT_XGXS0_LINK10G \ | 946 | #define NIG_STATUS_XGXS0_LINK10G \ |
943 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G | 947 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G |
944 | #define NIG_XGXS0_LINK_STATUS \ | 948 | #define NIG_STATUS_XGXS0_LINK_STATUS \ |
945 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS | 949 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS |
946 | #define NIG_XGXS0_LINK_STATUS_SIZE \ | 950 | #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \ |
947 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE | 951 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE |
948 | #define NIG_SERDES0_LINK_STATUS \ | 952 | #define NIG_STATUS_SERDES0_LINK_STATUS \ |
949 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS | 953 | NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS |
950 | #define NIG_MASK_MI_INT \ | 954 | #define NIG_MASK_MI_INT \ |
951 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT | 955 | NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT |
diff --git a/drivers/net/bnx2x_fw_defs.h b/drivers/net/bnx2x_fw_defs.h index 62a6eb81025a..3b968904ca65 100644 --- a/drivers/net/bnx2x_fw_defs.h +++ b/drivers/net/bnx2x_fw_defs.h | |||
@@ -1,6 +1,6 @@ | |||
1 | /* bnx2x_fw_defs.h: Broadcom Everest network driver. | 1 | /* bnx2x_fw_defs.h: Broadcom Everest network driver. |
2 | * | 2 | * |
3 | * Copyright (c) 2007 Broadcom Corporation | 3 | * Copyright (c) 2007-2008 Broadcom Corporation |
4 | * | 4 | * |
5 | * This program is free software; you can redistribute it and/or modify | 5 | * This program is free software; you can redistribute it and/or modify |
6 | * it under the terms of the GNU General Public License as published by | 6 | * it under the terms of the GNU General Public License as published by |
diff --git a/drivers/net/bnx2x_hsi.h b/drivers/net/bnx2x_hsi.h index 6fd959c34d1f..b21075ccb52e 100644 --- a/drivers/net/bnx2x_hsi.h +++ b/drivers/net/bnx2x_hsi.h | |||
@@ -1,6 +1,6 @@ | |||
1 | /* bnx2x_hsi.h: Broadcom Everest network driver. | 1 | /* bnx2x_hsi.h: Broadcom Everest network driver. |
2 | * | 2 | * |
3 | * Copyright (c) 2007 Broadcom Corporation | 3 | * Copyright (c) 2007-2008 Broadcom Corporation |
4 | * | 4 | * |
5 | * This program is free software; you can redistribute it and/or modify | 5 | * This program is free software; you can redistribute it and/or modify |
6 | * it under the terms of the GNU General Public License as published by | 6 | * it under the terms of the GNU General Public License as published by |
@@ -8,169 +8,9 @@ | |||
8 | */ | 8 | */ |
9 | 9 | ||
10 | 10 | ||
11 | #define FUNC_0 0 | 11 | #define PORT_0 0 |
12 | #define FUNC_1 1 | 12 | #define PORT_1 1 |
13 | #define FUNC_MAX 2 | 13 | #define PORT_MAX 2 |
14 | |||
15 | |||
16 | /* This value (in milliseconds) determines the frequency of the driver | ||
17 | * issuing the PULSE message code. The firmware monitors this periodic | ||
18 | * pulse to determine when to switch to an OS-absent mode. */ | ||
19 | #define DRV_PULSE_PERIOD_MS 250 | ||
20 | |||
21 | /* This value (in milliseconds) determines how long the driver should | ||
22 | * wait for an acknowledgement from the firmware before timing out. Once | ||
23 | * the firmware has timed out, the driver will assume there is no firmware | ||
24 | * running and there won't be any firmware-driver synchronization during a | ||
25 | * driver reset. */ | ||
26 | #define FW_ACK_TIME_OUT_MS 5000 | ||
27 | |||
28 | #define FW_ACK_POLL_TIME_MS 1 | ||
29 | |||
30 | #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) | ||
31 | |||
32 | /* LED Blink rate that will achieve ~15.9Hz */ | ||
33 | #define LED_BLINK_RATE_VAL 480 | ||
34 | |||
35 | /**************************************************************************** | ||
36 | * Driver <-> FW Mailbox * | ||
37 | ****************************************************************************/ | ||
38 | struct drv_fw_mb { | ||
39 | u32 drv_mb_header; | ||
40 | #define DRV_MSG_CODE_MASK 0xffff0000 | ||
41 | #define DRV_MSG_CODE_LOAD_REQ 0x10000000 | ||
42 | #define DRV_MSG_CODE_LOAD_DONE 0x11000000 | ||
43 | #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 | ||
44 | #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 | ||
45 | #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 | ||
46 | #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 | ||
47 | #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 | ||
48 | #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 | ||
49 | #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 | ||
50 | #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000 | ||
51 | #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 | ||
52 | #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 | ||
53 | #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 | ||
54 | |||
55 | #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff | ||
56 | |||
57 | u32 drv_mb_param; | ||
58 | |||
59 | u32 fw_mb_header; | ||
60 | #define FW_MSG_CODE_MASK 0xffff0000 | ||
61 | #define FW_MSG_CODE_DRV_LOAD_COMMON 0x11000000 | ||
62 | #define FW_MSG_CODE_DRV_LOAD_PORT 0x12000000 | ||
63 | #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x13000000 | ||
64 | #define FW_MSG_CODE_DRV_LOAD_DONE 0x14000000 | ||
65 | #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x21000000 | ||
66 | #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x22000000 | ||
67 | #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x23000000 | ||
68 | #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50000000 | ||
69 | #define FW_MSG_CODE_DIAG_REFUSE 0x51000000 | ||
70 | #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70000000 | ||
71 | #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x71000000 | ||
72 | #define FW_MSG_CODE_GET_KEY_DONE 0x80000000 | ||
73 | #define FW_MSG_CODE_NO_KEY 0x8f000000 | ||
74 | #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x8f800000 | ||
75 | #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90000000 | ||
76 | #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x91000000 | ||
77 | #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x92000000 | ||
78 | #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x93000000 | ||
79 | #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x94000000 | ||
80 | |||
81 | #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff | ||
82 | |||
83 | u32 fw_mb_param; | ||
84 | |||
85 | u32 link_status; | ||
86 | /* Driver should update this field on any link change event */ | ||
87 | |||
88 | #define LINK_STATUS_LINK_FLAG_MASK 0x00000001 | ||
89 | #define LINK_STATUS_LINK_UP 0x00000001 | ||
90 | #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E | ||
91 | #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) | ||
92 | #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) | ||
93 | #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) | ||
94 | #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) | ||
95 | #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) | ||
96 | #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) | ||
97 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) | ||
98 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) | ||
99 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) | ||
100 | #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) | ||
101 | #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) | ||
102 | #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) | ||
103 | #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) | ||
104 | #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) | ||
105 | #define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD (11<<1) | ||
106 | #define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD (11<<1) | ||
107 | #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD (12<<1) | ||
108 | #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD (12<<1) | ||
109 | #define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD (13<<1) | ||
110 | #define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD (13<<1) | ||
111 | #define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD (14<<1) | ||
112 | #define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD (14<<1) | ||
113 | #define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD (15<<1) | ||
114 | #define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD (15<<1) | ||
115 | |||
116 | #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 | ||
117 | #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 | ||
118 | |||
119 | #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 | ||
120 | #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 | ||
121 | #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 | ||
122 | |||
123 | #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 | ||
124 | #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 | ||
125 | #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 | ||
126 | #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 | ||
127 | #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 | ||
128 | #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 | ||
129 | #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 | ||
130 | |||
131 | #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 | ||
132 | #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 | ||
133 | |||
134 | #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 | ||
135 | #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 | ||
136 | |||
137 | #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 | ||
138 | #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) | ||
139 | #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) | ||
140 | #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) | ||
141 | #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) | ||
142 | |||
143 | #define LINK_STATUS_SERDES_LINK 0x00100000 | ||
144 | |||
145 | #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 | ||
146 | #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 | ||
147 | #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 | ||
148 | #define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE 0x01000000 | ||
149 | #define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE 0x02000000 | ||
150 | #define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE 0x04000000 | ||
151 | #define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000 | ||
152 | #define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000 | ||
153 | |||
154 | u32 drv_pulse_mb; | ||
155 | #define DRV_PULSE_SEQ_MASK 0x00007fff | ||
156 | #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 | ||
157 | /* The system time is in the format of | ||
158 | * (year-2001)*12*32 + month*32 + day. */ | ||
159 | #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 | ||
160 | /* Indicate to the firmware not to go into the | ||
161 | * OS-absent when it is not getting driver pulse. | ||
162 | * This is used for debugging as well for PXE(MBA). */ | ||
163 | |||
164 | u32 mcp_pulse_mb; | ||
165 | #define MCP_PULSE_SEQ_MASK 0x00007fff | ||
166 | #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 | ||
167 | /* Indicates to the driver not to assert due to lack | ||
168 | * of MCP response */ | ||
169 | #define MCP_EVENT_MASK 0xffff0000 | ||
170 | #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 | ||
171 | |||
172 | }; | ||
173 | |||
174 | 14 | ||
175 | /**************************************************************************** | 15 | /**************************************************************************** |
176 | * Shared HW configuration * | 16 | * Shared HW configuration * |
@@ -249,7 +89,7 @@ struct shared_hw_cfg { /* NVRAM Offset */ | |||
249 | #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 | 89 | #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 |
250 | #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 | 90 | #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 |
251 | 91 | ||
252 | #define SHARED_HW_CFG_HIDE_FUNC1 0x00002000 | 92 | #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 |
253 | 93 | ||
254 | u32 power_dissipated; /* 0x11c */ | 94 | u32 power_dissipated; /* 0x11c */ |
255 | #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000 | 95 | #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000 |
@@ -290,6 +130,8 @@ struct shared_hw_cfg { /* NVRAM Offset */ | |||
290 | #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1015G 0x00000006 | 130 | #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1015G 0x00000006 |
291 | #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1020G 0x00000007 | 131 | #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1020G 0x00000007 |
292 | #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G 0x00000008 | 132 | #define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G 0x00000008 |
133 | #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G 0x00000009 | ||
134 | #define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G 0x0000000a | ||
293 | 135 | ||
294 | #define SHARED_HW_CFG_BOARD_VER_MASK 0xffff0000 | 136 | #define SHARED_HW_CFG_BOARD_VER_MASK 0xffff0000 |
295 | #define SHARED_HW_CFG_BOARD_VER_SHIFT 16 | 137 | #define SHARED_HW_CFG_BOARD_VER_SHIFT 16 |
@@ -304,13 +146,12 @@ struct shared_hw_cfg { /* NVRAM Offset */ | |||
304 | 146 | ||
305 | }; | 147 | }; |
306 | 148 | ||
149 | |||
307 | /**************************************************************************** | 150 | /**************************************************************************** |
308 | * Port HW configuration * | 151 | * Port HW configuration * |
309 | ****************************************************************************/ | 152 | ****************************************************************************/ |
310 | struct port_hw_cfg { /* function 0: 0x12c-0x2bb, function 1: 0x2bc-0x44b */ | 153 | struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ |
311 | 154 | ||
312 | /* Fields below are port specific (in anticipation of dual port | ||
313 | devices */ | ||
314 | u32 pci_id; | 155 | u32 pci_id; |
315 | #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000 | 156 | #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000 |
316 | #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff | 157 | #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff |
@@ -420,6 +261,8 @@ struct port_hw_cfg { /* function 0: 0x12c-0x2bb, function 1: 0x2bc-0x44b */ | |||
420 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 | 261 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 |
421 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8276 0x00000600 | 262 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8276 0x00000600 |
422 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 | 263 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 |
264 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 | ||
265 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 | ||
423 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 | 266 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 |
424 | 267 | ||
425 | #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff | 268 | #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff |
@@ -462,11 +305,13 @@ struct port_hw_cfg { /* function 0: 0x12c-0x2bb, function 1: 0x2bc-0x44b */ | |||
462 | 305 | ||
463 | }; | 306 | }; |
464 | 307 | ||
308 | |||
465 | /**************************************************************************** | 309 | /**************************************************************************** |
466 | * Shared Feature configuration * | 310 | * Shared Feature configuration * |
467 | ****************************************************************************/ | 311 | ****************************************************************************/ |
468 | struct shared_feat_cfg { /* NVRAM Offset */ | 312 | struct shared_feat_cfg { /* NVRAM Offset */ |
469 | u32 bmc_common; /* 0x450 */ | 313 | |
314 | u32 config; /* 0x450 */ | ||
470 | #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 | 315 | #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 |
471 | 316 | ||
472 | }; | 317 | }; |
@@ -475,7 +320,8 @@ struct shared_feat_cfg { /* NVRAM Offset */ | |||
475 | /**************************************************************************** | 320 | /**************************************************************************** |
476 | * Port Feature configuration * | 321 | * Port Feature configuration * |
477 | ****************************************************************************/ | 322 | ****************************************************************************/ |
478 | struct port_feat_cfg { /* function 0: 0x454-0x4c7, function 1: 0x4c8-0x53b */ | 323 | struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ |
324 | |||
479 | u32 config; | 325 | u32 config; |
480 | #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f | 326 | #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f |
481 | #define PORT_FEATURE_BAR1_SIZE_SHIFT 0 | 327 | #define PORT_FEATURE_BAR1_SIZE_SHIFT 0 |
@@ -609,8 +455,7 @@ struct port_feat_cfg { /* function 0: 0x454-0x4c7, function 1: 0x4c8-0x53b */ | |||
609 | #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe | 455 | #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe |
610 | #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 | 456 | #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 |
611 | 457 | ||
612 | u32 iscsib_boot_cfg; | 458 | u32 reserved1; |
613 | #define PORT_FEATURE_ISCSIB_SKIP_TARGET_BOOT 0x00000001 | ||
614 | 459 | ||
615 | u32 link_config; /* Used as HW defaults for the driver */ | 460 | u32 link_config; /* Used as HW defaults for the driver */ |
616 | #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 | 461 | #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 |
@@ -657,20 +502,201 @@ struct port_feat_cfg { /* function 0: 0x454-0x4c7, function 1: 0x4c8-0x53b */ | |||
657 | }; | 502 | }; |
658 | 503 | ||
659 | 504 | ||
505 | /***************************************************************************** | ||
506 | * Device Information * | ||
507 | *****************************************************************************/ | ||
508 | struct dev_info { /* size */ | ||
509 | |||
510 | u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ | ||
511 | |||
512 | struct shared_hw_cfg shared_hw_config; /* 40 */ | ||
513 | |||
514 | struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ | ||
515 | |||
516 | struct shared_feat_cfg shared_feature_config; /* 4 */ | ||
517 | |||
518 | struct port_feat_cfg port_feature_config[PORT_MAX]; /* 116*2=232 */ | ||
519 | |||
520 | }; | ||
521 | |||
522 | |||
523 | #define FUNC_0 0 | ||
524 | #define FUNC_1 1 | ||
525 | #define E1_FUNC_MAX 2 | ||
526 | #define FUNC_MAX E1_FUNC_MAX | ||
527 | |||
528 | |||
529 | /* This value (in milliseconds) determines the frequency of the driver | ||
530 | * issuing the PULSE message code. The firmware monitors this periodic | ||
531 | * pulse to determine when to switch to an OS-absent mode. */ | ||
532 | #define DRV_PULSE_PERIOD_MS 250 | ||
533 | |||
534 | /* This value (in milliseconds) determines how long the driver should | ||
535 | * wait for an acknowledgement from the firmware before timing out. Once | ||
536 | * the firmware has timed out, the driver will assume there is no firmware | ||
537 | * running and there won't be any firmware-driver synchronization during a | ||
538 | * driver reset. */ | ||
539 | #define FW_ACK_TIME_OUT_MS 5000 | ||
540 | |||
541 | #define FW_ACK_POLL_TIME_MS 1 | ||
542 | |||
543 | #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) | ||
544 | |||
545 | /* LED Blink rate that will achieve ~15.9Hz */ | ||
546 | #define LED_BLINK_RATE_VAL 480 | ||
547 | |||
660 | /**************************************************************************** | 548 | /**************************************************************************** |
661 | * Device Information * | 549 | * Driver <-> FW Mailbox * |
662 | ****************************************************************************/ | 550 | ****************************************************************************/ |
663 | struct dev_info { /* size */ | 551 | struct drv_port_mb { |
552 | |||
553 | u32 link_status; | ||
554 | /* Driver should update this field on any link change event */ | ||
555 | |||
556 | #define LINK_STATUS_LINK_FLAG_MASK 0x00000001 | ||
557 | #define LINK_STATUS_LINK_UP 0x00000001 | ||
558 | #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E | ||
559 | #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) | ||
560 | #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) | ||
561 | #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) | ||
562 | #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) | ||
563 | #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) | ||
564 | #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) | ||
565 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) | ||
566 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) | ||
567 | #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) | ||
568 | #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) | ||
569 | #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) | ||
570 | #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) | ||
571 | #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) | ||
572 | #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) | ||
573 | #define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD (11<<1) | ||
574 | #define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD (11<<1) | ||
575 | #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD (12<<1) | ||
576 | #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD (12<<1) | ||
577 | #define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD (13<<1) | ||
578 | #define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD (13<<1) | ||
579 | #define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD (14<<1) | ||
580 | #define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD (14<<1) | ||
581 | #define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD (15<<1) | ||
582 | #define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD (15<<1) | ||
583 | |||
584 | #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 | ||
585 | #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 | ||
586 | |||
587 | #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 | ||
588 | #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 | ||
589 | #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 | ||
590 | |||
591 | #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 | ||
592 | #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 | ||
593 | #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 | ||
594 | #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 | ||
595 | #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 | ||
596 | #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 | ||
597 | #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 | ||
598 | |||
599 | #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 | ||
600 | #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 | ||
601 | |||
602 | #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 | ||
603 | #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 | ||
604 | |||
605 | #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 | ||
606 | #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) | ||
607 | #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) | ||
608 | #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) | ||
609 | #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) | ||
610 | |||
611 | #define LINK_STATUS_SERDES_LINK 0x00100000 | ||
612 | |||
613 | #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 | ||
614 | #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 | ||
615 | #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 | ||
616 | #define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE 0x01000000 | ||
617 | #define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE 0x02000000 | ||
618 | #define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE 0x04000000 | ||
619 | #define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000 | ||
620 | #define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000 | ||
664 | 621 | ||
665 | u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ | 622 | u32 reserved[3]; |
666 | 623 | ||
667 | struct shared_hw_cfg shared_hw_config; /* 40 */ | 624 | }; |
625 | |||
626 | |||
627 | struct drv_func_mb { | ||
628 | |||
629 | u32 drv_mb_header; | ||
630 | #define DRV_MSG_CODE_MASK 0xffff0000 | ||
631 | #define DRV_MSG_CODE_LOAD_REQ 0x10000000 | ||
632 | #define DRV_MSG_CODE_LOAD_DONE 0x11000000 | ||
633 | #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 | ||
634 | #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 | ||
635 | #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 | ||
636 | #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 | ||
637 | #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 | ||
638 | #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 | ||
639 | #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 | ||
640 | #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000 | ||
641 | #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 | ||
642 | #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 | ||
643 | #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 | ||
644 | |||
645 | #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff | ||
646 | |||
647 | u32 drv_mb_param; | ||
648 | |||
649 | u32 fw_mb_header; | ||
650 | #define FW_MSG_CODE_MASK 0xffff0000 | ||
651 | #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000 | ||
652 | #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 | ||
653 | #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 | ||
654 | #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000 | ||
655 | #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 | ||
656 | #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000 | ||
657 | #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 | ||
658 | #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 | ||
659 | #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 | ||
660 | #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 | ||
661 | #define FW_MSG_CODE_DIAG_REFUSE 0x50200000 | ||
662 | #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 | ||
663 | #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000 | ||
664 | #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000 | ||
665 | #define FW_MSG_CODE_GET_KEY_DONE 0x80100000 | ||
666 | #define FW_MSG_CODE_NO_KEY 0x80f00000 | ||
667 | #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000 | ||
668 | #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000 | ||
669 | #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000 | ||
670 | #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 | ||
671 | #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 | ||
672 | #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 | ||
673 | |||
674 | #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff | ||
675 | |||
676 | u32 fw_mb_param; | ||
677 | |||
678 | u32 drv_pulse_mb; | ||
679 | #define DRV_PULSE_SEQ_MASK 0x00007fff | ||
680 | #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 | ||
681 | /* The system time is in the format of | ||
682 | * (year-2001)*12*32 + month*32 + day. */ | ||
683 | #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 | ||
684 | /* Indicate to the firmware not to go into the | ||
685 | * OS-absent when it is not getting driver pulse. | ||
686 | * This is used for debugging as well for PXE(MBA). */ | ||
668 | 687 | ||
669 | struct port_hw_cfg port_hw_config[FUNC_MAX]; /* 400*2=800 */ | 688 | u32 mcp_pulse_mb; |
689 | #define MCP_PULSE_SEQ_MASK 0x00007fff | ||
690 | #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 | ||
691 | /* Indicates to the driver not to assert due to lack | ||
692 | * of MCP response */ | ||
693 | #define MCP_EVENT_MASK 0xffff0000 | ||
694 | #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 | ||
670 | 695 | ||
671 | struct shared_feat_cfg shared_feature_config; /* 4 */ | 696 | u32 iscsi_boot_signature; |
697 | u32 iscsi_boot_block_offset; | ||
672 | 698 | ||
673 | struct port_feat_cfg port_feature_config[FUNC_MAX];/* 116*2=232 */ | 699 | u32 reserved[3]; |
674 | 700 | ||
675 | }; | 701 | }; |
676 | 702 | ||
@@ -678,9 +704,8 @@ struct dev_info { /* size */ | |||
678 | /**************************************************************************** | 704 | /**************************************************************************** |
679 | * Management firmware state * | 705 | * Management firmware state * |
680 | ****************************************************************************/ | 706 | ****************************************************************************/ |
681 | /* Allocate 320 bytes for management firmware: still not known exactly | 707 | /* Allocate 440 bytes for management firmware */ |
682 | * how much IMD needs. */ | 708 | #define MGMTFW_STATE_WORD_SIZE 110 |
683 | #define MGMTFW_STATE_WORD_SIZE 80 | ||
684 | 709 | ||
685 | struct mgmtfw_state { | 710 | struct mgmtfw_state { |
686 | u32 opaque[MGMTFW_STATE_WORD_SIZE]; | 711 | u32 opaque[MGMTFW_STATE_WORD_SIZE]; |
@@ -691,31 +716,40 @@ struct mgmtfw_state { | |||
691 | * Shared Memory Region * | 716 | * Shared Memory Region * |
692 | ****************************************************************************/ | 717 | ****************************************************************************/ |
693 | struct shmem_region { /* SharedMem Offset (size) */ | 718 | struct shmem_region { /* SharedMem Offset (size) */ |
694 | u32 validity_map[FUNC_MAX]; /* 0x0 (4 * 2 = 0x8) */ | 719 | |
695 | #define SHR_MEM_VALIDITY_PCI_CFG 0x00000001 | 720 | u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */ |
696 | #define SHR_MEM_VALIDITY_MB 0x00000002 | 721 | #define SHR_MEM_FORMAT_REV_ID ('A'<<24) |
697 | #define SHR_MEM_VALIDITY_DEV_INFO 0x00000004 | 722 | #define SHR_MEM_FORMAT_REV_MASK 0xff000000 |
723 | /* validity bits */ | ||
724 | #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000 | ||
725 | #define SHR_MEM_VALIDITY_MB 0x00200000 | ||
726 | #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000 | ||
727 | #define SHR_MEM_VALIDITY_RESERVED 0x00000007 | ||
698 | /* One licensing bit should be set */ | 728 | /* One licensing bit should be set */ |
699 | #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 | 729 | #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 |
700 | #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 | 730 | #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 |
701 | #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 | 731 | #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 |
702 | #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 | 732 | #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 |
733 | /* Active MFW */ | ||
734 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 | ||
735 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040 | ||
736 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080 | ||
737 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0 | ||
738 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 | ||
739 | #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 | ||
703 | 740 | ||
704 | struct drv_fw_mb drv_fw_mb[FUNC_MAX]; /* 0x8 (28 * 2 = 0x38) */ | 741 | struct dev_info dev_info; /* 0x8 (0x438) */ |
705 | |||
706 | struct dev_info dev_info; /* 0x40 (0x438) */ | ||
707 | 742 | ||
708 | #ifdef _LICENSE_H | 743 | u8 reserved[52*PORT_MAX]; |
709 | license_key_t drv_lic_key[FUNC_MAX]; /* 0x478 (52 * 2 = 0x68) */ | ||
710 | #else /* Linux! */ | ||
711 | u8 reserved[52*FUNC_MAX]; | ||
712 | #endif | ||
713 | 744 | ||
714 | /* FW information (for internal FW use) */ | 745 | /* FW information (for internal FW use) */ |
715 | u32 fw_info_fio_offset; /* 0x4e0 (0x4) */ | 746 | u32 fw_info_fio_offset; /* 0x4a8 (0x4) */ |
716 | struct mgmtfw_state mgmtfw_state; /* 0x4e4 (0x140) */ | 747 | struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ |
748 | |||
749 | struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ | ||
750 | struct drv_func_mb func_mb[FUNC_MAX]; /* 0x684 (44*2=0x58) */ | ||
717 | 751 | ||
718 | }; /* 0x624 */ | 752 | }; /* 0x6dc */ |
719 | 753 | ||
720 | 754 | ||
721 | #define BCM_5710_FW_MAJOR_VERSION 4 | 755 | #define BCM_5710_FW_MAJOR_VERSION 4 |
diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h index 04f93bff2ef4..dcaecc53bdb1 100644 --- a/drivers/net/bnx2x_init.h +++ b/drivers/net/bnx2x_init.h | |||
@@ -1,6 +1,6 @@ | |||
1 | /* bnx2x_init.h: Broadcom Everest network driver. | 1 | /* bnx2x_init.h: Broadcom Everest network driver. |
2 | * | 2 | * |
3 | * Copyright (c) 2007 Broadcom Corporation | 3 | * Copyright (c) 2007-2008 Broadcom Corporation |
4 | * | 4 | * |
5 | * This program is free software; you can redistribute it and/or modify | 5 | * This program is free software; you can redistribute it and/or modify |
6 | * it under the terms of the GNU General Public License as published by | 6 | * it under the terms of the GNU General Public License as published by |
@@ -409,7 +409,7 @@ static void bnx2x_init_pxp(struct bnx2x *bp) | |||
409 | 409 | ||
410 | pci_read_config_word(bp->pdev, | 410 | pci_read_config_word(bp->pdev, |
411 | bp->pcie_cap + PCI_EXP_DEVCTL, (u16 *)&val); | 411 | bp->pcie_cap + PCI_EXP_DEVCTL, (u16 *)&val); |
412 | DP(NETIF_MSG_HW, "read 0x%x from devctl\n", val); | 412 | DP(NETIF_MSG_HW, "read 0x%x from devctl\n", (u16)val); |
413 | w_order = ((val & PCI_EXP_DEVCTL_PAYLOAD) >> 5); | 413 | w_order = ((val & PCI_EXP_DEVCTL_PAYLOAD) >> 5); |
414 | r_order = ((val & PCI_EXP_DEVCTL_READRQ) >> 12); | 414 | r_order = ((val & PCI_EXP_DEVCTL_READRQ) >> 12); |
415 | 415 | ||
@@ -472,10 +472,14 @@ static void bnx2x_init_pxp(struct bnx2x *bp) | |||
472 | REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val); | 472 | REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val); |
473 | 473 | ||
474 | REG_WR(bp, PXP2_REG_RQ_WR_MBS0, w_order); | 474 | REG_WR(bp, PXP2_REG_RQ_WR_MBS0, w_order); |
475 | REG_WR(bp, PXP2_REG_RQ_WR_MBS0 + 8, w_order); | 475 | REG_WR(bp, PXP2_REG_RQ_WR_MBS1, w_order); |
476 | REG_WR(bp, PXP2_REG_RQ_RD_MBS0, r_order); | 476 | REG_WR(bp, PXP2_REG_RQ_RD_MBS0, r_order); |
477 | REG_WR(bp, PXP2_REG_RQ_RD_MBS0 + 8, r_order); | 477 | REG_WR(bp, PXP2_REG_RQ_RD_MBS1, r_order); |
478 | 478 | ||
479 | if (r_order == MAX_RD_ORD) | ||
480 | REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00); | ||
481 | |||
482 | REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order)); | ||
479 | REG_WR(bp, PXP2_REG_WR_DMAE_TH, (128 << w_order)/16); | 483 | REG_WR(bp, PXP2_REG_WR_DMAE_TH, (128 << w_order)/16); |
480 | } | 484 | } |
481 | 485 | ||
diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h index 86055297ab02..5a1aa0b55044 100644 --- a/drivers/net/bnx2x_reg.h +++ b/drivers/net/bnx2x_reg.h | |||
@@ -1,6 +1,6 @@ | |||
1 | /* bnx2x_reg.h: Broadcom Everest network driver. | 1 | /* bnx2x_reg.h: Broadcom Everest network driver. |
2 | * | 2 | * |
3 | * Copyright (c) 2007 Broadcom Corporation | 3 | * Copyright (c) 2007-2008 Broadcom Corporation |
4 | * | 4 | * |
5 | * This program is free software; you can redistribute it and/or modify | 5 | * This program is free software; you can redistribute it and/or modify |
6 | * it under the terms of the GNU General Public License as published by | 6 | * it under the terms of the GNU General Public License as published by |
@@ -24,6 +24,8 @@ | |||
24 | #define BRB1_REG_BRB1_INT_STS 0x6011c | 24 | #define BRB1_REG_BRB1_INT_STS 0x6011c |
25 | /* [RW 4] Parity mask register #0 read/write */ | 25 | /* [RW 4] Parity mask register #0 read/write */ |
26 | #define BRB1_REG_BRB1_PRTY_MASK 0x60138 | 26 | #define BRB1_REG_BRB1_PRTY_MASK 0x60138 |
27 | /* [R 4] Parity register #0 read */ | ||
28 | #define BRB1_REG_BRB1_PRTY_STS 0x6012c | ||
27 | /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At | 29 | /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At |
28 | address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address | 30 | address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address |
29 | BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. */ | 31 | BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. */ |
@@ -281,6 +283,8 @@ | |||
281 | #define CDU_REG_CDU_INT_STS 0x101030 | 283 | #define CDU_REG_CDU_INT_STS 0x101030 |
282 | /* [RW 5] Parity mask register #0 read/write */ | 284 | /* [RW 5] Parity mask register #0 read/write */ |
283 | #define CDU_REG_CDU_PRTY_MASK 0x10104c | 285 | #define CDU_REG_CDU_PRTY_MASK 0x10104c |
286 | /* [R 5] Parity register #0 read */ | ||
287 | #define CDU_REG_CDU_PRTY_STS 0x101040 | ||
284 | /* [RC 32] logging of error data in case of a CDU load error: | 288 | /* [RC 32] logging of error data in case of a CDU load error: |
285 | {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error; | 289 | {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error; |
286 | ype_error; ctual_active; ctual_compressed_context}; */ | 290 | ype_error; ctual_active; ctual_compressed_context}; */ |
@@ -308,6 +312,8 @@ | |||
308 | #define CFC_REG_CFC_INT_STS_CLR 0x104100 | 312 | #define CFC_REG_CFC_INT_STS_CLR 0x104100 |
309 | /* [RW 4] Parity mask register #0 read/write */ | 313 | /* [RW 4] Parity mask register #0 read/write */ |
310 | #define CFC_REG_CFC_PRTY_MASK 0x104118 | 314 | #define CFC_REG_CFC_PRTY_MASK 0x104118 |
315 | /* [R 4] Parity register #0 read */ | ||
316 | #define CFC_REG_CFC_PRTY_STS 0x10410c | ||
311 | /* [RW 21] CID cam access (21:1 - Data; alid - 0) */ | 317 | /* [RW 21] CID cam access (21:1 - Data; alid - 0) */ |
312 | #define CFC_REG_CID_CAM 0x104800 | 318 | #define CFC_REG_CID_CAM 0x104800 |
313 | #define CFC_REG_CONTROL0 0x104028 | 319 | #define CFC_REG_CONTROL0 0x104028 |
@@ -354,6 +360,8 @@ | |||
354 | #define CSDM_REG_CSDM_INT_MASK_1 0xc22ac | 360 | #define CSDM_REG_CSDM_INT_MASK_1 0xc22ac |
355 | /* [RW 11] Parity mask register #0 read/write */ | 361 | /* [RW 11] Parity mask register #0 read/write */ |
356 | #define CSDM_REG_CSDM_PRTY_MASK 0xc22bc | 362 | #define CSDM_REG_CSDM_PRTY_MASK 0xc22bc |
363 | /* [R 11] Parity register #0 read */ | ||
364 | #define CSDM_REG_CSDM_PRTY_STS 0xc22b0 | ||
357 | #define CSDM_REG_ENABLE_IN1 0xc2238 | 365 | #define CSDM_REG_ENABLE_IN1 0xc2238 |
358 | #define CSDM_REG_ENABLE_IN2 0xc223c | 366 | #define CSDM_REG_ENABLE_IN2 0xc223c |
359 | #define CSDM_REG_ENABLE_OUT1 0xc2240 | 367 | #define CSDM_REG_ENABLE_OUT1 0xc2240 |
@@ -438,6 +446,9 @@ | |||
438 | /* [RW 32] Parity mask register #0 read/write */ | 446 | /* [RW 32] Parity mask register #0 read/write */ |
439 | #define CSEM_REG_CSEM_PRTY_MASK_0 0x200130 | 447 | #define CSEM_REG_CSEM_PRTY_MASK_0 0x200130 |
440 | #define CSEM_REG_CSEM_PRTY_MASK_1 0x200140 | 448 | #define CSEM_REG_CSEM_PRTY_MASK_1 0x200140 |
449 | /* [R 32] Parity register #0 read */ | ||
450 | #define CSEM_REG_CSEM_PRTY_STS_0 0x200124 | ||
451 | #define CSEM_REG_CSEM_PRTY_STS_1 0x200134 | ||
441 | #define CSEM_REG_ENABLE_IN 0x2000a4 | 452 | #define CSEM_REG_ENABLE_IN 0x2000a4 |
442 | #define CSEM_REG_ENABLE_OUT 0x2000a8 | 453 | #define CSEM_REG_ENABLE_OUT 0x2000a8 |
443 | /* [RW 32] This address space contains all registers and memories that are | 454 | /* [RW 32] This address space contains all registers and memories that are |
@@ -526,6 +537,8 @@ | |||
526 | #define CSEM_REG_TS_9_AS 0x20005c | 537 | #define CSEM_REG_TS_9_AS 0x20005c |
527 | /* [RW 1] Parity mask register #0 read/write */ | 538 | /* [RW 1] Parity mask register #0 read/write */ |
528 | #define DBG_REG_DBG_PRTY_MASK 0xc0a8 | 539 | #define DBG_REG_DBG_PRTY_MASK 0xc0a8 |
540 | /* [R 1] Parity register #0 read */ | ||
541 | #define DBG_REG_DBG_PRTY_STS 0xc09c | ||
529 | /* [RW 2] debug only: These bits indicate the credit for PCI request type 4 | 542 | /* [RW 2] debug only: These bits indicate the credit for PCI request type 4 |
530 | interface; MUST be configured AFTER pci_ext_buffer_strt_addr_lsb/msb are | 543 | interface; MUST be configured AFTER pci_ext_buffer_strt_addr_lsb/msb are |
531 | configured */ | 544 | configured */ |
@@ -543,6 +556,8 @@ | |||
543 | #define DMAE_REG_DMAE_INT_MASK 0x102054 | 556 | #define DMAE_REG_DMAE_INT_MASK 0x102054 |
544 | /* [RW 4] Parity mask register #0 read/write */ | 557 | /* [RW 4] Parity mask register #0 read/write */ |
545 | #define DMAE_REG_DMAE_PRTY_MASK 0x102064 | 558 | #define DMAE_REG_DMAE_PRTY_MASK 0x102064 |
559 | /* [R 4] Parity register #0 read */ | ||
560 | #define DMAE_REG_DMAE_PRTY_STS 0x102058 | ||
546 | /* [RW 1] Command 0 go. */ | 561 | /* [RW 1] Command 0 go. */ |
547 | #define DMAE_REG_GO_C0 0x102080 | 562 | #define DMAE_REG_GO_C0 0x102080 |
548 | /* [RW 1] Command 1 go. */ | 563 | /* [RW 1] Command 1 go. */ |
@@ -623,6 +638,8 @@ | |||
623 | #define DORQ_REG_DORQ_INT_STS_CLR 0x170178 | 638 | #define DORQ_REG_DORQ_INT_STS_CLR 0x170178 |
624 | /* [RW 2] Parity mask register #0 read/write */ | 639 | /* [RW 2] Parity mask register #0 read/write */ |
625 | #define DORQ_REG_DORQ_PRTY_MASK 0x170190 | 640 | #define DORQ_REG_DORQ_PRTY_MASK 0x170190 |
641 | /* [R 2] Parity register #0 read */ | ||
642 | #define DORQ_REG_DORQ_PRTY_STS 0x170184 | ||
626 | /* [RW 8] The address to write the DPM CID to STORM. */ | 643 | /* [RW 8] The address to write the DPM CID to STORM. */ |
627 | #define DORQ_REG_DPM_CID_ADDR 0x170044 | 644 | #define DORQ_REG_DPM_CID_ADDR 0x170044 |
628 | /* [RW 5] The DPM mode CID extraction offset. */ | 645 | /* [RW 5] The DPM mode CID extraction offset. */ |
@@ -692,6 +709,8 @@ | |||
692 | #define HC_REG_CONFIG_1 0x108004 | 709 | #define HC_REG_CONFIG_1 0x108004 |
693 | /* [RW 3] Parity mask register #0 read/write */ | 710 | /* [RW 3] Parity mask register #0 read/write */ |
694 | #define HC_REG_HC_PRTY_MASK 0x1080a0 | 711 | #define HC_REG_HC_PRTY_MASK 0x1080a0 |
712 | /* [R 3] Parity register #0 read */ | ||
713 | #define HC_REG_HC_PRTY_STS 0x108094 | ||
695 | /* [RW 17] status block interrupt mask; one in each bit means unmask; zerow | 714 | /* [RW 17] status block interrupt mask; one in each bit means unmask; zerow |
696 | in each bit means mask; bit 0 - default SB; bit 1 - SB_0; bit 2 - SB_1... | 715 | in each bit means mask; bit 0 - default SB; bit 1 - SB_0; bit 2 - SB_1... |
697 | bit 16- SB_15; addr 0 - port 0; addr 1 - port 1 */ | 716 | bit 16- SB_15; addr 0 - port 0; addr 1 - port 1 */ |
@@ -1127,6 +1146,7 @@ | |||
1127 | #define MISC_REG_AEU_GENERAL_ATTN_17 0xa044 | 1146 | #define MISC_REG_AEU_GENERAL_ATTN_17 0xa044 |
1128 | #define MISC_REG_AEU_GENERAL_ATTN_18 0xa048 | 1147 | #define MISC_REG_AEU_GENERAL_ATTN_18 0xa048 |
1129 | #define MISC_REG_AEU_GENERAL_ATTN_19 0xa04c | 1148 | #define MISC_REG_AEU_GENERAL_ATTN_19 0xa04c |
1149 | #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028 | ||
1130 | #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c | 1150 | #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c |
1131 | #define MISC_REG_AEU_GENERAL_ATTN_2 0xa008 | 1151 | #define MISC_REG_AEU_GENERAL_ATTN_2 0xa008 |
1132 | #define MISC_REG_AEU_GENERAL_ATTN_20 0xa050 | 1152 | #define MISC_REG_AEU_GENERAL_ATTN_20 0xa050 |
@@ -1135,6 +1155,9 @@ | |||
1135 | #define MISC_REG_AEU_GENERAL_ATTN_4 0xa010 | 1155 | #define MISC_REG_AEU_GENERAL_ATTN_4 0xa010 |
1136 | #define MISC_REG_AEU_GENERAL_ATTN_5 0xa014 | 1156 | #define MISC_REG_AEU_GENERAL_ATTN_5 0xa014 |
1137 | #define MISC_REG_AEU_GENERAL_ATTN_6 0xa018 | 1157 | #define MISC_REG_AEU_GENERAL_ATTN_6 0xa018 |
1158 | #define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c | ||
1159 | #define MISC_REG_AEU_GENERAL_ATTN_8 0xa020 | ||
1160 | #define MISC_REG_AEU_GENERAL_ATTN_9 0xa024 | ||
1138 | /* [RW 32] first 32b for inverting the input for function 0; for each bit: | 1161 | /* [RW 32] first 32b for inverting the input for function 0; for each bit: |
1139 | 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for | 1162 | 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for |
1140 | function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; | 1163 | function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; |
@@ -1183,6 +1206,40 @@ | |||
1183 | starts at 0x0 for the A0 tape-out and increments by one for each | 1206 | starts at 0x0 for the A0 tape-out and increments by one for each |
1184 | all-layer tape-out. */ | 1207 | all-layer tape-out. */ |
1185 | #define MISC_REG_CHIP_REV 0xa40c | 1208 | #define MISC_REG_CHIP_REV 0xa40c |
1209 | /* [RW 32] The following driver registers(1..6) represent 6 drivers and 32 | ||
1210 | clients. Each client can be controlled by one driver only. One in each | ||
1211 | bit represent that this driver control the appropriate client (Ex: bit 5 | ||
1212 | is set means this driver control client number 5). addr1 = set; addr0 = | ||
1213 | clear; read from both addresses will give the same result = status. write | ||
1214 | to address 1 will set a request to control all the clients that their | ||
1215 | appropriate bit (in the write command) is set. if the client is free (the | ||
1216 | appropriate bit in all the other drivers is clear) one will be written to | ||
1217 | that driver register; if the client isn't free the bit will remain zero. | ||
1218 | if the appropriate bit is set (the driver request to gain control on a | ||
1219 | client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW | ||
1220 | interrupt will be asserted). write to address 0 will set a request to | ||
1221 | free all the clients that their appropriate bit (in the write command) is | ||
1222 | set. if the appropriate bit is clear (the driver request to free a client | ||
1223 | it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will | ||
1224 | be asserted). */ | ||
1225 | #define MISC_REG_DRIVER_CONTROL_1 0xa510 | ||
1226 | /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of | ||
1227 | these bits is written as a '1'; the corresponding SPIO bit will turn off | ||
1228 | it's drivers and become an input. This is the reset state of all GPIO | ||
1229 | pins. The read value of these bits will be a '1' if that last command | ||
1230 | (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff). | ||
1231 | [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written | ||
1232 | as a '1'; the corresponding GPIO bit will drive low. The read value of | ||
1233 | these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for | ||
1234 | this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0; | ||
1235 | SET When any of these bits is written as a '1'; the corresponding GPIO | ||
1236 | bit will drive high (if it has that capability). The read value of these | ||
1237 | bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this | ||
1238 | bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0; | ||
1239 | RO; These bits indicate the read value of each of the eight GPIO pins. | ||
1240 | This is the result value of the pin; not the drive value. Writing these | ||
1241 | bits will have not effect. */ | ||
1242 | #define MISC_REG_GPIO 0xa490 | ||
1186 | /* [RW 1] Setting this bit enables a timer in the GRC block to timeout any | 1243 | /* [RW 1] Setting this bit enables a timer in the GRC block to timeout any |
1187 | access that does not finish within | 1244 | access that does not finish within |
1188 | ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is | 1245 | ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is |
@@ -1223,6 +1280,8 @@ | |||
1223 | #define MISC_REG_MISC_INT_MASK 0xa388 | 1280 | #define MISC_REG_MISC_INT_MASK 0xa388 |
1224 | /* [RW 1] Parity mask register #0 read/write */ | 1281 | /* [RW 1] Parity mask register #0 read/write */ |
1225 | #define MISC_REG_MISC_PRTY_MASK 0xa398 | 1282 | #define MISC_REG_MISC_PRTY_MASK 0xa398 |
1283 | /* [R 1] Parity register #0 read */ | ||
1284 | #define MISC_REG_MISC_PRTY_STS 0xa38c | ||
1226 | /* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911. | 1285 | /* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911. |
1227 | inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1 | 1286 | inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1 |
1228 | divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1 | 1287 | divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1 |
@@ -1264,6 +1323,55 @@ | |||
1264 | /* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is | 1323 | /* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is |
1265 | shared with the driver resides */ | 1324 | shared with the driver resides */ |
1266 | #define MISC_REG_SHARED_MEM_ADDR 0xa2b4 | 1325 | #define MISC_REG_SHARED_MEM_ADDR 0xa2b4 |
1326 | /* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1'; | ||
1327 | the corresponding SPIO bit will turn off it's drivers and become an | ||
1328 | input. This is the reset state of all SPIO pins. The read value of these | ||
1329 | bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this | ||
1330 | bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits | ||
1331 | is written as a '1'; the corresponding SPIO bit will drive low. The read | ||
1332 | value of these bits will be a '1' if that last command (#SET; #CLR; or | ||
1333 | #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of | ||
1334 | these bits is written as a '1'; the corresponding SPIO bit will drive | ||
1335 | high (if it has that capability). The read value of these bits will be a | ||
1336 | '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET. | ||
1337 | (reset value 0). [7-0] VALUE RO; These bits indicate the read value of | ||
1338 | each of the eight SPIO pins. This is the result value of the pin; not the | ||
1339 | drive value. Writing these bits will have not effect. Each 8 bits field | ||
1340 | is divided as follows: [0] VAUX Enable; when pulsed low; enables supply | ||
1341 | from VAUX. (This is an output pin only; the FLOAT field is not applicable | ||
1342 | for this pin); [1] VAUX Disable; when pulsed low; disables supply form | ||
1343 | VAUX. (This is an output pin only; FLOAT field is not applicable for this | ||
1344 | pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to | ||
1345 | select VAUX supply. (This is an output pin only; it is not controlled by | ||
1346 | the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT | ||
1347 | field is not applicable for this pin; only the VALUE fields is relevant - | ||
1348 | it reflects the output value); [3] reserved; [4] spio_4; [5] spio_5; [6] | ||
1349 | Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP | ||
1350 | device ID select; read by UMP firmware. */ | ||
1351 | #define MISC_REG_SPIO 0xa4fc | ||
1352 | /* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC. | ||
1353 | according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5; | ||
1354 | [7:0] reserved */ | ||
1355 | #define MISC_REG_SPIO_EVENT_EN 0xa2b8 | ||
1356 | /* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the | ||
1357 | corresponding bit in the #OLD_VALUE register. This will acknowledge an | ||
1358 | interrupt on the falling edge of corresponding SPIO input (reset value | ||
1359 | 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit | ||
1360 | in the #OLD_VALUE register. This will acknowledge an interrupt on the | ||
1361 | rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE | ||
1362 | RO; These bits indicate the old value of the SPIO input value. When the | ||
1363 | ~INT_STATE bit is set; this bit indicates the OLD value of the pin such | ||
1364 | that if ~INT_STATE is set and this bit is '0'; then the interrupt is due | ||
1365 | to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the | ||
1366 | interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE | ||
1367 | RO; These bits indicate the current SPIO interrupt state for each SPIO | ||
1368 | pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR | ||
1369 | command bit is written. This bit is set when the SPIO input does not | ||
1370 | match the current value in #OLD_VALUE (reset value 0). */ | ||
1371 | #define MISC_REG_SPIO_INT 0xa500 | ||
1372 | /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are | ||
1373 | loaded; 0-prepare; -unprepare */ | ||
1374 | #define MISC_REG_UNPREPARED 0xa424 | ||
1267 | #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0) | 1375 | #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0) |
1268 | #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9) | 1376 | #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9) |
1269 | #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15) | 1377 | #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15) |
@@ -1392,6 +1500,9 @@ | |||
1392 | #define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044 | 1500 | #define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044 |
1393 | /* [RW 1] Input enable for RX PBF LP IF */ | 1501 | /* [RW 1] Input enable for RX PBF LP IF */ |
1394 | #define NIG_REG_PBF_LB_IN_EN 0x100b4 | 1502 | #define NIG_REG_PBF_LB_IN_EN 0x100b4 |
1503 | /* [RW 1] Value of this register will be transmitted to port swap when | ||
1504 | ~nig_registers_strap_override.strap_override =1 */ | ||
1505 | #define NIG_REG_PORT_SWAP 0x10394 | ||
1395 | /* [RW 1] output enable for RX parser descriptor IF */ | 1506 | /* [RW 1] output enable for RX parser descriptor IF */ |
1396 | #define NIG_REG_PRS_EOP_OUT_EN 0x10104 | 1507 | #define NIG_REG_PRS_EOP_OUT_EN 0x10104 |
1397 | /* [RW 1] Input enable for RX parser request IF */ | 1508 | /* [RW 1] Input enable for RX parser request IF */ |
@@ -1410,6 +1521,10 @@ | |||
1410 | #define NIG_REG_STAT2_BRB_OCTET 0x107e0 | 1521 | #define NIG_REG_STAT2_BRB_OCTET 0x107e0 |
1411 | #define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328 | 1522 | #define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328 |
1412 | #define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c | 1523 | #define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c |
1524 | /* [RW 1] port swap mux selection. If this register equal to 0 then port | ||
1525 | swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then | ||
1526 | ort swap is equal to ~nig_registers_port_swap.port_swap */ | ||
1527 | #define NIG_REG_STRAP_OVERRIDE 0x10398 | ||
1413 | /* [RW 1] output enable for RX_XCM0 IF */ | 1528 | /* [RW 1] output enable for RX_XCM0 IF */ |
1414 | #define NIG_REG_XCM0_OUT_EN 0x100f0 | 1529 | #define NIG_REG_XCM0_OUT_EN 0x100f0 |
1415 | /* [RW 1] output enable for RX_XCM1 IF */ | 1530 | /* [RW 1] output enable for RX_XCM1 IF */ |
@@ -1499,6 +1614,8 @@ | |||
1499 | #define PB_REG_PB_INT_STS 0x1c | 1614 | #define PB_REG_PB_INT_STS 0x1c |
1500 | /* [RW 4] Parity mask register #0 read/write */ | 1615 | /* [RW 4] Parity mask register #0 read/write */ |
1501 | #define PB_REG_PB_PRTY_MASK 0x38 | 1616 | #define PB_REG_PB_PRTY_MASK 0x38 |
1617 | /* [R 4] Parity register #0 read */ | ||
1618 | #define PB_REG_PB_PRTY_STS 0x2c | ||
1502 | #define PRS_REG_A_PRSU_20 0x40134 | 1619 | #define PRS_REG_A_PRSU_20 0x40134 |
1503 | /* [R 8] debug only: CFC load request current credit. Transaction based. */ | 1620 | /* [R 8] debug only: CFC load request current credit. Transaction based. */ |
1504 | #define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164 | 1621 | #define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164 |
@@ -1590,6 +1707,8 @@ | |||
1590 | #define PRS_REG_PRS_INT_STS 0x40188 | 1707 | #define PRS_REG_PRS_INT_STS 0x40188 |
1591 | /* [RW 8] Parity mask register #0 read/write */ | 1708 | /* [RW 8] Parity mask register #0 read/write */ |
1592 | #define PRS_REG_PRS_PRTY_MASK 0x401a4 | 1709 | #define PRS_REG_PRS_PRTY_MASK 0x401a4 |
1710 | /* [R 8] Parity register #0 read */ | ||
1711 | #define PRS_REG_PRS_PRTY_STS 0x40198 | ||
1593 | /* [RW 8] Context region for pure acknowledge packets. Used in CFC load | 1712 | /* [RW 8] Context region for pure acknowledge packets. Used in CFC load |
1594 | request message */ | 1713 | request message */ |
1595 | #define PRS_REG_PURE_REGIONS 0x40024 | 1714 | #define PRS_REG_PURE_REGIONS 0x40024 |
@@ -1718,6 +1837,9 @@ | |||
1718 | /* [RW 32] Parity mask register #0 read/write */ | 1837 | /* [RW 32] Parity mask register #0 read/write */ |
1719 | #define PXP2_REG_PXP2_PRTY_MASK_0 0x120588 | 1838 | #define PXP2_REG_PXP2_PRTY_MASK_0 0x120588 |
1720 | #define PXP2_REG_PXP2_PRTY_MASK_1 0x120598 | 1839 | #define PXP2_REG_PXP2_PRTY_MASK_1 0x120598 |
1840 | /* [R 32] Parity register #0 read */ | ||
1841 | #define PXP2_REG_PXP2_PRTY_STS_0 0x12057c | ||
1842 | #define PXP2_REG_PXP2_PRTY_STS_1 0x12058c | ||
1721 | /* [R 1] Debug only: The 'almost full' indication from each fifo (gives | 1843 | /* [R 1] Debug only: The 'almost full' indication from each fifo (gives |
1722 | indication about backpressure) */ | 1844 | indication about backpressure) */ |
1723 | #define PXP2_REG_RD_ALMOST_FULL_0 0x120424 | 1845 | #define PXP2_REG_RD_ALMOST_FULL_0 0x120424 |
@@ -1911,6 +2033,8 @@ | |||
1911 | #define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8 | 2033 | #define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8 |
1912 | /* [WB 53] Onchip address table */ | 2034 | /* [WB 53] Onchip address table */ |
1913 | #define PXP2_REG_RQ_ONCHIP_AT 0x122000 | 2035 | #define PXP2_REG_RQ_ONCHIP_AT 0x122000 |
2036 | /* [RW 13] Pending read limiter threshold; in Dwords */ | ||
2037 | #define PXP2_REG_RQ_PDR_LIMIT 0x12033c | ||
1914 | /* [RW 2] Endian mode for qm */ | 2038 | /* [RW 2] Endian mode for qm */ |
1915 | #define PXP2_REG_RQ_QM_ENDIAN_M 0x120194 | 2039 | #define PXP2_REG_RQ_QM_ENDIAN_M 0x120194 |
1916 | /* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k; | 2040 | /* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k; |
@@ -1921,6 +2045,9 @@ | |||
1921 | /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B; | 2045 | /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B; |
1922 | 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */ | 2046 | 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */ |
1923 | #define PXP2_REG_RQ_RD_MBS0 0x120160 | 2047 | #define PXP2_REG_RQ_RD_MBS0 0x120160 |
2048 | /* [RW 3] Max burst size filed for read requests port 1; 000 - 128B; | ||
2049 | 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */ | ||
2050 | #define PXP2_REG_RQ_RD_MBS1 0x120168 | ||
1924 | /* [RW 2] Endian mode for src */ | 2051 | /* [RW 2] Endian mode for src */ |
1925 | #define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c | 2052 | #define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c |
1926 | /* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k; | 2053 | /* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k; |
@@ -2000,10 +2127,17 @@ | |||
2000 | /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B; | 2127 | /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B; |
2001 | 001:256B; 010: 512B; */ | 2128 | 001:256B; 010: 512B; */ |
2002 | #define PXP2_REG_RQ_WR_MBS0 0x12015c | 2129 | #define PXP2_REG_RQ_WR_MBS0 0x12015c |
2130 | /* [RW 3] Max burst size filed for write requests port 1; 000 - 128B; | ||
2131 | 001:256B; 010: 512B; */ | ||
2132 | #define PXP2_REG_RQ_WR_MBS1 0x120164 | ||
2003 | /* [RW 10] if Number of entries in dmae fifo will be higer than this | 2133 | /* [RW 10] if Number of entries in dmae fifo will be higer than this |
2004 | threshold then has_payload indication will be asserted; the default value | 2134 | threshold then has_payload indication will be asserted; the default value |
2005 | should be equal to > write MBS size! */ | 2135 | should be equal to > write MBS size! */ |
2006 | #define PXP2_REG_WR_DMAE_TH 0x120368 | 2136 | #define PXP2_REG_WR_DMAE_TH 0x120368 |
2137 | /* [RW 10] if Number of entries in usdmdp fifo will be higer than this | ||
2138 | threshold then has_payload indication will be asserted; the default value | ||
2139 | should be equal to > write MBS size! */ | ||
2140 | #define PXP2_REG_WR_USDMDP_TH 0x120348 | ||
2007 | /* [R 1] debug only: Indication if PSWHST arbiter is idle */ | 2141 | /* [R 1] debug only: Indication if PSWHST arbiter is idle */ |
2008 | #define PXP_REG_HST_ARB_IS_IDLE 0x103004 | 2142 | #define PXP_REG_HST_ARB_IS_IDLE 0x103004 |
2009 | /* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means | 2143 | /* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means |
@@ -2021,6 +2155,8 @@ | |||
2021 | #define PXP_REG_PXP_INT_STS_CLR_0 0x10306c | 2155 | #define PXP_REG_PXP_INT_STS_CLR_0 0x10306c |
2022 | /* [RW 26] Parity mask register #0 read/write */ | 2156 | /* [RW 26] Parity mask register #0 read/write */ |
2023 | #define PXP_REG_PXP_PRTY_MASK 0x103094 | 2157 | #define PXP_REG_PXP_PRTY_MASK 0x103094 |
2158 | /* [R 26] Parity register #0 read */ | ||
2159 | #define PXP_REG_PXP_PRTY_STS 0x103088 | ||
2024 | /* [RW 4] The activity counter initial increment value sent in the load | 2160 | /* [RW 4] The activity counter initial increment value sent in the load |
2025 | request */ | 2161 | request */ |
2026 | #define QM_REG_ACTCTRINITVAL_0 0x168040 | 2162 | #define QM_REG_ACTCTRINITVAL_0 0x168040 |
@@ -2127,6 +2263,8 @@ | |||
2127 | #define QM_REG_QM_INT_STS 0x168438 | 2263 | #define QM_REG_QM_INT_STS 0x168438 |
2128 | /* [RW 9] Parity mask register #0 read/write */ | 2264 | /* [RW 9] Parity mask register #0 read/write */ |
2129 | #define QM_REG_QM_PRTY_MASK 0x168454 | 2265 | #define QM_REG_QM_PRTY_MASK 0x168454 |
2266 | /* [R 9] Parity register #0 read */ | ||
2267 | #define QM_REG_QM_PRTY_STS 0x168448 | ||
2130 | /* [R 32] Current queues in pipeline: Queues from 32 to 63 */ | 2268 | /* [R 32] Current queues in pipeline: Queues from 32 to 63 */ |
2131 | #define QM_REG_QSTATUS_HIGH 0x16802c | 2269 | #define QM_REG_QSTATUS_HIGH 0x16802c |
2132 | /* [R 32] Current queues in pipeline: Queues from 0 to 31 */ | 2270 | /* [R 32] Current queues in pipeline: Queues from 0 to 31 */ |
@@ -2410,6 +2548,8 @@ | |||
2410 | #define SRC_REG_SRC_INT_STS 0x404ac | 2548 | #define SRC_REG_SRC_INT_STS 0x404ac |
2411 | /* [RW 3] Parity mask register #0 read/write */ | 2549 | /* [RW 3] Parity mask register #0 read/write */ |
2412 | #define SRC_REG_SRC_PRTY_MASK 0x404c8 | 2550 | #define SRC_REG_SRC_PRTY_MASK 0x404c8 |
2551 | /* [R 3] Parity register #0 read */ | ||
2552 | #define SRC_REG_SRC_PRTY_STS 0x404bc | ||
2413 | /* [R 4] Used to read the value of the XX protection CAM occupancy counter. */ | 2553 | /* [R 4] Used to read the value of the XX protection CAM occupancy counter. */ |
2414 | #define TCM_REG_CAM_OCCUP 0x5017c | 2554 | #define TCM_REG_CAM_OCCUP 0x5017c |
2415 | /* [RW 1] CDU AG read Interface enable. If 0 - the request input is | 2555 | /* [RW 1] CDU AG read Interface enable. If 0 - the request input is |
@@ -2730,6 +2870,8 @@ | |||
2730 | #define TSDM_REG_TSDM_INT_MASK_1 0x422ac | 2870 | #define TSDM_REG_TSDM_INT_MASK_1 0x422ac |
2731 | /* [RW 11] Parity mask register #0 read/write */ | 2871 | /* [RW 11] Parity mask register #0 read/write */ |
2732 | #define TSDM_REG_TSDM_PRTY_MASK 0x422bc | 2872 | #define TSDM_REG_TSDM_PRTY_MASK 0x422bc |
2873 | /* [R 11] Parity register #0 read */ | ||
2874 | #define TSDM_REG_TSDM_PRTY_STS 0x422b0 | ||
2733 | /* [RW 5] The number of time_slots in the arbitration cycle */ | 2875 | /* [RW 5] The number of time_slots in the arbitration cycle */ |
2734 | #define TSEM_REG_ARB_CYCLE_SIZE 0x180034 | 2876 | #define TSEM_REG_ARB_CYCLE_SIZE 0x180034 |
2735 | /* [RW 3] The source that is associated with arbitration element 0. Source | 2877 | /* [RW 3] The source that is associated with arbitration element 0. Source |
@@ -2854,6 +2996,9 @@ | |||
2854 | /* [RW 32] Parity mask register #0 read/write */ | 2996 | /* [RW 32] Parity mask register #0 read/write */ |
2855 | #define TSEM_REG_TSEM_PRTY_MASK_0 0x180120 | 2997 | #define TSEM_REG_TSEM_PRTY_MASK_0 0x180120 |
2856 | #define TSEM_REG_TSEM_PRTY_MASK_1 0x180130 | 2998 | #define TSEM_REG_TSEM_PRTY_MASK_1 0x180130 |
2999 | /* [R 32] Parity register #0 read */ | ||
3000 | #define TSEM_REG_TSEM_PRTY_STS_0 0x180114 | ||
3001 | #define TSEM_REG_TSEM_PRTY_STS_1 0x180124 | ||
2857 | /* [R 5] Used to read the XX protection CAM occupancy counter. */ | 3002 | /* [R 5] Used to read the XX protection CAM occupancy counter. */ |
2858 | #define UCM_REG_CAM_OCCUP 0xe0170 | 3003 | #define UCM_REG_CAM_OCCUP 0xe0170 |
2859 | /* [RW 1] CDU AG read Interface enable. If 0 - the request input is | 3004 | /* [RW 1] CDU AG read Interface enable. If 0 - the request input is |
@@ -3155,6 +3300,8 @@ | |||
3155 | #define USDM_REG_USDM_INT_MASK_1 0xc42b0 | 3300 | #define USDM_REG_USDM_INT_MASK_1 0xc42b0 |
3156 | /* [RW 11] Parity mask register #0 read/write */ | 3301 | /* [RW 11] Parity mask register #0 read/write */ |
3157 | #define USDM_REG_USDM_PRTY_MASK 0xc42c0 | 3302 | #define USDM_REG_USDM_PRTY_MASK 0xc42c0 |
3303 | /* [R 11] Parity register #0 read */ | ||
3304 | #define USDM_REG_USDM_PRTY_STS 0xc42b4 | ||
3158 | /* [RW 5] The number of time_slots in the arbitration cycle */ | 3305 | /* [RW 5] The number of time_slots in the arbitration cycle */ |
3159 | #define USEM_REG_ARB_CYCLE_SIZE 0x300034 | 3306 | #define USEM_REG_ARB_CYCLE_SIZE 0x300034 |
3160 | /* [RW 3] The source that is associated with arbitration element 0. Source | 3307 | /* [RW 3] The source that is associated with arbitration element 0. Source |
@@ -3279,6 +3426,9 @@ | |||
3279 | /* [RW 32] Parity mask register #0 read/write */ | 3426 | /* [RW 32] Parity mask register #0 read/write */ |
3280 | #define USEM_REG_USEM_PRTY_MASK_0 0x300130 | 3427 | #define USEM_REG_USEM_PRTY_MASK_0 0x300130 |
3281 | #define USEM_REG_USEM_PRTY_MASK_1 0x300140 | 3428 | #define USEM_REG_USEM_PRTY_MASK_1 0x300140 |
3429 | /* [R 32] Parity register #0 read */ | ||
3430 | #define USEM_REG_USEM_PRTY_STS_0 0x300124 | ||
3431 | #define USEM_REG_USEM_PRTY_STS_1 0x300134 | ||
3282 | /* [RW 2] The queue index for registration on Aux1 counter flag. */ | 3432 | /* [RW 2] The queue index for registration on Aux1 counter flag. */ |
3283 | #define XCM_REG_AUX1_Q 0x20134 | 3433 | #define XCM_REG_AUX1_Q 0x20134 |
3284 | /* [RW 2] Per each decision rule the queue index to register to. */ | 3434 | /* [RW 2] Per each decision rule the queue index to register to. */ |
@@ -3684,6 +3834,8 @@ | |||
3684 | #define XSDM_REG_XSDM_INT_MASK_1 0x1662ac | 3834 | #define XSDM_REG_XSDM_INT_MASK_1 0x1662ac |
3685 | /* [RW 11] Parity mask register #0 read/write */ | 3835 | /* [RW 11] Parity mask register #0 read/write */ |
3686 | #define XSDM_REG_XSDM_PRTY_MASK 0x1662bc | 3836 | #define XSDM_REG_XSDM_PRTY_MASK 0x1662bc |
3837 | /* [R 11] Parity register #0 read */ | ||
3838 | #define XSDM_REG_XSDM_PRTY_STS 0x1662b0 | ||
3687 | /* [RW 5] The number of time_slots in the arbitration cycle */ | 3839 | /* [RW 5] The number of time_slots in the arbitration cycle */ |
3688 | #define XSEM_REG_ARB_CYCLE_SIZE 0x280034 | 3840 | #define XSEM_REG_ARB_CYCLE_SIZE 0x280034 |
3689 | /* [RW 3] The source that is associated with arbitration element 0. Source | 3841 | /* [RW 3] The source that is associated with arbitration element 0. Source |
@@ -3808,6 +3960,9 @@ | |||
3808 | /* [RW 32] Parity mask register #0 read/write */ | 3960 | /* [RW 32] Parity mask register #0 read/write */ |
3809 | #define XSEM_REG_XSEM_PRTY_MASK_0 0x280130 | 3961 | #define XSEM_REG_XSEM_PRTY_MASK_0 0x280130 |
3810 | #define XSEM_REG_XSEM_PRTY_MASK_1 0x280140 | 3962 | #define XSEM_REG_XSEM_PRTY_MASK_1 0x280140 |
3963 | /* [R 32] Parity register #0 read */ | ||
3964 | #define XSEM_REG_XSEM_PRTY_STS_0 0x280124 | ||
3965 | #define XSEM_REG_XSEM_PRTY_STS_1 0x280134 | ||
3811 | #define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0) | 3966 | #define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0) |
3812 | #define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1) | 3967 | #define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1) |
3813 | #define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) | 3968 | #define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) |
@@ -3847,6 +4002,8 @@ | |||
3847 | #define EMAC_MDIO_COMM_START_BUSY (1L<<29) | 4002 | #define EMAC_MDIO_COMM_START_BUSY (1L<<29) |
3848 | #define EMAC_MDIO_MODE_AUTO_POLL (1L<<4) | 4003 | #define EMAC_MDIO_MODE_AUTO_POLL (1L<<4) |
3849 | #define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31) | 4004 | #define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31) |
4005 | #define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16) | ||
4006 | #define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16 | ||
3850 | #define EMAC_MODE_25G_MODE (1L<<5) | 4007 | #define EMAC_MODE_25G_MODE (1L<<5) |
3851 | #define EMAC_MODE_ACPI_RCVD (1L<<20) | 4008 | #define EMAC_MODE_ACPI_RCVD (1L<<20) |
3852 | #define EMAC_MODE_HALF_DUPLEX (1L<<1) | 4009 | #define EMAC_MODE_HALF_DUPLEX (1L<<1) |
@@ -3874,6 +4031,17 @@ | |||
3874 | #define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) | 4031 | #define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) |
3875 | #define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) | 4032 | #define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) |
3876 | #define EMAC_TX_MODE_RESET (1L<<0) | 4033 | #define EMAC_TX_MODE_RESET (1L<<0) |
4034 | #define MISC_REGISTERS_GPIO_1 1 | ||
4035 | #define MISC_REGISTERS_GPIO_2 2 | ||
4036 | #define MISC_REGISTERS_GPIO_3 3 | ||
4037 | #define MISC_REGISTERS_GPIO_CLR_POS 16 | ||
4038 | #define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24) | ||
4039 | #define MISC_REGISTERS_GPIO_FLOAT_POS 24 | ||
4040 | #define MISC_REGISTERS_GPIO_INPUT_HI_Z 2 | ||
4041 | #define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1 | ||
4042 | #define MISC_REGISTERS_GPIO_OUTPUT_LOW 0 | ||
4043 | #define MISC_REGISTERS_GPIO_PORT_SHIFT 4 | ||
4044 | #define MISC_REGISTERS_GPIO_SET_POS 8 | ||
3877 | #define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588 | 4045 | #define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588 |
3878 | #define MISC_REGISTERS_RESET_REG_1_SET 0x584 | 4046 | #define MISC_REGISTERS_RESET_REG_1_SET 0x584 |
3879 | #define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598 | 4047 | #define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598 |
@@ -3891,6 +4059,25 @@ | |||
3891 | #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4) | 4059 | #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4) |
3892 | #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8) | 4060 | #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8) |
3893 | #define MISC_REGISTERS_RESET_REG_3_SET 0x5a4 | 4061 | #define MISC_REGISTERS_RESET_REG_3_SET 0x5a4 |
4062 | #define MISC_REGISTERS_SPIO_4 4 | ||
4063 | #define MISC_REGISTERS_SPIO_5 5 | ||
4064 | #define MISC_REGISTERS_SPIO_7 7 | ||
4065 | #define MISC_REGISTERS_SPIO_CLR_POS 16 | ||
4066 | #define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24) | ||
4067 | #define GRC_MISC_REGISTERS_SPIO_FLOAT7 0x80000000 | ||
4068 | #define GRC_MISC_REGISTERS_SPIO_FLOAT6 0x40000000 | ||
4069 | #define GRC_MISC_REGISTERS_SPIO_FLOAT5 0x20000000 | ||
4070 | #define GRC_MISC_REGISTERS_SPIO_FLOAT4 0x10000000 | ||
4071 | #define MISC_REGISTERS_SPIO_FLOAT_POS 24 | ||
4072 | #define MISC_REGISTERS_SPIO_INPUT_HI_Z 2 | ||
4073 | #define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16 | ||
4074 | #define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1 | ||
4075 | #define MISC_REGISTERS_SPIO_OUTPUT_LOW 0 | ||
4076 | #define MISC_REGISTERS_SPIO_SET_POS 8 | ||
4077 | #define HW_LOCK_MAX_RESOURCE_VALUE 31 | ||
4078 | #define HW_LOCK_RESOURCE_8072_MDIO 0 | ||
4079 | #define HW_LOCK_RESOURCE_GPIO 1 | ||
4080 | #define HW_LOCK_RESOURCE_SPIO 2 | ||
3894 | #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18) | 4081 | #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18) |
3895 | #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31) | 4082 | #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31) |
3896 | #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9) | 4083 | #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9) |
@@ -3918,6 +4105,7 @@ | |||
3918 | #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (1<<3) | 4105 | #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (1<<3) |
3919 | #define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (1<<2) | 4106 | #define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (1<<2) |
3920 | #define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (1<<22) | 4107 | #define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (1<<22) |
4108 | #define AEU_INPUTS_ATTN_BITS_SPIO5 (1<<15) | ||
3921 | #define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (1<<27) | 4109 | #define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (1<<27) |
3922 | #define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (1<<5) | 4110 | #define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (1<<5) |
3923 | #define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (1<<25) | 4111 | #define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (1<<25) |
@@ -4206,6 +4394,9 @@ | |||
4206 | #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000 | 4394 | #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000 |
4207 | #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11 | 4395 | #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11 |
4208 | #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000 | 4396 | #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000 |
4397 | #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14 | ||
4398 | #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001 | ||
4399 | #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010 | ||
4209 | #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15 | 4400 | #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15 |
4210 | 4401 | ||
4211 | #define MDIO_REG_BANK_GP_STATUS 0x8120 | 4402 | #define MDIO_REG_BANK_GP_STATUS 0x8120 |
@@ -4362,11 +4553,13 @@ | |||
4362 | #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001 | 4553 | #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001 |
4363 | 4554 | ||
4364 | 4555 | ||
4556 | #define EXT_PHY_AUTO_NEG_DEVAD 0x7 | ||
4365 | #define EXT_PHY_OPT_PMA_PMD_DEVAD 0x1 | 4557 | #define EXT_PHY_OPT_PMA_PMD_DEVAD 0x1 |
4366 | #define EXT_PHY_OPT_WIS_DEVAD 0x2 | 4558 | #define EXT_PHY_OPT_WIS_DEVAD 0x2 |
4367 | #define EXT_PHY_OPT_PCS_DEVAD 0x3 | 4559 | #define EXT_PHY_OPT_PCS_DEVAD 0x3 |
4368 | #define EXT_PHY_OPT_PHY_XS_DEVAD 0x4 | 4560 | #define EXT_PHY_OPT_PHY_XS_DEVAD 0x4 |
4369 | #define EXT_PHY_OPT_CNTL 0x0 | 4561 | #define EXT_PHY_OPT_CNTL 0x0 |
4562 | #define EXT_PHY_OPT_CNTL2 0x7 | ||
4370 | #define EXT_PHY_OPT_PMD_RX_SD 0xa | 4563 | #define EXT_PHY_OPT_PMD_RX_SD 0xa |
4371 | #define EXT_PHY_OPT_PMD_MISC_CNTL 0xca0a | 4564 | #define EXT_PHY_OPT_PMD_MISC_CNTL 0xca0a |
4372 | #define EXT_PHY_OPT_PHY_IDENTIFIER 0xc800 | 4565 | #define EXT_PHY_OPT_PHY_IDENTIFIER 0xc800 |
@@ -4378,11 +4571,24 @@ | |||
4378 | #define EXT_PHY_OPT_LASI_STATUS 0x9005 | 4571 | #define EXT_PHY_OPT_LASI_STATUS 0x9005 |
4379 | #define EXT_PHY_OPT_PCS_STATUS 0x0020 | 4572 | #define EXT_PHY_OPT_PCS_STATUS 0x0020 |
4380 | #define EXT_PHY_OPT_XGXS_LANE_STATUS 0x0018 | 4573 | #define EXT_PHY_OPT_XGXS_LANE_STATUS 0x0018 |
4574 | #define EXT_PHY_OPT_AN_LINK_STATUS 0x8304 | ||
4575 | #define EXT_PHY_OPT_AN_CL37_CL73 0x8370 | ||
4576 | #define EXT_PHY_OPT_AN_CL37_FD 0xffe4 | ||
4577 | #define EXT_PHY_OPT_AN_CL37_AN 0xffe0 | ||
4578 | #define EXT_PHY_OPT_AN_ADV 0x11 | ||
4381 | 4579 | ||
4382 | #define EXT_PHY_KR_PMA_PMD_DEVAD 0x1 | 4580 | #define EXT_PHY_KR_PMA_PMD_DEVAD 0x1 |
4383 | #define EXT_PHY_KR_PCS_DEVAD 0x3 | 4581 | #define EXT_PHY_KR_PCS_DEVAD 0x3 |
4384 | #define EXT_PHY_KR_AUTO_NEG_DEVAD 0x7 | 4582 | #define EXT_PHY_KR_AUTO_NEG_DEVAD 0x7 |
4385 | #define EXT_PHY_KR_CTRL 0x0000 | 4583 | #define EXT_PHY_KR_CTRL 0x0000 |
4584 | #define EXT_PHY_KR_STATUS 0x0001 | ||
4585 | #define EXT_PHY_KR_AUTO_NEG_COMPLETE 0x0020 | ||
4586 | #define EXT_PHY_KR_AUTO_NEG_ADVERT 0x0010 | ||
4587 | #define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE 0x0400 | ||
4588 | #define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_ASYMMETRIC 0x0800 | ||
4589 | #define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_BOTH 0x0C00 | ||
4590 | #define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_MASK 0x0C00 | ||
4591 | #define EXT_PHY_KR_LP_AUTO_NEG 0x0013 | ||
4386 | #define EXT_PHY_KR_CTRL2 0x0007 | 4592 | #define EXT_PHY_KR_CTRL2 0x0007 |
4387 | #define EXT_PHY_KR_PCS_STATUS 0x0020 | 4593 | #define EXT_PHY_KR_PCS_STATUS 0x0020 |
4388 | #define EXT_PHY_KR_PMD_CTRL 0x0096 | 4594 | #define EXT_PHY_KR_PMD_CTRL 0x0096 |
@@ -4391,4 +4597,8 @@ | |||
4391 | #define EXT_PHY_KR_MISC_CTRL1 0xca85 | 4597 | #define EXT_PHY_KR_MISC_CTRL1 0xca85 |
4392 | #define EXT_PHY_KR_GEN_CTRL 0xca10 | 4598 | #define EXT_PHY_KR_GEN_CTRL 0xca10 |
4393 | #define EXT_PHY_KR_ROM_CODE 0xca19 | 4599 | #define EXT_PHY_KR_ROM_CODE 0xca19 |
4600 | #define EXT_PHY_KR_ROM_RESET_INTERNAL_MP 0x0188 | ||
4601 | #define EXT_PHY_KR_ROM_MICRO_RESET 0x018a | ||
4602 | |||
4603 | #define EXT_PHY_SFX7101_XGXS_TEST1 0xc00a | ||
4394 | 4604 | ||
diff --git a/drivers/net/cs89x0.c b/drivers/net/cs89x0.c index 571750975137..348371fda597 100644 --- a/drivers/net/cs89x0.c +++ b/drivers/net/cs89x0.c | |||
@@ -172,30 +172,30 @@ static char version[] __initdata = | |||
172 | them to system IRQ numbers. This mapping is card specific and is set to | 172 | them to system IRQ numbers. This mapping is card specific and is set to |
173 | the configuration of the Cirrus Eval board for this chip. */ | 173 | the configuration of the Cirrus Eval board for this chip. */ |
174 | #ifdef CONFIG_ARCH_CLPS7500 | 174 | #ifdef CONFIG_ARCH_CLPS7500 |
175 | static unsigned int netcard_portlist[] __initdata = | 175 | static unsigned int netcard_portlist[] __used __initdata = |
176 | { 0x80090303, 0x300, 0x320, 0x340, 0x360, 0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0, 0}; | 176 | { 0x80090303, 0x300, 0x320, 0x340, 0x360, 0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0, 0}; |
177 | static unsigned int cs8900_irq_map[] = {12,0,0,0}; | 177 | static unsigned int cs8900_irq_map[] = {12,0,0,0}; |
178 | #elif defined(CONFIG_SH_HICOSH4) | 178 | #elif defined(CONFIG_SH_HICOSH4) |
179 | static unsigned int netcard_portlist[] __initdata = | 179 | static unsigned int netcard_portlist[] __used __initdata = |
180 | { 0x0300, 0}; | 180 | { 0x0300, 0}; |
181 | static unsigned int cs8900_irq_map[] = {1,0,0,0}; | 181 | static unsigned int cs8900_irq_map[] = {1,0,0,0}; |
182 | #elif defined(CONFIG_MACH_IXDP2351) | 182 | #elif defined(CONFIG_MACH_IXDP2351) |
183 | static unsigned int netcard_portlist[] __initdata = {IXDP2351_VIRT_CS8900_BASE, 0}; | 183 | static unsigned int netcard_portlist[] __used __initdata = {IXDP2351_VIRT_CS8900_BASE, 0}; |
184 | static unsigned int cs8900_irq_map[] = {IRQ_IXDP2351_CS8900, 0, 0, 0}; | 184 | static unsigned int cs8900_irq_map[] = {IRQ_IXDP2351_CS8900, 0, 0, 0}; |
185 | #include <asm/irq.h> | 185 | #include <asm/irq.h> |
186 | #elif defined(CONFIG_ARCH_IXDP2X01) | 186 | #elif defined(CONFIG_ARCH_IXDP2X01) |
187 | #include <asm/irq.h> | 187 | #include <asm/irq.h> |
188 | static unsigned int netcard_portlist[] __initdata = {IXDP2X01_CS8900_VIRT_BASE, 0}; | 188 | static unsigned int netcard_portlist[] __used __initdata = {IXDP2X01_CS8900_VIRT_BASE, 0}; |
189 | static unsigned int cs8900_irq_map[] = {IRQ_IXDP2X01_CS8900, 0, 0, 0}; | 189 | static unsigned int cs8900_irq_map[] = {IRQ_IXDP2X01_CS8900, 0, 0, 0}; |
190 | #elif defined(CONFIG_ARCH_PNX010X) | 190 | #elif defined(CONFIG_ARCH_PNX010X) |
191 | #include <asm/irq.h> | 191 | #include <asm/irq.h> |
192 | #include <asm/arch/gpio.h> | 192 | #include <asm/arch/gpio.h> |
193 | #define CIRRUS_DEFAULT_BASE IO_ADDRESS(EXT_STATIC2_s0_BASE + 0x200000) /* = Physical address 0x48200000 */ | 193 | #define CIRRUS_DEFAULT_BASE IO_ADDRESS(EXT_STATIC2_s0_BASE + 0x200000) /* = Physical address 0x48200000 */ |
194 | #define CIRRUS_DEFAULT_IRQ VH_INTC_INT_NUM_CASCADED_INTERRUPT_1 /* Event inputs bank 1 - ID 35/bit 3 */ | 194 | #define CIRRUS_DEFAULT_IRQ VH_INTC_INT_NUM_CASCADED_INTERRUPT_1 /* Event inputs bank 1 - ID 35/bit 3 */ |
195 | static unsigned int netcard_portlist[] __initdata = {CIRRUS_DEFAULT_BASE, 0}; | 195 | static unsigned int netcard_portlist[] __used __initdata = {CIRRUS_DEFAULT_BASE, 0}; |
196 | static unsigned int cs8900_irq_map[] = {CIRRUS_DEFAULT_IRQ, 0, 0, 0}; | 196 | static unsigned int cs8900_irq_map[] = {CIRRUS_DEFAULT_IRQ, 0, 0, 0}; |
197 | #else | 197 | #else |
198 | static unsigned int netcard_portlist[] __initdata = | 198 | static unsigned int netcard_portlist[] __used __initdata = |
199 | { 0x300, 0x320, 0x340, 0x360, 0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0, 0}; | 199 | { 0x300, 0x320, 0x340, 0x360, 0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0, 0}; |
200 | static unsigned int cs8900_irq_map[] = {10,11,12,5}; | 200 | static unsigned int cs8900_irq_map[] = {10,11,12,5}; |
201 | #endif | 201 | #endif |
diff --git a/drivers/net/e100.c b/drivers/net/e100.c index 36ba6dc96acc..cdf3090a1885 100644 --- a/drivers/net/e100.c +++ b/drivers/net/e100.c | |||
@@ -2782,16 +2782,13 @@ static void __devexit e100_remove(struct pci_dev *pdev) | |||
2782 | } | 2782 | } |
2783 | } | 2783 | } |
2784 | 2784 | ||
2785 | #ifdef CONFIG_PM | ||
2786 | static int e100_suspend(struct pci_dev *pdev, pm_message_t state) | 2785 | static int e100_suspend(struct pci_dev *pdev, pm_message_t state) |
2787 | { | 2786 | { |
2788 | struct net_device *netdev = pci_get_drvdata(pdev); | 2787 | struct net_device *netdev = pci_get_drvdata(pdev); |
2789 | struct nic *nic = netdev_priv(netdev); | 2788 | struct nic *nic = netdev_priv(netdev); |
2790 | 2789 | ||
2791 | if (netif_running(netdev)) | 2790 | if (netif_running(netdev)) |
2792 | napi_disable(&nic->napi); | 2791 | e100_down(nic); |
2793 | del_timer_sync(&nic->watchdog); | ||
2794 | netif_carrier_off(nic->netdev); | ||
2795 | netif_device_detach(netdev); | 2792 | netif_device_detach(netdev); |
2796 | 2793 | ||
2797 | pci_save_state(pdev); | 2794 | pci_save_state(pdev); |
@@ -2804,14 +2801,13 @@ static int e100_suspend(struct pci_dev *pdev, pm_message_t state) | |||
2804 | pci_enable_wake(pdev, PCI_D3cold, 0); | 2801 | pci_enable_wake(pdev, PCI_D3cold, 0); |
2805 | } | 2802 | } |
2806 | 2803 | ||
2807 | free_irq(pdev->irq, netdev); | ||
2808 | |||
2809 | pci_disable_device(pdev); | 2804 | pci_disable_device(pdev); |
2810 | pci_set_power_state(pdev, PCI_D3hot); | 2805 | pci_set_power_state(pdev, PCI_D3hot); |
2811 | 2806 | ||
2812 | return 0; | 2807 | return 0; |
2813 | } | 2808 | } |
2814 | 2809 | ||
2810 | #ifdef CONFIG_PM | ||
2815 | static int e100_resume(struct pci_dev *pdev) | 2811 | static int e100_resume(struct pci_dev *pdev) |
2816 | { | 2812 | { |
2817 | struct net_device *netdev = pci_get_drvdata(pdev); | 2813 | struct net_device *netdev = pci_get_drvdata(pdev); |
@@ -2832,26 +2828,7 @@ static int e100_resume(struct pci_dev *pdev) | |||
2832 | 2828 | ||
2833 | static void e100_shutdown(struct pci_dev *pdev) | 2829 | static void e100_shutdown(struct pci_dev *pdev) |
2834 | { | 2830 | { |
2835 | struct net_device *netdev = pci_get_drvdata(pdev); | 2831 | e100_suspend(pdev, PMSG_SUSPEND); |
2836 | struct nic *nic = netdev_priv(netdev); | ||
2837 | |||
2838 | if (netif_running(netdev)) | ||
2839 | napi_disable(&nic->napi); | ||
2840 | del_timer_sync(&nic->watchdog); | ||
2841 | netif_carrier_off(nic->netdev); | ||
2842 | |||
2843 | if ((nic->flags & wol_magic) | e100_asf(nic)) { | ||
2844 | pci_enable_wake(pdev, PCI_D3hot, 1); | ||
2845 | pci_enable_wake(pdev, PCI_D3cold, 1); | ||
2846 | } else { | ||
2847 | pci_enable_wake(pdev, PCI_D3hot, 0); | ||
2848 | pci_enable_wake(pdev, PCI_D3cold, 0); | ||
2849 | } | ||
2850 | |||
2851 | free_irq(pdev->irq, netdev); | ||
2852 | |||
2853 | pci_disable_device(pdev); | ||
2854 | pci_set_power_state(pdev, PCI_D3hot); | ||
2855 | } | 2832 | } |
2856 | 2833 | ||
2857 | /* ------------------ PCI Error Recovery infrastructure -------------- */ | 2834 | /* ------------------ PCI Error Recovery infrastructure -------------- */ |
diff --git a/drivers/net/e1000e/82571.c b/drivers/net/e1000e/82571.c index 3beace55b58d..7fe20310eb5f 100644 --- a/drivers/net/e1000e/82571.c +++ b/drivers/net/e1000e/82571.c | |||
@@ -438,7 +438,7 @@ static void e1000_release_nvm_82571(struct e1000_hw *hw) | |||
438 | * For non-82573 silicon, write data to EEPROM at offset using SPI interface. | 438 | * For non-82573 silicon, write data to EEPROM at offset using SPI interface. |
439 | * | 439 | * |
440 | * If e1000e_update_nvm_checksum is not called after this function, the | 440 | * If e1000e_update_nvm_checksum is not called after this function, the |
441 | * EEPROM will most likley contain an invalid checksum. | 441 | * EEPROM will most likely contain an invalid checksum. |
442 | **/ | 442 | **/ |
443 | static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, | 443 | static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, |
444 | u16 *data) | 444 | u16 *data) |
@@ -547,7 +547,7 @@ static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) | |||
547 | * poll for completion. | 547 | * poll for completion. |
548 | * | 548 | * |
549 | * If e1000e_update_nvm_checksum is not called after this function, the | 549 | * If e1000e_update_nvm_checksum is not called after this function, the |
550 | * EEPROM will most likley contain an invalid checksum. | 550 | * EEPROM will most likely contain an invalid checksum. |
551 | **/ | 551 | **/ |
552 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, | 552 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, |
553 | u16 words, u16 *data) | 553 | u16 words, u16 *data) |
@@ -1053,7 +1053,7 @@ static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) | |||
1053 | /* If SerDes loopback mode is entered, there is no form | 1053 | /* If SerDes loopback mode is entered, there is no form |
1054 | * of reset to take the adapter out of that mode. So we | 1054 | * of reset to take the adapter out of that mode. So we |
1055 | * have to explicitly take the adapter out of loopback | 1055 | * have to explicitly take the adapter out of loopback |
1056 | * mode. This prevents drivers from twidling their thumbs | 1056 | * mode. This prevents drivers from twiddling their thumbs |
1057 | * if another tool failed to take it out of loopback mode. | 1057 | * if another tool failed to take it out of loopback mode. |
1058 | */ | 1058 | */ |
1059 | ew32(SCTL, | 1059 | ew32(SCTL, |
@@ -1098,7 +1098,7 @@ static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) | |||
1098 | * e1000e_get_laa_state_82571 - Get locally administered address state | 1098 | * e1000e_get_laa_state_82571 - Get locally administered address state |
1099 | * @hw: pointer to the HW structure | 1099 | * @hw: pointer to the HW structure |
1100 | * | 1100 | * |
1101 | * Retrieve and return the current locally administed address state. | 1101 | * Retrieve and return the current locally administered address state. |
1102 | **/ | 1102 | **/ |
1103 | bool e1000e_get_laa_state_82571(struct e1000_hw *hw) | 1103 | bool e1000e_get_laa_state_82571(struct e1000_hw *hw) |
1104 | { | 1104 | { |
@@ -1113,7 +1113,7 @@ bool e1000e_get_laa_state_82571(struct e1000_hw *hw) | |||
1113 | * @hw: pointer to the HW structure | 1113 | * @hw: pointer to the HW structure |
1114 | * @state: enable/disable locally administered address | 1114 | * @state: enable/disable locally administered address |
1115 | * | 1115 | * |
1116 | * Enable/Disable the current locally administed address state. | 1116 | * Enable/Disable the current locally administers address state. |
1117 | **/ | 1117 | **/ |
1118 | void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state) | 1118 | void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state) |
1119 | { | 1119 | { |
@@ -1281,16 +1281,6 @@ static struct e1000_phy_operations e82_phy_ops_m88 = { | |||
1281 | 1281 | ||
1282 | static struct e1000_nvm_operations e82571_nvm_ops = { | 1282 | static struct e1000_nvm_operations e82571_nvm_ops = { |
1283 | .acquire_nvm = e1000_acquire_nvm_82571, | 1283 | .acquire_nvm = e1000_acquire_nvm_82571, |
1284 | .read_nvm = e1000e_read_nvm_spi, | ||
1285 | .release_nvm = e1000_release_nvm_82571, | ||
1286 | .update_nvm = e1000_update_nvm_checksum_82571, | ||
1287 | .valid_led_default = e1000_valid_led_default_82571, | ||
1288 | .validate_nvm = e1000_validate_nvm_checksum_82571, | ||
1289 | .write_nvm = e1000_write_nvm_82571, | ||
1290 | }; | ||
1291 | |||
1292 | static struct e1000_nvm_operations e82573_nvm_ops = { | ||
1293 | .acquire_nvm = e1000_acquire_nvm_82571, | ||
1294 | .read_nvm = e1000e_read_nvm_eerd, | 1284 | .read_nvm = e1000e_read_nvm_eerd, |
1295 | .release_nvm = e1000_release_nvm_82571, | 1285 | .release_nvm = e1000_release_nvm_82571, |
1296 | .update_nvm = e1000_update_nvm_checksum_82571, | 1286 | .update_nvm = e1000_update_nvm_checksum_82571, |
@@ -1355,6 +1345,6 @@ struct e1000_info e1000_82573_info = { | |||
1355 | .get_invariants = e1000_get_invariants_82571, | 1345 | .get_invariants = e1000_get_invariants_82571, |
1356 | .mac_ops = &e82571_mac_ops, | 1346 | .mac_ops = &e82571_mac_ops, |
1357 | .phy_ops = &e82_phy_ops_m88, | 1347 | .phy_ops = &e82_phy_ops_m88, |
1358 | .nvm_ops = &e82573_nvm_ops, | 1348 | .nvm_ops = &e82571_nvm_ops, |
1359 | }; | 1349 | }; |
1360 | 1350 | ||
diff --git a/drivers/net/e1000e/defines.h b/drivers/net/e1000e/defines.h index 6232c3e96689..a4f511f549f7 100644 --- a/drivers/net/e1000e/defines.h +++ b/drivers/net/e1000e/defines.h | |||
@@ -66,7 +66,7 @@ | |||
66 | #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ | 66 | #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ |
67 | 67 | ||
68 | /* Extended Device Control */ | 68 | /* Extended Device Control */ |
69 | #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ | 69 | #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Definable Pin 7 */ |
70 | #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ | 70 | #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ |
71 | #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ | 71 | #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ |
72 | #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 | 72 | #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 |
@@ -75,12 +75,12 @@ | |||
75 | #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ | 75 | #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ |
76 | #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ | 76 | #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ |
77 | 77 | ||
78 | /* Receive Decriptor bit definitions */ | 78 | /* Receive Descriptor bit definitions */ |
79 | #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ | 79 | #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ |
80 | #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ | 80 | #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ |
81 | #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ | 81 | #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ |
82 | #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ | 82 | #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ |
83 | #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */ | 83 | #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ |
84 | #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ | 84 | #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ |
85 | #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ | 85 | #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ |
86 | #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ | 86 | #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ |
@@ -223,7 +223,7 @@ | |||
223 | #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */ | 223 | #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */ |
224 | #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ | 224 | #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ |
225 | 225 | ||
226 | /* Constants used to intrepret the masked PCI-X bus speed. */ | 226 | /* Constants used to interpret the masked PCI-X bus speed. */ |
227 | 227 | ||
228 | #define HALF_DUPLEX 1 | 228 | #define HALF_DUPLEX 1 |
229 | #define FULL_DUPLEX 2 | 229 | #define FULL_DUPLEX 2 |
@@ -517,7 +517,7 @@ | |||
517 | /* PHY 1000 MII Register/Bit Definitions */ | 517 | /* PHY 1000 MII Register/Bit Definitions */ |
518 | /* PHY Registers defined by IEEE */ | 518 | /* PHY Registers defined by IEEE */ |
519 | #define PHY_CONTROL 0x00 /* Control Register */ | 519 | #define PHY_CONTROL 0x00 /* Control Register */ |
520 | #define PHY_STATUS 0x01 /* Status Regiser */ | 520 | #define PHY_STATUS 0x01 /* Status Register */ |
521 | #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ | 521 | #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ |
522 | #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ | 522 | #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ |
523 | #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ | 523 | #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ |
diff --git a/drivers/net/e1000e/e1000.h b/drivers/net/e1000e/e1000.h index 8b88c226e858..327c0620da31 100644 --- a/drivers/net/e1000e/e1000.h +++ b/drivers/net/e1000e/e1000.h | |||
@@ -42,8 +42,7 @@ | |||
42 | struct e1000_info; | 42 | struct e1000_info; |
43 | 43 | ||
44 | #define ndev_printk(level, netdev, format, arg...) \ | 44 | #define ndev_printk(level, netdev, format, arg...) \ |
45 | printk(level "%s: %s: " format, (netdev)->dev.parent->bus_id, \ | 45 | printk(level "%s: " format, (netdev)->name, ## arg) |
46 | (netdev)->name, ## arg) | ||
47 | 46 | ||
48 | #ifdef DEBUG | 47 | #ifdef DEBUG |
49 | #define ndev_dbg(netdev, format, arg...) \ | 48 | #define ndev_dbg(netdev, format, arg...) \ |
diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h index 3c5862f97dbf..916025b30fc3 100644 --- a/drivers/net/e1000e/hw.h +++ b/drivers/net/e1000e/hw.h | |||
@@ -184,7 +184,7 @@ enum e1e_registers { | |||
184 | E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */ | 184 | E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */ |
185 | E1000_ICRXOC = 0x04124, /* Irq Cause Receiver Overrun Count */ | 185 | E1000_ICRXOC = 0x04124, /* Irq Cause Receiver Overrun Count */ |
186 | E1000_RXCSUM = 0x05000, /* RX Checksum Control - RW */ | 186 | E1000_RXCSUM = 0x05000, /* RX Checksum Control - RW */ |
187 | E1000_RFCTL = 0x05008, /* Receive Filter Control*/ | 187 | E1000_RFCTL = 0x05008, /* Receive Filter Control */ |
188 | E1000_MTA = 0x05200, /* Multicast Table Array - RW Array */ | 188 | E1000_MTA = 0x05200, /* Multicast Table Array - RW Array */ |
189 | E1000_RA = 0x05400, /* Receive Address - RW Array */ | 189 | E1000_RA = 0x05400, /* Receive Address - RW Array */ |
190 | E1000_VFTA = 0x05600, /* VLAN Filter Table Array - RW Array */ | 190 | E1000_VFTA = 0x05600, /* VLAN Filter Table Array - RW Array */ |
@@ -202,7 +202,7 @@ enum e1e_registers { | |||
202 | E1000_FACTPS = 0x05B30, /* Function Active and Power State to MNG */ | 202 | E1000_FACTPS = 0x05B30, /* Function Active and Power State to MNG */ |
203 | E1000_SWSM = 0x05B50, /* SW Semaphore */ | 203 | E1000_SWSM = 0x05B50, /* SW Semaphore */ |
204 | E1000_FWSM = 0x05B54, /* FW Semaphore */ | 204 | E1000_FWSM = 0x05B54, /* FW Semaphore */ |
205 | E1000_HICR = 0x08F00, /* Host Inteface Control */ | 205 | E1000_HICR = 0x08F00, /* Host Interface Control */ |
206 | }; | 206 | }; |
207 | 207 | ||
208 | /* RSS registers */ | 208 | /* RSS registers */ |
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c index 8f8139de1f48..0ae39550768d 100644 --- a/drivers/net/e1000e/ich8lan.c +++ b/drivers/net/e1000e/ich8lan.c | |||
@@ -671,7 +671,7 @@ static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw) | |||
671 | * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY | 671 | * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY |
672 | * @hw: pointer to the HW structure | 672 | * @hw: pointer to the HW structure |
673 | * | 673 | * |
674 | * Polarity is determined on the polarity reveral feature being enabled. | 674 | * Polarity is determined on the polarity reversal feature being enabled. |
675 | * This function is only called by other family-specific | 675 | * This function is only called by other family-specific |
676 | * routines. | 676 | * routines. |
677 | **/ | 677 | **/ |
@@ -947,7 +947,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) | |||
947 | /* Either we should have a hardware SPI cycle in progress | 947 | /* Either we should have a hardware SPI cycle in progress |
948 | * bit to check against, in order to start a new cycle or | 948 | * bit to check against, in order to start a new cycle or |
949 | * FDONE bit should be changed in the hardware so that it | 949 | * FDONE bit should be changed in the hardware so that it |
950 | * is 1 after harware reset, which can then be used as an | 950 | * is 1 after hardware reset, which can then be used as an |
951 | * indication whether a cycle is in progress or has been | 951 | * indication whether a cycle is in progress or has been |
952 | * completed. | 952 | * completed. |
953 | */ | 953 | */ |
@@ -1155,7 +1155,7 @@ static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, | |||
1155 | * which writes the checksum to the shadow ram. The changes in the shadow | 1155 | * which writes the checksum to the shadow ram. The changes in the shadow |
1156 | * ram are then committed to the EEPROM by processing each bank at a time | 1156 | * ram are then committed to the EEPROM by processing each bank at a time |
1157 | * checking for the modified bit and writing only the pending changes. | 1157 | * checking for the modified bit and writing only the pending changes. |
1158 | * After a succesful commit, the shadow ram is cleared and is ready for | 1158 | * After a successful commit, the shadow ram is cleared and is ready for |
1159 | * future writes. | 1159 | * future writes. |
1160 | **/ | 1160 | **/ |
1161 | static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) | 1161 | static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) |
@@ -1680,7 +1680,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) | |||
1680 | * - initialize LED identification | 1680 | * - initialize LED identification |
1681 | * - setup receive address registers | 1681 | * - setup receive address registers |
1682 | * - setup flow control | 1682 | * - setup flow control |
1683 | * - setup transmit discriptors | 1683 | * - setup transmit descriptors |
1684 | * - clear statistics | 1684 | * - clear statistics |
1685 | **/ | 1685 | **/ |
1686 | static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) | 1686 | static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) |
@@ -1961,7 +1961,7 @@ static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) | |||
1961 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); | 1961 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); |
1962 | ew32(PHY_CTRL, phy_ctrl); | 1962 | ew32(PHY_CTRL, phy_ctrl); |
1963 | 1963 | ||
1964 | /* Call gig speed drop workaround on Giga disable before accessing | 1964 | /* Call gig speed drop workaround on Gig disable before accessing |
1965 | * any PHY registers */ | 1965 | * any PHY registers */ |
1966 | e1000e_gig_downshift_workaround_ich8lan(hw); | 1966 | e1000e_gig_downshift_workaround_ich8lan(hw); |
1967 | 1967 | ||
@@ -1972,7 +1972,7 @@ static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) | |||
1972 | /** | 1972 | /** |
1973 | * e1000_set_kmrn_lock_loss_workaound_ich8lan - Set Kumeran workaround state | 1973 | * e1000_set_kmrn_lock_loss_workaound_ich8lan - Set Kumeran workaround state |
1974 | * @hw: pointer to the HW structure | 1974 | * @hw: pointer to the HW structure |
1975 | * @state: boolean value used to set the current Kumaran workaround state | 1975 | * @state: boolean value used to set the current Kumeran workaround state |
1976 | * | 1976 | * |
1977 | * If ICH8, set the current Kumeran workaround state (enabled - TRUE | 1977 | * If ICH8, set the current Kumeran workaround state (enabled - TRUE |
1978 | * /disabled - FALSE). | 1978 | * /disabled - FALSE). |
@@ -2017,7 +2017,7 @@ void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) | |||
2017 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); | 2017 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); |
2018 | ew32(PHY_CTRL, reg); | 2018 | ew32(PHY_CTRL, reg); |
2019 | 2019 | ||
2020 | /* Call gig speed drop workaround on Giga disable before | 2020 | /* Call gig speed drop workaround on Gig disable before |
2021 | * accessing any PHY registers */ | 2021 | * accessing any PHY registers */ |
2022 | if (hw->mac.type == e1000_ich8lan) | 2022 | if (hw->mac.type == e1000_ich8lan) |
2023 | e1000e_gig_downshift_workaround_ich8lan(hw); | 2023 | e1000e_gig_downshift_workaround_ich8lan(hw); |
@@ -2045,7 +2045,7 @@ void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) | |||
2045 | * @hw: pointer to the HW structure | 2045 | * @hw: pointer to the HW structure |
2046 | * | 2046 | * |
2047 | * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), | 2047 | * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), |
2048 | * LPLU, Giga disable, MDIC PHY reset): | 2048 | * LPLU, Gig disable, MDIC PHY reset): |
2049 | * 1) Set Kumeran Near-end loopback | 2049 | * 1) Set Kumeran Near-end loopback |
2050 | * 2) Clear Kumeran Near-end loopback | 2050 | * 2) Clear Kumeran Near-end loopback |
2051 | * Should only be called for ICH8[m] devices with IGP_3 Phy. | 2051 | * Should only be called for ICH8[m] devices with IGP_3 Phy. |
@@ -2089,10 +2089,10 @@ static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) | |||
2089 | } | 2089 | } |
2090 | 2090 | ||
2091 | /** | 2091 | /** |
2092 | * e1000_led_on_ich8lan - Turn LED's on | 2092 | * e1000_led_on_ich8lan - Turn LEDs on |
2093 | * @hw: pointer to the HW structure | 2093 | * @hw: pointer to the HW structure |
2094 | * | 2094 | * |
2095 | * Turn on the LED's. | 2095 | * Turn on the LEDs. |
2096 | **/ | 2096 | **/ |
2097 | static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) | 2097 | static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) |
2098 | { | 2098 | { |
@@ -2105,10 +2105,10 @@ static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) | |||
2105 | } | 2105 | } |
2106 | 2106 | ||
2107 | /** | 2107 | /** |
2108 | * e1000_led_off_ich8lan - Turn LED's off | 2108 | * e1000_led_off_ich8lan - Turn LEDs off |
2109 | * @hw: pointer to the HW structure | 2109 | * @hw: pointer to the HW structure |
2110 | * | 2110 | * |
2111 | * Turn off the LED's. | 2111 | * Turn off the LEDs. |
2112 | **/ | 2112 | **/ |
2113 | static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) | 2113 | static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) |
2114 | { | 2114 | { |
diff --git a/drivers/net/e1000e/lib.c b/drivers/net/e1000e/lib.c index 16f35fadb74b..95f75a43c9f9 100644 --- a/drivers/net/e1000e/lib.c +++ b/drivers/net/e1000e/lib.c | |||
@@ -589,9 +589,6 @@ static s32 e1000_set_default_fc_generic(struct e1000_hw *hw) | |||
589 | s32 ret_val; | 589 | s32 ret_val; |
590 | u16 nvm_data; | 590 | u16 nvm_data; |
591 | 591 | ||
592 | if (mac->fc != e1000_fc_default) | ||
593 | return 0; | ||
594 | |||
595 | /* Read and store word 0x0F of the EEPROM. This word contains bits | 592 | /* Read and store word 0x0F of the EEPROM. This word contains bits |
596 | * that determine the hardware's default PAUSE (flow control) mode, | 593 | * that determine the hardware's default PAUSE (flow control) mode, |
597 | * a bit that determines whether the HW defaults to enabling or | 594 | * a bit that determines whether the HW defaults to enabling or |
@@ -1107,34 +1104,13 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw) | |||
1107 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { | 1104 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { |
1108 | mac->fc = e1000_fc_rx_pause; | 1105 | mac->fc = e1000_fc_rx_pause; |
1109 | hw_dbg(hw, "Flow Control = RX PAUSE frames only.\r\n"); | 1106 | hw_dbg(hw, "Flow Control = RX PAUSE frames only.\r\n"); |
1110 | } | 1107 | } else { |
1111 | /* Per the IEEE spec, at this point flow control should be | 1108 | /* |
1112 | * disabled. However, we want to consider that we could | 1109 | * Per the IEEE spec, at this point flow control |
1113 | * be connected to a legacy switch that doesn't advertise | 1110 | * should be disabled. |
1114 | * desired flow control, but can be forced on the link | 1111 | */ |
1115 | * partner. So if we advertised no flow control, that is | ||
1116 | * what we will resolve to. If we advertised some kind of | ||
1117 | * receive capability (Rx Pause Only or Full Flow Control) | ||
1118 | * and the link partner advertised none, we will configure | ||
1119 | * ourselves to enable Rx Flow Control only. We can do | ||
1120 | * this safely for two reasons: If the link partner really | ||
1121 | * didn't want flow control enabled, and we enable Rx, no | ||
1122 | * harm done since we won't be receiving any PAUSE frames | ||
1123 | * anyway. If the intent on the link partner was to have | ||
1124 | * flow control enabled, then by us enabling RX only, we | ||
1125 | * can at least receive pause frames and process them. | ||
1126 | * This is a good idea because in most cases, since we are | ||
1127 | * predominantly a server NIC, more times than not we will | ||
1128 | * be asked to delay transmission of packets than asking | ||
1129 | * our link partner to pause transmission of frames. | ||
1130 | */ | ||
1131 | else if ((mac->original_fc == e1000_fc_none) || | ||
1132 | (mac->original_fc == e1000_fc_tx_pause)) { | ||
1133 | mac->fc = e1000_fc_none; | 1112 | mac->fc = e1000_fc_none; |
1134 | hw_dbg(hw, "Flow Control = NONE.\r\n"); | 1113 | hw_dbg(hw, "Flow Control = NONE.\r\n"); |
1135 | } else { | ||
1136 | mac->fc = e1000_fc_rx_pause; | ||
1137 | hw_dbg(hw, "Flow Control = RX PAUSE frames only.\r\n"); | ||
1138 | } | 1114 | } |
1139 | 1115 | ||
1140 | /* Now we need to do one last check... If we auto- | 1116 | /* Now we need to do one last check... If we auto- |
@@ -1164,7 +1140,7 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw) | |||
1164 | } | 1140 | } |
1165 | 1141 | ||
1166 | /** | 1142 | /** |
1167 | * e1000e_get_speed_and_duplex_copper - Retreive current speed/duplex | 1143 | * e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex |
1168 | * @hw: pointer to the HW structure | 1144 | * @hw: pointer to the HW structure |
1169 | * @speed: stores the current speed | 1145 | * @speed: stores the current speed |
1170 | * @duplex: stores the current duplex | 1146 | * @duplex: stores the current duplex |
@@ -1200,7 +1176,7 @@ s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *dup | |||
1200 | } | 1176 | } |
1201 | 1177 | ||
1202 | /** | 1178 | /** |
1203 | * e1000e_get_speed_and_duplex_fiber_serdes - Retreive current speed/duplex | 1179 | * e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex |
1204 | * @hw: pointer to the HW structure | 1180 | * @hw: pointer to the HW structure |
1205 | * @speed: stores the current speed | 1181 | * @speed: stores the current speed |
1206 | * @duplex: stores the current duplex | 1182 | * @duplex: stores the current duplex |
@@ -1410,7 +1386,7 @@ s32 e1000e_cleanup_led_generic(struct e1000_hw *hw) | |||
1410 | * e1000e_blink_led - Blink LED | 1386 | * e1000e_blink_led - Blink LED |
1411 | * @hw: pointer to the HW structure | 1387 | * @hw: pointer to the HW structure |
1412 | * | 1388 | * |
1413 | * Blink the led's which are set to be on. | 1389 | * Blink the LEDs which are set to be on. |
1414 | **/ | 1390 | **/ |
1415 | s32 e1000e_blink_led(struct e1000_hw *hw) | 1391 | s32 e1000e_blink_led(struct e1000_hw *hw) |
1416 | { | 1392 | { |
@@ -1515,7 +1491,7 @@ void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop) | |||
1515 | * @hw: pointer to the HW structure | 1491 | * @hw: pointer to the HW structure |
1516 | * | 1492 | * |
1517 | * Returns 0 if successful, else returns -10 | 1493 | * Returns 0 if successful, else returns -10 |
1518 | * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not casued | 1494 | * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused |
1519 | * the master requests to be disabled. | 1495 | * the master requests to be disabled. |
1520 | * | 1496 | * |
1521 | * Disables PCI-Express master access and verifies there are no pending | 1497 | * Disables PCI-Express master access and verifies there are no pending |
@@ -1876,7 +1852,7 @@ static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw) | |||
1876 | } | 1852 | } |
1877 | 1853 | ||
1878 | /** | 1854 | /** |
1879 | * e1000e_read_nvm_spi - Read EEPROM's using SPI | 1855 | * e1000e_read_nvm_spi - Reads EEPROM using SPI |
1880 | * @hw: pointer to the HW structure | 1856 | * @hw: pointer to the HW structure |
1881 | * @offset: offset of word in the EEPROM to read | 1857 | * @offset: offset of word in the EEPROM to read |
1882 | * @words: number of words to read | 1858 | * @words: number of words to read |
@@ -1980,7 +1956,7 @@ s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) | |||
1980 | * Writes data to EEPROM at offset using SPI interface. | 1956 | * Writes data to EEPROM at offset using SPI interface. |
1981 | * | 1957 | * |
1982 | * If e1000e_update_nvm_checksum is not called after this function , the | 1958 | * If e1000e_update_nvm_checksum is not called after this function , the |
1983 | * EEPROM will most likley contain an invalid checksum. | 1959 | * EEPROM will most likely contain an invalid checksum. |
1984 | **/ | 1960 | **/ |
1985 | s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) | 1961 | s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) |
1986 | { | 1962 | { |
@@ -2222,7 +2198,7 @@ static u8 e1000_calculate_checksum(u8 *buffer, u32 length) | |||
2222 | * | 2198 | * |
2223 | * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND | 2199 | * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND |
2224 | * | 2200 | * |
2225 | * This function checks whether the HOST IF is enabled for command operaton | 2201 | * This function checks whether the HOST IF is enabled for command operation |
2226 | * and also checks whether the previous command is completed. It busy waits | 2202 | * and also checks whether the previous command is completed. It busy waits |
2227 | * in case of previous command is not completed. | 2203 | * in case of previous command is not completed. |
2228 | **/ | 2204 | **/ |
@@ -2254,7 +2230,7 @@ static s32 e1000_mng_enable_host_if(struct e1000_hw *hw) | |||
2254 | } | 2230 | } |
2255 | 2231 | ||
2256 | /** | 2232 | /** |
2257 | * e1000e_check_mng_mode - check managament mode | 2233 | * e1000e_check_mng_mode - check management mode |
2258 | * @hw: pointer to the HW structure | 2234 | * @hw: pointer to the HW structure |
2259 | * | 2235 | * |
2260 | * Reads the firmware semaphore register and returns true (>0) if | 2236 | * Reads the firmware semaphore register and returns true (>0) if |
diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c index 3031d6d16247..fc5c63f4f578 100644 --- a/drivers/net/e1000e/netdev.c +++ b/drivers/net/e1000e/netdev.c | |||
@@ -1006,7 +1006,7 @@ static void e1000_irq_enable(struct e1000_adapter *adapter) | |||
1006 | * e1000_get_hw_control - get control of the h/w from f/w | 1006 | * e1000_get_hw_control - get control of the h/w from f/w |
1007 | * @adapter: address of board private structure | 1007 | * @adapter: address of board private structure |
1008 | * | 1008 | * |
1009 | * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit. | 1009 | * e1000_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit. |
1010 | * For ASF and Pass Through versions of f/w this means that | 1010 | * For ASF and Pass Through versions of f/w this means that |
1011 | * the driver is loaded. For AMT version (only with 82573) | 1011 | * the driver is loaded. For AMT version (only with 82573) |
1012 | * of the f/w this means that the network i/f is open. | 1012 | * of the f/w this means that the network i/f is open. |
@@ -1032,7 +1032,7 @@ static void e1000_get_hw_control(struct e1000_adapter *adapter) | |||
1032 | * e1000_release_hw_control - release control of the h/w to f/w | 1032 | * e1000_release_hw_control - release control of the h/w to f/w |
1033 | * @adapter: address of board private structure | 1033 | * @adapter: address of board private structure |
1034 | * | 1034 | * |
1035 | * e1000_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. | 1035 | * e1000_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit. |
1036 | * For ASF and Pass Through versions of f/w this means that the | 1036 | * For ASF and Pass Through versions of f/w this means that the |
1037 | * driver is no longer loaded. For AMT version (only with 82573) i | 1037 | * driver is no longer loaded. For AMT version (only with 82573) i |
1038 | * of the f/w this means that the network i/f is closed. | 1038 | * of the f/w this means that the network i/f is closed. |
@@ -1241,6 +1241,11 @@ void e1000e_free_rx_resources(struct e1000_adapter *adapter) | |||
1241 | 1241 | ||
1242 | /** | 1242 | /** |
1243 | * e1000_update_itr - update the dynamic ITR value based on statistics | 1243 | * e1000_update_itr - update the dynamic ITR value based on statistics |
1244 | * @adapter: pointer to adapter | ||
1245 | * @itr_setting: current adapter->itr | ||
1246 | * @packets: the number of packets during this measurement interval | ||
1247 | * @bytes: the number of bytes during this measurement interval | ||
1248 | * | ||
1244 | * Stores a new ITR value based on packets and byte | 1249 | * Stores a new ITR value based on packets and byte |
1245 | * counts during the last interrupt. The advantage of per interrupt | 1250 | * counts during the last interrupt. The advantage of per interrupt |
1246 | * computation is faster updates and more accurate ITR for the current | 1251 | * computation is faster updates and more accurate ITR for the current |
@@ -1250,10 +1255,6 @@ void e1000e_free_rx_resources(struct e1000_adapter *adapter) | |||
1250 | * while increasing bulk throughput. | 1255 | * while increasing bulk throughput. |
1251 | * this functionality is controlled by the InterruptThrottleRate module | 1256 | * this functionality is controlled by the InterruptThrottleRate module |
1252 | * parameter (see e1000_param.c) | 1257 | * parameter (see e1000_param.c) |
1253 | * @adapter: pointer to adapter | ||
1254 | * @itr_setting: current adapter->itr | ||
1255 | * @packets: the number of packets during this measurement interval | ||
1256 | * @bytes: the number of bytes during this measurement interval | ||
1257 | **/ | 1258 | **/ |
1258 | static unsigned int e1000_update_itr(struct e1000_adapter *adapter, | 1259 | static unsigned int e1000_update_itr(struct e1000_adapter *adapter, |
1259 | u16 itr_setting, int packets, | 1260 | u16 itr_setting, int packets, |
@@ -1366,6 +1367,7 @@ set_itr_now: | |||
1366 | /** | 1367 | /** |
1367 | * e1000_clean - NAPI Rx polling callback | 1368 | * e1000_clean - NAPI Rx polling callback |
1368 | * @adapter: board private structure | 1369 | * @adapter: board private structure |
1370 | * @budget: amount of packets driver is allowed to process this poll | ||
1369 | **/ | 1371 | **/ |
1370 | static int e1000_clean(struct napi_struct *napi, int budget) | 1372 | static int e1000_clean(struct napi_struct *napi, int budget) |
1371 | { | 1373 | { |
@@ -2000,7 +2002,7 @@ static void e1000_power_down_phy(struct e1000_adapter *adapter) | |||
2000 | e1000_check_reset_block(hw)) | 2002 | e1000_check_reset_block(hw)) |
2001 | return; | 2003 | return; |
2002 | 2004 | ||
2003 | /* managebility (AMT) is enabled */ | 2005 | /* manageability (AMT) is enabled */ |
2004 | if (er32(MANC) & E1000_MANC_SMBUS_EN) | 2006 | if (er32(MANC) & E1000_MANC_SMBUS_EN) |
2005 | return; | 2007 | return; |
2006 | 2008 | ||
@@ -3488,7 +3490,6 @@ static int e1000_suspend(struct pci_dev *pdev, pm_message_t state) | |||
3488 | static void e1000e_disable_l1aspm(struct pci_dev *pdev) | 3490 | static void e1000e_disable_l1aspm(struct pci_dev *pdev) |
3489 | { | 3491 | { |
3490 | int pos; | 3492 | int pos; |
3491 | u32 cap; | ||
3492 | u16 val; | 3493 | u16 val; |
3493 | 3494 | ||
3494 | /* | 3495 | /* |
@@ -3503,7 +3504,6 @@ static void e1000e_disable_l1aspm(struct pci_dev *pdev) | |||
3503 | * active. | 3504 | * active. |
3504 | */ | 3505 | */ |
3505 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); | 3506 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); |
3506 | pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, &cap); | ||
3507 | pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &val); | 3507 | pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &val); |
3508 | if (val & 0x2) { | 3508 | if (val & 0x2) { |
3509 | dev_warn(&pdev->dev, "Disabling L1 ASPM\n"); | 3509 | dev_warn(&pdev->dev, "Disabling L1 ASPM\n"); |
diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c index fc6fee112f1c..dab3c468a768 100644 --- a/drivers/net/e1000e/phy.c +++ b/drivers/net/e1000e/phy.c | |||
@@ -121,7 +121,7 @@ s32 e1000e_phy_reset_dsp(struct e1000_hw *hw) | |||
121 | * @offset: register offset to be read | 121 | * @offset: register offset to be read |
122 | * @data: pointer to the read data | 122 | * @data: pointer to the read data |
123 | * | 123 | * |
124 | * Reads the MDI control regsiter in the PHY at offset and stores the | 124 | * Reads the MDI control register in the PHY at offset and stores the |
125 | * information read to data. | 125 | * information read to data. |
126 | **/ | 126 | **/ |
127 | static s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) | 127 | static s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) |
@@ -1172,7 +1172,7 @@ s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active) | |||
1172 | } | 1172 | } |
1173 | 1173 | ||
1174 | /** | 1174 | /** |
1175 | * e1000e_check_downshift - Checks whether a downshift in speed occured | 1175 | * e1000e_check_downshift - Checks whether a downshift in speed occurred |
1176 | * @hw: pointer to the HW structure | 1176 | * @hw: pointer to the HW structure |
1177 | * | 1177 | * |
1178 | * Success returns 0, Failure returns 1 | 1178 | * Success returns 0, Failure returns 1 |
@@ -1388,8 +1388,8 @@ s32 e1000e_get_cable_length_m88(struct e1000_hw *hw) | |||
1388 | * | 1388 | * |
1389 | * The automatic gain control (agc) normalizes the amplitude of the | 1389 | * The automatic gain control (agc) normalizes the amplitude of the |
1390 | * received signal, adjusting for the attenuation produced by the | 1390 | * received signal, adjusting for the attenuation produced by the |
1391 | * cable. By reading the AGC registers, which reperesent the | 1391 | * cable. By reading the AGC registers, which represent the |
1392 | * cobination of course and fine gain value, the value can be put | 1392 | * combination of course and fine gain value, the value can be put |
1393 | * into a lookup table to obtain the approximate cable length | 1393 | * into a lookup table to obtain the approximate cable length |
1394 | * for each channel. | 1394 | * for each channel. |
1395 | **/ | 1395 | **/ |
@@ -1619,7 +1619,7 @@ s32 e1000e_phy_sw_reset(struct e1000_hw *hw) | |||
1619 | * Verify the reset block is not blocking us from resetting. Acquire | 1619 | * Verify the reset block is not blocking us from resetting. Acquire |
1620 | * semaphore (if necessary) and read/set/write the device control reset | 1620 | * semaphore (if necessary) and read/set/write the device control reset |
1621 | * bit in the PHY. Wait the appropriate delay time for the device to | 1621 | * bit in the PHY. Wait the appropriate delay time for the device to |
1622 | * reset and relase the semaphore (if necessary). | 1622 | * reset and release the semaphore (if necessary). |
1623 | **/ | 1623 | **/ |
1624 | s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw) | 1624 | s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw) |
1625 | { | 1625 | { |
diff --git a/drivers/net/ehea/ehea.h b/drivers/net/ehea/ehea.h index 88fb53eba715..7c4ead35cfa2 100644 --- a/drivers/net/ehea/ehea.h +++ b/drivers/net/ehea/ehea.h | |||
@@ -40,7 +40,7 @@ | |||
40 | #include <asm/io.h> | 40 | #include <asm/io.h> |
41 | 41 | ||
42 | #define DRV_NAME "ehea" | 42 | #define DRV_NAME "ehea" |
43 | #define DRV_VERSION "EHEA_0083" | 43 | #define DRV_VERSION "EHEA_0087" |
44 | 44 | ||
45 | /* eHEA capability flags */ | 45 | /* eHEA capability flags */ |
46 | #define DLPAR_PORT_ADD_REM 1 | 46 | #define DLPAR_PORT_ADD_REM 1 |
@@ -386,6 +386,13 @@ struct ehea_port_res { | |||
386 | 386 | ||
387 | 387 | ||
388 | #define EHEA_MAX_PORTS 16 | 388 | #define EHEA_MAX_PORTS 16 |
389 | |||
390 | #define EHEA_NUM_PORTRES_FW_HANDLES 6 /* QP handle, SendCQ handle, | ||
391 | RecvCQ handle, EQ handle, | ||
392 | SendMR handle, RecvMR handle */ | ||
393 | #define EHEA_NUM_PORT_FW_HANDLES 1 /* EQ handle */ | ||
394 | #define EHEA_NUM_ADAPTER_FW_HANDLES 2 /* MR handle, NEQ handle */ | ||
395 | |||
389 | struct ehea_adapter { | 396 | struct ehea_adapter { |
390 | u64 handle; | 397 | u64 handle; |
391 | struct of_device *ofdev; | 398 | struct of_device *ofdev; |
@@ -405,6 +412,31 @@ struct ehea_mc_list { | |||
405 | u64 macaddr; | 412 | u64 macaddr; |
406 | }; | 413 | }; |
407 | 414 | ||
415 | /* kdump support */ | ||
416 | struct ehea_fw_handle_entry { | ||
417 | u64 adh; /* Adapter Handle */ | ||
418 | u64 fwh; /* Firmware Handle */ | ||
419 | }; | ||
420 | |||
421 | struct ehea_fw_handle_array { | ||
422 | struct ehea_fw_handle_entry *arr; | ||
423 | int num_entries; | ||
424 | struct semaphore lock; | ||
425 | }; | ||
426 | |||
427 | struct ehea_bcmc_reg_entry { | ||
428 | u64 adh; /* Adapter Handle */ | ||
429 | u32 port_id; /* Logical Port Id */ | ||
430 | u8 reg_type; /* Registration Type */ | ||
431 | u64 macaddr; | ||
432 | }; | ||
433 | |||
434 | struct ehea_bcmc_reg_array { | ||
435 | struct ehea_bcmc_reg_entry *arr; | ||
436 | int num_entries; | ||
437 | struct semaphore lock; | ||
438 | }; | ||
439 | |||
408 | #define EHEA_PORT_UP 1 | 440 | #define EHEA_PORT_UP 1 |
409 | #define EHEA_PORT_DOWN 0 | 441 | #define EHEA_PORT_DOWN 0 |
410 | #define EHEA_PHY_LINK_UP 1 | 442 | #define EHEA_PHY_LINK_UP 1 |
diff --git a/drivers/net/ehea/ehea_main.c b/drivers/net/ehea/ehea_main.c index c051c7e09b9a..21af674b764e 100644 --- a/drivers/net/ehea/ehea_main.c +++ b/drivers/net/ehea/ehea_main.c | |||
@@ -35,6 +35,7 @@ | |||
35 | #include <linux/if_ether.h> | 35 | #include <linux/if_ether.h> |
36 | #include <linux/notifier.h> | 36 | #include <linux/notifier.h> |
37 | #include <linux/reboot.h> | 37 | #include <linux/reboot.h> |
38 | #include <asm/kexec.h> | ||
38 | 39 | ||
39 | #include <net/ip.h> | 40 | #include <net/ip.h> |
40 | 41 | ||
@@ -98,8 +99,10 @@ static int port_name_cnt; | |||
98 | static LIST_HEAD(adapter_list); | 99 | static LIST_HEAD(adapter_list); |
99 | u64 ehea_driver_flags; | 100 | u64 ehea_driver_flags; |
100 | struct work_struct ehea_rereg_mr_task; | 101 | struct work_struct ehea_rereg_mr_task; |
101 | |||
102 | struct semaphore dlpar_mem_lock; | 102 | struct semaphore dlpar_mem_lock; |
103 | struct ehea_fw_handle_array ehea_fw_handles; | ||
104 | struct ehea_bcmc_reg_array ehea_bcmc_regs; | ||
105 | |||
103 | 106 | ||
104 | static int __devinit ehea_probe_adapter(struct of_device *dev, | 107 | static int __devinit ehea_probe_adapter(struct of_device *dev, |
105 | const struct of_device_id *id); | 108 | const struct of_device_id *id); |
@@ -132,6 +135,160 @@ void ehea_dump(void *adr, int len, char *msg) | |||
132 | } | 135 | } |
133 | } | 136 | } |
134 | 137 | ||
138 | static void ehea_update_firmware_handles(void) | ||
139 | { | ||
140 | struct ehea_fw_handle_entry *arr = NULL; | ||
141 | struct ehea_adapter *adapter; | ||
142 | int num_adapters = 0; | ||
143 | int num_ports = 0; | ||
144 | int num_portres = 0; | ||
145 | int i = 0; | ||
146 | int num_fw_handles, k, l; | ||
147 | |||
148 | /* Determine number of handles */ | ||
149 | list_for_each_entry(adapter, &adapter_list, list) { | ||
150 | num_adapters++; | ||
151 | |||
152 | for (k = 0; k < EHEA_MAX_PORTS; k++) { | ||
153 | struct ehea_port *port = adapter->port[k]; | ||
154 | |||
155 | if (!port || (port->state != EHEA_PORT_UP)) | ||
156 | continue; | ||
157 | |||
158 | num_ports++; | ||
159 | num_portres += port->num_def_qps + port->num_add_tx_qps; | ||
160 | } | ||
161 | } | ||
162 | |||
163 | num_fw_handles = num_adapters * EHEA_NUM_ADAPTER_FW_HANDLES + | ||
164 | num_ports * EHEA_NUM_PORT_FW_HANDLES + | ||
165 | num_portres * EHEA_NUM_PORTRES_FW_HANDLES; | ||
166 | |||
167 | if (num_fw_handles) { | ||
168 | arr = kzalloc(num_fw_handles * sizeof(*arr), GFP_KERNEL); | ||
169 | if (!arr) | ||
170 | return; /* Keep the existing array */ | ||
171 | } else | ||
172 | goto out_update; | ||
173 | |||
174 | list_for_each_entry(adapter, &adapter_list, list) { | ||
175 | for (k = 0; k < EHEA_MAX_PORTS; k++) { | ||
176 | struct ehea_port *port = adapter->port[k]; | ||
177 | |||
178 | if (!port || (port->state != EHEA_PORT_UP)) | ||
179 | continue; | ||
180 | |||
181 | for (l = 0; | ||
182 | l < port->num_def_qps + port->num_add_tx_qps; | ||
183 | l++) { | ||
184 | struct ehea_port_res *pr = &port->port_res[l]; | ||
185 | |||
186 | arr[i].adh = adapter->handle; | ||
187 | arr[i++].fwh = pr->qp->fw_handle; | ||
188 | arr[i].adh = adapter->handle; | ||
189 | arr[i++].fwh = pr->send_cq->fw_handle; | ||
190 | arr[i].adh = adapter->handle; | ||
191 | arr[i++].fwh = pr->recv_cq->fw_handle; | ||
192 | arr[i].adh = adapter->handle; | ||
193 | arr[i++].fwh = pr->eq->fw_handle; | ||
194 | arr[i].adh = adapter->handle; | ||
195 | arr[i++].fwh = pr->send_mr.handle; | ||
196 | arr[i].adh = adapter->handle; | ||
197 | arr[i++].fwh = pr->recv_mr.handle; | ||
198 | } | ||
199 | arr[i].adh = adapter->handle; | ||
200 | arr[i++].fwh = port->qp_eq->fw_handle; | ||
201 | } | ||
202 | |||
203 | arr[i].adh = adapter->handle; | ||
204 | arr[i++].fwh = adapter->neq->fw_handle; | ||
205 | |||
206 | if (adapter->mr.handle) { | ||
207 | arr[i].adh = adapter->handle; | ||
208 | arr[i++].fwh = adapter->mr.handle; | ||
209 | } | ||
210 | } | ||
211 | |||
212 | out_update: | ||
213 | kfree(ehea_fw_handles.arr); | ||
214 | ehea_fw_handles.arr = arr; | ||
215 | ehea_fw_handles.num_entries = i; | ||
216 | } | ||
217 | |||
218 | static void ehea_update_bcmc_registrations(void) | ||
219 | { | ||
220 | struct ehea_bcmc_reg_entry *arr = NULL; | ||
221 | struct ehea_adapter *adapter; | ||
222 | struct ehea_mc_list *mc_entry; | ||
223 | int num_registrations = 0; | ||
224 | int i = 0; | ||
225 | int k; | ||
226 | |||
227 | /* Determine number of registrations */ | ||
228 | list_for_each_entry(adapter, &adapter_list, list) | ||
229 | for (k = 0; k < EHEA_MAX_PORTS; k++) { | ||
230 | struct ehea_port *port = adapter->port[k]; | ||
231 | |||
232 | if (!port || (port->state != EHEA_PORT_UP)) | ||
233 | continue; | ||
234 | |||
235 | num_registrations += 2; /* Broadcast registrations */ | ||
236 | |||
237 | list_for_each_entry(mc_entry, &port->mc_list->list,list) | ||
238 | num_registrations += 2; | ||
239 | } | ||
240 | |||
241 | if (num_registrations) { | ||
242 | arr = kzalloc(num_registrations * sizeof(*arr), GFP_KERNEL); | ||
243 | if (!arr) | ||
244 | return; /* Keep the existing array */ | ||
245 | } else | ||
246 | goto out_update; | ||
247 | |||
248 | list_for_each_entry(adapter, &adapter_list, list) { | ||
249 | for (k = 0; k < EHEA_MAX_PORTS; k++) { | ||
250 | struct ehea_port *port = adapter->port[k]; | ||
251 | |||
252 | if (!port || (port->state != EHEA_PORT_UP)) | ||
253 | continue; | ||
254 | |||
255 | arr[i].adh = adapter->handle; | ||
256 | arr[i].port_id = port->logical_port_id; | ||
257 | arr[i].reg_type = EHEA_BCMC_BROADCAST | | ||
258 | EHEA_BCMC_UNTAGGED; | ||
259 | arr[i++].macaddr = port->mac_addr; | ||
260 | |||
261 | arr[i].adh = adapter->handle; | ||
262 | arr[i].port_id = port->logical_port_id; | ||
263 | arr[i].reg_type = EHEA_BCMC_BROADCAST | | ||
264 | EHEA_BCMC_VLANID_ALL; | ||
265 | arr[i++].macaddr = port->mac_addr; | ||
266 | |||
267 | list_for_each_entry(mc_entry, | ||
268 | &port->mc_list->list, list) { | ||
269 | arr[i].adh = adapter->handle; | ||
270 | arr[i].port_id = port->logical_port_id; | ||
271 | arr[i].reg_type = EHEA_BCMC_SCOPE_ALL | | ||
272 | EHEA_BCMC_MULTICAST | | ||
273 | EHEA_BCMC_UNTAGGED; | ||
274 | arr[i++].macaddr = mc_entry->macaddr; | ||
275 | |||
276 | arr[i].adh = adapter->handle; | ||
277 | arr[i].port_id = port->logical_port_id; | ||
278 | arr[i].reg_type = EHEA_BCMC_SCOPE_ALL | | ||
279 | EHEA_BCMC_MULTICAST | | ||
280 | EHEA_BCMC_VLANID_ALL; | ||
281 | arr[i++].macaddr = mc_entry->macaddr; | ||
282 | } | ||
283 | } | ||
284 | } | ||
285 | |||
286 | out_update: | ||
287 | kfree(ehea_bcmc_regs.arr); | ||
288 | ehea_bcmc_regs.arr = arr; | ||
289 | ehea_bcmc_regs.num_entries = i; | ||
290 | } | ||
291 | |||
135 | static struct net_device_stats *ehea_get_stats(struct net_device *dev) | 292 | static struct net_device_stats *ehea_get_stats(struct net_device *dev) |
136 | { | 293 | { |
137 | struct ehea_port *port = netdev_priv(dev); | 294 | struct ehea_port *port = netdev_priv(dev); |
@@ -1601,19 +1758,25 @@ static int ehea_set_mac_addr(struct net_device *dev, void *sa) | |||
1601 | 1758 | ||
1602 | memcpy(dev->dev_addr, mac_addr->sa_data, dev->addr_len); | 1759 | memcpy(dev->dev_addr, mac_addr->sa_data, dev->addr_len); |
1603 | 1760 | ||
1761 | down(&ehea_bcmc_regs.lock); | ||
1762 | |||
1604 | /* Deregister old MAC in pHYP */ | 1763 | /* Deregister old MAC in pHYP */ |
1605 | ret = ehea_broadcast_reg_helper(port, H_DEREG_BCMC); | 1764 | ret = ehea_broadcast_reg_helper(port, H_DEREG_BCMC); |
1606 | if (ret) | 1765 | if (ret) |
1607 | goto out_free; | 1766 | goto out_upregs; |
1608 | 1767 | ||
1609 | port->mac_addr = cb0->port_mac_addr << 16; | 1768 | port->mac_addr = cb0->port_mac_addr << 16; |
1610 | 1769 | ||
1611 | /* Register new MAC in pHYP */ | 1770 | /* Register new MAC in pHYP */ |
1612 | ret = ehea_broadcast_reg_helper(port, H_REG_BCMC); | 1771 | ret = ehea_broadcast_reg_helper(port, H_REG_BCMC); |
1613 | if (ret) | 1772 | if (ret) |
1614 | goto out_free; | 1773 | goto out_upregs; |
1615 | 1774 | ||
1616 | ret = 0; | 1775 | ret = 0; |
1776 | |||
1777 | out_upregs: | ||
1778 | ehea_update_bcmc_registrations(); | ||
1779 | up(&ehea_bcmc_regs.lock); | ||
1617 | out_free: | 1780 | out_free: |
1618 | kfree(cb0); | 1781 | kfree(cb0); |
1619 | out: | 1782 | out: |
@@ -1775,9 +1938,11 @@ static void ehea_set_multicast_list(struct net_device *dev) | |||
1775 | } | 1938 | } |
1776 | ehea_promiscuous(dev, 0); | 1939 | ehea_promiscuous(dev, 0); |
1777 | 1940 | ||
1941 | down(&ehea_bcmc_regs.lock); | ||
1942 | |||
1778 | if (dev->flags & IFF_ALLMULTI) { | 1943 | if (dev->flags & IFF_ALLMULTI) { |
1779 | ehea_allmulti(dev, 1); | 1944 | ehea_allmulti(dev, 1); |
1780 | return; | 1945 | goto out; |
1781 | } | 1946 | } |
1782 | ehea_allmulti(dev, 0); | 1947 | ehea_allmulti(dev, 0); |
1783 | 1948 | ||
@@ -1803,6 +1968,8 @@ static void ehea_set_multicast_list(struct net_device *dev) | |||
1803 | 1968 | ||
1804 | } | 1969 | } |
1805 | out: | 1970 | out: |
1971 | ehea_update_bcmc_registrations(); | ||
1972 | up(&ehea_bcmc_regs.lock); | ||
1806 | return; | 1973 | return; |
1807 | } | 1974 | } |
1808 | 1975 | ||
@@ -2285,6 +2452,8 @@ static int ehea_up(struct net_device *dev) | |||
2285 | if (port->state == EHEA_PORT_UP) | 2452 | if (port->state == EHEA_PORT_UP) |
2286 | return 0; | 2453 | return 0; |
2287 | 2454 | ||
2455 | down(&ehea_fw_handles.lock); | ||
2456 | |||
2288 | ret = ehea_port_res_setup(port, port->num_def_qps, | 2457 | ret = ehea_port_res_setup(port, port->num_def_qps, |
2289 | port->num_add_tx_qps); | 2458 | port->num_add_tx_qps); |
2290 | if (ret) { | 2459 | if (ret) { |
@@ -2321,8 +2490,17 @@ static int ehea_up(struct net_device *dev) | |||
2321 | } | 2490 | } |
2322 | } | 2491 | } |
2323 | 2492 | ||
2324 | ret = 0; | 2493 | down(&ehea_bcmc_regs.lock); |
2494 | |||
2495 | ret = ehea_broadcast_reg_helper(port, H_REG_BCMC); | ||
2496 | if (ret) { | ||
2497 | ret = -EIO; | ||
2498 | goto out_free_irqs; | ||
2499 | } | ||
2500 | |||
2325 | port->state = EHEA_PORT_UP; | 2501 | port->state = EHEA_PORT_UP; |
2502 | |||
2503 | ret = 0; | ||
2326 | goto out; | 2504 | goto out; |
2327 | 2505 | ||
2328 | out_free_irqs: | 2506 | out_free_irqs: |
@@ -2334,6 +2512,12 @@ out: | |||
2334 | if (ret) | 2512 | if (ret) |
2335 | ehea_info("Failed starting %s. ret=%i", dev->name, ret); | 2513 | ehea_info("Failed starting %s. ret=%i", dev->name, ret); |
2336 | 2514 | ||
2515 | ehea_update_bcmc_registrations(); | ||
2516 | up(&ehea_bcmc_regs.lock); | ||
2517 | |||
2518 | ehea_update_firmware_handles(); | ||
2519 | up(&ehea_fw_handles.lock); | ||
2520 | |||
2337 | return ret; | 2521 | return ret; |
2338 | } | 2522 | } |
2339 | 2523 | ||
@@ -2382,16 +2566,27 @@ static int ehea_down(struct net_device *dev) | |||
2382 | if (port->state == EHEA_PORT_DOWN) | 2566 | if (port->state == EHEA_PORT_DOWN) |
2383 | return 0; | 2567 | return 0; |
2384 | 2568 | ||
2569 | down(&ehea_bcmc_regs.lock); | ||
2385 | ehea_drop_multicast_list(dev); | 2570 | ehea_drop_multicast_list(dev); |
2571 | ehea_broadcast_reg_helper(port, H_DEREG_BCMC); | ||
2572 | |||
2386 | ehea_free_interrupts(dev); | 2573 | ehea_free_interrupts(dev); |
2387 | 2574 | ||
2575 | down(&ehea_fw_handles.lock); | ||
2576 | |||
2388 | port->state = EHEA_PORT_DOWN; | 2577 | port->state = EHEA_PORT_DOWN; |
2389 | 2578 | ||
2579 | ehea_update_bcmc_registrations(); | ||
2580 | up(&ehea_bcmc_regs.lock); | ||
2581 | |||
2390 | ret = ehea_clean_all_portres(port); | 2582 | ret = ehea_clean_all_portres(port); |
2391 | if (ret) | 2583 | if (ret) |
2392 | ehea_info("Failed freeing resources for %s. ret=%i", | 2584 | ehea_info("Failed freeing resources for %s. ret=%i", |
2393 | dev->name, ret); | 2585 | dev->name, ret); |
2394 | 2586 | ||
2587 | ehea_update_firmware_handles(); | ||
2588 | up(&ehea_fw_handles.lock); | ||
2589 | |||
2395 | return ret; | 2590 | return ret; |
2396 | } | 2591 | } |
2397 | 2592 | ||
@@ -2920,19 +3115,12 @@ struct ehea_port *ehea_setup_single_port(struct ehea_adapter *adapter, | |||
2920 | dev->watchdog_timeo = EHEA_WATCH_DOG_TIMEOUT; | 3115 | dev->watchdog_timeo = EHEA_WATCH_DOG_TIMEOUT; |
2921 | 3116 | ||
2922 | INIT_WORK(&port->reset_task, ehea_reset_port); | 3117 | INIT_WORK(&port->reset_task, ehea_reset_port); |
2923 | |||
2924 | ret = ehea_broadcast_reg_helper(port, H_REG_BCMC); | ||
2925 | if (ret) { | ||
2926 | ret = -EIO; | ||
2927 | goto out_unreg_port; | ||
2928 | } | ||
2929 | |||
2930 | ehea_set_ethtool_ops(dev); | 3118 | ehea_set_ethtool_ops(dev); |
2931 | 3119 | ||
2932 | ret = register_netdev(dev); | 3120 | ret = register_netdev(dev); |
2933 | if (ret) { | 3121 | if (ret) { |
2934 | ehea_error("register_netdev failed. ret=%d", ret); | 3122 | ehea_error("register_netdev failed. ret=%d", ret); |
2935 | goto out_dereg_bc; | 3123 | goto out_unreg_port; |
2936 | } | 3124 | } |
2937 | 3125 | ||
2938 | port->lro_max_aggr = lro_max_aggr; | 3126 | port->lro_max_aggr = lro_max_aggr; |
@@ -2949,9 +3137,6 @@ struct ehea_port *ehea_setup_single_port(struct ehea_adapter *adapter, | |||
2949 | 3137 | ||
2950 | return port; | 3138 | return port; |
2951 | 3139 | ||
2952 | out_dereg_bc: | ||
2953 | ehea_broadcast_reg_helper(port, H_DEREG_BCMC); | ||
2954 | |||
2955 | out_unreg_port: | 3140 | out_unreg_port: |
2956 | ehea_unregister_port(port); | 3141 | ehea_unregister_port(port); |
2957 | 3142 | ||
@@ -2971,7 +3156,6 @@ static void ehea_shutdown_single_port(struct ehea_port *port) | |||
2971 | { | 3156 | { |
2972 | unregister_netdev(port->netdev); | 3157 | unregister_netdev(port->netdev); |
2973 | ehea_unregister_port(port); | 3158 | ehea_unregister_port(port); |
2974 | ehea_broadcast_reg_helper(port, H_DEREG_BCMC); | ||
2975 | kfree(port->mc_list); | 3159 | kfree(port->mc_list); |
2976 | free_netdev(port->netdev); | 3160 | free_netdev(port->netdev); |
2977 | port->adapter->active_ports--; | 3161 | port->adapter->active_ports--; |
@@ -3014,7 +3198,6 @@ static int ehea_setup_ports(struct ehea_adapter *adapter) | |||
3014 | 3198 | ||
3015 | i++; | 3199 | i++; |
3016 | }; | 3200 | }; |
3017 | |||
3018 | return 0; | 3201 | return 0; |
3019 | } | 3202 | } |
3020 | 3203 | ||
@@ -3159,6 +3342,7 @@ static int __devinit ehea_probe_adapter(struct of_device *dev, | |||
3159 | ehea_error("Invalid ibmebus device probed"); | 3342 | ehea_error("Invalid ibmebus device probed"); |
3160 | return -EINVAL; | 3343 | return -EINVAL; |
3161 | } | 3344 | } |
3345 | down(&ehea_fw_handles.lock); | ||
3162 | 3346 | ||
3163 | adapter = kzalloc(sizeof(*adapter), GFP_KERNEL); | 3347 | adapter = kzalloc(sizeof(*adapter), GFP_KERNEL); |
3164 | if (!adapter) { | 3348 | if (!adapter) { |
@@ -3239,7 +3423,10 @@ out_kill_eq: | |||
3239 | 3423 | ||
3240 | out_free_ad: | 3424 | out_free_ad: |
3241 | kfree(adapter); | 3425 | kfree(adapter); |
3426 | |||
3242 | out: | 3427 | out: |
3428 | ehea_update_firmware_handles(); | ||
3429 | up(&ehea_fw_handles.lock); | ||
3243 | return ret; | 3430 | return ret; |
3244 | } | 3431 | } |
3245 | 3432 | ||
@@ -3258,18 +3445,41 @@ static int __devexit ehea_remove(struct of_device *dev) | |||
3258 | 3445 | ||
3259 | flush_scheduled_work(); | 3446 | flush_scheduled_work(); |
3260 | 3447 | ||
3448 | down(&ehea_fw_handles.lock); | ||
3449 | |||
3261 | ibmebus_free_irq(adapter->neq->attr.ist1, adapter); | 3450 | ibmebus_free_irq(adapter->neq->attr.ist1, adapter); |
3262 | tasklet_kill(&adapter->neq_tasklet); | 3451 | tasklet_kill(&adapter->neq_tasklet); |
3263 | 3452 | ||
3264 | ehea_destroy_eq(adapter->neq); | 3453 | ehea_destroy_eq(adapter->neq); |
3265 | ehea_remove_adapter_mr(adapter); | 3454 | ehea_remove_adapter_mr(adapter); |
3266 | list_del(&adapter->list); | 3455 | list_del(&adapter->list); |
3267 | |||
3268 | kfree(adapter); | 3456 | kfree(adapter); |
3269 | 3457 | ||
3458 | ehea_update_firmware_handles(); | ||
3459 | up(&ehea_fw_handles.lock); | ||
3460 | |||
3270 | return 0; | 3461 | return 0; |
3271 | } | 3462 | } |
3272 | 3463 | ||
3464 | void ehea_crash_handler(void) | ||
3465 | { | ||
3466 | int i; | ||
3467 | |||
3468 | if (ehea_fw_handles.arr) | ||
3469 | for (i = 0; i < ehea_fw_handles.num_entries; i++) | ||
3470 | ehea_h_free_resource(ehea_fw_handles.arr[i].adh, | ||
3471 | ehea_fw_handles.arr[i].fwh, | ||
3472 | FORCE_FREE); | ||
3473 | |||
3474 | if (ehea_bcmc_regs.arr) | ||
3475 | for (i = 0; i < ehea_bcmc_regs.num_entries; i++) | ||
3476 | ehea_h_reg_dereg_bcmc(ehea_bcmc_regs.arr[i].adh, | ||
3477 | ehea_bcmc_regs.arr[i].port_id, | ||
3478 | ehea_bcmc_regs.arr[i].reg_type, | ||
3479 | ehea_bcmc_regs.arr[i].macaddr, | ||
3480 | 0, H_DEREG_BCMC); | ||
3481 | } | ||
3482 | |||
3273 | static int ehea_reboot_notifier(struct notifier_block *nb, | 3483 | static int ehea_reboot_notifier(struct notifier_block *nb, |
3274 | unsigned long action, void *unused) | 3484 | unsigned long action, void *unused) |
3275 | { | 3485 | { |
@@ -3330,7 +3540,12 @@ int __init ehea_module_init(void) | |||
3330 | 3540 | ||
3331 | 3541 | ||
3332 | INIT_WORK(&ehea_rereg_mr_task, ehea_rereg_mrs); | 3542 | INIT_WORK(&ehea_rereg_mr_task, ehea_rereg_mrs); |
3543 | memset(&ehea_fw_handles, 0, sizeof(ehea_fw_handles)); | ||
3544 | memset(&ehea_bcmc_regs, 0, sizeof(ehea_bcmc_regs)); | ||
3545 | |||
3333 | sema_init(&dlpar_mem_lock, 1); | 3546 | sema_init(&dlpar_mem_lock, 1); |
3547 | sema_init(&ehea_fw_handles.lock, 1); | ||
3548 | sema_init(&ehea_bcmc_regs.lock, 1); | ||
3334 | 3549 | ||
3335 | ret = check_module_parm(); | 3550 | ret = check_module_parm(); |
3336 | if (ret) | 3551 | if (ret) |
@@ -3340,12 +3555,18 @@ int __init ehea_module_init(void) | |||
3340 | if (ret) | 3555 | if (ret) |
3341 | goto out; | 3556 | goto out; |
3342 | 3557 | ||
3343 | register_reboot_notifier(&ehea_reboot_nb); | 3558 | ret = register_reboot_notifier(&ehea_reboot_nb); |
3559 | if (ret) | ||
3560 | ehea_info("failed registering reboot notifier"); | ||
3561 | |||
3562 | ret = crash_shutdown_register(&ehea_crash_handler); | ||
3563 | if (ret) | ||
3564 | ehea_info("failed registering crash handler"); | ||
3344 | 3565 | ||
3345 | ret = ibmebus_register_driver(&ehea_driver); | 3566 | ret = ibmebus_register_driver(&ehea_driver); |
3346 | if (ret) { | 3567 | if (ret) { |
3347 | ehea_error("failed registering eHEA device driver on ebus"); | 3568 | ehea_error("failed registering eHEA device driver on ebus"); |
3348 | goto out; | 3569 | goto out2; |
3349 | } | 3570 | } |
3350 | 3571 | ||
3351 | ret = driver_create_file(&ehea_driver.driver, | 3572 | ret = driver_create_file(&ehea_driver.driver, |
@@ -3353,21 +3574,33 @@ int __init ehea_module_init(void) | |||
3353 | if (ret) { | 3574 | if (ret) { |
3354 | ehea_error("failed to register capabilities attribute, ret=%d", | 3575 | ehea_error("failed to register capabilities attribute, ret=%d", |
3355 | ret); | 3576 | ret); |
3356 | unregister_reboot_notifier(&ehea_reboot_nb); | 3577 | goto out3; |
3357 | ibmebus_unregister_driver(&ehea_driver); | ||
3358 | goto out; | ||
3359 | } | 3578 | } |
3360 | 3579 | ||
3580 | return ret; | ||
3581 | |||
3582 | out3: | ||
3583 | ibmebus_unregister_driver(&ehea_driver); | ||
3584 | out2: | ||
3585 | unregister_reboot_notifier(&ehea_reboot_nb); | ||
3586 | crash_shutdown_unregister(&ehea_crash_handler); | ||
3361 | out: | 3587 | out: |
3362 | return ret; | 3588 | return ret; |
3363 | } | 3589 | } |
3364 | 3590 | ||
3365 | static void __exit ehea_module_exit(void) | 3591 | static void __exit ehea_module_exit(void) |
3366 | { | 3592 | { |
3593 | int ret; | ||
3594 | |||
3367 | flush_scheduled_work(); | 3595 | flush_scheduled_work(); |
3368 | driver_remove_file(&ehea_driver.driver, &driver_attr_capabilities); | 3596 | driver_remove_file(&ehea_driver.driver, &driver_attr_capabilities); |
3369 | ibmebus_unregister_driver(&ehea_driver); | 3597 | ibmebus_unregister_driver(&ehea_driver); |
3370 | unregister_reboot_notifier(&ehea_reboot_nb); | 3598 | unregister_reboot_notifier(&ehea_reboot_nb); |
3599 | ret = crash_shutdown_unregister(&ehea_crash_handler); | ||
3600 | if (ret) | ||
3601 | ehea_info("failed unregistering crash handler"); | ||
3602 | kfree(ehea_fw_handles.arr); | ||
3603 | kfree(ehea_bcmc_regs.arr); | ||
3371 | ehea_destroy_busmap(); | 3604 | ehea_destroy_busmap(); |
3372 | } | 3605 | } |
3373 | 3606 | ||
diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c index 0809a6a5a286..46a90e9ec563 100644 --- a/drivers/net/enc28j60.c +++ b/drivers/net/enc28j60.c | |||
@@ -900,7 +900,7 @@ static void enc28j60_hw_rx(struct net_device *ndev) | |||
900 | if (RSV_GETBIT(rxstat, RSV_LENCHECKERR)) | 900 | if (RSV_GETBIT(rxstat, RSV_LENCHECKERR)) |
901 | ndev->stats.rx_frame_errors++; | 901 | ndev->stats.rx_frame_errors++; |
902 | } else { | 902 | } else { |
903 | skb = dev_alloc_skb(len); | 903 | skb = dev_alloc_skb(len + NET_IP_ALIGN); |
904 | if (!skb) { | 904 | if (!skb) { |
905 | if (netif_msg_rx_err(priv)) | 905 | if (netif_msg_rx_err(priv)) |
906 | dev_err(&ndev->dev, | 906 | dev_err(&ndev->dev, |
@@ -908,6 +908,7 @@ static void enc28j60_hw_rx(struct net_device *ndev) | |||
908 | ndev->stats.rx_dropped++; | 908 | ndev->stats.rx_dropped++; |
909 | } else { | 909 | } else { |
910 | skb->dev = ndev; | 910 | skb->dev = ndev; |
911 | skb_reserve(skb, NET_IP_ALIGN); | ||
911 | /* copy the packet from the receive buffer */ | 912 | /* copy the packet from the receive buffer */ |
912 | enc28j60_mem_read(priv, priv->next_pk_ptr + sizeof(rsv), | 913 | enc28j60_mem_read(priv, priv->next_pk_ptr + sizeof(rsv), |
913 | len, skb_put(skb, len)); | 914 | len, skb_put(skb, len)); |
diff --git a/drivers/net/fec.c b/drivers/net/fec.c index 0fbf1bbbaee9..d7a3ea88eddb 100644 --- a/drivers/net/fec.c +++ b/drivers/net/fec.c | |||
@@ -1253,7 +1253,7 @@ static void __inline__ fec_request_intrs(struct net_device *dev) | |||
1253 | 1253 | ||
1254 | /* Setup interrupt handlers. */ | 1254 | /* Setup interrupt handlers. */ |
1255 | for (idp = id; idp->name; idp++) { | 1255 | for (idp = id; idp->name; idp++) { |
1256 | if (request_irq(idp->irq, idp->handler, 0, idp->name, dev) != 0) | 1256 | if (request_irq(idp->irq, idp->handler, IRQF_DISABLED, idp->name, dev) != 0) |
1257 | printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, idp->irq); | 1257 | printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, idp->irq); |
1258 | } | 1258 | } |
1259 | 1259 | ||
@@ -1382,7 +1382,7 @@ static void __inline__ fec_request_intrs(struct net_device *dev) | |||
1382 | 1382 | ||
1383 | /* Setup interrupt handlers. */ | 1383 | /* Setup interrupt handlers. */ |
1384 | for (idp = id; idp->name; idp++) { | 1384 | for (idp = id; idp->name; idp++) { |
1385 | if (request_irq(b+idp->irq, fec_enet_interrupt, 0, idp->name, dev) != 0) | 1385 | if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name, dev) != 0) |
1386 | printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq); | 1386 | printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq); |
1387 | } | 1387 | } |
1388 | 1388 | ||
@@ -1553,7 +1553,7 @@ static void __inline__ fec_request_intrs(struct net_device *dev) | |||
1553 | 1553 | ||
1554 | /* Setup interrupt handlers. */ | 1554 | /* Setup interrupt handlers. */ |
1555 | for (idp = id; idp->name; idp++) { | 1555 | for (idp = id; idp->name; idp++) { |
1556 | if (request_irq(b+idp->irq,fec_enet_interrupt,0,idp->name,dev)!=0) | 1556 | if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name,dev) != 0) |
1557 | printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq); | 1557 | printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq); |
1558 | } | 1558 | } |
1559 | 1559 | ||
@@ -1680,7 +1680,7 @@ static void __inline__ fec_request_intrs(struct net_device *dev) | |||
1680 | 1680 | ||
1681 | /* Setup interrupt handlers. */ | 1681 | /* Setup interrupt handlers. */ |
1682 | for (idp = id; idp->name; idp++) { | 1682 | for (idp = id; idp->name; idp++) { |
1683 | if (request_irq(b+idp->irq,fec_enet_interrupt,0,idp->name,dev)!=0) | 1683 | if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name,dev) != 0) |
1684 | printk("FEC: Could not allocate %s IRQ(%d)!\n", | 1684 | printk("FEC: Could not allocate %s IRQ(%d)!\n", |
1685 | idp->name, b+idp->irq); | 1685 | idp->name, b+idp->irq); |
1686 | } | 1686 | } |
diff --git a/drivers/net/fs_enet/fs_enet-main.c b/drivers/net/fs_enet/fs_enet-main.c index 42d94edeee26..af869cf9ae7d 100644 --- a/drivers/net/fs_enet/fs_enet-main.c +++ b/drivers/net/fs_enet/fs_enet-main.c | |||
@@ -946,16 +946,11 @@ static int fs_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |||
946 | { | 946 | { |
947 | struct fs_enet_private *fep = netdev_priv(dev); | 947 | struct fs_enet_private *fep = netdev_priv(dev); |
948 | struct mii_ioctl_data *mii = (struct mii_ioctl_data *)&rq->ifr_data; | 948 | struct mii_ioctl_data *mii = (struct mii_ioctl_data *)&rq->ifr_data; |
949 | unsigned long flags; | ||
950 | int rc; | ||
951 | 949 | ||
952 | if (!netif_running(dev)) | 950 | if (!netif_running(dev)) |
953 | return -EINVAL; | 951 | return -EINVAL; |
954 | 952 | ||
955 | spin_lock_irqsave(&fep->lock, flags); | 953 | return phy_mii_ioctl(fep->phydev, mii, cmd); |
956 | rc = phy_mii_ioctl(fep->phydev, mii, cmd); | ||
957 | spin_unlock_irqrestore(&fep->lock, flags); | ||
958 | return rc; | ||
959 | } | 954 | } |
960 | 955 | ||
961 | extern int fs_mii_connect(struct net_device *dev); | 956 | extern int fs_mii_connect(struct net_device *dev); |
diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c index 4244fc282f21..718cf77e345a 100644 --- a/drivers/net/gianfar.c +++ b/drivers/net/gianfar.c | |||
@@ -605,7 +605,7 @@ void stop_gfar(struct net_device *dev) | |||
605 | 605 | ||
606 | free_skb_resources(priv); | 606 | free_skb_resources(priv); |
607 | 607 | ||
608 | dma_free_coherent(NULL, | 608 | dma_free_coherent(&dev->dev, |
609 | sizeof(struct txbd8)*priv->tx_ring_size | 609 | sizeof(struct txbd8)*priv->tx_ring_size |
610 | + sizeof(struct rxbd8)*priv->rx_ring_size, | 610 | + sizeof(struct rxbd8)*priv->rx_ring_size, |
611 | priv->tx_bd_base, | 611 | priv->tx_bd_base, |
@@ -626,7 +626,7 @@ static void free_skb_resources(struct gfar_private *priv) | |||
626 | for (i = 0; i < priv->tx_ring_size; i++) { | 626 | for (i = 0; i < priv->tx_ring_size; i++) { |
627 | 627 | ||
628 | if (priv->tx_skbuff[i]) { | 628 | if (priv->tx_skbuff[i]) { |
629 | dma_unmap_single(NULL, txbdp->bufPtr, | 629 | dma_unmap_single(&priv->dev->dev, txbdp->bufPtr, |
630 | txbdp->length, | 630 | txbdp->length, |
631 | DMA_TO_DEVICE); | 631 | DMA_TO_DEVICE); |
632 | dev_kfree_skb_any(priv->tx_skbuff[i]); | 632 | dev_kfree_skb_any(priv->tx_skbuff[i]); |
@@ -643,7 +643,7 @@ static void free_skb_resources(struct gfar_private *priv) | |||
643 | if(priv->rx_skbuff != NULL) { | 643 | if(priv->rx_skbuff != NULL) { |
644 | for (i = 0; i < priv->rx_ring_size; i++) { | 644 | for (i = 0; i < priv->rx_ring_size; i++) { |
645 | if (priv->rx_skbuff[i]) { | 645 | if (priv->rx_skbuff[i]) { |
646 | dma_unmap_single(NULL, rxbdp->bufPtr, | 646 | dma_unmap_single(&priv->dev->dev, rxbdp->bufPtr, |
647 | priv->rx_buffer_size, | 647 | priv->rx_buffer_size, |
648 | DMA_FROM_DEVICE); | 648 | DMA_FROM_DEVICE); |
649 | 649 | ||
@@ -708,7 +708,7 @@ int startup_gfar(struct net_device *dev) | |||
708 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | 708 | gfar_write(®s->imask, IMASK_INIT_CLEAR); |
709 | 709 | ||
710 | /* Allocate memory for the buffer descriptors */ | 710 | /* Allocate memory for the buffer descriptors */ |
711 | vaddr = (unsigned long) dma_alloc_coherent(NULL, | 711 | vaddr = (unsigned long) dma_alloc_coherent(&dev->dev, |
712 | sizeof (struct txbd8) * priv->tx_ring_size + | 712 | sizeof (struct txbd8) * priv->tx_ring_size + |
713 | sizeof (struct rxbd8) * priv->rx_ring_size, | 713 | sizeof (struct rxbd8) * priv->rx_ring_size, |
714 | &addr, GFP_KERNEL); | 714 | &addr, GFP_KERNEL); |
@@ -919,7 +919,7 @@ err_irq_fail: | |||
919 | rx_skb_fail: | 919 | rx_skb_fail: |
920 | free_skb_resources(priv); | 920 | free_skb_resources(priv); |
921 | tx_skb_fail: | 921 | tx_skb_fail: |
922 | dma_free_coherent(NULL, | 922 | dma_free_coherent(&dev->dev, |
923 | sizeof(struct txbd8)*priv->tx_ring_size | 923 | sizeof(struct txbd8)*priv->tx_ring_size |
924 | + sizeof(struct rxbd8)*priv->rx_ring_size, | 924 | + sizeof(struct rxbd8)*priv->rx_ring_size, |
925 | priv->tx_bd_base, | 925 | priv->tx_bd_base, |
@@ -1053,7 +1053,7 @@ static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) | |||
1053 | 1053 | ||
1054 | /* Set buffer length and pointer */ | 1054 | /* Set buffer length and pointer */ |
1055 | txbdp->length = skb->len; | 1055 | txbdp->length = skb->len; |
1056 | txbdp->bufPtr = dma_map_single(NULL, skb->data, | 1056 | txbdp->bufPtr = dma_map_single(&dev->dev, skb->data, |
1057 | skb->len, DMA_TO_DEVICE); | 1057 | skb->len, DMA_TO_DEVICE); |
1058 | 1058 | ||
1059 | /* Save the skb pointer so we can free it later */ | 1059 | /* Save the skb pointer so we can free it later */ |
@@ -1332,7 +1332,7 @@ struct sk_buff * gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp) | |||
1332 | */ | 1332 | */ |
1333 | skb_reserve(skb, alignamount); | 1333 | skb_reserve(skb, alignamount); |
1334 | 1334 | ||
1335 | bdp->bufPtr = dma_map_single(NULL, skb->data, | 1335 | bdp->bufPtr = dma_map_single(&dev->dev, skb->data, |
1336 | priv->rx_buffer_size, DMA_FROM_DEVICE); | 1336 | priv->rx_buffer_size, DMA_FROM_DEVICE); |
1337 | 1337 | ||
1338 | bdp->length = 0; | 1338 | bdp->length = 0; |
diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c index bff280eff5e3..6a1f23092099 100644 --- a/drivers/net/igb/igb_main.c +++ b/drivers/net/igb/igb_main.c | |||
@@ -439,7 +439,7 @@ static int igb_request_irq(struct igb_adapter *adapter) | |||
439 | err = igb_request_msix(adapter); | 439 | err = igb_request_msix(adapter); |
440 | if (!err) { | 440 | if (!err) { |
441 | /* enable IAM, auto-mask, | 441 | /* enable IAM, auto-mask, |
442 | * DO NOT USE EIAME or IAME in legacy mode */ | 442 | * DO NOT USE EIAM or IAM in legacy mode */ |
443 | wr32(E1000_IAM, IMS_ENABLE_MASK); | 443 | wr32(E1000_IAM, IMS_ENABLE_MASK); |
444 | goto request_done; | 444 | goto request_done; |
445 | } | 445 | } |
@@ -465,14 +465,9 @@ static int igb_request_irq(struct igb_adapter *adapter) | |||
465 | err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED, | 465 | err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED, |
466 | netdev->name, netdev); | 466 | netdev->name, netdev); |
467 | 467 | ||
468 | if (err) { | 468 | if (err) |
469 | dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n", | 469 | dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n", |
470 | err); | 470 | err); |
471 | goto request_done; | ||
472 | } | ||
473 | |||
474 | /* enable IAM, auto-mask */ | ||
475 | wr32(E1000_IAM, IMS_ENABLE_MASK); | ||
476 | 471 | ||
477 | request_done: | 472 | request_done: |
478 | return err; | 473 | return err; |
@@ -821,7 +816,8 @@ void igb_reset(struct igb_adapter *adapter) | |||
821 | wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); | 816 | wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); |
822 | 817 | ||
823 | igb_reset_adaptive(&adapter->hw); | 818 | igb_reset_adaptive(&adapter->hw); |
824 | adapter->hw.phy.ops.get_phy_info(&adapter->hw); | 819 | if (adapter->hw.phy.ops.get_phy_info) |
820 | adapter->hw.phy.ops.get_phy_info(&adapter->hw); | ||
825 | } | 821 | } |
826 | 822 | ||
827 | /** | 823 | /** |
@@ -2057,7 +2053,8 @@ static void igb_set_multi(struct net_device *netdev) | |||
2057 | static void igb_update_phy_info(unsigned long data) | 2053 | static void igb_update_phy_info(unsigned long data) |
2058 | { | 2054 | { |
2059 | struct igb_adapter *adapter = (struct igb_adapter *) data; | 2055 | struct igb_adapter *adapter = (struct igb_adapter *) data; |
2060 | adapter->hw.phy.ops.get_phy_info(&adapter->hw); | 2056 | if (adapter->hw.phy.ops.get_phy_info) |
2057 | adapter->hw.phy.ops.get_phy_info(&adapter->hw); | ||
2061 | } | 2058 | } |
2062 | 2059 | ||
2063 | /** | 2060 | /** |
diff --git a/drivers/net/ixgb/ixgb_ethtool.c b/drivers/net/ixgb/ixgb_ethtool.c index 53a9fd086f96..75f3a68ee354 100644 --- a/drivers/net/ixgb/ixgb_ethtool.c +++ b/drivers/net/ixgb/ixgb_ethtool.c | |||
@@ -67,6 +67,7 @@ static struct ixgb_stats ixgb_gstrings_stats[] = { | |||
67 | {"rx_over_errors", IXGB_STAT(net_stats.rx_over_errors)}, | 67 | {"rx_over_errors", IXGB_STAT(net_stats.rx_over_errors)}, |
68 | {"rx_crc_errors", IXGB_STAT(net_stats.rx_crc_errors)}, | 68 | {"rx_crc_errors", IXGB_STAT(net_stats.rx_crc_errors)}, |
69 | {"rx_frame_errors", IXGB_STAT(net_stats.rx_frame_errors)}, | 69 | {"rx_frame_errors", IXGB_STAT(net_stats.rx_frame_errors)}, |
70 | {"rx_no_buffer_count", IXGB_STAT(stats.rnbc)}, | ||
70 | {"rx_fifo_errors", IXGB_STAT(net_stats.rx_fifo_errors)}, | 71 | {"rx_fifo_errors", IXGB_STAT(net_stats.rx_fifo_errors)}, |
71 | {"rx_missed_errors", IXGB_STAT(net_stats.rx_missed_errors)}, | 72 | {"rx_missed_errors", IXGB_STAT(net_stats.rx_missed_errors)}, |
72 | {"tx_aborted_errors", IXGB_STAT(net_stats.tx_aborted_errors)}, | 73 | {"tx_aborted_errors", IXGB_STAT(net_stats.tx_aborted_errors)}, |
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c index 23d0a4afe0e1..c2095ce531c9 100644 --- a/drivers/net/ixgbe/ixgbe_main.c +++ b/drivers/net/ixgbe/ixgbe_main.c | |||
@@ -2133,7 +2133,7 @@ static void ixgbe_watchdog(unsigned long data) | |||
2133 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? | 2133 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? |
2134 | "10 Gbps" : | 2134 | "10 Gbps" : |
2135 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | 2135 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? |
2136 | "1 Gpbs" : "unknown speed")), | 2136 | "1 Gbps" : "unknown speed")), |
2137 | ((FLOW_RX && FLOW_TX) ? "RX/TX" : | 2137 | ((FLOW_RX && FLOW_TX) ? "RX/TX" : |
2138 | (FLOW_RX ? "RX" : | 2138 | (FLOW_RX ? "RX" : |
2139 | (FLOW_TX ? "TX" : "None")))); | 2139 | (FLOW_TX ? "TX" : "None")))); |
diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 81bf005ff280..1d210ed46130 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c | |||
@@ -148,7 +148,7 @@ static void macb_handle_link_change(struct net_device *dev) | |||
148 | 148 | ||
149 | if (phydev->duplex) | 149 | if (phydev->duplex) |
150 | reg |= MACB_BIT(FD); | 150 | reg |= MACB_BIT(FD); |
151 | if (phydev->speed) | 151 | if (phydev->speed == SPEED_100) |
152 | reg |= MACB_BIT(SPD); | 152 | reg |= MACB_BIT(SPD); |
153 | 153 | ||
154 | macb_writel(bp, NCFGR, reg); | 154 | macb_writel(bp, NCFGR, reg); |
diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c index b528ce77c406..771139e283af 100644 --- a/drivers/net/mv643xx_eth.c +++ b/drivers/net/mv643xx_eth.c | |||
@@ -2104,6 +2104,7 @@ MODULE_LICENSE("GPL"); | |||
2104 | MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani" | 2104 | MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani" |
2105 | " and Dale Farnsworth"); | 2105 | " and Dale Farnsworth"); |
2106 | MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); | 2106 | MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); |
2107 | MODULE_ALIAS("platform:mv643xx_eth"); | ||
2107 | 2108 | ||
2108 | /* | 2109 | /* |
2109 | * The second part is the low level driver of the gigE ethernet ports. | 2110 | * The second part is the low level driver of the gigE ethernet ports. |
diff --git a/drivers/net/pcmcia/axnet_cs.c b/drivers/net/pcmcia/axnet_cs.c index e8a63e483a2b..ce95c5d168fe 100644 --- a/drivers/net/pcmcia/axnet_cs.c +++ b/drivers/net/pcmcia/axnet_cs.c | |||
@@ -1268,7 +1268,7 @@ static irqreturn_t ax_interrupt(int irq, void *dev_id) | |||
1268 | } | 1268 | } |
1269 | } | 1269 | } |
1270 | 1270 | ||
1271 | if (interrupts && ei_debug) | 1271 | if (interrupts && ei_debug > 3) |
1272 | { | 1272 | { |
1273 | handled = 1; | 1273 | handled = 1; |
1274 | if (nr_serviced >= MAX_SERVICE) | 1274 | if (nr_serviced >= MAX_SERVICE) |
diff --git a/drivers/net/pcmcia/pcnet_cs.c b/drivers/net/pcmcia/pcnet_cs.c index 6323988dfa1d..fd8158a86f64 100644 --- a/drivers/net/pcmcia/pcnet_cs.c +++ b/drivers/net/pcmcia/pcnet_cs.c | |||
@@ -590,6 +590,13 @@ static int pcnet_config(struct pcmcia_device *link) | |||
590 | dev->if_port = 0; | 590 | dev->if_port = 0; |
591 | } | 591 | } |
592 | 592 | ||
593 | if ((link->conf.ConfigBase == 0x03c0) | ||
594 | && (link->manf_id == 0x149) && (link->card_id = 0xc1ab)) { | ||
595 | printk(KERN_INFO "pcnet_cs: this is an AX88190 card!\n"); | ||
596 | printk(KERN_INFO "pcnet_cs: use axnet_cs instead.\n"); | ||
597 | goto failed; | ||
598 | } | ||
599 | |||
593 | local_hw_info = get_hwinfo(link); | 600 | local_hw_info = get_hwinfo(link); |
594 | if (local_hw_info == NULL) | 601 | if (local_hw_info == NULL) |
595 | local_hw_info = get_prom(link); | 602 | local_hw_info = get_prom(link); |
@@ -1567,12 +1574,11 @@ static struct pcmcia_device_id pcnet_ids[] = { | |||
1567 | PCMCIA_DEVICE_MANF_CARD(0x0104, 0x0145), | 1574 | PCMCIA_DEVICE_MANF_CARD(0x0104, 0x0145), |
1568 | PCMCIA_DEVICE_MANF_CARD(0x0149, 0x0230), | 1575 | PCMCIA_DEVICE_MANF_CARD(0x0149, 0x0230), |
1569 | PCMCIA_DEVICE_MANF_CARD(0x0149, 0x4530), | 1576 | PCMCIA_DEVICE_MANF_CARD(0x0149, 0x4530), |
1570 | /* PCMCIA_DEVICE_MANF_CARD(0x0149, 0xc1ab), conflict with axnet_cs */ | 1577 | PCMCIA_DEVICE_MANF_CARD(0x0149, 0xc1ab), |
1571 | PCMCIA_DEVICE_MANF_CARD(0x0186, 0x0110), | 1578 | PCMCIA_DEVICE_MANF_CARD(0x0186, 0x0110), |
1572 | PCMCIA_DEVICE_MANF_CARD(0x01bf, 0x2328), | 1579 | PCMCIA_DEVICE_MANF_CARD(0x01bf, 0x2328), |
1573 | PCMCIA_DEVICE_MANF_CARD(0x01bf, 0x8041), | 1580 | PCMCIA_DEVICE_MANF_CARD(0x01bf, 0x8041), |
1574 | PCMCIA_DEVICE_MANF_CARD(0x0213, 0x2452), | 1581 | PCMCIA_DEVICE_MANF_CARD(0x0213, 0x2452), |
1575 | /* PCMCIA_DEVICE_MANF_CARD(0x021b, 0x0202), conflict with axnet_cs */ | ||
1576 | PCMCIA_DEVICE_MANF_CARD(0x026f, 0x0300), | 1582 | PCMCIA_DEVICE_MANF_CARD(0x026f, 0x0300), |
1577 | PCMCIA_DEVICE_MANF_CARD(0x026f, 0x0307), | 1583 | PCMCIA_DEVICE_MANF_CARD(0x026f, 0x0307), |
1578 | PCMCIA_DEVICE_MANF_CARD(0x026f, 0x030a), | 1584 | PCMCIA_DEVICE_MANF_CARD(0x026f, 0x030a), |
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index f4ca0591231d..3ac8529bb92c 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig | |||
@@ -67,6 +67,7 @@ config REALTEK_PHY | |||
67 | 67 | ||
68 | config FIXED_PHY | 68 | config FIXED_PHY |
69 | bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" | 69 | bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" |
70 | depends on PHYLIB=y | ||
70 | ---help--- | 71 | ---help--- |
71 | Adds the platform "fixed" MDIO Bus to cover the boards that use | 72 | Adds the platform "fixed" MDIO Bus to cover the boards that use |
72 | PHYs that are not connected to the real MDIO bus. | 73 | PHYs that are not connected to the real MDIO bus. |
diff --git a/drivers/net/phy/davicom.c b/drivers/net/phy/davicom.c index 7ed632db00d7..d926168bc780 100644 --- a/drivers/net/phy/davicom.c +++ b/drivers/net/phy/davicom.c | |||
@@ -37,6 +37,7 @@ | |||
37 | 37 | ||
38 | #define MII_DM9161_SCR 0x10 | 38 | #define MII_DM9161_SCR 0x10 |
39 | #define MII_DM9161_SCR_INIT 0x0610 | 39 | #define MII_DM9161_SCR_INIT 0x0610 |
40 | #define MII_DM9161_SCR_RMII 0x0100 | ||
40 | 41 | ||
41 | /* DM9161 Interrupt Register */ | 42 | /* DM9161 Interrupt Register */ |
42 | #define MII_DM9161_INTR 0x15 | 43 | #define MII_DM9161_INTR 0x15 |
@@ -103,7 +104,7 @@ static int dm9161_config_aneg(struct phy_device *phydev) | |||
103 | 104 | ||
104 | static int dm9161_config_init(struct phy_device *phydev) | 105 | static int dm9161_config_init(struct phy_device *phydev) |
105 | { | 106 | { |
106 | int err; | 107 | int err, temp; |
107 | 108 | ||
108 | /* Isolate the PHY */ | 109 | /* Isolate the PHY */ |
109 | err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE); | 110 | err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE); |
@@ -111,9 +112,19 @@ static int dm9161_config_init(struct phy_device *phydev) | |||
111 | if (err < 0) | 112 | if (err < 0) |
112 | return err; | 113 | return err; |
113 | 114 | ||
114 | /* Do not bypass the scrambler/descrambler */ | 115 | switch (phydev->interface) { |
115 | err = phy_write(phydev, MII_DM9161_SCR, MII_DM9161_SCR_INIT); | 116 | case PHY_INTERFACE_MODE_MII: |
117 | temp = MII_DM9161_SCR_INIT; | ||
118 | break; | ||
119 | case PHY_INTERFACE_MODE_RMII: | ||
120 | temp = MII_DM9161_SCR_INIT | MII_DM9161_SCR_RMII; | ||
121 | break; | ||
122 | default: | ||
123 | return -EINVAL; | ||
124 | } | ||
116 | 125 | ||
126 | /* Do not bypass the scrambler/descrambler */ | ||
127 | err = phy_write(phydev, MII_DM9161_SCR, temp); | ||
117 | if (err < 0) | 128 | if (err < 0) |
118 | return err; | 129 | return err; |
119 | 130 | ||
diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c index 6e9f619c491f..963630c65ca9 100644 --- a/drivers/net/phy/mdio_bus.c +++ b/drivers/net/phy/mdio_bus.c | |||
@@ -49,13 +49,13 @@ int mdiobus_register(struct mii_bus *bus) | |||
49 | int i; | 49 | int i; |
50 | int err = 0; | 50 | int err = 0; |
51 | 51 | ||
52 | mutex_init(&bus->mdio_lock); | ||
53 | |||
54 | if (NULL == bus || NULL == bus->name || | 52 | if (NULL == bus || NULL == bus->name || |
55 | NULL == bus->read || | 53 | NULL == bus->read || |
56 | NULL == bus->write) | 54 | NULL == bus->write) |
57 | return -EINVAL; | 55 | return -EINVAL; |
58 | 56 | ||
57 | mutex_init(&bus->mdio_lock); | ||
58 | |||
59 | if (bus->reset) | 59 | if (bus->reset) |
60 | bus->reset(bus); | 60 | bus->reset(bus); |
61 | 61 | ||
diff --git a/drivers/net/pppol2tp.c b/drivers/net/pppol2tp.c index e0b072d9fdb7..3d10ca050b79 100644 --- a/drivers/net/pppol2tp.c +++ b/drivers/net/pppol2tp.c | |||
@@ -302,14 +302,14 @@ pppol2tp_session_find(struct pppol2tp_tunnel *tunnel, u16 session_id) | |||
302 | struct pppol2tp_session *session; | 302 | struct pppol2tp_session *session; |
303 | struct hlist_node *walk; | 303 | struct hlist_node *walk; |
304 | 304 | ||
305 | read_lock(&tunnel->hlist_lock); | 305 | read_lock_bh(&tunnel->hlist_lock); |
306 | hlist_for_each_entry(session, walk, session_list, hlist) { | 306 | hlist_for_each_entry(session, walk, session_list, hlist) { |
307 | if (session->tunnel_addr.s_session == session_id) { | 307 | if (session->tunnel_addr.s_session == session_id) { |
308 | read_unlock(&tunnel->hlist_lock); | 308 | read_unlock_bh(&tunnel->hlist_lock); |
309 | return session; | 309 | return session; |
310 | } | 310 | } |
311 | } | 311 | } |
312 | read_unlock(&tunnel->hlist_lock); | 312 | read_unlock_bh(&tunnel->hlist_lock); |
313 | 313 | ||
314 | return NULL; | 314 | return NULL; |
315 | } | 315 | } |
@@ -320,14 +320,14 @@ static struct pppol2tp_tunnel *pppol2tp_tunnel_find(u16 tunnel_id) | |||
320 | { | 320 | { |
321 | struct pppol2tp_tunnel *tunnel = NULL; | 321 | struct pppol2tp_tunnel *tunnel = NULL; |
322 | 322 | ||
323 | read_lock(&pppol2tp_tunnel_list_lock); | 323 | read_lock_bh(&pppol2tp_tunnel_list_lock); |
324 | list_for_each_entry(tunnel, &pppol2tp_tunnel_list, list) { | 324 | list_for_each_entry(tunnel, &pppol2tp_tunnel_list, list) { |
325 | if (tunnel->stats.tunnel_id == tunnel_id) { | 325 | if (tunnel->stats.tunnel_id == tunnel_id) { |
326 | read_unlock(&pppol2tp_tunnel_list_lock); | 326 | read_unlock_bh(&pppol2tp_tunnel_list_lock); |
327 | return tunnel; | 327 | return tunnel; |
328 | } | 328 | } |
329 | } | 329 | } |
330 | read_unlock(&pppol2tp_tunnel_list_lock); | 330 | read_unlock_bh(&pppol2tp_tunnel_list_lock); |
331 | 331 | ||
332 | return NULL; | 332 | return NULL; |
333 | } | 333 | } |
@@ -342,10 +342,11 @@ static struct pppol2tp_tunnel *pppol2tp_tunnel_find(u16 tunnel_id) | |||
342 | static void pppol2tp_recv_queue_skb(struct pppol2tp_session *session, struct sk_buff *skb) | 342 | static void pppol2tp_recv_queue_skb(struct pppol2tp_session *session, struct sk_buff *skb) |
343 | { | 343 | { |
344 | struct sk_buff *skbp; | 344 | struct sk_buff *skbp; |
345 | struct sk_buff *tmp; | ||
345 | u16 ns = PPPOL2TP_SKB_CB(skb)->ns; | 346 | u16 ns = PPPOL2TP_SKB_CB(skb)->ns; |
346 | 347 | ||
347 | spin_lock(&session->reorder_q.lock); | 348 | spin_lock_bh(&session->reorder_q.lock); |
348 | skb_queue_walk(&session->reorder_q, skbp) { | 349 | skb_queue_walk_safe(&session->reorder_q, skbp, tmp) { |
349 | if (PPPOL2TP_SKB_CB(skbp)->ns > ns) { | 350 | if (PPPOL2TP_SKB_CB(skbp)->ns > ns) { |
350 | __skb_insert(skb, skbp->prev, skbp, &session->reorder_q); | 351 | __skb_insert(skb, skbp->prev, skbp, &session->reorder_q); |
351 | PRINTK(session->debug, PPPOL2TP_MSG_SEQ, KERN_DEBUG, | 352 | PRINTK(session->debug, PPPOL2TP_MSG_SEQ, KERN_DEBUG, |
@@ -360,7 +361,7 @@ static void pppol2tp_recv_queue_skb(struct pppol2tp_session *session, struct sk_ | |||
360 | __skb_queue_tail(&session->reorder_q, skb); | 361 | __skb_queue_tail(&session->reorder_q, skb); |
361 | 362 | ||
362 | out: | 363 | out: |
363 | spin_unlock(&session->reorder_q.lock); | 364 | spin_unlock_bh(&session->reorder_q.lock); |
364 | } | 365 | } |
365 | 366 | ||
366 | /* Dequeue a single skb. | 367 | /* Dequeue a single skb. |
@@ -371,10 +372,9 @@ static void pppol2tp_recv_dequeue_skb(struct pppol2tp_session *session, struct s | |||
371 | int length = PPPOL2TP_SKB_CB(skb)->length; | 372 | int length = PPPOL2TP_SKB_CB(skb)->length; |
372 | struct sock *session_sock = NULL; | 373 | struct sock *session_sock = NULL; |
373 | 374 | ||
374 | /* We're about to requeue the skb, so unlink it and return resources | 375 | /* We're about to requeue the skb, so return resources |
375 | * to its current owner (a socket receive buffer). | 376 | * to its current owner (a socket receive buffer). |
376 | */ | 377 | */ |
377 | skb_unlink(skb, &session->reorder_q); | ||
378 | skb_orphan(skb); | 378 | skb_orphan(skb); |
379 | 379 | ||
380 | tunnel->stats.rx_packets++; | 380 | tunnel->stats.rx_packets++; |
@@ -442,7 +442,7 @@ static void pppol2tp_recv_dequeue(struct pppol2tp_session *session) | |||
442 | * expect to send up next, dequeue it and any other | 442 | * expect to send up next, dequeue it and any other |
443 | * in-sequence packets behind it. | 443 | * in-sequence packets behind it. |
444 | */ | 444 | */ |
445 | spin_lock(&session->reorder_q.lock); | 445 | spin_lock_bh(&session->reorder_q.lock); |
446 | skb_queue_walk_safe(&session->reorder_q, skb, tmp) { | 446 | skb_queue_walk_safe(&session->reorder_q, skb, tmp) { |
447 | if (time_after(jiffies, PPPOL2TP_SKB_CB(skb)->expires)) { | 447 | if (time_after(jiffies, PPPOL2TP_SKB_CB(skb)->expires)) { |
448 | session->stats.rx_seq_discards++; | 448 | session->stats.rx_seq_discards++; |
@@ -455,6 +455,7 @@ static void pppol2tp_recv_dequeue(struct pppol2tp_session *session) | |||
455 | skb_queue_len(&session->reorder_q)); | 455 | skb_queue_len(&session->reorder_q)); |
456 | __skb_unlink(skb, &session->reorder_q); | 456 | __skb_unlink(skb, &session->reorder_q); |
457 | kfree_skb(skb); | 457 | kfree_skb(skb); |
458 | sock_put(session->sock); | ||
458 | continue; | 459 | continue; |
459 | } | 460 | } |
460 | 461 | ||
@@ -469,13 +470,18 @@ static void pppol2tp_recv_dequeue(struct pppol2tp_session *session) | |||
469 | goto out; | 470 | goto out; |
470 | } | 471 | } |
471 | } | 472 | } |
472 | spin_unlock(&session->reorder_q.lock); | 473 | __skb_unlink(skb, &session->reorder_q); |
474 | |||
475 | /* Process the skb. We release the queue lock while we | ||
476 | * do so to let other contexts process the queue. | ||
477 | */ | ||
478 | spin_unlock_bh(&session->reorder_q.lock); | ||
473 | pppol2tp_recv_dequeue_skb(session, skb); | 479 | pppol2tp_recv_dequeue_skb(session, skb); |
474 | spin_lock(&session->reorder_q.lock); | 480 | spin_lock_bh(&session->reorder_q.lock); |
475 | } | 481 | } |
476 | 482 | ||
477 | out: | 483 | out: |
478 | spin_unlock(&session->reorder_q.lock); | 484 | spin_unlock_bh(&session->reorder_q.lock); |
479 | } | 485 | } |
480 | 486 | ||
481 | /* Internal receive frame. Do the real work of receiving an L2TP data frame | 487 | /* Internal receive frame. Do the real work of receiving an L2TP data frame |
@@ -1058,7 +1064,7 @@ static int pppol2tp_xmit(struct ppp_channel *chan, struct sk_buff *skb) | |||
1058 | 1064 | ||
1059 | /* Get routing info from the tunnel socket */ | 1065 | /* Get routing info from the tunnel socket */ |
1060 | dst_release(skb->dst); | 1066 | dst_release(skb->dst); |
1061 | skb->dst = sk_dst_get(sk_tun); | 1067 | skb->dst = dst_clone(__sk_dst_get(sk_tun)); |
1062 | skb_orphan(skb); | 1068 | skb_orphan(skb); |
1063 | skb->sk = sk_tun; | 1069 | skb->sk = sk_tun; |
1064 | 1070 | ||
@@ -1106,10 +1112,12 @@ static void pppol2tp_tunnel_closeall(struct pppol2tp_tunnel *tunnel) | |||
1106 | PRINTK(tunnel->debug, PPPOL2TP_MSG_CONTROL, KERN_INFO, | 1112 | PRINTK(tunnel->debug, PPPOL2TP_MSG_CONTROL, KERN_INFO, |
1107 | "%s: closing all sessions...\n", tunnel->name); | 1113 | "%s: closing all sessions...\n", tunnel->name); |
1108 | 1114 | ||
1109 | write_lock(&tunnel->hlist_lock); | 1115 | write_lock_bh(&tunnel->hlist_lock); |
1110 | for (hash = 0; hash < PPPOL2TP_HASH_SIZE; hash++) { | 1116 | for (hash = 0; hash < PPPOL2TP_HASH_SIZE; hash++) { |
1111 | again: | 1117 | again: |
1112 | hlist_for_each_safe(walk, tmp, &tunnel->session_hlist[hash]) { | 1118 | hlist_for_each_safe(walk, tmp, &tunnel->session_hlist[hash]) { |
1119 | struct sk_buff *skb; | ||
1120 | |||
1113 | session = hlist_entry(walk, struct pppol2tp_session, hlist); | 1121 | session = hlist_entry(walk, struct pppol2tp_session, hlist); |
1114 | 1122 | ||
1115 | sk = session->sock; | 1123 | sk = session->sock; |
@@ -1126,7 +1134,7 @@ again: | |||
1126 | * disappear as we're jumping between locks. | 1134 | * disappear as we're jumping between locks. |
1127 | */ | 1135 | */ |
1128 | sock_hold(sk); | 1136 | sock_hold(sk); |
1129 | write_unlock(&tunnel->hlist_lock); | 1137 | write_unlock_bh(&tunnel->hlist_lock); |
1130 | lock_sock(sk); | 1138 | lock_sock(sk); |
1131 | 1139 | ||
1132 | if (sk->sk_state & (PPPOX_CONNECTED | PPPOX_BOUND)) { | 1140 | if (sk->sk_state & (PPPOX_CONNECTED | PPPOX_BOUND)) { |
@@ -1138,7 +1146,10 @@ again: | |||
1138 | /* Purge any queued data */ | 1146 | /* Purge any queued data */ |
1139 | skb_queue_purge(&sk->sk_receive_queue); | 1147 | skb_queue_purge(&sk->sk_receive_queue); |
1140 | skb_queue_purge(&sk->sk_write_queue); | 1148 | skb_queue_purge(&sk->sk_write_queue); |
1141 | skb_queue_purge(&session->reorder_q); | 1149 | while ((skb = skb_dequeue(&session->reorder_q))) { |
1150 | kfree_skb(skb); | ||
1151 | sock_put(sk); | ||
1152 | } | ||
1142 | 1153 | ||
1143 | release_sock(sk); | 1154 | release_sock(sk); |
1144 | sock_put(sk); | 1155 | sock_put(sk); |
@@ -1148,11 +1159,11 @@ again: | |||
1148 | * list so we are guaranteed to make forward | 1159 | * list so we are guaranteed to make forward |
1149 | * progress. | 1160 | * progress. |
1150 | */ | 1161 | */ |
1151 | write_lock(&tunnel->hlist_lock); | 1162 | write_lock_bh(&tunnel->hlist_lock); |
1152 | goto again; | 1163 | goto again; |
1153 | } | 1164 | } |
1154 | } | 1165 | } |
1155 | write_unlock(&tunnel->hlist_lock); | 1166 | write_unlock_bh(&tunnel->hlist_lock); |
1156 | } | 1167 | } |
1157 | 1168 | ||
1158 | /* Really kill the tunnel. | 1169 | /* Really kill the tunnel. |
@@ -1161,9 +1172,9 @@ again: | |||
1161 | static void pppol2tp_tunnel_free(struct pppol2tp_tunnel *tunnel) | 1172 | static void pppol2tp_tunnel_free(struct pppol2tp_tunnel *tunnel) |
1162 | { | 1173 | { |
1163 | /* Remove from socket list */ | 1174 | /* Remove from socket list */ |
1164 | write_lock(&pppol2tp_tunnel_list_lock); | 1175 | write_lock_bh(&pppol2tp_tunnel_list_lock); |
1165 | list_del_init(&tunnel->list); | 1176 | list_del_init(&tunnel->list); |
1166 | write_unlock(&pppol2tp_tunnel_list_lock); | 1177 | write_unlock_bh(&pppol2tp_tunnel_list_lock); |
1167 | 1178 | ||
1168 | atomic_dec(&pppol2tp_tunnel_count); | 1179 | atomic_dec(&pppol2tp_tunnel_count); |
1169 | kfree(tunnel); | 1180 | kfree(tunnel); |
@@ -1239,9 +1250,9 @@ static void pppol2tp_session_destruct(struct sock *sk) | |||
1239 | /* Delete the session socket from the | 1250 | /* Delete the session socket from the |
1240 | * hash | 1251 | * hash |
1241 | */ | 1252 | */ |
1242 | write_lock(&tunnel->hlist_lock); | 1253 | write_lock_bh(&tunnel->hlist_lock); |
1243 | hlist_del_init(&session->hlist); | 1254 | hlist_del_init(&session->hlist); |
1244 | write_unlock(&tunnel->hlist_lock); | 1255 | write_unlock_bh(&tunnel->hlist_lock); |
1245 | 1256 | ||
1246 | atomic_dec(&pppol2tp_session_count); | 1257 | atomic_dec(&pppol2tp_session_count); |
1247 | } | 1258 | } |
@@ -1386,9 +1397,9 @@ static struct sock *pppol2tp_prepare_tunnel_socket(int fd, u16 tunnel_id, | |||
1386 | 1397 | ||
1387 | /* Add tunnel to our list */ | 1398 | /* Add tunnel to our list */ |
1388 | INIT_LIST_HEAD(&tunnel->list); | 1399 | INIT_LIST_HEAD(&tunnel->list); |
1389 | write_lock(&pppol2tp_tunnel_list_lock); | 1400 | write_lock_bh(&pppol2tp_tunnel_list_lock); |
1390 | list_add(&tunnel->list, &pppol2tp_tunnel_list); | 1401 | list_add(&tunnel->list, &pppol2tp_tunnel_list); |
1391 | write_unlock(&pppol2tp_tunnel_list_lock); | 1402 | write_unlock_bh(&pppol2tp_tunnel_list_lock); |
1392 | atomic_inc(&pppol2tp_tunnel_count); | 1403 | atomic_inc(&pppol2tp_tunnel_count); |
1393 | 1404 | ||
1394 | /* Bump the reference count. The tunnel context is deleted | 1405 | /* Bump the reference count. The tunnel context is deleted |
@@ -1593,11 +1604,11 @@ static int pppol2tp_connect(struct socket *sock, struct sockaddr *uservaddr, | |||
1593 | sk->sk_user_data = session; | 1604 | sk->sk_user_data = session; |
1594 | 1605 | ||
1595 | /* Add session to the tunnel's hash list */ | 1606 | /* Add session to the tunnel's hash list */ |
1596 | write_lock(&tunnel->hlist_lock); | 1607 | write_lock_bh(&tunnel->hlist_lock); |
1597 | hlist_add_head(&session->hlist, | 1608 | hlist_add_head(&session->hlist, |
1598 | pppol2tp_session_id_hash(tunnel, | 1609 | pppol2tp_session_id_hash(tunnel, |
1599 | session->tunnel_addr.s_session)); | 1610 | session->tunnel_addr.s_session)); |
1600 | write_unlock(&tunnel->hlist_lock); | 1611 | write_unlock_bh(&tunnel->hlist_lock); |
1601 | 1612 | ||
1602 | atomic_inc(&pppol2tp_session_count); | 1613 | atomic_inc(&pppol2tp_session_count); |
1603 | 1614 | ||
@@ -2199,7 +2210,7 @@ static struct pppol2tp_session *next_session(struct pppol2tp_tunnel *tunnel, str | |||
2199 | int next = 0; | 2210 | int next = 0; |
2200 | int i; | 2211 | int i; |
2201 | 2212 | ||
2202 | read_lock(&tunnel->hlist_lock); | 2213 | read_lock_bh(&tunnel->hlist_lock); |
2203 | for (i = 0; i < PPPOL2TP_HASH_SIZE; i++) { | 2214 | for (i = 0; i < PPPOL2TP_HASH_SIZE; i++) { |
2204 | hlist_for_each_entry(session, walk, &tunnel->session_hlist[i], hlist) { | 2215 | hlist_for_each_entry(session, walk, &tunnel->session_hlist[i], hlist) { |
2205 | if (curr == NULL) { | 2216 | if (curr == NULL) { |
@@ -2217,7 +2228,7 @@ static struct pppol2tp_session *next_session(struct pppol2tp_tunnel *tunnel, str | |||
2217 | } | 2228 | } |
2218 | } | 2229 | } |
2219 | out: | 2230 | out: |
2220 | read_unlock(&tunnel->hlist_lock); | 2231 | read_unlock_bh(&tunnel->hlist_lock); |
2221 | if (!found) | 2232 | if (!found) |
2222 | session = NULL; | 2233 | session = NULL; |
2223 | 2234 | ||
@@ -2228,13 +2239,13 @@ static struct pppol2tp_tunnel *next_tunnel(struct pppol2tp_tunnel *curr) | |||
2228 | { | 2239 | { |
2229 | struct pppol2tp_tunnel *tunnel = NULL; | 2240 | struct pppol2tp_tunnel *tunnel = NULL; |
2230 | 2241 | ||
2231 | read_lock(&pppol2tp_tunnel_list_lock); | 2242 | read_lock_bh(&pppol2tp_tunnel_list_lock); |
2232 | if (list_is_last(&curr->list, &pppol2tp_tunnel_list)) { | 2243 | if (list_is_last(&curr->list, &pppol2tp_tunnel_list)) { |
2233 | goto out; | 2244 | goto out; |
2234 | } | 2245 | } |
2235 | tunnel = list_entry(curr->list.next, struct pppol2tp_tunnel, list); | 2246 | tunnel = list_entry(curr->list.next, struct pppol2tp_tunnel, list); |
2236 | out: | 2247 | out: |
2237 | read_unlock(&pppol2tp_tunnel_list_lock); | 2248 | read_unlock_bh(&pppol2tp_tunnel_list_lock); |
2238 | 2249 | ||
2239 | return tunnel; | 2250 | return tunnel; |
2240 | } | 2251 | } |
diff --git a/drivers/net/ps3_gelic_wireless.c b/drivers/net/ps3_gelic_wireless.c index 750d2a99cb4f..daf5abab9534 100644 --- a/drivers/net/ps3_gelic_wireless.c +++ b/drivers/net/ps3_gelic_wireless.c | |||
@@ -2690,6 +2690,7 @@ int gelic_wl_driver_probe(struct gelic_card *card) | |||
2690 | return -ENOMEM; | 2690 | return -ENOMEM; |
2691 | 2691 | ||
2692 | /* setup net_device structure */ | 2692 | /* setup net_device structure */ |
2693 | SET_NETDEV_DEV(netdev, &card->dev->core); | ||
2693 | gelic_wl_setup_netdev_ops(netdev); | 2694 | gelic_wl_setup_netdev_ops(netdev); |
2694 | 2695 | ||
2695 | /* setup some of net_device and register it */ | 2696 | /* setup some of net_device and register it */ |
diff --git a/drivers/net/s2io.c b/drivers/net/s2io.c index 6179a0a2032c..c72787adeba3 100644 --- a/drivers/net/s2io.c +++ b/drivers/net/s2io.c | |||
@@ -1088,7 +1088,7 @@ static int s2io_print_pci_mode(struct s2io_nic *nic) | |||
1088 | * '-1' on failure | 1088 | * '-1' on failure |
1089 | */ | 1089 | */ |
1090 | 1090 | ||
1091 | int init_tti(struct s2io_nic *nic, int link) | 1091 | static int init_tti(struct s2io_nic *nic, int link) |
1092 | { | 1092 | { |
1093 | struct XENA_dev_config __iomem *bar0 = nic->bar0; | 1093 | struct XENA_dev_config __iomem *bar0 = nic->bar0; |
1094 | register u64 val64 = 0; | 1094 | register u64 val64 = 0; |
diff --git a/drivers/net/sis190.c b/drivers/net/sis190.c index 202fdf356621..20745fd4e973 100644 --- a/drivers/net/sis190.c +++ b/drivers/net/sis190.c | |||
@@ -1633,13 +1633,18 @@ static inline void sis190_init_rxfilter(struct net_device *dev) | |||
1633 | static int __devinit sis190_get_mac_addr(struct pci_dev *pdev, | 1633 | static int __devinit sis190_get_mac_addr(struct pci_dev *pdev, |
1634 | struct net_device *dev) | 1634 | struct net_device *dev) |
1635 | { | 1635 | { |
1636 | u8 from; | 1636 | int rc; |
1637 | |||
1638 | rc = sis190_get_mac_addr_from_eeprom(pdev, dev); | ||
1639 | if (rc < 0) { | ||
1640 | u8 reg; | ||
1637 | 1641 | ||
1638 | pci_read_config_byte(pdev, 0x73, &from); | 1642 | pci_read_config_byte(pdev, 0x73, ®); |
1639 | 1643 | ||
1640 | return (from & 0x00000001) ? | 1644 | if (reg & 0x00000001) |
1641 | sis190_get_mac_addr_from_apc(pdev, dev) : | 1645 | rc = sis190_get_mac_addr_from_apc(pdev, dev); |
1642 | sis190_get_mac_addr_from_eeprom(pdev, dev); | 1646 | } |
1647 | return rc; | ||
1643 | } | 1648 | } |
1644 | 1649 | ||
1645 | static void sis190_set_speed_auto(struct net_device *dev) | 1650 | static void sis190_set_speed_auto(struct net_device *dev) |
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c index 9a6295909e43..54c662690f65 100644 --- a/drivers/net/sky2.c +++ b/drivers/net/sky2.c | |||
@@ -572,8 +572,9 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port) | |||
572 | default: | 572 | default: |
573 | /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ | 573 | /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ |
574 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; | 574 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; |
575 | |||
575 | /* turn off the Rx LED (LED_RX) */ | 576 | /* turn off the Rx LED (LED_RX) */ |
576 | ledover &= ~PHY_M_LED_MO_RX; | 577 | ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); |
577 | } | 578 | } |
578 | 579 | ||
579 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && | 580 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && |
@@ -602,7 +603,7 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port) | |||
602 | 603 | ||
603 | if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) { | 604 | if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) { |
604 | /* turn on 100 Mbps LED (LED_LINK100) */ | 605 | /* turn on 100 Mbps LED (LED_LINK100) */ |
605 | ledover |= PHY_M_LED_MO_100; | 606 | ledover |= PHY_M_LED_MO_100(MO_LED_ON); |
606 | } | 607 | } |
607 | 608 | ||
608 | if (ledover) | 609 | if (ledover) |
@@ -3322,82 +3323,80 @@ static void sky2_set_multicast(struct net_device *dev) | |||
3322 | /* Can have one global because blinking is controlled by | 3323 | /* Can have one global because blinking is controlled by |
3323 | * ethtool and that is always under RTNL mutex | 3324 | * ethtool and that is always under RTNL mutex |
3324 | */ | 3325 | */ |
3325 | static void sky2_led(struct sky2_hw *hw, unsigned port, int on) | 3326 | static void sky2_led(struct sky2_port *sky2, enum led_mode mode) |
3326 | { | 3327 | { |
3327 | u16 pg; | 3328 | struct sky2_hw *hw = sky2->hw; |
3329 | unsigned port = sky2->port; | ||
3328 | 3330 | ||
3329 | switch (hw->chip_id) { | 3331 | spin_lock_bh(&sky2->phy_lock); |
3330 | case CHIP_ID_YUKON_XL: | 3332 | if (hw->chip_id == CHIP_ID_YUKON_EC_U || |
3333 | hw->chip_id == CHIP_ID_YUKON_EX || | ||
3334 | hw->chip_id == CHIP_ID_YUKON_SUPR) { | ||
3335 | u16 pg; | ||
3331 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | 3336 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
3332 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | 3337 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); |
3333 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | ||
3334 | on ? (PHY_M_LEDC_LOS_CTRL(1) | | ||
3335 | PHY_M_LEDC_INIT_CTRL(7) | | ||
3336 | PHY_M_LEDC_STA1_CTRL(7) | | ||
3337 | PHY_M_LEDC_STA0_CTRL(7)) | ||
3338 | : 0); | ||
3339 | 3338 | ||
3340 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | 3339 | switch (mode) { |
3341 | break; | 3340 | case MO_LED_OFF: |
3341 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | ||
3342 | PHY_M_LEDC_LOS_CTRL(8) | | ||
3343 | PHY_M_LEDC_INIT_CTRL(8) | | ||
3344 | PHY_M_LEDC_STA1_CTRL(8) | | ||
3345 | PHY_M_LEDC_STA0_CTRL(8)); | ||
3346 | break; | ||
3347 | case MO_LED_ON: | ||
3348 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | ||
3349 | PHY_M_LEDC_LOS_CTRL(9) | | ||
3350 | PHY_M_LEDC_INIT_CTRL(9) | | ||
3351 | PHY_M_LEDC_STA1_CTRL(9) | | ||
3352 | PHY_M_LEDC_STA0_CTRL(9)); | ||
3353 | break; | ||
3354 | case MO_LED_BLINK: | ||
3355 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | ||
3356 | PHY_M_LEDC_LOS_CTRL(0xa) | | ||
3357 | PHY_M_LEDC_INIT_CTRL(0xa) | | ||
3358 | PHY_M_LEDC_STA1_CTRL(0xa) | | ||
3359 | PHY_M_LEDC_STA0_CTRL(0xa)); | ||
3360 | break; | ||
3361 | case MO_LED_NORM: | ||
3362 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | ||
3363 | PHY_M_LEDC_LOS_CTRL(1) | | ||
3364 | PHY_M_LEDC_INIT_CTRL(8) | | ||
3365 | PHY_M_LEDC_STA1_CTRL(7) | | ||
3366 | PHY_M_LEDC_STA0_CTRL(7)); | ||
3367 | } | ||
3342 | 3368 | ||
3343 | default: | 3369 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); |
3344 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); | 3370 | } else |
3345 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, | 3371 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, |
3346 | on ? PHY_M_LED_ALL : 0); | 3372 | PHY_M_LED_MO_DUP(mode) | |
3347 | } | 3373 | PHY_M_LED_MO_10(mode) | |
3374 | PHY_M_LED_MO_100(mode) | | ||
3375 | PHY_M_LED_MO_1000(mode) | | ||
3376 | PHY_M_LED_MO_RX(mode) | | ||
3377 | PHY_M_LED_MO_TX(mode)); | ||
3378 | |||
3379 | spin_unlock_bh(&sky2->phy_lock); | ||
3348 | } | 3380 | } |
3349 | 3381 | ||
3350 | /* blink LED's for finding board */ | 3382 | /* blink LED's for finding board */ |
3351 | static int sky2_phys_id(struct net_device *dev, u32 data) | 3383 | static int sky2_phys_id(struct net_device *dev, u32 data) |
3352 | { | 3384 | { |
3353 | struct sky2_port *sky2 = netdev_priv(dev); | 3385 | struct sky2_port *sky2 = netdev_priv(dev); |
3354 | struct sky2_hw *hw = sky2->hw; | 3386 | unsigned int i; |
3355 | unsigned port = sky2->port; | ||
3356 | u16 ledctrl, ledover = 0; | ||
3357 | long ms; | ||
3358 | int interrupted; | ||
3359 | int onoff = 1; | ||
3360 | 3387 | ||
3361 | if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)) | 3388 | if (data == 0) |
3362 | ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT); | 3389 | data = UINT_MAX; |
3363 | else | ||
3364 | ms = data * 1000; | ||
3365 | |||
3366 | /* save initial values */ | ||
3367 | spin_lock_bh(&sky2->phy_lock); | ||
3368 | if (hw->chip_id == CHIP_ID_YUKON_XL) { | ||
3369 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | ||
3370 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | ||
3371 | ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | ||
3372 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | ||
3373 | } else { | ||
3374 | ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL); | ||
3375 | ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER); | ||
3376 | } | ||
3377 | |||
3378 | interrupted = 0; | ||
3379 | while (!interrupted && ms > 0) { | ||
3380 | sky2_led(hw, port, onoff); | ||
3381 | onoff = !onoff; | ||
3382 | |||
3383 | spin_unlock_bh(&sky2->phy_lock); | ||
3384 | interrupted = msleep_interruptible(250); | ||
3385 | spin_lock_bh(&sky2->phy_lock); | ||
3386 | |||
3387 | ms -= 250; | ||
3388 | } | ||
3389 | 3390 | ||
3390 | /* resume regularly scheduled programming */ | 3391 | for (i = 0; i < data; i++) { |
3391 | if (hw->chip_id == CHIP_ID_YUKON_XL) { | 3392 | sky2_led(sky2, MO_LED_ON); |
3392 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | 3393 | if (msleep_interruptible(500)) |
3393 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | 3394 | break; |
3394 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl); | 3395 | sky2_led(sky2, MO_LED_OFF); |
3395 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | 3396 | if (msleep_interruptible(500)) |
3396 | } else { | 3397 | break; |
3397 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); | ||
3398 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | ||
3399 | } | 3398 | } |
3400 | spin_unlock_bh(&sky2->phy_lock); | 3399 | sky2_led(sky2, MO_LED_NORM); |
3401 | 3400 | ||
3402 | return 0; | 3401 | return 0; |
3403 | } | 3402 | } |
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h index 5ab5c1c7c5aa..7bb3ba9bcbd8 100644 --- a/drivers/net/sky2.h +++ b/drivers/net/sky2.h | |||
@@ -1318,18 +1318,21 @@ enum { | |||
1318 | BLINK_670MS = 4,/* 670 ms */ | 1318 | BLINK_670MS = 4,/* 670 ms */ |
1319 | }; | 1319 | }; |
1320 | 1320 | ||
1321 | /**** PHY_MARV_LED_OVER 16 bit r/w LED control */ | 1321 | /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/ |
1322 | enum { | 1322 | #define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */ |
1323 | PHY_M_LED_MO_DUP = 3<<10,/* Bit 11..10: Duplex */ | 1323 | |
1324 | PHY_M_LED_MO_10 = 3<<8, /* Bit 9.. 8: Link 10 */ | 1324 | #define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */ |
1325 | PHY_M_LED_MO_100 = 3<<6, /* Bit 7.. 6: Link 100 */ | 1325 | #define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */ |
1326 | PHY_M_LED_MO_1000 = 3<<4, /* Bit 5.. 4: Link 1000 */ | 1326 | #define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */ |
1327 | PHY_M_LED_MO_RX = 3<<2, /* Bit 3.. 2: Rx */ | 1327 | #define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */ |
1328 | PHY_M_LED_MO_TX = 3<<0, /* Bit 1.. 0: Tx */ | 1328 | #define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */ |
1329 | 1329 | #define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */ | |
1330 | PHY_M_LED_ALL = PHY_M_LED_MO_DUP | PHY_M_LED_MO_10 | 1330 | |
1331 | | PHY_M_LED_MO_100 | PHY_M_LED_MO_1000 | 1331 | enum led_mode { |
1332 | | PHY_M_LED_MO_RX, | 1332 | MO_LED_NORM = 0, |
1333 | MO_LED_BLINK = 1, | ||
1334 | MO_LED_OFF = 2, | ||
1335 | MO_LED_ON = 3, | ||
1333 | }; | 1336 | }; |
1334 | 1337 | ||
1335 | /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/ | 1338 | /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/ |
diff --git a/drivers/net/tlan.c b/drivers/net/tlan.c index 3af5b92b48c8..0166407d7061 100644 --- a/drivers/net/tlan.c +++ b/drivers/net/tlan.c | |||
@@ -1400,7 +1400,7 @@ static void TLan_SetMulticastList( struct net_device *dev ) | |||
1400 | * | 1400 | * |
1401 | **************************************************************/ | 1401 | **************************************************************/ |
1402 | 1402 | ||
1403 | u32 TLan_HandleInvalid( struct net_device *dev, u16 host_int ) | 1403 | static u32 TLan_HandleInvalid( struct net_device *dev, u16 host_int ) |
1404 | { | 1404 | { |
1405 | /* printk( "TLAN: Invalid interrupt on %s.\n", dev->name ); */ | 1405 | /* printk( "TLAN: Invalid interrupt on %s.\n", dev->name ); */ |
1406 | return 0; | 1406 | return 0; |
@@ -1432,7 +1432,7 @@ u32 TLan_HandleInvalid( struct net_device *dev, u16 host_int ) | |||
1432 | * | 1432 | * |
1433 | **************************************************************/ | 1433 | **************************************************************/ |
1434 | 1434 | ||
1435 | u32 TLan_HandleTxEOF( struct net_device *dev, u16 host_int ) | 1435 | static u32 TLan_HandleTxEOF( struct net_device *dev, u16 host_int ) |
1436 | { | 1436 | { |
1437 | TLanPrivateInfo *priv = netdev_priv(dev); | 1437 | TLanPrivateInfo *priv = netdev_priv(dev); |
1438 | int eoc = 0; | 1438 | int eoc = 0; |
@@ -1518,7 +1518,7 @@ u32 TLan_HandleTxEOF( struct net_device *dev, u16 host_int ) | |||
1518 | * | 1518 | * |
1519 | **************************************************************/ | 1519 | **************************************************************/ |
1520 | 1520 | ||
1521 | u32 TLan_HandleStatOverflow( struct net_device *dev, u16 host_int ) | 1521 | static u32 TLan_HandleStatOverflow( struct net_device *dev, u16 host_int ) |
1522 | { | 1522 | { |
1523 | TLan_ReadAndClearStats( dev, TLAN_RECORD ); | 1523 | TLan_ReadAndClearStats( dev, TLAN_RECORD ); |
1524 | 1524 | ||
@@ -1554,7 +1554,7 @@ u32 TLan_HandleStatOverflow( struct net_device *dev, u16 host_int ) | |||
1554 | * | 1554 | * |
1555 | **************************************************************/ | 1555 | **************************************************************/ |
1556 | 1556 | ||
1557 | u32 TLan_HandleRxEOF( struct net_device *dev, u16 host_int ) | 1557 | static u32 TLan_HandleRxEOF( struct net_device *dev, u16 host_int ) |
1558 | { | 1558 | { |
1559 | TLanPrivateInfo *priv = netdev_priv(dev); | 1559 | TLanPrivateInfo *priv = netdev_priv(dev); |
1560 | u32 ack = 0; | 1560 | u32 ack = 0; |
@@ -1689,7 +1689,7 @@ u32 TLan_HandleRxEOF( struct net_device *dev, u16 host_int ) | |||
1689 | * | 1689 | * |
1690 | **************************************************************/ | 1690 | **************************************************************/ |
1691 | 1691 | ||
1692 | u32 TLan_HandleDummy( struct net_device *dev, u16 host_int ) | 1692 | static u32 TLan_HandleDummy( struct net_device *dev, u16 host_int ) |
1693 | { | 1693 | { |
1694 | printk( "TLAN: Test interrupt on %s.\n", dev->name ); | 1694 | printk( "TLAN: Test interrupt on %s.\n", dev->name ); |
1695 | return 1; | 1695 | return 1; |
@@ -1719,7 +1719,7 @@ u32 TLan_HandleDummy( struct net_device *dev, u16 host_int ) | |||
1719 | * | 1719 | * |
1720 | **************************************************************/ | 1720 | **************************************************************/ |
1721 | 1721 | ||
1722 | u32 TLan_HandleTxEOC( struct net_device *dev, u16 host_int ) | 1722 | static u32 TLan_HandleTxEOC( struct net_device *dev, u16 host_int ) |
1723 | { | 1723 | { |
1724 | TLanPrivateInfo *priv = netdev_priv(dev); | 1724 | TLanPrivateInfo *priv = netdev_priv(dev); |
1725 | TLanList *head_list; | 1725 | TLanList *head_list; |
@@ -1767,7 +1767,7 @@ u32 TLan_HandleTxEOC( struct net_device *dev, u16 host_int ) | |||
1767 | * | 1767 | * |
1768 | **************************************************************/ | 1768 | **************************************************************/ |
1769 | 1769 | ||
1770 | u32 TLan_HandleStatusCheck( struct net_device *dev, u16 host_int ) | 1770 | static u32 TLan_HandleStatusCheck( struct net_device *dev, u16 host_int ) |
1771 | { | 1771 | { |
1772 | TLanPrivateInfo *priv = netdev_priv(dev); | 1772 | TLanPrivateInfo *priv = netdev_priv(dev); |
1773 | u32 ack; | 1773 | u32 ack; |
@@ -1842,7 +1842,7 @@ u32 TLan_HandleStatusCheck( struct net_device *dev, u16 host_int ) | |||
1842 | * | 1842 | * |
1843 | **************************************************************/ | 1843 | **************************************************************/ |
1844 | 1844 | ||
1845 | u32 TLan_HandleRxEOC( struct net_device *dev, u16 host_int ) | 1845 | static u32 TLan_HandleRxEOC( struct net_device *dev, u16 host_int ) |
1846 | { | 1846 | { |
1847 | TLanPrivateInfo *priv = netdev_priv(dev); | 1847 | TLanPrivateInfo *priv = netdev_priv(dev); |
1848 | dma_addr_t head_list_phys; | 1848 | dma_addr_t head_list_phys; |
@@ -1902,7 +1902,7 @@ u32 TLan_HandleRxEOC( struct net_device *dev, u16 host_int ) | |||
1902 | * | 1902 | * |
1903 | **************************************************************/ | 1903 | **************************************************************/ |
1904 | 1904 | ||
1905 | void TLan_Timer( unsigned long data ) | 1905 | static void TLan_Timer( unsigned long data ) |
1906 | { | 1906 | { |
1907 | struct net_device *dev = (struct net_device *) data; | 1907 | struct net_device *dev = (struct net_device *) data; |
1908 | TLanPrivateInfo *priv = netdev_priv(dev); | 1908 | TLanPrivateInfo *priv = netdev_priv(dev); |
@@ -1983,7 +1983,7 @@ void TLan_Timer( unsigned long data ) | |||
1983 | * | 1983 | * |
1984 | **************************************************************/ | 1984 | **************************************************************/ |
1985 | 1985 | ||
1986 | void TLan_ResetLists( struct net_device *dev ) | 1986 | static void TLan_ResetLists( struct net_device *dev ) |
1987 | { | 1987 | { |
1988 | TLanPrivateInfo *priv = netdev_priv(dev); | 1988 | TLanPrivateInfo *priv = netdev_priv(dev); |
1989 | int i; | 1989 | int i; |
@@ -2043,7 +2043,7 @@ void TLan_ResetLists( struct net_device *dev ) | |||
2043 | } /* TLan_ResetLists */ | 2043 | } /* TLan_ResetLists */ |
2044 | 2044 | ||
2045 | 2045 | ||
2046 | void TLan_FreeLists( struct net_device *dev ) | 2046 | static void TLan_FreeLists( struct net_device *dev ) |
2047 | { | 2047 | { |
2048 | TLanPrivateInfo *priv = netdev_priv(dev); | 2048 | TLanPrivateInfo *priv = netdev_priv(dev); |
2049 | int i; | 2049 | int i; |
@@ -2092,7 +2092,7 @@ void TLan_FreeLists( struct net_device *dev ) | |||
2092 | * | 2092 | * |
2093 | **************************************************************/ | 2093 | **************************************************************/ |
2094 | 2094 | ||
2095 | void TLan_PrintDio( u16 io_base ) | 2095 | static void TLan_PrintDio( u16 io_base ) |
2096 | { | 2096 | { |
2097 | u32 data0, data1; | 2097 | u32 data0, data1; |
2098 | int i; | 2098 | int i; |
@@ -2127,7 +2127,7 @@ void TLan_PrintDio( u16 io_base ) | |||
2127 | * | 2127 | * |
2128 | **************************************************************/ | 2128 | **************************************************************/ |
2129 | 2129 | ||
2130 | void TLan_PrintList( TLanList *list, char *type, int num) | 2130 | static void TLan_PrintList( TLanList *list, char *type, int num) |
2131 | { | 2131 | { |
2132 | int i; | 2132 | int i; |
2133 | 2133 | ||
@@ -2163,7 +2163,7 @@ void TLan_PrintList( TLanList *list, char *type, int num) | |||
2163 | * | 2163 | * |
2164 | **************************************************************/ | 2164 | **************************************************************/ |
2165 | 2165 | ||
2166 | void TLan_ReadAndClearStats( struct net_device *dev, int record ) | 2166 | static void TLan_ReadAndClearStats( struct net_device *dev, int record ) |
2167 | { | 2167 | { |
2168 | TLanPrivateInfo *priv = netdev_priv(dev); | 2168 | TLanPrivateInfo *priv = netdev_priv(dev); |
2169 | u32 tx_good, tx_under; | 2169 | u32 tx_good, tx_under; |
@@ -2238,7 +2238,7 @@ void TLan_ReadAndClearStats( struct net_device *dev, int record ) | |||
2238 | * | 2238 | * |
2239 | **************************************************************/ | 2239 | **************************************************************/ |
2240 | 2240 | ||
2241 | void | 2241 | static void |
2242 | TLan_ResetAdapter( struct net_device *dev ) | 2242 | TLan_ResetAdapter( struct net_device *dev ) |
2243 | { | 2243 | { |
2244 | TLanPrivateInfo *priv = netdev_priv(dev); | 2244 | TLanPrivateInfo *priv = netdev_priv(dev); |
@@ -2324,7 +2324,7 @@ TLan_ResetAdapter( struct net_device *dev ) | |||
2324 | 2324 | ||
2325 | 2325 | ||
2326 | 2326 | ||
2327 | void | 2327 | static void |
2328 | TLan_FinishReset( struct net_device *dev ) | 2328 | TLan_FinishReset( struct net_device *dev ) |
2329 | { | 2329 | { |
2330 | TLanPrivateInfo *priv = netdev_priv(dev); | 2330 | TLanPrivateInfo *priv = netdev_priv(dev); |
@@ -2448,7 +2448,7 @@ TLan_FinishReset( struct net_device *dev ) | |||
2448 | * | 2448 | * |
2449 | **************************************************************/ | 2449 | **************************************************************/ |
2450 | 2450 | ||
2451 | void TLan_SetMac( struct net_device *dev, int areg, char *mac ) | 2451 | static void TLan_SetMac( struct net_device *dev, int areg, char *mac ) |
2452 | { | 2452 | { |
2453 | int i; | 2453 | int i; |
2454 | 2454 | ||
@@ -2490,7 +2490,7 @@ void TLan_SetMac( struct net_device *dev, int areg, char *mac ) | |||
2490 | * | 2490 | * |
2491 | ********************************************************************/ | 2491 | ********************************************************************/ |
2492 | 2492 | ||
2493 | void TLan_PhyPrint( struct net_device *dev ) | 2493 | static void TLan_PhyPrint( struct net_device *dev ) |
2494 | { | 2494 | { |
2495 | TLanPrivateInfo *priv = netdev_priv(dev); | 2495 | TLanPrivateInfo *priv = netdev_priv(dev); |
2496 | u16 i, data0, data1, data2, data3, phy; | 2496 | u16 i, data0, data1, data2, data3, phy; |
@@ -2539,7 +2539,7 @@ void TLan_PhyPrint( struct net_device *dev ) | |||
2539 | * | 2539 | * |
2540 | ********************************************************************/ | 2540 | ********************************************************************/ |
2541 | 2541 | ||
2542 | void TLan_PhyDetect( struct net_device *dev ) | 2542 | static void TLan_PhyDetect( struct net_device *dev ) |
2543 | { | 2543 | { |
2544 | TLanPrivateInfo *priv = netdev_priv(dev); | 2544 | TLanPrivateInfo *priv = netdev_priv(dev); |
2545 | u16 control; | 2545 | u16 control; |
@@ -2586,7 +2586,7 @@ void TLan_PhyDetect( struct net_device *dev ) | |||
2586 | 2586 | ||
2587 | 2587 | ||
2588 | 2588 | ||
2589 | void TLan_PhyPowerDown( struct net_device *dev ) | 2589 | static void TLan_PhyPowerDown( struct net_device *dev ) |
2590 | { | 2590 | { |
2591 | TLanPrivateInfo *priv = netdev_priv(dev); | 2591 | TLanPrivateInfo *priv = netdev_priv(dev); |
2592 | u16 value; | 2592 | u16 value; |
@@ -2611,7 +2611,7 @@ void TLan_PhyPowerDown( struct net_device *dev ) | |||
2611 | 2611 | ||
2612 | 2612 | ||
2613 | 2613 | ||
2614 | void TLan_PhyPowerUp( struct net_device *dev ) | 2614 | static void TLan_PhyPowerUp( struct net_device *dev ) |
2615 | { | 2615 | { |
2616 | TLanPrivateInfo *priv = netdev_priv(dev); | 2616 | TLanPrivateInfo *priv = netdev_priv(dev); |
2617 | u16 value; | 2617 | u16 value; |
@@ -2632,7 +2632,7 @@ void TLan_PhyPowerUp( struct net_device *dev ) | |||
2632 | 2632 | ||
2633 | 2633 | ||
2634 | 2634 | ||
2635 | void TLan_PhyReset( struct net_device *dev ) | 2635 | static void TLan_PhyReset( struct net_device *dev ) |
2636 | { | 2636 | { |
2637 | TLanPrivateInfo *priv = netdev_priv(dev); | 2637 | TLanPrivateInfo *priv = netdev_priv(dev); |
2638 | u16 phy; | 2638 | u16 phy; |
@@ -2660,7 +2660,7 @@ void TLan_PhyReset( struct net_device *dev ) | |||
2660 | 2660 | ||
2661 | 2661 | ||
2662 | 2662 | ||
2663 | void TLan_PhyStartLink( struct net_device *dev ) | 2663 | static void TLan_PhyStartLink( struct net_device *dev ) |
2664 | { | 2664 | { |
2665 | TLanPrivateInfo *priv = netdev_priv(dev); | 2665 | TLanPrivateInfo *priv = netdev_priv(dev); |
2666 | u16 ability; | 2666 | u16 ability; |
@@ -2747,7 +2747,7 @@ void TLan_PhyStartLink( struct net_device *dev ) | |||
2747 | 2747 | ||
2748 | 2748 | ||
2749 | 2749 | ||
2750 | void TLan_PhyFinishAutoNeg( struct net_device *dev ) | 2750 | static void TLan_PhyFinishAutoNeg( struct net_device *dev ) |
2751 | { | 2751 | { |
2752 | TLanPrivateInfo *priv = netdev_priv(dev); | 2752 | TLanPrivateInfo *priv = netdev_priv(dev); |
2753 | u16 an_adv; | 2753 | u16 an_adv; |
@@ -2903,7 +2903,7 @@ void TLan_PhyMonitor( struct net_device *dev ) | |||
2903 | * | 2903 | * |
2904 | **************************************************************/ | 2904 | **************************************************************/ |
2905 | 2905 | ||
2906 | int TLan_MiiReadReg( struct net_device *dev, u16 phy, u16 reg, u16 *val ) | 2906 | static int TLan_MiiReadReg( struct net_device *dev, u16 phy, u16 reg, u16 *val ) |
2907 | { | 2907 | { |
2908 | u8 nack; | 2908 | u8 nack; |
2909 | u16 sio, tmp; | 2909 | u16 sio, tmp; |
@@ -2993,7 +2993,7 @@ int TLan_MiiReadReg( struct net_device *dev, u16 phy, u16 reg, u16 *val ) | |||
2993 | * | 2993 | * |
2994 | **************************************************************/ | 2994 | **************************************************************/ |
2995 | 2995 | ||
2996 | void TLan_MiiSendData( u16 base_port, u32 data, unsigned num_bits ) | 2996 | static void TLan_MiiSendData( u16 base_port, u32 data, unsigned num_bits ) |
2997 | { | 2997 | { |
2998 | u16 sio; | 2998 | u16 sio; |
2999 | u32 i; | 2999 | u32 i; |
@@ -3035,7 +3035,7 @@ void TLan_MiiSendData( u16 base_port, u32 data, unsigned num_bits ) | |||
3035 | * | 3035 | * |
3036 | **************************************************************/ | 3036 | **************************************************************/ |
3037 | 3037 | ||
3038 | void TLan_MiiSync( u16 base_port ) | 3038 | static void TLan_MiiSync( u16 base_port ) |
3039 | { | 3039 | { |
3040 | int i; | 3040 | int i; |
3041 | u16 sio; | 3041 | u16 sio; |
@@ -3074,7 +3074,7 @@ void TLan_MiiSync( u16 base_port ) | |||
3074 | * | 3074 | * |
3075 | **************************************************************/ | 3075 | **************************************************************/ |
3076 | 3076 | ||
3077 | void TLan_MiiWriteReg( struct net_device *dev, u16 phy, u16 reg, u16 val ) | 3077 | static void TLan_MiiWriteReg( struct net_device *dev, u16 phy, u16 reg, u16 val ) |
3078 | { | 3078 | { |
3079 | u16 sio; | 3079 | u16 sio; |
3080 | int minten; | 3080 | int minten; |
@@ -3144,7 +3144,7 @@ void TLan_MiiWriteReg( struct net_device *dev, u16 phy, u16 reg, u16 val ) | |||
3144 | * | 3144 | * |
3145 | **************************************************************/ | 3145 | **************************************************************/ |
3146 | 3146 | ||
3147 | void TLan_EeSendStart( u16 io_base ) | 3147 | static void TLan_EeSendStart( u16 io_base ) |
3148 | { | 3148 | { |
3149 | u16 sio; | 3149 | u16 sio; |
3150 | 3150 | ||
@@ -3184,7 +3184,7 @@ void TLan_EeSendStart( u16 io_base ) | |||
3184 | * | 3184 | * |
3185 | **************************************************************/ | 3185 | **************************************************************/ |
3186 | 3186 | ||
3187 | int TLan_EeSendByte( u16 io_base, u8 data, int stop ) | 3187 | static int TLan_EeSendByte( u16 io_base, u8 data, int stop ) |
3188 | { | 3188 | { |
3189 | int err; | 3189 | int err; |
3190 | u8 place; | 3190 | u8 place; |
@@ -3245,7 +3245,7 @@ int TLan_EeSendByte( u16 io_base, u8 data, int stop ) | |||
3245 | * | 3245 | * |
3246 | **************************************************************/ | 3246 | **************************************************************/ |
3247 | 3247 | ||
3248 | void TLan_EeReceiveByte( u16 io_base, u8 *data, int stop ) | 3248 | static void TLan_EeReceiveByte( u16 io_base, u8 *data, int stop ) |
3249 | { | 3249 | { |
3250 | u8 place; | 3250 | u8 place; |
3251 | u16 sio; | 3251 | u16 sio; |
@@ -3303,7 +3303,7 @@ void TLan_EeReceiveByte( u16 io_base, u8 *data, int stop ) | |||
3303 | * | 3303 | * |
3304 | **************************************************************/ | 3304 | **************************************************************/ |
3305 | 3305 | ||
3306 | int TLan_EeReadByte( struct net_device *dev, u8 ee_addr, u8 *data ) | 3306 | static int TLan_EeReadByte( struct net_device *dev, u8 ee_addr, u8 *data ) |
3307 | { | 3307 | { |
3308 | int err; | 3308 | int err; |
3309 | TLanPrivateInfo *priv = netdev_priv(dev); | 3309 | TLanPrivateInfo *priv = netdev_priv(dev); |
diff --git a/drivers/net/tulip/de2104x.c b/drivers/net/tulip/de2104x.c index 77d9dd7ea34f..567c62757e9d 100644 --- a/drivers/net/tulip/de2104x.c +++ b/drivers/net/tulip/de2104x.c | |||
@@ -910,7 +910,8 @@ static void de_set_media (struct de_private *de) | |||
910 | unsigned media = de->media_type; | 910 | unsigned media = de->media_type; |
911 | u32 macmode = dr32(MacMode); | 911 | u32 macmode = dr32(MacMode); |
912 | 912 | ||
913 | BUG_ON(de_is_running(de)); | 913 | if (de_is_running(de)) |
914 | printk(KERN_WARNING "%s: chip is running while changing media!\n", de->dev->name); | ||
914 | 915 | ||
915 | if (de->de21040) | 916 | if (de->de21040) |
916 | dw32(CSR11, FULL_DUPLEX_MAGIC); | 917 | dw32(CSR11, FULL_DUPLEX_MAGIC); |
diff --git a/drivers/net/tulip/uli526x.c b/drivers/net/tulip/uli526x.c index a7afeea156bd..a59c1f224aa8 100644 --- a/drivers/net/tulip/uli526x.c +++ b/drivers/net/tulip/uli526x.c | |||
@@ -482,9 +482,11 @@ static void uli526x_init(struct net_device *dev) | |||
482 | struct uli526x_board_info *db = netdev_priv(dev); | 482 | struct uli526x_board_info *db = netdev_priv(dev); |
483 | unsigned long ioaddr = db->ioaddr; | 483 | unsigned long ioaddr = db->ioaddr; |
484 | u8 phy_tmp; | 484 | u8 phy_tmp; |
485 | u8 timeout; | ||
485 | u16 phy_value; | 486 | u16 phy_value; |
486 | u16 phy_reg_reset; | 487 | u16 phy_reg_reset; |
487 | 488 | ||
489 | |||
488 | ULI526X_DBUG(0, "uli526x_init()", 0); | 490 | ULI526X_DBUG(0, "uli526x_init()", 0); |
489 | 491 | ||
490 | /* Reset M526x MAC controller */ | 492 | /* Reset M526x MAC controller */ |
@@ -509,11 +511,19 @@ static void uli526x_init(struct net_device *dev) | |||
509 | /* Parser SROM and media mode */ | 511 | /* Parser SROM and media mode */ |
510 | db->media_mode = uli526x_media_mode; | 512 | db->media_mode = uli526x_media_mode; |
511 | 513 | ||
512 | /* Phyxcer capability setting */ | 514 | /* phyxcer capability setting */ |
513 | phy_reg_reset = phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id); | 515 | phy_reg_reset = phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id); |
514 | phy_reg_reset = (phy_reg_reset | 0x8000); | 516 | phy_reg_reset = (phy_reg_reset | 0x8000); |
515 | phy_write(db->ioaddr, db->phy_addr, 0, phy_reg_reset, db->chip_id); | 517 | phy_write(db->ioaddr, db->phy_addr, 0, phy_reg_reset, db->chip_id); |
518 | |||
519 | /* See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management | ||
520 | * functions") or phy data sheet for details on phy reset | ||
521 | */ | ||
516 | udelay(500); | 522 | udelay(500); |
523 | timeout = 10; | ||
524 | while (timeout-- && | ||
525 | phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id) & 0x8000) | ||
526 | udelay(100); | ||
517 | 527 | ||
518 | /* Process Phyxcer Media Mode */ | 528 | /* Process Phyxcer Media Mode */ |
519 | uli526x_set_phyxcer(db); | 529 | uli526x_set_phyxcer(db); |
diff --git a/drivers/net/tun.c b/drivers/net/tun.c index 038c1ef94d2e..7b816a032957 100644 --- a/drivers/net/tun.c +++ b/drivers/net/tun.c | |||
@@ -663,7 +663,11 @@ static int tun_chr_ioctl(struct inode *inode, struct file *file, | |||
663 | case SIOCSIFHWADDR: | 663 | case SIOCSIFHWADDR: |
664 | { | 664 | { |
665 | /* try to set the actual net device's hw address */ | 665 | /* try to set the actual net device's hw address */ |
666 | int ret = dev_set_mac_address(tun->dev, &ifr.ifr_hwaddr); | 666 | int ret; |
667 | |||
668 | rtnl_lock(); | ||
669 | ret = dev_set_mac_address(tun->dev, &ifr.ifr_hwaddr); | ||
670 | rtnl_unlock(); | ||
667 | 671 | ||
668 | if (ret == 0) { | 672 | if (ret == 0) { |
669 | /** Set the character device's hardware address. This is used when | 673 | /** Set the character device's hardware address. This is used when |
diff --git a/drivers/net/via-rhine.c b/drivers/net/via-rhine.c index 7c851b1e6daa..8c9d6ae2bb31 100644 --- a/drivers/net/via-rhine.c +++ b/drivers/net/via-rhine.c | |||
@@ -1893,7 +1893,7 @@ static void rhine_shutdown (struct pci_dev *pdev) | |||
1893 | 1893 | ||
1894 | /* Make sure we use pattern 0, 1 and not 4, 5 */ | 1894 | /* Make sure we use pattern 0, 1 and not 4, 5 */ |
1895 | if (rp->quirks & rq6patterns) | 1895 | if (rp->quirks & rq6patterns) |
1896 | iowrite8(0x04, ioaddr + 0xA7); | 1896 | iowrite8(0x04, ioaddr + WOLcgClr); |
1897 | 1897 | ||
1898 | if (rp->wolopts & WAKE_MAGIC) { | 1898 | if (rp->wolopts & WAKE_MAGIC) { |
1899 | iowrite8(WOLmagic, ioaddr + WOLcrSet); | 1899 | iowrite8(WOLmagic, ioaddr + WOLcrSet); |
diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c index fdc23678117b..19fd4cb0ddf8 100644 --- a/drivers/net/virtio_net.c +++ b/drivers/net/virtio_net.c | |||
@@ -361,6 +361,7 @@ static int virtnet_probe(struct virtio_device *vdev) | |||
361 | netif_napi_add(dev, &vi->napi, virtnet_poll, napi_weight); | 361 | netif_napi_add(dev, &vi->napi, virtnet_poll, napi_weight); |
362 | vi->dev = dev; | 362 | vi->dev = dev; |
363 | vi->vdev = vdev; | 363 | vi->vdev = vdev; |
364 | vdev->priv = vi; | ||
364 | 365 | ||
365 | /* We expect two virtqueues, receive then send. */ | 366 | /* We expect two virtqueues, receive then send. */ |
366 | vi->rvq = vdev->config->find_vq(vdev, 0, skb_recv_done); | 367 | vi->rvq = vdev->config->find_vq(vdev, 0, skb_recv_done); |
@@ -395,7 +396,6 @@ static int virtnet_probe(struct virtio_device *vdev) | |||
395 | } | 396 | } |
396 | 397 | ||
397 | pr_debug("virtnet: registered device %s\n", dev->name); | 398 | pr_debug("virtnet: registered device %s\n", dev->name); |
398 | vdev->priv = vi; | ||
399 | return 0; | 399 | return 0; |
400 | 400 | ||
401 | unregister: | 401 | unregister: |
diff --git a/drivers/net/wan/sbni.c b/drivers/net/wan/sbni.c index 15d5c58e57bc..e59255a155a9 100644 --- a/drivers/net/wan/sbni.c +++ b/drivers/net/wan/sbni.c | |||
@@ -751,7 +751,7 @@ upload_data( struct net_device *dev, unsigned framelen, unsigned frameno, | |||
751 | } | 751 | } |
752 | 752 | ||
753 | 753 | ||
754 | static __inline void | 754 | static inline void |
755 | send_complete( struct net_local *nl ) | 755 | send_complete( struct net_local *nl ) |
756 | { | 756 | { |
757 | #ifdef CONFIG_SBNI_MULTILINE | 757 | #ifdef CONFIG_SBNI_MULTILINE |
diff --git a/drivers/net/wireless/b43/Kconfig b/drivers/net/wireless/b43/Kconfig index 1a2141dabdc7..8bc4bc4c330e 100644 --- a/drivers/net/wireless/b43/Kconfig +++ b/drivers/net/wireless/b43/Kconfig | |||
@@ -32,6 +32,7 @@ config B43_PCI_AUTOSELECT | |||
32 | bool | 32 | bool |
33 | depends on B43 && SSB_PCIHOST_POSSIBLE | 33 | depends on B43 && SSB_PCIHOST_POSSIBLE |
34 | select SSB_PCIHOST | 34 | select SSB_PCIHOST |
35 | select SSB_B43_PCI_BRIDGE | ||
35 | default y | 36 | default y |
36 | 37 | ||
37 | # Auto-select SSB PCICORE driver, if possible | 38 | # Auto-select SSB PCICORE driver, if possible |
diff --git a/drivers/net/wireless/b43legacy/Kconfig b/drivers/net/wireless/b43legacy/Kconfig index 6745579ba96d..13c65faf0247 100644 --- a/drivers/net/wireless/b43legacy/Kconfig +++ b/drivers/net/wireless/b43legacy/Kconfig | |||
@@ -25,6 +25,7 @@ config B43LEGACY_PCI_AUTOSELECT | |||
25 | bool | 25 | bool |
26 | depends on B43LEGACY && SSB_PCIHOST_POSSIBLE | 26 | depends on B43LEGACY && SSB_PCIHOST_POSSIBLE |
27 | select SSB_PCIHOST | 27 | select SSB_PCIHOST |
28 | select SSB_B43_PCI_BRIDGE | ||
28 | default y | 29 | default y |
29 | 30 | ||
30 | # Auto-select SSB PCICORE driver, if possible | 31 | # Auto-select SSB PCICORE driver, if possible |
diff --git a/drivers/net/wireless/b43legacy/main.c b/drivers/net/wireless/b43legacy/main.c index c39de422e220..5f3f34e1dbfd 100644 --- a/drivers/net/wireless/b43legacy/main.c +++ b/drivers/net/wireless/b43legacy/main.c | |||
@@ -3829,7 +3829,7 @@ static void b43legacy_print_driverinfo(void) | |||
3829 | #ifdef CONFIG_B43LEGACY_DMA | 3829 | #ifdef CONFIG_B43LEGACY_DMA |
3830 | feat_dma = "D"; | 3830 | feat_dma = "D"; |
3831 | #endif | 3831 | #endif |
3832 | printk(KERN_INFO "Broadcom 43xx driver loaded " | 3832 | printk(KERN_INFO "Broadcom 43xx-legacy driver loaded " |
3833 | "[ Features: %s%s%s%s%s, Firmware-ID: " | 3833 | "[ Features: %s%s%s%s%s, Firmware-ID: " |
3834 | B43legacy_SUPPORTED_FIRMWARE_ID " ]\n", | 3834 | B43legacy_SUPPORTED_FIRMWARE_ID " ]\n", |
3835 | feat_pci, feat_leds, feat_rfkill, feat_pio, feat_dma); | 3835 | feat_pci, feat_leds, feat_rfkill, feat_pio, feat_dma); |
diff --git a/drivers/net/wireless/bcm43xx/Kconfig b/drivers/net/wireless/bcm43xx/Kconfig index 0159701e8456..afb8f4305c24 100644 --- a/drivers/net/wireless/bcm43xx/Kconfig +++ b/drivers/net/wireless/bcm43xx/Kconfig | |||
@@ -1,6 +1,6 @@ | |||
1 | config BCM43XX | 1 | config BCM43XX |
2 | tristate "Broadcom BCM43xx wireless support (DEPRECATED)" | 2 | tristate "Broadcom BCM43xx wireless support (DEPRECATED)" |
3 | depends on PCI && IEEE80211 && IEEE80211_SOFTMAC && WLAN_80211 && EXPERIMENTAL | 3 | depends on PCI && IEEE80211 && IEEE80211_SOFTMAC && WLAN_80211 && (!SSB_B43_PCI_BRIDGE || SSB != y) && EXPERIMENTAL |
4 | select WIRELESS_EXT | 4 | select WIRELESS_EXT |
5 | select FW_LOADER | 5 | select FW_LOADER |
6 | select HW_RANDOM | 6 | select HW_RANDOM |
diff --git a/drivers/net/wireless/libertas/cmd.c b/drivers/net/wireless/libertas/cmd.c index eab020338fde..b3c1acbcc655 100644 --- a/drivers/net/wireless/libertas/cmd.c +++ b/drivers/net/wireless/libertas/cmd.c | |||
@@ -1040,7 +1040,6 @@ int lbs_mesh_access(struct lbs_private *priv, uint16_t cmd_action, | |||
1040 | lbs_deb_leave(LBS_DEB_CMD); | 1040 | lbs_deb_leave(LBS_DEB_CMD); |
1041 | return ret; | 1041 | return ret; |
1042 | } | 1042 | } |
1043 | EXPORT_SYMBOL_GPL(lbs_mesh_access); | ||
1044 | 1043 | ||
1045 | int lbs_mesh_config(struct lbs_private *priv, uint16_t enable, uint16_t chan) | 1044 | int lbs_mesh_config(struct lbs_private *priv, uint16_t enable, uint16_t chan) |
1046 | { | 1045 | { |
@@ -1576,7 +1575,6 @@ done: | |||
1576 | lbs_deb_leave_args(LBS_DEB_HOST, "ret %d", ret); | 1575 | lbs_deb_leave_args(LBS_DEB_HOST, "ret %d", ret); |
1577 | return ret; | 1576 | return ret; |
1578 | } | 1577 | } |
1579 | EXPORT_SYMBOL_GPL(lbs_prepare_and_send_command); | ||
1580 | 1578 | ||
1581 | /** | 1579 | /** |
1582 | * @brief This function allocates the command buffer and link | 1580 | * @brief This function allocates the command buffer and link |
diff --git a/drivers/net/wireless/libertas/cmdresp.c b/drivers/net/wireless/libertas/cmdresp.c index 159216a91903..f0ef7081bdeb 100644 --- a/drivers/net/wireless/libertas/cmdresp.c +++ b/drivers/net/wireless/libertas/cmdresp.c | |||
@@ -562,9 +562,7 @@ int lbs_process_rx_command(struct lbs_private *priv) | |||
562 | } | 562 | } |
563 | 563 | ||
564 | resp = (void *)priv->upld_buf; | 564 | resp = (void *)priv->upld_buf; |
565 | 565 | curcmd = le16_to_cpu(priv->cur_cmd->cmdbuf->command); | |
566 | curcmd = le16_to_cpu(resp->command); | ||
567 | |||
568 | respcmd = le16_to_cpu(resp->command); | 566 | respcmd = le16_to_cpu(resp->command); |
569 | result = le16_to_cpu(resp->result); | 567 | result = le16_to_cpu(resp->result); |
570 | 568 | ||
@@ -572,15 +570,15 @@ int lbs_process_rx_command(struct lbs_private *priv) | |||
572 | respcmd, le16_to_cpu(resp->seqnum), priv->upld_len, jiffies); | 570 | respcmd, le16_to_cpu(resp->seqnum), priv->upld_len, jiffies); |
573 | lbs_deb_hex(LBS_DEB_HOST, "CMD_RESP", (void *) resp, priv->upld_len); | 571 | lbs_deb_hex(LBS_DEB_HOST, "CMD_RESP", (void *) resp, priv->upld_len); |
574 | 572 | ||
575 | if (resp->seqnum != resp->seqnum) { | 573 | if (resp->seqnum != priv->cur_cmd->cmdbuf->seqnum) { |
576 | lbs_pr_info("Received CMD_RESP with invalid sequence %d (expected %d)\n", | 574 | lbs_pr_info("Received CMD_RESP with invalid sequence %d (expected %d)\n", |
577 | le16_to_cpu(resp->seqnum), le16_to_cpu(resp->seqnum)); | 575 | le16_to_cpu(resp->seqnum), le16_to_cpu(priv->cur_cmd->cmdbuf->seqnum)); |
578 | spin_unlock_irqrestore(&priv->driver_lock, flags); | 576 | spin_unlock_irqrestore(&priv->driver_lock, flags); |
579 | ret = -1; | 577 | ret = -1; |
580 | goto done; | 578 | goto done; |
581 | } | 579 | } |
582 | if (respcmd != CMD_RET(curcmd) && | 580 | if (respcmd != CMD_RET(curcmd) && |
583 | respcmd != CMD_802_11_ASSOCIATE && curcmd != CMD_RET_802_11_ASSOCIATE) { | 581 | respcmd != CMD_RET_802_11_ASSOCIATE && curcmd != CMD_802_11_ASSOCIATE) { |
584 | lbs_pr_info("Invalid CMD_RESP %x to command %x!\n", respcmd, curcmd); | 582 | lbs_pr_info("Invalid CMD_RESP %x to command %x!\n", respcmd, curcmd); |
585 | spin_unlock_irqrestore(&priv->driver_lock, flags); | 583 | spin_unlock_irqrestore(&priv->driver_lock, flags); |
586 | ret = -1; | 584 | ret = -1; |
diff --git a/drivers/net/wireless/libertas/decl.h b/drivers/net/wireless/libertas/decl.h index aaacd9bd6bd2..4e22341b4f3d 100644 --- a/drivers/net/wireless/libertas/decl.h +++ b/drivers/net/wireless/libertas/decl.h | |||
@@ -69,7 +69,6 @@ struct lbs_private *lbs_add_card(void *card, struct device *dmdev); | |||
69 | int lbs_remove_card(struct lbs_private *priv); | 69 | int lbs_remove_card(struct lbs_private *priv); |
70 | int lbs_start_card(struct lbs_private *priv); | 70 | int lbs_start_card(struct lbs_private *priv); |
71 | int lbs_stop_card(struct lbs_private *priv); | 71 | int lbs_stop_card(struct lbs_private *priv); |
72 | int lbs_reset_device(struct lbs_private *priv); | ||
73 | void lbs_host_to_card_done(struct lbs_private *priv); | 72 | void lbs_host_to_card_done(struct lbs_private *priv); |
74 | 73 | ||
75 | int lbs_update_channel(struct lbs_private *priv); | 74 | int lbs_update_channel(struct lbs_private *priv); |
diff --git a/drivers/net/wireless/libertas/main.c b/drivers/net/wireless/libertas/main.c index 84fb49ca0fae..4d4e2f3b66ac 100644 --- a/drivers/net/wireless/libertas/main.c +++ b/drivers/net/wireless/libertas/main.c | |||
@@ -1351,8 +1351,6 @@ done: | |||
1351 | lbs_deb_leave_args(LBS_DEB_MESH, "ret %d", ret); | 1351 | lbs_deb_leave_args(LBS_DEB_MESH, "ret %d", ret); |
1352 | return ret; | 1352 | return ret; |
1353 | } | 1353 | } |
1354 | EXPORT_SYMBOL_GPL(lbs_add_mesh); | ||
1355 | |||
1356 | 1354 | ||
1357 | static void lbs_remove_mesh(struct lbs_private *priv) | 1355 | static void lbs_remove_mesh(struct lbs_private *priv) |
1358 | { | 1356 | { |
@@ -1372,7 +1370,6 @@ static void lbs_remove_mesh(struct lbs_private *priv) | |||
1372 | free_netdev(mesh_dev); | 1370 | free_netdev(mesh_dev); |
1373 | lbs_deb_leave(LBS_DEB_MESH); | 1371 | lbs_deb_leave(LBS_DEB_MESH); |
1374 | } | 1372 | } |
1375 | EXPORT_SYMBOL_GPL(lbs_remove_mesh); | ||
1376 | 1373 | ||
1377 | /** | 1374 | /** |
1378 | * @brief This function finds the CFP in | 1375 | * @brief This function finds the CFP in |
@@ -1458,20 +1455,6 @@ void lbs_interrupt(struct lbs_private *priv) | |||
1458 | } | 1455 | } |
1459 | EXPORT_SYMBOL_GPL(lbs_interrupt); | 1456 | EXPORT_SYMBOL_GPL(lbs_interrupt); |
1460 | 1457 | ||
1461 | int lbs_reset_device(struct lbs_private *priv) | ||
1462 | { | ||
1463 | int ret; | ||
1464 | |||
1465 | lbs_deb_enter(LBS_DEB_MAIN); | ||
1466 | ret = lbs_prepare_and_send_command(priv, CMD_802_11_RESET, | ||
1467 | CMD_ACT_HALT, 0, 0, NULL); | ||
1468 | msleep_interruptible(10); | ||
1469 | |||
1470 | lbs_deb_leave_args(LBS_DEB_MAIN, "ret %d", ret); | ||
1471 | return ret; | ||
1472 | } | ||
1473 | EXPORT_SYMBOL_GPL(lbs_reset_device); | ||
1474 | |||
1475 | static int __init lbs_init_module(void) | 1458 | static int __init lbs_init_module(void) |
1476 | { | 1459 | { |
1477 | lbs_deb_enter(LBS_DEB_MAIN); | 1460 | lbs_deb_enter(LBS_DEB_MAIN); |
diff --git a/drivers/net/wireless/p54common.c b/drivers/net/wireless/p54common.c index 5cda49aff3a8..d191e055a788 100644 --- a/drivers/net/wireless/p54common.c +++ b/drivers/net/wireless/p54common.c | |||
@@ -166,18 +166,23 @@ int p54_parse_eeprom(struct ieee80211_hw *dev, void *eeprom, int len) | |||
166 | struct p54_common *priv = dev->priv; | 166 | struct p54_common *priv = dev->priv; |
167 | struct eeprom_pda_wrap *wrap = NULL; | 167 | struct eeprom_pda_wrap *wrap = NULL; |
168 | struct pda_entry *entry; | 168 | struct pda_entry *entry; |
169 | int i = 0; | ||
170 | unsigned int data_len, entry_len; | 169 | unsigned int data_len, entry_len; |
171 | void *tmp; | 170 | void *tmp; |
172 | int err; | 171 | int err; |
172 | u8 *end = (u8 *)eeprom + len; | ||
173 | 173 | ||
174 | wrap = (struct eeprom_pda_wrap *) eeprom; | 174 | wrap = (struct eeprom_pda_wrap *) eeprom; |
175 | entry = (void *)wrap->data + wrap->len; | 175 | entry = (void *)wrap->data + le16_to_cpu(wrap->len); |
176 | i += 2; | 176 | |
177 | i += le16_to_cpu(entry->len)*2; | 177 | /* verify that at least the entry length/code fits */ |
178 | while (i < len) { | 178 | while ((u8 *)entry <= end - sizeof(*entry)) { |
179 | entry_len = le16_to_cpu(entry->len); | 179 | entry_len = le16_to_cpu(entry->len); |
180 | data_len = ((entry_len - 1) << 1); | 180 | data_len = ((entry_len - 1) << 1); |
181 | |||
182 | /* abort if entry exceeds whole structure */ | ||
183 | if ((u8 *)entry + sizeof(*entry) + data_len > end) | ||
184 | break; | ||
185 | |||
181 | switch (le16_to_cpu(entry->code)) { | 186 | switch (le16_to_cpu(entry->code)) { |
182 | case PDR_MAC_ADDRESS: | 187 | case PDR_MAC_ADDRESS: |
183 | SET_IEEE80211_PERM_ADDR(dev, entry->data); | 188 | SET_IEEE80211_PERM_ADDR(dev, entry->data); |
@@ -249,13 +254,12 @@ int p54_parse_eeprom(struct ieee80211_hw *dev, void *eeprom, int len) | |||
249 | priv->version = *(u8 *)(entry->data + 1); | 254 | priv->version = *(u8 *)(entry->data + 1); |
250 | break; | 255 | break; |
251 | case PDR_END: | 256 | case PDR_END: |
252 | i = len; | 257 | /* make it overrun */ |
258 | entry_len = len; | ||
253 | break; | 259 | break; |
254 | } | 260 | } |
255 | 261 | ||
256 | entry = (void *)entry + (entry_len + 1)*2; | 262 | entry = (void *)entry + (entry_len + 1)*2; |
257 | i += 2; | ||
258 | i += entry_len*2; | ||
259 | } | 263 | } |
260 | 264 | ||
261 | if (!priv->iq_autocal || !priv->output_limit || !priv->curve_data) { | 265 | if (!priv->iq_autocal || !priv->output_limit || !priv->curve_data) { |
diff --git a/drivers/net/wireless/p54common.h b/drivers/net/wireless/p54common.h index a721334e20d9..b67ff34e26fe 100644 --- a/drivers/net/wireless/p54common.h +++ b/drivers/net/wireless/p54common.h | |||
@@ -53,10 +53,10 @@ struct pda_entry { | |||
53 | } __attribute__ ((packed)); | 53 | } __attribute__ ((packed)); |
54 | 54 | ||
55 | struct eeprom_pda_wrap { | 55 | struct eeprom_pda_wrap { |
56 | u32 magic; | 56 | __le32 magic; |
57 | u16 pad; | 57 | __le16 pad; |
58 | u16 len; | 58 | __le16 len; |
59 | u32 arm_opcode; | 59 | __le32 arm_opcode; |
60 | u8 data[0]; | 60 | u8 data[0]; |
61 | } __attribute__ ((packed)); | 61 | } __attribute__ ((packed)); |
62 | 62 | ||
diff --git a/drivers/net/wireless/rndis_wlan.c b/drivers/net/wireless/rndis_wlan.c index 8ce2ddf8024f..10b776c1adc5 100644 --- a/drivers/net/wireless/rndis_wlan.c +++ b/drivers/net/wireless/rndis_wlan.c | |||
@@ -228,9 +228,9 @@ struct NDIS_WLAN_BSSID_EX { | |||
228 | struct NDIS_802_11_SSID Ssid; | 228 | struct NDIS_802_11_SSID Ssid; |
229 | __le32 Privacy; | 229 | __le32 Privacy; |
230 | __le32 Rssi; | 230 | __le32 Rssi; |
231 | enum NDIS_802_11_NETWORK_TYPE NetworkTypeInUse; | 231 | __le32 NetworkTypeInUse; |
232 | struct NDIS_802_11_CONFIGURATION Configuration; | 232 | struct NDIS_802_11_CONFIGURATION Configuration; |
233 | enum NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode; | 233 | __le32 InfrastructureMode; |
234 | u8 SupportedRates[NDIS_802_11_LENGTH_RATES_EX]; | 234 | u8 SupportedRates[NDIS_802_11_LENGTH_RATES_EX]; |
235 | __le32 IELength; | 235 | __le32 IELength; |
236 | u8 IEs[0]; | 236 | u8 IEs[0]; |
@@ -260,7 +260,7 @@ struct NDIS_802_11_KEY { | |||
260 | __le32 KeyLength; | 260 | __le32 KeyLength; |
261 | u8 Bssid[6]; | 261 | u8 Bssid[6]; |
262 | u8 Padding[6]; | 262 | u8 Padding[6]; |
263 | __le64 KeyRSC; | 263 | u8 KeyRSC[8]; |
264 | u8 KeyMaterial[32]; | 264 | u8 KeyMaterial[32]; |
265 | } __attribute__((packed)); | 265 | } __attribute__((packed)); |
266 | 266 | ||
@@ -279,11 +279,11 @@ struct RNDIS_CONFIG_PARAMETER_INFOBUFFER { | |||
279 | } __attribute__((packed)); | 279 | } __attribute__((packed)); |
280 | 280 | ||
281 | /* these have to match what is in wpa_supplicant */ | 281 | /* these have to match what is in wpa_supplicant */ |
282 | enum { WPA_ALG_NONE, WPA_ALG_WEP, WPA_ALG_TKIP, WPA_ALG_CCMP } wpa_alg; | 282 | enum wpa_alg { WPA_ALG_NONE, WPA_ALG_WEP, WPA_ALG_TKIP, WPA_ALG_CCMP }; |
283 | enum { CIPHER_NONE, CIPHER_WEP40, CIPHER_TKIP, CIPHER_CCMP, CIPHER_WEP104 } | 283 | enum wpa_cipher { CIPHER_NONE, CIPHER_WEP40, CIPHER_TKIP, CIPHER_CCMP, |
284 | wpa_cipher; | 284 | CIPHER_WEP104 }; |
285 | enum { KEY_MGMT_802_1X, KEY_MGMT_PSK, KEY_MGMT_NONE, KEY_MGMT_802_1X_NO_WPA, | 285 | enum wpa_key_mgmt { KEY_MGMT_802_1X, KEY_MGMT_PSK, KEY_MGMT_NONE, |
286 | KEY_MGMT_WPA_NONE } wpa_key_mgmt; | 286 | KEY_MGMT_802_1X_NO_WPA, KEY_MGMT_WPA_NONE }; |
287 | 287 | ||
288 | /* | 288 | /* |
289 | * private data | 289 | * private data |
@@ -1508,7 +1508,7 @@ static int rndis_iw_set_encode_ext(struct net_device *dev, | |||
1508 | struct usbnet *usbdev = dev->priv; | 1508 | struct usbnet *usbdev = dev->priv; |
1509 | struct rndis_wext_private *priv = get_rndis_wext_priv(usbdev); | 1509 | struct rndis_wext_private *priv = get_rndis_wext_priv(usbdev); |
1510 | struct NDIS_802_11_KEY ndis_key; | 1510 | struct NDIS_802_11_KEY ndis_key; |
1511 | int i, keyidx, ret; | 1511 | int keyidx, ret; |
1512 | u8 *addr; | 1512 | u8 *addr; |
1513 | 1513 | ||
1514 | keyidx = wrqu->encoding.flags & IW_ENCODE_INDEX; | 1514 | keyidx = wrqu->encoding.flags & IW_ENCODE_INDEX; |
@@ -1543,9 +1543,7 @@ static int rndis_iw_set_encode_ext(struct net_device *dev, | |||
1543 | ndis_key.KeyIndex = cpu_to_le32(keyidx); | 1543 | ndis_key.KeyIndex = cpu_to_le32(keyidx); |
1544 | 1544 | ||
1545 | if (ext->ext_flags & IW_ENCODE_EXT_RX_SEQ_VALID) { | 1545 | if (ext->ext_flags & IW_ENCODE_EXT_RX_SEQ_VALID) { |
1546 | for (i = 0; i < 6; i++) | 1546 | memcpy(ndis_key.KeyRSC, ext->rx_seq, 6); |
1547 | ndis_key.KeyRSC |= | ||
1548 | cpu_to_le64(ext->rx_seq[i] << (i * 8)); | ||
1549 | ndis_key.KeyIndex |= cpu_to_le32(1 << 29); | 1547 | ndis_key.KeyIndex |= cpu_to_le32(1 << 29); |
1550 | } | 1548 | } |
1551 | 1549 | ||
diff --git a/drivers/net/wireless/rt2x00/rt2400pci.c b/drivers/net/wireless/rt2x00/rt2400pci.c index d6cba138c7ab..c69f85ed7669 100644 --- a/drivers/net/wireless/rt2x00/rt2400pci.c +++ b/drivers/net/wireless/rt2x00/rt2400pci.c | |||
@@ -960,8 +960,12 @@ static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev, | |||
960 | rt2400pci_disable_radio(rt2x00dev); | 960 | rt2400pci_disable_radio(rt2x00dev); |
961 | break; | 961 | break; |
962 | case STATE_RADIO_RX_ON: | 962 | case STATE_RADIO_RX_ON: |
963 | case STATE_RADIO_RX_ON_LINK: | ||
964 | rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON); | ||
965 | break; | ||
963 | case STATE_RADIO_RX_OFF: | 966 | case STATE_RADIO_RX_OFF: |
964 | rt2400pci_toggle_rx(rt2x00dev, state); | 967 | case STATE_RADIO_RX_OFF_LINK: |
968 | rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF); | ||
965 | break; | 969 | break; |
966 | case STATE_DEEP_SLEEP: | 970 | case STATE_DEEP_SLEEP: |
967 | case STATE_SLEEP: | 971 | case STATE_SLEEP: |
diff --git a/drivers/net/wireless/rt2x00/rt2500pci.c b/drivers/net/wireless/rt2x00/rt2500pci.c index e874fdcae204..91e87b53374f 100644 --- a/drivers/net/wireless/rt2x00/rt2500pci.c +++ b/drivers/net/wireless/rt2x00/rt2500pci.c | |||
@@ -1112,8 +1112,12 @@ static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev, | |||
1112 | rt2500pci_disable_radio(rt2x00dev); | 1112 | rt2500pci_disable_radio(rt2x00dev); |
1113 | break; | 1113 | break; |
1114 | case STATE_RADIO_RX_ON: | 1114 | case STATE_RADIO_RX_ON: |
1115 | case STATE_RADIO_RX_ON_LINK: | ||
1116 | rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON); | ||
1117 | break; | ||
1115 | case STATE_RADIO_RX_OFF: | 1118 | case STATE_RADIO_RX_OFF: |
1116 | rt2500pci_toggle_rx(rt2x00dev, state); | 1119 | case STATE_RADIO_RX_OFF_LINK: |
1120 | rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF); | ||
1117 | break; | 1121 | break; |
1118 | case STATE_DEEP_SLEEP: | 1122 | case STATE_DEEP_SLEEP: |
1119 | case STATE_SLEEP: | 1123 | case STATE_SLEEP: |
diff --git a/drivers/net/wireless/rt2x00/rt2500usb.c b/drivers/net/wireless/rt2x00/rt2500usb.c index 4ca9730e5e92..638c3d243108 100644 --- a/drivers/net/wireless/rt2x00/rt2500usb.c +++ b/drivers/net/wireless/rt2x00/rt2500usb.c | |||
@@ -1001,8 +1001,12 @@ static int rt2500usb_set_device_state(struct rt2x00_dev *rt2x00dev, | |||
1001 | rt2500usb_disable_radio(rt2x00dev); | 1001 | rt2500usb_disable_radio(rt2x00dev); |
1002 | break; | 1002 | break; |
1003 | case STATE_RADIO_RX_ON: | 1003 | case STATE_RADIO_RX_ON: |
1004 | case STATE_RADIO_RX_ON_LINK: | ||
1005 | rt2500usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON); | ||
1006 | break; | ||
1004 | case STATE_RADIO_RX_OFF: | 1007 | case STATE_RADIO_RX_OFF: |
1005 | rt2500usb_toggle_rx(rt2x00dev, state); | 1008 | case STATE_RADIO_RX_OFF_LINK: |
1009 | rt2500usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF); | ||
1006 | break; | 1010 | break; |
1007 | case STATE_DEEP_SLEEP: | 1011 | case STATE_DEEP_SLEEP: |
1008 | case STATE_SLEEP: | 1012 | case STATE_SLEEP: |
diff --git a/drivers/net/wireless/rt2x00/rt2x00config.c b/drivers/net/wireless/rt2x00/rt2x00config.c index 72cfe00c1ed7..07adc576db49 100644 --- a/drivers/net/wireless/rt2x00/rt2x00config.c +++ b/drivers/net/wireless/rt2x00/rt2x00config.c | |||
@@ -97,12 +97,16 @@ void rt2x00lib_config_antenna(struct rt2x00_dev *rt2x00dev, | |||
97 | libconf.ant.rx = rx; | 97 | libconf.ant.rx = rx; |
98 | libconf.ant.tx = tx; | 98 | libconf.ant.tx = tx; |
99 | 99 | ||
100 | if (rx == rt2x00dev->link.ant.active.rx && | ||
101 | tx == rt2x00dev->link.ant.active.tx) | ||
102 | return; | ||
103 | |||
100 | /* | 104 | /* |
101 | * Antenna setup changes require the RX to be disabled, | 105 | * Antenna setup changes require the RX to be disabled, |
102 | * else the changes will be ignored by the device. | 106 | * else the changes will be ignored by the device. |
103 | */ | 107 | */ |
104 | if (test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags)) | 108 | if (test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags)) |
105 | rt2x00lib_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF); | 109 | rt2x00lib_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF_LINK); |
106 | 110 | ||
107 | /* | 111 | /* |
108 | * Write new antenna setup to device and reset the link tuner. | 112 | * Write new antenna setup to device and reset the link tuner. |
@@ -116,7 +120,7 @@ void rt2x00lib_config_antenna(struct rt2x00_dev *rt2x00dev, | |||
116 | rt2x00dev->link.ant.active.tx = libconf.ant.tx; | 120 | rt2x00dev->link.ant.active.tx = libconf.ant.tx; |
117 | 121 | ||
118 | if (test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags)) | 122 | if (test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags)) |
119 | rt2x00lib_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON); | 123 | rt2x00lib_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON_LINK); |
120 | } | 124 | } |
121 | 125 | ||
122 | void rt2x00lib_config(struct rt2x00_dev *rt2x00dev, | 126 | void rt2x00lib_config(struct rt2x00_dev *rt2x00dev, |
diff --git a/drivers/net/wireless/rt2x00/rt2x00dev.c b/drivers/net/wireless/rt2x00/rt2x00dev.c index c4be2ac4d7a4..0d51f478bcdf 100644 --- a/drivers/net/wireless/rt2x00/rt2x00dev.c +++ b/drivers/net/wireless/rt2x00/rt2x00dev.c | |||
@@ -61,11 +61,33 @@ EXPORT_SYMBOL_GPL(rt2x00lib_get_ring); | |||
61 | /* | 61 | /* |
62 | * Link tuning handlers | 62 | * Link tuning handlers |
63 | */ | 63 | */ |
64 | static void rt2x00lib_start_link_tuner(struct rt2x00_dev *rt2x00dev) | 64 | void rt2x00lib_reset_link_tuner(struct rt2x00_dev *rt2x00dev) |
65 | { | 65 | { |
66 | if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags)) | ||
67 | return; | ||
68 | |||
69 | /* | ||
70 | * Reset link information. | ||
71 | * Both the currently active vgc level as well as | ||
72 | * the link tuner counter should be reset. Resetting | ||
73 | * the counter is important for devices where the | ||
74 | * device should only perform link tuning during the | ||
75 | * first minute after being enabled. | ||
76 | */ | ||
66 | rt2x00dev->link.count = 0; | 77 | rt2x00dev->link.count = 0; |
67 | rt2x00dev->link.vgc_level = 0; | 78 | rt2x00dev->link.vgc_level = 0; |
68 | 79 | ||
80 | /* | ||
81 | * Reset the link tuner. | ||
82 | */ | ||
83 | rt2x00dev->ops->lib->reset_tuner(rt2x00dev); | ||
84 | } | ||
85 | |||
86 | static void rt2x00lib_start_link_tuner(struct rt2x00_dev *rt2x00dev) | ||
87 | { | ||
88 | /* | ||
89 | * Clear all (possibly) pre-existing quality statistics. | ||
90 | */ | ||
69 | memset(&rt2x00dev->link.qual, 0, sizeof(rt2x00dev->link.qual)); | 91 | memset(&rt2x00dev->link.qual, 0, sizeof(rt2x00dev->link.qual)); |
70 | 92 | ||
71 | /* | 93 | /* |
@@ -79,10 +101,7 @@ static void rt2x00lib_start_link_tuner(struct rt2x00_dev *rt2x00dev) | |||
79 | rt2x00dev->link.qual.rx_percentage = 50; | 101 | rt2x00dev->link.qual.rx_percentage = 50; |
80 | rt2x00dev->link.qual.tx_percentage = 50; | 102 | rt2x00dev->link.qual.tx_percentage = 50; |
81 | 103 | ||
82 | /* | 104 | rt2x00lib_reset_link_tuner(rt2x00dev); |
83 | * Reset the link tuner. | ||
84 | */ | ||
85 | rt2x00dev->ops->lib->reset_tuner(rt2x00dev); | ||
86 | 105 | ||
87 | queue_delayed_work(rt2x00dev->hw->workqueue, | 106 | queue_delayed_work(rt2x00dev->hw->workqueue, |
88 | &rt2x00dev->link.work, LINK_TUNE_INTERVAL); | 107 | &rt2x00dev->link.work, LINK_TUNE_INTERVAL); |
@@ -93,15 +112,6 @@ static void rt2x00lib_stop_link_tuner(struct rt2x00_dev *rt2x00dev) | |||
93 | cancel_delayed_work_sync(&rt2x00dev->link.work); | 112 | cancel_delayed_work_sync(&rt2x00dev->link.work); |
94 | } | 113 | } |
95 | 114 | ||
96 | void rt2x00lib_reset_link_tuner(struct rt2x00_dev *rt2x00dev) | ||
97 | { | ||
98 | if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags)) | ||
99 | return; | ||
100 | |||
101 | rt2x00lib_stop_link_tuner(rt2x00dev); | ||
102 | rt2x00lib_start_link_tuner(rt2x00dev); | ||
103 | } | ||
104 | |||
105 | /* | 115 | /* |
106 | * Ring initialization | 116 | * Ring initialization |
107 | */ | 117 | */ |
@@ -260,19 +270,11 @@ static void rt2x00lib_evaluate_antenna_sample(struct rt2x00_dev *rt2x00dev) | |||
260 | if (sample_a == sample_b) | 270 | if (sample_a == sample_b) |
261 | return; | 271 | return; |
262 | 272 | ||
263 | if (rt2x00dev->link.ant.flags & ANTENNA_RX_DIVERSITY) { | 273 | if (rt2x00dev->link.ant.flags & ANTENNA_RX_DIVERSITY) |
264 | if (sample_a > sample_b && rx == ANTENNA_B) | 274 | rx = (sample_a > sample_b) ? ANTENNA_A : ANTENNA_B; |
265 | rx = ANTENNA_A; | ||
266 | else if (rx == ANTENNA_A) | ||
267 | rx = ANTENNA_B; | ||
268 | } | ||
269 | 275 | ||
270 | if (rt2x00dev->link.ant.flags & ANTENNA_TX_DIVERSITY) { | 276 | if (rt2x00dev->link.ant.flags & ANTENNA_TX_DIVERSITY) |
271 | if (sample_a > sample_b && tx == ANTENNA_B) | 277 | tx = (sample_a > sample_b) ? ANTENNA_A : ANTENNA_B; |
272 | tx = ANTENNA_A; | ||
273 | else if (tx == ANTENNA_A) | ||
274 | tx = ANTENNA_B; | ||
275 | } | ||
276 | 278 | ||
277 | rt2x00lib_config_antenna(rt2x00dev, rx, tx); | 279 | rt2x00lib_config_antenna(rt2x00dev, rx, tx); |
278 | } | 280 | } |
@@ -293,7 +295,7 @@ static void rt2x00lib_evaluate_antenna_eval(struct rt2x00_dev *rt2x00dev) | |||
293 | * sample the rssi from the other antenna to make a valid | 295 | * sample the rssi from the other antenna to make a valid |
294 | * comparison between the 2 antennas. | 296 | * comparison between the 2 antennas. |
295 | */ | 297 | */ |
296 | if ((rssi_curr - rssi_old) > -5 || (rssi_curr - rssi_old) < 5) | 298 | if (abs(rssi_curr - rssi_old) < 5) |
297 | return; | 299 | return; |
298 | 300 | ||
299 | rt2x00dev->link.ant.flags |= ANTENNA_MODE_SAMPLE; | 301 | rt2x00dev->link.ant.flags |= ANTENNA_MODE_SAMPLE; |
@@ -319,15 +321,15 @@ static void rt2x00lib_evaluate_antenna(struct rt2x00_dev *rt2x00dev) | |||
319 | rt2x00dev->link.ant.flags &= ~ANTENNA_TX_DIVERSITY; | 321 | rt2x00dev->link.ant.flags &= ~ANTENNA_TX_DIVERSITY; |
320 | 322 | ||
321 | if (rt2x00dev->hw->conf.antenna_sel_rx == 0 && | 323 | if (rt2x00dev->hw->conf.antenna_sel_rx == 0 && |
322 | rt2x00dev->default_ant.rx != ANTENNA_SW_DIVERSITY) | 324 | rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY) |
323 | rt2x00dev->link.ant.flags |= ANTENNA_RX_DIVERSITY; | 325 | rt2x00dev->link.ant.flags |= ANTENNA_RX_DIVERSITY; |
324 | if (rt2x00dev->hw->conf.antenna_sel_tx == 0 && | 326 | if (rt2x00dev->hw->conf.antenna_sel_tx == 0 && |
325 | rt2x00dev->default_ant.tx != ANTENNA_SW_DIVERSITY) | 327 | rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY) |
326 | rt2x00dev->link.ant.flags |= ANTENNA_TX_DIVERSITY; | 328 | rt2x00dev->link.ant.flags |= ANTENNA_TX_DIVERSITY; |
327 | 329 | ||
328 | if (!(rt2x00dev->link.ant.flags & ANTENNA_RX_DIVERSITY) && | 330 | if (!(rt2x00dev->link.ant.flags & ANTENNA_RX_DIVERSITY) && |
329 | !(rt2x00dev->link.ant.flags & ANTENNA_TX_DIVERSITY)) { | 331 | !(rt2x00dev->link.ant.flags & ANTENNA_TX_DIVERSITY)) { |
330 | rt2x00dev->link.ant.flags &= ~ANTENNA_MODE_SAMPLE; | 332 | rt2x00dev->link.ant.flags = 0; |
331 | return; | 333 | return; |
332 | } | 334 | } |
333 | 335 | ||
@@ -441,17 +443,18 @@ static void rt2x00lib_link_tuner(struct work_struct *work) | |||
441 | rt2x00dev->ops->lib->link_tuner(rt2x00dev); | 443 | rt2x00dev->ops->lib->link_tuner(rt2x00dev); |
442 | 444 | ||
443 | /* | 445 | /* |
444 | * Evaluate antenna setup. | ||
445 | */ | ||
446 | rt2x00lib_evaluate_antenna(rt2x00dev); | ||
447 | |||
448 | /* | ||
449 | * Precalculate a portion of the link signal which is | 446 | * Precalculate a portion of the link signal which is |
450 | * in based on the tx/rx success/failure counters. | 447 | * in based on the tx/rx success/failure counters. |
451 | */ | 448 | */ |
452 | rt2x00lib_precalculate_link_signal(&rt2x00dev->link.qual); | 449 | rt2x00lib_precalculate_link_signal(&rt2x00dev->link.qual); |
453 | 450 | ||
454 | /* | 451 | /* |
452 | * Evaluate antenna setup, make this the last step since this could | ||
453 | * possibly reset some statistics. | ||
454 | */ | ||
455 | rt2x00lib_evaluate_antenna(rt2x00dev); | ||
456 | |||
457 | /* | ||
455 | * Increase tuner counter, and reschedule the next link tuner run. | 458 | * Increase tuner counter, and reschedule the next link tuner run. |
456 | */ | 459 | */ |
457 | rt2x00dev->link.count++; | 460 | rt2x00dev->link.count++; |
diff --git a/drivers/net/wireless/rt2x00/rt2x00reg.h b/drivers/net/wireless/rt2x00/rt2x00reg.h index 838421216da0..b1915dc7dda1 100644 --- a/drivers/net/wireless/rt2x00/rt2x00reg.h +++ b/drivers/net/wireless/rt2x00/rt2x00reg.h | |||
@@ -85,6 +85,8 @@ enum dev_state { | |||
85 | STATE_RADIO_OFF, | 85 | STATE_RADIO_OFF, |
86 | STATE_RADIO_RX_ON, | 86 | STATE_RADIO_RX_ON, |
87 | STATE_RADIO_RX_OFF, | 87 | STATE_RADIO_RX_OFF, |
88 | STATE_RADIO_RX_ON_LINK, | ||
89 | STATE_RADIO_RX_OFF_LINK, | ||
88 | STATE_RADIO_IRQ_ON, | 90 | STATE_RADIO_IRQ_ON, |
89 | STATE_RADIO_IRQ_OFF, | 91 | STATE_RADIO_IRQ_OFF, |
90 | }; | 92 | }; |
diff --git a/drivers/net/wireless/rt2x00/rt61pci.c b/drivers/net/wireless/rt2x00/rt61pci.c index b31f0c26c32b..93ea212fedd5 100644 --- a/drivers/net/wireless/rt2x00/rt61pci.c +++ b/drivers/net/wireless/rt2x00/rt61pci.c | |||
@@ -1482,8 +1482,12 @@ static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev, | |||
1482 | rt61pci_disable_radio(rt2x00dev); | 1482 | rt61pci_disable_radio(rt2x00dev); |
1483 | break; | 1483 | break; |
1484 | case STATE_RADIO_RX_ON: | 1484 | case STATE_RADIO_RX_ON: |
1485 | case STATE_RADIO_RX_ON_LINK: | ||
1486 | rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON); | ||
1487 | break; | ||
1485 | case STATE_RADIO_RX_OFF: | 1488 | case STATE_RADIO_RX_OFF: |
1486 | rt61pci_toggle_rx(rt2x00dev, state); | 1489 | case STATE_RADIO_RX_OFF_LINK: |
1490 | rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF); | ||
1487 | break; | 1491 | break; |
1488 | case STATE_DEEP_SLEEP: | 1492 | case STATE_DEEP_SLEEP: |
1489 | case STATE_SLEEP: | 1493 | case STATE_SLEEP: |
@@ -2298,9 +2302,9 @@ static void rt61pci_configure_filter(struct ieee80211_hw *hw, | |||
2298 | * Apply some rules to the filters: | 2302 | * Apply some rules to the filters: |
2299 | * - Some filters imply different filters to be set. | 2303 | * - Some filters imply different filters to be set. |
2300 | * - Some things we can't filter out at all. | 2304 | * - Some things we can't filter out at all. |
2305 | * - Multicast filter seems to kill broadcast traffic so never use it. | ||
2301 | */ | 2306 | */ |
2302 | if (mc_count) | 2307 | *total_flags |= FIF_ALLMULTI; |
2303 | *total_flags |= FIF_ALLMULTI; | ||
2304 | if (*total_flags & FIF_OTHER_BSS || | 2308 | if (*total_flags & FIF_OTHER_BSS || |
2305 | *total_flags & FIF_PROMISC_IN_BSS) | 2309 | *total_flags & FIF_PROMISC_IN_BSS) |
2306 | *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS; | 2310 | *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS; |
diff --git a/drivers/net/wireless/rt2x00/rt73usb.c b/drivers/net/wireless/rt2x00/rt73usb.c index 4d576ab3e7f9..8103d41a1543 100644 --- a/drivers/net/wireless/rt2x00/rt73usb.c +++ b/drivers/net/wireless/rt2x00/rt73usb.c | |||
@@ -1208,8 +1208,12 @@ static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev, | |||
1208 | rt73usb_disable_radio(rt2x00dev); | 1208 | rt73usb_disable_radio(rt2x00dev); |
1209 | break; | 1209 | break; |
1210 | case STATE_RADIO_RX_ON: | 1210 | case STATE_RADIO_RX_ON: |
1211 | case STATE_RADIO_RX_ON_LINK: | ||
1212 | rt73usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON); | ||
1213 | break; | ||
1211 | case STATE_RADIO_RX_OFF: | 1214 | case STATE_RADIO_RX_OFF: |
1212 | rt73usb_toggle_rx(rt2x00dev, state); | 1215 | case STATE_RADIO_RX_OFF_LINK: |
1216 | rt73usb_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF); | ||
1213 | break; | 1217 | break; |
1214 | case STATE_DEEP_SLEEP: | 1218 | case STATE_DEEP_SLEEP: |
1215 | case STATE_SLEEP: | 1219 | case STATE_SLEEP: |
@@ -1865,9 +1869,9 @@ static void rt73usb_configure_filter(struct ieee80211_hw *hw, | |||
1865 | * Apply some rules to the filters: | 1869 | * Apply some rules to the filters: |
1866 | * - Some filters imply different filters to be set. | 1870 | * - Some filters imply different filters to be set. |
1867 | * - Some things we can't filter out at all. | 1871 | * - Some things we can't filter out at all. |
1872 | * - Multicast filter seems to kill broadcast traffic so never use it. | ||
1868 | */ | 1873 | */ |
1869 | if (mc_count) | 1874 | *total_flags |= FIF_ALLMULTI; |
1870 | *total_flags |= FIF_ALLMULTI; | ||
1871 | if (*total_flags & FIF_OTHER_BSS || | 1875 | if (*total_flags & FIF_OTHER_BSS || |
1872 | *total_flags & FIF_PROMISC_IN_BSS) | 1876 | *total_flags & FIF_PROMISC_IN_BSS) |
1873 | *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS; | 1877 | *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS; |
@@ -2094,6 +2098,7 @@ static struct usb_device_id rt73usb_device_table[] = { | |||
2094 | /* D-Link */ | 2098 | /* D-Link */ |
2095 | { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) }, | 2099 | { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) }, |
2096 | { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) }, | 2100 | { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) }, |
2101 | { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) }, | ||
2097 | /* Gemtek */ | 2102 | /* Gemtek */ |
2098 | { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) }, | 2103 | { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) }, |
2099 | /* Gigabyte */ | 2104 | /* Gigabyte */ |