diff options
author | Winkler, Tomas <tomas.winkler@intel.com> | 2008-10-29 17:05:43 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2008-11-10 15:17:35 -0500 |
commit | 9c80c50211d638555bc4b160d9ccd348e98eedad (patch) | |
tree | 32f9ac7d53da13dad96299323b8bb78af4efc189 /drivers/net | |
parent | c7ab5ef9bcd281135c21b4732c9be779585181be (diff) |
iwlwifi: reorganize flow handler bitology
This patch cleans up FH bits and adds missing register values
that will be used later in TX initialization rewrite
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net')
-rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-5000.c | 8 | ||||
-rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-fh.h | 52 | ||||
-rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-tx.c | 4 |
3 files changed, 35 insertions, 29 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-5000.c b/drivers/net/wireless/iwlwifi/iwl-5000.c index 4348c7db3d1f..1608b289aa7b 100644 --- a/drivers/net/wireless/iwlwifi/iwl-5000.c +++ b/drivers/net/wireless/iwlwifi/iwl-5000.c | |||
@@ -535,7 +535,7 @@ static int iwl5000_load_section(struct iwl_priv *priv, | |||
535 | iwl_write_direct32(priv, | 535 | iwl_write_direct32(priv, |
536 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), | 536 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), |
537 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | 537 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | |
538 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL | | 538 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | |
539 | FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); | 539 | FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); |
540 | 540 | ||
541 | iwl_release_nic_access(priv); | 541 | iwl_release_nic_access(priv); |
@@ -549,14 +549,13 @@ static int iwl5000_load_given_ucode(struct iwl_priv *priv, | |||
549 | { | 549 | { |
550 | int ret = 0; | 550 | int ret = 0; |
551 | 551 | ||
552 | ret = iwl5000_load_section( | 552 | ret = iwl5000_load_section(priv, inst_image, RTC_INST_LOWER_BOUND); |
553 | priv, inst_image, RTC_INST_LOWER_BOUND); | ||
554 | if (ret) | 553 | if (ret) |
555 | return ret; | 554 | return ret; |
556 | 555 | ||
557 | IWL_DEBUG_INFO("INST uCode section being loaded...\n"); | 556 | IWL_DEBUG_INFO("INST uCode section being loaded...\n"); |
558 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | 557 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, |
559 | priv->ucode_write_complete, 5 * HZ); | 558 | priv->ucode_write_complete, 5 * HZ); |
560 | if (ret == -ERESTARTSYS) { | 559 | if (ret == -ERESTARTSYS) { |
561 | IWL_ERROR("Could not load the INST uCode section due " | 560 | IWL_ERROR("Could not load the INST uCode section due " |
562 | "to interrupt\n"); | 561 | "to interrupt\n"); |
@@ -753,6 +752,7 @@ static int iwl5000_alive_notify(struct iwl_priv *priv) | |||
753 | priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7)); | 752 | priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7)); |
754 | 753 | ||
755 | iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0); | 754 | iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0); |
755 | |||
756 | /* map qos queues to fifos one-to-one */ | 756 | /* map qos queues to fifos one-to-one */ |
757 | for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) { | 757 | for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) { |
758 | int ac = iwl5000_default_queue_to_tx_fifo[i]; | 758 | int ac = iwl5000_default_queue_to_tx_fifo[i]; |
diff --git a/drivers/net/wireless/iwlwifi/iwl-fh.h b/drivers/net/wireless/iwlwifi/iwl-fh.h index f2688d551830..97e2cf41258d 100644 --- a/drivers/net/wireless/iwlwifi/iwl-fh.h +++ b/drivers/net/wireless/iwlwifi/iwl-fh.h | |||
@@ -318,34 +318,40 @@ | |||
318 | #define FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60) | 318 | #define FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60) |
319 | 319 | ||
320 | /* Find Control/Status reg for given Tx DMA/FIFO channel */ | 320 | /* Find Control/Status reg for given Tx DMA/FIFO channel */ |
321 | #define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ | 321 | #define FH49_TCSR_CHNL_NUM (7) |
322 | (FH_TCSR_LOWER_BOUND + 0x20 * _chnl) | 322 | #define FH50_TCSR_CHNL_NUM (8) |
323 | 323 | ||
324 | #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000) | 324 | #define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ |
325 | #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008) | 325 | (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) |
326 | #define FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ | ||
327 | (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) | ||
328 | #define FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ | ||
329 | (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) | ||
326 | 330 | ||
327 | #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) | 331 | #define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) |
328 | #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) | 332 | #define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) |
329 | #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) | ||
330 | 333 | ||
331 | #define FH_TCSR_CHNL_NUM (7) | 334 | #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) |
335 | #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) | ||
332 | 336 | ||
333 | #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) | 337 | #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) |
334 | #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) | 338 | #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) |
335 | #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) | 339 | #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) |
336 | 340 | ||
337 | #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) | 341 | #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) |
338 | #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) | 342 | #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) |
339 | #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) | 343 | #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) |
340 | 344 | ||
341 | #define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) | 345 | #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) |
342 | #define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) | 346 | #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) |
343 | #define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ | 347 | #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) |
344 | (FH_TCSR_LOWER_BOUND + 0x20 * _chnl) | 348 | |
345 | #define FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ | 349 | #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) |
346 | (FH_TCSR_LOWER_BOUND + 0x20 * _chnl + 0x4) | 350 | #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) |
347 | #define FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ | 351 | #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) |
348 | (FH_TCSR_LOWER_BOUND + 0x20 * _chnl + 0x8) | 352 | |
353 | #define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) | ||
354 | #define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) | ||
349 | 355 | ||
350 | /** | 356 | /** |
351 | * Tx Shared Status Registers (TSSR) | 357 | * Tx Shared Status Registers (TSSR) |
@@ -362,7 +368,7 @@ | |||
362 | #define FH_TSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEA0) | 368 | #define FH_TSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEA0) |
363 | #define FH_TSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEC0) | 369 | #define FH_TSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEC0) |
364 | 370 | ||
365 | #define FH_TSSR_TX_STATUS_REG (FH_TSSR_LOWER_BOUND + 0x010) | 371 | #define FH_TSSR_TX_STATUS_REG (FH_TSSR_LOWER_BOUND + 0x010) |
366 | 372 | ||
367 | #define FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) ((1 << (_chnl)) << 24) | 373 | #define FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) ((1 << (_chnl)) << 24) |
368 | #define FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl) ((1 << (_chnl)) << 16) | 374 | #define FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl) ((1 << (_chnl)) << 16) |
diff --git a/drivers/net/wireless/iwlwifi/iwl-tx.c b/drivers/net/wireless/iwlwifi/iwl-tx.c index 6008c0cce214..7d8b4e2d5094 100644 --- a/drivers/net/wireless/iwlwifi/iwl-tx.c +++ b/drivers/net/wireless/iwlwifi/iwl-tx.c | |||
@@ -431,8 +431,8 @@ static int iwl_hw_tx_queue_init(struct iwl_priv *priv, | |||
431 | 431 | ||
432 | /* Enable DMA channel, using same id as for TFD queue */ | 432 | /* Enable DMA channel, using same id as for TFD queue */ |
433 | iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), | 433 | iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), |
434 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | 434 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | |
435 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL); | 435 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); |
436 | 436 | ||
437 | iwl_release_nic_access(priv); | 437 | iwl_release_nic_access(priv); |
438 | spin_unlock_irqrestore(&priv->lock, flags); | 438 | spin_unlock_irqrestore(&priv->lock, flags); |