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authorEugene Surovegin <ebs@ebshome.net>2005-10-29 15:43:14 -0400
committerJeff Garzik <jgarzik@pobox.com>2005-10-29 18:06:54 -0400
commit7ad8a89c2e8a930a902cb0622956b27796c027e5 (patch)
treec1241696b8fc5ab55d389f9accd80f399e3d9d86 /drivers/net
parentbe15cd72d256e5eb3261a781b8507fac83ab33f6 (diff)
[PATCH] PPC 44x EMAC driver: add 440SPe support
For some reason, the hardware designers made the polarity of one bit in the 440SPe's PHY interface register the opposite of all other PPC 440 chips. To handle this, abstract our access to this bit and do the right thing based on the configured CPU type. Signed-off-by: Roland Dreier <rolandd@cisco.com> Signed-off-by: Eugene Surovegin <ebs@ebshome.net> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/ibm_emac/ibm_emac.h21
-rw-r--r--drivers/net/ibm_emac/ibm_emac_core.c13
-rw-r--r--drivers/net/ibm_emac/ibm_emac_mal.h3
3 files changed, 29 insertions, 8 deletions
diff --git a/drivers/net/ibm_emac/ibm_emac.h b/drivers/net/ibm_emac/ibm_emac.h
index 28c476f28c20..d3166da753ef 100644
--- a/drivers/net/ibm_emac/ibm_emac.h
+++ b/drivers/net/ibm_emac/ibm_emac.h
@@ -26,7 +26,7 @@
26/* This is a simple check to prevent use of this driver on non-tested SoCs */ 26/* This is a simple check to prevent use of this driver on non-tested SoCs */
27#if !defined(CONFIG_405GP) && !defined(CONFIG_405GPR) && !defined(CONFIG_405EP) && \ 27#if !defined(CONFIG_405GP) && !defined(CONFIG_405GPR) && !defined(CONFIG_405EP) && \
28 !defined(CONFIG_440GP) && !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && \ 28 !defined(CONFIG_440GP) && !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && \
29 !defined(CONFIG_440EP) && !defined(CONFIG_NP405H) 29 !defined(CONFIG_440EP) && !defined(CONFIG_NP405H) && !defined(CONFIG_440SPE)
30#error "Unknown SoC. Please, check chip user manual and make sure EMAC defines are OK" 30#error "Unknown SoC. Please, check chip user manual and make sure EMAC defines are OK"
31#endif 31#endif
32 32
@@ -246,6 +246,25 @@ struct emac_regs {
246#define EMAC_STACR_PCDA_SHIFT 5 246#define EMAC_STACR_PCDA_SHIFT 5
247#define EMAC_STACR_PRA_MASK 0x1f 247#define EMAC_STACR_PRA_MASK 0x1f
248 248
249/*
250 * For the 440SPe, AMCC inexplicably changed the polarity of
251 * the "operation complete" bit in the MII control register.
252 */
253#if defined(CONFIG_440SPE)
254static inline int emac_phy_done(u32 stacr)
255{
256 return !(stacr & EMAC_STACR_OC);
257};
258#define EMAC_STACR_START EMAC_STACR_OC
259
260#else /* CONFIG_440SPE */
261static inline int emac_phy_done(u32 stacr)
262{
263 return stacr & EMAC_STACR_OC;
264};
265#define EMAC_STACR_START 0
266#endif /* !CONFIG_440SPE */
267
249/* EMACx_TRTR */ 268/* EMACx_TRTR */
250#if !defined(CONFIG_IBM_EMAC4) 269#if !defined(CONFIG_IBM_EMAC4)
251#define EMAC_TRTR_SHIFT 27 270#define EMAC_TRTR_SHIFT 27
diff --git a/drivers/net/ibm_emac/ibm_emac_core.c b/drivers/net/ibm_emac/ibm_emac_core.c
index 943fbd1546ff..48239e17d351 100644
--- a/drivers/net/ibm_emac/ibm_emac_core.c
+++ b/drivers/net/ibm_emac/ibm_emac_core.c
@@ -546,7 +546,7 @@ static int __emac_mdio_read(struct ocp_enet_private *dev, u8 id, u8 reg)
546 546
547 /* Wait for management interface to become idle */ 547 /* Wait for management interface to become idle */
548 n = 10; 548 n = 10;
549 while (!(in_be32(&p->stacr) & EMAC_STACR_OC)) { 549 while (!emac_phy_done(in_be32(&p->stacr))) {
550 udelay(1); 550 udelay(1);
551 if (!--n) 551 if (!--n)
552 goto to; 552 goto to;
@@ -556,11 +556,12 @@ static int __emac_mdio_read(struct ocp_enet_private *dev, u8 id, u8 reg)
556 out_be32(&p->stacr, 556 out_be32(&p->stacr,
557 EMAC_STACR_BASE(emac_opb_mhz()) | EMAC_STACR_STAC_READ | 557 EMAC_STACR_BASE(emac_opb_mhz()) | EMAC_STACR_STAC_READ |
558 (reg & EMAC_STACR_PRA_MASK) 558 (reg & EMAC_STACR_PRA_MASK)
559 | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT)); 559 | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT)
560 | EMAC_STACR_START);
560 561
561 /* Wait for read to complete */ 562 /* Wait for read to complete */
562 n = 100; 563 n = 100;
563 while (!((r = in_be32(&p->stacr)) & EMAC_STACR_OC)) { 564 while (!emac_phy_done(r = in_be32(&p->stacr))) {
564 udelay(1); 565 udelay(1);
565 if (!--n) 566 if (!--n)
566 goto to; 567 goto to;
@@ -594,7 +595,7 @@ static void __emac_mdio_write(struct ocp_enet_private *dev, u8 id, u8 reg,
594 595
595 /* Wait for management interface to be idle */ 596 /* Wait for management interface to be idle */
596 n = 10; 597 n = 10;
597 while (!(in_be32(&p->stacr) & EMAC_STACR_OC)) { 598 while (!emac_phy_done(in_be32(&p->stacr))) {
598 udelay(1); 599 udelay(1);
599 if (!--n) 600 if (!--n)
600 goto to; 601 goto to;
@@ -605,11 +606,11 @@ static void __emac_mdio_write(struct ocp_enet_private *dev, u8 id, u8 reg,
605 EMAC_STACR_BASE(emac_opb_mhz()) | EMAC_STACR_STAC_WRITE | 606 EMAC_STACR_BASE(emac_opb_mhz()) | EMAC_STACR_STAC_WRITE |
606 (reg & EMAC_STACR_PRA_MASK) | 607 (reg & EMAC_STACR_PRA_MASK) |
607 ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) | 608 ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) |
608 (val << EMAC_STACR_PHYD_SHIFT)); 609 (val << EMAC_STACR_PHYD_SHIFT) | EMAC_STACR_START);
609 610
610 /* Wait for write to complete */ 611 /* Wait for write to complete */
611 n = 100; 612 n = 100;
612 while (!(in_be32(&p->stacr) & EMAC_STACR_OC)) { 613 while (!emac_phy_done(in_be32(&p->stacr))) {
613 udelay(1); 614 udelay(1);
614 if (!--n) 615 if (!--n)
615 goto to; 616 goto to;
diff --git a/drivers/net/ibm_emac/ibm_emac_mal.h b/drivers/net/ibm_emac/ibm_emac_mal.h
index 15b0bdae26ac..fb6dfe1197b2 100644
--- a/drivers/net/ibm_emac/ibm_emac_mal.h
+++ b/drivers/net/ibm_emac/ibm_emac_mal.h
@@ -34,7 +34,8 @@
34#if defined(CONFIG_405GP) || defined(CONFIG_405GPR) || defined(CONFIG_405EP) || \ 34#if defined(CONFIG_405GP) || defined(CONFIG_405GPR) || defined(CONFIG_405EP) || \
35 defined(CONFIG_440EP) || defined(CONFIG_NP405H) 35 defined(CONFIG_440EP) || defined(CONFIG_NP405H)
36#define MAL_VERSION 1 36#define MAL_VERSION 1
37#elif defined(CONFIG_440GP) || defined(CONFIG_440GX) || defined(CONFIG_440SP) 37#elif defined(CONFIG_440GP) || defined(CONFIG_440GX) || defined(CONFIG_440SP) || \
38 defined(CONFIG_440SPE)
38#define MAL_VERSION 2 39#define MAL_VERSION 2
39#else 40#else
40#error "Unknown SoC, please check chip manual and choose MAL 'version'" 41#error "Unknown SoC, please check chip manual and choose MAL 'version'"