diff options
author | <jgarzik@pretzel.yyz.us> | 2005-05-27 22:07:02 -0400 |
---|---|---|
committer | Jeff Garzik <jgarzik@pobox.com> | 2005-05-27 22:07:02 -0400 |
commit | 1f15d694522af9cd7492695f11dd2dc77b6cf098 (patch) | |
tree | 7f67a4c38456ec73359d576a5c602d18c3c3ef72 /drivers/net | |
parent | fff9cfd99c0f88645c3f50d7476d6c8cef99f140 (diff) | |
parent | 254feb882a7c6e4e51416dff6a97d847fbbba551 (diff) |
Automatic merge of /spare/repo/netdev-2.6 branch master
Diffstat (limited to 'drivers/net')
35 files changed, 16446 insertions, 1110 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 3a0a55b62aaf..f08e01b2fd19 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig | |||
@@ -1555,6 +1555,7 @@ config SIS900 | |||
1555 | tristate "SiS 900/7016 PCI Fast Ethernet Adapter support" | 1555 | tristate "SiS 900/7016 PCI Fast Ethernet Adapter support" |
1556 | depends on NET_PCI && PCI | 1556 | depends on NET_PCI && PCI |
1557 | select CRC32 | 1557 | select CRC32 |
1558 | select MII | ||
1558 | ---help--- | 1559 | ---help--- |
1559 | This is a driver for the Fast Ethernet PCI network cards based on | 1560 | This is a driver for the Fast Ethernet PCI network cards based on |
1560 | the SiS 900 and SiS 7016 chips. The SiS 900 core is also embedded in | 1561 | the SiS 900 and SiS 7016 chips. The SiS 900 core is also embedded in |
@@ -2031,6 +2032,15 @@ config TIGON3 | |||
2031 | To compile this driver as a module, choose M here: the module | 2032 | To compile this driver as a module, choose M here: the module |
2032 | will be called tg3. This is recommended. | 2033 | will be called tg3. This is recommended. |
2033 | 2034 | ||
2035 | config BNX2 | ||
2036 | tristate "Broadcom NetXtremeII support" | ||
2037 | depends on PCI | ||
2038 | help | ||
2039 | This driver supports Broadcom NetXtremeII gigabit Ethernet cards. | ||
2040 | |||
2041 | To compile this driver as a module, choose M here: the module | ||
2042 | will be called bnx2. This is recommended. | ||
2043 | |||
2034 | config GIANFAR | 2044 | config GIANFAR |
2035 | tristate "Gianfar Ethernet" | 2045 | tristate "Gianfar Ethernet" |
2036 | depends on 85xx || 83xx | 2046 | depends on 85xx || 83xx |
diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 6202b10dbb4d..30c7567001fe 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile | |||
@@ -51,6 +51,7 @@ obj-$(CONFIG_NS83820) += ns83820.o | |||
51 | obj-$(CONFIG_STNIC) += stnic.o 8390.o | 51 | obj-$(CONFIG_STNIC) += stnic.o 8390.o |
52 | obj-$(CONFIG_FEALNX) += fealnx.o | 52 | obj-$(CONFIG_FEALNX) += fealnx.o |
53 | obj-$(CONFIG_TIGON3) += tg3.o | 53 | obj-$(CONFIG_TIGON3) += tg3.o |
54 | obj-$(CONFIG_BNX2) += bnx2.o | ||
54 | obj-$(CONFIG_TC35815) += tc35815.o | 55 | obj-$(CONFIG_TC35815) += tc35815.o |
55 | obj-$(CONFIG_SK98LIN) += sk98lin/ | 56 | obj-$(CONFIG_SK98LIN) += sk98lin/ |
56 | obj-$(CONFIG_SKFP) += skfp/ | 57 | obj-$(CONFIG_SKFP) += skfp/ |
@@ -187,7 +188,7 @@ obj-$(CONFIG_TR) += tokenring/ | |||
187 | obj-$(CONFIG_WAN) += wan/ | 188 | obj-$(CONFIG_WAN) += wan/ |
188 | obj-$(CONFIG_ARCNET) += arcnet/ | 189 | obj-$(CONFIG_ARCNET) += arcnet/ |
189 | obj-$(CONFIG_NET_PCMCIA) += pcmcia/ | 190 | obj-$(CONFIG_NET_PCMCIA) += pcmcia/ |
190 | obj-$(CONFIG_NET_WIRELESS) += wireless/ | 191 | obj-$(CONFIG_NET_RADIO) += wireless/ |
191 | obj-$(CONFIG_NET_TULIP) += tulip/ | 192 | obj-$(CONFIG_NET_TULIP) += tulip/ |
192 | obj-$(CONFIG_HAMRADIO) += hamradio/ | 193 | obj-$(CONFIG_HAMRADIO) += hamradio/ |
193 | obj-$(CONFIG_IRDA) += irda/ | 194 | obj-$(CONFIG_IRDA) += irda/ |
diff --git a/drivers/net/amd8111e.c b/drivers/net/amd8111e.c index f2e937abf7b4..b7dd7260cafb 100755 --- a/drivers/net/amd8111e.c +++ b/drivers/net/amd8111e.c | |||
@@ -738,6 +738,7 @@ static int amd8111e_rx_poll(struct net_device *dev, int * budget) | |||
738 | short vtag; | 738 | short vtag; |
739 | #endif | 739 | #endif |
740 | int rx_pkt_limit = dev->quota; | 740 | int rx_pkt_limit = dev->quota; |
741 | unsigned long flags; | ||
741 | 742 | ||
742 | do{ | 743 | do{ |
743 | /* process receive packets until we use the quota*/ | 744 | /* process receive packets until we use the quota*/ |
@@ -841,18 +842,19 @@ static int amd8111e_rx_poll(struct net_device *dev, int * budget) | |||
841 | /* Receive descriptor is empty now */ | 842 | /* Receive descriptor is empty now */ |
842 | dev->quota -= num_rx_pkt; | 843 | dev->quota -= num_rx_pkt; |
843 | *budget -= num_rx_pkt; | 844 | *budget -= num_rx_pkt; |
845 | |||
846 | spin_lock_irqsave(&lp->lock, flags); | ||
844 | netif_rx_complete(dev); | 847 | netif_rx_complete(dev); |
845 | /* enable receive interrupt */ | ||
846 | writel(VAL0|RINTEN0, mmio + INTEN0); | 848 | writel(VAL0|RINTEN0, mmio + INTEN0); |
847 | writel(VAL2 | RDMD0, mmio + CMD0); | 849 | writel(VAL2 | RDMD0, mmio + CMD0); |
850 | spin_unlock_irqrestore(&lp->lock, flags); | ||
848 | return 0; | 851 | return 0; |
852 | |||
849 | rx_not_empty: | 853 | rx_not_empty: |
850 | /* Do not call a netif_rx_complete */ | 854 | /* Do not call a netif_rx_complete */ |
851 | dev->quota -= num_rx_pkt; | 855 | dev->quota -= num_rx_pkt; |
852 | *budget -= num_rx_pkt; | 856 | *budget -= num_rx_pkt; |
853 | return 1; | 857 | return 1; |
854 | |||
855 | |||
856 | } | 858 | } |
857 | 859 | ||
858 | #else | 860 | #else |
@@ -1261,18 +1263,20 @@ static irqreturn_t amd8111e_interrupt(int irq, void *dev_id, struct pt_regs *reg | |||
1261 | struct net_device * dev = (struct net_device *) dev_id; | 1263 | struct net_device * dev = (struct net_device *) dev_id; |
1262 | struct amd8111e_priv *lp = netdev_priv(dev); | 1264 | struct amd8111e_priv *lp = netdev_priv(dev); |
1263 | void __iomem *mmio = lp->mmio; | 1265 | void __iomem *mmio = lp->mmio; |
1264 | unsigned int intr0; | 1266 | unsigned int intr0, intren0; |
1265 | unsigned int handled = 1; | 1267 | unsigned int handled = 1; |
1266 | 1268 | ||
1267 | if(dev == NULL) | 1269 | if(unlikely(dev == NULL)) |
1268 | return IRQ_NONE; | 1270 | return IRQ_NONE; |
1269 | 1271 | ||
1270 | if (regs) spin_lock (&lp->lock); | 1272 | spin_lock(&lp->lock); |
1273 | |||
1271 | /* disabling interrupt */ | 1274 | /* disabling interrupt */ |
1272 | writel(INTREN, mmio + CMD0); | 1275 | writel(INTREN, mmio + CMD0); |
1273 | 1276 | ||
1274 | /* Read interrupt status */ | 1277 | /* Read interrupt status */ |
1275 | intr0 = readl(mmio + INT0); | 1278 | intr0 = readl(mmio + INT0); |
1279 | intren0 = readl(mmio + INTEN0); | ||
1276 | 1280 | ||
1277 | /* Process all the INT event until INTR bit is clear. */ | 1281 | /* Process all the INT event until INTR bit is clear. */ |
1278 | 1282 | ||
@@ -1293,11 +1297,11 @@ static irqreturn_t amd8111e_interrupt(int irq, void *dev_id, struct pt_regs *reg | |||
1293 | /* Schedule a polling routine */ | 1297 | /* Schedule a polling routine */ |
1294 | __netif_rx_schedule(dev); | 1298 | __netif_rx_schedule(dev); |
1295 | } | 1299 | } |
1296 | else { | 1300 | else if (intren0 & RINTEN0) { |
1297 | printk("************Driver bug! \ | 1301 | printk("************Driver bug! \ |
1298 | interrupt while in poll\n"); | 1302 | interrupt while in poll\n"); |
1299 | /* Fix by disabling interrupts */ | 1303 | /* Fix by disable receive interrupts */ |
1300 | writel(RINT0, mmio + INT0); | 1304 | writel(RINTEN0, mmio + INTEN0); |
1301 | } | 1305 | } |
1302 | } | 1306 | } |
1303 | #else | 1307 | #else |
@@ -1321,7 +1325,7 @@ static irqreturn_t amd8111e_interrupt(int irq, void *dev_id, struct pt_regs *reg | |||
1321 | err_no_interrupt: | 1325 | err_no_interrupt: |
1322 | writel( VAL0 | INTREN,mmio + CMD0); | 1326 | writel( VAL0 | INTREN,mmio + CMD0); |
1323 | 1327 | ||
1324 | if (regs) spin_unlock(&lp->lock); | 1328 | spin_unlock(&lp->lock); |
1325 | 1329 | ||
1326 | return IRQ_RETVAL(handled); | 1330 | return IRQ_RETVAL(handled); |
1327 | } | 1331 | } |
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c new file mode 100644 index 000000000000..8acc655ec1e8 --- /dev/null +++ b/drivers/net/bnx2.c | |||
@@ -0,0 +1,5530 @@ | |||
1 | /* bnx2.c: Broadcom NX2 network driver. | ||
2 | * | ||
3 | * Copyright (c) 2004, 2005 Broadcom Corporation | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License as published by | ||
7 | * the Free Software Foundation. | ||
8 | * | ||
9 | * Written by: Michael Chan (mchan@broadcom.com) | ||
10 | */ | ||
11 | |||
12 | #include "bnx2.h" | ||
13 | #include "bnx2_fw.h" | ||
14 | |||
15 | #define DRV_MODULE_NAME "bnx2" | ||
16 | #define PFX DRV_MODULE_NAME ": " | ||
17 | #define DRV_MODULE_VERSION "1.2.19" | ||
18 | #define DRV_MODULE_RELDATE "May 23, 2005" | ||
19 | |||
20 | #define RUN_AT(x) (jiffies + (x)) | ||
21 | |||
22 | /* Time in jiffies before concluding the transmitter is hung. */ | ||
23 | #define TX_TIMEOUT (5*HZ) | ||
24 | |||
25 | static char version[] __devinitdata = | ||
26 | "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; | ||
27 | |||
28 | MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>"); | ||
29 | MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706 Driver"); | ||
30 | MODULE_LICENSE("GPL"); | ||
31 | MODULE_VERSION(DRV_MODULE_VERSION); | ||
32 | |||
33 | static int disable_msi = 0; | ||
34 | |||
35 | module_param(disable_msi, int, 0); | ||
36 | MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); | ||
37 | |||
38 | typedef enum { | ||
39 | BCM5706 = 0, | ||
40 | NC370T, | ||
41 | NC370I, | ||
42 | BCM5706S, | ||
43 | NC370F, | ||
44 | } board_t; | ||
45 | |||
46 | /* indexed by board_t, above */ | ||
47 | static struct { | ||
48 | char *name; | ||
49 | } board_info[] __devinitdata = { | ||
50 | { "Broadcom NetXtreme II BCM5706 1000Base-T" }, | ||
51 | { "HP NC370T Multifunction Gigabit Server Adapter" }, | ||
52 | { "HP NC370i Multifunction Gigabit Server Adapter" }, | ||
53 | { "Broadcom NetXtreme II BCM5706 1000Base-SX" }, | ||
54 | { "HP NC370F Multifunction Gigabit Server Adapter" }, | ||
55 | { 0 }, | ||
56 | }; | ||
57 | |||
58 | static struct pci_device_id bnx2_pci_tbl[] = { | ||
59 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, | ||
60 | PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T }, | ||
61 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, | ||
62 | PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I }, | ||
63 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706, | ||
64 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 }, | ||
65 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S, | ||
66 | PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F }, | ||
67 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S, | ||
68 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S }, | ||
69 | { 0, } | ||
70 | }; | ||
71 | |||
72 | static struct flash_spec flash_table[] = | ||
73 | { | ||
74 | /* Slow EEPROM */ | ||
75 | {0x00000000, 0x40030380, 0x009f0081, 0xa184a053, 0xaf000400, | ||
76 | 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, | ||
77 | SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, | ||
78 | "EEPROM - slow"}, | ||
79 | /* Fast EEPROM */ | ||
80 | {0x02000000, 0x62008380, 0x009f0081, 0xa184a053, 0xaf000400, | ||
81 | 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE, | ||
82 | SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE, | ||
83 | "EEPROM - fast"}, | ||
84 | /* ATMEL AT45DB011B (buffered flash) */ | ||
85 | {0x02000003, 0x6e008173, 0x00570081, 0x68848353, 0xaf000400, | ||
86 | 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE, | ||
87 | BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE, | ||
88 | "Buffered flash"}, | ||
89 | /* Saifun SA25F005 (non-buffered flash) */ | ||
90 | /* strap, cfg1, & write1 need updates */ | ||
91 | {0x01000003, 0x5f008081, 0x00050081, 0x03840253, 0xaf020406, | ||
92 | 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, | ||
93 | SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE, | ||
94 | "Non-buffered flash (64kB)"}, | ||
95 | /* Saifun SA25F010 (non-buffered flash) */ | ||
96 | /* strap, cfg1, & write1 need updates */ | ||
97 | {0x00000001, 0x47008081, 0x00050081, 0x03840253, 0xaf020406, | ||
98 | 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, | ||
99 | SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2, | ||
100 | "Non-buffered flash (128kB)"}, | ||
101 | /* Saifun SA25F020 (non-buffered flash) */ | ||
102 | /* strap, cfg1, & write1 need updates */ | ||
103 | {0x00000003, 0x4f008081, 0x00050081, 0x03840253, 0xaf020406, | ||
104 | 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE, | ||
105 | SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4, | ||
106 | "Non-buffered flash (256kB)"}, | ||
107 | }; | ||
108 | |||
109 | MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl); | ||
110 | |||
111 | static u32 | ||
112 | bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset) | ||
113 | { | ||
114 | REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); | ||
115 | return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW)); | ||
116 | } | ||
117 | |||
118 | static void | ||
119 | bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val) | ||
120 | { | ||
121 | REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); | ||
122 | REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val); | ||
123 | } | ||
124 | |||
125 | static void | ||
126 | bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val) | ||
127 | { | ||
128 | offset += cid_addr; | ||
129 | REG_WR(bp, BNX2_CTX_DATA_ADR, offset); | ||
130 | REG_WR(bp, BNX2_CTX_DATA, val); | ||
131 | } | ||
132 | |||
133 | static int | ||
134 | bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val) | ||
135 | { | ||
136 | u32 val1; | ||
137 | int i, ret; | ||
138 | |||
139 | if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) { | ||
140 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); | ||
141 | val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; | ||
142 | |||
143 | REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); | ||
144 | REG_RD(bp, BNX2_EMAC_MDIO_MODE); | ||
145 | |||
146 | udelay(40); | ||
147 | } | ||
148 | |||
149 | val1 = (bp->phy_addr << 21) | (reg << 16) | | ||
150 | BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT | | ||
151 | BNX2_EMAC_MDIO_COMM_START_BUSY; | ||
152 | REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1); | ||
153 | |||
154 | for (i = 0; i < 50; i++) { | ||
155 | udelay(10); | ||
156 | |||
157 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM); | ||
158 | if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) { | ||
159 | udelay(5); | ||
160 | |||
161 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM); | ||
162 | val1 &= BNX2_EMAC_MDIO_COMM_DATA; | ||
163 | |||
164 | break; | ||
165 | } | ||
166 | } | ||
167 | |||
168 | if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) { | ||
169 | *val = 0x0; | ||
170 | ret = -EBUSY; | ||
171 | } | ||
172 | else { | ||
173 | *val = val1; | ||
174 | ret = 0; | ||
175 | } | ||
176 | |||
177 | if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) { | ||
178 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); | ||
179 | val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; | ||
180 | |||
181 | REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); | ||
182 | REG_RD(bp, BNX2_EMAC_MDIO_MODE); | ||
183 | |||
184 | udelay(40); | ||
185 | } | ||
186 | |||
187 | return ret; | ||
188 | } | ||
189 | |||
190 | static int | ||
191 | bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val) | ||
192 | { | ||
193 | u32 val1; | ||
194 | int i, ret; | ||
195 | |||
196 | if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) { | ||
197 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); | ||
198 | val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; | ||
199 | |||
200 | REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); | ||
201 | REG_RD(bp, BNX2_EMAC_MDIO_MODE); | ||
202 | |||
203 | udelay(40); | ||
204 | } | ||
205 | |||
206 | val1 = (bp->phy_addr << 21) | (reg << 16) | val | | ||
207 | BNX2_EMAC_MDIO_COMM_COMMAND_WRITE | | ||
208 | BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT; | ||
209 | REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1); | ||
210 | |||
211 | for (i = 0; i < 50; i++) { | ||
212 | udelay(10); | ||
213 | |||
214 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM); | ||
215 | if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) { | ||
216 | udelay(5); | ||
217 | break; | ||
218 | } | ||
219 | } | ||
220 | |||
221 | if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) | ||
222 | ret = -EBUSY; | ||
223 | else | ||
224 | ret = 0; | ||
225 | |||
226 | if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) { | ||
227 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); | ||
228 | val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; | ||
229 | |||
230 | REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); | ||
231 | REG_RD(bp, BNX2_EMAC_MDIO_MODE); | ||
232 | |||
233 | udelay(40); | ||
234 | } | ||
235 | |||
236 | return ret; | ||
237 | } | ||
238 | |||
239 | static void | ||
240 | bnx2_disable_int(struct bnx2 *bp) | ||
241 | { | ||
242 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, | ||
243 | BNX2_PCICFG_INT_ACK_CMD_MASK_INT); | ||
244 | REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD); | ||
245 | } | ||
246 | |||
247 | static void | ||
248 | bnx2_enable_int(struct bnx2 *bp) | ||
249 | { | ||
250 | u32 val; | ||
251 | |||
252 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, | ||
253 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx); | ||
254 | |||
255 | val = REG_RD(bp, BNX2_HC_COMMAND); | ||
256 | REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW); | ||
257 | } | ||
258 | |||
259 | static void | ||
260 | bnx2_disable_int_sync(struct bnx2 *bp) | ||
261 | { | ||
262 | atomic_inc(&bp->intr_sem); | ||
263 | bnx2_disable_int(bp); | ||
264 | synchronize_irq(bp->pdev->irq); | ||
265 | } | ||
266 | |||
267 | static void | ||
268 | bnx2_netif_stop(struct bnx2 *bp) | ||
269 | { | ||
270 | bnx2_disable_int_sync(bp); | ||
271 | if (netif_running(bp->dev)) { | ||
272 | netif_poll_disable(bp->dev); | ||
273 | netif_tx_disable(bp->dev); | ||
274 | bp->dev->trans_start = jiffies; /* prevent tx timeout */ | ||
275 | } | ||
276 | } | ||
277 | |||
278 | static void | ||
279 | bnx2_netif_start(struct bnx2 *bp) | ||
280 | { | ||
281 | if (atomic_dec_and_test(&bp->intr_sem)) { | ||
282 | if (netif_running(bp->dev)) { | ||
283 | netif_wake_queue(bp->dev); | ||
284 | netif_poll_enable(bp->dev); | ||
285 | bnx2_enable_int(bp); | ||
286 | } | ||
287 | } | ||
288 | } | ||
289 | |||
290 | static void | ||
291 | bnx2_free_mem(struct bnx2 *bp) | ||
292 | { | ||
293 | if (bp->stats_blk) { | ||
294 | pci_free_consistent(bp->pdev, sizeof(struct statistics_block), | ||
295 | bp->stats_blk, bp->stats_blk_mapping); | ||
296 | bp->stats_blk = NULL; | ||
297 | } | ||
298 | if (bp->status_blk) { | ||
299 | pci_free_consistent(bp->pdev, sizeof(struct status_block), | ||
300 | bp->status_blk, bp->status_blk_mapping); | ||
301 | bp->status_blk = NULL; | ||
302 | } | ||
303 | if (bp->tx_desc_ring) { | ||
304 | pci_free_consistent(bp->pdev, | ||
305 | sizeof(struct tx_bd) * TX_DESC_CNT, | ||
306 | bp->tx_desc_ring, bp->tx_desc_mapping); | ||
307 | bp->tx_desc_ring = NULL; | ||
308 | } | ||
309 | if (bp->tx_buf_ring) { | ||
310 | kfree(bp->tx_buf_ring); | ||
311 | bp->tx_buf_ring = NULL; | ||
312 | } | ||
313 | if (bp->rx_desc_ring) { | ||
314 | pci_free_consistent(bp->pdev, | ||
315 | sizeof(struct rx_bd) * RX_DESC_CNT, | ||
316 | bp->rx_desc_ring, bp->rx_desc_mapping); | ||
317 | bp->rx_desc_ring = NULL; | ||
318 | } | ||
319 | if (bp->rx_buf_ring) { | ||
320 | kfree(bp->rx_buf_ring); | ||
321 | bp->rx_buf_ring = NULL; | ||
322 | } | ||
323 | } | ||
324 | |||
325 | static int | ||
326 | bnx2_alloc_mem(struct bnx2 *bp) | ||
327 | { | ||
328 | bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT, | ||
329 | GFP_KERNEL); | ||
330 | if (bp->tx_buf_ring == NULL) | ||
331 | return -ENOMEM; | ||
332 | |||
333 | memset(bp->tx_buf_ring, 0, sizeof(struct sw_bd) * TX_DESC_CNT); | ||
334 | bp->tx_desc_ring = pci_alloc_consistent(bp->pdev, | ||
335 | sizeof(struct tx_bd) * | ||
336 | TX_DESC_CNT, | ||
337 | &bp->tx_desc_mapping); | ||
338 | if (bp->tx_desc_ring == NULL) | ||
339 | goto alloc_mem_err; | ||
340 | |||
341 | bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT, | ||
342 | GFP_KERNEL); | ||
343 | if (bp->rx_buf_ring == NULL) | ||
344 | goto alloc_mem_err; | ||
345 | |||
346 | memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT); | ||
347 | bp->rx_desc_ring = pci_alloc_consistent(bp->pdev, | ||
348 | sizeof(struct rx_bd) * | ||
349 | RX_DESC_CNT, | ||
350 | &bp->rx_desc_mapping); | ||
351 | if (bp->rx_desc_ring == NULL) | ||
352 | goto alloc_mem_err; | ||
353 | |||
354 | bp->status_blk = pci_alloc_consistent(bp->pdev, | ||
355 | sizeof(struct status_block), | ||
356 | &bp->status_blk_mapping); | ||
357 | if (bp->status_blk == NULL) | ||
358 | goto alloc_mem_err; | ||
359 | |||
360 | memset(bp->status_blk, 0, sizeof(struct status_block)); | ||
361 | |||
362 | bp->stats_blk = pci_alloc_consistent(bp->pdev, | ||
363 | sizeof(struct statistics_block), | ||
364 | &bp->stats_blk_mapping); | ||
365 | if (bp->stats_blk == NULL) | ||
366 | goto alloc_mem_err; | ||
367 | |||
368 | memset(bp->stats_blk, 0, sizeof(struct statistics_block)); | ||
369 | |||
370 | return 0; | ||
371 | |||
372 | alloc_mem_err: | ||
373 | bnx2_free_mem(bp); | ||
374 | return -ENOMEM; | ||
375 | } | ||
376 | |||
377 | static void | ||
378 | bnx2_report_link(struct bnx2 *bp) | ||
379 | { | ||
380 | if (bp->link_up) { | ||
381 | netif_carrier_on(bp->dev); | ||
382 | printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name); | ||
383 | |||
384 | printk("%d Mbps ", bp->line_speed); | ||
385 | |||
386 | if (bp->duplex == DUPLEX_FULL) | ||
387 | printk("full duplex"); | ||
388 | else | ||
389 | printk("half duplex"); | ||
390 | |||
391 | if (bp->flow_ctrl) { | ||
392 | if (bp->flow_ctrl & FLOW_CTRL_RX) { | ||
393 | printk(", receive "); | ||
394 | if (bp->flow_ctrl & FLOW_CTRL_TX) | ||
395 | printk("& transmit "); | ||
396 | } | ||
397 | else { | ||
398 | printk(", transmit "); | ||
399 | } | ||
400 | printk("flow control ON"); | ||
401 | } | ||
402 | printk("\n"); | ||
403 | } | ||
404 | else { | ||
405 | netif_carrier_off(bp->dev); | ||
406 | printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name); | ||
407 | } | ||
408 | } | ||
409 | |||
410 | static void | ||
411 | bnx2_resolve_flow_ctrl(struct bnx2 *bp) | ||
412 | { | ||
413 | u32 local_adv, remote_adv; | ||
414 | |||
415 | bp->flow_ctrl = 0; | ||
416 | if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) != | ||
417 | (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) { | ||
418 | |||
419 | if (bp->duplex == DUPLEX_FULL) { | ||
420 | bp->flow_ctrl = bp->req_flow_ctrl; | ||
421 | } | ||
422 | return; | ||
423 | } | ||
424 | |||
425 | if (bp->duplex != DUPLEX_FULL) { | ||
426 | return; | ||
427 | } | ||
428 | |||
429 | bnx2_read_phy(bp, MII_ADVERTISE, &local_adv); | ||
430 | bnx2_read_phy(bp, MII_LPA, &remote_adv); | ||
431 | |||
432 | if (bp->phy_flags & PHY_SERDES_FLAG) { | ||
433 | u32 new_local_adv = 0; | ||
434 | u32 new_remote_adv = 0; | ||
435 | |||
436 | if (local_adv & ADVERTISE_1000XPAUSE) | ||
437 | new_local_adv |= ADVERTISE_PAUSE_CAP; | ||
438 | if (local_adv & ADVERTISE_1000XPSE_ASYM) | ||
439 | new_local_adv |= ADVERTISE_PAUSE_ASYM; | ||
440 | if (remote_adv & ADVERTISE_1000XPAUSE) | ||
441 | new_remote_adv |= ADVERTISE_PAUSE_CAP; | ||
442 | if (remote_adv & ADVERTISE_1000XPSE_ASYM) | ||
443 | new_remote_adv |= ADVERTISE_PAUSE_ASYM; | ||
444 | |||
445 | local_adv = new_local_adv; | ||
446 | remote_adv = new_remote_adv; | ||
447 | } | ||
448 | |||
449 | /* See Table 28B-3 of 802.3ab-1999 spec. */ | ||
450 | if (local_adv & ADVERTISE_PAUSE_CAP) { | ||
451 | if(local_adv & ADVERTISE_PAUSE_ASYM) { | ||
452 | if (remote_adv & ADVERTISE_PAUSE_CAP) { | ||
453 | bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; | ||
454 | } | ||
455 | else if (remote_adv & ADVERTISE_PAUSE_ASYM) { | ||
456 | bp->flow_ctrl = FLOW_CTRL_RX; | ||
457 | } | ||
458 | } | ||
459 | else { | ||
460 | if (remote_adv & ADVERTISE_PAUSE_CAP) { | ||
461 | bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; | ||
462 | } | ||
463 | } | ||
464 | } | ||
465 | else if (local_adv & ADVERTISE_PAUSE_ASYM) { | ||
466 | if ((remote_adv & ADVERTISE_PAUSE_CAP) && | ||
467 | (remote_adv & ADVERTISE_PAUSE_ASYM)) { | ||
468 | |||
469 | bp->flow_ctrl = FLOW_CTRL_TX; | ||
470 | } | ||
471 | } | ||
472 | } | ||
473 | |||
474 | static int | ||
475 | bnx2_serdes_linkup(struct bnx2 *bp) | ||
476 | { | ||
477 | u32 bmcr, local_adv, remote_adv, common; | ||
478 | |||
479 | bp->link_up = 1; | ||
480 | bp->line_speed = SPEED_1000; | ||
481 | |||
482 | bnx2_read_phy(bp, MII_BMCR, &bmcr); | ||
483 | if (bmcr & BMCR_FULLDPLX) { | ||
484 | bp->duplex = DUPLEX_FULL; | ||
485 | } | ||
486 | else { | ||
487 | bp->duplex = DUPLEX_HALF; | ||
488 | } | ||
489 | |||
490 | if (!(bmcr & BMCR_ANENABLE)) { | ||
491 | return 0; | ||
492 | } | ||
493 | |||
494 | bnx2_read_phy(bp, MII_ADVERTISE, &local_adv); | ||
495 | bnx2_read_phy(bp, MII_LPA, &remote_adv); | ||
496 | |||
497 | common = local_adv & remote_adv; | ||
498 | if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) { | ||
499 | |||
500 | if (common & ADVERTISE_1000XFULL) { | ||
501 | bp->duplex = DUPLEX_FULL; | ||
502 | } | ||
503 | else { | ||
504 | bp->duplex = DUPLEX_HALF; | ||
505 | } | ||
506 | } | ||
507 | |||
508 | return 0; | ||
509 | } | ||
510 | |||
511 | static int | ||
512 | bnx2_copper_linkup(struct bnx2 *bp) | ||
513 | { | ||
514 | u32 bmcr; | ||
515 | |||
516 | bnx2_read_phy(bp, MII_BMCR, &bmcr); | ||
517 | if (bmcr & BMCR_ANENABLE) { | ||
518 | u32 local_adv, remote_adv, common; | ||
519 | |||
520 | bnx2_read_phy(bp, MII_CTRL1000, &local_adv); | ||
521 | bnx2_read_phy(bp, MII_STAT1000, &remote_adv); | ||
522 | |||
523 | common = local_adv & (remote_adv >> 2); | ||
524 | if (common & ADVERTISE_1000FULL) { | ||
525 | bp->line_speed = SPEED_1000; | ||
526 | bp->duplex = DUPLEX_FULL; | ||
527 | } | ||
528 | else if (common & ADVERTISE_1000HALF) { | ||
529 | bp->line_speed = SPEED_1000; | ||
530 | bp->duplex = DUPLEX_HALF; | ||
531 | } | ||
532 | else { | ||
533 | bnx2_read_phy(bp, MII_ADVERTISE, &local_adv); | ||
534 | bnx2_read_phy(bp, MII_LPA, &remote_adv); | ||
535 | |||
536 | common = local_adv & remote_adv; | ||
537 | if (common & ADVERTISE_100FULL) { | ||
538 | bp->line_speed = SPEED_100; | ||
539 | bp->duplex = DUPLEX_FULL; | ||
540 | } | ||
541 | else if (common & ADVERTISE_100HALF) { | ||
542 | bp->line_speed = SPEED_100; | ||
543 | bp->duplex = DUPLEX_HALF; | ||
544 | } | ||
545 | else if (common & ADVERTISE_10FULL) { | ||
546 | bp->line_speed = SPEED_10; | ||
547 | bp->duplex = DUPLEX_FULL; | ||
548 | } | ||
549 | else if (common & ADVERTISE_10HALF) { | ||
550 | bp->line_speed = SPEED_10; | ||
551 | bp->duplex = DUPLEX_HALF; | ||
552 | } | ||
553 | else { | ||
554 | bp->line_speed = 0; | ||
555 | bp->link_up = 0; | ||
556 | } | ||
557 | } | ||
558 | } | ||
559 | else { | ||
560 | if (bmcr & BMCR_SPEED100) { | ||
561 | bp->line_speed = SPEED_100; | ||
562 | } | ||
563 | else { | ||
564 | bp->line_speed = SPEED_10; | ||
565 | } | ||
566 | if (bmcr & BMCR_FULLDPLX) { | ||
567 | bp->duplex = DUPLEX_FULL; | ||
568 | } | ||
569 | else { | ||
570 | bp->duplex = DUPLEX_HALF; | ||
571 | } | ||
572 | } | ||
573 | |||
574 | return 0; | ||
575 | } | ||
576 | |||
577 | static int | ||
578 | bnx2_set_mac_link(struct bnx2 *bp) | ||
579 | { | ||
580 | u32 val; | ||
581 | |||
582 | REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620); | ||
583 | if (bp->link_up && (bp->line_speed == SPEED_1000) && | ||
584 | (bp->duplex == DUPLEX_HALF)) { | ||
585 | REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff); | ||
586 | } | ||
587 | |||
588 | /* Configure the EMAC mode register. */ | ||
589 | val = REG_RD(bp, BNX2_EMAC_MODE); | ||
590 | |||
591 | val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX | | ||
592 | BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK); | ||
593 | |||
594 | if (bp->link_up) { | ||
595 | if (bp->line_speed != SPEED_1000) | ||
596 | val |= BNX2_EMAC_MODE_PORT_MII; | ||
597 | else | ||
598 | val |= BNX2_EMAC_MODE_PORT_GMII; | ||
599 | } | ||
600 | else { | ||
601 | val |= BNX2_EMAC_MODE_PORT_GMII; | ||
602 | } | ||
603 | |||
604 | /* Set the MAC to operate in the appropriate duplex mode. */ | ||
605 | if (bp->duplex == DUPLEX_HALF) | ||
606 | val |= BNX2_EMAC_MODE_HALF_DUPLEX; | ||
607 | REG_WR(bp, BNX2_EMAC_MODE, val); | ||
608 | |||
609 | /* Enable/disable rx PAUSE. */ | ||
610 | bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN; | ||
611 | |||
612 | if (bp->flow_ctrl & FLOW_CTRL_RX) | ||
613 | bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN; | ||
614 | REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode); | ||
615 | |||
616 | /* Enable/disable tx PAUSE. */ | ||
617 | val = REG_RD(bp, BNX2_EMAC_TX_MODE); | ||
618 | val &= ~BNX2_EMAC_TX_MODE_FLOW_EN; | ||
619 | |||
620 | if (bp->flow_ctrl & FLOW_CTRL_TX) | ||
621 | val |= BNX2_EMAC_TX_MODE_FLOW_EN; | ||
622 | REG_WR(bp, BNX2_EMAC_TX_MODE, val); | ||
623 | |||
624 | /* Acknowledge the interrupt. */ | ||
625 | REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE); | ||
626 | |||
627 | return 0; | ||
628 | } | ||
629 | |||
630 | static int | ||
631 | bnx2_set_link(struct bnx2 *bp) | ||
632 | { | ||
633 | u32 bmsr; | ||
634 | u8 link_up; | ||
635 | |||
636 | if (bp->loopback == MAC_LOOPBACK) { | ||
637 | bp->link_up = 1; | ||
638 | return 0; | ||
639 | } | ||
640 | |||
641 | link_up = bp->link_up; | ||
642 | |||
643 | bnx2_read_phy(bp, MII_BMSR, &bmsr); | ||
644 | bnx2_read_phy(bp, MII_BMSR, &bmsr); | ||
645 | |||
646 | if ((bp->phy_flags & PHY_SERDES_FLAG) && | ||
647 | (CHIP_NUM(bp) == CHIP_NUM_5706)) { | ||
648 | u32 val; | ||
649 | |||
650 | val = REG_RD(bp, BNX2_EMAC_STATUS); | ||
651 | if (val & BNX2_EMAC_STATUS_LINK) | ||
652 | bmsr |= BMSR_LSTATUS; | ||
653 | else | ||
654 | bmsr &= ~BMSR_LSTATUS; | ||
655 | } | ||
656 | |||
657 | if (bmsr & BMSR_LSTATUS) { | ||
658 | bp->link_up = 1; | ||
659 | |||
660 | if (bp->phy_flags & PHY_SERDES_FLAG) { | ||
661 | bnx2_serdes_linkup(bp); | ||
662 | } | ||
663 | else { | ||
664 | bnx2_copper_linkup(bp); | ||
665 | } | ||
666 | bnx2_resolve_flow_ctrl(bp); | ||
667 | } | ||
668 | else { | ||
669 | if ((bp->phy_flags & PHY_SERDES_FLAG) && | ||
670 | (bp->autoneg & AUTONEG_SPEED)) { | ||
671 | |||
672 | u32 bmcr; | ||
673 | |||
674 | bnx2_read_phy(bp, MII_BMCR, &bmcr); | ||
675 | if (!(bmcr & BMCR_ANENABLE)) { | ||
676 | bnx2_write_phy(bp, MII_BMCR, bmcr | | ||
677 | BMCR_ANENABLE); | ||
678 | } | ||
679 | } | ||
680 | bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG; | ||
681 | bp->link_up = 0; | ||
682 | } | ||
683 | |||
684 | if (bp->link_up != link_up) { | ||
685 | bnx2_report_link(bp); | ||
686 | } | ||
687 | |||
688 | bnx2_set_mac_link(bp); | ||
689 | |||
690 | return 0; | ||
691 | } | ||
692 | |||
693 | static int | ||
694 | bnx2_reset_phy(struct bnx2 *bp) | ||
695 | { | ||
696 | int i; | ||
697 | u32 reg; | ||
698 | |||
699 | bnx2_write_phy(bp, MII_BMCR, BMCR_RESET); | ||
700 | |||
701 | #define PHY_RESET_MAX_WAIT 100 | ||
702 | for (i = 0; i < PHY_RESET_MAX_WAIT; i++) { | ||
703 | udelay(10); | ||
704 | |||
705 | bnx2_read_phy(bp, MII_BMCR, ®); | ||
706 | if (!(reg & BMCR_RESET)) { | ||
707 | udelay(20); | ||
708 | break; | ||
709 | } | ||
710 | } | ||
711 | if (i == PHY_RESET_MAX_WAIT) { | ||
712 | return -EBUSY; | ||
713 | } | ||
714 | return 0; | ||
715 | } | ||
716 | |||
717 | static u32 | ||
718 | bnx2_phy_get_pause_adv(struct bnx2 *bp) | ||
719 | { | ||
720 | u32 adv = 0; | ||
721 | |||
722 | if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) == | ||
723 | (FLOW_CTRL_RX | FLOW_CTRL_TX)) { | ||
724 | |||
725 | if (bp->phy_flags & PHY_SERDES_FLAG) { | ||
726 | adv = ADVERTISE_1000XPAUSE; | ||
727 | } | ||
728 | else { | ||
729 | adv = ADVERTISE_PAUSE_CAP; | ||
730 | } | ||
731 | } | ||
732 | else if (bp->req_flow_ctrl & FLOW_CTRL_TX) { | ||
733 | if (bp->phy_flags & PHY_SERDES_FLAG) { | ||
734 | adv = ADVERTISE_1000XPSE_ASYM; | ||
735 | } | ||
736 | else { | ||
737 | adv = ADVERTISE_PAUSE_ASYM; | ||
738 | } | ||
739 | } | ||
740 | else if (bp->req_flow_ctrl & FLOW_CTRL_RX) { | ||
741 | if (bp->phy_flags & PHY_SERDES_FLAG) { | ||
742 | adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; | ||
743 | } | ||
744 | else { | ||
745 | adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | ||
746 | } | ||
747 | } | ||
748 | return adv; | ||
749 | } | ||
750 | |||
751 | static int | ||
752 | bnx2_setup_serdes_phy(struct bnx2 *bp) | ||
753 | { | ||
754 | u32 adv, bmcr; | ||
755 | u32 new_adv = 0; | ||
756 | |||
757 | if (!(bp->autoneg & AUTONEG_SPEED)) { | ||
758 | u32 new_bmcr; | ||
759 | |||
760 | bnx2_read_phy(bp, MII_BMCR, &bmcr); | ||
761 | new_bmcr = bmcr & ~BMCR_ANENABLE; | ||
762 | new_bmcr |= BMCR_SPEED1000; | ||
763 | if (bp->req_duplex == DUPLEX_FULL) { | ||
764 | new_bmcr |= BMCR_FULLDPLX; | ||
765 | } | ||
766 | else { | ||
767 | new_bmcr &= ~BMCR_FULLDPLX; | ||
768 | } | ||
769 | if (new_bmcr != bmcr) { | ||
770 | /* Force a link down visible on the other side */ | ||
771 | if (bp->link_up) { | ||
772 | bnx2_read_phy(bp, MII_ADVERTISE, &adv); | ||
773 | adv &= ~(ADVERTISE_1000XFULL | | ||
774 | ADVERTISE_1000XHALF); | ||
775 | bnx2_write_phy(bp, MII_ADVERTISE, adv); | ||
776 | bnx2_write_phy(bp, MII_BMCR, bmcr | | ||
777 | BMCR_ANRESTART | BMCR_ANENABLE); | ||
778 | |||
779 | bp->link_up = 0; | ||
780 | netif_carrier_off(bp->dev); | ||
781 | } | ||
782 | bnx2_write_phy(bp, MII_BMCR, new_bmcr); | ||
783 | } | ||
784 | return 0; | ||
785 | } | ||
786 | |||
787 | if (bp->advertising & ADVERTISED_1000baseT_Full) | ||
788 | new_adv |= ADVERTISE_1000XFULL; | ||
789 | |||
790 | new_adv |= bnx2_phy_get_pause_adv(bp); | ||
791 | |||
792 | bnx2_read_phy(bp, MII_ADVERTISE, &adv); | ||
793 | bnx2_read_phy(bp, MII_BMCR, &bmcr); | ||
794 | |||
795 | bp->serdes_an_pending = 0; | ||
796 | if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) { | ||
797 | /* Force a link down visible on the other side */ | ||
798 | if (bp->link_up) { | ||
799 | int i; | ||
800 | |||
801 | bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK); | ||
802 | for (i = 0; i < 110; i++) { | ||
803 | udelay(100); | ||
804 | } | ||
805 | } | ||
806 | |||
807 | bnx2_write_phy(bp, MII_ADVERTISE, new_adv); | ||
808 | bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | | ||
809 | BMCR_ANENABLE); | ||
810 | bp->serdes_an_pending = SERDES_AN_TIMEOUT / bp->timer_interval; | ||
811 | } | ||
812 | |||
813 | return 0; | ||
814 | } | ||
815 | |||
816 | #define ETHTOOL_ALL_FIBRE_SPEED \ | ||
817 | (ADVERTISED_1000baseT_Full) | ||
818 | |||
819 | #define ETHTOOL_ALL_COPPER_SPEED \ | ||
820 | (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \ | ||
821 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \ | ||
822 | ADVERTISED_1000baseT_Full) | ||
823 | |||
824 | #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \ | ||
825 | ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA) | ||
826 | |||
827 | #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL) | ||
828 | |||
829 | static int | ||
830 | bnx2_setup_copper_phy(struct bnx2 *bp) | ||
831 | { | ||
832 | u32 bmcr; | ||
833 | u32 new_bmcr; | ||
834 | |||
835 | bnx2_read_phy(bp, MII_BMCR, &bmcr); | ||
836 | |||
837 | if (bp->autoneg & AUTONEG_SPEED) { | ||
838 | u32 adv_reg, adv1000_reg; | ||
839 | u32 new_adv_reg = 0; | ||
840 | u32 new_adv1000_reg = 0; | ||
841 | |||
842 | bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg); | ||
843 | adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP | | ||
844 | ADVERTISE_PAUSE_ASYM); | ||
845 | |||
846 | bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg); | ||
847 | adv1000_reg &= PHY_ALL_1000_SPEED; | ||
848 | |||
849 | if (bp->advertising & ADVERTISED_10baseT_Half) | ||
850 | new_adv_reg |= ADVERTISE_10HALF; | ||
851 | if (bp->advertising & ADVERTISED_10baseT_Full) | ||
852 | new_adv_reg |= ADVERTISE_10FULL; | ||
853 | if (bp->advertising & ADVERTISED_100baseT_Half) | ||
854 | new_adv_reg |= ADVERTISE_100HALF; | ||
855 | if (bp->advertising & ADVERTISED_100baseT_Full) | ||
856 | new_adv_reg |= ADVERTISE_100FULL; | ||
857 | if (bp->advertising & ADVERTISED_1000baseT_Full) | ||
858 | new_adv1000_reg |= ADVERTISE_1000FULL; | ||
859 | |||
860 | new_adv_reg |= ADVERTISE_CSMA; | ||
861 | |||
862 | new_adv_reg |= bnx2_phy_get_pause_adv(bp); | ||
863 | |||
864 | if ((adv1000_reg != new_adv1000_reg) || | ||
865 | (adv_reg != new_adv_reg) || | ||
866 | ((bmcr & BMCR_ANENABLE) == 0)) { | ||
867 | |||
868 | bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg); | ||
869 | bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg); | ||
870 | bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART | | ||
871 | BMCR_ANENABLE); | ||
872 | } | ||
873 | else if (bp->link_up) { | ||
874 | /* Flow ctrl may have changed from auto to forced */ | ||
875 | /* or vice-versa. */ | ||
876 | |||
877 | bnx2_resolve_flow_ctrl(bp); | ||
878 | bnx2_set_mac_link(bp); | ||
879 | } | ||
880 | return 0; | ||
881 | } | ||
882 | |||
883 | new_bmcr = 0; | ||
884 | if (bp->req_line_speed == SPEED_100) { | ||
885 | new_bmcr |= BMCR_SPEED100; | ||
886 | } | ||
887 | if (bp->req_duplex == DUPLEX_FULL) { | ||
888 | new_bmcr |= BMCR_FULLDPLX; | ||
889 | } | ||
890 | if (new_bmcr != bmcr) { | ||
891 | u32 bmsr; | ||
892 | int i = 0; | ||
893 | |||
894 | bnx2_read_phy(bp, MII_BMSR, &bmsr); | ||
895 | bnx2_read_phy(bp, MII_BMSR, &bmsr); | ||
896 | |||
897 | if (bmsr & BMSR_LSTATUS) { | ||
898 | /* Force link down */ | ||
899 | bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK); | ||
900 | do { | ||
901 | udelay(100); | ||
902 | bnx2_read_phy(bp, MII_BMSR, &bmsr); | ||
903 | bnx2_read_phy(bp, MII_BMSR, &bmsr); | ||
904 | i++; | ||
905 | } while ((bmsr & BMSR_LSTATUS) && (i < 620)); | ||
906 | } | ||
907 | |||
908 | bnx2_write_phy(bp, MII_BMCR, new_bmcr); | ||
909 | |||
910 | /* Normally, the new speed is setup after the link has | ||
911 | * gone down and up again. In some cases, link will not go | ||
912 | * down so we need to set up the new speed here. | ||
913 | */ | ||
914 | if (bmsr & BMSR_LSTATUS) { | ||
915 | bp->line_speed = bp->req_line_speed; | ||
916 | bp->duplex = bp->req_duplex; | ||
917 | bnx2_resolve_flow_ctrl(bp); | ||
918 | bnx2_set_mac_link(bp); | ||
919 | } | ||
920 | } | ||
921 | return 0; | ||
922 | } | ||
923 | |||
924 | static int | ||
925 | bnx2_setup_phy(struct bnx2 *bp) | ||
926 | { | ||
927 | if (bp->loopback == MAC_LOOPBACK) | ||
928 | return 0; | ||
929 | |||
930 | if (bp->phy_flags & PHY_SERDES_FLAG) { | ||
931 | return (bnx2_setup_serdes_phy(bp)); | ||
932 | } | ||
933 | else { | ||
934 | return (bnx2_setup_copper_phy(bp)); | ||
935 | } | ||
936 | } | ||
937 | |||
938 | static int | ||
939 | bnx2_init_serdes_phy(struct bnx2 *bp) | ||
940 | { | ||
941 | bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG; | ||
942 | |||
943 | if (CHIP_NUM(bp) == CHIP_NUM_5706) { | ||
944 | REG_WR(bp, BNX2_MISC_UNUSED0, 0x300); | ||
945 | } | ||
946 | |||
947 | if (bp->dev->mtu > 1500) { | ||
948 | u32 val; | ||
949 | |||
950 | /* Set extended packet length bit */ | ||
951 | bnx2_write_phy(bp, 0x18, 0x7); | ||
952 | bnx2_read_phy(bp, 0x18, &val); | ||
953 | bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000); | ||
954 | |||
955 | bnx2_write_phy(bp, 0x1c, 0x6c00); | ||
956 | bnx2_read_phy(bp, 0x1c, &val); | ||
957 | bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02); | ||
958 | } | ||
959 | else { | ||
960 | u32 val; | ||
961 | |||
962 | bnx2_write_phy(bp, 0x18, 0x7); | ||
963 | bnx2_read_phy(bp, 0x18, &val); | ||
964 | bnx2_write_phy(bp, 0x18, val & ~0x4007); | ||
965 | |||
966 | bnx2_write_phy(bp, 0x1c, 0x6c00); | ||
967 | bnx2_read_phy(bp, 0x1c, &val); | ||
968 | bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00); | ||
969 | } | ||
970 | |||
971 | return 0; | ||
972 | } | ||
973 | |||
974 | static int | ||
975 | bnx2_init_copper_phy(struct bnx2 *bp) | ||
976 | { | ||
977 | bp->phy_flags |= PHY_CRC_FIX_FLAG; | ||
978 | |||
979 | if (bp->phy_flags & PHY_CRC_FIX_FLAG) { | ||
980 | bnx2_write_phy(bp, 0x18, 0x0c00); | ||
981 | bnx2_write_phy(bp, 0x17, 0x000a); | ||
982 | bnx2_write_phy(bp, 0x15, 0x310b); | ||
983 | bnx2_write_phy(bp, 0x17, 0x201f); | ||
984 | bnx2_write_phy(bp, 0x15, 0x9506); | ||
985 | bnx2_write_phy(bp, 0x17, 0x401f); | ||
986 | bnx2_write_phy(bp, 0x15, 0x14e2); | ||
987 | bnx2_write_phy(bp, 0x18, 0x0400); | ||
988 | } | ||
989 | |||
990 | if (bp->dev->mtu > 1500) { | ||
991 | u32 val; | ||
992 | |||
993 | /* Set extended packet length bit */ | ||
994 | bnx2_write_phy(bp, 0x18, 0x7); | ||
995 | bnx2_read_phy(bp, 0x18, &val); | ||
996 | bnx2_write_phy(bp, 0x18, val | 0x4000); | ||
997 | |||
998 | bnx2_read_phy(bp, 0x10, &val); | ||
999 | bnx2_write_phy(bp, 0x10, val | 0x1); | ||
1000 | } | ||
1001 | else { | ||
1002 | u32 val; | ||
1003 | |||
1004 | bnx2_write_phy(bp, 0x18, 0x7); | ||
1005 | bnx2_read_phy(bp, 0x18, &val); | ||
1006 | bnx2_write_phy(bp, 0x18, val & ~0x4007); | ||
1007 | |||
1008 | bnx2_read_phy(bp, 0x10, &val); | ||
1009 | bnx2_write_phy(bp, 0x10, val & ~0x1); | ||
1010 | } | ||
1011 | |||
1012 | return 0; | ||
1013 | } | ||
1014 | |||
1015 | |||
1016 | static int | ||
1017 | bnx2_init_phy(struct bnx2 *bp) | ||
1018 | { | ||
1019 | u32 val; | ||
1020 | int rc = 0; | ||
1021 | |||
1022 | bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG; | ||
1023 | bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG; | ||
1024 | |||
1025 | REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); | ||
1026 | |||
1027 | bnx2_reset_phy(bp); | ||
1028 | |||
1029 | bnx2_read_phy(bp, MII_PHYSID1, &val); | ||
1030 | bp->phy_id = val << 16; | ||
1031 | bnx2_read_phy(bp, MII_PHYSID2, &val); | ||
1032 | bp->phy_id |= val & 0xffff; | ||
1033 | |||
1034 | if (bp->phy_flags & PHY_SERDES_FLAG) { | ||
1035 | rc = bnx2_init_serdes_phy(bp); | ||
1036 | } | ||
1037 | else { | ||
1038 | rc = bnx2_init_copper_phy(bp); | ||
1039 | } | ||
1040 | |||
1041 | bnx2_setup_phy(bp); | ||
1042 | |||
1043 | return rc; | ||
1044 | } | ||
1045 | |||
1046 | static int | ||
1047 | bnx2_set_mac_loopback(struct bnx2 *bp) | ||
1048 | { | ||
1049 | u32 mac_mode; | ||
1050 | |||
1051 | mac_mode = REG_RD(bp, BNX2_EMAC_MODE); | ||
1052 | mac_mode &= ~BNX2_EMAC_MODE_PORT; | ||
1053 | mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK; | ||
1054 | REG_WR(bp, BNX2_EMAC_MODE, mac_mode); | ||
1055 | bp->link_up = 1; | ||
1056 | return 0; | ||
1057 | } | ||
1058 | |||
1059 | static int | ||
1060 | bnx2_fw_sync(struct bnx2 *bp, u32 msg_data) | ||
1061 | { | ||
1062 | int i; | ||
1063 | u32 val; | ||
1064 | |||
1065 | if (bp->fw_timed_out) | ||
1066 | return -EBUSY; | ||
1067 | |||
1068 | bp->fw_wr_seq++; | ||
1069 | msg_data |= bp->fw_wr_seq; | ||
1070 | |||
1071 | REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data); | ||
1072 | |||
1073 | /* wait for an acknowledgement. */ | ||
1074 | for (i = 0; i < (FW_ACK_TIME_OUT_MS * 1000)/5; i++) { | ||
1075 | udelay(5); | ||
1076 | |||
1077 | val = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_FW_MB); | ||
1078 | |||
1079 | if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ)) | ||
1080 | break; | ||
1081 | } | ||
1082 | |||
1083 | /* If we timed out, inform the firmware that this is the case. */ | ||
1084 | if (((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) && | ||
1085 | ((msg_data & BNX2_DRV_MSG_DATA) != BNX2_DRV_MSG_DATA_WAIT0)) { | ||
1086 | |||
1087 | msg_data &= ~BNX2_DRV_MSG_CODE; | ||
1088 | msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT; | ||
1089 | |||
1090 | REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data); | ||
1091 | |||
1092 | bp->fw_timed_out = 1; | ||
1093 | |||
1094 | return -EBUSY; | ||
1095 | } | ||
1096 | |||
1097 | return 0; | ||
1098 | } | ||
1099 | |||
1100 | static void | ||
1101 | bnx2_init_context(struct bnx2 *bp) | ||
1102 | { | ||
1103 | u32 vcid; | ||
1104 | |||
1105 | vcid = 96; | ||
1106 | while (vcid) { | ||
1107 | u32 vcid_addr, pcid_addr, offset; | ||
1108 | |||
1109 | vcid--; | ||
1110 | |||
1111 | if (CHIP_ID(bp) == CHIP_ID_5706_A0) { | ||
1112 | u32 new_vcid; | ||
1113 | |||
1114 | vcid_addr = GET_PCID_ADDR(vcid); | ||
1115 | if (vcid & 0x8) { | ||
1116 | new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7); | ||
1117 | } | ||
1118 | else { | ||
1119 | new_vcid = vcid; | ||
1120 | } | ||
1121 | pcid_addr = GET_PCID_ADDR(new_vcid); | ||
1122 | } | ||
1123 | else { | ||
1124 | vcid_addr = GET_CID_ADDR(vcid); | ||
1125 | pcid_addr = vcid_addr; | ||
1126 | } | ||
1127 | |||
1128 | REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00); | ||
1129 | REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr); | ||
1130 | |||
1131 | /* Zero out the context. */ | ||
1132 | for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) { | ||
1133 | CTX_WR(bp, 0x00, offset, 0); | ||
1134 | } | ||
1135 | |||
1136 | REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr); | ||
1137 | REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr); | ||
1138 | } | ||
1139 | } | ||
1140 | |||
1141 | static int | ||
1142 | bnx2_alloc_bad_rbuf(struct bnx2 *bp) | ||
1143 | { | ||
1144 | u16 *good_mbuf; | ||
1145 | u32 good_mbuf_cnt; | ||
1146 | u32 val; | ||
1147 | |||
1148 | good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL); | ||
1149 | if (good_mbuf == NULL) { | ||
1150 | printk(KERN_ERR PFX "Failed to allocate memory in " | ||
1151 | "bnx2_alloc_bad_rbuf\n"); | ||
1152 | return -ENOMEM; | ||
1153 | } | ||
1154 | |||
1155 | REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, | ||
1156 | BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE); | ||
1157 | |||
1158 | good_mbuf_cnt = 0; | ||
1159 | |||
1160 | /* Allocate a bunch of mbufs and save the good ones in an array. */ | ||
1161 | val = REG_RD_IND(bp, BNX2_RBUF_STATUS1); | ||
1162 | while (val & BNX2_RBUF_STATUS1_FREE_COUNT) { | ||
1163 | REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ); | ||
1164 | |||
1165 | val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC); | ||
1166 | |||
1167 | val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE; | ||
1168 | |||
1169 | /* The addresses with Bit 9 set are bad memory blocks. */ | ||
1170 | if (!(val & (1 << 9))) { | ||
1171 | good_mbuf[good_mbuf_cnt] = (u16) val; | ||
1172 | good_mbuf_cnt++; | ||
1173 | } | ||
1174 | |||
1175 | val = REG_RD_IND(bp, BNX2_RBUF_STATUS1); | ||
1176 | } | ||
1177 | |||
1178 | /* Free the good ones back to the mbuf pool thus discarding | ||
1179 | * all the bad ones. */ | ||
1180 | while (good_mbuf_cnt) { | ||
1181 | good_mbuf_cnt--; | ||
1182 | |||
1183 | val = good_mbuf[good_mbuf_cnt]; | ||
1184 | val = (val << 9) | val | 1; | ||
1185 | |||
1186 | REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val); | ||
1187 | } | ||
1188 | kfree(good_mbuf); | ||
1189 | return 0; | ||
1190 | } | ||
1191 | |||
1192 | static void | ||
1193 | bnx2_set_mac_addr(struct bnx2 *bp) | ||
1194 | { | ||
1195 | u32 val; | ||
1196 | u8 *mac_addr = bp->dev->dev_addr; | ||
1197 | |||
1198 | val = (mac_addr[0] << 8) | mac_addr[1]; | ||
1199 | |||
1200 | REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val); | ||
1201 | |||
1202 | val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | | ||
1203 | (mac_addr[4] << 8) | mac_addr[5]; | ||
1204 | |||
1205 | REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val); | ||
1206 | } | ||
1207 | |||
1208 | static inline int | ||
1209 | bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index) | ||
1210 | { | ||
1211 | struct sk_buff *skb; | ||
1212 | struct sw_bd *rx_buf = &bp->rx_buf_ring[index]; | ||
1213 | dma_addr_t mapping; | ||
1214 | struct rx_bd *rxbd = &bp->rx_desc_ring[index]; | ||
1215 | unsigned long align; | ||
1216 | |||
1217 | skb = dev_alloc_skb(bp->rx_buf_size); | ||
1218 | if (skb == NULL) { | ||
1219 | return -ENOMEM; | ||
1220 | } | ||
1221 | |||
1222 | if (unlikely((align = (unsigned long) skb->data & 0x7))) { | ||
1223 | skb_reserve(skb, 8 - align); | ||
1224 | } | ||
1225 | |||
1226 | skb->dev = bp->dev; | ||
1227 | mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size, | ||
1228 | PCI_DMA_FROMDEVICE); | ||
1229 | |||
1230 | rx_buf->skb = skb; | ||
1231 | pci_unmap_addr_set(rx_buf, mapping, mapping); | ||
1232 | |||
1233 | rxbd->rx_bd_haddr_hi = (u64) mapping >> 32; | ||
1234 | rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff; | ||
1235 | |||
1236 | bp->rx_prod_bseq += bp->rx_buf_use_size; | ||
1237 | |||
1238 | return 0; | ||
1239 | } | ||
1240 | |||
1241 | static void | ||
1242 | bnx2_phy_int(struct bnx2 *bp) | ||
1243 | { | ||
1244 | u32 new_link_state, old_link_state; | ||
1245 | |||
1246 | new_link_state = bp->status_blk->status_attn_bits & | ||
1247 | STATUS_ATTN_BITS_LINK_STATE; | ||
1248 | old_link_state = bp->status_blk->status_attn_bits_ack & | ||
1249 | STATUS_ATTN_BITS_LINK_STATE; | ||
1250 | if (new_link_state != old_link_state) { | ||
1251 | if (new_link_state) { | ||
1252 | REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, | ||
1253 | STATUS_ATTN_BITS_LINK_STATE); | ||
1254 | } | ||
1255 | else { | ||
1256 | REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, | ||
1257 | STATUS_ATTN_BITS_LINK_STATE); | ||
1258 | } | ||
1259 | bnx2_set_link(bp); | ||
1260 | } | ||
1261 | } | ||
1262 | |||
1263 | static void | ||
1264 | bnx2_tx_int(struct bnx2 *bp) | ||
1265 | { | ||
1266 | u16 hw_cons, sw_cons, sw_ring_cons; | ||
1267 | int tx_free_bd = 0; | ||
1268 | |||
1269 | hw_cons = bp->status_blk->status_tx_quick_consumer_index0; | ||
1270 | if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) { | ||
1271 | hw_cons++; | ||
1272 | } | ||
1273 | sw_cons = bp->tx_cons; | ||
1274 | |||
1275 | while (sw_cons != hw_cons) { | ||
1276 | struct sw_bd *tx_buf; | ||
1277 | struct sk_buff *skb; | ||
1278 | int i, last; | ||
1279 | |||
1280 | sw_ring_cons = TX_RING_IDX(sw_cons); | ||
1281 | |||
1282 | tx_buf = &bp->tx_buf_ring[sw_ring_cons]; | ||
1283 | skb = tx_buf->skb; | ||
1284 | #ifdef BCM_TSO | ||
1285 | /* partial BD completions possible with TSO packets */ | ||
1286 | if (skb_shinfo(skb)->tso_size) { | ||
1287 | u16 last_idx, last_ring_idx; | ||
1288 | |||
1289 | last_idx = sw_cons + | ||
1290 | skb_shinfo(skb)->nr_frags + 1; | ||
1291 | last_ring_idx = sw_ring_cons + | ||
1292 | skb_shinfo(skb)->nr_frags + 1; | ||
1293 | if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) { | ||
1294 | last_idx++; | ||
1295 | } | ||
1296 | if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) { | ||
1297 | break; | ||
1298 | } | ||
1299 | } | ||
1300 | #endif | ||
1301 | pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping), | ||
1302 | skb_headlen(skb), PCI_DMA_TODEVICE); | ||
1303 | |||
1304 | tx_buf->skb = NULL; | ||
1305 | last = skb_shinfo(skb)->nr_frags; | ||
1306 | |||
1307 | for (i = 0; i < last; i++) { | ||
1308 | sw_cons = NEXT_TX_BD(sw_cons); | ||
1309 | |||
1310 | pci_unmap_page(bp->pdev, | ||
1311 | pci_unmap_addr( | ||
1312 | &bp->tx_buf_ring[TX_RING_IDX(sw_cons)], | ||
1313 | mapping), | ||
1314 | skb_shinfo(skb)->frags[i].size, | ||
1315 | PCI_DMA_TODEVICE); | ||
1316 | } | ||
1317 | |||
1318 | sw_cons = NEXT_TX_BD(sw_cons); | ||
1319 | |||
1320 | tx_free_bd += last + 1; | ||
1321 | |||
1322 | dev_kfree_skb_irq(skb); | ||
1323 | |||
1324 | hw_cons = bp->status_blk->status_tx_quick_consumer_index0; | ||
1325 | if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) { | ||
1326 | hw_cons++; | ||
1327 | } | ||
1328 | } | ||
1329 | |||
1330 | atomic_add(tx_free_bd, &bp->tx_avail_bd); | ||
1331 | |||
1332 | if (unlikely(netif_queue_stopped(bp->dev))) { | ||
1333 | unsigned long flags; | ||
1334 | |||
1335 | spin_lock_irqsave(&bp->tx_lock, flags); | ||
1336 | if ((netif_queue_stopped(bp->dev)) && | ||
1337 | (atomic_read(&bp->tx_avail_bd) > MAX_SKB_FRAGS)) { | ||
1338 | |||
1339 | netif_wake_queue(bp->dev); | ||
1340 | } | ||
1341 | spin_unlock_irqrestore(&bp->tx_lock, flags); | ||
1342 | } | ||
1343 | |||
1344 | bp->tx_cons = sw_cons; | ||
1345 | |||
1346 | } | ||
1347 | |||
1348 | static inline void | ||
1349 | bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb, | ||
1350 | u16 cons, u16 prod) | ||
1351 | { | ||
1352 | struct sw_bd *cons_rx_buf = &bp->rx_buf_ring[cons]; | ||
1353 | struct sw_bd *prod_rx_buf = &bp->rx_buf_ring[prod]; | ||
1354 | struct rx_bd *cons_bd = &bp->rx_desc_ring[cons]; | ||
1355 | struct rx_bd *prod_bd = &bp->rx_desc_ring[prod]; | ||
1356 | |||
1357 | pci_dma_sync_single_for_device(bp->pdev, | ||
1358 | pci_unmap_addr(cons_rx_buf, mapping), | ||
1359 | bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE); | ||
1360 | |||
1361 | prod_rx_buf->skb = cons_rx_buf->skb; | ||
1362 | pci_unmap_addr_set(prod_rx_buf, mapping, | ||
1363 | pci_unmap_addr(cons_rx_buf, mapping)); | ||
1364 | |||
1365 | memcpy(prod_bd, cons_bd, 8); | ||
1366 | |||
1367 | bp->rx_prod_bseq += bp->rx_buf_use_size; | ||
1368 | |||
1369 | } | ||
1370 | |||
1371 | static int | ||
1372 | bnx2_rx_int(struct bnx2 *bp, int budget) | ||
1373 | { | ||
1374 | u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod; | ||
1375 | struct l2_fhdr *rx_hdr; | ||
1376 | int rx_pkt = 0; | ||
1377 | |||
1378 | hw_cons = bp->status_blk->status_rx_quick_consumer_index0; | ||
1379 | if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) { | ||
1380 | hw_cons++; | ||
1381 | } | ||
1382 | sw_cons = bp->rx_cons; | ||
1383 | sw_prod = bp->rx_prod; | ||
1384 | |||
1385 | /* Memory barrier necessary as speculative reads of the rx | ||
1386 | * buffer can be ahead of the index in the status block | ||
1387 | */ | ||
1388 | rmb(); | ||
1389 | while (sw_cons != hw_cons) { | ||
1390 | unsigned int len; | ||
1391 | u16 status; | ||
1392 | struct sw_bd *rx_buf; | ||
1393 | struct sk_buff *skb; | ||
1394 | |||
1395 | sw_ring_cons = RX_RING_IDX(sw_cons); | ||
1396 | sw_ring_prod = RX_RING_IDX(sw_prod); | ||
1397 | |||
1398 | rx_buf = &bp->rx_buf_ring[sw_ring_cons]; | ||
1399 | skb = rx_buf->skb; | ||
1400 | pci_dma_sync_single_for_cpu(bp->pdev, | ||
1401 | pci_unmap_addr(rx_buf, mapping), | ||
1402 | bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE); | ||
1403 | |||
1404 | rx_hdr = (struct l2_fhdr *) skb->data; | ||
1405 | len = rx_hdr->l2_fhdr_pkt_len - 4; | ||
1406 | |||
1407 | if (rx_hdr->l2_fhdr_errors & | ||
1408 | (L2_FHDR_ERRORS_BAD_CRC | | ||
1409 | L2_FHDR_ERRORS_PHY_DECODE | | ||
1410 | L2_FHDR_ERRORS_ALIGNMENT | | ||
1411 | L2_FHDR_ERRORS_TOO_SHORT | | ||
1412 | L2_FHDR_ERRORS_GIANT_FRAME)) { | ||
1413 | |||
1414 | goto reuse_rx; | ||
1415 | } | ||
1416 | |||
1417 | /* Since we don't have a jumbo ring, copy small packets | ||
1418 | * if mtu > 1500 | ||
1419 | */ | ||
1420 | if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) { | ||
1421 | struct sk_buff *new_skb; | ||
1422 | |||
1423 | new_skb = dev_alloc_skb(len + 2); | ||
1424 | if (new_skb == NULL) | ||
1425 | goto reuse_rx; | ||
1426 | |||
1427 | /* aligned copy */ | ||
1428 | memcpy(new_skb->data, | ||
1429 | skb->data + bp->rx_offset - 2, | ||
1430 | len + 2); | ||
1431 | |||
1432 | skb_reserve(new_skb, 2); | ||
1433 | skb_put(new_skb, len); | ||
1434 | new_skb->dev = bp->dev; | ||
1435 | |||
1436 | bnx2_reuse_rx_skb(bp, skb, | ||
1437 | sw_ring_cons, sw_ring_prod); | ||
1438 | |||
1439 | skb = new_skb; | ||
1440 | } | ||
1441 | else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) { | ||
1442 | pci_unmap_single(bp->pdev, | ||
1443 | pci_unmap_addr(rx_buf, mapping), | ||
1444 | bp->rx_buf_use_size, PCI_DMA_FROMDEVICE); | ||
1445 | |||
1446 | skb_reserve(skb, bp->rx_offset); | ||
1447 | skb_put(skb, len); | ||
1448 | } | ||
1449 | else { | ||
1450 | reuse_rx: | ||
1451 | bnx2_reuse_rx_skb(bp, skb, | ||
1452 | sw_ring_cons, sw_ring_prod); | ||
1453 | goto next_rx; | ||
1454 | } | ||
1455 | |||
1456 | skb->protocol = eth_type_trans(skb, bp->dev); | ||
1457 | |||
1458 | if ((len > (bp->dev->mtu + ETH_HLEN)) && | ||
1459 | (htons(skb->protocol) != 0x8100)) { | ||
1460 | |||
1461 | dev_kfree_skb_irq(skb); | ||
1462 | goto next_rx; | ||
1463 | |||
1464 | } | ||
1465 | |||
1466 | status = rx_hdr->l2_fhdr_status; | ||
1467 | skb->ip_summed = CHECKSUM_NONE; | ||
1468 | if (bp->rx_csum && | ||
1469 | (status & (L2_FHDR_STATUS_TCP_SEGMENT | | ||
1470 | L2_FHDR_STATUS_UDP_DATAGRAM))) { | ||
1471 | |||
1472 | u16 cksum = rx_hdr->l2_fhdr_tcp_udp_xsum; | ||
1473 | |||
1474 | if (cksum == 0xffff) | ||
1475 | skb->ip_summed = CHECKSUM_UNNECESSARY; | ||
1476 | } | ||
1477 | |||
1478 | #ifdef BCM_VLAN | ||
1479 | if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) { | ||
1480 | vlan_hwaccel_receive_skb(skb, bp->vlgrp, | ||
1481 | rx_hdr->l2_fhdr_vlan_tag); | ||
1482 | } | ||
1483 | else | ||
1484 | #endif | ||
1485 | netif_receive_skb(skb); | ||
1486 | |||
1487 | bp->dev->last_rx = jiffies; | ||
1488 | rx_pkt++; | ||
1489 | |||
1490 | next_rx: | ||
1491 | rx_buf->skb = NULL; | ||
1492 | |||
1493 | sw_cons = NEXT_RX_BD(sw_cons); | ||
1494 | sw_prod = NEXT_RX_BD(sw_prod); | ||
1495 | |||
1496 | if ((rx_pkt == budget)) | ||
1497 | break; | ||
1498 | } | ||
1499 | bp->rx_cons = sw_cons; | ||
1500 | bp->rx_prod = sw_prod; | ||
1501 | |||
1502 | REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod); | ||
1503 | |||
1504 | REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq); | ||
1505 | |||
1506 | mmiowb(); | ||
1507 | |||
1508 | return rx_pkt; | ||
1509 | |||
1510 | } | ||
1511 | |||
1512 | /* MSI ISR - The only difference between this and the INTx ISR | ||
1513 | * is that the MSI interrupt is always serviced. | ||
1514 | */ | ||
1515 | static irqreturn_t | ||
1516 | bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs) | ||
1517 | { | ||
1518 | struct net_device *dev = dev_instance; | ||
1519 | struct bnx2 *bp = dev->priv; | ||
1520 | |||
1521 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, | ||
1522 | BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | | ||
1523 | BNX2_PCICFG_INT_ACK_CMD_MASK_INT); | ||
1524 | |||
1525 | /* Return here if interrupt is disabled. */ | ||
1526 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) { | ||
1527 | return IRQ_RETVAL(1); | ||
1528 | } | ||
1529 | |||
1530 | if (netif_rx_schedule_prep(dev)) { | ||
1531 | __netif_rx_schedule(dev); | ||
1532 | } | ||
1533 | |||
1534 | return IRQ_RETVAL(1); | ||
1535 | } | ||
1536 | |||
1537 | static irqreturn_t | ||
1538 | bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs) | ||
1539 | { | ||
1540 | struct net_device *dev = dev_instance; | ||
1541 | struct bnx2 *bp = dev->priv; | ||
1542 | |||
1543 | /* When using INTx, it is possible for the interrupt to arrive | ||
1544 | * at the CPU before the status block posted prior to the | ||
1545 | * interrupt. Reading a register will flush the status block. | ||
1546 | * When using MSI, the MSI message will always complete after | ||
1547 | * the status block write. | ||
1548 | */ | ||
1549 | if ((bp->status_blk->status_idx == bp->last_status_idx) || | ||
1550 | (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) & | ||
1551 | BNX2_PCICFG_MISC_STATUS_INTA_VALUE)) | ||
1552 | return IRQ_RETVAL(0); | ||
1553 | |||
1554 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, | ||
1555 | BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM | | ||
1556 | BNX2_PCICFG_INT_ACK_CMD_MASK_INT); | ||
1557 | |||
1558 | /* Return here if interrupt is shared and is disabled. */ | ||
1559 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) { | ||
1560 | return IRQ_RETVAL(1); | ||
1561 | } | ||
1562 | |||
1563 | if (netif_rx_schedule_prep(dev)) { | ||
1564 | __netif_rx_schedule(dev); | ||
1565 | } | ||
1566 | |||
1567 | return IRQ_RETVAL(1); | ||
1568 | } | ||
1569 | |||
1570 | static int | ||
1571 | bnx2_poll(struct net_device *dev, int *budget) | ||
1572 | { | ||
1573 | struct bnx2 *bp = dev->priv; | ||
1574 | int rx_done = 1; | ||
1575 | |||
1576 | bp->last_status_idx = bp->status_blk->status_idx; | ||
1577 | |||
1578 | rmb(); | ||
1579 | if ((bp->status_blk->status_attn_bits & | ||
1580 | STATUS_ATTN_BITS_LINK_STATE) != | ||
1581 | (bp->status_blk->status_attn_bits_ack & | ||
1582 | STATUS_ATTN_BITS_LINK_STATE)) { | ||
1583 | |||
1584 | unsigned long flags; | ||
1585 | |||
1586 | spin_lock_irqsave(&bp->phy_lock, flags); | ||
1587 | bnx2_phy_int(bp); | ||
1588 | spin_unlock_irqrestore(&bp->phy_lock, flags); | ||
1589 | } | ||
1590 | |||
1591 | if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_cons) { | ||
1592 | bnx2_tx_int(bp); | ||
1593 | } | ||
1594 | |||
1595 | if (bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) { | ||
1596 | int orig_budget = *budget; | ||
1597 | int work_done; | ||
1598 | |||
1599 | if (orig_budget > dev->quota) | ||
1600 | orig_budget = dev->quota; | ||
1601 | |||
1602 | work_done = bnx2_rx_int(bp, orig_budget); | ||
1603 | *budget -= work_done; | ||
1604 | dev->quota -= work_done; | ||
1605 | |||
1606 | if (work_done >= orig_budget) { | ||
1607 | rx_done = 0; | ||
1608 | } | ||
1609 | } | ||
1610 | |||
1611 | if (rx_done) { | ||
1612 | netif_rx_complete(dev); | ||
1613 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, | ||
1614 | BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | | ||
1615 | bp->last_status_idx); | ||
1616 | return 0; | ||
1617 | } | ||
1618 | |||
1619 | return 1; | ||
1620 | } | ||
1621 | |||
1622 | /* Called with rtnl_lock from vlan functions and also dev->xmit_lock | ||
1623 | * from set_multicast. | ||
1624 | */ | ||
1625 | static void | ||
1626 | bnx2_set_rx_mode(struct net_device *dev) | ||
1627 | { | ||
1628 | struct bnx2 *bp = dev->priv; | ||
1629 | u32 rx_mode, sort_mode; | ||
1630 | int i; | ||
1631 | unsigned long flags; | ||
1632 | |||
1633 | spin_lock_irqsave(&bp->phy_lock, flags); | ||
1634 | |||
1635 | rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS | | ||
1636 | BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG); | ||
1637 | sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN; | ||
1638 | #ifdef BCM_VLAN | ||
1639 | if (!bp->vlgrp) { | ||
1640 | rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG; | ||
1641 | } | ||
1642 | #else | ||
1643 | rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG; | ||
1644 | #endif | ||
1645 | if (dev->flags & IFF_PROMISC) { | ||
1646 | /* Promiscuous mode. */ | ||
1647 | rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS; | ||
1648 | sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN; | ||
1649 | } | ||
1650 | else if (dev->flags & IFF_ALLMULTI) { | ||
1651 | for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { | ||
1652 | REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), | ||
1653 | 0xffffffff); | ||
1654 | } | ||
1655 | sort_mode |= BNX2_RPM_SORT_USER0_MC_EN; | ||
1656 | } | ||
1657 | else { | ||
1658 | /* Accept one or more multicast(s). */ | ||
1659 | struct dev_mc_list *mclist; | ||
1660 | u32 mc_filter[NUM_MC_HASH_REGISTERS]; | ||
1661 | u32 regidx; | ||
1662 | u32 bit; | ||
1663 | u32 crc; | ||
1664 | |||
1665 | memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS); | ||
1666 | |||
1667 | for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; | ||
1668 | i++, mclist = mclist->next) { | ||
1669 | |||
1670 | crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr); | ||
1671 | bit = crc & 0xff; | ||
1672 | regidx = (bit & 0xe0) >> 5; | ||
1673 | bit &= 0x1f; | ||
1674 | mc_filter[regidx] |= (1 << bit); | ||
1675 | } | ||
1676 | |||
1677 | for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { | ||
1678 | REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), | ||
1679 | mc_filter[i]); | ||
1680 | } | ||
1681 | |||
1682 | sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN; | ||
1683 | } | ||
1684 | |||
1685 | if (rx_mode != bp->rx_mode) { | ||
1686 | bp->rx_mode = rx_mode; | ||
1687 | REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode); | ||
1688 | } | ||
1689 | |||
1690 | REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0); | ||
1691 | REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode); | ||
1692 | REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA); | ||
1693 | |||
1694 | spin_unlock_irqrestore(&bp->phy_lock, flags); | ||
1695 | } | ||
1696 | |||
1697 | static void | ||
1698 | load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len, | ||
1699 | u32 rv2p_proc) | ||
1700 | { | ||
1701 | int i; | ||
1702 | u32 val; | ||
1703 | |||
1704 | |||
1705 | for (i = 0; i < rv2p_code_len; i += 8) { | ||
1706 | REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code); | ||
1707 | rv2p_code++; | ||
1708 | REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code); | ||
1709 | rv2p_code++; | ||
1710 | |||
1711 | if (rv2p_proc == RV2P_PROC1) { | ||
1712 | val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR; | ||
1713 | REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val); | ||
1714 | } | ||
1715 | else { | ||
1716 | val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR; | ||
1717 | REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val); | ||
1718 | } | ||
1719 | } | ||
1720 | |||
1721 | /* Reset the processor, un-stall is done later. */ | ||
1722 | if (rv2p_proc == RV2P_PROC1) { | ||
1723 | REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET); | ||
1724 | } | ||
1725 | else { | ||
1726 | REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET); | ||
1727 | } | ||
1728 | } | ||
1729 | |||
1730 | static void | ||
1731 | load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) | ||
1732 | { | ||
1733 | u32 offset; | ||
1734 | u32 val; | ||
1735 | |||
1736 | /* Halt the CPU. */ | ||
1737 | val = REG_RD_IND(bp, cpu_reg->mode); | ||
1738 | val |= cpu_reg->mode_value_halt; | ||
1739 | REG_WR_IND(bp, cpu_reg->mode, val); | ||
1740 | REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); | ||
1741 | |||
1742 | /* Load the Text area. */ | ||
1743 | offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); | ||
1744 | if (fw->text) { | ||
1745 | int j; | ||
1746 | |||
1747 | for (j = 0; j < (fw->text_len / 4); j++, offset += 4) { | ||
1748 | REG_WR_IND(bp, offset, fw->text[j]); | ||
1749 | } | ||
1750 | } | ||
1751 | |||
1752 | /* Load the Data area. */ | ||
1753 | offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); | ||
1754 | if (fw->data) { | ||
1755 | int j; | ||
1756 | |||
1757 | for (j = 0; j < (fw->data_len / 4); j++, offset += 4) { | ||
1758 | REG_WR_IND(bp, offset, fw->data[j]); | ||
1759 | } | ||
1760 | } | ||
1761 | |||
1762 | /* Load the SBSS area. */ | ||
1763 | offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); | ||
1764 | if (fw->sbss) { | ||
1765 | int j; | ||
1766 | |||
1767 | for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) { | ||
1768 | REG_WR_IND(bp, offset, fw->sbss[j]); | ||
1769 | } | ||
1770 | } | ||
1771 | |||
1772 | /* Load the BSS area. */ | ||
1773 | offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); | ||
1774 | if (fw->bss) { | ||
1775 | int j; | ||
1776 | |||
1777 | for (j = 0; j < (fw->bss_len/4); j++, offset += 4) { | ||
1778 | REG_WR_IND(bp, offset, fw->bss[j]); | ||
1779 | } | ||
1780 | } | ||
1781 | |||
1782 | /* Load the Read-Only area. */ | ||
1783 | offset = cpu_reg->spad_base + | ||
1784 | (fw->rodata_addr - cpu_reg->mips_view_base); | ||
1785 | if (fw->rodata) { | ||
1786 | int j; | ||
1787 | |||
1788 | for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) { | ||
1789 | REG_WR_IND(bp, offset, fw->rodata[j]); | ||
1790 | } | ||
1791 | } | ||
1792 | |||
1793 | /* Clear the pre-fetch instruction. */ | ||
1794 | REG_WR_IND(bp, cpu_reg->inst, 0); | ||
1795 | REG_WR_IND(bp, cpu_reg->pc, fw->start_addr); | ||
1796 | |||
1797 | /* Start the CPU. */ | ||
1798 | val = REG_RD_IND(bp, cpu_reg->mode); | ||
1799 | val &= ~cpu_reg->mode_value_halt; | ||
1800 | REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); | ||
1801 | REG_WR_IND(bp, cpu_reg->mode, val); | ||
1802 | } | ||
1803 | |||
1804 | static void | ||
1805 | bnx2_init_cpus(struct bnx2 *bp) | ||
1806 | { | ||
1807 | struct cpu_reg cpu_reg; | ||
1808 | struct fw_info fw; | ||
1809 | |||
1810 | /* Initialize the RV2P processor. */ | ||
1811 | load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1); | ||
1812 | load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2); | ||
1813 | |||
1814 | /* Initialize the RX Processor. */ | ||
1815 | cpu_reg.mode = BNX2_RXP_CPU_MODE; | ||
1816 | cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT; | ||
1817 | cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA; | ||
1818 | cpu_reg.state = BNX2_RXP_CPU_STATE; | ||
1819 | cpu_reg.state_value_clear = 0xffffff; | ||
1820 | cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE; | ||
1821 | cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK; | ||
1822 | cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER; | ||
1823 | cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION; | ||
1824 | cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT; | ||
1825 | cpu_reg.spad_base = BNX2_RXP_SCRATCH; | ||
1826 | cpu_reg.mips_view_base = 0x8000000; | ||
1827 | |||
1828 | fw.ver_major = bnx2_RXP_b06FwReleaseMajor; | ||
1829 | fw.ver_minor = bnx2_RXP_b06FwReleaseMinor; | ||
1830 | fw.ver_fix = bnx2_RXP_b06FwReleaseFix; | ||
1831 | fw.start_addr = bnx2_RXP_b06FwStartAddr; | ||
1832 | |||
1833 | fw.text_addr = bnx2_RXP_b06FwTextAddr; | ||
1834 | fw.text_len = bnx2_RXP_b06FwTextLen; | ||
1835 | fw.text_index = 0; | ||
1836 | fw.text = bnx2_RXP_b06FwText; | ||
1837 | |||
1838 | fw.data_addr = bnx2_RXP_b06FwDataAddr; | ||
1839 | fw.data_len = bnx2_RXP_b06FwDataLen; | ||
1840 | fw.data_index = 0; | ||
1841 | fw.data = bnx2_RXP_b06FwData; | ||
1842 | |||
1843 | fw.sbss_addr = bnx2_RXP_b06FwSbssAddr; | ||
1844 | fw.sbss_len = bnx2_RXP_b06FwSbssLen; | ||
1845 | fw.sbss_index = 0; | ||
1846 | fw.sbss = bnx2_RXP_b06FwSbss; | ||
1847 | |||
1848 | fw.bss_addr = bnx2_RXP_b06FwBssAddr; | ||
1849 | fw.bss_len = bnx2_RXP_b06FwBssLen; | ||
1850 | fw.bss_index = 0; | ||
1851 | fw.bss = bnx2_RXP_b06FwBss; | ||
1852 | |||
1853 | fw.rodata_addr = bnx2_RXP_b06FwRodataAddr; | ||
1854 | fw.rodata_len = bnx2_RXP_b06FwRodataLen; | ||
1855 | fw.rodata_index = 0; | ||
1856 | fw.rodata = bnx2_RXP_b06FwRodata; | ||
1857 | |||
1858 | load_cpu_fw(bp, &cpu_reg, &fw); | ||
1859 | |||
1860 | /* Initialize the TX Processor. */ | ||
1861 | cpu_reg.mode = BNX2_TXP_CPU_MODE; | ||
1862 | cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT; | ||
1863 | cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA; | ||
1864 | cpu_reg.state = BNX2_TXP_CPU_STATE; | ||
1865 | cpu_reg.state_value_clear = 0xffffff; | ||
1866 | cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE; | ||
1867 | cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK; | ||
1868 | cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER; | ||
1869 | cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION; | ||
1870 | cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT; | ||
1871 | cpu_reg.spad_base = BNX2_TXP_SCRATCH; | ||
1872 | cpu_reg.mips_view_base = 0x8000000; | ||
1873 | |||
1874 | fw.ver_major = bnx2_TXP_b06FwReleaseMajor; | ||
1875 | fw.ver_minor = bnx2_TXP_b06FwReleaseMinor; | ||
1876 | fw.ver_fix = bnx2_TXP_b06FwReleaseFix; | ||
1877 | fw.start_addr = bnx2_TXP_b06FwStartAddr; | ||
1878 | |||
1879 | fw.text_addr = bnx2_TXP_b06FwTextAddr; | ||
1880 | fw.text_len = bnx2_TXP_b06FwTextLen; | ||
1881 | fw.text_index = 0; | ||
1882 | fw.text = bnx2_TXP_b06FwText; | ||
1883 | |||
1884 | fw.data_addr = bnx2_TXP_b06FwDataAddr; | ||
1885 | fw.data_len = bnx2_TXP_b06FwDataLen; | ||
1886 | fw.data_index = 0; | ||
1887 | fw.data = bnx2_TXP_b06FwData; | ||
1888 | |||
1889 | fw.sbss_addr = bnx2_TXP_b06FwSbssAddr; | ||
1890 | fw.sbss_len = bnx2_TXP_b06FwSbssLen; | ||
1891 | fw.sbss_index = 0; | ||
1892 | fw.sbss = bnx2_TXP_b06FwSbss; | ||
1893 | |||
1894 | fw.bss_addr = bnx2_TXP_b06FwBssAddr; | ||
1895 | fw.bss_len = bnx2_TXP_b06FwBssLen; | ||
1896 | fw.bss_index = 0; | ||
1897 | fw.bss = bnx2_TXP_b06FwBss; | ||
1898 | |||
1899 | fw.rodata_addr = bnx2_TXP_b06FwRodataAddr; | ||
1900 | fw.rodata_len = bnx2_TXP_b06FwRodataLen; | ||
1901 | fw.rodata_index = 0; | ||
1902 | fw.rodata = bnx2_TXP_b06FwRodata; | ||
1903 | |||
1904 | load_cpu_fw(bp, &cpu_reg, &fw); | ||
1905 | |||
1906 | /* Initialize the TX Patch-up Processor. */ | ||
1907 | cpu_reg.mode = BNX2_TPAT_CPU_MODE; | ||
1908 | cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT; | ||
1909 | cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA; | ||
1910 | cpu_reg.state = BNX2_TPAT_CPU_STATE; | ||
1911 | cpu_reg.state_value_clear = 0xffffff; | ||
1912 | cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE; | ||
1913 | cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK; | ||
1914 | cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER; | ||
1915 | cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION; | ||
1916 | cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT; | ||
1917 | cpu_reg.spad_base = BNX2_TPAT_SCRATCH; | ||
1918 | cpu_reg.mips_view_base = 0x8000000; | ||
1919 | |||
1920 | fw.ver_major = bnx2_TPAT_b06FwReleaseMajor; | ||
1921 | fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor; | ||
1922 | fw.ver_fix = bnx2_TPAT_b06FwReleaseFix; | ||
1923 | fw.start_addr = bnx2_TPAT_b06FwStartAddr; | ||
1924 | |||
1925 | fw.text_addr = bnx2_TPAT_b06FwTextAddr; | ||
1926 | fw.text_len = bnx2_TPAT_b06FwTextLen; | ||
1927 | fw.text_index = 0; | ||
1928 | fw.text = bnx2_TPAT_b06FwText; | ||
1929 | |||
1930 | fw.data_addr = bnx2_TPAT_b06FwDataAddr; | ||
1931 | fw.data_len = bnx2_TPAT_b06FwDataLen; | ||
1932 | fw.data_index = 0; | ||
1933 | fw.data = bnx2_TPAT_b06FwData; | ||
1934 | |||
1935 | fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr; | ||
1936 | fw.sbss_len = bnx2_TPAT_b06FwSbssLen; | ||
1937 | fw.sbss_index = 0; | ||
1938 | fw.sbss = bnx2_TPAT_b06FwSbss; | ||
1939 | |||
1940 | fw.bss_addr = bnx2_TPAT_b06FwBssAddr; | ||
1941 | fw.bss_len = bnx2_TPAT_b06FwBssLen; | ||
1942 | fw.bss_index = 0; | ||
1943 | fw.bss = bnx2_TPAT_b06FwBss; | ||
1944 | |||
1945 | fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr; | ||
1946 | fw.rodata_len = bnx2_TPAT_b06FwRodataLen; | ||
1947 | fw.rodata_index = 0; | ||
1948 | fw.rodata = bnx2_TPAT_b06FwRodata; | ||
1949 | |||
1950 | load_cpu_fw(bp, &cpu_reg, &fw); | ||
1951 | |||
1952 | /* Initialize the Completion Processor. */ | ||
1953 | cpu_reg.mode = BNX2_COM_CPU_MODE; | ||
1954 | cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT; | ||
1955 | cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA; | ||
1956 | cpu_reg.state = BNX2_COM_CPU_STATE; | ||
1957 | cpu_reg.state_value_clear = 0xffffff; | ||
1958 | cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE; | ||
1959 | cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK; | ||
1960 | cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER; | ||
1961 | cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION; | ||
1962 | cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT; | ||
1963 | cpu_reg.spad_base = BNX2_COM_SCRATCH; | ||
1964 | cpu_reg.mips_view_base = 0x8000000; | ||
1965 | |||
1966 | fw.ver_major = bnx2_COM_b06FwReleaseMajor; | ||
1967 | fw.ver_minor = bnx2_COM_b06FwReleaseMinor; | ||
1968 | fw.ver_fix = bnx2_COM_b06FwReleaseFix; | ||
1969 | fw.start_addr = bnx2_COM_b06FwStartAddr; | ||
1970 | |||
1971 | fw.text_addr = bnx2_COM_b06FwTextAddr; | ||
1972 | fw.text_len = bnx2_COM_b06FwTextLen; | ||
1973 | fw.text_index = 0; | ||
1974 | fw.text = bnx2_COM_b06FwText; | ||
1975 | |||
1976 | fw.data_addr = bnx2_COM_b06FwDataAddr; | ||
1977 | fw.data_len = bnx2_COM_b06FwDataLen; | ||
1978 | fw.data_index = 0; | ||
1979 | fw.data = bnx2_COM_b06FwData; | ||
1980 | |||
1981 | fw.sbss_addr = bnx2_COM_b06FwSbssAddr; | ||
1982 | fw.sbss_len = bnx2_COM_b06FwSbssLen; | ||
1983 | fw.sbss_index = 0; | ||
1984 | fw.sbss = bnx2_COM_b06FwSbss; | ||
1985 | |||
1986 | fw.bss_addr = bnx2_COM_b06FwBssAddr; | ||
1987 | fw.bss_len = bnx2_COM_b06FwBssLen; | ||
1988 | fw.bss_index = 0; | ||
1989 | fw.bss = bnx2_COM_b06FwBss; | ||
1990 | |||
1991 | fw.rodata_addr = bnx2_COM_b06FwRodataAddr; | ||
1992 | fw.rodata_len = bnx2_COM_b06FwRodataLen; | ||
1993 | fw.rodata_index = 0; | ||
1994 | fw.rodata = bnx2_COM_b06FwRodata; | ||
1995 | |||
1996 | load_cpu_fw(bp, &cpu_reg, &fw); | ||
1997 | |||
1998 | } | ||
1999 | |||
2000 | static int | ||
2001 | bnx2_set_power_state(struct bnx2 *bp, int state) | ||
2002 | { | ||
2003 | u16 pmcsr; | ||
2004 | |||
2005 | pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr); | ||
2006 | |||
2007 | switch (state) { | ||
2008 | case 0: { | ||
2009 | u32 val; | ||
2010 | |||
2011 | pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, | ||
2012 | (pmcsr & ~PCI_PM_CTRL_STATE_MASK) | | ||
2013 | PCI_PM_CTRL_PME_STATUS); | ||
2014 | |||
2015 | if (pmcsr & PCI_PM_CTRL_STATE_MASK) | ||
2016 | /* delay required during transition out of D3hot */ | ||
2017 | msleep(20); | ||
2018 | |||
2019 | val = REG_RD(bp, BNX2_EMAC_MODE); | ||
2020 | val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD; | ||
2021 | val &= ~BNX2_EMAC_MODE_MPKT; | ||
2022 | REG_WR(bp, BNX2_EMAC_MODE, val); | ||
2023 | |||
2024 | val = REG_RD(bp, BNX2_RPM_CONFIG); | ||
2025 | val &= ~BNX2_RPM_CONFIG_ACPI_ENA; | ||
2026 | REG_WR(bp, BNX2_RPM_CONFIG, val); | ||
2027 | break; | ||
2028 | } | ||
2029 | case 3: { | ||
2030 | int i; | ||
2031 | u32 val, wol_msg; | ||
2032 | |||
2033 | if (bp->wol) { | ||
2034 | u32 advertising; | ||
2035 | u8 autoneg; | ||
2036 | |||
2037 | autoneg = bp->autoneg; | ||
2038 | advertising = bp->advertising; | ||
2039 | |||
2040 | bp->autoneg = AUTONEG_SPEED; | ||
2041 | bp->advertising = ADVERTISED_10baseT_Half | | ||
2042 | ADVERTISED_10baseT_Full | | ||
2043 | ADVERTISED_100baseT_Half | | ||
2044 | ADVERTISED_100baseT_Full | | ||
2045 | ADVERTISED_Autoneg; | ||
2046 | |||
2047 | bnx2_setup_copper_phy(bp); | ||
2048 | |||
2049 | bp->autoneg = autoneg; | ||
2050 | bp->advertising = advertising; | ||
2051 | |||
2052 | bnx2_set_mac_addr(bp); | ||
2053 | |||
2054 | val = REG_RD(bp, BNX2_EMAC_MODE); | ||
2055 | |||
2056 | /* Enable port mode. */ | ||
2057 | val &= ~BNX2_EMAC_MODE_PORT; | ||
2058 | val |= BNX2_EMAC_MODE_PORT_MII | | ||
2059 | BNX2_EMAC_MODE_MPKT_RCVD | | ||
2060 | BNX2_EMAC_MODE_ACPI_RCVD | | ||
2061 | BNX2_EMAC_MODE_FORCE_LINK | | ||
2062 | BNX2_EMAC_MODE_MPKT; | ||
2063 | |||
2064 | REG_WR(bp, BNX2_EMAC_MODE, val); | ||
2065 | |||
2066 | /* receive all multicast */ | ||
2067 | for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) { | ||
2068 | REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4), | ||
2069 | 0xffffffff); | ||
2070 | } | ||
2071 | REG_WR(bp, BNX2_EMAC_RX_MODE, | ||
2072 | BNX2_EMAC_RX_MODE_SORT_MODE); | ||
2073 | |||
2074 | val = 1 | BNX2_RPM_SORT_USER0_BC_EN | | ||
2075 | BNX2_RPM_SORT_USER0_MC_EN; | ||
2076 | REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0); | ||
2077 | REG_WR(bp, BNX2_RPM_SORT_USER0, val); | ||
2078 | REG_WR(bp, BNX2_RPM_SORT_USER0, val | | ||
2079 | BNX2_RPM_SORT_USER0_ENA); | ||
2080 | |||
2081 | /* Need to enable EMAC and RPM for WOL. */ | ||
2082 | REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, | ||
2083 | BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE | | ||
2084 | BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE | | ||
2085 | BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE); | ||
2086 | |||
2087 | val = REG_RD(bp, BNX2_RPM_CONFIG); | ||
2088 | val &= ~BNX2_RPM_CONFIG_ACPI_ENA; | ||
2089 | REG_WR(bp, BNX2_RPM_CONFIG, val); | ||
2090 | |||
2091 | wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL; | ||
2092 | } | ||
2093 | else { | ||
2094 | wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; | ||
2095 | } | ||
2096 | |||
2097 | bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg); | ||
2098 | |||
2099 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | ||
2100 | if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || | ||
2101 | (CHIP_ID(bp) == CHIP_ID_5706_A1)) { | ||
2102 | |||
2103 | if (bp->wol) | ||
2104 | pmcsr |= 3; | ||
2105 | } | ||
2106 | else { | ||
2107 | pmcsr |= 3; | ||
2108 | } | ||
2109 | if (bp->wol) { | ||
2110 | pmcsr |= PCI_PM_CTRL_PME_ENABLE; | ||
2111 | } | ||
2112 | pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, | ||
2113 | pmcsr); | ||
2114 | |||
2115 | /* No more memory access after this point until | ||
2116 | * device is brought back to D0. | ||
2117 | */ | ||
2118 | udelay(50); | ||
2119 | break; | ||
2120 | } | ||
2121 | default: | ||
2122 | return -EINVAL; | ||
2123 | } | ||
2124 | return 0; | ||
2125 | } | ||
2126 | |||
2127 | static int | ||
2128 | bnx2_acquire_nvram_lock(struct bnx2 *bp) | ||
2129 | { | ||
2130 | u32 val; | ||
2131 | int j; | ||
2132 | |||
2133 | /* Request access to the flash interface. */ | ||
2134 | REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2); | ||
2135 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | ||
2136 | val = REG_RD(bp, BNX2_NVM_SW_ARB); | ||
2137 | if (val & BNX2_NVM_SW_ARB_ARB_ARB2) | ||
2138 | break; | ||
2139 | |||
2140 | udelay(5); | ||
2141 | } | ||
2142 | |||
2143 | if (j >= NVRAM_TIMEOUT_COUNT) | ||
2144 | return -EBUSY; | ||
2145 | |||
2146 | return 0; | ||
2147 | } | ||
2148 | |||
2149 | static int | ||
2150 | bnx2_release_nvram_lock(struct bnx2 *bp) | ||
2151 | { | ||
2152 | int j; | ||
2153 | u32 val; | ||
2154 | |||
2155 | /* Relinquish nvram interface. */ | ||
2156 | REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2); | ||
2157 | |||
2158 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | ||
2159 | val = REG_RD(bp, BNX2_NVM_SW_ARB); | ||
2160 | if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2)) | ||
2161 | break; | ||
2162 | |||
2163 | udelay(5); | ||
2164 | } | ||
2165 | |||
2166 | if (j >= NVRAM_TIMEOUT_COUNT) | ||
2167 | return -EBUSY; | ||
2168 | |||
2169 | return 0; | ||
2170 | } | ||
2171 | |||
2172 | |||
2173 | static int | ||
2174 | bnx2_enable_nvram_write(struct bnx2 *bp) | ||
2175 | { | ||
2176 | u32 val; | ||
2177 | |||
2178 | val = REG_RD(bp, BNX2_MISC_CFG); | ||
2179 | REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI); | ||
2180 | |||
2181 | if (!bp->flash_info->buffered) { | ||
2182 | int j; | ||
2183 | |||
2184 | REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); | ||
2185 | REG_WR(bp, BNX2_NVM_COMMAND, | ||
2186 | BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT); | ||
2187 | |||
2188 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | ||
2189 | udelay(5); | ||
2190 | |||
2191 | val = REG_RD(bp, BNX2_NVM_COMMAND); | ||
2192 | if (val & BNX2_NVM_COMMAND_DONE) | ||
2193 | break; | ||
2194 | } | ||
2195 | |||
2196 | if (j >= NVRAM_TIMEOUT_COUNT) | ||
2197 | return -EBUSY; | ||
2198 | } | ||
2199 | return 0; | ||
2200 | } | ||
2201 | |||
2202 | static void | ||
2203 | bnx2_disable_nvram_write(struct bnx2 *bp) | ||
2204 | { | ||
2205 | u32 val; | ||
2206 | |||
2207 | val = REG_RD(bp, BNX2_MISC_CFG); | ||
2208 | REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN); | ||
2209 | } | ||
2210 | |||
2211 | |||
2212 | static void | ||
2213 | bnx2_enable_nvram_access(struct bnx2 *bp) | ||
2214 | { | ||
2215 | u32 val; | ||
2216 | |||
2217 | val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE); | ||
2218 | /* Enable both bits, even on read. */ | ||
2219 | REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, | ||
2220 | val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN); | ||
2221 | } | ||
2222 | |||
2223 | static void | ||
2224 | bnx2_disable_nvram_access(struct bnx2 *bp) | ||
2225 | { | ||
2226 | u32 val; | ||
2227 | |||
2228 | val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE); | ||
2229 | /* Disable both bits, even after read. */ | ||
2230 | REG_WR(bp, BNX2_NVM_ACCESS_ENABLE, | ||
2231 | val & ~(BNX2_NVM_ACCESS_ENABLE_EN | | ||
2232 | BNX2_NVM_ACCESS_ENABLE_WR_EN)); | ||
2233 | } | ||
2234 | |||
2235 | static int | ||
2236 | bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset) | ||
2237 | { | ||
2238 | u32 cmd; | ||
2239 | int j; | ||
2240 | |||
2241 | if (bp->flash_info->buffered) | ||
2242 | /* Buffered flash, no erase needed */ | ||
2243 | return 0; | ||
2244 | |||
2245 | /* Build an erase command */ | ||
2246 | cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR | | ||
2247 | BNX2_NVM_COMMAND_DOIT; | ||
2248 | |||
2249 | /* Need to clear DONE bit separately. */ | ||
2250 | REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); | ||
2251 | |||
2252 | /* Address of the NVRAM to read from. */ | ||
2253 | REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); | ||
2254 | |||
2255 | /* Issue an erase command. */ | ||
2256 | REG_WR(bp, BNX2_NVM_COMMAND, cmd); | ||
2257 | |||
2258 | /* Wait for completion. */ | ||
2259 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | ||
2260 | u32 val; | ||
2261 | |||
2262 | udelay(5); | ||
2263 | |||
2264 | val = REG_RD(bp, BNX2_NVM_COMMAND); | ||
2265 | if (val & BNX2_NVM_COMMAND_DONE) | ||
2266 | break; | ||
2267 | } | ||
2268 | |||
2269 | if (j >= NVRAM_TIMEOUT_COUNT) | ||
2270 | return -EBUSY; | ||
2271 | |||
2272 | return 0; | ||
2273 | } | ||
2274 | |||
2275 | static int | ||
2276 | bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags) | ||
2277 | { | ||
2278 | u32 cmd; | ||
2279 | int j; | ||
2280 | |||
2281 | /* Build the command word. */ | ||
2282 | cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags; | ||
2283 | |||
2284 | /* Calculate an offset of a buffered flash. */ | ||
2285 | if (bp->flash_info->buffered) { | ||
2286 | offset = ((offset / bp->flash_info->page_size) << | ||
2287 | bp->flash_info->page_bits) + | ||
2288 | (offset % bp->flash_info->page_size); | ||
2289 | } | ||
2290 | |||
2291 | /* Need to clear DONE bit separately. */ | ||
2292 | REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); | ||
2293 | |||
2294 | /* Address of the NVRAM to read from. */ | ||
2295 | REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); | ||
2296 | |||
2297 | /* Issue a read command. */ | ||
2298 | REG_WR(bp, BNX2_NVM_COMMAND, cmd); | ||
2299 | |||
2300 | /* Wait for completion. */ | ||
2301 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | ||
2302 | u32 val; | ||
2303 | |||
2304 | udelay(5); | ||
2305 | |||
2306 | val = REG_RD(bp, BNX2_NVM_COMMAND); | ||
2307 | if (val & BNX2_NVM_COMMAND_DONE) { | ||
2308 | val = REG_RD(bp, BNX2_NVM_READ); | ||
2309 | |||
2310 | val = be32_to_cpu(val); | ||
2311 | memcpy(ret_val, &val, 4); | ||
2312 | break; | ||
2313 | } | ||
2314 | } | ||
2315 | if (j >= NVRAM_TIMEOUT_COUNT) | ||
2316 | return -EBUSY; | ||
2317 | |||
2318 | return 0; | ||
2319 | } | ||
2320 | |||
2321 | |||
2322 | static int | ||
2323 | bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags) | ||
2324 | { | ||
2325 | u32 cmd, val32; | ||
2326 | int j; | ||
2327 | |||
2328 | /* Build the command word. */ | ||
2329 | cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags; | ||
2330 | |||
2331 | /* Calculate an offset of a buffered flash. */ | ||
2332 | if (bp->flash_info->buffered) { | ||
2333 | offset = ((offset / bp->flash_info->page_size) << | ||
2334 | bp->flash_info->page_bits) + | ||
2335 | (offset % bp->flash_info->page_size); | ||
2336 | } | ||
2337 | |||
2338 | /* Need to clear DONE bit separately. */ | ||
2339 | REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE); | ||
2340 | |||
2341 | memcpy(&val32, val, 4); | ||
2342 | val32 = cpu_to_be32(val32); | ||
2343 | |||
2344 | /* Write the data. */ | ||
2345 | REG_WR(bp, BNX2_NVM_WRITE, val32); | ||
2346 | |||
2347 | /* Address of the NVRAM to write to. */ | ||
2348 | REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE); | ||
2349 | |||
2350 | /* Issue the write command. */ | ||
2351 | REG_WR(bp, BNX2_NVM_COMMAND, cmd); | ||
2352 | |||
2353 | /* Wait for completion. */ | ||
2354 | for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) { | ||
2355 | udelay(5); | ||
2356 | |||
2357 | if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE) | ||
2358 | break; | ||
2359 | } | ||
2360 | if (j >= NVRAM_TIMEOUT_COUNT) | ||
2361 | return -EBUSY; | ||
2362 | |||
2363 | return 0; | ||
2364 | } | ||
2365 | |||
2366 | static int | ||
2367 | bnx2_init_nvram(struct bnx2 *bp) | ||
2368 | { | ||
2369 | u32 val; | ||
2370 | int j, entry_count, rc; | ||
2371 | struct flash_spec *flash; | ||
2372 | |||
2373 | /* Determine the selected interface. */ | ||
2374 | val = REG_RD(bp, BNX2_NVM_CFG1); | ||
2375 | |||
2376 | entry_count = sizeof(flash_table) / sizeof(struct flash_spec); | ||
2377 | |||
2378 | rc = 0; | ||
2379 | if (val & 0x40000000) { | ||
2380 | |||
2381 | /* Flash interface has been reconfigured */ | ||
2382 | for (j = 0, flash = &flash_table[0]; j < entry_count; | ||
2383 | j++, flash++) { | ||
2384 | |||
2385 | if (val == flash->config1) { | ||
2386 | bp->flash_info = flash; | ||
2387 | break; | ||
2388 | } | ||
2389 | } | ||
2390 | } | ||
2391 | else { | ||
2392 | /* Not yet been reconfigured */ | ||
2393 | |||
2394 | for (j = 0, flash = &flash_table[0]; j < entry_count; | ||
2395 | j++, flash++) { | ||
2396 | |||
2397 | if ((val & FLASH_STRAP_MASK) == flash->strapping) { | ||
2398 | bp->flash_info = flash; | ||
2399 | |||
2400 | /* Request access to the flash interface. */ | ||
2401 | if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) | ||
2402 | return rc; | ||
2403 | |||
2404 | /* Enable access to flash interface */ | ||
2405 | bnx2_enable_nvram_access(bp); | ||
2406 | |||
2407 | /* Reconfigure the flash interface */ | ||
2408 | REG_WR(bp, BNX2_NVM_CFG1, flash->config1); | ||
2409 | REG_WR(bp, BNX2_NVM_CFG2, flash->config2); | ||
2410 | REG_WR(bp, BNX2_NVM_CFG3, flash->config3); | ||
2411 | REG_WR(bp, BNX2_NVM_WRITE1, flash->write1); | ||
2412 | |||
2413 | /* Disable access to flash interface */ | ||
2414 | bnx2_disable_nvram_access(bp); | ||
2415 | bnx2_release_nvram_lock(bp); | ||
2416 | |||
2417 | break; | ||
2418 | } | ||
2419 | } | ||
2420 | } /* if (val & 0x40000000) */ | ||
2421 | |||
2422 | if (j == entry_count) { | ||
2423 | bp->flash_info = NULL; | ||
2424 | printk(KERN_ALERT "Unknown flash/EEPROM type.\n"); | ||
2425 | rc = -ENODEV; | ||
2426 | } | ||
2427 | |||
2428 | return rc; | ||
2429 | } | ||
2430 | |||
2431 | static int | ||
2432 | bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf, | ||
2433 | int buf_size) | ||
2434 | { | ||
2435 | int rc = 0; | ||
2436 | u32 cmd_flags, offset32, len32, extra; | ||
2437 | |||
2438 | if (buf_size == 0) | ||
2439 | return 0; | ||
2440 | |||
2441 | /* Request access to the flash interface. */ | ||
2442 | if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) | ||
2443 | return rc; | ||
2444 | |||
2445 | /* Enable access to flash interface */ | ||
2446 | bnx2_enable_nvram_access(bp); | ||
2447 | |||
2448 | len32 = buf_size; | ||
2449 | offset32 = offset; | ||
2450 | extra = 0; | ||
2451 | |||
2452 | cmd_flags = 0; | ||
2453 | |||
2454 | if (offset32 & 3) { | ||
2455 | u8 buf[4]; | ||
2456 | u32 pre_len; | ||
2457 | |||
2458 | offset32 &= ~3; | ||
2459 | pre_len = 4 - (offset & 3); | ||
2460 | |||
2461 | if (pre_len >= len32) { | ||
2462 | pre_len = len32; | ||
2463 | cmd_flags = BNX2_NVM_COMMAND_FIRST | | ||
2464 | BNX2_NVM_COMMAND_LAST; | ||
2465 | } | ||
2466 | else { | ||
2467 | cmd_flags = BNX2_NVM_COMMAND_FIRST; | ||
2468 | } | ||
2469 | |||
2470 | rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags); | ||
2471 | |||
2472 | if (rc) | ||
2473 | return rc; | ||
2474 | |||
2475 | memcpy(ret_buf, buf + (offset & 3), pre_len); | ||
2476 | |||
2477 | offset32 += 4; | ||
2478 | ret_buf += pre_len; | ||
2479 | len32 -= pre_len; | ||
2480 | } | ||
2481 | if (len32 & 3) { | ||
2482 | extra = 4 - (len32 & 3); | ||
2483 | len32 = (len32 + 4) & ~3; | ||
2484 | } | ||
2485 | |||
2486 | if (len32 == 4) { | ||
2487 | u8 buf[4]; | ||
2488 | |||
2489 | if (cmd_flags) | ||
2490 | cmd_flags = BNX2_NVM_COMMAND_LAST; | ||
2491 | else | ||
2492 | cmd_flags = BNX2_NVM_COMMAND_FIRST | | ||
2493 | BNX2_NVM_COMMAND_LAST; | ||
2494 | |||
2495 | rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags); | ||
2496 | |||
2497 | memcpy(ret_buf, buf, 4 - extra); | ||
2498 | } | ||
2499 | else if (len32 > 0) { | ||
2500 | u8 buf[4]; | ||
2501 | |||
2502 | /* Read the first word. */ | ||
2503 | if (cmd_flags) | ||
2504 | cmd_flags = 0; | ||
2505 | else | ||
2506 | cmd_flags = BNX2_NVM_COMMAND_FIRST; | ||
2507 | |||
2508 | rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags); | ||
2509 | |||
2510 | /* Advance to the next dword. */ | ||
2511 | offset32 += 4; | ||
2512 | ret_buf += 4; | ||
2513 | len32 -= 4; | ||
2514 | |||
2515 | while (len32 > 4 && rc == 0) { | ||
2516 | rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0); | ||
2517 | |||
2518 | /* Advance to the next dword. */ | ||
2519 | offset32 += 4; | ||
2520 | ret_buf += 4; | ||
2521 | len32 -= 4; | ||
2522 | } | ||
2523 | |||
2524 | if (rc) | ||
2525 | return rc; | ||
2526 | |||
2527 | cmd_flags = BNX2_NVM_COMMAND_LAST; | ||
2528 | rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags); | ||
2529 | |||
2530 | memcpy(ret_buf, buf, 4 - extra); | ||
2531 | } | ||
2532 | |||
2533 | /* Disable access to flash interface */ | ||
2534 | bnx2_disable_nvram_access(bp); | ||
2535 | |||
2536 | bnx2_release_nvram_lock(bp); | ||
2537 | |||
2538 | return rc; | ||
2539 | } | ||
2540 | |||
2541 | static int | ||
2542 | bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf, | ||
2543 | int buf_size) | ||
2544 | { | ||
2545 | u32 written, offset32, len32; | ||
2546 | u8 *buf, start[4], end[4]; | ||
2547 | int rc = 0; | ||
2548 | int align_start, align_end; | ||
2549 | |||
2550 | buf = data_buf; | ||
2551 | offset32 = offset; | ||
2552 | len32 = buf_size; | ||
2553 | align_start = align_end = 0; | ||
2554 | |||
2555 | if ((align_start = (offset32 & 3))) { | ||
2556 | offset32 &= ~3; | ||
2557 | len32 += align_start; | ||
2558 | if ((rc = bnx2_nvram_read(bp, offset32, start, 4))) | ||
2559 | return rc; | ||
2560 | } | ||
2561 | |||
2562 | if (len32 & 3) { | ||
2563 | if ((len32 > 4) || !align_start) { | ||
2564 | align_end = 4 - (len32 & 3); | ||
2565 | len32 += align_end; | ||
2566 | if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, | ||
2567 | end, 4))) { | ||
2568 | return rc; | ||
2569 | } | ||
2570 | } | ||
2571 | } | ||
2572 | |||
2573 | if (align_start || align_end) { | ||
2574 | buf = kmalloc(len32, GFP_KERNEL); | ||
2575 | if (buf == 0) | ||
2576 | return -ENOMEM; | ||
2577 | if (align_start) { | ||
2578 | memcpy(buf, start, 4); | ||
2579 | } | ||
2580 | if (align_end) { | ||
2581 | memcpy(buf + len32 - 4, end, 4); | ||
2582 | } | ||
2583 | memcpy(buf + align_start, data_buf, buf_size); | ||
2584 | } | ||
2585 | |||
2586 | written = 0; | ||
2587 | while ((written < len32) && (rc == 0)) { | ||
2588 | u32 page_start, page_end, data_start, data_end; | ||
2589 | u32 addr, cmd_flags; | ||
2590 | int i; | ||
2591 | u8 flash_buffer[264]; | ||
2592 | |||
2593 | /* Find the page_start addr */ | ||
2594 | page_start = offset32 + written; | ||
2595 | page_start -= (page_start % bp->flash_info->page_size); | ||
2596 | /* Find the page_end addr */ | ||
2597 | page_end = page_start + bp->flash_info->page_size; | ||
2598 | /* Find the data_start addr */ | ||
2599 | data_start = (written == 0) ? offset32 : page_start; | ||
2600 | /* Find the data_end addr */ | ||
2601 | data_end = (page_end > offset32 + len32) ? | ||
2602 | (offset32 + len32) : page_end; | ||
2603 | |||
2604 | /* Request access to the flash interface. */ | ||
2605 | if ((rc = bnx2_acquire_nvram_lock(bp)) != 0) | ||
2606 | goto nvram_write_end; | ||
2607 | |||
2608 | /* Enable access to flash interface */ | ||
2609 | bnx2_enable_nvram_access(bp); | ||
2610 | |||
2611 | cmd_flags = BNX2_NVM_COMMAND_FIRST; | ||
2612 | if (bp->flash_info->buffered == 0) { | ||
2613 | int j; | ||
2614 | |||
2615 | /* Read the whole page into the buffer | ||
2616 | * (non-buffer flash only) */ | ||
2617 | for (j = 0; j < bp->flash_info->page_size; j += 4) { | ||
2618 | if (j == (bp->flash_info->page_size - 4)) { | ||
2619 | cmd_flags |= BNX2_NVM_COMMAND_LAST; | ||
2620 | } | ||
2621 | rc = bnx2_nvram_read_dword(bp, | ||
2622 | page_start + j, | ||
2623 | &flash_buffer[j], | ||
2624 | cmd_flags); | ||
2625 | |||
2626 | if (rc) | ||
2627 | goto nvram_write_end; | ||
2628 | |||
2629 | cmd_flags = 0; | ||
2630 | } | ||
2631 | } | ||
2632 | |||
2633 | /* Enable writes to flash interface (unlock write-protect) */ | ||
2634 | if ((rc = bnx2_enable_nvram_write(bp)) != 0) | ||
2635 | goto nvram_write_end; | ||
2636 | |||
2637 | /* Erase the page */ | ||
2638 | if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0) | ||
2639 | goto nvram_write_end; | ||
2640 | |||
2641 | /* Re-enable the write again for the actual write */ | ||
2642 | bnx2_enable_nvram_write(bp); | ||
2643 | |||
2644 | /* Loop to write back the buffer data from page_start to | ||
2645 | * data_start */ | ||
2646 | i = 0; | ||
2647 | if (bp->flash_info->buffered == 0) { | ||
2648 | for (addr = page_start; addr < data_start; | ||
2649 | addr += 4, i += 4) { | ||
2650 | |||
2651 | rc = bnx2_nvram_write_dword(bp, addr, | ||
2652 | &flash_buffer[i], cmd_flags); | ||
2653 | |||
2654 | if (rc != 0) | ||
2655 | goto nvram_write_end; | ||
2656 | |||
2657 | cmd_flags = 0; | ||
2658 | } | ||
2659 | } | ||
2660 | |||
2661 | /* Loop to write the new data from data_start to data_end */ | ||
2662 | for (addr = data_start; addr < data_end; addr += 4, i++) { | ||
2663 | if ((addr == page_end - 4) || | ||
2664 | ((bp->flash_info->buffered) && | ||
2665 | (addr == data_end - 4))) { | ||
2666 | |||
2667 | cmd_flags |= BNX2_NVM_COMMAND_LAST; | ||
2668 | } | ||
2669 | rc = bnx2_nvram_write_dword(bp, addr, buf, | ||
2670 | cmd_flags); | ||
2671 | |||
2672 | if (rc != 0) | ||
2673 | goto nvram_write_end; | ||
2674 | |||
2675 | cmd_flags = 0; | ||
2676 | buf += 4; | ||
2677 | } | ||
2678 | |||
2679 | /* Loop to write back the buffer data from data_end | ||
2680 | * to page_end */ | ||
2681 | if (bp->flash_info->buffered == 0) { | ||
2682 | for (addr = data_end; addr < page_end; | ||
2683 | addr += 4, i += 4) { | ||
2684 | |||
2685 | if (addr == page_end-4) { | ||
2686 | cmd_flags = BNX2_NVM_COMMAND_LAST; | ||
2687 | } | ||
2688 | rc = bnx2_nvram_write_dword(bp, addr, | ||
2689 | &flash_buffer[i], cmd_flags); | ||
2690 | |||
2691 | if (rc != 0) | ||
2692 | goto nvram_write_end; | ||
2693 | |||
2694 | cmd_flags = 0; | ||
2695 | } | ||
2696 | } | ||
2697 | |||
2698 | /* Disable writes to flash interface (lock write-protect) */ | ||
2699 | bnx2_disable_nvram_write(bp); | ||
2700 | |||
2701 | /* Disable access to flash interface */ | ||
2702 | bnx2_disable_nvram_access(bp); | ||
2703 | bnx2_release_nvram_lock(bp); | ||
2704 | |||
2705 | /* Increment written */ | ||
2706 | written += data_end - data_start; | ||
2707 | } | ||
2708 | |||
2709 | nvram_write_end: | ||
2710 | if (align_start || align_end) | ||
2711 | kfree(buf); | ||
2712 | return rc; | ||
2713 | } | ||
2714 | |||
2715 | static int | ||
2716 | bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) | ||
2717 | { | ||
2718 | u32 val; | ||
2719 | int i, rc = 0; | ||
2720 | |||
2721 | /* Wait for the current PCI transaction to complete before | ||
2722 | * issuing a reset. */ | ||
2723 | REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS, | ||
2724 | BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE | | ||
2725 | BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE | | ||
2726 | BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE | | ||
2727 | BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE); | ||
2728 | val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS); | ||
2729 | udelay(5); | ||
2730 | |||
2731 | /* Deposit a driver reset signature so the firmware knows that | ||
2732 | * this is a soft reset. */ | ||
2733 | REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_RESET_SIGNATURE, | ||
2734 | BNX2_DRV_RESET_SIGNATURE_MAGIC); | ||
2735 | |||
2736 | bp->fw_timed_out = 0; | ||
2737 | |||
2738 | /* Wait for the firmware to tell us it is ok to issue a reset. */ | ||
2739 | bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code); | ||
2740 | |||
2741 | /* Do a dummy read to force the chip to complete all current transaction | ||
2742 | * before we issue a reset. */ | ||
2743 | val = REG_RD(bp, BNX2_MISC_ID); | ||
2744 | |||
2745 | val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | | ||
2746 | BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | | ||
2747 | BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP; | ||
2748 | |||
2749 | /* Chip reset. */ | ||
2750 | REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val); | ||
2751 | |||
2752 | if ((CHIP_ID(bp) == CHIP_ID_5706_A0) || | ||
2753 | (CHIP_ID(bp) == CHIP_ID_5706_A1)) | ||
2754 | msleep(15); | ||
2755 | |||
2756 | /* Reset takes approximate 30 usec */ | ||
2757 | for (i = 0; i < 10; i++) { | ||
2758 | val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG); | ||
2759 | if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | | ||
2760 | BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) { | ||
2761 | break; | ||
2762 | } | ||
2763 | udelay(10); | ||
2764 | } | ||
2765 | |||
2766 | if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ | | ||
2767 | BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) { | ||
2768 | printk(KERN_ERR PFX "Chip reset did not complete\n"); | ||
2769 | return -EBUSY; | ||
2770 | } | ||
2771 | |||
2772 | /* Make sure byte swapping is properly configured. */ | ||
2773 | val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0); | ||
2774 | if (val != 0x01020304) { | ||
2775 | printk(KERN_ERR PFX "Chip not in correct endian mode\n"); | ||
2776 | return -ENODEV; | ||
2777 | } | ||
2778 | |||
2779 | bp->fw_timed_out = 0; | ||
2780 | |||
2781 | /* Wait for the firmware to finish its initialization. */ | ||
2782 | bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code); | ||
2783 | |||
2784 | if (CHIP_ID(bp) == CHIP_ID_5706_A0) { | ||
2785 | /* Adjust the voltage regular to two steps lower. The default | ||
2786 | * of this register is 0x0000000e. */ | ||
2787 | REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa); | ||
2788 | |||
2789 | /* Remove bad rbuf memory from the free pool. */ | ||
2790 | rc = bnx2_alloc_bad_rbuf(bp); | ||
2791 | } | ||
2792 | |||
2793 | return rc; | ||
2794 | } | ||
2795 | |||
2796 | static int | ||
2797 | bnx2_init_chip(struct bnx2 *bp) | ||
2798 | { | ||
2799 | u32 val; | ||
2800 | |||
2801 | /* Make sure the interrupt is not active. */ | ||
2802 | REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT); | ||
2803 | |||
2804 | val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP | | ||
2805 | BNX2_DMA_CONFIG_DATA_WORD_SWAP | | ||
2806 | #ifdef __BIG_ENDIAN | ||
2807 | BNX2_DMA_CONFIG_CNTL_BYTE_SWAP | | ||
2808 | #endif | ||
2809 | BNX2_DMA_CONFIG_CNTL_WORD_SWAP | | ||
2810 | DMA_READ_CHANS << 12 | | ||
2811 | DMA_WRITE_CHANS << 16; | ||
2812 | |||
2813 | val |= (0x2 << 20) | (1 << 11); | ||
2814 | |||
2815 | if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz = 133)) | ||
2816 | val |= (1 << 23); | ||
2817 | |||
2818 | if ((CHIP_NUM(bp) == CHIP_NUM_5706) && | ||
2819 | (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG)) | ||
2820 | val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA; | ||
2821 | |||
2822 | REG_WR(bp, BNX2_DMA_CONFIG, val); | ||
2823 | |||
2824 | if (CHIP_ID(bp) == CHIP_ID_5706_A0) { | ||
2825 | val = REG_RD(bp, BNX2_TDMA_CONFIG); | ||
2826 | val |= BNX2_TDMA_CONFIG_ONE_DMA; | ||
2827 | REG_WR(bp, BNX2_TDMA_CONFIG, val); | ||
2828 | } | ||
2829 | |||
2830 | if (bp->flags & PCIX_FLAG) { | ||
2831 | u16 val16; | ||
2832 | |||
2833 | pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD, | ||
2834 | &val16); | ||
2835 | pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD, | ||
2836 | val16 & ~PCI_X_CMD_ERO); | ||
2837 | } | ||
2838 | |||
2839 | REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, | ||
2840 | BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE | | ||
2841 | BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE | | ||
2842 | BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE); | ||
2843 | |||
2844 | /* Initialize context mapping and zero out the quick contexts. The | ||
2845 | * context block must have already been enabled. */ | ||
2846 | bnx2_init_context(bp); | ||
2847 | |||
2848 | bnx2_init_cpus(bp); | ||
2849 | bnx2_init_nvram(bp); | ||
2850 | |||
2851 | bnx2_set_mac_addr(bp); | ||
2852 | |||
2853 | val = REG_RD(bp, BNX2_MQ_CONFIG); | ||
2854 | val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE; | ||
2855 | val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256; | ||
2856 | REG_WR(bp, BNX2_MQ_CONFIG, val); | ||
2857 | |||
2858 | val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE); | ||
2859 | REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val); | ||
2860 | REG_WR(bp, BNX2_MQ_KNL_WIND_END, val); | ||
2861 | |||
2862 | val = (BCM_PAGE_BITS - 8) << 24; | ||
2863 | REG_WR(bp, BNX2_RV2P_CONFIG, val); | ||
2864 | |||
2865 | /* Configure page size. */ | ||
2866 | val = REG_RD(bp, BNX2_TBDR_CONFIG); | ||
2867 | val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE; | ||
2868 | val |= (BCM_PAGE_BITS - 8) << 24 | 0x40; | ||
2869 | REG_WR(bp, BNX2_TBDR_CONFIG, val); | ||
2870 | |||
2871 | val = bp->mac_addr[0] + | ||
2872 | (bp->mac_addr[1] << 8) + | ||
2873 | (bp->mac_addr[2] << 16) + | ||
2874 | bp->mac_addr[3] + | ||
2875 | (bp->mac_addr[4] << 8) + | ||
2876 | (bp->mac_addr[5] << 16); | ||
2877 | REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val); | ||
2878 | |||
2879 | /* Program the MTU. Also include 4 bytes for CRC32. */ | ||
2880 | val = bp->dev->mtu + ETH_HLEN + 4; | ||
2881 | if (val > (MAX_ETHERNET_PACKET_SIZE + 4)) | ||
2882 | val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA; | ||
2883 | REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val); | ||
2884 | |||
2885 | bp->last_status_idx = 0; | ||
2886 | bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE; | ||
2887 | |||
2888 | /* Set up how to generate a link change interrupt. */ | ||
2889 | REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); | ||
2890 | |||
2891 | REG_WR(bp, BNX2_HC_STATUS_ADDR_L, | ||
2892 | (u64) bp->status_blk_mapping & 0xffffffff); | ||
2893 | REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32); | ||
2894 | |||
2895 | REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L, | ||
2896 | (u64) bp->stats_blk_mapping & 0xffffffff); | ||
2897 | REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H, | ||
2898 | (u64) bp->stats_blk_mapping >> 32); | ||
2899 | |||
2900 | REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP, | ||
2901 | (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip); | ||
2902 | |||
2903 | REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP, | ||
2904 | (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip); | ||
2905 | |||
2906 | REG_WR(bp, BNX2_HC_COMP_PROD_TRIP, | ||
2907 | (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip); | ||
2908 | |||
2909 | REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks); | ||
2910 | |||
2911 | REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks); | ||
2912 | |||
2913 | REG_WR(bp, BNX2_HC_COM_TICKS, | ||
2914 | (bp->com_ticks_int << 16) | bp->com_ticks); | ||
2915 | |||
2916 | REG_WR(bp, BNX2_HC_CMD_TICKS, | ||
2917 | (bp->cmd_ticks_int << 16) | bp->cmd_ticks); | ||
2918 | |||
2919 | REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00); | ||
2920 | REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */ | ||
2921 | |||
2922 | if (CHIP_ID(bp) == CHIP_ID_5706_A1) | ||
2923 | REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS); | ||
2924 | else { | ||
2925 | REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE | | ||
2926 | BNX2_HC_CONFIG_TX_TMR_MODE | | ||
2927 | BNX2_HC_CONFIG_COLLECT_STATS); | ||
2928 | } | ||
2929 | |||
2930 | /* Clear internal stats counters. */ | ||
2931 | REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW); | ||
2932 | |||
2933 | REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE); | ||
2934 | |||
2935 | /* Initialize the receive filter. */ | ||
2936 | bnx2_set_rx_mode(bp->dev); | ||
2937 | |||
2938 | bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET); | ||
2939 | |||
2940 | REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff); | ||
2941 | REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS); | ||
2942 | |||
2943 | udelay(20); | ||
2944 | |||
2945 | return 0; | ||
2946 | } | ||
2947 | |||
2948 | |||
2949 | static void | ||
2950 | bnx2_init_tx_ring(struct bnx2 *bp) | ||
2951 | { | ||
2952 | struct tx_bd *txbd; | ||
2953 | u32 val; | ||
2954 | |||
2955 | txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT]; | ||
2956 | |||
2957 | txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32; | ||
2958 | txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff; | ||
2959 | |||
2960 | bp->tx_prod = 0; | ||
2961 | bp->tx_cons = 0; | ||
2962 | bp->tx_prod_bseq = 0; | ||
2963 | atomic_set(&bp->tx_avail_bd, bp->tx_ring_size); | ||
2964 | |||
2965 | val = BNX2_L2CTX_TYPE_TYPE_L2; | ||
2966 | val |= BNX2_L2CTX_TYPE_SIZE_L2; | ||
2967 | CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val); | ||
2968 | |||
2969 | val = BNX2_L2CTX_CMD_TYPE_TYPE_L2; | ||
2970 | val |= 8 << 16; | ||
2971 | CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val); | ||
2972 | |||
2973 | val = (u64) bp->tx_desc_mapping >> 32; | ||
2974 | CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val); | ||
2975 | |||
2976 | val = (u64) bp->tx_desc_mapping & 0xffffffff; | ||
2977 | CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val); | ||
2978 | } | ||
2979 | |||
2980 | static void | ||
2981 | bnx2_init_rx_ring(struct bnx2 *bp) | ||
2982 | { | ||
2983 | struct rx_bd *rxbd; | ||
2984 | int i; | ||
2985 | u16 prod, ring_prod; | ||
2986 | u32 val; | ||
2987 | |||
2988 | /* 8 for CRC and VLAN */ | ||
2989 | bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8; | ||
2990 | /* 8 for alignment */ | ||
2991 | bp->rx_buf_size = bp->rx_buf_use_size + 8; | ||
2992 | |||
2993 | ring_prod = prod = bp->rx_prod = 0; | ||
2994 | bp->rx_cons = 0; | ||
2995 | bp->rx_prod_bseq = 0; | ||
2996 | |||
2997 | rxbd = &bp->rx_desc_ring[0]; | ||
2998 | for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) { | ||
2999 | rxbd->rx_bd_len = bp->rx_buf_use_size; | ||
3000 | rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END; | ||
3001 | } | ||
3002 | |||
3003 | rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32; | ||
3004 | rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff; | ||
3005 | |||
3006 | val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE; | ||
3007 | val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2; | ||
3008 | val |= 0x02 << 8; | ||
3009 | CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val); | ||
3010 | |||
3011 | val = (u64) bp->rx_desc_mapping >> 32; | ||
3012 | CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val); | ||
3013 | |||
3014 | val = (u64) bp->rx_desc_mapping & 0xffffffff; | ||
3015 | CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val); | ||
3016 | |||
3017 | for ( ;ring_prod < bp->rx_ring_size; ) { | ||
3018 | if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) { | ||
3019 | break; | ||
3020 | } | ||
3021 | prod = NEXT_RX_BD(prod); | ||
3022 | ring_prod = RX_RING_IDX(prod); | ||
3023 | } | ||
3024 | bp->rx_prod = prod; | ||
3025 | |||
3026 | REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod); | ||
3027 | |||
3028 | REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq); | ||
3029 | } | ||
3030 | |||
3031 | static void | ||
3032 | bnx2_free_tx_skbs(struct bnx2 *bp) | ||
3033 | { | ||
3034 | int i; | ||
3035 | |||
3036 | if (bp->tx_buf_ring == NULL) | ||
3037 | return; | ||
3038 | |||
3039 | for (i = 0; i < TX_DESC_CNT; ) { | ||
3040 | struct sw_bd *tx_buf = &bp->tx_buf_ring[i]; | ||
3041 | struct sk_buff *skb = tx_buf->skb; | ||
3042 | int j, last; | ||
3043 | |||
3044 | if (skb == NULL) { | ||
3045 | i++; | ||
3046 | continue; | ||
3047 | } | ||
3048 | |||
3049 | pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping), | ||
3050 | skb_headlen(skb), PCI_DMA_TODEVICE); | ||
3051 | |||
3052 | tx_buf->skb = NULL; | ||
3053 | |||
3054 | last = skb_shinfo(skb)->nr_frags; | ||
3055 | for (j = 0; j < last; j++) { | ||
3056 | tx_buf = &bp->tx_buf_ring[i + j + 1]; | ||
3057 | pci_unmap_page(bp->pdev, | ||
3058 | pci_unmap_addr(tx_buf, mapping), | ||
3059 | skb_shinfo(skb)->frags[j].size, | ||
3060 | PCI_DMA_TODEVICE); | ||
3061 | } | ||
3062 | dev_kfree_skb_any(skb); | ||
3063 | i += j + 1; | ||
3064 | } | ||
3065 | |||
3066 | } | ||
3067 | |||
3068 | static void | ||
3069 | bnx2_free_rx_skbs(struct bnx2 *bp) | ||
3070 | { | ||
3071 | int i; | ||
3072 | |||
3073 | if (bp->rx_buf_ring == NULL) | ||
3074 | return; | ||
3075 | |||
3076 | for (i = 0; i < RX_DESC_CNT; i++) { | ||
3077 | struct sw_bd *rx_buf = &bp->rx_buf_ring[i]; | ||
3078 | struct sk_buff *skb = rx_buf->skb; | ||
3079 | |||
3080 | if (skb == 0) | ||
3081 | continue; | ||
3082 | |||
3083 | pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping), | ||
3084 | bp->rx_buf_use_size, PCI_DMA_FROMDEVICE); | ||
3085 | |||
3086 | rx_buf->skb = NULL; | ||
3087 | |||
3088 | dev_kfree_skb_any(skb); | ||
3089 | } | ||
3090 | } | ||
3091 | |||
3092 | static void | ||
3093 | bnx2_free_skbs(struct bnx2 *bp) | ||
3094 | { | ||
3095 | bnx2_free_tx_skbs(bp); | ||
3096 | bnx2_free_rx_skbs(bp); | ||
3097 | } | ||
3098 | |||
3099 | static int | ||
3100 | bnx2_reset_nic(struct bnx2 *bp, u32 reset_code) | ||
3101 | { | ||
3102 | int rc; | ||
3103 | |||
3104 | rc = bnx2_reset_chip(bp, reset_code); | ||
3105 | bnx2_free_skbs(bp); | ||
3106 | if (rc) | ||
3107 | return rc; | ||
3108 | |||
3109 | bnx2_init_chip(bp); | ||
3110 | bnx2_init_tx_ring(bp); | ||
3111 | bnx2_init_rx_ring(bp); | ||
3112 | return 0; | ||
3113 | } | ||
3114 | |||
3115 | static int | ||
3116 | bnx2_init_nic(struct bnx2 *bp) | ||
3117 | { | ||
3118 | int rc; | ||
3119 | |||
3120 | if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0) | ||
3121 | return rc; | ||
3122 | |||
3123 | bnx2_init_phy(bp); | ||
3124 | bnx2_set_link(bp); | ||
3125 | return 0; | ||
3126 | } | ||
3127 | |||
3128 | static int | ||
3129 | bnx2_test_registers(struct bnx2 *bp) | ||
3130 | { | ||
3131 | int ret; | ||
3132 | int i; | ||
3133 | static struct { | ||
3134 | u16 offset; | ||
3135 | u16 flags; | ||
3136 | u32 rw_mask; | ||
3137 | u32 ro_mask; | ||
3138 | } reg_tbl[] = { | ||
3139 | { 0x006c, 0, 0x00000000, 0x0000003f }, | ||
3140 | { 0x0090, 0, 0xffffffff, 0x00000000 }, | ||
3141 | { 0x0094, 0, 0x00000000, 0x00000000 }, | ||
3142 | |||
3143 | { 0x0404, 0, 0x00003f00, 0x00000000 }, | ||
3144 | { 0x0418, 0, 0x00000000, 0xffffffff }, | ||
3145 | { 0x041c, 0, 0x00000000, 0xffffffff }, | ||
3146 | { 0x0420, 0, 0x00000000, 0x80ffffff }, | ||
3147 | { 0x0424, 0, 0x00000000, 0x00000000 }, | ||
3148 | { 0x0428, 0, 0x00000000, 0x00000001 }, | ||
3149 | { 0x0450, 0, 0x00000000, 0x0000ffff }, | ||
3150 | { 0x0454, 0, 0x00000000, 0xffffffff }, | ||
3151 | { 0x0458, 0, 0x00000000, 0xffffffff }, | ||
3152 | |||
3153 | { 0x0808, 0, 0x00000000, 0xffffffff }, | ||
3154 | { 0x0854, 0, 0x00000000, 0xffffffff }, | ||
3155 | { 0x0868, 0, 0x00000000, 0x77777777 }, | ||
3156 | { 0x086c, 0, 0x00000000, 0x77777777 }, | ||
3157 | { 0x0870, 0, 0x00000000, 0x77777777 }, | ||
3158 | { 0x0874, 0, 0x00000000, 0x77777777 }, | ||
3159 | |||
3160 | { 0x0c00, 0, 0x00000000, 0x00000001 }, | ||
3161 | { 0x0c04, 0, 0x00000000, 0x03ff0001 }, | ||
3162 | { 0x0c08, 0, 0x0f0ff073, 0x00000000 }, | ||
3163 | { 0x0c0c, 0, 0x00ffffff, 0x00000000 }, | ||
3164 | { 0x0c30, 0, 0x00000000, 0xffffffff }, | ||
3165 | { 0x0c34, 0, 0x00000000, 0xffffffff }, | ||
3166 | { 0x0c38, 0, 0x00000000, 0xffffffff }, | ||
3167 | { 0x0c3c, 0, 0x00000000, 0xffffffff }, | ||
3168 | { 0x0c40, 0, 0x00000000, 0xffffffff }, | ||
3169 | { 0x0c44, 0, 0x00000000, 0xffffffff }, | ||
3170 | { 0x0c48, 0, 0x00000000, 0x0007ffff }, | ||
3171 | { 0x0c4c, 0, 0x00000000, 0xffffffff }, | ||
3172 | { 0x0c50, 0, 0x00000000, 0xffffffff }, | ||
3173 | { 0x0c54, 0, 0x00000000, 0xffffffff }, | ||
3174 | { 0x0c58, 0, 0x00000000, 0xffffffff }, | ||
3175 | { 0x0c5c, 0, 0x00000000, 0xffffffff }, | ||
3176 | { 0x0c60, 0, 0x00000000, 0xffffffff }, | ||
3177 | { 0x0c64, 0, 0x00000000, 0xffffffff }, | ||
3178 | { 0x0c68, 0, 0x00000000, 0xffffffff }, | ||
3179 | { 0x0c6c, 0, 0x00000000, 0xffffffff }, | ||
3180 | { 0x0c70, 0, 0x00000000, 0xffffffff }, | ||
3181 | { 0x0c74, 0, 0x00000000, 0xffffffff }, | ||
3182 | { 0x0c78, 0, 0x00000000, 0xffffffff }, | ||
3183 | { 0x0c7c, 0, 0x00000000, 0xffffffff }, | ||
3184 | { 0x0c80, 0, 0x00000000, 0xffffffff }, | ||
3185 | { 0x0c84, 0, 0x00000000, 0xffffffff }, | ||
3186 | { 0x0c88, 0, 0x00000000, 0xffffffff }, | ||
3187 | { 0x0c8c, 0, 0x00000000, 0xffffffff }, | ||
3188 | { 0x0c90, 0, 0x00000000, 0xffffffff }, | ||
3189 | { 0x0c94, 0, 0x00000000, 0xffffffff }, | ||
3190 | { 0x0c98, 0, 0x00000000, 0xffffffff }, | ||
3191 | { 0x0c9c, 0, 0x00000000, 0xffffffff }, | ||
3192 | { 0x0ca0, 0, 0x00000000, 0xffffffff }, | ||
3193 | { 0x0ca4, 0, 0x00000000, 0xffffffff }, | ||
3194 | { 0x0ca8, 0, 0x00000000, 0x0007ffff }, | ||
3195 | { 0x0cac, 0, 0x00000000, 0xffffffff }, | ||
3196 | { 0x0cb0, 0, 0x00000000, 0xffffffff }, | ||
3197 | { 0x0cb4, 0, 0x00000000, 0xffffffff }, | ||
3198 | { 0x0cb8, 0, 0x00000000, 0xffffffff }, | ||
3199 | { 0x0cbc, 0, 0x00000000, 0xffffffff }, | ||
3200 | { 0x0cc0, 0, 0x00000000, 0xffffffff }, | ||
3201 | { 0x0cc4, 0, 0x00000000, 0xffffffff }, | ||
3202 | { 0x0cc8, 0, 0x00000000, 0xffffffff }, | ||
3203 | { 0x0ccc, 0, 0x00000000, 0xffffffff }, | ||
3204 | { 0x0cd0, 0, 0x00000000, 0xffffffff }, | ||
3205 | { 0x0cd4, 0, 0x00000000, 0xffffffff }, | ||
3206 | { 0x0cd8, 0, 0x00000000, 0xffffffff }, | ||
3207 | { 0x0cdc, 0, 0x00000000, 0xffffffff }, | ||
3208 | { 0x0ce0, 0, 0x00000000, 0xffffffff }, | ||
3209 | { 0x0ce4, 0, 0x00000000, 0xffffffff }, | ||
3210 | { 0x0ce8, 0, 0x00000000, 0xffffffff }, | ||
3211 | { 0x0cec, 0, 0x00000000, 0xffffffff }, | ||
3212 | { 0x0cf0, 0, 0x00000000, 0xffffffff }, | ||
3213 | { 0x0cf4, 0, 0x00000000, 0xffffffff }, | ||
3214 | { 0x0cf8, 0, 0x00000000, 0xffffffff }, | ||
3215 | { 0x0cfc, 0, 0x00000000, 0xffffffff }, | ||
3216 | { 0x0d00, 0, 0x00000000, 0xffffffff }, | ||
3217 | { 0x0d04, 0, 0x00000000, 0xffffffff }, | ||
3218 | |||
3219 | { 0x1000, 0, 0x00000000, 0x00000001 }, | ||
3220 | { 0x1004, 0, 0x00000000, 0x000f0001 }, | ||
3221 | { 0x1044, 0, 0x00000000, 0xffc003ff }, | ||
3222 | { 0x1080, 0, 0x00000000, 0x0001ffff }, | ||
3223 | { 0x1084, 0, 0x00000000, 0xffffffff }, | ||
3224 | { 0x1088, 0, 0x00000000, 0xffffffff }, | ||
3225 | { 0x108c, 0, 0x00000000, 0xffffffff }, | ||
3226 | { 0x1090, 0, 0x00000000, 0xffffffff }, | ||
3227 | { 0x1094, 0, 0x00000000, 0xffffffff }, | ||
3228 | { 0x1098, 0, 0x00000000, 0xffffffff }, | ||
3229 | { 0x109c, 0, 0x00000000, 0xffffffff }, | ||
3230 | { 0x10a0, 0, 0x00000000, 0xffffffff }, | ||
3231 | |||
3232 | { 0x1408, 0, 0x01c00800, 0x00000000 }, | ||
3233 | { 0x149c, 0, 0x8000ffff, 0x00000000 }, | ||
3234 | { 0x14a8, 0, 0x00000000, 0x000001ff }, | ||
3235 | { 0x14ac, 0, 0x4fffffff, 0x10000000 }, | ||
3236 | { 0x14b0, 0, 0x00000002, 0x00000001 }, | ||
3237 | { 0x14b8, 0, 0x00000000, 0x00000000 }, | ||
3238 | { 0x14c0, 0, 0x00000000, 0x00000009 }, | ||
3239 | { 0x14c4, 0, 0x00003fff, 0x00000000 }, | ||
3240 | { 0x14cc, 0, 0x00000000, 0x00000001 }, | ||
3241 | { 0x14d0, 0, 0xffffffff, 0x00000000 }, | ||
3242 | { 0x1500, 0, 0x00000000, 0xffffffff }, | ||
3243 | { 0x1504, 0, 0x00000000, 0xffffffff }, | ||
3244 | { 0x1508, 0, 0x00000000, 0xffffffff }, | ||
3245 | { 0x150c, 0, 0x00000000, 0xffffffff }, | ||
3246 | { 0x1510, 0, 0x00000000, 0xffffffff }, | ||
3247 | { 0x1514, 0, 0x00000000, 0xffffffff }, | ||
3248 | { 0x1518, 0, 0x00000000, 0xffffffff }, | ||
3249 | { 0x151c, 0, 0x00000000, 0xffffffff }, | ||
3250 | { 0x1520, 0, 0x00000000, 0xffffffff }, | ||
3251 | { 0x1524, 0, 0x00000000, 0xffffffff }, | ||
3252 | { 0x1528, 0, 0x00000000, 0xffffffff }, | ||
3253 | { 0x152c, 0, 0x00000000, 0xffffffff }, | ||
3254 | { 0x1530, 0, 0x00000000, 0xffffffff }, | ||
3255 | { 0x1534, 0, 0x00000000, 0xffffffff }, | ||
3256 | { 0x1538, 0, 0x00000000, 0xffffffff }, | ||
3257 | { 0x153c, 0, 0x00000000, 0xffffffff }, | ||
3258 | { 0x1540, 0, 0x00000000, 0xffffffff }, | ||
3259 | { 0x1544, 0, 0x00000000, 0xffffffff }, | ||
3260 | { 0x1548, 0, 0x00000000, 0xffffffff }, | ||
3261 | { 0x154c, 0, 0x00000000, 0xffffffff }, | ||
3262 | { 0x1550, 0, 0x00000000, 0xffffffff }, | ||
3263 | { 0x1554, 0, 0x00000000, 0xffffffff }, | ||
3264 | { 0x1558, 0, 0x00000000, 0xffffffff }, | ||
3265 | { 0x1600, 0, 0x00000000, 0xffffffff }, | ||
3266 | { 0x1604, 0, 0x00000000, 0xffffffff }, | ||
3267 | { 0x1608, 0, 0x00000000, 0xffffffff }, | ||
3268 | { 0x160c, 0, 0x00000000, 0xffffffff }, | ||
3269 | { 0x1610, 0, 0x00000000, 0xffffffff }, | ||
3270 | { 0x1614, 0, 0x00000000, 0xffffffff }, | ||
3271 | { 0x1618, 0, 0x00000000, 0xffffffff }, | ||
3272 | { 0x161c, 0, 0x00000000, 0xffffffff }, | ||
3273 | { 0x1620, 0, 0x00000000, 0xffffffff }, | ||
3274 | { 0x1624, 0, 0x00000000, 0xffffffff }, | ||
3275 | { 0x1628, 0, 0x00000000, 0xffffffff }, | ||
3276 | { 0x162c, 0, 0x00000000, 0xffffffff }, | ||
3277 | { 0x1630, 0, 0x00000000, 0xffffffff }, | ||
3278 | { 0x1634, 0, 0x00000000, 0xffffffff }, | ||
3279 | { 0x1638, 0, 0x00000000, 0xffffffff }, | ||
3280 | { 0x163c, 0, 0x00000000, 0xffffffff }, | ||
3281 | { 0x1640, 0, 0x00000000, 0xffffffff }, | ||
3282 | { 0x1644, 0, 0x00000000, 0xffffffff }, | ||
3283 | { 0x1648, 0, 0x00000000, 0xffffffff }, | ||
3284 | { 0x164c, 0, 0x00000000, 0xffffffff }, | ||
3285 | { 0x1650, 0, 0x00000000, 0xffffffff }, | ||
3286 | { 0x1654, 0, 0x00000000, 0xffffffff }, | ||
3287 | |||
3288 | { 0x1800, 0, 0x00000000, 0x00000001 }, | ||
3289 | { 0x1804, 0, 0x00000000, 0x00000003 }, | ||
3290 | { 0x1840, 0, 0x00000000, 0xffffffff }, | ||
3291 | { 0x1844, 0, 0x00000000, 0xffffffff }, | ||
3292 | { 0x1848, 0, 0x00000000, 0xffffffff }, | ||
3293 | { 0x184c, 0, 0x00000000, 0xffffffff }, | ||
3294 | { 0x1850, 0, 0x00000000, 0xffffffff }, | ||
3295 | { 0x1900, 0, 0x7ffbffff, 0x00000000 }, | ||
3296 | { 0x1904, 0, 0xffffffff, 0x00000000 }, | ||
3297 | { 0x190c, 0, 0xffffffff, 0x00000000 }, | ||
3298 | { 0x1914, 0, 0xffffffff, 0x00000000 }, | ||
3299 | { 0x191c, 0, 0xffffffff, 0x00000000 }, | ||
3300 | { 0x1924, 0, 0xffffffff, 0x00000000 }, | ||
3301 | { 0x192c, 0, 0xffffffff, 0x00000000 }, | ||
3302 | { 0x1934, 0, 0xffffffff, 0x00000000 }, | ||
3303 | { 0x193c, 0, 0xffffffff, 0x00000000 }, | ||
3304 | { 0x1944, 0, 0xffffffff, 0x00000000 }, | ||
3305 | { 0x194c, 0, 0xffffffff, 0x00000000 }, | ||
3306 | { 0x1954, 0, 0xffffffff, 0x00000000 }, | ||
3307 | { 0x195c, 0, 0xffffffff, 0x00000000 }, | ||
3308 | { 0x1964, 0, 0xffffffff, 0x00000000 }, | ||
3309 | { 0x196c, 0, 0xffffffff, 0x00000000 }, | ||
3310 | { 0x1974, 0, 0xffffffff, 0x00000000 }, | ||
3311 | { 0x197c, 0, 0xffffffff, 0x00000000 }, | ||
3312 | { 0x1980, 0, 0x0700ffff, 0x00000000 }, | ||
3313 | |||
3314 | { 0x1c00, 0, 0x00000000, 0x00000001 }, | ||
3315 | { 0x1c04, 0, 0x00000000, 0x00000003 }, | ||
3316 | { 0x1c08, 0, 0x0000000f, 0x00000000 }, | ||
3317 | { 0x1c40, 0, 0x00000000, 0xffffffff }, | ||
3318 | { 0x1c44, 0, 0x00000000, 0xffffffff }, | ||
3319 | { 0x1c48, 0, 0x00000000, 0xffffffff }, | ||
3320 | { 0x1c4c, 0, 0x00000000, 0xffffffff }, | ||
3321 | { 0x1c50, 0, 0x00000000, 0xffffffff }, | ||
3322 | { 0x1d00, 0, 0x7ffbffff, 0x00000000 }, | ||
3323 | { 0x1d04, 0, 0xffffffff, 0x00000000 }, | ||
3324 | { 0x1d0c, 0, 0xffffffff, 0x00000000 }, | ||
3325 | { 0x1d14, 0, 0xffffffff, 0x00000000 }, | ||
3326 | { 0x1d1c, 0, 0xffffffff, 0x00000000 }, | ||
3327 | { 0x1d24, 0, 0xffffffff, 0x00000000 }, | ||
3328 | { 0x1d2c, 0, 0xffffffff, 0x00000000 }, | ||
3329 | { 0x1d34, 0, 0xffffffff, 0x00000000 }, | ||
3330 | { 0x1d3c, 0, 0xffffffff, 0x00000000 }, | ||
3331 | { 0x1d44, 0, 0xffffffff, 0x00000000 }, | ||
3332 | { 0x1d4c, 0, 0xffffffff, 0x00000000 }, | ||
3333 | { 0x1d54, 0, 0xffffffff, 0x00000000 }, | ||
3334 | { 0x1d5c, 0, 0xffffffff, 0x00000000 }, | ||
3335 | { 0x1d64, 0, 0xffffffff, 0x00000000 }, | ||
3336 | { 0x1d6c, 0, 0xffffffff, 0x00000000 }, | ||
3337 | { 0x1d74, 0, 0xffffffff, 0x00000000 }, | ||
3338 | { 0x1d7c, 0, 0xffffffff, 0x00000000 }, | ||
3339 | { 0x1d80, 0, 0x0700ffff, 0x00000000 }, | ||
3340 | |||
3341 | { 0x2004, 0, 0x00000000, 0x0337000f }, | ||
3342 | { 0x2008, 0, 0xffffffff, 0x00000000 }, | ||
3343 | { 0x200c, 0, 0xffffffff, 0x00000000 }, | ||
3344 | { 0x2010, 0, 0xffffffff, 0x00000000 }, | ||
3345 | { 0x2014, 0, 0x801fff80, 0x00000000 }, | ||
3346 | { 0x2018, 0, 0x000003ff, 0x00000000 }, | ||
3347 | |||
3348 | { 0x2800, 0, 0x00000000, 0x00000001 }, | ||
3349 | { 0x2804, 0, 0x00000000, 0x00003f01 }, | ||
3350 | { 0x2808, 0, 0x0f3f3f03, 0x00000000 }, | ||
3351 | { 0x2810, 0, 0xffff0000, 0x00000000 }, | ||
3352 | { 0x2814, 0, 0xffff0000, 0x00000000 }, | ||
3353 | { 0x2818, 0, 0xffff0000, 0x00000000 }, | ||
3354 | { 0x281c, 0, 0xffff0000, 0x00000000 }, | ||
3355 | { 0x2834, 0, 0xffffffff, 0x00000000 }, | ||
3356 | { 0x2840, 0, 0x00000000, 0xffffffff }, | ||
3357 | { 0x2844, 0, 0x00000000, 0xffffffff }, | ||
3358 | { 0x2848, 0, 0xffffffff, 0x00000000 }, | ||
3359 | { 0x284c, 0, 0xf800f800, 0x07ff07ff }, | ||
3360 | |||
3361 | { 0x2c00, 0, 0x00000000, 0x00000011 }, | ||
3362 | { 0x2c04, 0, 0x00000000, 0x00030007 }, | ||
3363 | |||
3364 | { 0x3000, 0, 0x00000000, 0x00000001 }, | ||
3365 | { 0x3004, 0, 0x00000000, 0x007007ff }, | ||
3366 | { 0x3008, 0, 0x00000003, 0x00000000 }, | ||
3367 | { 0x300c, 0, 0xffffffff, 0x00000000 }, | ||
3368 | { 0x3010, 0, 0xffffffff, 0x00000000 }, | ||
3369 | { 0x3014, 0, 0xffffffff, 0x00000000 }, | ||
3370 | { 0x3034, 0, 0xffffffff, 0x00000000 }, | ||
3371 | { 0x3038, 0, 0xffffffff, 0x00000000 }, | ||
3372 | { 0x3050, 0, 0x00000001, 0x00000000 }, | ||
3373 | |||
3374 | { 0x3c00, 0, 0x00000000, 0x00000001 }, | ||
3375 | { 0x3c04, 0, 0x00000000, 0x00070000 }, | ||
3376 | { 0x3c08, 0, 0x00007f71, 0x07f00000 }, | ||
3377 | { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 }, | ||
3378 | { 0x3c10, 0, 0xffffffff, 0x00000000 }, | ||
3379 | { 0x3c14, 0, 0x00000000, 0xffffffff }, | ||
3380 | { 0x3c18, 0, 0x00000000, 0xffffffff }, | ||
3381 | { 0x3c1c, 0, 0xfffff000, 0x00000000 }, | ||
3382 | { 0x3c20, 0, 0xffffff00, 0x00000000 }, | ||
3383 | { 0x3c24, 0, 0xffffffff, 0x00000000 }, | ||
3384 | { 0x3c28, 0, 0xffffffff, 0x00000000 }, | ||
3385 | { 0x3c2c, 0, 0xffffffff, 0x00000000 }, | ||
3386 | { 0x3c30, 0, 0xffffffff, 0x00000000 }, | ||
3387 | { 0x3c34, 0, 0xffffffff, 0x00000000 }, | ||
3388 | { 0x3c38, 0, 0xffffffff, 0x00000000 }, | ||
3389 | { 0x3c3c, 0, 0xffffffff, 0x00000000 }, | ||
3390 | { 0x3c40, 0, 0xffffffff, 0x00000000 }, | ||
3391 | { 0x3c44, 0, 0xffffffff, 0x00000000 }, | ||
3392 | { 0x3c48, 0, 0xffffffff, 0x00000000 }, | ||
3393 | { 0x3c4c, 0, 0xffffffff, 0x00000000 }, | ||
3394 | { 0x3c50, 0, 0xffffffff, 0x00000000 }, | ||
3395 | { 0x3c54, 0, 0xffffffff, 0x00000000 }, | ||
3396 | { 0x3c58, 0, 0xffffffff, 0x00000000 }, | ||
3397 | { 0x3c5c, 0, 0xffffffff, 0x00000000 }, | ||
3398 | { 0x3c60, 0, 0xffffffff, 0x00000000 }, | ||
3399 | { 0x3c64, 0, 0xffffffff, 0x00000000 }, | ||
3400 | { 0x3c68, 0, 0xffffffff, 0x00000000 }, | ||
3401 | { 0x3c6c, 0, 0xffffffff, 0x00000000 }, | ||
3402 | { 0x3c70, 0, 0xffffffff, 0x00000000 }, | ||
3403 | { 0x3c74, 0, 0x0000003f, 0x00000000 }, | ||
3404 | { 0x3c78, 0, 0x00000000, 0x00000000 }, | ||
3405 | { 0x3c7c, 0, 0x00000000, 0x00000000 }, | ||
3406 | { 0x3c80, 0, 0x3fffffff, 0x00000000 }, | ||
3407 | { 0x3c84, 0, 0x0000003f, 0x00000000 }, | ||
3408 | { 0x3c88, 0, 0x00000000, 0xffffffff }, | ||
3409 | { 0x3c8c, 0, 0x00000000, 0xffffffff }, | ||
3410 | |||
3411 | { 0x4000, 0, 0x00000000, 0x00000001 }, | ||
3412 | { 0x4004, 0, 0x00000000, 0x00030000 }, | ||
3413 | { 0x4008, 0, 0x00000ff0, 0x00000000 }, | ||
3414 | { 0x400c, 0, 0xffffffff, 0x00000000 }, | ||
3415 | { 0x4088, 0, 0x00000000, 0x00070303 }, | ||
3416 | |||
3417 | { 0x4400, 0, 0x00000000, 0x00000001 }, | ||
3418 | { 0x4404, 0, 0x00000000, 0x00003f01 }, | ||
3419 | { 0x4408, 0, 0x7fff00ff, 0x00000000 }, | ||
3420 | { 0x440c, 0, 0xffffffff, 0x00000000 }, | ||
3421 | { 0x4410, 0, 0xffff, 0x0000 }, | ||
3422 | { 0x4414, 0, 0xffff, 0x0000 }, | ||
3423 | { 0x4418, 0, 0xffff, 0x0000 }, | ||
3424 | { 0x441c, 0, 0xffff, 0x0000 }, | ||
3425 | { 0x4428, 0, 0xffffffff, 0x00000000 }, | ||
3426 | { 0x442c, 0, 0xffffffff, 0x00000000 }, | ||
3427 | { 0x4430, 0, 0xffffffff, 0x00000000 }, | ||
3428 | { 0x4434, 0, 0xffffffff, 0x00000000 }, | ||
3429 | { 0x4438, 0, 0xffffffff, 0x00000000 }, | ||
3430 | { 0x443c, 0, 0xffffffff, 0x00000000 }, | ||
3431 | { 0x4440, 0, 0xffffffff, 0x00000000 }, | ||
3432 | { 0x4444, 0, 0xffffffff, 0x00000000 }, | ||
3433 | |||
3434 | { 0x4c00, 0, 0x00000000, 0x00000001 }, | ||
3435 | { 0x4c04, 0, 0x00000000, 0x0000003f }, | ||
3436 | { 0x4c08, 0, 0xffffffff, 0x00000000 }, | ||
3437 | { 0x4c0c, 0, 0x0007fc00, 0x00000000 }, | ||
3438 | { 0x4c10, 0, 0x80003fe0, 0x00000000 }, | ||
3439 | { 0x4c14, 0, 0xffffffff, 0x00000000 }, | ||
3440 | { 0x4c44, 0, 0x00000000, 0x9fff9fff }, | ||
3441 | { 0x4c48, 0, 0x00000000, 0xb3009fff }, | ||
3442 | { 0x4c4c, 0, 0x00000000, 0x77f33b30 }, | ||
3443 | { 0x4c50, 0, 0x00000000, 0xffffffff }, | ||
3444 | |||
3445 | { 0x5004, 0, 0x00000000, 0x0000007f }, | ||
3446 | { 0x5008, 0, 0x0f0007ff, 0x00000000 }, | ||
3447 | { 0x500c, 0, 0xf800f800, 0x07ff07ff }, | ||
3448 | |||
3449 | { 0x5400, 0, 0x00000008, 0x00000001 }, | ||
3450 | { 0x5404, 0, 0x00000000, 0x0000003f }, | ||
3451 | { 0x5408, 0, 0x0000001f, 0x00000000 }, | ||
3452 | { 0x540c, 0, 0xffffffff, 0x00000000 }, | ||
3453 | { 0x5410, 0, 0xffffffff, 0x00000000 }, | ||
3454 | { 0x5414, 0, 0x0000ffff, 0x00000000 }, | ||
3455 | { 0x5418, 0, 0x0000ffff, 0x00000000 }, | ||
3456 | { 0x541c, 0, 0x0000ffff, 0x00000000 }, | ||
3457 | { 0x5420, 0, 0x0000ffff, 0x00000000 }, | ||
3458 | { 0x5428, 0, 0x000000ff, 0x00000000 }, | ||
3459 | { 0x542c, 0, 0xff00ffff, 0x00000000 }, | ||
3460 | { 0x5430, 0, 0x001fff80, 0x00000000 }, | ||
3461 | { 0x5438, 0, 0xffffffff, 0x00000000 }, | ||
3462 | { 0x543c, 0, 0xffffffff, 0x00000000 }, | ||
3463 | { 0x5440, 0, 0xf800f800, 0x07ff07ff }, | ||
3464 | |||
3465 | { 0x5c00, 0, 0x00000000, 0x00000001 }, | ||
3466 | { 0x5c04, 0, 0x00000000, 0x0003000f }, | ||
3467 | { 0x5c08, 0, 0x00000003, 0x00000000 }, | ||
3468 | { 0x5c0c, 0, 0x0000fff8, 0x00000000 }, | ||
3469 | { 0x5c10, 0, 0x00000000, 0xffffffff }, | ||
3470 | { 0x5c80, 0, 0x00000000, 0x0f7113f1 }, | ||
3471 | { 0x5c84, 0, 0x00000000, 0x0000f333 }, | ||
3472 | { 0x5c88, 0, 0x00000000, 0x00077373 }, | ||
3473 | { 0x5c8c, 0, 0x00000000, 0x0007f737 }, | ||
3474 | |||
3475 | { 0x6808, 0, 0x0000ff7f, 0x00000000 }, | ||
3476 | { 0x680c, 0, 0xffffffff, 0x00000000 }, | ||
3477 | { 0x6810, 0, 0xffffffff, 0x00000000 }, | ||
3478 | { 0x6814, 0, 0xffffffff, 0x00000000 }, | ||
3479 | { 0x6818, 0, 0xffffffff, 0x00000000 }, | ||
3480 | { 0x681c, 0, 0xffffffff, 0x00000000 }, | ||
3481 | { 0x6820, 0, 0x00ff00ff, 0x00000000 }, | ||
3482 | { 0x6824, 0, 0x00ff00ff, 0x00000000 }, | ||
3483 | { 0x6828, 0, 0x00ff00ff, 0x00000000 }, | ||
3484 | { 0x682c, 0, 0x03ff03ff, 0x00000000 }, | ||
3485 | { 0x6830, 0, 0x03ff03ff, 0x00000000 }, | ||
3486 | { 0x6834, 0, 0x03ff03ff, 0x00000000 }, | ||
3487 | { 0x6838, 0, 0x03ff03ff, 0x00000000 }, | ||
3488 | { 0x683c, 0, 0x0000ffff, 0x00000000 }, | ||
3489 | { 0x6840, 0, 0x00000ff0, 0x00000000 }, | ||
3490 | { 0x6844, 0, 0x00ffff00, 0x00000000 }, | ||
3491 | { 0x684c, 0, 0xffffffff, 0x00000000 }, | ||
3492 | { 0x6850, 0, 0x7f7f7f7f, 0x00000000 }, | ||
3493 | { 0x6854, 0, 0x7f7f7f7f, 0x00000000 }, | ||
3494 | { 0x6858, 0, 0x7f7f7f7f, 0x00000000 }, | ||
3495 | { 0x685c, 0, 0x7f7f7f7f, 0x00000000 }, | ||
3496 | { 0x6908, 0, 0x00000000, 0x0001ff0f }, | ||
3497 | { 0x690c, 0, 0x00000000, 0x0ffe00f0 }, | ||
3498 | |||
3499 | { 0xffff, 0, 0x00000000, 0x00000000 }, | ||
3500 | }; | ||
3501 | |||
3502 | ret = 0; | ||
3503 | for (i = 0; reg_tbl[i].offset != 0xffff; i++) { | ||
3504 | u32 offset, rw_mask, ro_mask, save_val, val; | ||
3505 | |||
3506 | offset = (u32) reg_tbl[i].offset; | ||
3507 | rw_mask = reg_tbl[i].rw_mask; | ||
3508 | ro_mask = reg_tbl[i].ro_mask; | ||
3509 | |||
3510 | save_val = readl((u8 *) bp->regview + offset); | ||
3511 | |||
3512 | writel(0, (u8 *) bp->regview + offset); | ||
3513 | |||
3514 | val = readl((u8 *) bp->regview + offset); | ||
3515 | if ((val & rw_mask) != 0) { | ||
3516 | goto reg_test_err; | ||
3517 | } | ||
3518 | |||
3519 | if ((val & ro_mask) != (save_val & ro_mask)) { | ||
3520 | goto reg_test_err; | ||
3521 | } | ||
3522 | |||
3523 | writel(0xffffffff, (u8 *) bp->regview + offset); | ||
3524 | |||
3525 | val = readl((u8 *) bp->regview + offset); | ||
3526 | if ((val & rw_mask) != rw_mask) { | ||
3527 | goto reg_test_err; | ||
3528 | } | ||
3529 | |||
3530 | if ((val & ro_mask) != (save_val & ro_mask)) { | ||
3531 | goto reg_test_err; | ||
3532 | } | ||
3533 | |||
3534 | writel(save_val, (u8 *) bp->regview + offset); | ||
3535 | continue; | ||
3536 | |||
3537 | reg_test_err: | ||
3538 | writel(save_val, (u8 *) bp->regview + offset); | ||
3539 | ret = -ENODEV; | ||
3540 | break; | ||
3541 | } | ||
3542 | return ret; | ||
3543 | } | ||
3544 | |||
3545 | static int | ||
3546 | bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size) | ||
3547 | { | ||
3548 | static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555, | ||
3549 | 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa }; | ||
3550 | int i; | ||
3551 | |||
3552 | for (i = 0; i < sizeof(test_pattern) / 4; i++) { | ||
3553 | u32 offset; | ||
3554 | |||
3555 | for (offset = 0; offset < size; offset += 4) { | ||
3556 | |||
3557 | REG_WR_IND(bp, start + offset, test_pattern[i]); | ||
3558 | |||
3559 | if (REG_RD_IND(bp, start + offset) != | ||
3560 | test_pattern[i]) { | ||
3561 | return -ENODEV; | ||
3562 | } | ||
3563 | } | ||
3564 | } | ||
3565 | return 0; | ||
3566 | } | ||
3567 | |||
3568 | static int | ||
3569 | bnx2_test_memory(struct bnx2 *bp) | ||
3570 | { | ||
3571 | int ret = 0; | ||
3572 | int i; | ||
3573 | static struct { | ||
3574 | u32 offset; | ||
3575 | u32 len; | ||
3576 | } mem_tbl[] = { | ||
3577 | { 0x60000, 0x4000 }, | ||
3578 | { 0xa0000, 0x4000 }, | ||
3579 | { 0xe0000, 0x4000 }, | ||
3580 | { 0x120000, 0x4000 }, | ||
3581 | { 0x1a0000, 0x4000 }, | ||
3582 | { 0x160000, 0x4000 }, | ||
3583 | { 0xffffffff, 0 }, | ||
3584 | }; | ||
3585 | |||
3586 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { | ||
3587 | if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset, | ||
3588 | mem_tbl[i].len)) != 0) { | ||
3589 | return ret; | ||
3590 | } | ||
3591 | } | ||
3592 | |||
3593 | return ret; | ||
3594 | } | ||
3595 | |||
3596 | static int | ||
3597 | bnx2_test_loopback(struct bnx2 *bp) | ||
3598 | { | ||
3599 | unsigned int pkt_size, num_pkts, i; | ||
3600 | struct sk_buff *skb, *rx_skb; | ||
3601 | unsigned char *packet; | ||
3602 | u16 rx_start_idx, rx_idx, send_idx; | ||
3603 | u32 send_bseq, val; | ||
3604 | dma_addr_t map; | ||
3605 | struct tx_bd *txbd; | ||
3606 | struct sw_bd *rx_buf; | ||
3607 | struct l2_fhdr *rx_hdr; | ||
3608 | int ret = -ENODEV; | ||
3609 | |||
3610 | if (!netif_running(bp->dev)) | ||
3611 | return -ENODEV; | ||
3612 | |||
3613 | bp->loopback = MAC_LOOPBACK; | ||
3614 | bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_DIAG); | ||
3615 | bnx2_set_mac_loopback(bp); | ||
3616 | |||
3617 | pkt_size = 1514; | ||
3618 | skb = dev_alloc_skb(pkt_size); | ||
3619 | packet = skb_put(skb, pkt_size); | ||
3620 | memcpy(packet, bp->mac_addr, 6); | ||
3621 | memset(packet + 6, 0x0, 8); | ||
3622 | for (i = 14; i < pkt_size; i++) | ||
3623 | packet[i] = (unsigned char) (i & 0xff); | ||
3624 | |||
3625 | map = pci_map_single(bp->pdev, skb->data, pkt_size, | ||
3626 | PCI_DMA_TODEVICE); | ||
3627 | |||
3628 | val = REG_RD(bp, BNX2_HC_COMMAND); | ||
3629 | REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT); | ||
3630 | REG_RD(bp, BNX2_HC_COMMAND); | ||
3631 | |||
3632 | udelay(5); | ||
3633 | rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0; | ||
3634 | |||
3635 | send_idx = 0; | ||
3636 | send_bseq = 0; | ||
3637 | num_pkts = 0; | ||
3638 | |||
3639 | txbd = &bp->tx_desc_ring[send_idx]; | ||
3640 | |||
3641 | txbd->tx_bd_haddr_hi = (u64) map >> 32; | ||
3642 | txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff; | ||
3643 | txbd->tx_bd_mss_nbytes = pkt_size; | ||
3644 | txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END; | ||
3645 | |||
3646 | num_pkts++; | ||
3647 | send_idx = NEXT_TX_BD(send_idx); | ||
3648 | |||
3649 | send_bseq += pkt_size; | ||
3650 | |||
3651 | REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, send_idx); | ||
3652 | REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, send_bseq); | ||
3653 | |||
3654 | |||
3655 | udelay(100); | ||
3656 | |||
3657 | val = REG_RD(bp, BNX2_HC_COMMAND); | ||
3658 | REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT); | ||
3659 | REG_RD(bp, BNX2_HC_COMMAND); | ||
3660 | |||
3661 | udelay(5); | ||
3662 | |||
3663 | pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE); | ||
3664 | dev_kfree_skb_irq(skb); | ||
3665 | |||
3666 | if (bp->status_blk->status_tx_quick_consumer_index0 != send_idx) { | ||
3667 | goto loopback_test_done; | ||
3668 | } | ||
3669 | |||
3670 | rx_idx = bp->status_blk->status_rx_quick_consumer_index0; | ||
3671 | if (rx_idx != rx_start_idx + num_pkts) { | ||
3672 | goto loopback_test_done; | ||
3673 | } | ||
3674 | |||
3675 | rx_buf = &bp->rx_buf_ring[rx_start_idx]; | ||
3676 | rx_skb = rx_buf->skb; | ||
3677 | |||
3678 | rx_hdr = (struct l2_fhdr *) rx_skb->data; | ||
3679 | skb_reserve(rx_skb, bp->rx_offset); | ||
3680 | |||
3681 | pci_dma_sync_single_for_cpu(bp->pdev, | ||
3682 | pci_unmap_addr(rx_buf, mapping), | ||
3683 | bp->rx_buf_size, PCI_DMA_FROMDEVICE); | ||
3684 | |||
3685 | if (rx_hdr->l2_fhdr_errors & | ||
3686 | (L2_FHDR_ERRORS_BAD_CRC | | ||
3687 | L2_FHDR_ERRORS_PHY_DECODE | | ||
3688 | L2_FHDR_ERRORS_ALIGNMENT | | ||
3689 | L2_FHDR_ERRORS_TOO_SHORT | | ||
3690 | L2_FHDR_ERRORS_GIANT_FRAME)) { | ||
3691 | |||
3692 | goto loopback_test_done; | ||
3693 | } | ||
3694 | |||
3695 | if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) { | ||
3696 | goto loopback_test_done; | ||
3697 | } | ||
3698 | |||
3699 | for (i = 14; i < pkt_size; i++) { | ||
3700 | if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) { | ||
3701 | goto loopback_test_done; | ||
3702 | } | ||
3703 | } | ||
3704 | |||
3705 | ret = 0; | ||
3706 | |||
3707 | loopback_test_done: | ||
3708 | bp->loopback = 0; | ||
3709 | return ret; | ||
3710 | } | ||
3711 | |||
3712 | #define NVRAM_SIZE 0x200 | ||
3713 | #define CRC32_RESIDUAL 0xdebb20e3 | ||
3714 | |||
3715 | static int | ||
3716 | bnx2_test_nvram(struct bnx2 *bp) | ||
3717 | { | ||
3718 | u32 buf[NVRAM_SIZE / 4]; | ||
3719 | u8 *data = (u8 *) buf; | ||
3720 | int rc = 0; | ||
3721 | u32 magic, csum; | ||
3722 | |||
3723 | if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0) | ||
3724 | goto test_nvram_done; | ||
3725 | |||
3726 | magic = be32_to_cpu(buf[0]); | ||
3727 | if (magic != 0x669955aa) { | ||
3728 | rc = -ENODEV; | ||
3729 | goto test_nvram_done; | ||
3730 | } | ||
3731 | |||
3732 | if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0) | ||
3733 | goto test_nvram_done; | ||
3734 | |||
3735 | csum = ether_crc_le(0x100, data); | ||
3736 | if (csum != CRC32_RESIDUAL) { | ||
3737 | rc = -ENODEV; | ||
3738 | goto test_nvram_done; | ||
3739 | } | ||
3740 | |||
3741 | csum = ether_crc_le(0x100, data + 0x100); | ||
3742 | if (csum != CRC32_RESIDUAL) { | ||
3743 | rc = -ENODEV; | ||
3744 | } | ||
3745 | |||
3746 | test_nvram_done: | ||
3747 | return rc; | ||
3748 | } | ||
3749 | |||
3750 | static int | ||
3751 | bnx2_test_link(struct bnx2 *bp) | ||
3752 | { | ||
3753 | u32 bmsr; | ||
3754 | |||
3755 | spin_lock_irq(&bp->phy_lock); | ||
3756 | bnx2_read_phy(bp, MII_BMSR, &bmsr); | ||
3757 | bnx2_read_phy(bp, MII_BMSR, &bmsr); | ||
3758 | spin_unlock_irq(&bp->phy_lock); | ||
3759 | |||
3760 | if (bmsr & BMSR_LSTATUS) { | ||
3761 | return 0; | ||
3762 | } | ||
3763 | return -ENODEV; | ||
3764 | } | ||
3765 | |||
3766 | static int | ||
3767 | bnx2_test_intr(struct bnx2 *bp) | ||
3768 | { | ||
3769 | int i; | ||
3770 | u32 val; | ||
3771 | u16 status_idx; | ||
3772 | |||
3773 | if (!netif_running(bp->dev)) | ||
3774 | return -ENODEV; | ||
3775 | |||
3776 | status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff; | ||
3777 | |||
3778 | /* This register is not touched during run-time. */ | ||
3779 | val = REG_RD(bp, BNX2_HC_COMMAND); | ||
3780 | REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW); | ||
3781 | REG_RD(bp, BNX2_HC_COMMAND); | ||
3782 | |||
3783 | for (i = 0; i < 10; i++) { | ||
3784 | if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) != | ||
3785 | status_idx) { | ||
3786 | |||
3787 | break; | ||
3788 | } | ||
3789 | |||
3790 | msleep_interruptible(10); | ||
3791 | } | ||
3792 | if (i < 10) | ||
3793 | return 0; | ||
3794 | |||
3795 | return -ENODEV; | ||
3796 | } | ||
3797 | |||
3798 | static void | ||
3799 | bnx2_timer(unsigned long data) | ||
3800 | { | ||
3801 | struct bnx2 *bp = (struct bnx2 *) data; | ||
3802 | u32 msg; | ||
3803 | |||
3804 | if (atomic_read(&bp->intr_sem) != 0) | ||
3805 | goto bnx2_restart_timer; | ||
3806 | |||
3807 | msg = (u32) ++bp->fw_drv_pulse_wr_seq; | ||
3808 | REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_PULSE_MB, msg); | ||
3809 | |||
3810 | if ((bp->phy_flags & PHY_SERDES_FLAG) && | ||
3811 | (CHIP_NUM(bp) == CHIP_NUM_5706)) { | ||
3812 | unsigned long flags; | ||
3813 | |||
3814 | spin_lock_irqsave(&bp->phy_lock, flags); | ||
3815 | if (bp->serdes_an_pending) { | ||
3816 | bp->serdes_an_pending--; | ||
3817 | } | ||
3818 | else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) { | ||
3819 | u32 bmcr; | ||
3820 | |||
3821 | bnx2_read_phy(bp, MII_BMCR, &bmcr); | ||
3822 | |||
3823 | if (bmcr & BMCR_ANENABLE) { | ||
3824 | u32 phy1, phy2; | ||
3825 | |||
3826 | bnx2_write_phy(bp, 0x1c, 0x7c00); | ||
3827 | bnx2_read_phy(bp, 0x1c, &phy1); | ||
3828 | |||
3829 | bnx2_write_phy(bp, 0x17, 0x0f01); | ||
3830 | bnx2_read_phy(bp, 0x15, &phy2); | ||
3831 | bnx2_write_phy(bp, 0x17, 0x0f01); | ||
3832 | bnx2_read_phy(bp, 0x15, &phy2); | ||
3833 | |||
3834 | if ((phy1 & 0x10) && /* SIGNAL DETECT */ | ||
3835 | !(phy2 & 0x20)) { /* no CONFIG */ | ||
3836 | |||
3837 | bmcr &= ~BMCR_ANENABLE; | ||
3838 | bmcr |= BMCR_SPEED1000 | | ||
3839 | BMCR_FULLDPLX; | ||
3840 | bnx2_write_phy(bp, MII_BMCR, bmcr); | ||
3841 | bp->phy_flags |= | ||
3842 | PHY_PARALLEL_DETECT_FLAG; | ||
3843 | } | ||
3844 | } | ||
3845 | } | ||
3846 | else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) && | ||
3847 | (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) { | ||
3848 | u32 phy2; | ||
3849 | |||
3850 | bnx2_write_phy(bp, 0x17, 0x0f01); | ||
3851 | bnx2_read_phy(bp, 0x15, &phy2); | ||
3852 | if (phy2 & 0x20) { | ||
3853 | u32 bmcr; | ||
3854 | |||
3855 | bnx2_read_phy(bp, MII_BMCR, &bmcr); | ||
3856 | bmcr |= BMCR_ANENABLE; | ||
3857 | bnx2_write_phy(bp, MII_BMCR, bmcr); | ||
3858 | |||
3859 | bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG; | ||
3860 | |||
3861 | } | ||
3862 | } | ||
3863 | |||
3864 | spin_unlock_irqrestore(&bp->phy_lock, flags); | ||
3865 | } | ||
3866 | |||
3867 | bnx2_restart_timer: | ||
3868 | bp->timer.expires = RUN_AT(bp->timer_interval); | ||
3869 | |||
3870 | add_timer(&bp->timer); | ||
3871 | } | ||
3872 | |||
3873 | /* Called with rtnl_lock */ | ||
3874 | static int | ||
3875 | bnx2_open(struct net_device *dev) | ||
3876 | { | ||
3877 | struct bnx2 *bp = dev->priv; | ||
3878 | int rc; | ||
3879 | |||
3880 | bnx2_set_power_state(bp, 0); | ||
3881 | bnx2_disable_int(bp); | ||
3882 | |||
3883 | rc = bnx2_alloc_mem(bp); | ||
3884 | if (rc) | ||
3885 | return rc; | ||
3886 | |||
3887 | if ((CHIP_ID(bp) != CHIP_ID_5706_A0) && | ||
3888 | (CHIP_ID(bp) != CHIP_ID_5706_A1) && | ||
3889 | !disable_msi) { | ||
3890 | |||
3891 | if (pci_enable_msi(bp->pdev) == 0) { | ||
3892 | bp->flags |= USING_MSI_FLAG; | ||
3893 | rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name, | ||
3894 | dev); | ||
3895 | } | ||
3896 | else { | ||
3897 | rc = request_irq(bp->pdev->irq, bnx2_interrupt, | ||
3898 | SA_SHIRQ, dev->name, dev); | ||
3899 | } | ||
3900 | } | ||
3901 | else { | ||
3902 | rc = request_irq(bp->pdev->irq, bnx2_interrupt, SA_SHIRQ, | ||
3903 | dev->name, dev); | ||
3904 | } | ||
3905 | if (rc) { | ||
3906 | bnx2_free_mem(bp); | ||
3907 | return rc; | ||
3908 | } | ||
3909 | |||
3910 | rc = bnx2_init_nic(bp); | ||
3911 | |||
3912 | if (rc) { | ||
3913 | free_irq(bp->pdev->irq, dev); | ||
3914 | if (bp->flags & USING_MSI_FLAG) { | ||
3915 | pci_disable_msi(bp->pdev); | ||
3916 | bp->flags &= ~USING_MSI_FLAG; | ||
3917 | } | ||
3918 | bnx2_free_skbs(bp); | ||
3919 | bnx2_free_mem(bp); | ||
3920 | return rc; | ||
3921 | } | ||
3922 | |||
3923 | init_timer(&bp->timer); | ||
3924 | |||
3925 | bp->timer.expires = RUN_AT(bp->timer_interval); | ||
3926 | bp->timer.data = (unsigned long) bp; | ||
3927 | bp->timer.function = bnx2_timer; | ||
3928 | add_timer(&bp->timer); | ||
3929 | |||
3930 | atomic_set(&bp->intr_sem, 0); | ||
3931 | |||
3932 | bnx2_enable_int(bp); | ||
3933 | |||
3934 | if (bp->flags & USING_MSI_FLAG) { | ||
3935 | /* Test MSI to make sure it is working | ||
3936 | * If MSI test fails, go back to INTx mode | ||
3937 | */ | ||
3938 | if (bnx2_test_intr(bp) != 0) { | ||
3939 | printk(KERN_WARNING PFX "%s: No interrupt was generated" | ||
3940 | " using MSI, switching to INTx mode. Please" | ||
3941 | " report this failure to the PCI maintainer" | ||
3942 | " and include system chipset information.\n", | ||
3943 | bp->dev->name); | ||
3944 | |||
3945 | bnx2_disable_int(bp); | ||
3946 | free_irq(bp->pdev->irq, dev); | ||
3947 | pci_disable_msi(bp->pdev); | ||
3948 | bp->flags &= ~USING_MSI_FLAG; | ||
3949 | |||
3950 | rc = bnx2_init_nic(bp); | ||
3951 | |||
3952 | if (!rc) { | ||
3953 | rc = request_irq(bp->pdev->irq, bnx2_interrupt, | ||
3954 | SA_SHIRQ, dev->name, dev); | ||
3955 | } | ||
3956 | if (rc) { | ||
3957 | bnx2_free_skbs(bp); | ||
3958 | bnx2_free_mem(bp); | ||
3959 | del_timer_sync(&bp->timer); | ||
3960 | return rc; | ||
3961 | } | ||
3962 | bnx2_enable_int(bp); | ||
3963 | } | ||
3964 | } | ||
3965 | if (bp->flags & USING_MSI_FLAG) { | ||
3966 | printk(KERN_INFO PFX "%s: using MSI\n", dev->name); | ||
3967 | } | ||
3968 | |||
3969 | netif_start_queue(dev); | ||
3970 | |||
3971 | return 0; | ||
3972 | } | ||
3973 | |||
3974 | static void | ||
3975 | bnx2_reset_task(void *data) | ||
3976 | { | ||
3977 | struct bnx2 *bp = data; | ||
3978 | |||
3979 | bnx2_netif_stop(bp); | ||
3980 | |||
3981 | bnx2_init_nic(bp); | ||
3982 | |||
3983 | atomic_set(&bp->intr_sem, 1); | ||
3984 | bnx2_netif_start(bp); | ||
3985 | } | ||
3986 | |||
3987 | static void | ||
3988 | bnx2_tx_timeout(struct net_device *dev) | ||
3989 | { | ||
3990 | struct bnx2 *bp = dev->priv; | ||
3991 | |||
3992 | /* This allows the netif to be shutdown gracefully before resetting */ | ||
3993 | schedule_work(&bp->reset_task); | ||
3994 | } | ||
3995 | |||
3996 | #ifdef BCM_VLAN | ||
3997 | /* Called with rtnl_lock */ | ||
3998 | static void | ||
3999 | bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp) | ||
4000 | { | ||
4001 | struct bnx2 *bp = dev->priv; | ||
4002 | |||
4003 | bnx2_netif_stop(bp); | ||
4004 | |||
4005 | bp->vlgrp = vlgrp; | ||
4006 | bnx2_set_rx_mode(dev); | ||
4007 | |||
4008 | bnx2_netif_start(bp); | ||
4009 | } | ||
4010 | |||
4011 | /* Called with rtnl_lock */ | ||
4012 | static void | ||
4013 | bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid) | ||
4014 | { | ||
4015 | struct bnx2 *bp = dev->priv; | ||
4016 | |||
4017 | bnx2_netif_stop(bp); | ||
4018 | |||
4019 | if (bp->vlgrp) | ||
4020 | bp->vlgrp->vlan_devices[vid] = NULL; | ||
4021 | bnx2_set_rx_mode(dev); | ||
4022 | |||
4023 | bnx2_netif_start(bp); | ||
4024 | } | ||
4025 | #endif | ||
4026 | |||
4027 | /* Called with dev->xmit_lock. | ||
4028 | * hard_start_xmit is pseudo-lockless - a lock is only required when | ||
4029 | * the tx queue is full. This way, we get the benefit of lockless | ||
4030 | * operations most of the time without the complexities to handle | ||
4031 | * netif_stop_queue/wake_queue race conditions. | ||
4032 | */ | ||
4033 | static int | ||
4034 | bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) | ||
4035 | { | ||
4036 | struct bnx2 *bp = dev->priv; | ||
4037 | dma_addr_t mapping; | ||
4038 | struct tx_bd *txbd; | ||
4039 | struct sw_bd *tx_buf; | ||
4040 | u32 len, vlan_tag_flags, last_frag, mss; | ||
4041 | u16 prod, ring_prod; | ||
4042 | int i; | ||
4043 | |||
4044 | if (unlikely(atomic_read(&bp->tx_avail_bd) < | ||
4045 | (skb_shinfo(skb)->nr_frags + 1))) { | ||
4046 | |||
4047 | netif_stop_queue(dev); | ||
4048 | printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n", | ||
4049 | dev->name); | ||
4050 | |||
4051 | return NETDEV_TX_BUSY; | ||
4052 | } | ||
4053 | len = skb_headlen(skb); | ||
4054 | prod = bp->tx_prod; | ||
4055 | ring_prod = TX_RING_IDX(prod); | ||
4056 | |||
4057 | vlan_tag_flags = 0; | ||
4058 | if (skb->ip_summed == CHECKSUM_HW) { | ||
4059 | vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM; | ||
4060 | } | ||
4061 | |||
4062 | if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) { | ||
4063 | vlan_tag_flags |= | ||
4064 | (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16)); | ||
4065 | } | ||
4066 | #ifdef BCM_TSO | ||
4067 | if ((mss = skb_shinfo(skb)->tso_size) && | ||
4068 | (skb->len > (bp->dev->mtu + ETH_HLEN))) { | ||
4069 | u32 tcp_opt_len, ip_tcp_len; | ||
4070 | |||
4071 | if (skb_header_cloned(skb) && | ||
4072 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | ||
4073 | dev_kfree_skb(skb); | ||
4074 | return NETDEV_TX_OK; | ||
4075 | } | ||
4076 | |||
4077 | tcp_opt_len = ((skb->h.th->doff - 5) * 4); | ||
4078 | vlan_tag_flags |= TX_BD_FLAGS_SW_LSO; | ||
4079 | |||
4080 | tcp_opt_len = 0; | ||
4081 | if (skb->h.th->doff > 5) { | ||
4082 | tcp_opt_len = (skb->h.th->doff - 5) << 2; | ||
4083 | } | ||
4084 | ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr); | ||
4085 | |||
4086 | skb->nh.iph->check = 0; | ||
4087 | skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len); | ||
4088 | skb->h.th->check = | ||
4089 | ~csum_tcpudp_magic(skb->nh.iph->saddr, | ||
4090 | skb->nh.iph->daddr, | ||
4091 | 0, IPPROTO_TCP, 0); | ||
4092 | |||
4093 | if (tcp_opt_len || (skb->nh.iph->ihl > 5)) { | ||
4094 | vlan_tag_flags |= ((skb->nh.iph->ihl - 5) + | ||
4095 | (tcp_opt_len >> 2)) << 8; | ||
4096 | } | ||
4097 | } | ||
4098 | else | ||
4099 | #endif | ||
4100 | { | ||
4101 | mss = 0; | ||
4102 | } | ||
4103 | |||
4104 | mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE); | ||
4105 | |||
4106 | tx_buf = &bp->tx_buf_ring[ring_prod]; | ||
4107 | tx_buf->skb = skb; | ||
4108 | pci_unmap_addr_set(tx_buf, mapping, mapping); | ||
4109 | |||
4110 | txbd = &bp->tx_desc_ring[ring_prod]; | ||
4111 | |||
4112 | txbd->tx_bd_haddr_hi = (u64) mapping >> 32; | ||
4113 | txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; | ||
4114 | txbd->tx_bd_mss_nbytes = len | (mss << 16); | ||
4115 | txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START; | ||
4116 | |||
4117 | last_frag = skb_shinfo(skb)->nr_frags; | ||
4118 | |||
4119 | for (i = 0; i < last_frag; i++) { | ||
4120 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | ||
4121 | |||
4122 | prod = NEXT_TX_BD(prod); | ||
4123 | ring_prod = TX_RING_IDX(prod); | ||
4124 | txbd = &bp->tx_desc_ring[ring_prod]; | ||
4125 | |||
4126 | len = frag->size; | ||
4127 | mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset, | ||
4128 | len, PCI_DMA_TODEVICE); | ||
4129 | pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod], | ||
4130 | mapping, mapping); | ||
4131 | |||
4132 | txbd->tx_bd_haddr_hi = (u64) mapping >> 32; | ||
4133 | txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff; | ||
4134 | txbd->tx_bd_mss_nbytes = len | (mss << 16); | ||
4135 | txbd->tx_bd_vlan_tag_flags = vlan_tag_flags; | ||
4136 | |||
4137 | } | ||
4138 | txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END; | ||
4139 | |||
4140 | prod = NEXT_TX_BD(prod); | ||
4141 | bp->tx_prod_bseq += skb->len; | ||
4142 | |||
4143 | atomic_sub(last_frag + 1, &bp->tx_avail_bd); | ||
4144 | |||
4145 | REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod); | ||
4146 | REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq); | ||
4147 | |||
4148 | mmiowb(); | ||
4149 | |||
4150 | bp->tx_prod = prod; | ||
4151 | dev->trans_start = jiffies; | ||
4152 | |||
4153 | if (unlikely(atomic_read(&bp->tx_avail_bd) <= MAX_SKB_FRAGS)) { | ||
4154 | unsigned long flags; | ||
4155 | |||
4156 | spin_lock_irqsave(&bp->tx_lock, flags); | ||
4157 | if (atomic_read(&bp->tx_avail_bd) <= MAX_SKB_FRAGS) { | ||
4158 | netif_stop_queue(dev); | ||
4159 | |||
4160 | if (atomic_read(&bp->tx_avail_bd) > MAX_SKB_FRAGS) | ||
4161 | netif_wake_queue(dev); | ||
4162 | } | ||
4163 | spin_unlock_irqrestore(&bp->tx_lock, flags); | ||
4164 | } | ||
4165 | |||
4166 | return NETDEV_TX_OK; | ||
4167 | } | ||
4168 | |||
4169 | /* Called with rtnl_lock */ | ||
4170 | static int | ||
4171 | bnx2_close(struct net_device *dev) | ||
4172 | { | ||
4173 | struct bnx2 *bp = dev->priv; | ||
4174 | u32 reset_code; | ||
4175 | |||
4176 | flush_scheduled_work(); | ||
4177 | bnx2_netif_stop(bp); | ||
4178 | del_timer_sync(&bp->timer); | ||
4179 | if (bp->wol) | ||
4180 | reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL; | ||
4181 | else | ||
4182 | reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; | ||
4183 | bnx2_reset_chip(bp, reset_code); | ||
4184 | free_irq(bp->pdev->irq, dev); | ||
4185 | if (bp->flags & USING_MSI_FLAG) { | ||
4186 | pci_disable_msi(bp->pdev); | ||
4187 | bp->flags &= ~USING_MSI_FLAG; | ||
4188 | } | ||
4189 | bnx2_free_skbs(bp); | ||
4190 | bnx2_free_mem(bp); | ||
4191 | bp->link_up = 0; | ||
4192 | netif_carrier_off(bp->dev); | ||
4193 | bnx2_set_power_state(bp, 3); | ||
4194 | return 0; | ||
4195 | } | ||
4196 | |||
4197 | #define GET_NET_STATS64(ctr) \ | ||
4198 | (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \ | ||
4199 | (unsigned long) (ctr##_lo) | ||
4200 | |||
4201 | #define GET_NET_STATS32(ctr) \ | ||
4202 | (ctr##_lo) | ||
4203 | |||
4204 | #if (BITS_PER_LONG == 64) | ||
4205 | #define GET_NET_STATS GET_NET_STATS64 | ||
4206 | #else | ||
4207 | #define GET_NET_STATS GET_NET_STATS32 | ||
4208 | #endif | ||
4209 | |||
4210 | static struct net_device_stats * | ||
4211 | bnx2_get_stats(struct net_device *dev) | ||
4212 | { | ||
4213 | struct bnx2 *bp = dev->priv; | ||
4214 | struct statistics_block *stats_blk = bp->stats_blk; | ||
4215 | struct net_device_stats *net_stats = &bp->net_stats; | ||
4216 | |||
4217 | if (bp->stats_blk == NULL) { | ||
4218 | return net_stats; | ||
4219 | } | ||
4220 | net_stats->rx_packets = | ||
4221 | GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) + | ||
4222 | GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) + | ||
4223 | GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts); | ||
4224 | |||
4225 | net_stats->tx_packets = | ||
4226 | GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) + | ||
4227 | GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) + | ||
4228 | GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts); | ||
4229 | |||
4230 | net_stats->rx_bytes = | ||
4231 | GET_NET_STATS(stats_blk->stat_IfHCInOctets); | ||
4232 | |||
4233 | net_stats->tx_bytes = | ||
4234 | GET_NET_STATS(stats_blk->stat_IfHCOutOctets); | ||
4235 | |||
4236 | net_stats->multicast = | ||
4237 | GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts); | ||
4238 | |||
4239 | net_stats->collisions = | ||
4240 | (unsigned long) stats_blk->stat_EtherStatsCollisions; | ||
4241 | |||
4242 | net_stats->rx_length_errors = | ||
4243 | (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts + | ||
4244 | stats_blk->stat_EtherStatsOverrsizePkts); | ||
4245 | |||
4246 | net_stats->rx_over_errors = | ||
4247 | (unsigned long) stats_blk->stat_IfInMBUFDiscards; | ||
4248 | |||
4249 | net_stats->rx_frame_errors = | ||
4250 | (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors; | ||
4251 | |||
4252 | net_stats->rx_crc_errors = | ||
4253 | (unsigned long) stats_blk->stat_Dot3StatsFCSErrors; | ||
4254 | |||
4255 | net_stats->rx_errors = net_stats->rx_length_errors + | ||
4256 | net_stats->rx_over_errors + net_stats->rx_frame_errors + | ||
4257 | net_stats->rx_crc_errors; | ||
4258 | |||
4259 | net_stats->tx_aborted_errors = | ||
4260 | (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions + | ||
4261 | stats_blk->stat_Dot3StatsLateCollisions); | ||
4262 | |||
4263 | if (CHIP_NUM(bp) == CHIP_NUM_5706) | ||
4264 | net_stats->tx_carrier_errors = 0; | ||
4265 | else { | ||
4266 | net_stats->tx_carrier_errors = | ||
4267 | (unsigned long) | ||
4268 | stats_blk->stat_Dot3StatsCarrierSenseErrors; | ||
4269 | } | ||
4270 | |||
4271 | net_stats->tx_errors = | ||
4272 | (unsigned long) | ||
4273 | stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors | ||
4274 | + | ||
4275 | net_stats->tx_aborted_errors + | ||
4276 | net_stats->tx_carrier_errors; | ||
4277 | |||
4278 | return net_stats; | ||
4279 | } | ||
4280 | |||
4281 | /* All ethtool functions called with rtnl_lock */ | ||
4282 | |||
4283 | static int | ||
4284 | bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | ||
4285 | { | ||
4286 | struct bnx2 *bp = dev->priv; | ||
4287 | |||
4288 | cmd->supported = SUPPORTED_Autoneg; | ||
4289 | if (bp->phy_flags & PHY_SERDES_FLAG) { | ||
4290 | cmd->supported |= SUPPORTED_1000baseT_Full | | ||
4291 | SUPPORTED_FIBRE; | ||
4292 | |||
4293 | cmd->port = PORT_FIBRE; | ||
4294 | } | ||
4295 | else { | ||
4296 | cmd->supported |= SUPPORTED_10baseT_Half | | ||
4297 | SUPPORTED_10baseT_Full | | ||
4298 | SUPPORTED_100baseT_Half | | ||
4299 | SUPPORTED_100baseT_Full | | ||
4300 | SUPPORTED_1000baseT_Full | | ||
4301 | SUPPORTED_TP; | ||
4302 | |||
4303 | cmd->port = PORT_TP; | ||
4304 | } | ||
4305 | |||
4306 | cmd->advertising = bp->advertising; | ||
4307 | |||
4308 | if (bp->autoneg & AUTONEG_SPEED) { | ||
4309 | cmd->autoneg = AUTONEG_ENABLE; | ||
4310 | } | ||
4311 | else { | ||
4312 | cmd->autoneg = AUTONEG_DISABLE; | ||
4313 | } | ||
4314 | |||
4315 | if (netif_carrier_ok(dev)) { | ||
4316 | cmd->speed = bp->line_speed; | ||
4317 | cmd->duplex = bp->duplex; | ||
4318 | } | ||
4319 | else { | ||
4320 | cmd->speed = -1; | ||
4321 | cmd->duplex = -1; | ||
4322 | } | ||
4323 | |||
4324 | cmd->transceiver = XCVR_INTERNAL; | ||
4325 | cmd->phy_address = bp->phy_addr; | ||
4326 | |||
4327 | return 0; | ||
4328 | } | ||
4329 | |||
4330 | static int | ||
4331 | bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | ||
4332 | { | ||
4333 | struct bnx2 *bp = dev->priv; | ||
4334 | u8 autoneg = bp->autoneg; | ||
4335 | u8 req_duplex = bp->req_duplex; | ||
4336 | u16 req_line_speed = bp->req_line_speed; | ||
4337 | u32 advertising = bp->advertising; | ||
4338 | |||
4339 | if (cmd->autoneg == AUTONEG_ENABLE) { | ||
4340 | autoneg |= AUTONEG_SPEED; | ||
4341 | |||
4342 | cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED; | ||
4343 | |||
4344 | /* allow advertising 1 speed */ | ||
4345 | if ((cmd->advertising == ADVERTISED_10baseT_Half) || | ||
4346 | (cmd->advertising == ADVERTISED_10baseT_Full) || | ||
4347 | (cmd->advertising == ADVERTISED_100baseT_Half) || | ||
4348 | (cmd->advertising == ADVERTISED_100baseT_Full)) { | ||
4349 | |||
4350 | if (bp->phy_flags & PHY_SERDES_FLAG) | ||
4351 | return -EINVAL; | ||
4352 | |||
4353 | advertising = cmd->advertising; | ||
4354 | |||
4355 | } | ||
4356 | else if (cmd->advertising == ADVERTISED_1000baseT_Full) { | ||
4357 | advertising = cmd->advertising; | ||
4358 | } | ||
4359 | else if (cmd->advertising == ADVERTISED_1000baseT_Half) { | ||
4360 | return -EINVAL; | ||
4361 | } | ||
4362 | else { | ||
4363 | if (bp->phy_flags & PHY_SERDES_FLAG) { | ||
4364 | advertising = ETHTOOL_ALL_FIBRE_SPEED; | ||
4365 | } | ||
4366 | else { | ||
4367 | advertising = ETHTOOL_ALL_COPPER_SPEED; | ||
4368 | } | ||
4369 | } | ||
4370 | advertising |= ADVERTISED_Autoneg; | ||
4371 | } | ||
4372 | else { | ||
4373 | if (bp->phy_flags & PHY_SERDES_FLAG) { | ||
4374 | if ((cmd->speed != SPEED_1000) || | ||
4375 | (cmd->duplex != DUPLEX_FULL)) { | ||
4376 | return -EINVAL; | ||
4377 | } | ||
4378 | } | ||
4379 | else if (cmd->speed == SPEED_1000) { | ||
4380 | return -EINVAL; | ||
4381 | } | ||
4382 | autoneg &= ~AUTONEG_SPEED; | ||
4383 | req_line_speed = cmd->speed; | ||
4384 | req_duplex = cmd->duplex; | ||
4385 | advertising = 0; | ||
4386 | } | ||
4387 | |||
4388 | bp->autoneg = autoneg; | ||
4389 | bp->advertising = advertising; | ||
4390 | bp->req_line_speed = req_line_speed; | ||
4391 | bp->req_duplex = req_duplex; | ||
4392 | |||
4393 | spin_lock_irq(&bp->phy_lock); | ||
4394 | |||
4395 | bnx2_setup_phy(bp); | ||
4396 | |||
4397 | spin_unlock_irq(&bp->phy_lock); | ||
4398 | |||
4399 | return 0; | ||
4400 | } | ||
4401 | |||
4402 | static void | ||
4403 | bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | ||
4404 | { | ||
4405 | struct bnx2 *bp = dev->priv; | ||
4406 | |||
4407 | strcpy(info->driver, DRV_MODULE_NAME); | ||
4408 | strcpy(info->version, DRV_MODULE_VERSION); | ||
4409 | strcpy(info->bus_info, pci_name(bp->pdev)); | ||
4410 | info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0'; | ||
4411 | info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0'; | ||
4412 | info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0'; | ||
4413 | info->fw_version[6] = (bp->fw_ver & 0xff) + '0'; | ||
4414 | info->fw_version[1] = info->fw_version[3] = info->fw_version[5] = '.'; | ||
4415 | info->fw_version[7] = 0; | ||
4416 | } | ||
4417 | |||
4418 | static void | ||
4419 | bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | ||
4420 | { | ||
4421 | struct bnx2 *bp = dev->priv; | ||
4422 | |||
4423 | if (bp->flags & NO_WOL_FLAG) { | ||
4424 | wol->supported = 0; | ||
4425 | wol->wolopts = 0; | ||
4426 | } | ||
4427 | else { | ||
4428 | wol->supported = WAKE_MAGIC; | ||
4429 | if (bp->wol) | ||
4430 | wol->wolopts = WAKE_MAGIC; | ||
4431 | else | ||
4432 | wol->wolopts = 0; | ||
4433 | } | ||
4434 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | ||
4435 | } | ||
4436 | |||
4437 | static int | ||
4438 | bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | ||
4439 | { | ||
4440 | struct bnx2 *bp = dev->priv; | ||
4441 | |||
4442 | if (wol->wolopts & ~WAKE_MAGIC) | ||
4443 | return -EINVAL; | ||
4444 | |||
4445 | if (wol->wolopts & WAKE_MAGIC) { | ||
4446 | if (bp->flags & NO_WOL_FLAG) | ||
4447 | return -EINVAL; | ||
4448 | |||
4449 | bp->wol = 1; | ||
4450 | } | ||
4451 | else { | ||
4452 | bp->wol = 0; | ||
4453 | } | ||
4454 | return 0; | ||
4455 | } | ||
4456 | |||
4457 | static int | ||
4458 | bnx2_nway_reset(struct net_device *dev) | ||
4459 | { | ||
4460 | struct bnx2 *bp = dev->priv; | ||
4461 | u32 bmcr; | ||
4462 | |||
4463 | if (!(bp->autoneg & AUTONEG_SPEED)) { | ||
4464 | return -EINVAL; | ||
4465 | } | ||
4466 | |||
4467 | spin_lock_irq(&bp->phy_lock); | ||
4468 | |||
4469 | /* Force a link down visible on the other side */ | ||
4470 | if (bp->phy_flags & PHY_SERDES_FLAG) { | ||
4471 | bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK); | ||
4472 | spin_unlock_irq(&bp->phy_lock); | ||
4473 | |||
4474 | msleep(20); | ||
4475 | |||
4476 | spin_lock_irq(&bp->phy_lock); | ||
4477 | if (CHIP_NUM(bp) == CHIP_NUM_5706) { | ||
4478 | bp->serdes_an_pending = SERDES_AN_TIMEOUT / | ||
4479 | bp->timer_interval; | ||
4480 | } | ||
4481 | } | ||
4482 | |||
4483 | bnx2_read_phy(bp, MII_BMCR, &bmcr); | ||
4484 | bmcr &= ~BMCR_LOOPBACK; | ||
4485 | bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE); | ||
4486 | |||
4487 | spin_unlock_irq(&bp->phy_lock); | ||
4488 | |||
4489 | return 0; | ||
4490 | } | ||
4491 | |||
4492 | static int | ||
4493 | bnx2_get_eeprom_len(struct net_device *dev) | ||
4494 | { | ||
4495 | struct bnx2 *bp = dev->priv; | ||
4496 | |||
4497 | if (bp->flash_info == 0) | ||
4498 | return 0; | ||
4499 | |||
4500 | return (int) bp->flash_info->total_size; | ||
4501 | } | ||
4502 | |||
4503 | static int | ||
4504 | bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, | ||
4505 | u8 *eebuf) | ||
4506 | { | ||
4507 | struct bnx2 *bp = dev->priv; | ||
4508 | int rc; | ||
4509 | |||
4510 | if (eeprom->offset > bp->flash_info->total_size) | ||
4511 | return -EINVAL; | ||
4512 | |||
4513 | if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size) | ||
4514 | eeprom->len = bp->flash_info->total_size - eeprom->offset; | ||
4515 | |||
4516 | rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len); | ||
4517 | |||
4518 | return rc; | ||
4519 | } | ||
4520 | |||
4521 | static int | ||
4522 | bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, | ||
4523 | u8 *eebuf) | ||
4524 | { | ||
4525 | struct bnx2 *bp = dev->priv; | ||
4526 | int rc; | ||
4527 | |||
4528 | if (eeprom->offset > bp->flash_info->total_size) | ||
4529 | return -EINVAL; | ||
4530 | |||
4531 | if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size) | ||
4532 | eeprom->len = bp->flash_info->total_size - eeprom->offset; | ||
4533 | |||
4534 | rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); | ||
4535 | |||
4536 | return rc; | ||
4537 | } | ||
4538 | |||
4539 | static int | ||
4540 | bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal) | ||
4541 | { | ||
4542 | struct bnx2 *bp = dev->priv; | ||
4543 | |||
4544 | memset(coal, 0, sizeof(struct ethtool_coalesce)); | ||
4545 | |||
4546 | coal->rx_coalesce_usecs = bp->rx_ticks; | ||
4547 | coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip; | ||
4548 | coal->rx_coalesce_usecs_irq = bp->rx_ticks_int; | ||
4549 | coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int; | ||
4550 | |||
4551 | coal->tx_coalesce_usecs = bp->tx_ticks; | ||
4552 | coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip; | ||
4553 | coal->tx_coalesce_usecs_irq = bp->tx_ticks_int; | ||
4554 | coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int; | ||
4555 | |||
4556 | coal->stats_block_coalesce_usecs = bp->stats_ticks; | ||
4557 | |||
4558 | return 0; | ||
4559 | } | ||
4560 | |||
4561 | static int | ||
4562 | bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal) | ||
4563 | { | ||
4564 | struct bnx2 *bp = dev->priv; | ||
4565 | |||
4566 | bp->rx_ticks = (u16) coal->rx_coalesce_usecs; | ||
4567 | if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff; | ||
4568 | |||
4569 | bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames; | ||
4570 | if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff; | ||
4571 | |||
4572 | bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq; | ||
4573 | if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff; | ||
4574 | |||
4575 | bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq; | ||
4576 | if (bp->rx_quick_cons_trip_int > 0xff) | ||
4577 | bp->rx_quick_cons_trip_int = 0xff; | ||
4578 | |||
4579 | bp->tx_ticks = (u16) coal->tx_coalesce_usecs; | ||
4580 | if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff; | ||
4581 | |||
4582 | bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames; | ||
4583 | if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff; | ||
4584 | |||
4585 | bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq; | ||
4586 | if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff; | ||
4587 | |||
4588 | bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq; | ||
4589 | if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int = | ||
4590 | 0xff; | ||
4591 | |||
4592 | bp->stats_ticks = coal->stats_block_coalesce_usecs; | ||
4593 | if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00; | ||
4594 | bp->stats_ticks &= 0xffff00; | ||
4595 | |||
4596 | if (netif_running(bp->dev)) { | ||
4597 | bnx2_netif_stop(bp); | ||
4598 | bnx2_init_nic(bp); | ||
4599 | bnx2_netif_start(bp); | ||
4600 | } | ||
4601 | |||
4602 | return 0; | ||
4603 | } | ||
4604 | |||
4605 | static void | ||
4606 | bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) | ||
4607 | { | ||
4608 | struct bnx2 *bp = dev->priv; | ||
4609 | |||
4610 | ering->rx_max_pending = MAX_RX_DESC_CNT; | ||
4611 | ering->rx_mini_max_pending = 0; | ||
4612 | ering->rx_jumbo_max_pending = 0; | ||
4613 | |||
4614 | ering->rx_pending = bp->rx_ring_size; | ||
4615 | ering->rx_mini_pending = 0; | ||
4616 | ering->rx_jumbo_pending = 0; | ||
4617 | |||
4618 | ering->tx_max_pending = MAX_TX_DESC_CNT; | ||
4619 | ering->tx_pending = bp->tx_ring_size; | ||
4620 | } | ||
4621 | |||
4622 | static int | ||
4623 | bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) | ||
4624 | { | ||
4625 | struct bnx2 *bp = dev->priv; | ||
4626 | |||
4627 | if ((ering->rx_pending > MAX_RX_DESC_CNT) || | ||
4628 | (ering->tx_pending > MAX_TX_DESC_CNT) || | ||
4629 | (ering->tx_pending <= MAX_SKB_FRAGS)) { | ||
4630 | |||
4631 | return -EINVAL; | ||
4632 | } | ||
4633 | bp->rx_ring_size = ering->rx_pending; | ||
4634 | bp->tx_ring_size = ering->tx_pending; | ||
4635 | |||
4636 | if (netif_running(bp->dev)) { | ||
4637 | bnx2_netif_stop(bp); | ||
4638 | bnx2_init_nic(bp); | ||
4639 | bnx2_netif_start(bp); | ||
4640 | } | ||
4641 | |||
4642 | return 0; | ||
4643 | } | ||
4644 | |||
4645 | static void | ||
4646 | bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) | ||
4647 | { | ||
4648 | struct bnx2 *bp = dev->priv; | ||
4649 | |||
4650 | epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0); | ||
4651 | epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0); | ||
4652 | epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0); | ||
4653 | } | ||
4654 | |||
4655 | static int | ||
4656 | bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) | ||
4657 | { | ||
4658 | struct bnx2 *bp = dev->priv; | ||
4659 | |||
4660 | bp->req_flow_ctrl = 0; | ||
4661 | if (epause->rx_pause) | ||
4662 | bp->req_flow_ctrl |= FLOW_CTRL_RX; | ||
4663 | if (epause->tx_pause) | ||
4664 | bp->req_flow_ctrl |= FLOW_CTRL_TX; | ||
4665 | |||
4666 | if (epause->autoneg) { | ||
4667 | bp->autoneg |= AUTONEG_FLOW_CTRL; | ||
4668 | } | ||
4669 | else { | ||
4670 | bp->autoneg &= ~AUTONEG_FLOW_CTRL; | ||
4671 | } | ||
4672 | |||
4673 | spin_lock_irq(&bp->phy_lock); | ||
4674 | |||
4675 | bnx2_setup_phy(bp); | ||
4676 | |||
4677 | spin_unlock_irq(&bp->phy_lock); | ||
4678 | |||
4679 | return 0; | ||
4680 | } | ||
4681 | |||
4682 | static u32 | ||
4683 | bnx2_get_rx_csum(struct net_device *dev) | ||
4684 | { | ||
4685 | struct bnx2 *bp = dev->priv; | ||
4686 | |||
4687 | return bp->rx_csum; | ||
4688 | } | ||
4689 | |||
4690 | static int | ||
4691 | bnx2_set_rx_csum(struct net_device *dev, u32 data) | ||
4692 | { | ||
4693 | struct bnx2 *bp = dev->priv; | ||
4694 | |||
4695 | bp->rx_csum = data; | ||
4696 | return 0; | ||
4697 | } | ||
4698 | |||
4699 | #define BNX2_NUM_STATS 45 | ||
4700 | |||
4701 | struct { | ||
4702 | char string[ETH_GSTRING_LEN]; | ||
4703 | } bnx2_stats_str_arr[BNX2_NUM_STATS] = { | ||
4704 | { "rx_bytes" }, | ||
4705 | { "rx_error_bytes" }, | ||
4706 | { "tx_bytes" }, | ||
4707 | { "tx_error_bytes" }, | ||
4708 | { "rx_ucast_packets" }, | ||
4709 | { "rx_mcast_packets" }, | ||
4710 | { "rx_bcast_packets" }, | ||
4711 | { "tx_ucast_packets" }, | ||
4712 | { "tx_mcast_packets" }, | ||
4713 | { "tx_bcast_packets" }, | ||
4714 | { "tx_mac_errors" }, | ||
4715 | { "tx_carrier_errors" }, | ||
4716 | { "rx_crc_errors" }, | ||
4717 | { "rx_align_errors" }, | ||
4718 | { "tx_single_collisions" }, | ||
4719 | { "tx_multi_collisions" }, | ||
4720 | { "tx_deferred" }, | ||
4721 | { "tx_excess_collisions" }, | ||
4722 | { "tx_late_collisions" }, | ||
4723 | { "tx_total_collisions" }, | ||
4724 | { "rx_fragments" }, | ||
4725 | { "rx_jabbers" }, | ||
4726 | { "rx_undersize_packets" }, | ||
4727 | { "rx_oversize_packets" }, | ||
4728 | { "rx_64_byte_packets" }, | ||
4729 | { "rx_65_to_127_byte_packets" }, | ||
4730 | { "rx_128_to_255_byte_packets" }, | ||
4731 | { "rx_256_to_511_byte_packets" }, | ||
4732 | { "rx_512_to_1023_byte_packets" }, | ||
4733 | { "rx_1024_to_1522_byte_packets" }, | ||
4734 | { "rx_1523_to_9022_byte_packets" }, | ||
4735 | { "tx_64_byte_packets" }, | ||
4736 | { "tx_65_to_127_byte_packets" }, | ||
4737 | { "tx_128_to_255_byte_packets" }, | ||
4738 | { "tx_256_to_511_byte_packets" }, | ||
4739 | { "tx_512_to_1023_byte_packets" }, | ||
4740 | { "tx_1024_to_1522_byte_packets" }, | ||
4741 | { "tx_1523_to_9022_byte_packets" }, | ||
4742 | { "rx_xon_frames" }, | ||
4743 | { "rx_xoff_frames" }, | ||
4744 | { "tx_xon_frames" }, | ||
4745 | { "tx_xoff_frames" }, | ||
4746 | { "rx_mac_ctrl_frames" }, | ||
4747 | { "rx_filtered_packets" }, | ||
4748 | { "rx_discards" }, | ||
4749 | }; | ||
4750 | |||
4751 | #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4) | ||
4752 | |||
4753 | unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = { | ||
4754 | STATS_OFFSET32(stat_IfHCInOctets_hi), | ||
4755 | STATS_OFFSET32(stat_IfHCInBadOctets_hi), | ||
4756 | STATS_OFFSET32(stat_IfHCOutOctets_hi), | ||
4757 | STATS_OFFSET32(stat_IfHCOutBadOctets_hi), | ||
4758 | STATS_OFFSET32(stat_IfHCInUcastPkts_hi), | ||
4759 | STATS_OFFSET32(stat_IfHCInMulticastPkts_hi), | ||
4760 | STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi), | ||
4761 | STATS_OFFSET32(stat_IfHCOutUcastPkts_hi), | ||
4762 | STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi), | ||
4763 | STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi), | ||
4764 | STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors), | ||
4765 | STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors), | ||
4766 | STATS_OFFSET32(stat_Dot3StatsFCSErrors), | ||
4767 | STATS_OFFSET32(stat_Dot3StatsAlignmentErrors), | ||
4768 | STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames), | ||
4769 | STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames), | ||
4770 | STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions), | ||
4771 | STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions), | ||
4772 | STATS_OFFSET32(stat_Dot3StatsLateCollisions), | ||
4773 | STATS_OFFSET32(stat_EtherStatsCollisions), | ||
4774 | STATS_OFFSET32(stat_EtherStatsFragments), | ||
4775 | STATS_OFFSET32(stat_EtherStatsJabbers), | ||
4776 | STATS_OFFSET32(stat_EtherStatsUndersizePkts), | ||
4777 | STATS_OFFSET32(stat_EtherStatsOverrsizePkts), | ||
4778 | STATS_OFFSET32(stat_EtherStatsPktsRx64Octets), | ||
4779 | STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets), | ||
4780 | STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets), | ||
4781 | STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets), | ||
4782 | STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets), | ||
4783 | STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets), | ||
4784 | STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets), | ||
4785 | STATS_OFFSET32(stat_EtherStatsPktsTx64Octets), | ||
4786 | STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets), | ||
4787 | STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets), | ||
4788 | STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets), | ||
4789 | STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets), | ||
4790 | STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets), | ||
4791 | STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets), | ||
4792 | STATS_OFFSET32(stat_XonPauseFramesReceived), | ||
4793 | STATS_OFFSET32(stat_XoffPauseFramesReceived), | ||
4794 | STATS_OFFSET32(stat_OutXonSent), | ||
4795 | STATS_OFFSET32(stat_OutXoffSent), | ||
4796 | STATS_OFFSET32(stat_MacControlFramesReceived), | ||
4797 | STATS_OFFSET32(stat_IfInFramesL2FilterDiscards), | ||
4798 | STATS_OFFSET32(stat_IfInMBUFDiscards), | ||
4799 | }; | ||
4800 | |||
4801 | /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are | ||
4802 | * skipped because of errata. | ||
4803 | */ | ||
4804 | u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = { | ||
4805 | 8,0,8,8,8,8,8,8,8,8, | ||
4806 | 4,0,4,4,4,4,4,4,4,4, | ||
4807 | 4,4,4,4,4,4,4,4,4,4, | ||
4808 | 4,4,4,4,4,4,4,4,4,4, | ||
4809 | 4,4,4,4,4, | ||
4810 | }; | ||
4811 | |||
4812 | #define BNX2_NUM_TESTS 6 | ||
4813 | |||
4814 | struct { | ||
4815 | char string[ETH_GSTRING_LEN]; | ||
4816 | } bnx2_tests_str_arr[BNX2_NUM_TESTS] = { | ||
4817 | { "register_test (offline)" }, | ||
4818 | { "memory_test (offline)" }, | ||
4819 | { "loopback_test (offline)" }, | ||
4820 | { "nvram_test (online)" }, | ||
4821 | { "interrupt_test (online)" }, | ||
4822 | { "link_test (online)" }, | ||
4823 | }; | ||
4824 | |||
4825 | static int | ||
4826 | bnx2_self_test_count(struct net_device *dev) | ||
4827 | { | ||
4828 | return BNX2_NUM_TESTS; | ||
4829 | } | ||
4830 | |||
4831 | static void | ||
4832 | bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf) | ||
4833 | { | ||
4834 | struct bnx2 *bp = dev->priv; | ||
4835 | |||
4836 | memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS); | ||
4837 | if (etest->flags & ETH_TEST_FL_OFFLINE) { | ||
4838 | bnx2_netif_stop(bp); | ||
4839 | bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG); | ||
4840 | bnx2_free_skbs(bp); | ||
4841 | |||
4842 | if (bnx2_test_registers(bp) != 0) { | ||
4843 | buf[0] = 1; | ||
4844 | etest->flags |= ETH_TEST_FL_FAILED; | ||
4845 | } | ||
4846 | if (bnx2_test_memory(bp) != 0) { | ||
4847 | buf[1] = 1; | ||
4848 | etest->flags |= ETH_TEST_FL_FAILED; | ||
4849 | } | ||
4850 | if (bnx2_test_loopback(bp) != 0) { | ||
4851 | buf[2] = 1; | ||
4852 | etest->flags |= ETH_TEST_FL_FAILED; | ||
4853 | } | ||
4854 | |||
4855 | if (!netif_running(bp->dev)) { | ||
4856 | bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET); | ||
4857 | } | ||
4858 | else { | ||
4859 | bnx2_init_nic(bp); | ||
4860 | bnx2_netif_start(bp); | ||
4861 | } | ||
4862 | |||
4863 | /* wait for link up */ | ||
4864 | msleep_interruptible(3000); | ||
4865 | if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG)) | ||
4866 | msleep_interruptible(4000); | ||
4867 | } | ||
4868 | |||
4869 | if (bnx2_test_nvram(bp) != 0) { | ||
4870 | buf[3] = 1; | ||
4871 | etest->flags |= ETH_TEST_FL_FAILED; | ||
4872 | } | ||
4873 | if (bnx2_test_intr(bp) != 0) { | ||
4874 | buf[4] = 1; | ||
4875 | etest->flags |= ETH_TEST_FL_FAILED; | ||
4876 | } | ||
4877 | |||
4878 | if (bnx2_test_link(bp) != 0) { | ||
4879 | buf[5] = 1; | ||
4880 | etest->flags |= ETH_TEST_FL_FAILED; | ||
4881 | |||
4882 | } | ||
4883 | } | ||
4884 | |||
4885 | static void | ||
4886 | bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf) | ||
4887 | { | ||
4888 | switch (stringset) { | ||
4889 | case ETH_SS_STATS: | ||
4890 | memcpy(buf, bnx2_stats_str_arr, | ||
4891 | sizeof(bnx2_stats_str_arr)); | ||
4892 | break; | ||
4893 | case ETH_SS_TEST: | ||
4894 | memcpy(buf, bnx2_tests_str_arr, | ||
4895 | sizeof(bnx2_tests_str_arr)); | ||
4896 | break; | ||
4897 | } | ||
4898 | } | ||
4899 | |||
4900 | static int | ||
4901 | bnx2_get_stats_count(struct net_device *dev) | ||
4902 | { | ||
4903 | return BNX2_NUM_STATS; | ||
4904 | } | ||
4905 | |||
4906 | static void | ||
4907 | bnx2_get_ethtool_stats(struct net_device *dev, | ||
4908 | struct ethtool_stats *stats, u64 *buf) | ||
4909 | { | ||
4910 | struct bnx2 *bp = dev->priv; | ||
4911 | int i; | ||
4912 | u32 *hw_stats = (u32 *) bp->stats_blk; | ||
4913 | u8 *stats_len_arr = 0; | ||
4914 | |||
4915 | if (hw_stats == NULL) { | ||
4916 | memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS); | ||
4917 | return; | ||
4918 | } | ||
4919 | |||
4920 | if (CHIP_NUM(bp) == CHIP_NUM_5706) | ||
4921 | stats_len_arr = bnx2_5706_stats_len_arr; | ||
4922 | |||
4923 | for (i = 0; i < BNX2_NUM_STATS; i++) { | ||
4924 | if (stats_len_arr[i] == 0) { | ||
4925 | /* skip this counter */ | ||
4926 | buf[i] = 0; | ||
4927 | continue; | ||
4928 | } | ||
4929 | if (stats_len_arr[i] == 4) { | ||
4930 | /* 4-byte counter */ | ||
4931 | buf[i] = (u64) | ||
4932 | *(hw_stats + bnx2_stats_offset_arr[i]); | ||
4933 | continue; | ||
4934 | } | ||
4935 | /* 8-byte counter */ | ||
4936 | buf[i] = (((u64) *(hw_stats + | ||
4937 | bnx2_stats_offset_arr[i])) << 32) + | ||
4938 | *(hw_stats + bnx2_stats_offset_arr[i] + 1); | ||
4939 | } | ||
4940 | } | ||
4941 | |||
4942 | static int | ||
4943 | bnx2_phys_id(struct net_device *dev, u32 data) | ||
4944 | { | ||
4945 | struct bnx2 *bp = dev->priv; | ||
4946 | int i; | ||
4947 | u32 save; | ||
4948 | |||
4949 | if (data == 0) | ||
4950 | data = 2; | ||
4951 | |||
4952 | save = REG_RD(bp, BNX2_MISC_CFG); | ||
4953 | REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC); | ||
4954 | |||
4955 | for (i = 0; i < (data * 2); i++) { | ||
4956 | if ((i % 2) == 0) { | ||
4957 | REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE); | ||
4958 | } | ||
4959 | else { | ||
4960 | REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE | | ||
4961 | BNX2_EMAC_LED_1000MB_OVERRIDE | | ||
4962 | BNX2_EMAC_LED_100MB_OVERRIDE | | ||
4963 | BNX2_EMAC_LED_10MB_OVERRIDE | | ||
4964 | BNX2_EMAC_LED_TRAFFIC_OVERRIDE | | ||
4965 | BNX2_EMAC_LED_TRAFFIC); | ||
4966 | } | ||
4967 | msleep_interruptible(500); | ||
4968 | if (signal_pending(current)) | ||
4969 | break; | ||
4970 | } | ||
4971 | REG_WR(bp, BNX2_EMAC_LED, 0); | ||
4972 | REG_WR(bp, BNX2_MISC_CFG, save); | ||
4973 | return 0; | ||
4974 | } | ||
4975 | |||
4976 | static struct ethtool_ops bnx2_ethtool_ops = { | ||
4977 | .get_settings = bnx2_get_settings, | ||
4978 | .set_settings = bnx2_set_settings, | ||
4979 | .get_drvinfo = bnx2_get_drvinfo, | ||
4980 | .get_wol = bnx2_get_wol, | ||
4981 | .set_wol = bnx2_set_wol, | ||
4982 | .nway_reset = bnx2_nway_reset, | ||
4983 | .get_link = ethtool_op_get_link, | ||
4984 | .get_eeprom_len = bnx2_get_eeprom_len, | ||
4985 | .get_eeprom = bnx2_get_eeprom, | ||
4986 | .set_eeprom = bnx2_set_eeprom, | ||
4987 | .get_coalesce = bnx2_get_coalesce, | ||
4988 | .set_coalesce = bnx2_set_coalesce, | ||
4989 | .get_ringparam = bnx2_get_ringparam, | ||
4990 | .set_ringparam = bnx2_set_ringparam, | ||
4991 | .get_pauseparam = bnx2_get_pauseparam, | ||
4992 | .set_pauseparam = bnx2_set_pauseparam, | ||
4993 | .get_rx_csum = bnx2_get_rx_csum, | ||
4994 | .set_rx_csum = bnx2_set_rx_csum, | ||
4995 | .get_tx_csum = ethtool_op_get_tx_csum, | ||
4996 | .set_tx_csum = ethtool_op_set_tx_csum, | ||
4997 | .get_sg = ethtool_op_get_sg, | ||
4998 | .set_sg = ethtool_op_set_sg, | ||
4999 | #ifdef BCM_TSO | ||
5000 | .get_tso = ethtool_op_get_tso, | ||
5001 | .set_tso = ethtool_op_set_tso, | ||
5002 | #endif | ||
5003 | .self_test_count = bnx2_self_test_count, | ||
5004 | .self_test = bnx2_self_test, | ||
5005 | .get_strings = bnx2_get_strings, | ||
5006 | .phys_id = bnx2_phys_id, | ||
5007 | .get_stats_count = bnx2_get_stats_count, | ||
5008 | .get_ethtool_stats = bnx2_get_ethtool_stats, | ||
5009 | }; | ||
5010 | |||
5011 | /* Called with rtnl_lock */ | ||
5012 | static int | ||
5013 | bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | ||
5014 | { | ||
5015 | struct mii_ioctl_data *data = (struct mii_ioctl_data *)&ifr->ifr_data; | ||
5016 | struct bnx2 *bp = dev->priv; | ||
5017 | int err; | ||
5018 | |||
5019 | switch(cmd) { | ||
5020 | case SIOCGMIIPHY: | ||
5021 | data->phy_id = bp->phy_addr; | ||
5022 | |||
5023 | /* fallthru */ | ||
5024 | case SIOCGMIIREG: { | ||
5025 | u32 mii_regval; | ||
5026 | |||
5027 | spin_lock_irq(&bp->phy_lock); | ||
5028 | err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval); | ||
5029 | spin_unlock_irq(&bp->phy_lock); | ||
5030 | |||
5031 | data->val_out = mii_regval; | ||
5032 | |||
5033 | return err; | ||
5034 | } | ||
5035 | |||
5036 | case SIOCSMIIREG: | ||
5037 | if (!capable(CAP_NET_ADMIN)) | ||
5038 | return -EPERM; | ||
5039 | |||
5040 | spin_lock_irq(&bp->phy_lock); | ||
5041 | err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in); | ||
5042 | spin_unlock_irq(&bp->phy_lock); | ||
5043 | |||
5044 | return err; | ||
5045 | |||
5046 | default: | ||
5047 | /* do nothing */ | ||
5048 | break; | ||
5049 | } | ||
5050 | return -EOPNOTSUPP; | ||
5051 | } | ||
5052 | |||
5053 | /* Called with rtnl_lock */ | ||
5054 | static int | ||
5055 | bnx2_change_mac_addr(struct net_device *dev, void *p) | ||
5056 | { | ||
5057 | struct sockaddr *addr = p; | ||
5058 | struct bnx2 *bp = dev->priv; | ||
5059 | |||
5060 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | ||
5061 | if (netif_running(dev)) | ||
5062 | bnx2_set_mac_addr(bp); | ||
5063 | |||
5064 | return 0; | ||
5065 | } | ||
5066 | |||
5067 | /* Called with rtnl_lock */ | ||
5068 | static int | ||
5069 | bnx2_change_mtu(struct net_device *dev, int new_mtu) | ||
5070 | { | ||
5071 | struct bnx2 *bp = dev->priv; | ||
5072 | |||
5073 | if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) || | ||
5074 | ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE)) | ||
5075 | return -EINVAL; | ||
5076 | |||
5077 | dev->mtu = new_mtu; | ||
5078 | if (netif_running(dev)) { | ||
5079 | bnx2_netif_stop(bp); | ||
5080 | |||
5081 | bnx2_init_nic(bp); | ||
5082 | |||
5083 | bnx2_netif_start(bp); | ||
5084 | } | ||
5085 | return 0; | ||
5086 | } | ||
5087 | |||
5088 | #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER) | ||
5089 | static void | ||
5090 | poll_bnx2(struct net_device *dev) | ||
5091 | { | ||
5092 | struct bnx2 *bp = dev->priv; | ||
5093 | |||
5094 | disable_irq(bp->pdev->irq); | ||
5095 | bnx2_interrupt(bp->pdev->irq, dev, NULL); | ||
5096 | enable_irq(bp->pdev->irq); | ||
5097 | } | ||
5098 | #endif | ||
5099 | |||
5100 | static int __devinit | ||
5101 | bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) | ||
5102 | { | ||
5103 | struct bnx2 *bp; | ||
5104 | unsigned long mem_len; | ||
5105 | int rc; | ||
5106 | u32 reg; | ||
5107 | |||
5108 | SET_MODULE_OWNER(dev); | ||
5109 | SET_NETDEV_DEV(dev, &pdev->dev); | ||
5110 | bp = dev->priv; | ||
5111 | |||
5112 | bp->flags = 0; | ||
5113 | bp->phy_flags = 0; | ||
5114 | |||
5115 | /* enable device (incl. PCI PM wakeup), and bus-mastering */ | ||
5116 | rc = pci_enable_device(pdev); | ||
5117 | if (rc) { | ||
5118 | printk(KERN_ERR PFX "Cannot enable PCI device, aborting."); | ||
5119 | goto err_out; | ||
5120 | } | ||
5121 | |||
5122 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | ||
5123 | printk(KERN_ERR PFX "Cannot find PCI device base address, " | ||
5124 | "aborting.\n"); | ||
5125 | rc = -ENODEV; | ||
5126 | goto err_out_disable; | ||
5127 | } | ||
5128 | |||
5129 | rc = pci_request_regions(pdev, DRV_MODULE_NAME); | ||
5130 | if (rc) { | ||
5131 | printk(KERN_ERR PFX "Cannot obtain PCI resources, aborting.\n"); | ||
5132 | goto err_out_disable; | ||
5133 | } | ||
5134 | |||
5135 | pci_set_master(pdev); | ||
5136 | |||
5137 | bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | ||
5138 | if (bp->pm_cap == 0) { | ||
5139 | printk(KERN_ERR PFX "Cannot find power management capability, " | ||
5140 | "aborting.\n"); | ||
5141 | rc = -EIO; | ||
5142 | goto err_out_release; | ||
5143 | } | ||
5144 | |||
5145 | bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX); | ||
5146 | if (bp->pcix_cap == 0) { | ||
5147 | printk(KERN_ERR PFX "Cannot find PCIX capability, aborting.\n"); | ||
5148 | rc = -EIO; | ||
5149 | goto err_out_release; | ||
5150 | } | ||
5151 | |||
5152 | if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) { | ||
5153 | bp->flags |= USING_DAC_FLAG; | ||
5154 | if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) { | ||
5155 | printk(KERN_ERR PFX "pci_set_consistent_dma_mask " | ||
5156 | "failed, aborting.\n"); | ||
5157 | rc = -EIO; | ||
5158 | goto err_out_release; | ||
5159 | } | ||
5160 | } | ||
5161 | else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) { | ||
5162 | printk(KERN_ERR PFX "System does not support DMA, aborting.\n"); | ||
5163 | rc = -EIO; | ||
5164 | goto err_out_release; | ||
5165 | } | ||
5166 | |||
5167 | bp->dev = dev; | ||
5168 | bp->pdev = pdev; | ||
5169 | |||
5170 | spin_lock_init(&bp->phy_lock); | ||
5171 | spin_lock_init(&bp->tx_lock); | ||
5172 | INIT_WORK(&bp->reset_task, bnx2_reset_task, bp); | ||
5173 | |||
5174 | dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0); | ||
5175 | mem_len = MB_GET_CID_ADDR(17); | ||
5176 | dev->mem_end = dev->mem_start + mem_len; | ||
5177 | dev->irq = pdev->irq; | ||
5178 | |||
5179 | bp->regview = ioremap_nocache(dev->base_addr, mem_len); | ||
5180 | |||
5181 | if (!bp->regview) { | ||
5182 | printk(KERN_ERR PFX "Cannot map register space, aborting.\n"); | ||
5183 | rc = -ENOMEM; | ||
5184 | goto err_out_release; | ||
5185 | } | ||
5186 | |||
5187 | /* Configure byte swap and enable write to the reg_window registers. | ||
5188 | * Rely on CPU to do target byte swapping on big endian systems | ||
5189 | * The chip's target access swapping will not swap all accesses | ||
5190 | */ | ||
5191 | pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, | ||
5192 | BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA | | ||
5193 | BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP); | ||
5194 | |||
5195 | bnx2_set_power_state(bp, 0); | ||
5196 | |||
5197 | bp->chip_id = REG_RD(bp, BNX2_MISC_ID); | ||
5198 | |||
5199 | bp->phy_addr = 1; | ||
5200 | |||
5201 | /* Get bus information. */ | ||
5202 | reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS); | ||
5203 | if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) { | ||
5204 | u32 clkreg; | ||
5205 | |||
5206 | bp->flags |= PCIX_FLAG; | ||
5207 | |||
5208 | clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS); | ||
5209 | |||
5210 | clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET; | ||
5211 | switch (clkreg) { | ||
5212 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ: | ||
5213 | bp->bus_speed_mhz = 133; | ||
5214 | break; | ||
5215 | |||
5216 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ: | ||
5217 | bp->bus_speed_mhz = 100; | ||
5218 | break; | ||
5219 | |||
5220 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ: | ||
5221 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ: | ||
5222 | bp->bus_speed_mhz = 66; | ||
5223 | break; | ||
5224 | |||
5225 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ: | ||
5226 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ: | ||
5227 | bp->bus_speed_mhz = 50; | ||
5228 | break; | ||
5229 | |||
5230 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW: | ||
5231 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ: | ||
5232 | case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ: | ||
5233 | bp->bus_speed_mhz = 33; | ||
5234 | break; | ||
5235 | } | ||
5236 | } | ||
5237 | else { | ||
5238 | if (reg & BNX2_PCICFG_MISC_STATUS_M66EN) | ||
5239 | bp->bus_speed_mhz = 66; | ||
5240 | else | ||
5241 | bp->bus_speed_mhz = 33; | ||
5242 | } | ||
5243 | |||
5244 | if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET) | ||
5245 | bp->flags |= PCI_32BIT_FLAG; | ||
5246 | |||
5247 | /* 5706A0 may falsely detect SERR and PERR. */ | ||
5248 | if (CHIP_ID(bp) == CHIP_ID_5706_A0) { | ||
5249 | reg = REG_RD(bp, PCI_COMMAND); | ||
5250 | reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY); | ||
5251 | REG_WR(bp, PCI_COMMAND, reg); | ||
5252 | } | ||
5253 | else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) && | ||
5254 | !(bp->flags & PCIX_FLAG)) { | ||
5255 | |||
5256 | printk(KERN_ERR PFX "5706 A1 can only be used in a PCIX bus, " | ||
5257 | "aborting.\n"); | ||
5258 | goto err_out_unmap; | ||
5259 | } | ||
5260 | |||
5261 | bnx2_init_nvram(bp); | ||
5262 | |||
5263 | /* Get the permanent MAC address. First we need to make sure the | ||
5264 | * firmware is actually running. | ||
5265 | */ | ||
5266 | reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DEV_INFO_SIGNATURE); | ||
5267 | |||
5268 | if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) != | ||
5269 | BNX2_DEV_INFO_SIGNATURE_MAGIC) { | ||
5270 | printk(KERN_ERR PFX "Firmware not running, aborting.\n"); | ||
5271 | rc = -ENODEV; | ||
5272 | goto err_out_unmap; | ||
5273 | } | ||
5274 | |||
5275 | bp->fw_ver = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + | ||
5276 | BNX2_DEV_INFO_BC_REV); | ||
5277 | |||
5278 | reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_UPPER); | ||
5279 | bp->mac_addr[0] = (u8) (reg >> 8); | ||
5280 | bp->mac_addr[1] = (u8) reg; | ||
5281 | |||
5282 | reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_LOWER); | ||
5283 | bp->mac_addr[2] = (u8) (reg >> 24); | ||
5284 | bp->mac_addr[3] = (u8) (reg >> 16); | ||
5285 | bp->mac_addr[4] = (u8) (reg >> 8); | ||
5286 | bp->mac_addr[5] = (u8) reg; | ||
5287 | |||
5288 | bp->tx_ring_size = MAX_TX_DESC_CNT; | ||
5289 | bp->rx_ring_size = 100; | ||
5290 | |||
5291 | bp->rx_csum = 1; | ||
5292 | |||
5293 | bp->rx_offset = sizeof(struct l2_fhdr) + 2; | ||
5294 | |||
5295 | bp->tx_quick_cons_trip_int = 20; | ||
5296 | bp->tx_quick_cons_trip = 20; | ||
5297 | bp->tx_ticks_int = 80; | ||
5298 | bp->tx_ticks = 80; | ||
5299 | |||
5300 | bp->rx_quick_cons_trip_int = 6; | ||
5301 | bp->rx_quick_cons_trip = 6; | ||
5302 | bp->rx_ticks_int = 18; | ||
5303 | bp->rx_ticks = 18; | ||
5304 | |||
5305 | bp->stats_ticks = 1000000 & 0xffff00; | ||
5306 | |||
5307 | bp->timer_interval = HZ; | ||
5308 | |||
5309 | /* Disable WOL support if we are running on a SERDES chip. */ | ||
5310 | if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) { | ||
5311 | bp->phy_flags |= PHY_SERDES_FLAG; | ||
5312 | bp->flags |= NO_WOL_FLAG; | ||
5313 | } | ||
5314 | |||
5315 | if (CHIP_ID(bp) == CHIP_ID_5706_A0) { | ||
5316 | bp->tx_quick_cons_trip_int = | ||
5317 | bp->tx_quick_cons_trip; | ||
5318 | bp->tx_ticks_int = bp->tx_ticks; | ||
5319 | bp->rx_quick_cons_trip_int = | ||
5320 | bp->rx_quick_cons_trip; | ||
5321 | bp->rx_ticks_int = bp->rx_ticks; | ||
5322 | bp->comp_prod_trip_int = bp->comp_prod_trip; | ||
5323 | bp->com_ticks_int = bp->com_ticks; | ||
5324 | bp->cmd_ticks_int = bp->cmd_ticks; | ||
5325 | } | ||
5326 | |||
5327 | bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL; | ||
5328 | bp->req_line_speed = 0; | ||
5329 | if (bp->phy_flags & PHY_SERDES_FLAG) { | ||
5330 | bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg; | ||
5331 | } | ||
5332 | else { | ||
5333 | bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg; | ||
5334 | } | ||
5335 | |||
5336 | bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX; | ||
5337 | |||
5338 | return 0; | ||
5339 | |||
5340 | err_out_unmap: | ||
5341 | if (bp->regview) { | ||
5342 | iounmap(bp->regview); | ||
5343 | } | ||
5344 | |||
5345 | err_out_release: | ||
5346 | pci_release_regions(pdev); | ||
5347 | |||
5348 | err_out_disable: | ||
5349 | pci_disable_device(pdev); | ||
5350 | pci_set_drvdata(pdev, NULL); | ||
5351 | |||
5352 | err_out: | ||
5353 | return rc; | ||
5354 | } | ||
5355 | |||
5356 | static int __devinit | ||
5357 | bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | ||
5358 | { | ||
5359 | static int version_printed = 0; | ||
5360 | struct net_device *dev = NULL; | ||
5361 | struct bnx2 *bp; | ||
5362 | int rc, i; | ||
5363 | |||
5364 | if (version_printed++ == 0) | ||
5365 | printk(KERN_INFO "%s", version); | ||
5366 | |||
5367 | /* dev zeroed in init_etherdev */ | ||
5368 | dev = alloc_etherdev(sizeof(*bp)); | ||
5369 | |||
5370 | if (!dev) | ||
5371 | return -ENOMEM; | ||
5372 | |||
5373 | rc = bnx2_init_board(pdev, dev); | ||
5374 | if (rc < 0) { | ||
5375 | free_netdev(dev); | ||
5376 | return rc; | ||
5377 | } | ||
5378 | |||
5379 | dev->open = bnx2_open; | ||
5380 | dev->hard_start_xmit = bnx2_start_xmit; | ||
5381 | dev->stop = bnx2_close; | ||
5382 | dev->get_stats = bnx2_get_stats; | ||
5383 | dev->set_multicast_list = bnx2_set_rx_mode; | ||
5384 | dev->do_ioctl = bnx2_ioctl; | ||
5385 | dev->set_mac_address = bnx2_change_mac_addr; | ||
5386 | dev->change_mtu = bnx2_change_mtu; | ||
5387 | dev->tx_timeout = bnx2_tx_timeout; | ||
5388 | dev->watchdog_timeo = TX_TIMEOUT; | ||
5389 | #ifdef BCM_VLAN | ||
5390 | dev->vlan_rx_register = bnx2_vlan_rx_register; | ||
5391 | dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid; | ||
5392 | #endif | ||
5393 | dev->poll = bnx2_poll; | ||
5394 | dev->ethtool_ops = &bnx2_ethtool_ops; | ||
5395 | dev->weight = 64; | ||
5396 | |||
5397 | bp = dev->priv; | ||
5398 | |||
5399 | #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER) | ||
5400 | dev->poll_controller = poll_bnx2; | ||
5401 | #endif | ||
5402 | |||
5403 | if ((rc = register_netdev(dev))) { | ||
5404 | printk(KERN_ERR PFX "Cannot register net device\n"); | ||
5405 | if (bp->regview) | ||
5406 | iounmap(bp->regview); | ||
5407 | pci_release_regions(pdev); | ||
5408 | pci_disable_device(pdev); | ||
5409 | pci_set_drvdata(pdev, NULL); | ||
5410 | free_netdev(dev); | ||
5411 | return rc; | ||
5412 | } | ||
5413 | |||
5414 | pci_set_drvdata(pdev, dev); | ||
5415 | |||
5416 | memcpy(dev->dev_addr, bp->mac_addr, 6); | ||
5417 | bp->name = board_info[ent->driver_data].name, | ||
5418 | printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, " | ||
5419 | "IRQ %d, ", | ||
5420 | dev->name, | ||
5421 | bp->name, | ||
5422 | ((CHIP_ID(bp) & 0xf000) >> 12) + 'A', | ||
5423 | ((CHIP_ID(bp) & 0x0ff0) >> 4), | ||
5424 | ((bp->flags & PCIX_FLAG) ? "-X" : ""), | ||
5425 | ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"), | ||
5426 | bp->bus_speed_mhz, | ||
5427 | dev->base_addr, | ||
5428 | bp->pdev->irq); | ||
5429 | |||
5430 | printk("node addr "); | ||
5431 | for (i = 0; i < 6; i++) | ||
5432 | printk("%2.2x", dev->dev_addr[i]); | ||
5433 | printk("\n"); | ||
5434 | |||
5435 | dev->features |= NETIF_F_SG; | ||
5436 | if (bp->flags & USING_DAC_FLAG) | ||
5437 | dev->features |= NETIF_F_HIGHDMA; | ||
5438 | dev->features |= NETIF_F_IP_CSUM; | ||
5439 | #ifdef BCM_VLAN | ||
5440 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | ||
5441 | #endif | ||
5442 | #ifdef BCM_TSO | ||
5443 | dev->features |= NETIF_F_TSO; | ||
5444 | #endif | ||
5445 | |||
5446 | netif_carrier_off(bp->dev); | ||
5447 | |||
5448 | return 0; | ||
5449 | } | ||
5450 | |||
5451 | static void __devexit | ||
5452 | bnx2_remove_one(struct pci_dev *pdev) | ||
5453 | { | ||
5454 | struct net_device *dev = pci_get_drvdata(pdev); | ||
5455 | struct bnx2 *bp = dev->priv; | ||
5456 | |||
5457 | unregister_netdev(dev); | ||
5458 | |||
5459 | if (bp->regview) | ||
5460 | iounmap(bp->regview); | ||
5461 | |||
5462 | free_netdev(dev); | ||
5463 | pci_release_regions(pdev); | ||
5464 | pci_disable_device(pdev); | ||
5465 | pci_set_drvdata(pdev, NULL); | ||
5466 | } | ||
5467 | |||
5468 | static int | ||
5469 | bnx2_suspend(struct pci_dev *pdev, u32 state) | ||
5470 | { | ||
5471 | struct net_device *dev = pci_get_drvdata(pdev); | ||
5472 | struct bnx2 *bp = dev->priv; | ||
5473 | u32 reset_code; | ||
5474 | |||
5475 | if (!netif_running(dev)) | ||
5476 | return 0; | ||
5477 | |||
5478 | bnx2_netif_stop(bp); | ||
5479 | netif_device_detach(dev); | ||
5480 | del_timer_sync(&bp->timer); | ||
5481 | if (bp->wol) | ||
5482 | reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL; | ||
5483 | else | ||
5484 | reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL; | ||
5485 | bnx2_reset_chip(bp, reset_code); | ||
5486 | bnx2_free_skbs(bp); | ||
5487 | bnx2_set_power_state(bp, state); | ||
5488 | return 0; | ||
5489 | } | ||
5490 | |||
5491 | static int | ||
5492 | bnx2_resume(struct pci_dev *pdev) | ||
5493 | { | ||
5494 | struct net_device *dev = pci_get_drvdata(pdev); | ||
5495 | struct bnx2 *bp = dev->priv; | ||
5496 | |||
5497 | if (!netif_running(dev)) | ||
5498 | return 0; | ||
5499 | |||
5500 | bnx2_set_power_state(bp, 0); | ||
5501 | netif_device_attach(dev); | ||
5502 | bnx2_init_nic(bp); | ||
5503 | bnx2_netif_start(bp); | ||
5504 | return 0; | ||
5505 | } | ||
5506 | |||
5507 | static struct pci_driver bnx2_pci_driver = { | ||
5508 | name: DRV_MODULE_NAME, | ||
5509 | id_table: bnx2_pci_tbl, | ||
5510 | probe: bnx2_init_one, | ||
5511 | remove: __devexit_p(bnx2_remove_one), | ||
5512 | suspend: bnx2_suspend, | ||
5513 | resume: bnx2_resume, | ||
5514 | }; | ||
5515 | |||
5516 | static int __init bnx2_init(void) | ||
5517 | { | ||
5518 | return pci_module_init(&bnx2_pci_driver); | ||
5519 | } | ||
5520 | |||
5521 | static void __exit bnx2_cleanup(void) | ||
5522 | { | ||
5523 | pci_unregister_driver(&bnx2_pci_driver); | ||
5524 | } | ||
5525 | |||
5526 | module_init(bnx2_init); | ||
5527 | module_exit(bnx2_cleanup); | ||
5528 | |||
5529 | |||
5530 | |||
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h new file mode 100644 index 000000000000..8214a2853d0d --- /dev/null +++ b/drivers/net/bnx2.h | |||
@@ -0,0 +1,4352 @@ | |||
1 | /* bnx2.h: Broadcom NX2 network driver. | ||
2 | * | ||
3 | * Copyright (c) 2004, 2005 Broadcom Corporation | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License as published by | ||
7 | * the Free Software Foundation. | ||
8 | * | ||
9 | * Written by: Michael Chan (mchan@broadcom.com) | ||
10 | */ | ||
11 | |||
12 | |||
13 | #ifndef BNX2_H | ||
14 | #define BNX2_H | ||
15 | |||
16 | #include <linux/config.h> | ||
17 | |||
18 | #include <linux/module.h> | ||
19 | #include <linux/moduleparam.h> | ||
20 | |||
21 | #include <linux/kernel.h> | ||
22 | #include <linux/timer.h> | ||
23 | #include <linux/errno.h> | ||
24 | #include <linux/ioport.h> | ||
25 | #include <linux/slab.h> | ||
26 | #include <linux/interrupt.h> | ||
27 | #include <linux/pci.h> | ||
28 | #include <linux/init.h> | ||
29 | #include <linux/netdevice.h> | ||
30 | #include <linux/etherdevice.h> | ||
31 | #include <linux/skbuff.h> | ||
32 | #include <linux/dma-mapping.h> | ||
33 | #include <asm/bitops.h> | ||
34 | #include <asm/io.h> | ||
35 | #include <asm/irq.h> | ||
36 | #include <linux/delay.h> | ||
37 | #include <asm/byteorder.h> | ||
38 | #include <linux/time.h> | ||
39 | #include <linux/ethtool.h> | ||
40 | #include <linux/mii.h> | ||
41 | #ifdef NETIF_F_HW_VLAN_TX | ||
42 | #include <linux/if_vlan.h> | ||
43 | #define BCM_VLAN 1 | ||
44 | #endif | ||
45 | #ifdef NETIF_F_TSO | ||
46 | #include <net/ip.h> | ||
47 | #include <net/tcp.h> | ||
48 | #include <net/checksum.h> | ||
49 | #define BCM_TSO 1 | ||
50 | #endif | ||
51 | #include <linux/workqueue.h> | ||
52 | #include <linux/crc32.h> | ||
53 | |||
54 | /* Hardware data structures and register definitions automatically | ||
55 | * generated from RTL code. Do not modify. | ||
56 | */ | ||
57 | |||
58 | /* | ||
59 | * tx_bd definition | ||
60 | */ | ||
61 | struct tx_bd { | ||
62 | u32 tx_bd_haddr_hi; | ||
63 | u32 tx_bd_haddr_lo; | ||
64 | u32 tx_bd_mss_nbytes; | ||
65 | u32 tx_bd_vlan_tag_flags; | ||
66 | #define TX_BD_FLAGS_CONN_FAULT (1<<0) | ||
67 | #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1) | ||
68 | #define TX_BD_FLAGS_IP_CKSUM (1<<2) | ||
69 | #define TX_BD_FLAGS_VLAN_TAG (1<<3) | ||
70 | #define TX_BD_FLAGS_COAL_NOW (1<<4) | ||
71 | #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5) | ||
72 | #define TX_BD_FLAGS_END (1<<6) | ||
73 | #define TX_BD_FLAGS_START (1<<7) | ||
74 | #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8) | ||
75 | #define TX_BD_FLAGS_SW_FLAGS (1<<13) | ||
76 | #define TX_BD_FLAGS_SW_SNAP (1<<14) | ||
77 | #define TX_BD_FLAGS_SW_LSO (1<<15) | ||
78 | |||
79 | }; | ||
80 | |||
81 | |||
82 | /* | ||
83 | * rx_bd definition | ||
84 | */ | ||
85 | struct rx_bd { | ||
86 | u32 rx_bd_haddr_hi; | ||
87 | u32 rx_bd_haddr_lo; | ||
88 | u32 rx_bd_len; | ||
89 | u32 rx_bd_flags; | ||
90 | #define RX_BD_FLAGS_NOPUSH (1<<0) | ||
91 | #define RX_BD_FLAGS_DUMMY (1<<1) | ||
92 | #define RX_BD_FLAGS_END (1<<2) | ||
93 | #define RX_BD_FLAGS_START (1<<3) | ||
94 | |||
95 | }; | ||
96 | |||
97 | |||
98 | /* | ||
99 | * status_block definition | ||
100 | */ | ||
101 | struct status_block { | ||
102 | u32 status_attn_bits; | ||
103 | #define STATUS_ATTN_BITS_LINK_STATE (1L<<0) | ||
104 | #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1) | ||
105 | #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2) | ||
106 | #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3) | ||
107 | #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4) | ||
108 | #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5) | ||
109 | #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6) | ||
110 | #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7) | ||
111 | #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8) | ||
112 | #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9) | ||
113 | #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10) | ||
114 | #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11) | ||
115 | #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12) | ||
116 | #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13) | ||
117 | #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14) | ||
118 | #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15) | ||
119 | #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16) | ||
120 | #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17) | ||
121 | #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18) | ||
122 | #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19) | ||
123 | #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20) | ||
124 | #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21) | ||
125 | #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22) | ||
126 | #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23) | ||
127 | #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24) | ||
128 | #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25) | ||
129 | #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26) | ||
130 | #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27) | ||
131 | #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31) | ||
132 | |||
133 | u32 status_attn_bits_ack; | ||
134 | #if defined(__BIG_ENDIAN) | ||
135 | u16 status_tx_quick_consumer_index0; | ||
136 | u16 status_tx_quick_consumer_index1; | ||
137 | u16 status_tx_quick_consumer_index2; | ||
138 | u16 status_tx_quick_consumer_index3; | ||
139 | u16 status_rx_quick_consumer_index0; | ||
140 | u16 status_rx_quick_consumer_index1; | ||
141 | u16 status_rx_quick_consumer_index2; | ||
142 | u16 status_rx_quick_consumer_index3; | ||
143 | u16 status_rx_quick_consumer_index4; | ||
144 | u16 status_rx_quick_consumer_index5; | ||
145 | u16 status_rx_quick_consumer_index6; | ||
146 | u16 status_rx_quick_consumer_index7; | ||
147 | u16 status_rx_quick_consumer_index8; | ||
148 | u16 status_rx_quick_consumer_index9; | ||
149 | u16 status_rx_quick_consumer_index10; | ||
150 | u16 status_rx_quick_consumer_index11; | ||
151 | u16 status_rx_quick_consumer_index12; | ||
152 | u16 status_rx_quick_consumer_index13; | ||
153 | u16 status_rx_quick_consumer_index14; | ||
154 | u16 status_rx_quick_consumer_index15; | ||
155 | u16 status_completion_producer_index; | ||
156 | u16 status_cmd_consumer_index; | ||
157 | u16 status_idx; | ||
158 | u16 status_unused; | ||
159 | #elif defined(__LITTLE_ENDIAN) | ||
160 | u16 status_tx_quick_consumer_index1; | ||
161 | u16 status_tx_quick_consumer_index0; | ||
162 | u16 status_tx_quick_consumer_index3; | ||
163 | u16 status_tx_quick_consumer_index2; | ||
164 | u16 status_rx_quick_consumer_index1; | ||
165 | u16 status_rx_quick_consumer_index0; | ||
166 | u16 status_rx_quick_consumer_index3; | ||
167 | u16 status_rx_quick_consumer_index2; | ||
168 | u16 status_rx_quick_consumer_index5; | ||
169 | u16 status_rx_quick_consumer_index4; | ||
170 | u16 status_rx_quick_consumer_index7; | ||
171 | u16 status_rx_quick_consumer_index6; | ||
172 | u16 status_rx_quick_consumer_index9; | ||
173 | u16 status_rx_quick_consumer_index8; | ||
174 | u16 status_rx_quick_consumer_index11; | ||
175 | u16 status_rx_quick_consumer_index10; | ||
176 | u16 status_rx_quick_consumer_index13; | ||
177 | u16 status_rx_quick_consumer_index12; | ||
178 | u16 status_rx_quick_consumer_index15; | ||
179 | u16 status_rx_quick_consumer_index14; | ||
180 | u16 status_cmd_consumer_index; | ||
181 | u16 status_completion_producer_index; | ||
182 | u16 status_unused; | ||
183 | u16 status_idx; | ||
184 | #endif | ||
185 | }; | ||
186 | |||
187 | |||
188 | /* | ||
189 | * statistics_block definition | ||
190 | */ | ||
191 | struct statistics_block { | ||
192 | u32 stat_IfHCInOctets_hi; | ||
193 | u32 stat_IfHCInOctets_lo; | ||
194 | u32 stat_IfHCInBadOctets_hi; | ||
195 | u32 stat_IfHCInBadOctets_lo; | ||
196 | u32 stat_IfHCOutOctets_hi; | ||
197 | u32 stat_IfHCOutOctets_lo; | ||
198 | u32 stat_IfHCOutBadOctets_hi; | ||
199 | u32 stat_IfHCOutBadOctets_lo; | ||
200 | u32 stat_IfHCInUcastPkts_hi; | ||
201 | u32 stat_IfHCInUcastPkts_lo; | ||
202 | u32 stat_IfHCInMulticastPkts_hi; | ||
203 | u32 stat_IfHCInMulticastPkts_lo; | ||
204 | u32 stat_IfHCInBroadcastPkts_hi; | ||
205 | u32 stat_IfHCInBroadcastPkts_lo; | ||
206 | u32 stat_IfHCOutUcastPkts_hi; | ||
207 | u32 stat_IfHCOutUcastPkts_lo; | ||
208 | u32 stat_IfHCOutMulticastPkts_hi; | ||
209 | u32 stat_IfHCOutMulticastPkts_lo; | ||
210 | u32 stat_IfHCOutBroadcastPkts_hi; | ||
211 | u32 stat_IfHCOutBroadcastPkts_lo; | ||
212 | u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors; | ||
213 | u32 stat_Dot3StatsCarrierSenseErrors; | ||
214 | u32 stat_Dot3StatsFCSErrors; | ||
215 | u32 stat_Dot3StatsAlignmentErrors; | ||
216 | u32 stat_Dot3StatsSingleCollisionFrames; | ||
217 | u32 stat_Dot3StatsMultipleCollisionFrames; | ||
218 | u32 stat_Dot3StatsDeferredTransmissions; | ||
219 | u32 stat_Dot3StatsExcessiveCollisions; | ||
220 | u32 stat_Dot3StatsLateCollisions; | ||
221 | u32 stat_EtherStatsCollisions; | ||
222 | u32 stat_EtherStatsFragments; | ||
223 | u32 stat_EtherStatsJabbers; | ||
224 | u32 stat_EtherStatsUndersizePkts; | ||
225 | u32 stat_EtherStatsOverrsizePkts; | ||
226 | u32 stat_EtherStatsPktsRx64Octets; | ||
227 | u32 stat_EtherStatsPktsRx65Octetsto127Octets; | ||
228 | u32 stat_EtherStatsPktsRx128Octetsto255Octets; | ||
229 | u32 stat_EtherStatsPktsRx256Octetsto511Octets; | ||
230 | u32 stat_EtherStatsPktsRx512Octetsto1023Octets; | ||
231 | u32 stat_EtherStatsPktsRx1024Octetsto1522Octets; | ||
232 | u32 stat_EtherStatsPktsRx1523Octetsto9022Octets; | ||
233 | u32 stat_EtherStatsPktsTx64Octets; | ||
234 | u32 stat_EtherStatsPktsTx65Octetsto127Octets; | ||
235 | u32 stat_EtherStatsPktsTx128Octetsto255Octets; | ||
236 | u32 stat_EtherStatsPktsTx256Octetsto511Octets; | ||
237 | u32 stat_EtherStatsPktsTx512Octetsto1023Octets; | ||
238 | u32 stat_EtherStatsPktsTx1024Octetsto1522Octets; | ||
239 | u32 stat_EtherStatsPktsTx1523Octetsto9022Octets; | ||
240 | u32 stat_XonPauseFramesReceived; | ||
241 | u32 stat_XoffPauseFramesReceived; | ||
242 | u32 stat_OutXonSent; | ||
243 | u32 stat_OutXoffSent; | ||
244 | u32 stat_FlowControlDone; | ||
245 | u32 stat_MacControlFramesReceived; | ||
246 | u32 stat_XoffStateEntered; | ||
247 | u32 stat_IfInFramesL2FilterDiscards; | ||
248 | u32 stat_IfInRuleCheckerDiscards; | ||
249 | u32 stat_IfInFTQDiscards; | ||
250 | u32 stat_IfInMBUFDiscards; | ||
251 | u32 stat_IfInRuleCheckerP4Hit; | ||
252 | u32 stat_CatchupInRuleCheckerDiscards; | ||
253 | u32 stat_CatchupInFTQDiscards; | ||
254 | u32 stat_CatchupInMBUFDiscards; | ||
255 | u32 stat_CatchupInRuleCheckerP4Hit; | ||
256 | u32 stat_GenStat00; | ||
257 | u32 stat_GenStat01; | ||
258 | u32 stat_GenStat02; | ||
259 | u32 stat_GenStat03; | ||
260 | u32 stat_GenStat04; | ||
261 | u32 stat_GenStat05; | ||
262 | u32 stat_GenStat06; | ||
263 | u32 stat_GenStat07; | ||
264 | u32 stat_GenStat08; | ||
265 | u32 stat_GenStat09; | ||
266 | u32 stat_GenStat10; | ||
267 | u32 stat_GenStat11; | ||
268 | u32 stat_GenStat12; | ||
269 | u32 stat_GenStat13; | ||
270 | u32 stat_GenStat14; | ||
271 | u32 stat_GenStat15; | ||
272 | }; | ||
273 | |||
274 | |||
275 | /* | ||
276 | * l2_fhdr definition | ||
277 | */ | ||
278 | struct l2_fhdr { | ||
279 | #if defined(__BIG_ENDIAN) | ||
280 | u16 l2_fhdr_errors; | ||
281 | u16 l2_fhdr_status; | ||
282 | #elif defined(__LITTLE_ENDIAN) | ||
283 | u16 l2_fhdr_status; | ||
284 | u16 l2_fhdr_errors; | ||
285 | #endif | ||
286 | #define L2_FHDR_ERRORS_BAD_CRC (1<<1) | ||
287 | #define L2_FHDR_ERRORS_PHY_DECODE (1<<2) | ||
288 | #define L2_FHDR_ERRORS_ALIGNMENT (1<<3) | ||
289 | #define L2_FHDR_ERRORS_TOO_SHORT (1<<4) | ||
290 | #define L2_FHDR_ERRORS_GIANT_FRAME (1<<5) | ||
291 | |||
292 | #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0) | ||
293 | #define L2_FHDR_STATUS_RULE_P2 (1<<3) | ||
294 | #define L2_FHDR_STATUS_RULE_P3 (1<<4) | ||
295 | #define L2_FHDR_STATUS_RULE_P4 (1<<5) | ||
296 | #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6) | ||
297 | #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7) | ||
298 | #define L2_FHDR_STATUS_RSS_HASH (1<<8) | ||
299 | #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13) | ||
300 | #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14) | ||
301 | #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15) | ||
302 | |||
303 | u32 l2_fhdr_hash; | ||
304 | #if defined(__BIG_ENDIAN) | ||
305 | u16 l2_fhdr_pkt_len; | ||
306 | u16 l2_fhdr_vlan_tag; | ||
307 | u16 l2_fhdr_ip_xsum; | ||
308 | u16 l2_fhdr_tcp_udp_xsum; | ||
309 | #elif defined(__LITTLE_ENDIAN) | ||
310 | u16 l2_fhdr_vlan_tag; | ||
311 | u16 l2_fhdr_pkt_len; | ||
312 | u16 l2_fhdr_tcp_udp_xsum; | ||
313 | u16 l2_fhdr_ip_xsum; | ||
314 | #endif | ||
315 | }; | ||
316 | |||
317 | |||
318 | /* | ||
319 | * l2_context definition | ||
320 | */ | ||
321 | #define BNX2_L2CTX_TYPE 0x00000000 | ||
322 | #define BNX2_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16) | ||
323 | #define BNX2_L2CTX_TYPE_TYPE (0xf<<28) | ||
324 | #define BNX2_L2CTX_TYPE_TYPE_EMPTY (0<<28) | ||
325 | #define BNX2_L2CTX_TYPE_TYPE_L2 (1<<28) | ||
326 | |||
327 | #define BNX2_L2CTX_TX_HOST_BIDX 0x00000088 | ||
328 | #define BNX2_L2CTX_EST_NBD 0x00000088 | ||
329 | #define BNX2_L2CTX_CMD_TYPE 0x00000088 | ||
330 | #define BNX2_L2CTX_CMD_TYPE_TYPE (0xf<<24) | ||
331 | #define BNX2_L2CTX_CMD_TYPE_TYPE_L2 (0<<24) | ||
332 | #define BNX2_L2CTX_CMD_TYPE_TYPE_TCP (1<<24) | ||
333 | |||
334 | #define BNX2_L2CTX_TX_HOST_BSEQ 0x00000090 | ||
335 | #define BNX2_L2CTX_TSCH_BSEQ 0x00000094 | ||
336 | #define BNX2_L2CTX_TBDR_BSEQ 0x00000098 | ||
337 | #define BNX2_L2CTX_TBDR_BOFF 0x0000009c | ||
338 | #define BNX2_L2CTX_TBDR_BIDX 0x0000009c | ||
339 | #define BNX2_L2CTX_TBDR_BHADDR_HI 0x000000a0 | ||
340 | #define BNX2_L2CTX_TBDR_BHADDR_LO 0x000000a4 | ||
341 | #define BNX2_L2CTX_TXP_BOFF 0x000000a8 | ||
342 | #define BNX2_L2CTX_TXP_BIDX 0x000000a8 | ||
343 | #define BNX2_L2CTX_TXP_BSEQ 0x000000ac | ||
344 | |||
345 | |||
346 | /* | ||
347 | * l2_bd_chain_context definition | ||
348 | */ | ||
349 | #define BNX2_L2CTX_BD_PRE_READ 0x00000000 | ||
350 | #define BNX2_L2CTX_CTX_SIZE 0x00000000 | ||
351 | #define BNX2_L2CTX_CTX_TYPE 0x00000000 | ||
352 | #define BNX2_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16) | ||
353 | #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28) | ||
354 | #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28) | ||
355 | #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28) | ||
356 | |||
357 | #define BNX2_L2CTX_HOST_BDIDX 0x00000004 | ||
358 | #define BNX2_L2CTX_HOST_BSEQ 0x00000008 | ||
359 | #define BNX2_L2CTX_NX_BSEQ 0x0000000c | ||
360 | #define BNX2_L2CTX_NX_BDHADDR_HI 0x00000010 | ||
361 | #define BNX2_L2CTX_NX_BDHADDR_LO 0x00000014 | ||
362 | #define BNX2_L2CTX_NX_BDIDX 0x00000018 | ||
363 | |||
364 | |||
365 | /* | ||
366 | * pci_config_l definition | ||
367 | * offset: 0000 | ||
368 | */ | ||
369 | #define BNX2_PCICFG_MISC_CONFIG 0x00000068 | ||
370 | #define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2) | ||
371 | #define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3) | ||
372 | #define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5) | ||
373 | #define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6) | ||
374 | #define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7) | ||
375 | #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8) | ||
376 | #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9) | ||
377 | #define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16) | ||
378 | #define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24) | ||
379 | #define BNX2_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28) | ||
380 | |||
381 | #define BNX2_PCICFG_MISC_STATUS 0x0000006c | ||
382 | #define BNX2_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0) | ||
383 | #define BNX2_PCICFG_MISC_STATUS_32BIT_DET (1L<<1) | ||
384 | #define BNX2_PCICFG_MISC_STATUS_M66EN (1L<<2) | ||
385 | #define BNX2_PCICFG_MISC_STATUS_PCIX_DET (1L<<3) | ||
386 | #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED (0x3L<<4) | ||
387 | #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4) | ||
388 | #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4) | ||
389 | #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4) | ||
390 | #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4) | ||
391 | |||
392 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070 | ||
393 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) | ||
394 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) | ||
395 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) | ||
396 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) | ||
397 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) | ||
398 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) | ||
399 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) | ||
400 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) | ||
401 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) | ||
402 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) | ||
403 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) | ||
404 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) | ||
405 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) | ||
406 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) | ||
407 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) | ||
408 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) | ||
409 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) | ||
410 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) | ||
411 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) | ||
412 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) | ||
413 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) | ||
414 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) | ||
415 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) | ||
416 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) | ||
417 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) | ||
418 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) | ||
419 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) | ||
420 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) | ||
421 | #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) | ||
422 | |||
423 | #define BNX2_PCICFG_REG_WINDOW_ADDRESS 0x00000078 | ||
424 | #define BNX2_PCICFG_REG_WINDOW 0x00000080 | ||
425 | #define BNX2_PCICFG_INT_ACK_CMD 0x00000084 | ||
426 | #define BNX2_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0) | ||
427 | #define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16) | ||
428 | #define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17) | ||
429 | #define BNX2_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18) | ||
430 | |||
431 | #define BNX2_PCICFG_STATUS_BIT_SET_CMD 0x00000088 | ||
432 | #define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c | ||
433 | #define BNX2_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090 | ||
434 | #define BNX2_PCICFG_MAILBOX_QUEUE_DATA 0x00000094 | ||
435 | |||
436 | |||
437 | /* | ||
438 | * pci_reg definition | ||
439 | * offset: 0x400 | ||
440 | */ | ||
441 | #define BNX2_PCI_GRC_WINDOW_ADDR 0x00000400 | ||
442 | #define BNX2_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE (0x3ffffL<<8) | ||
443 | |||
444 | #define BNX2_PCI_CONFIG_1 0x00000404 | ||
445 | #define BNX2_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8) | ||
446 | #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8) | ||
447 | #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8) | ||
448 | #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8) | ||
449 | #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8) | ||
450 | #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8) | ||
451 | #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8) | ||
452 | #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8) | ||
453 | #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8) | ||
454 | #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY (0x7L<<11) | ||
455 | #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11) | ||
456 | #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11) | ||
457 | #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11) | ||
458 | #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11) | ||
459 | #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11) | ||
460 | #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11) | ||
461 | #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11) | ||
462 | #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11) | ||
463 | |||
464 | #define BNX2_PCI_CONFIG_2 0x00000408 | ||
465 | #define BNX2_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) | ||
466 | #define BNX2_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) | ||
467 | #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) | ||
468 | #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) | ||
469 | #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) | ||
470 | #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) | ||
471 | #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) | ||
472 | #define BNX2_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) | ||
473 | #define BNX2_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) | ||
474 | #define BNX2_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) | ||
475 | #define BNX2_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) | ||
476 | #define BNX2_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) | ||
477 | #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) | ||
478 | #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) | ||
479 | #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) | ||
480 | #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) | ||
481 | #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) | ||
482 | #define BNX2_PCI_CONFIG_2_BAR1_64ENA (1L<<4) | ||
483 | #define BNX2_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) | ||
484 | #define BNX2_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) | ||
485 | #define BNX2_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) | ||
486 | #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) | ||
487 | #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) | ||
488 | #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8) | ||
489 | #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8) | ||
490 | #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8) | ||
491 | #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8) | ||
492 | #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8) | ||
493 | #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8) | ||
494 | #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8) | ||
495 | #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8) | ||
496 | #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8) | ||
497 | #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8) | ||
498 | #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8) | ||
499 | #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8) | ||
500 | #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8) | ||
501 | #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8) | ||
502 | #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8) | ||
503 | #define BNX2_PCI_CONFIG_2_MAX_SPLIT_LIMIT (0x1fL<<16) | ||
504 | #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT (0x3L<<21) | ||
505 | #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21) | ||
506 | #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21) | ||
507 | #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21) | ||
508 | #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21) | ||
509 | #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23) | ||
510 | #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24) | ||
511 | #define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25) | ||
512 | |||
513 | #define BNX2_PCI_CONFIG_3 0x0000040c | ||
514 | #define BNX2_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) | ||
515 | #define BNX2_PCI_CONFIG_3_FORCE_PME (1L<<24) | ||
516 | #define BNX2_PCI_CONFIG_3_PME_STATUS (1L<<25) | ||
517 | #define BNX2_PCI_CONFIG_3_PME_ENABLE (1L<<26) | ||
518 | #define BNX2_PCI_CONFIG_3_PM_STATE (0x3L<<27) | ||
519 | #define BNX2_PCI_CONFIG_3_VAUX_PRESET (1L<<30) | ||
520 | #define BNX2_PCI_CONFIG_3_PCI_POWER (1L<<31) | ||
521 | |||
522 | #define BNX2_PCI_PM_DATA_A 0x00000410 | ||
523 | #define BNX2_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0) | ||
524 | #define BNX2_PCI_PM_DATA_A_PM_DATA_1_PRG (0xffL<<8) | ||
525 | #define BNX2_PCI_PM_DATA_A_PM_DATA_2_PRG (0xffL<<16) | ||
526 | #define BNX2_PCI_PM_DATA_A_PM_DATA_3_PRG (0xffL<<24) | ||
527 | |||
528 | #define BNX2_PCI_PM_DATA_B 0x00000414 | ||
529 | #define BNX2_PCI_PM_DATA_B_PM_DATA_4_PRG (0xffL<<0) | ||
530 | #define BNX2_PCI_PM_DATA_B_PM_DATA_5_PRG (0xffL<<8) | ||
531 | #define BNX2_PCI_PM_DATA_B_PM_DATA_6_PRG (0xffL<<16) | ||
532 | #define BNX2_PCI_PM_DATA_B_PM_DATA_7_PRG (0xffL<<24) | ||
533 | |||
534 | #define BNX2_PCI_SWAP_DIAG0 0x00000418 | ||
535 | #define BNX2_PCI_SWAP_DIAG1 0x0000041c | ||
536 | #define BNX2_PCI_EXP_ROM_ADDR 0x00000420 | ||
537 | #define BNX2_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2) | ||
538 | #define BNX2_PCI_EXP_ROM_ADDR_REQ (1L<<31) | ||
539 | |||
540 | #define BNX2_PCI_EXP_ROM_DATA 0x00000424 | ||
541 | #define BNX2_PCI_VPD_INTF 0x00000428 | ||
542 | #define BNX2_PCI_VPD_INTF_INTF_REQ (1L<<0) | ||
543 | |||
544 | #define BNX2_PCI_VPD_ADDR_FLAG 0x0000042c | ||
545 | #define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2) | ||
546 | #define BNX2_PCI_VPD_ADDR_FLAG_WR (1<<15) | ||
547 | |||
548 | #define BNX2_PCI_VPD_DATA 0x00000430 | ||
549 | #define BNX2_PCI_ID_VAL1 0x00000434 | ||
550 | #define BNX2_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0) | ||
551 | #define BNX2_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16) | ||
552 | |||
553 | #define BNX2_PCI_ID_VAL2 0x00000438 | ||
554 | #define BNX2_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffL<<0) | ||
555 | #define BNX2_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16) | ||
556 | |||
557 | #define BNX2_PCI_ID_VAL3 0x0000043c | ||
558 | #define BNX2_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0) | ||
559 | #define BNX2_PCI_ID_VAL3_REVISION_ID (0xffL<<24) | ||
560 | |||
561 | #define BNX2_PCI_ID_VAL4 0x00000440 | ||
562 | #define BNX2_PCI_ID_VAL4_CAP_ENA (0xfL<<0) | ||
563 | #define BNX2_PCI_ID_VAL4_CAP_ENA_0 (0L<<0) | ||
564 | #define BNX2_PCI_ID_VAL4_CAP_ENA_1 (1L<<0) | ||
565 | #define BNX2_PCI_ID_VAL4_CAP_ENA_2 (2L<<0) | ||
566 | #define BNX2_PCI_ID_VAL4_CAP_ENA_3 (3L<<0) | ||
567 | #define BNX2_PCI_ID_VAL4_CAP_ENA_4 (4L<<0) | ||
568 | #define BNX2_PCI_ID_VAL4_CAP_ENA_5 (5L<<0) | ||
569 | #define BNX2_PCI_ID_VAL4_CAP_ENA_6 (6L<<0) | ||
570 | #define BNX2_PCI_ID_VAL4_CAP_ENA_7 (7L<<0) | ||
571 | #define BNX2_PCI_ID_VAL4_CAP_ENA_8 (8L<<0) | ||
572 | #define BNX2_PCI_ID_VAL4_CAP_ENA_9 (9L<<0) | ||
573 | #define BNX2_PCI_ID_VAL4_CAP_ENA_10 (10L<<0) | ||
574 | #define BNX2_PCI_ID_VAL4_CAP_ENA_11 (11L<<0) | ||
575 | #define BNX2_PCI_ID_VAL4_CAP_ENA_12 (12L<<0) | ||
576 | #define BNX2_PCI_ID_VAL4_CAP_ENA_13 (13L<<0) | ||
577 | #define BNX2_PCI_ID_VAL4_CAP_ENA_14 (14L<<0) | ||
578 | #define BNX2_PCI_ID_VAL4_CAP_ENA_15 (15L<<0) | ||
579 | #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6) | ||
580 | #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6) | ||
581 | #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6) | ||
582 | #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6) | ||
583 | #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6) | ||
584 | #define BNX2_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9) | ||
585 | #define BNX2_PCI_ID_VAL4_MSI_ADVERTIZE (0x7L<<12) | ||
586 | #define BNX2_PCI_ID_VAL4_MSI_ENABLE (1L<<15) | ||
587 | #define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16) | ||
588 | #define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17) | ||
589 | #define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE (0x3L<<21) | ||
590 | #define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE (0x7L<<23) | ||
591 | #define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE (0x7L<<26) | ||
592 | |||
593 | #define BNX2_PCI_ID_VAL5 0x00000444 | ||
594 | #define BNX2_PCI_ID_VAL5_D1_SUPPORT (1L<<0) | ||
595 | #define BNX2_PCI_ID_VAL5_D2_SUPPORT (1L<<1) | ||
596 | #define BNX2_PCI_ID_VAL5_PME_IN_D0 (1L<<2) | ||
597 | #define BNX2_PCI_ID_VAL5_PME_IN_D1 (1L<<3) | ||
598 | #define BNX2_PCI_ID_VAL5_PME_IN_D2 (1L<<4) | ||
599 | #define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5) | ||
600 | |||
601 | #define BNX2_PCI_PCIX_EXTENDED_STATUS 0x00000448 | ||
602 | #define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8) | ||
603 | #define BNX2_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9) | ||
604 | #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfL<<16) | ||
605 | #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffL<<24) | ||
606 | |||
607 | #define BNX2_PCI_ID_VAL6 0x0000044c | ||
608 | #define BNX2_PCI_ID_VAL6_MAX_LAT (0xffL<<0) | ||
609 | #define BNX2_PCI_ID_VAL6_MIN_GNT (0xffL<<8) | ||
610 | #define BNX2_PCI_ID_VAL6_BIST (0xffL<<16) | ||
611 | |||
612 | #define BNX2_PCI_MSI_DATA 0x00000450 | ||
613 | #define BNX2_PCI_MSI_DATA_PCI_MSI_DATA (0xffffL<<0) | ||
614 | |||
615 | #define BNX2_PCI_MSI_ADDR_H 0x00000454 | ||
616 | #define BNX2_PCI_MSI_ADDR_L 0x00000458 | ||
617 | |||
618 | |||
619 | /* | ||
620 | * misc_reg definition | ||
621 | * offset: 0x800 | ||
622 | */ | ||
623 | #define BNX2_MISC_COMMAND 0x00000800 | ||
624 | #define BNX2_MISC_COMMAND_ENABLE_ALL (1L<<0) | ||
625 | #define BNX2_MISC_COMMAND_DISABLE_ALL (1L<<1) | ||
626 | #define BNX2_MISC_COMMAND_CORE_RESET (1L<<4) | ||
627 | #define BNX2_MISC_COMMAND_HARD_RESET (1L<<5) | ||
628 | #define BNX2_MISC_COMMAND_PAR_ERROR (1L<<8) | ||
629 | #define BNX2_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16) | ||
630 | |||
631 | #define BNX2_MISC_CFG 0x00000804 | ||
632 | #define BNX2_MISC_CFG_PCI_GRC_TMOUT (1L<<0) | ||
633 | #define BNX2_MISC_CFG_NVM_WR_EN (0x3L<<1) | ||
634 | #define BNX2_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1) | ||
635 | #define BNX2_MISC_CFG_NVM_WR_EN_PCI (1L<<1) | ||
636 | #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1) | ||
637 | #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1) | ||
638 | #define BNX2_MISC_CFG_BIST_EN (1L<<3) | ||
639 | #define BNX2_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4) | ||
640 | #define BNX2_MISC_CFG_BYPASS_BSCAN (1L<<5) | ||
641 | #define BNX2_MISC_CFG_BYPASS_EJTAG (1L<<6) | ||
642 | #define BNX2_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7) | ||
643 | #define BNX2_MISC_CFG_LEDMODE (0x3L<<8) | ||
644 | #define BNX2_MISC_CFG_LEDMODE_MAC (0L<<8) | ||
645 | #define BNX2_MISC_CFG_LEDMODE_GPHY1 (1L<<8) | ||
646 | #define BNX2_MISC_CFG_LEDMODE_GPHY2 (2L<<8) | ||
647 | |||
648 | #define BNX2_MISC_ID 0x00000808 | ||
649 | #define BNX2_MISC_ID_BOND_ID (0xfL<<0) | ||
650 | #define BNX2_MISC_ID_CHIP_METAL (0xffL<<4) | ||
651 | #define BNX2_MISC_ID_CHIP_REV (0xfL<<12) | ||
652 | #define BNX2_MISC_ID_CHIP_NUM (0xffffL<<16) | ||
653 | |||
654 | #define BNX2_MISC_ENABLE_STATUS_BITS 0x0000080c | ||
655 | #define BNX2_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0) | ||
656 | #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1) | ||
657 | #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2) | ||
658 | #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3) | ||
659 | #define BNX2_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4) | ||
660 | #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5) | ||
661 | #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) | ||
662 | #define BNX2_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7) | ||
663 | #define BNX2_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8) | ||
664 | #define BNX2_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9) | ||
665 | #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10) | ||
666 | #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) | ||
667 | #define BNX2_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12) | ||
668 | #define BNX2_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13) | ||
669 | #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14) | ||
670 | #define BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15) | ||
671 | #define BNX2_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16) | ||
672 | #define BNX2_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17) | ||
673 | #define BNX2_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18) | ||
674 | #define BNX2_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19) | ||
675 | #define BNX2_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) | ||
676 | #define BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21) | ||
677 | #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22) | ||
678 | #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23) | ||
679 | #define BNX2_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) | ||
680 | #define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25) | ||
681 | #define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26) | ||
682 | #define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27) | ||
683 | |||
684 | #define BNX2_MISC_ENABLE_SET_BITS 0x00000810 | ||
685 | #define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0) | ||
686 | #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1) | ||
687 | #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2) | ||
688 | #define BNX2_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3) | ||
689 | #define BNX2_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4) | ||
690 | #define BNX2_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5) | ||
691 | #define BNX2_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) | ||
692 | #define BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7) | ||
693 | #define BNX2_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8) | ||
694 | #define BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9) | ||
695 | #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10) | ||
696 | #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) | ||
697 | #define BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12) | ||
698 | #define BNX2_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13) | ||
699 | #define BNX2_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14) | ||
700 | #define BNX2_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15) | ||
701 | #define BNX2_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16) | ||
702 | #define BNX2_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17) | ||
703 | #define BNX2_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18) | ||
704 | #define BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19) | ||
705 | #define BNX2_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) | ||
706 | #define BNX2_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21) | ||
707 | #define BNX2_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22) | ||
708 | #define BNX2_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23) | ||
709 | #define BNX2_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) | ||
710 | #define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25) | ||
711 | #define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26) | ||
712 | #define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27) | ||
713 | |||
714 | #define BNX2_MISC_ENABLE_CLR_BITS 0x00000814 | ||
715 | #define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0) | ||
716 | #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1) | ||
717 | #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2) | ||
718 | #define BNX2_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3) | ||
719 | #define BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4) | ||
720 | #define BNX2_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5) | ||
721 | #define BNX2_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) | ||
722 | #define BNX2_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7) | ||
723 | #define BNX2_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8) | ||
724 | #define BNX2_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9) | ||
725 | #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10) | ||
726 | #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) | ||
727 | #define BNX2_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12) | ||
728 | #define BNX2_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13) | ||
729 | #define BNX2_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14) | ||
730 | #define BNX2_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15) | ||
731 | #define BNX2_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16) | ||
732 | #define BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17) | ||
733 | #define BNX2_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18) | ||
734 | #define BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19) | ||
735 | #define BNX2_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) | ||
736 | #define BNX2_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21) | ||
737 | #define BNX2_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22) | ||
738 | #define BNX2_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23) | ||
739 | #define BNX2_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) | ||
740 | #define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25) | ||
741 | #define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26) | ||
742 | #define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27) | ||
743 | |||
744 | #define BNX2_MISC_CLOCK_CONTROL_BITS 0x00000818 | ||
745 | #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) | ||
746 | #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) | ||
747 | #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) | ||
748 | #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) | ||
749 | #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) | ||
750 | #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) | ||
751 | #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) | ||
752 | #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) | ||
753 | #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) | ||
754 | #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) | ||
755 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) | ||
756 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) | ||
757 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) | ||
758 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) | ||
759 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) | ||
760 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) | ||
761 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) | ||
762 | #define BNX2_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) | ||
763 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) | ||
764 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) | ||
765 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) | ||
766 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) | ||
767 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) | ||
768 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) | ||
769 | #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) | ||
770 | #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) | ||
771 | #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) | ||
772 | #define BNX2_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) | ||
773 | #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) | ||
774 | |||
775 | #define BNX2_MISC_GPIO 0x0000081c | ||
776 | #define BNX2_MISC_GPIO_VALUE (0xffL<<0) | ||
777 | #define BNX2_MISC_GPIO_SET (0xffL<<8) | ||
778 | #define BNX2_MISC_GPIO_CLR (0xffL<<16) | ||
779 | #define BNX2_MISC_GPIO_FLOAT (0xffL<<24) | ||
780 | |||
781 | #define BNX2_MISC_GPIO_INT 0x00000820 | ||
782 | #define BNX2_MISC_GPIO_INT_INT_STATE (0xfL<<0) | ||
783 | #define BNX2_MISC_GPIO_INT_OLD_VALUE (0xfL<<8) | ||
784 | #define BNX2_MISC_GPIO_INT_OLD_SET (0xfL<<16) | ||
785 | #define BNX2_MISC_GPIO_INT_OLD_CLR (0xfL<<24) | ||
786 | |||
787 | #define BNX2_MISC_CONFIG_LFSR 0x00000824 | ||
788 | #define BNX2_MISC_CONFIG_LFSR_DIV (0xffffL<<0) | ||
789 | |||
790 | #define BNX2_MISC_LFSR_MASK_BITS 0x00000828 | ||
791 | #define BNX2_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0) | ||
792 | #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1) | ||
793 | #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2) | ||
794 | #define BNX2_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3) | ||
795 | #define BNX2_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4) | ||
796 | #define BNX2_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5) | ||
797 | #define BNX2_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) | ||
798 | #define BNX2_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7) | ||
799 | #define BNX2_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8) | ||
800 | #define BNX2_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9) | ||
801 | #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10) | ||
802 | #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) | ||
803 | #define BNX2_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12) | ||
804 | #define BNX2_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13) | ||
805 | #define BNX2_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14) | ||
806 | #define BNX2_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15) | ||
807 | #define BNX2_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16) | ||
808 | #define BNX2_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17) | ||
809 | #define BNX2_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18) | ||
810 | #define BNX2_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19) | ||
811 | #define BNX2_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) | ||
812 | #define BNX2_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21) | ||
813 | #define BNX2_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22) | ||
814 | #define BNX2_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23) | ||
815 | #define BNX2_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) | ||
816 | #define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25) | ||
817 | #define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26) | ||
818 | #define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27) | ||
819 | |||
820 | #define BNX2_MISC_ARB_REQ0 0x0000082c | ||
821 | #define BNX2_MISC_ARB_REQ1 0x00000830 | ||
822 | #define BNX2_MISC_ARB_REQ2 0x00000834 | ||
823 | #define BNX2_MISC_ARB_REQ3 0x00000838 | ||
824 | #define BNX2_MISC_ARB_REQ4 0x0000083c | ||
825 | #define BNX2_MISC_ARB_FREE0 0x00000840 | ||
826 | #define BNX2_MISC_ARB_FREE1 0x00000844 | ||
827 | #define BNX2_MISC_ARB_FREE2 0x00000848 | ||
828 | #define BNX2_MISC_ARB_FREE3 0x0000084c | ||
829 | #define BNX2_MISC_ARB_FREE4 0x00000850 | ||
830 | #define BNX2_MISC_ARB_REQ_STATUS0 0x00000854 | ||
831 | #define BNX2_MISC_ARB_REQ_STATUS1 0x00000858 | ||
832 | #define BNX2_MISC_ARB_REQ_STATUS2 0x0000085c | ||
833 | #define BNX2_MISC_ARB_REQ_STATUS3 0x00000860 | ||
834 | #define BNX2_MISC_ARB_REQ_STATUS4 0x00000864 | ||
835 | #define BNX2_MISC_ARB_GNT0 0x00000868 | ||
836 | #define BNX2_MISC_ARB_GNT0_0 (0x7L<<0) | ||
837 | #define BNX2_MISC_ARB_GNT0_1 (0x7L<<4) | ||
838 | #define BNX2_MISC_ARB_GNT0_2 (0x7L<<8) | ||
839 | #define BNX2_MISC_ARB_GNT0_3 (0x7L<<12) | ||
840 | #define BNX2_MISC_ARB_GNT0_4 (0x7L<<16) | ||
841 | #define BNX2_MISC_ARB_GNT0_5 (0x7L<<20) | ||
842 | #define BNX2_MISC_ARB_GNT0_6 (0x7L<<24) | ||
843 | #define BNX2_MISC_ARB_GNT0_7 (0x7L<<28) | ||
844 | |||
845 | #define BNX2_MISC_ARB_GNT1 0x0000086c | ||
846 | #define BNX2_MISC_ARB_GNT1_8 (0x7L<<0) | ||
847 | #define BNX2_MISC_ARB_GNT1_9 (0x7L<<4) | ||
848 | #define BNX2_MISC_ARB_GNT1_10 (0x7L<<8) | ||
849 | #define BNX2_MISC_ARB_GNT1_11 (0x7L<<12) | ||
850 | #define BNX2_MISC_ARB_GNT1_12 (0x7L<<16) | ||
851 | #define BNX2_MISC_ARB_GNT1_13 (0x7L<<20) | ||
852 | #define BNX2_MISC_ARB_GNT1_14 (0x7L<<24) | ||
853 | #define BNX2_MISC_ARB_GNT1_15 (0x7L<<28) | ||
854 | |||
855 | #define BNX2_MISC_ARB_GNT2 0x00000870 | ||
856 | #define BNX2_MISC_ARB_GNT2_16 (0x7L<<0) | ||
857 | #define BNX2_MISC_ARB_GNT2_17 (0x7L<<4) | ||
858 | #define BNX2_MISC_ARB_GNT2_18 (0x7L<<8) | ||
859 | #define BNX2_MISC_ARB_GNT2_19 (0x7L<<12) | ||
860 | #define BNX2_MISC_ARB_GNT2_20 (0x7L<<16) | ||
861 | #define BNX2_MISC_ARB_GNT2_21 (0x7L<<20) | ||
862 | #define BNX2_MISC_ARB_GNT2_22 (0x7L<<24) | ||
863 | #define BNX2_MISC_ARB_GNT2_23 (0x7L<<28) | ||
864 | |||
865 | #define BNX2_MISC_ARB_GNT3 0x00000874 | ||
866 | #define BNX2_MISC_ARB_GNT3_24 (0x7L<<0) | ||
867 | #define BNX2_MISC_ARB_GNT3_25 (0x7L<<4) | ||
868 | #define BNX2_MISC_ARB_GNT3_26 (0x7L<<8) | ||
869 | #define BNX2_MISC_ARB_GNT3_27 (0x7L<<12) | ||
870 | #define BNX2_MISC_ARB_GNT3_28 (0x7L<<16) | ||
871 | #define BNX2_MISC_ARB_GNT3_29 (0x7L<<20) | ||
872 | #define BNX2_MISC_ARB_GNT3_30 (0x7L<<24) | ||
873 | #define BNX2_MISC_ARB_GNT3_31 (0x7L<<28) | ||
874 | |||
875 | #define BNX2_MISC_PRBS_CONTROL 0x00000878 | ||
876 | #define BNX2_MISC_PRBS_CONTROL_EN (1L<<0) | ||
877 | #define BNX2_MISC_PRBS_CONTROL_RSTB (1L<<1) | ||
878 | #define BNX2_MISC_PRBS_CONTROL_INV (1L<<2) | ||
879 | #define BNX2_MISC_PRBS_CONTROL_ERR_CLR (1L<<3) | ||
880 | #define BNX2_MISC_PRBS_CONTROL_ORDER (0x3L<<4) | ||
881 | #define BNX2_MISC_PRBS_CONTROL_ORDER_7TH (0L<<4) | ||
882 | #define BNX2_MISC_PRBS_CONTROL_ORDER_15TH (1L<<4) | ||
883 | #define BNX2_MISC_PRBS_CONTROL_ORDER_23RD (2L<<4) | ||
884 | #define BNX2_MISC_PRBS_CONTROL_ORDER_31ST (3L<<4) | ||
885 | |||
886 | #define BNX2_MISC_PRBS_STATUS 0x0000087c | ||
887 | #define BNX2_MISC_PRBS_STATUS_LOCK (1L<<0) | ||
888 | #define BNX2_MISC_PRBS_STATUS_STKY (1L<<1) | ||
889 | #define BNX2_MISC_PRBS_STATUS_ERRORS (0x3fffL<<2) | ||
890 | #define BNX2_MISC_PRBS_STATUS_STATE (0xfL<<16) | ||
891 | |||
892 | #define BNX2_MISC_SM_ASF_CONTROL 0x00000880 | ||
893 | #define BNX2_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0) | ||
894 | #define BNX2_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1) | ||
895 | #define BNX2_MISC_SM_ASF_CONTROL_WG_TO (1L<<2) | ||
896 | #define BNX2_MISC_SM_ASF_CONTROL_HB_TO (1L<<3) | ||
897 | #define BNX2_MISC_SM_ASF_CONTROL_PA_TO (1L<<4) | ||
898 | #define BNX2_MISC_SM_ASF_CONTROL_PL_TO (1L<<5) | ||
899 | #define BNX2_MISC_SM_ASF_CONTROL_RT_TO (1L<<6) | ||
900 | #define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7) | ||
901 | #define BNX2_MISC_SM_ASF_CONTROL_RES (0xfL<<8) | ||
902 | #define BNX2_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12) | ||
903 | #define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13) | ||
904 | #define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14) | ||
905 | #define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15) | ||
906 | #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x3fL<<16) | ||
907 | #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x3fL<<24) | ||
908 | #define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30) | ||
909 | #define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31) | ||
910 | |||
911 | #define BNX2_MISC_SMB_IN 0x00000884 | ||
912 | #define BNX2_MISC_SMB_IN_DAT_IN (0xffL<<0) | ||
913 | #define BNX2_MISC_SMB_IN_RDY (1L<<8) | ||
914 | #define BNX2_MISC_SMB_IN_DONE (1L<<9) | ||
915 | #define BNX2_MISC_SMB_IN_FIRSTBYTE (1L<<10) | ||
916 | #define BNX2_MISC_SMB_IN_STATUS (0x7L<<11) | ||
917 | #define BNX2_MISC_SMB_IN_STATUS_OK (0x0L<<11) | ||
918 | #define BNX2_MISC_SMB_IN_STATUS_PEC (0x1L<<11) | ||
919 | #define BNX2_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11) | ||
920 | #define BNX2_MISC_SMB_IN_STATUS_STOP (0x3L<<11) | ||
921 | #define BNX2_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11) | ||
922 | |||
923 | #define BNX2_MISC_SMB_OUT 0x00000888 | ||
924 | #define BNX2_MISC_SMB_OUT_DAT_OUT (0xffL<<0) | ||
925 | #define BNX2_MISC_SMB_OUT_RDY (1L<<8) | ||
926 | #define BNX2_MISC_SMB_OUT_START (1L<<9) | ||
927 | #define BNX2_MISC_SMB_OUT_LAST (1L<<10) | ||
928 | #define BNX2_MISC_SMB_OUT_ACC_TYPE (1L<<11) | ||
929 | #define BNX2_MISC_SMB_OUT_ENB_PEC (1L<<12) | ||
930 | #define BNX2_MISC_SMB_OUT_GET_RX_LEN (1L<<13) | ||
931 | #define BNX2_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14) | ||
932 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20) | ||
933 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20) | ||
934 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20) | ||
935 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20) | ||
936 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20) | ||
937 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20) | ||
938 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20) | ||
939 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20) | ||
940 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20) | ||
941 | #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (0x6L<<20) | ||
942 | #define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24) | ||
943 | #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25) | ||
944 | #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26) | ||
945 | #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27) | ||
946 | #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28) | ||
947 | |||
948 | #define BNX2_MISC_SMB_WATCHDOG 0x0000088c | ||
949 | #define BNX2_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0) | ||
950 | |||
951 | #define BNX2_MISC_SMB_HEARTBEAT 0x00000890 | ||
952 | #define BNX2_MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffL<<0) | ||
953 | |||
954 | #define BNX2_MISC_SMB_POLL_ASF 0x00000894 | ||
955 | #define BNX2_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0) | ||
956 | |||
957 | #define BNX2_MISC_SMB_POLL_LEGACY 0x00000898 | ||
958 | #define BNX2_MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffL<<0) | ||
959 | |||
960 | #define BNX2_MISC_SMB_RETRAN 0x0000089c | ||
961 | #define BNX2_MISC_SMB_RETRAN_RETRAN (0xffL<<0) | ||
962 | |||
963 | #define BNX2_MISC_SMB_TIMESTAMP 0x000008a0 | ||
964 | #define BNX2_MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffL<<0) | ||
965 | |||
966 | #define BNX2_MISC_PERR_ENA0 0x000008a4 | ||
967 | #define BNX2_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0) | ||
968 | #define BNX2_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1) | ||
969 | #define BNX2_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2) | ||
970 | #define BNX2_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3) | ||
971 | #define BNX2_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4) | ||
972 | #define BNX2_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5) | ||
973 | #define BNX2_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6) | ||
974 | #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7) | ||
975 | #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8) | ||
976 | #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9) | ||
977 | #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10) | ||
978 | #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11) | ||
979 | #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12) | ||
980 | #define BNX2_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13) | ||
981 | #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14) | ||
982 | #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15) | ||
983 | #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16) | ||
984 | #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17) | ||
985 | #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18) | ||
986 | #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19) | ||
987 | #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20) | ||
988 | #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21) | ||
989 | #define BNX2_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22) | ||
990 | #define BNX2_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23) | ||
991 | #define BNX2_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24) | ||
992 | #define BNX2_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25) | ||
993 | #define BNX2_MISC_PERR_ENA0_RBDC_MISC (1L<<26) | ||
994 | #define BNX2_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27) | ||
995 | #define BNX2_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28) | ||
996 | #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29) | ||
997 | #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30) | ||
998 | #define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31) | ||
999 | |||
1000 | #define BNX2_MISC_PERR_ENA1 0x000008a8 | ||
1001 | #define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0) | ||
1002 | #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1) | ||
1003 | #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2) | ||
1004 | #define BNX2_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3) | ||
1005 | #define BNX2_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4) | ||
1006 | #define BNX2_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5) | ||
1007 | #define BNX2_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6) | ||
1008 | #define BNX2_MISC_PERR_ENA1_TBDC_MISC (1L<<7) | ||
1009 | #define BNX2_MISC_PERR_ENA1_TDMA_MISC (1L<<8) | ||
1010 | #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9) | ||
1011 | #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10) | ||
1012 | #define BNX2_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11) | ||
1013 | #define BNX2_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12) | ||
1014 | #define BNX2_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13) | ||
1015 | #define BNX2_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14) | ||
1016 | #define BNX2_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15) | ||
1017 | #define BNX2_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16) | ||
1018 | #define BNX2_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17) | ||
1019 | #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18) | ||
1020 | #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19) | ||
1021 | #define BNX2_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20) | ||
1022 | #define BNX2_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21) | ||
1023 | #define BNX2_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22) | ||
1024 | #define BNX2_MISC_PERR_ENA1_CSQ_MISC (1L<<23) | ||
1025 | #define BNX2_MISC_PERR_ENA1_CPQ_MISC (1L<<24) | ||
1026 | #define BNX2_MISC_PERR_ENA1_MCPQ_MISC (1L<<25) | ||
1027 | #define BNX2_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26) | ||
1028 | #define BNX2_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27) | ||
1029 | #define BNX2_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28) | ||
1030 | #define BNX2_MISC_PERR_ENA1_RXPQ_MISC (1L<<29) | ||
1031 | #define BNX2_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30) | ||
1032 | #define BNX2_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31) | ||
1033 | |||
1034 | #define BNX2_MISC_PERR_ENA2 0x000008ac | ||
1035 | #define BNX2_MISC_PERR_ENA2_COMQ_MISC (1L<<0) | ||
1036 | #define BNX2_MISC_PERR_ENA2_COMXQ_MISC (1L<<1) | ||
1037 | #define BNX2_MISC_PERR_ENA2_COMTQ_MISC (1L<<2) | ||
1038 | #define BNX2_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3) | ||
1039 | #define BNX2_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4) | ||
1040 | #define BNX2_MISC_PERR_ENA2_TXPQ_MISC (1L<<5) | ||
1041 | #define BNX2_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6) | ||
1042 | #define BNX2_MISC_PERR_ENA2_TPATQ_MISC (1L<<7) | ||
1043 | #define BNX2_MISC_PERR_ENA2_TASQ_MISC (1L<<8) | ||
1044 | |||
1045 | #define BNX2_MISC_DEBUG_VECTOR_SEL 0x000008b0 | ||
1046 | #define BNX2_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0) | ||
1047 | #define BNX2_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12) | ||
1048 | |||
1049 | #define BNX2_MISC_VREG_CONTROL 0x000008b4 | ||
1050 | #define BNX2_MISC_VREG_CONTROL_1_2 (0xfL<<0) | ||
1051 | #define BNX2_MISC_VREG_CONTROL_2_5 (0xfL<<4) | ||
1052 | |||
1053 | #define BNX2_MISC_FINAL_CLK_CTL_VAL 0x000008b8 | ||
1054 | #define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6) | ||
1055 | |||
1056 | #define BNX2_MISC_UNUSED0 0x000008bc | ||
1057 | |||
1058 | |||
1059 | /* | ||
1060 | * nvm_reg definition | ||
1061 | * offset: 0x6400 | ||
1062 | */ | ||
1063 | #define BNX2_NVM_COMMAND 0x00006400 | ||
1064 | #define BNX2_NVM_COMMAND_RST (1L<<0) | ||
1065 | #define BNX2_NVM_COMMAND_DONE (1L<<3) | ||
1066 | #define BNX2_NVM_COMMAND_DOIT (1L<<4) | ||
1067 | #define BNX2_NVM_COMMAND_WR (1L<<5) | ||
1068 | #define BNX2_NVM_COMMAND_ERASE (1L<<6) | ||
1069 | #define BNX2_NVM_COMMAND_FIRST (1L<<7) | ||
1070 | #define BNX2_NVM_COMMAND_LAST (1L<<8) | ||
1071 | #define BNX2_NVM_COMMAND_WREN (1L<<16) | ||
1072 | #define BNX2_NVM_COMMAND_WRDI (1L<<17) | ||
1073 | #define BNX2_NVM_COMMAND_EWSR (1L<<18) | ||
1074 | #define BNX2_NVM_COMMAND_WRSR (1L<<19) | ||
1075 | |||
1076 | #define BNX2_NVM_STATUS 0x00006404 | ||
1077 | #define BNX2_NVM_STATUS_PI_FSM_STATE (0xfL<<0) | ||
1078 | #define BNX2_NVM_STATUS_EE_FSM_STATE (0xfL<<4) | ||
1079 | #define BNX2_NVM_STATUS_EQ_FSM_STATE (0xfL<<8) | ||
1080 | |||
1081 | #define BNX2_NVM_WRITE 0x00006408 | ||
1082 | #define BNX2_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0) | ||
1083 | #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0) | ||
1084 | #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0) | ||
1085 | #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0) | ||
1086 | #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0) | ||
1087 | #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0) | ||
1088 | #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0) | ||
1089 | #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0) | ||
1090 | |||
1091 | #define BNX2_NVM_ADDR 0x0000640c | ||
1092 | #define BNX2_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) | ||
1093 | #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0) | ||
1094 | #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0) | ||
1095 | #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0) | ||
1096 | #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0) | ||
1097 | #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0) | ||
1098 | #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0) | ||
1099 | #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0) | ||
1100 | |||
1101 | #define BNX2_NVM_READ 0x00006410 | ||
1102 | #define BNX2_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0) | ||
1103 | #define BNX2_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0) | ||
1104 | #define BNX2_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0) | ||
1105 | #define BNX2_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0) | ||
1106 | #define BNX2_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0) | ||
1107 | #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0) | ||
1108 | #define BNX2_NVM_READ_NVM_READ_VALUE_SO (16L<<0) | ||
1109 | #define BNX2_NVM_READ_NVM_READ_VALUE_SI (32L<<0) | ||
1110 | |||
1111 | #define BNX2_NVM_CFG1 0x00006414 | ||
1112 | #define BNX2_NVM_CFG1_FLASH_MODE (1L<<0) | ||
1113 | #define BNX2_NVM_CFG1_BUFFER_MODE (1L<<1) | ||
1114 | #define BNX2_NVM_CFG1_PASS_MODE (1L<<2) | ||
1115 | #define BNX2_NVM_CFG1_BITBANG_MODE (1L<<3) | ||
1116 | #define BNX2_NVM_CFG1_STATUS_BIT (0x7L<<4) | ||
1117 | #define BNX2_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4) | ||
1118 | #define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4) | ||
1119 | #define BNX2_NVM_CFG1_SPI_CLK_DIV (0xfL<<7) | ||
1120 | #define BNX2_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11) | ||
1121 | #define BNX2_NVM_CFG1_PROTECT_MODE (1L<<24) | ||
1122 | #define BNX2_NVM_CFG1_FLASH_SIZE (1L<<25) | ||
1123 | #define BNX2_NVM_CFG1_COMPAT_BYPASSS (1L<<31) | ||
1124 | |||
1125 | #define BNX2_NVM_CFG2 0x00006418 | ||
1126 | #define BNX2_NVM_CFG2_ERASE_CMD (0xffL<<0) | ||
1127 | #define BNX2_NVM_CFG2_DUMMY (0xffL<<8) | ||
1128 | #define BNX2_NVM_CFG2_STATUS_CMD (0xffL<<16) | ||
1129 | |||
1130 | #define BNX2_NVM_CFG3 0x0000641c | ||
1131 | #define BNX2_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0) | ||
1132 | #define BNX2_NVM_CFG3_WRITE_CMD (0xffL<<8) | ||
1133 | #define BNX2_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16) | ||
1134 | #define BNX2_NVM_CFG3_READ_CMD (0xffL<<24) | ||
1135 | |||
1136 | #define BNX2_NVM_SW_ARB 0x00006420 | ||
1137 | #define BNX2_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0) | ||
1138 | #define BNX2_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1) | ||
1139 | #define BNX2_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2) | ||
1140 | #define BNX2_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3) | ||
1141 | #define BNX2_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4) | ||
1142 | #define BNX2_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5) | ||
1143 | #define BNX2_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6) | ||
1144 | #define BNX2_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7) | ||
1145 | #define BNX2_NVM_SW_ARB_ARB_ARB0 (1L<<8) | ||
1146 | #define BNX2_NVM_SW_ARB_ARB_ARB1 (1L<<9) | ||
1147 | #define BNX2_NVM_SW_ARB_ARB_ARB2 (1L<<10) | ||
1148 | #define BNX2_NVM_SW_ARB_ARB_ARB3 (1L<<11) | ||
1149 | #define BNX2_NVM_SW_ARB_REQ0 (1L<<12) | ||
1150 | #define BNX2_NVM_SW_ARB_REQ1 (1L<<13) | ||
1151 | #define BNX2_NVM_SW_ARB_REQ2 (1L<<14) | ||
1152 | #define BNX2_NVM_SW_ARB_REQ3 (1L<<15) | ||
1153 | |||
1154 | #define BNX2_NVM_ACCESS_ENABLE 0x00006424 | ||
1155 | #define BNX2_NVM_ACCESS_ENABLE_EN (1L<<0) | ||
1156 | #define BNX2_NVM_ACCESS_ENABLE_WR_EN (1L<<1) | ||
1157 | |||
1158 | #define BNX2_NVM_WRITE1 0x00006428 | ||
1159 | #define BNX2_NVM_WRITE1_WREN_CMD (0xffL<<0) | ||
1160 | #define BNX2_NVM_WRITE1_WRDI_CMD (0xffL<<8) | ||
1161 | #define BNX2_NVM_WRITE1_SR_DATA (0xffL<<16) | ||
1162 | |||
1163 | |||
1164 | |||
1165 | /* | ||
1166 | * dma_reg definition | ||
1167 | * offset: 0xc00 | ||
1168 | */ | ||
1169 | #define BNX2_DMA_COMMAND 0x00000c00 | ||
1170 | #define BNX2_DMA_COMMAND_ENABLE (1L<<0) | ||
1171 | |||
1172 | #define BNX2_DMA_STATUS 0x00000c04 | ||
1173 | #define BNX2_DMA_STATUS_PAR_ERROR_STATE (1L<<0) | ||
1174 | #define BNX2_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16) | ||
1175 | #define BNX2_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17) | ||
1176 | #define BNX2_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18) | ||
1177 | #define BNX2_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19) | ||
1178 | #define BNX2_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20) | ||
1179 | #define BNX2_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21) | ||
1180 | #define BNX2_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22) | ||
1181 | #define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23) | ||
1182 | #define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24) | ||
1183 | #define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25) | ||
1184 | |||
1185 | #define BNX2_DMA_CONFIG 0x00000c08 | ||
1186 | #define BNX2_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0) | ||
1187 | #define BNX2_DMA_CONFIG_DATA_WORD_SWAP (1L<<1) | ||
1188 | #define BNX2_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4) | ||
1189 | #define BNX2_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5) | ||
1190 | #define BNX2_DMA_CONFIG_ONE_DMA (1L<<6) | ||
1191 | #define BNX2_DMA_CONFIG_CNTL_TWO_DMA (1L<<7) | ||
1192 | #define BNX2_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8) | ||
1193 | #define BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10) | ||
1194 | #define BNX2_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11) | ||
1195 | #define BNX2_DMA_CONFIG_NO_RCHANS_IN_USE (0xfL<<12) | ||
1196 | #define BNX2_DMA_CONFIG_NO_WCHANS_IN_USE (0xfL<<16) | ||
1197 | #define BNX2_DMA_CONFIG_PCI_CLK_CMP_BITS (0x7L<<20) | ||
1198 | #define BNX2_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23) | ||
1199 | #define BNX2_DMA_CONFIG_BIG_SIZE (0xfL<<24) | ||
1200 | #define BNX2_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24) | ||
1201 | #define BNX2_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24) | ||
1202 | #define BNX2_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24) | ||
1203 | #define BNX2_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24) | ||
1204 | #define BNX2_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24) | ||
1205 | |||
1206 | #define BNX2_DMA_BLACKOUT 0x00000c0c | ||
1207 | #define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0) | ||
1208 | #define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8) | ||
1209 | #define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16) | ||
1210 | |||
1211 | #define BNX2_DMA_RCHAN_STAT 0x00000c30 | ||
1212 | #define BNX2_DMA_RCHAN_STAT_COMP_CODE_0 (0x7L<<0) | ||
1213 | #define BNX2_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3) | ||
1214 | #define BNX2_DMA_RCHAN_STAT_COMP_CODE_1 (0x7L<<4) | ||
1215 | #define BNX2_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7) | ||
1216 | #define BNX2_DMA_RCHAN_STAT_COMP_CODE_2 (0x7L<<8) | ||
1217 | #define BNX2_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11) | ||
1218 | #define BNX2_DMA_RCHAN_STAT_COMP_CODE_3 (0x7L<<12) | ||
1219 | #define BNX2_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15) | ||
1220 | #define BNX2_DMA_RCHAN_STAT_COMP_CODE_4 (0x7L<<16) | ||
1221 | #define BNX2_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19) | ||
1222 | #define BNX2_DMA_RCHAN_STAT_COMP_CODE_5 (0x7L<<20) | ||
1223 | #define BNX2_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23) | ||
1224 | #define BNX2_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24) | ||
1225 | #define BNX2_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27) | ||
1226 | #define BNX2_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28) | ||
1227 | #define BNX2_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31) | ||
1228 | |||
1229 | #define BNX2_DMA_WCHAN_STAT 0x00000c34 | ||
1230 | #define BNX2_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0) | ||
1231 | #define BNX2_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3) | ||
1232 | #define BNX2_DMA_WCHAN_STAT_COMP_CODE_1 (0x7L<<4) | ||
1233 | #define BNX2_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7) | ||
1234 | #define BNX2_DMA_WCHAN_STAT_COMP_CODE_2 (0x7L<<8) | ||
1235 | #define BNX2_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11) | ||
1236 | #define BNX2_DMA_WCHAN_STAT_COMP_CODE_3 (0x7L<<12) | ||
1237 | #define BNX2_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15) | ||
1238 | #define BNX2_DMA_WCHAN_STAT_COMP_CODE_4 (0x7L<<16) | ||
1239 | #define BNX2_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19) | ||
1240 | #define BNX2_DMA_WCHAN_STAT_COMP_CODE_5 (0x7L<<20) | ||
1241 | #define BNX2_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23) | ||
1242 | #define BNX2_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24) | ||
1243 | #define BNX2_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27) | ||
1244 | #define BNX2_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28) | ||
1245 | #define BNX2_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31) | ||
1246 | |||
1247 | #define BNX2_DMA_RCHAN_ASSIGNMENT 0x00000c38 | ||
1248 | #define BNX2_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0) | ||
1249 | #define BNX2_DMA_RCHAN_ASSIGNMENT_1 (0xfL<<4) | ||
1250 | #define BNX2_DMA_RCHAN_ASSIGNMENT_2 (0xfL<<8) | ||
1251 | #define BNX2_DMA_RCHAN_ASSIGNMENT_3 (0xfL<<12) | ||
1252 | #define BNX2_DMA_RCHAN_ASSIGNMENT_4 (0xfL<<16) | ||
1253 | #define BNX2_DMA_RCHAN_ASSIGNMENT_5 (0xfL<<20) | ||
1254 | #define BNX2_DMA_RCHAN_ASSIGNMENT_6 (0xfL<<24) | ||
1255 | #define BNX2_DMA_RCHAN_ASSIGNMENT_7 (0xfL<<28) | ||
1256 | |||
1257 | #define BNX2_DMA_WCHAN_ASSIGNMENT 0x00000c3c | ||
1258 | #define BNX2_DMA_WCHAN_ASSIGNMENT_0 (0xfL<<0) | ||
1259 | #define BNX2_DMA_WCHAN_ASSIGNMENT_1 (0xfL<<4) | ||
1260 | #define BNX2_DMA_WCHAN_ASSIGNMENT_2 (0xfL<<8) | ||
1261 | #define BNX2_DMA_WCHAN_ASSIGNMENT_3 (0xfL<<12) | ||
1262 | #define BNX2_DMA_WCHAN_ASSIGNMENT_4 (0xfL<<16) | ||
1263 | #define BNX2_DMA_WCHAN_ASSIGNMENT_5 (0xfL<<20) | ||
1264 | #define BNX2_DMA_WCHAN_ASSIGNMENT_6 (0xfL<<24) | ||
1265 | #define BNX2_DMA_WCHAN_ASSIGNMENT_7 (0xfL<<28) | ||
1266 | |||
1267 | #define BNX2_DMA_RCHAN_STAT_00 0x00000c40 | ||
1268 | #define BNX2_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) | ||
1269 | |||
1270 | #define BNX2_DMA_RCHAN_STAT_01 0x00000c44 | ||
1271 | #define BNX2_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) | ||
1272 | |||
1273 | #define BNX2_DMA_RCHAN_STAT_02 0x00000c48 | ||
1274 | #define BNX2_DMA_RCHAN_STAT_02_LENGTH (0xffffL<<0) | ||
1275 | #define BNX2_DMA_RCHAN_STAT_02_WORD_SWAP (1L<<16) | ||
1276 | #define BNX2_DMA_RCHAN_STAT_02_BYTE_SWAP (1L<<17) | ||
1277 | #define BNX2_DMA_RCHAN_STAT_02_PRIORITY_LVL (1L<<18) | ||
1278 | |||
1279 | #define BNX2_DMA_RCHAN_STAT_10 0x00000c4c | ||
1280 | #define BNX2_DMA_RCHAN_STAT_11 0x00000c50 | ||
1281 | #define BNX2_DMA_RCHAN_STAT_12 0x00000c54 | ||
1282 | #define BNX2_DMA_RCHAN_STAT_20 0x00000c58 | ||
1283 | #define BNX2_DMA_RCHAN_STAT_21 0x00000c5c | ||
1284 | #define BNX2_DMA_RCHAN_STAT_22 0x00000c60 | ||
1285 | #define BNX2_DMA_RCHAN_STAT_30 0x00000c64 | ||
1286 | #define BNX2_DMA_RCHAN_STAT_31 0x00000c68 | ||
1287 | #define BNX2_DMA_RCHAN_STAT_32 0x00000c6c | ||
1288 | #define BNX2_DMA_RCHAN_STAT_40 0x00000c70 | ||
1289 | #define BNX2_DMA_RCHAN_STAT_41 0x00000c74 | ||
1290 | #define BNX2_DMA_RCHAN_STAT_42 0x00000c78 | ||
1291 | #define BNX2_DMA_RCHAN_STAT_50 0x00000c7c | ||
1292 | #define BNX2_DMA_RCHAN_STAT_51 0x00000c80 | ||
1293 | #define BNX2_DMA_RCHAN_STAT_52 0x00000c84 | ||
1294 | #define BNX2_DMA_RCHAN_STAT_60 0x00000c88 | ||
1295 | #define BNX2_DMA_RCHAN_STAT_61 0x00000c8c | ||
1296 | #define BNX2_DMA_RCHAN_STAT_62 0x00000c90 | ||
1297 | #define BNX2_DMA_RCHAN_STAT_70 0x00000c94 | ||
1298 | #define BNX2_DMA_RCHAN_STAT_71 0x00000c98 | ||
1299 | #define BNX2_DMA_RCHAN_STAT_72 0x00000c9c | ||
1300 | #define BNX2_DMA_WCHAN_STAT_00 0x00000ca0 | ||
1301 | #define BNX2_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) | ||
1302 | |||
1303 | #define BNX2_DMA_WCHAN_STAT_01 0x00000ca4 | ||
1304 | #define BNX2_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) | ||
1305 | |||
1306 | #define BNX2_DMA_WCHAN_STAT_02 0x00000ca8 | ||
1307 | #define BNX2_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0) | ||
1308 | #define BNX2_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16) | ||
1309 | #define BNX2_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17) | ||
1310 | #define BNX2_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18) | ||
1311 | |||
1312 | #define BNX2_DMA_WCHAN_STAT_10 0x00000cac | ||
1313 | #define BNX2_DMA_WCHAN_STAT_11 0x00000cb0 | ||
1314 | #define BNX2_DMA_WCHAN_STAT_12 0x00000cb4 | ||
1315 | #define BNX2_DMA_WCHAN_STAT_20 0x00000cb8 | ||
1316 | #define BNX2_DMA_WCHAN_STAT_21 0x00000cbc | ||
1317 | #define BNX2_DMA_WCHAN_STAT_22 0x00000cc0 | ||
1318 | #define BNX2_DMA_WCHAN_STAT_30 0x00000cc4 | ||
1319 | #define BNX2_DMA_WCHAN_STAT_31 0x00000cc8 | ||
1320 | #define BNX2_DMA_WCHAN_STAT_32 0x00000ccc | ||
1321 | #define BNX2_DMA_WCHAN_STAT_40 0x00000cd0 | ||
1322 | #define BNX2_DMA_WCHAN_STAT_41 0x00000cd4 | ||
1323 | #define BNX2_DMA_WCHAN_STAT_42 0x00000cd8 | ||
1324 | #define BNX2_DMA_WCHAN_STAT_50 0x00000cdc | ||
1325 | #define BNX2_DMA_WCHAN_STAT_51 0x00000ce0 | ||
1326 | #define BNX2_DMA_WCHAN_STAT_52 0x00000ce4 | ||
1327 | #define BNX2_DMA_WCHAN_STAT_60 0x00000ce8 | ||
1328 | #define BNX2_DMA_WCHAN_STAT_61 0x00000cec | ||
1329 | #define BNX2_DMA_WCHAN_STAT_62 0x00000cf0 | ||
1330 | #define BNX2_DMA_WCHAN_STAT_70 0x00000cf4 | ||
1331 | #define BNX2_DMA_WCHAN_STAT_71 0x00000cf8 | ||
1332 | #define BNX2_DMA_WCHAN_STAT_72 0x00000cfc | ||
1333 | #define BNX2_DMA_ARB_STAT_00 0x00000d00 | ||
1334 | #define BNX2_DMA_ARB_STAT_00_MASTER (0xffffL<<0) | ||
1335 | #define BNX2_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16) | ||
1336 | #define BNX2_DMA_ARB_STAT_00_CUR_BINMSTR (0xffL<<24) | ||
1337 | |||
1338 | #define BNX2_DMA_ARB_STAT_01 0x00000d04 | ||
1339 | #define BNX2_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0) | ||
1340 | #define BNX2_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4) | ||
1341 | #define BNX2_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8) | ||
1342 | #define BNX2_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12) | ||
1343 | #define BNX2_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16) | ||
1344 | #define BNX2_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20) | ||
1345 | #define BNX2_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24) | ||
1346 | #define BNX2_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28) | ||
1347 | |||
1348 | #define BNX2_DMA_FUSE_CTRL0_CMD 0x00000f00 | ||
1349 | #define BNX2_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0) | ||
1350 | #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1) | ||
1351 | #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2) | ||
1352 | #define BNX2_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3) | ||
1353 | #define BNX2_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8) | ||
1354 | |||
1355 | #define BNX2_DMA_FUSE_CTRL0_DATA 0x00000f04 | ||
1356 | #define BNX2_DMA_FUSE_CTRL1_CMD 0x00000f08 | ||
1357 | #define BNX2_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0) | ||
1358 | #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1) | ||
1359 | #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2) | ||
1360 | #define BNX2_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3) | ||
1361 | #define BNX2_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8) | ||
1362 | |||
1363 | #define BNX2_DMA_FUSE_CTRL1_DATA 0x00000f0c | ||
1364 | #define BNX2_DMA_FUSE_CTRL2_CMD 0x00000f10 | ||
1365 | #define BNX2_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0) | ||
1366 | #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1) | ||
1367 | #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2) | ||
1368 | #define BNX2_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3) | ||
1369 | #define BNX2_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8) | ||
1370 | |||
1371 | #define BNX2_DMA_FUSE_CTRL2_DATA 0x00000f14 | ||
1372 | |||
1373 | |||
1374 | /* | ||
1375 | * context_reg definition | ||
1376 | * offset: 0x1000 | ||
1377 | */ | ||
1378 | #define BNX2_CTX_COMMAND 0x00001000 | ||
1379 | #define BNX2_CTX_COMMAND_ENABLED (1L<<0) | ||
1380 | |||
1381 | #define BNX2_CTX_STATUS 0x00001004 | ||
1382 | #define BNX2_CTX_STATUS_LOCK_WAIT (1L<<0) | ||
1383 | #define BNX2_CTX_STATUS_READ_STAT (1L<<16) | ||
1384 | #define BNX2_CTX_STATUS_WRITE_STAT (1L<<17) | ||
1385 | #define BNX2_CTX_STATUS_ACC_STALL_STAT (1L<<18) | ||
1386 | #define BNX2_CTX_STATUS_LOCK_STALL_STAT (1L<<19) | ||
1387 | |||
1388 | #define BNX2_CTX_VIRT_ADDR 0x00001008 | ||
1389 | #define BNX2_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6) | ||
1390 | |||
1391 | #define BNX2_CTX_PAGE_TBL 0x0000100c | ||
1392 | #define BNX2_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6) | ||
1393 | |||
1394 | #define BNX2_CTX_DATA_ADR 0x00001010 | ||
1395 | #define BNX2_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2) | ||
1396 | |||
1397 | #define BNX2_CTX_DATA 0x00001014 | ||
1398 | #define BNX2_CTX_LOCK 0x00001018 | ||
1399 | #define BNX2_CTX_LOCK_TYPE (0x7L<<0) | ||
1400 | #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0) | ||
1401 | #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0) | ||
1402 | #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0) | ||
1403 | #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0) | ||
1404 | #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0) | ||
1405 | #define BNX2_CTX_LOCK_CID_VALUE (0x3fffL<<7) | ||
1406 | #define BNX2_CTX_LOCK_GRANTED (1L<<26) | ||
1407 | #define BNX2_CTX_LOCK_MODE (0x7L<<27) | ||
1408 | #define BNX2_CTX_LOCK_MODE_UNLOCK (0x0L<<27) | ||
1409 | #define BNX2_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27) | ||
1410 | #define BNX2_CTX_LOCK_MODE_SURE (0x2L<<27) | ||
1411 | #define BNX2_CTX_LOCK_STATUS (1L<<30) | ||
1412 | #define BNX2_CTX_LOCK_REQ (1L<<31) | ||
1413 | |||
1414 | #define BNX2_CTX_ACCESS_STATUS 0x00001040 | ||
1415 | #define BNX2_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0) | ||
1416 | #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10) | ||
1417 | #define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12) | ||
1418 | #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14) | ||
1419 | #define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17) | ||
1420 | |||
1421 | #define BNX2_CTX_DBG_LOCK_STATUS 0x00001044 | ||
1422 | #define BNX2_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0) | ||
1423 | #define BNX2_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22) | ||
1424 | |||
1425 | #define BNX2_CTX_CHNL_LOCK_STATUS_0 0x00001080 | ||
1426 | #define BNX2_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0) | ||
1427 | #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14) | ||
1428 | #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16) | ||
1429 | |||
1430 | #define BNX2_CTX_CHNL_LOCK_STATUS_1 0x00001084 | ||
1431 | #define BNX2_CTX_CHNL_LOCK_STATUS_2 0x00001088 | ||
1432 | #define BNX2_CTX_CHNL_LOCK_STATUS_3 0x0000108c | ||
1433 | #define BNX2_CTX_CHNL_LOCK_STATUS_4 0x00001090 | ||
1434 | #define BNX2_CTX_CHNL_LOCK_STATUS_5 0x00001094 | ||
1435 | #define BNX2_CTX_CHNL_LOCK_STATUS_6 0x00001098 | ||
1436 | #define BNX2_CTX_CHNL_LOCK_STATUS_7 0x0000109c | ||
1437 | #define BNX2_CTX_CHNL_LOCK_STATUS_8 0x000010a0 | ||
1438 | |||
1439 | |||
1440 | /* | ||
1441 | * emac_reg definition | ||
1442 | * offset: 0x1400 | ||
1443 | */ | ||
1444 | #define BNX2_EMAC_MODE 0x00001400 | ||
1445 | #define BNX2_EMAC_MODE_RESET (1L<<0) | ||
1446 | #define BNX2_EMAC_MODE_HALF_DUPLEX (1L<<1) | ||
1447 | #define BNX2_EMAC_MODE_PORT (0x3L<<2) | ||
1448 | #define BNX2_EMAC_MODE_PORT_NONE (0L<<2) | ||
1449 | #define BNX2_EMAC_MODE_PORT_MII (1L<<2) | ||
1450 | #define BNX2_EMAC_MODE_PORT_GMII (2L<<2) | ||
1451 | #define BNX2_EMAC_MODE_PORT_UNDEF (3L<<2) | ||
1452 | #define BNX2_EMAC_MODE_MAC_LOOP (1L<<4) | ||
1453 | #define BNX2_EMAC_MODE_TAGGED_MAC_CTL (1L<<7) | ||
1454 | #define BNX2_EMAC_MODE_TX_BURST (1L<<8) | ||
1455 | #define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9) | ||
1456 | #define BNX2_EMAC_MODE_EXT_LINK_POL (1L<<10) | ||
1457 | #define BNX2_EMAC_MODE_FORCE_LINK (1L<<11) | ||
1458 | #define BNX2_EMAC_MODE_MPKT (1L<<18) | ||
1459 | #define BNX2_EMAC_MODE_MPKT_RCVD (1L<<19) | ||
1460 | #define BNX2_EMAC_MODE_ACPI_RCVD (1L<<20) | ||
1461 | |||
1462 | #define BNX2_EMAC_STATUS 0x00001404 | ||
1463 | #define BNX2_EMAC_STATUS_LINK (1L<<11) | ||
1464 | #define BNX2_EMAC_STATUS_LINK_CHANGE (1L<<12) | ||
1465 | #define BNX2_EMAC_STATUS_MI_COMPLETE (1L<<22) | ||
1466 | #define BNX2_EMAC_STATUS_MI_INT (1L<<23) | ||
1467 | #define BNX2_EMAC_STATUS_AP_ERROR (1L<<24) | ||
1468 | #define BNX2_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31) | ||
1469 | |||
1470 | #define BNX2_EMAC_ATTENTION_ENA 0x00001408 | ||
1471 | #define BNX2_EMAC_ATTENTION_ENA_LINK (1L<<11) | ||
1472 | #define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22) | ||
1473 | #define BNX2_EMAC_ATTENTION_ENA_MI_INT (1L<<23) | ||
1474 | #define BNX2_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24) | ||
1475 | |||
1476 | #define BNX2_EMAC_LED 0x0000140c | ||
1477 | #define BNX2_EMAC_LED_OVERRIDE (1L<<0) | ||
1478 | #define BNX2_EMAC_LED_1000MB_OVERRIDE (1L<<1) | ||
1479 | #define BNX2_EMAC_LED_100MB_OVERRIDE (1L<<2) | ||
1480 | #define BNX2_EMAC_LED_10MB_OVERRIDE (1L<<3) | ||
1481 | #define BNX2_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4) | ||
1482 | #define BNX2_EMAC_LED_BLNK_TRAFFIC (1L<<5) | ||
1483 | #define BNX2_EMAC_LED_TRAFFIC (1L<<6) | ||
1484 | #define BNX2_EMAC_LED_1000MB (1L<<7) | ||
1485 | #define BNX2_EMAC_LED_100MB (1L<<8) | ||
1486 | #define BNX2_EMAC_LED_10MB (1L<<9) | ||
1487 | #define BNX2_EMAC_LED_TRAFFIC_STAT (1L<<10) | ||
1488 | #define BNX2_EMAC_LED_BLNK_RATE (0xfffL<<19) | ||
1489 | #define BNX2_EMAC_LED_BLNK_RATE_ENA (1L<<31) | ||
1490 | |||
1491 | #define BNX2_EMAC_MAC_MATCH0 0x00001410 | ||
1492 | #define BNX2_EMAC_MAC_MATCH1 0x00001414 | ||
1493 | #define BNX2_EMAC_MAC_MATCH2 0x00001418 | ||
1494 | #define BNX2_EMAC_MAC_MATCH3 0x0000141c | ||
1495 | #define BNX2_EMAC_MAC_MATCH4 0x00001420 | ||
1496 | #define BNX2_EMAC_MAC_MATCH5 0x00001424 | ||
1497 | #define BNX2_EMAC_MAC_MATCH6 0x00001428 | ||
1498 | #define BNX2_EMAC_MAC_MATCH7 0x0000142c | ||
1499 | #define BNX2_EMAC_MAC_MATCH8 0x00001430 | ||
1500 | #define BNX2_EMAC_MAC_MATCH9 0x00001434 | ||
1501 | #define BNX2_EMAC_MAC_MATCH10 0x00001438 | ||
1502 | #define BNX2_EMAC_MAC_MATCH11 0x0000143c | ||
1503 | #define BNX2_EMAC_MAC_MATCH12 0x00001440 | ||
1504 | #define BNX2_EMAC_MAC_MATCH13 0x00001444 | ||
1505 | #define BNX2_EMAC_MAC_MATCH14 0x00001448 | ||
1506 | #define BNX2_EMAC_MAC_MATCH15 0x0000144c | ||
1507 | #define BNX2_EMAC_MAC_MATCH16 0x00001450 | ||
1508 | #define BNX2_EMAC_MAC_MATCH17 0x00001454 | ||
1509 | #define BNX2_EMAC_MAC_MATCH18 0x00001458 | ||
1510 | #define BNX2_EMAC_MAC_MATCH19 0x0000145c | ||
1511 | #define BNX2_EMAC_MAC_MATCH20 0x00001460 | ||
1512 | #define BNX2_EMAC_MAC_MATCH21 0x00001464 | ||
1513 | #define BNX2_EMAC_MAC_MATCH22 0x00001468 | ||
1514 | #define BNX2_EMAC_MAC_MATCH23 0x0000146c | ||
1515 | #define BNX2_EMAC_MAC_MATCH24 0x00001470 | ||
1516 | #define BNX2_EMAC_MAC_MATCH25 0x00001474 | ||
1517 | #define BNX2_EMAC_MAC_MATCH26 0x00001478 | ||
1518 | #define BNX2_EMAC_MAC_MATCH27 0x0000147c | ||
1519 | #define BNX2_EMAC_MAC_MATCH28 0x00001480 | ||
1520 | #define BNX2_EMAC_MAC_MATCH29 0x00001484 | ||
1521 | #define BNX2_EMAC_MAC_MATCH30 0x00001488 | ||
1522 | #define BNX2_EMAC_MAC_MATCH31 0x0000148c | ||
1523 | #define BNX2_EMAC_BACKOFF_SEED 0x00001498 | ||
1524 | #define BNX2_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0) | ||
1525 | |||
1526 | #define BNX2_EMAC_RX_MTU_SIZE 0x0000149c | ||
1527 | #define BNX2_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0) | ||
1528 | #define BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) | ||
1529 | |||
1530 | #define BNX2_EMAC_SERDES_CNTL 0x000014a4 | ||
1531 | #define BNX2_EMAC_SERDES_CNTL_RXR (0x7L<<0) | ||
1532 | #define BNX2_EMAC_SERDES_CNTL_RXG (0x3L<<3) | ||
1533 | #define BNX2_EMAC_SERDES_CNTL_RXCKSEL (1L<<6) | ||
1534 | #define BNX2_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7) | ||
1535 | #define BNX2_EMAC_SERDES_CNTL_BGMAX (1L<<10) | ||
1536 | #define BNX2_EMAC_SERDES_CNTL_BGMIN (1L<<11) | ||
1537 | #define BNX2_EMAC_SERDES_CNTL_TXMODE (1L<<12) | ||
1538 | #define BNX2_EMAC_SERDES_CNTL_TXEDGE (1L<<13) | ||
1539 | #define BNX2_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14) | ||
1540 | #define BNX2_EMAC_SERDES_CNTL_PLLTEST (1L<<15) | ||
1541 | #define BNX2_EMAC_SERDES_CNTL_CDET_EN (1L<<16) | ||
1542 | #define BNX2_EMAC_SERDES_CNTL_TBI_LBK (1L<<17) | ||
1543 | #define BNX2_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18) | ||
1544 | #define BNX2_EMAC_SERDES_CNTL_REV_PHASE (1L<<19) | ||
1545 | #define BNX2_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20) | ||
1546 | #define BNX2_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22) | ||
1547 | |||
1548 | #define BNX2_EMAC_SERDES_STATUS 0x000014a8 | ||
1549 | #define BNX2_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0) | ||
1550 | #define BNX2_EMAC_SERDES_STATUS_COMMA_DET (1L<<8) | ||
1551 | |||
1552 | #define BNX2_EMAC_MDIO_COMM 0x000014ac | ||
1553 | #define BNX2_EMAC_MDIO_COMM_DATA (0xffffL<<0) | ||
1554 | #define BNX2_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16) | ||
1555 | #define BNX2_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21) | ||
1556 | #define BNX2_EMAC_MDIO_COMM_COMMAND (0x3L<<26) | ||
1557 | #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26) | ||
1558 | #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26) | ||
1559 | #define BNX2_EMAC_MDIO_COMM_COMMAND_READ (2L<<26) | ||
1560 | #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26) | ||
1561 | #define BNX2_EMAC_MDIO_COMM_FAIL (1L<<28) | ||
1562 | #define BNX2_EMAC_MDIO_COMM_START_BUSY (1L<<29) | ||
1563 | #define BNX2_EMAC_MDIO_COMM_DISEXT (1L<<30) | ||
1564 | |||
1565 | #define BNX2_EMAC_MDIO_STATUS 0x000014b0 | ||
1566 | #define BNX2_EMAC_MDIO_STATUS_LINK (1L<<0) | ||
1567 | #define BNX2_EMAC_MDIO_STATUS_10MB (1L<<1) | ||
1568 | |||
1569 | #define BNX2_EMAC_MDIO_MODE 0x000014b4 | ||
1570 | #define BNX2_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1) | ||
1571 | #define BNX2_EMAC_MDIO_MODE_AUTO_POLL (1L<<4) | ||
1572 | #define BNX2_EMAC_MDIO_MODE_BIT_BANG (1L<<8) | ||
1573 | #define BNX2_EMAC_MDIO_MODE_MDIO (1L<<9) | ||
1574 | #define BNX2_EMAC_MDIO_MODE_MDIO_OE (1L<<10) | ||
1575 | #define BNX2_EMAC_MDIO_MODE_MDC (1L<<11) | ||
1576 | #define BNX2_EMAC_MDIO_MODE_MDINT (1L<<12) | ||
1577 | #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16) | ||
1578 | |||
1579 | #define BNX2_EMAC_MDIO_AUTO_STATUS 0x000014b8 | ||
1580 | #define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0) | ||
1581 | |||
1582 | #define BNX2_EMAC_TX_MODE 0x000014bc | ||
1583 | #define BNX2_EMAC_TX_MODE_RESET (1L<<0) | ||
1584 | #define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) | ||
1585 | #define BNX2_EMAC_TX_MODE_FLOW_EN (1L<<4) | ||
1586 | #define BNX2_EMAC_TX_MODE_BIG_BACKOFF (1L<<5) | ||
1587 | #define BNX2_EMAC_TX_MODE_LONG_PAUSE (1L<<6) | ||
1588 | #define BNX2_EMAC_TX_MODE_LINK_AWARE (1L<<7) | ||
1589 | |||
1590 | #define BNX2_EMAC_TX_STATUS 0x000014c0 | ||
1591 | #define BNX2_EMAC_TX_STATUS_XOFFED (1L<<0) | ||
1592 | #define BNX2_EMAC_TX_STATUS_XOFF_SENT (1L<<1) | ||
1593 | #define BNX2_EMAC_TX_STATUS_XON_SENT (1L<<2) | ||
1594 | #define BNX2_EMAC_TX_STATUS_LINK_UP (1L<<3) | ||
1595 | #define BNX2_EMAC_TX_STATUS_UNDERRUN (1L<<4) | ||
1596 | |||
1597 | #define BNX2_EMAC_TX_LENGTHS 0x000014c4 | ||
1598 | #define BNX2_EMAC_TX_LENGTHS_SLOT (0xffL<<0) | ||
1599 | #define BNX2_EMAC_TX_LENGTHS_IPG (0xfL<<8) | ||
1600 | #define BNX2_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12) | ||
1601 | |||
1602 | #define BNX2_EMAC_RX_MODE 0x000014c8 | ||
1603 | #define BNX2_EMAC_RX_MODE_RESET (1L<<0) | ||
1604 | #define BNX2_EMAC_RX_MODE_FLOW_EN (1L<<2) | ||
1605 | #define BNX2_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3) | ||
1606 | #define BNX2_EMAC_RX_MODE_KEEP_PAUSE (1L<<4) | ||
1607 | #define BNX2_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5) | ||
1608 | #define BNX2_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6) | ||
1609 | #define BNX2_EMAC_RX_MODE_LLC_CHK (1L<<7) | ||
1610 | #define BNX2_EMAC_RX_MODE_PROMISCUOUS (1L<<8) | ||
1611 | #define BNX2_EMAC_RX_MODE_NO_CRC_CHK (1L<<9) | ||
1612 | #define BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10) | ||
1613 | #define BNX2_EMAC_RX_MODE_FILT_BROADCAST (1L<<11) | ||
1614 | #define BNX2_EMAC_RX_MODE_SORT_MODE (1L<<12) | ||
1615 | |||
1616 | #define BNX2_EMAC_RX_STATUS 0x000014cc | ||
1617 | #define BNX2_EMAC_RX_STATUS_FFED (1L<<0) | ||
1618 | #define BNX2_EMAC_RX_STATUS_FF_RECEIVED (1L<<1) | ||
1619 | #define BNX2_EMAC_RX_STATUS_N_RECEIVED (1L<<2) | ||
1620 | |||
1621 | #define BNX2_EMAC_MULTICAST_HASH0 0x000014d0 | ||
1622 | #define BNX2_EMAC_MULTICAST_HASH1 0x000014d4 | ||
1623 | #define BNX2_EMAC_MULTICAST_HASH2 0x000014d8 | ||
1624 | #define BNX2_EMAC_MULTICAST_HASH3 0x000014dc | ||
1625 | #define BNX2_EMAC_MULTICAST_HASH4 0x000014e0 | ||
1626 | #define BNX2_EMAC_MULTICAST_HASH5 0x000014e4 | ||
1627 | #define BNX2_EMAC_MULTICAST_HASH6 0x000014e8 | ||
1628 | #define BNX2_EMAC_MULTICAST_HASH7 0x000014ec | ||
1629 | #define BNX2_EMAC_RX_STAT_IFHCINOCTETS 0x00001500 | ||
1630 | #define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504 | ||
1631 | #define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508 | ||
1632 | #define BNX2_EMAC_RX_STAT_IFHCINUCASTPKTS 0x0000150c | ||
1633 | #define BNX2_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x00001510 | ||
1634 | #define BNX2_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x00001514 | ||
1635 | #define BNX2_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x00001518 | ||
1636 | #define BNX2_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x0000151c | ||
1637 | #define BNX2_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x00001520 | ||
1638 | #define BNX2_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524 | ||
1639 | #define BNX2_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x00001528 | ||
1640 | #define BNX2_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x0000152c | ||
1641 | #define BNX2_EMAC_RX_STAT_XOFFSTATEENTERED 0x00001530 | ||
1642 | #define BNX2_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534 | ||
1643 | #define BNX2_EMAC_RX_STAT_ETHERSTATSJABBERS 0x00001538 | ||
1644 | #define BNX2_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x0000153c | ||
1645 | #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540 | ||
1646 | #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544 | ||
1647 | #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001548 | ||
1648 | #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c | ||
1649 | #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550 | ||
1650 | #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554 | ||
1651 | #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001558 | ||
1652 | #define BNX2_EMAC_RXMAC_DEBUG0 0x0000155c | ||
1653 | #define BNX2_EMAC_RXMAC_DEBUG1 0x00001560 | ||
1654 | #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0) | ||
1655 | #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1) | ||
1656 | #define BNX2_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2) | ||
1657 | #define BNX2_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3) | ||
1658 | #define BNX2_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4) | ||
1659 | #define BNX2_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5) | ||
1660 | #define BNX2_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6) | ||
1661 | #define BNX2_EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7) | ||
1662 | #define BNX2_EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23) | ||
1663 | |||
1664 | #define BNX2_EMAC_RXMAC_DEBUG2 0x00001564 | ||
1665 | #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0) | ||
1666 | #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0x0L<<0) | ||
1667 | #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SFD (0x1L<<0) | ||
1668 | #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DATA (0x2L<<0) | ||
1669 | #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (0x3L<<0) | ||
1670 | #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_EXT (0x4L<<0) | ||
1671 | #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DROP (0x5L<<0) | ||
1672 | #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (0x6L<<0) | ||
1673 | #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_FC (0x7L<<0) | ||
1674 | #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3) | ||
1675 | #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0x0L<<3) | ||
1676 | #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (0x1L<<3) | ||
1677 | #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (0x2L<<3) | ||
1678 | #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (0x3L<<3) | ||
1679 | #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (0x4L<<3) | ||
1680 | #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (0x5L<<3) | ||
1681 | #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (0x6L<<3) | ||
1682 | #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (0x7L<<3) | ||
1683 | #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (0x8L<<3) | ||
1684 | #define BNX2_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7) | ||
1685 | #define BNX2_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15) | ||
1686 | #define BNX2_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16) | ||
1687 | #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18) | ||
1688 | #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18) | ||
1689 | #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18) | ||
1690 | #define BNX2_EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19) | ||
1691 | #define BNX2_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23) | ||
1692 | |||
1693 | #define BNX2_EMAC_RXMAC_DEBUG3 0x00001568 | ||
1694 | #define BNX2_EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0) | ||
1695 | #define BNX2_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16) | ||
1696 | |||
1697 | #define BNX2_EMAC_RXMAC_DEBUG4 0x0000156c | ||
1698 | #define BNX2_EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0) | ||
1699 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16) | ||
1700 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0x0L<<16) | ||
1701 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16) | ||
1702 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16) | ||
1703 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16) | ||
1704 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16) | ||
1705 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16) | ||
1706 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16) | ||
1707 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16) | ||
1708 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16) | ||
1709 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16) | ||
1710 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (0xaL<<16) | ||
1711 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (0xeL<<16) | ||
1712 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (0xfL<<16) | ||
1713 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (0x10L<<16) | ||
1714 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC (0x11L<<16) | ||
1715 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (0x12L<<16) | ||
1716 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (0x13L<<16) | ||
1717 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (0x14L<<16) | ||
1718 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (0x15L<<16) | ||
1719 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (0x16L<<16) | ||
1720 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (0x17L<<16) | ||
1721 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC (0x18L<<16) | ||
1722 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (0x19L<<16) | ||
1723 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (0x1aL<<16) | ||
1724 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (0x1bL<<16) | ||
1725 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (0x1cL<<16) | ||
1726 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (0x1dL<<16) | ||
1727 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XON (0x1eL<<16) | ||
1728 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (0x1fL<<16) | ||
1729 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16) | ||
1730 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (0x21L<<16) | ||
1731 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (0x22L<<16) | ||
1732 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (0x23L<<16) | ||
1733 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (0x24L<<16) | ||
1734 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (0x25L<<16) | ||
1735 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (0x26L<<16) | ||
1736 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (0x27L<<16) | ||
1737 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (0x28L<<16) | ||
1738 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (0x29L<<16) | ||
1739 | #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (0x2aL<<16) | ||
1740 | #define BNX2_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22) | ||
1741 | #define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23) | ||
1742 | #define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24) | ||
1743 | #define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25) | ||
1744 | #define BNX2_EMAC_RXMAC_DEBUG4_sfd_FOUND (1L<<26) | ||
1745 | #define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27) | ||
1746 | #define BNX2_EMAC_RXMAC_DEBUG4_START (1L<<28) | ||
1747 | |||
1748 | #define BNX2_EMAC_RXMAC_DEBUG5 0x00001570 | ||
1749 | #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0) | ||
1750 | #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0) | ||
1751 | #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0) | ||
1752 | #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0) | ||
1753 | #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0) | ||
1754 | #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0) | ||
1755 | #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0) | ||
1756 | #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0) | ||
1757 | #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4) | ||
1758 | #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0x0L<<4) | ||
1759 | #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (0x1L<<4) | ||
1760 | #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (0x2L<<4) | ||
1761 | #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (0x3L<<4) | ||
1762 | #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (0x4L<<4) | ||
1763 | #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (0x6L<<4) | ||
1764 | #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (0x7L<<4) | ||
1765 | #define BNX2_EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7) | ||
1766 | #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8) | ||
1767 | #define BNX2_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11) | ||
1768 | #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12) | ||
1769 | #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13) | ||
1770 | #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14) | ||
1771 | #define BNX2_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15) | ||
1772 | #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16) | ||
1773 | #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19) | ||
1774 | #define BNX2_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20) | ||
1775 | |||
1776 | #define BNX2_EMAC_RX_STAT_AC0 0x00001580 | ||
1777 | #define BNX2_EMAC_RX_STAT_AC1 0x00001584 | ||
1778 | #define BNX2_EMAC_RX_STAT_AC2 0x00001588 | ||
1779 | #define BNX2_EMAC_RX_STAT_AC3 0x0000158c | ||
1780 | #define BNX2_EMAC_RX_STAT_AC4 0x00001590 | ||
1781 | #define BNX2_EMAC_RX_STAT_AC5 0x00001594 | ||
1782 | #define BNX2_EMAC_RX_STAT_AC6 0x00001598 | ||
1783 | #define BNX2_EMAC_RX_STAT_AC7 0x0000159c | ||
1784 | #define BNX2_EMAC_RX_STAT_AC8 0x000015a0 | ||
1785 | #define BNX2_EMAC_RX_STAT_AC9 0x000015a4 | ||
1786 | #define BNX2_EMAC_RX_STAT_AC10 0x000015a8 | ||
1787 | #define BNX2_EMAC_RX_STAT_AC11 0x000015ac | ||
1788 | #define BNX2_EMAC_RX_STAT_AC12 0x000015b0 | ||
1789 | #define BNX2_EMAC_RX_STAT_AC13 0x000015b4 | ||
1790 | #define BNX2_EMAC_RX_STAT_AC14 0x000015b8 | ||
1791 | #define BNX2_EMAC_RX_STAT_AC15 0x000015bc | ||
1792 | #define BNX2_EMAC_RX_STAT_AC16 0x000015c0 | ||
1793 | #define BNX2_EMAC_RX_STAT_AC17 0x000015c4 | ||
1794 | #define BNX2_EMAC_RX_STAT_AC18 0x000015c8 | ||
1795 | #define BNX2_EMAC_RX_STAT_AC19 0x000015cc | ||
1796 | #define BNX2_EMAC_RX_STAT_AC20 0x000015d0 | ||
1797 | #define BNX2_EMAC_RX_STAT_AC21 0x000015d4 | ||
1798 | #define BNX2_EMAC_RX_STAT_AC22 0x000015d8 | ||
1799 | #define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc | ||
1800 | #define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600 | ||
1801 | #define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604 | ||
1802 | #define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608 | ||
1803 | #define BNX2_EMAC_TX_STAT_OUTXONSENT 0x0000160c | ||
1804 | #define BNX2_EMAC_TX_STAT_OUTXOFFSENT 0x00001610 | ||
1805 | #define BNX2_EMAC_TX_STAT_FLOWCONTROLDONE 0x00001614 | ||
1806 | #define BNX2_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x00001618 | ||
1807 | #define BNX2_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x0000161c | ||
1808 | #define BNX2_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x00001620 | ||
1809 | #define BNX2_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x00001624 | ||
1810 | #define BNX2_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x00001628 | ||
1811 | #define BNX2_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x0000162c | ||
1812 | #define BNX2_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x00001630 | ||
1813 | #define BNX2_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x00001634 | ||
1814 | #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x00001638 | ||
1815 | #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x0000163c | ||
1816 | #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001640 | ||
1817 | #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644 | ||
1818 | #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648 | ||
1819 | #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c | ||
1820 | #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001650 | ||
1821 | #define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654 | ||
1822 | #define BNX2_EMAC_TXMAC_DEBUG0 0x00001658 | ||
1823 | #define BNX2_EMAC_TXMAC_DEBUG1 0x0000165c | ||
1824 | #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0) | ||
1825 | #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0x0L<<0) | ||
1826 | #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (0x1L<<0) | ||
1827 | #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (0x4L<<0) | ||
1828 | #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (0x5L<<0) | ||
1829 | #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (0x6L<<0) | ||
1830 | #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (0x7L<<0) | ||
1831 | #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (0x8L<<0) | ||
1832 | #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (0x9L<<0) | ||
1833 | #define BNX2_EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4) | ||
1834 | #define BNX2_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5) | ||
1835 | #define BNX2_EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6) | ||
1836 | #define BNX2_EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10) | ||
1837 | #define BNX2_EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11) | ||
1838 | #define BNX2_EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12) | ||
1839 | #define BNX2_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13) | ||
1840 | #define BNX2_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14) | ||
1841 | #define BNX2_EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15) | ||
1842 | #define BNX2_EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19) | ||
1843 | |||
1844 | #define BNX2_EMAC_TXMAC_DEBUG2 0x00001660 | ||
1845 | #define BNX2_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0) | ||
1846 | #define BNX2_EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10) | ||
1847 | #define BNX2_EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26) | ||
1848 | #define BNX2_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31) | ||
1849 | |||
1850 | #define BNX2_EMAC_TXMAC_DEBUG3 0x00001664 | ||
1851 | #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0) | ||
1852 | #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0x0L<<0) | ||
1853 | #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (0x1L<<0) | ||
1854 | #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (0x2L<<0) | ||
1855 | #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SFD (0x3L<<0) | ||
1856 | #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_DATA (0x4L<<0) | ||
1857 | #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (0x5L<<0) | ||
1858 | #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (0x6L<<0) | ||
1859 | #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EXT (0x7L<<0) | ||
1860 | #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATB (0x8L<<0) | ||
1861 | #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATG (0x9L<<0) | ||
1862 | #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_JAM (0xaL<<0) | ||
1863 | #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (0xbL<<0) | ||
1864 | #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (0xcL<<0) | ||
1865 | #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (0xdL<<0) | ||
1866 | #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (0xeL<<0) | ||
1867 | #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4) | ||
1868 | #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0x0L<<4) | ||
1869 | #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (0x1L<<4) | ||
1870 | #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (0x2L<<4) | ||
1871 | #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_MC (0x3L<<4) | ||
1872 | #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (0x4L<<4) | ||
1873 | #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (0x5L<<4) | ||
1874 | #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC (0x6L<<4) | ||
1875 | #define BNX2_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7) | ||
1876 | #define BNX2_EMAC_TXMAC_DEBUG3_XOFF (1L<<8) | ||
1877 | #define BNX2_EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9) | ||
1878 | #define BNX2_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13) | ||
1879 | |||
1880 | #define BNX2_EMAC_TXMAC_DEBUG4 0x00001668 | ||
1881 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0) | ||
1882 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16) | ||
1883 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16) | ||
1884 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16) | ||
1885 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16) | ||
1886 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16) | ||
1887 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16) | ||
1888 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16) | ||
1889 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16) | ||
1890 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16) | ||
1891 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16) | ||
1892 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16) | ||
1893 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16) | ||
1894 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16) | ||
1895 | #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16) | ||
1896 | #define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20) | ||
1897 | #define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21) | ||
1898 | #define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22) | ||
1899 | #define BNX2_EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23) | ||
1900 | #define BNX2_EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24) | ||
1901 | #define BNX2_EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25) | ||
1902 | #define BNX2_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26) | ||
1903 | #define BNX2_EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27) | ||
1904 | #define BNX2_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28) | ||
1905 | #define BNX2_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29) | ||
1906 | #define BNX2_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30) | ||
1907 | #define BNX2_EMAC_TXMAC_DEBUG4_GO (1L<<31) | ||
1908 | |||
1909 | #define BNX2_EMAC_TX_STAT_AC0 0x00001680 | ||
1910 | #define BNX2_EMAC_TX_STAT_AC1 0x00001684 | ||
1911 | #define BNX2_EMAC_TX_STAT_AC2 0x00001688 | ||
1912 | #define BNX2_EMAC_TX_STAT_AC3 0x0000168c | ||
1913 | #define BNX2_EMAC_TX_STAT_AC4 0x00001690 | ||
1914 | #define BNX2_EMAC_TX_STAT_AC5 0x00001694 | ||
1915 | #define BNX2_EMAC_TX_STAT_AC6 0x00001698 | ||
1916 | #define BNX2_EMAC_TX_STAT_AC7 0x0000169c | ||
1917 | #define BNX2_EMAC_TX_STAT_AC8 0x000016a0 | ||
1918 | #define BNX2_EMAC_TX_STAT_AC9 0x000016a4 | ||
1919 | #define BNX2_EMAC_TX_STAT_AC10 0x000016a8 | ||
1920 | #define BNX2_EMAC_TX_STAT_AC11 0x000016ac | ||
1921 | #define BNX2_EMAC_TX_STAT_AC12 0x000016b0 | ||
1922 | #define BNX2_EMAC_TX_STAT_AC13 0x000016b4 | ||
1923 | #define BNX2_EMAC_TX_STAT_AC14 0x000016b8 | ||
1924 | #define BNX2_EMAC_TX_STAT_AC15 0x000016bc | ||
1925 | #define BNX2_EMAC_TX_STAT_AC16 0x000016c0 | ||
1926 | #define BNX2_EMAC_TX_STAT_AC17 0x000016c4 | ||
1927 | #define BNX2_EMAC_TX_STAT_AC18 0x000016c8 | ||
1928 | #define BNX2_EMAC_TX_STAT_AC19 0x000016cc | ||
1929 | #define BNX2_EMAC_TX_STAT_AC20 0x000016d0 | ||
1930 | #define BNX2_EMAC_TX_STAT_AC21 0x000016d4 | ||
1931 | #define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8 | ||
1932 | |||
1933 | |||
1934 | /* | ||
1935 | * rpm_reg definition | ||
1936 | * offset: 0x1800 | ||
1937 | */ | ||
1938 | #define BNX2_RPM_COMMAND 0x00001800 | ||
1939 | #define BNX2_RPM_COMMAND_ENABLED (1L<<0) | ||
1940 | #define BNX2_RPM_COMMAND_OVERRUN_ABORT (1L<<4) | ||
1941 | |||
1942 | #define BNX2_RPM_STATUS 0x00001804 | ||
1943 | #define BNX2_RPM_STATUS_MBUF_WAIT (1L<<0) | ||
1944 | #define BNX2_RPM_STATUS_FREE_WAIT (1L<<1) | ||
1945 | |||
1946 | #define BNX2_RPM_CONFIG 0x00001808 | ||
1947 | #define BNX2_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0) | ||
1948 | #define BNX2_RPM_CONFIG_ACPI_ENA (1L<<1) | ||
1949 | #define BNX2_RPM_CONFIG_ACPI_KEEP (1L<<2) | ||
1950 | #define BNX2_RPM_CONFIG_MP_KEEP (1L<<3) | ||
1951 | #define BNX2_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4) | ||
1952 | #define BNX2_RPM_CONFIG_IGNORE_VLAN (1L<<31) | ||
1953 | |||
1954 | #define BNX2_RPM_VLAN_MATCH0 0x00001810 | ||
1955 | #define BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0) | ||
1956 | |||
1957 | #define BNX2_RPM_VLAN_MATCH1 0x00001814 | ||
1958 | #define BNX2_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffL<<0) | ||
1959 | |||
1960 | #define BNX2_RPM_VLAN_MATCH2 0x00001818 | ||
1961 | #define BNX2_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffL<<0) | ||
1962 | |||
1963 | #define BNX2_RPM_VLAN_MATCH3 0x0000181c | ||
1964 | #define BNX2_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffL<<0) | ||
1965 | |||
1966 | #define BNX2_RPM_SORT_USER0 0x00001820 | ||
1967 | #define BNX2_RPM_SORT_USER0_PM_EN (0xffffL<<0) | ||
1968 | #define BNX2_RPM_SORT_USER0_BC_EN (1L<<16) | ||
1969 | #define BNX2_RPM_SORT_USER0_MC_EN (1L<<17) | ||
1970 | #define BNX2_RPM_SORT_USER0_MC_HSH_EN (1L<<18) | ||
1971 | #define BNX2_RPM_SORT_USER0_PROM_EN (1L<<19) | ||
1972 | #define BNX2_RPM_SORT_USER0_VLAN_EN (0xfL<<20) | ||
1973 | #define BNX2_RPM_SORT_USER0_PROM_VLAN (1L<<24) | ||
1974 | #define BNX2_RPM_SORT_USER0_ENA (1L<<31) | ||
1975 | |||
1976 | #define BNX2_RPM_SORT_USER1 0x00001824 | ||
1977 | #define BNX2_RPM_SORT_USER1_PM_EN (0xffffL<<0) | ||
1978 | #define BNX2_RPM_SORT_USER1_BC_EN (1L<<16) | ||
1979 | #define BNX2_RPM_SORT_USER1_MC_EN (1L<<17) | ||
1980 | #define BNX2_RPM_SORT_USER1_MC_HSH_EN (1L<<18) | ||
1981 | #define BNX2_RPM_SORT_USER1_PROM_EN (1L<<19) | ||
1982 | #define BNX2_RPM_SORT_USER1_VLAN_EN (0xfL<<20) | ||
1983 | #define BNX2_RPM_SORT_USER1_PROM_VLAN (1L<<24) | ||
1984 | #define BNX2_RPM_SORT_USER1_ENA (1L<<31) | ||
1985 | |||
1986 | #define BNX2_RPM_SORT_USER2 0x00001828 | ||
1987 | #define BNX2_RPM_SORT_USER2_PM_EN (0xffffL<<0) | ||
1988 | #define BNX2_RPM_SORT_USER2_BC_EN (1L<<16) | ||
1989 | #define BNX2_RPM_SORT_USER2_MC_EN (1L<<17) | ||
1990 | #define BNX2_RPM_SORT_USER2_MC_HSH_EN (1L<<18) | ||
1991 | #define BNX2_RPM_SORT_USER2_PROM_EN (1L<<19) | ||
1992 | #define BNX2_RPM_SORT_USER2_VLAN_EN (0xfL<<20) | ||
1993 | #define BNX2_RPM_SORT_USER2_PROM_VLAN (1L<<24) | ||
1994 | #define BNX2_RPM_SORT_USER2_ENA (1L<<31) | ||
1995 | |||
1996 | #define BNX2_RPM_SORT_USER3 0x0000182c | ||
1997 | #define BNX2_RPM_SORT_USER3_PM_EN (0xffffL<<0) | ||
1998 | #define BNX2_RPM_SORT_USER3_BC_EN (1L<<16) | ||
1999 | #define BNX2_RPM_SORT_USER3_MC_EN (1L<<17) | ||
2000 | #define BNX2_RPM_SORT_USER3_MC_HSH_EN (1L<<18) | ||
2001 | #define BNX2_RPM_SORT_USER3_PROM_EN (1L<<19) | ||
2002 | #define BNX2_RPM_SORT_USER3_VLAN_EN (0xfL<<20) | ||
2003 | #define BNX2_RPM_SORT_USER3_PROM_VLAN (1L<<24) | ||
2004 | #define BNX2_RPM_SORT_USER3_ENA (1L<<31) | ||
2005 | |||
2006 | #define BNX2_RPM_STAT_L2_FILTER_DISCARDS 0x00001840 | ||
2007 | #define BNX2_RPM_STAT_RULE_CHECKER_DISCARDS 0x00001844 | ||
2008 | #define BNX2_RPM_STAT_IFINFTQDISCARDS 0x00001848 | ||
2009 | #define BNX2_RPM_STAT_IFINMBUFDISCARD 0x0000184c | ||
2010 | #define BNX2_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850 | ||
2011 | #define BNX2_RPM_STAT_AC0 0x00001880 | ||
2012 | #define BNX2_RPM_STAT_AC1 0x00001884 | ||
2013 | #define BNX2_RPM_STAT_AC2 0x00001888 | ||
2014 | #define BNX2_RPM_STAT_AC3 0x0000188c | ||
2015 | #define BNX2_RPM_STAT_AC4 0x00001890 | ||
2016 | #define BNX2_RPM_RC_CNTL_0 0x00001900 | ||
2017 | #define BNX2_RPM_RC_CNTL_0_OFFSET (0xffL<<0) | ||
2018 | #define BNX2_RPM_RC_CNTL_0_CLASS (0x7L<<8) | ||
2019 | #define BNX2_RPM_RC_CNTL_0_PRIORITY (1L<<11) | ||
2020 | #define BNX2_RPM_RC_CNTL_0_P4 (1L<<12) | ||
2021 | #define BNX2_RPM_RC_CNTL_0_HDR_TYPE (0x7L<<13) | ||
2022 | #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13) | ||
2023 | #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13) | ||
2024 | #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13) | ||
2025 | #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13) | ||
2026 | #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13) | ||
2027 | #define BNX2_RPM_RC_CNTL_0_COMP (0x3L<<16) | ||
2028 | #define BNX2_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16) | ||
2029 | #define BNX2_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16) | ||
2030 | #define BNX2_RPM_RC_CNTL_0_COMP_GREATER (2L<<16) | ||
2031 | #define BNX2_RPM_RC_CNTL_0_COMP_LESS (3L<<16) | ||
2032 | #define BNX2_RPM_RC_CNTL_0_SBIT (1L<<19) | ||
2033 | #define BNX2_RPM_RC_CNTL_0_CMDSEL (0xfL<<20) | ||
2034 | #define BNX2_RPM_RC_CNTL_0_MAP (1L<<24) | ||
2035 | #define BNX2_RPM_RC_CNTL_0_DISCARD (1L<<25) | ||
2036 | #define BNX2_RPM_RC_CNTL_0_MASK (1L<<26) | ||
2037 | #define BNX2_RPM_RC_CNTL_0_P1 (1L<<27) | ||
2038 | #define BNX2_RPM_RC_CNTL_0_P2 (1L<<28) | ||
2039 | #define BNX2_RPM_RC_CNTL_0_P3 (1L<<29) | ||
2040 | #define BNX2_RPM_RC_CNTL_0_NBIT (1L<<30) | ||
2041 | |||
2042 | #define BNX2_RPM_RC_VALUE_MASK_0 0x00001904 | ||
2043 | #define BNX2_RPM_RC_VALUE_MASK_0_VALUE (0xffffL<<0) | ||
2044 | #define BNX2_RPM_RC_VALUE_MASK_0_MASK (0xffffL<<16) | ||
2045 | |||
2046 | #define BNX2_RPM_RC_CNTL_1 0x00001908 | ||
2047 | #define BNX2_RPM_RC_CNTL_1_A (0x3ffffL<<0) | ||
2048 | #define BNX2_RPM_RC_CNTL_1_B (0xfffL<<19) | ||
2049 | |||
2050 | #define BNX2_RPM_RC_VALUE_MASK_1 0x0000190c | ||
2051 | #define BNX2_RPM_RC_CNTL_2 0x00001910 | ||
2052 | #define BNX2_RPM_RC_CNTL_2_A (0x3ffffL<<0) | ||
2053 | #define BNX2_RPM_RC_CNTL_2_B (0xfffL<<19) | ||
2054 | |||
2055 | #define BNX2_RPM_RC_VALUE_MASK_2 0x00001914 | ||
2056 | #define BNX2_RPM_RC_CNTL_3 0x00001918 | ||
2057 | #define BNX2_RPM_RC_CNTL_3_A (0x3ffffL<<0) | ||
2058 | #define BNX2_RPM_RC_CNTL_3_B (0xfffL<<19) | ||
2059 | |||
2060 | #define BNX2_RPM_RC_VALUE_MASK_3 0x0000191c | ||
2061 | #define BNX2_RPM_RC_CNTL_4 0x00001920 | ||
2062 | #define BNX2_RPM_RC_CNTL_4_A (0x3ffffL<<0) | ||
2063 | #define BNX2_RPM_RC_CNTL_4_B (0xfffL<<19) | ||
2064 | |||
2065 | #define BNX2_RPM_RC_VALUE_MASK_4 0x00001924 | ||
2066 | #define BNX2_RPM_RC_CNTL_5 0x00001928 | ||
2067 | #define BNX2_RPM_RC_CNTL_5_A (0x3ffffL<<0) | ||
2068 | #define BNX2_RPM_RC_CNTL_5_B (0xfffL<<19) | ||
2069 | |||
2070 | #define BNX2_RPM_RC_VALUE_MASK_5 0x0000192c | ||
2071 | #define BNX2_RPM_RC_CNTL_6 0x00001930 | ||
2072 | #define BNX2_RPM_RC_CNTL_6_A (0x3ffffL<<0) | ||
2073 | #define BNX2_RPM_RC_CNTL_6_B (0xfffL<<19) | ||
2074 | |||
2075 | #define BNX2_RPM_RC_VALUE_MASK_6 0x00001934 | ||
2076 | #define BNX2_RPM_RC_CNTL_7 0x00001938 | ||
2077 | #define BNX2_RPM_RC_CNTL_7_A (0x3ffffL<<0) | ||
2078 | #define BNX2_RPM_RC_CNTL_7_B (0xfffL<<19) | ||
2079 | |||
2080 | #define BNX2_RPM_RC_VALUE_MASK_7 0x0000193c | ||
2081 | #define BNX2_RPM_RC_CNTL_8 0x00001940 | ||
2082 | #define BNX2_RPM_RC_CNTL_8_A (0x3ffffL<<0) | ||
2083 | #define BNX2_RPM_RC_CNTL_8_B (0xfffL<<19) | ||
2084 | |||
2085 | #define BNX2_RPM_RC_VALUE_MASK_8 0x00001944 | ||
2086 | #define BNX2_RPM_RC_CNTL_9 0x00001948 | ||
2087 | #define BNX2_RPM_RC_CNTL_9_A (0x3ffffL<<0) | ||
2088 | #define BNX2_RPM_RC_CNTL_9_B (0xfffL<<19) | ||
2089 | |||
2090 | #define BNX2_RPM_RC_VALUE_MASK_9 0x0000194c | ||
2091 | #define BNX2_RPM_RC_CNTL_10 0x00001950 | ||
2092 | #define BNX2_RPM_RC_CNTL_10_A (0x3ffffL<<0) | ||
2093 | #define BNX2_RPM_RC_CNTL_10_B (0xfffL<<19) | ||
2094 | |||
2095 | #define BNX2_RPM_RC_VALUE_MASK_10 0x00001954 | ||
2096 | #define BNX2_RPM_RC_CNTL_11 0x00001958 | ||
2097 | #define BNX2_RPM_RC_CNTL_11_A (0x3ffffL<<0) | ||
2098 | #define BNX2_RPM_RC_CNTL_11_B (0xfffL<<19) | ||
2099 | |||
2100 | #define BNX2_RPM_RC_VALUE_MASK_11 0x0000195c | ||
2101 | #define BNX2_RPM_RC_CNTL_12 0x00001960 | ||
2102 | #define BNX2_RPM_RC_CNTL_12_A (0x3ffffL<<0) | ||
2103 | #define BNX2_RPM_RC_CNTL_12_B (0xfffL<<19) | ||
2104 | |||
2105 | #define BNX2_RPM_RC_VALUE_MASK_12 0x00001964 | ||
2106 | #define BNX2_RPM_RC_CNTL_13 0x00001968 | ||
2107 | #define BNX2_RPM_RC_CNTL_13_A (0x3ffffL<<0) | ||
2108 | #define BNX2_RPM_RC_CNTL_13_B (0xfffL<<19) | ||
2109 | |||
2110 | #define BNX2_RPM_RC_VALUE_MASK_13 0x0000196c | ||
2111 | #define BNX2_RPM_RC_CNTL_14 0x00001970 | ||
2112 | #define BNX2_RPM_RC_CNTL_14_A (0x3ffffL<<0) | ||
2113 | #define BNX2_RPM_RC_CNTL_14_B (0xfffL<<19) | ||
2114 | |||
2115 | #define BNX2_RPM_RC_VALUE_MASK_14 0x00001974 | ||
2116 | #define BNX2_RPM_RC_CNTL_15 0x00001978 | ||
2117 | #define BNX2_RPM_RC_CNTL_15_A (0x3ffffL<<0) | ||
2118 | #define BNX2_RPM_RC_CNTL_15_B (0xfffL<<19) | ||
2119 | |||
2120 | #define BNX2_RPM_RC_VALUE_MASK_15 0x0000197c | ||
2121 | #define BNX2_RPM_RC_CONFIG 0x00001980 | ||
2122 | #define BNX2_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0) | ||
2123 | #define BNX2_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24) | ||
2124 | |||
2125 | #define BNX2_RPM_DEBUG0 0x00001984 | ||
2126 | #define BNX2_RPM_DEBUG0_FM_BCNT (0xffffL<<0) | ||
2127 | #define BNX2_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16) | ||
2128 | #define BNX2_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17) | ||
2129 | #define BNX2_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18) | ||
2130 | #define BNX2_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19) | ||
2131 | #define BNX2_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20) | ||
2132 | #define BNX2_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1L<<21) | ||
2133 | #define BNX2_RPM_DEBUG0_LLC_SNAP (1L<<22) | ||
2134 | #define BNX2_RPM_DEBUG0_FM_STARTED (1L<<23) | ||
2135 | #define BNX2_RPM_DEBUG0_DONE (1L<<24) | ||
2136 | #define BNX2_RPM_DEBUG0_WAIT_4_DONE (1L<<25) | ||
2137 | #define BNX2_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26) | ||
2138 | #define BNX2_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27) | ||
2139 | #define BNX2_RPM_DEBUG0_IGNORE_VLAN (1L<<28) | ||
2140 | #define BNX2_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31) | ||
2141 | |||
2142 | #define BNX2_RPM_DEBUG1 0x00001988 | ||
2143 | #define BNX2_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0) | ||
2144 | #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0) | ||
2145 | #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0) | ||
2146 | #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0) | ||
2147 | #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0) | ||
2148 | #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0) | ||
2149 | #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0) | ||
2150 | #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0) | ||
2151 | #define BNX2_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0) | ||
2152 | #define BNX2_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0) | ||
2153 | #define BNX2_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0) | ||
2154 | #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0) | ||
2155 | #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0) | ||
2156 | #define BNX2_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0) | ||
2157 | #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (0x2000L<<0) | ||
2158 | #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (0x4000L<<0) | ||
2159 | #define BNX2_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (0x8000L<<0) | ||
2160 | #define BNX2_RPM_DEBUG1_HDR_BCNT (0x7ffL<<16) | ||
2161 | #define BNX2_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28) | ||
2162 | #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29) | ||
2163 | #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30) | ||
2164 | #define BNX2_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31) | ||
2165 | |||
2166 | #define BNX2_RPM_DEBUG2 0x0000198c | ||
2167 | #define BNX2_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0) | ||
2168 | #define BNX2_RPM_DEBUG2_IP_BCNT (0xffL<<16) | ||
2169 | #define BNX2_RPM_DEBUG2_THIS_CMD_M4 (1L<<24) | ||
2170 | #define BNX2_RPM_DEBUG2_THIS_CMD_M3 (1L<<25) | ||
2171 | #define BNX2_RPM_DEBUG2_THIS_CMD_M2 (1L<<26) | ||
2172 | #define BNX2_RPM_DEBUG2_THIS_CMD_M1 (1L<<27) | ||
2173 | #define BNX2_RPM_DEBUG2_IPIPE_EMPTY (1L<<28) | ||
2174 | #define BNX2_RPM_DEBUG2_FM_DISCARD (1L<<29) | ||
2175 | #define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30) | ||
2176 | #define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31) | ||
2177 | |||
2178 | #define BNX2_RPM_DEBUG3 0x00001990 | ||
2179 | #define BNX2_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0) | ||
2180 | #define BNX2_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1L<<9) | ||
2181 | #define BNX2_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1L<<10) | ||
2182 | #define BNX2_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1L<<11) | ||
2183 | #define BNX2_RPM_DEBUG3_RDE_RBUF_FREE_REQ (1L<<12) | ||
2184 | #define BNX2_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1L<<13) | ||
2185 | #define BNX2_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1L<<14) | ||
2186 | #define BNX2_RPM_DEBUG3_RBUF_RDE_SOF_DROP (1L<<15) | ||
2187 | #define BNX2_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfL<<16) | ||
2188 | #define BNX2_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1L<<21) | ||
2189 | #define BNX2_RPM_DEBUG3_DROP_NXT_VLD (1L<<22) | ||
2190 | #define BNX2_RPM_DEBUG3_DROP_NXT (1L<<23) | ||
2191 | #define BNX2_RPM_DEBUG3_FTQ_FSM (0x3L<<24) | ||
2192 | #define BNX2_RPM_DEBUG3_FTQ_FSM_IDLE (0x0L<<24) | ||
2193 | #define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_ACK (0x1L<<24) | ||
2194 | #define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_FREE (0x2L<<24) | ||
2195 | #define BNX2_RPM_DEBUG3_MBWRITE_FSM (0x3L<<26) | ||
2196 | #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0x0L<<26) | ||
2197 | #define BNX2_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (0x1L<<26) | ||
2198 | #define BNX2_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (0x2L<<26) | ||
2199 | #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (0x3L<<26) | ||
2200 | #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (0x4L<<26) | ||
2201 | #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (0x5L<<26) | ||
2202 | #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (0x6L<<26) | ||
2203 | #define BNX2_RPM_DEBUG3_MBWRITE_FSM_DONE (0x7L<<26) | ||
2204 | #define BNX2_RPM_DEBUG3_MBFREE_FSM (1L<<29) | ||
2205 | #define BNX2_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29) | ||
2206 | #define BNX2_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1L<<29) | ||
2207 | #define BNX2_RPM_DEBUG3_MBALLOC_FSM (1L<<30) | ||
2208 | #define BNX2_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0x0L<<30) | ||
2209 | #define BNX2_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (0x1L<<30) | ||
2210 | #define BNX2_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31) | ||
2211 | |||
2212 | #define BNX2_RPM_DEBUG4 0x00001994 | ||
2213 | #define BNX2_RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffL<<0) | ||
2214 | #define BNX2_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25) | ||
2215 | #define BNX2_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28) | ||
2216 | #define BNX2_RPM_DEBUG4_DFIFO_EMPTY (1L<<31) | ||
2217 | |||
2218 | #define BNX2_RPM_DEBUG5 0x00001998 | ||
2219 | #define BNX2_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0) | ||
2220 | #define BNX2_RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fL<<5) | ||
2221 | #define BNX2_RPM_DEBUG5_RDROP_MC_RPTR (0x1fL<<10) | ||
2222 | #define BNX2_RPM_DEBUG5_RDROP_RC_RPTR (0x1fL<<15) | ||
2223 | #define BNX2_RPM_DEBUG5_RDROP_ACPI_EMPTY (1L<<20) | ||
2224 | #define BNX2_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21) | ||
2225 | #define BNX2_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1L<<22) | ||
2226 | #define BNX2_RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1L<<23) | ||
2227 | #define BNX2_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24) | ||
2228 | #define BNX2_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1L<<25) | ||
2229 | #define BNX2_RPM_DEBUG5_HOLDREG_MC_EMPTY (1L<<26) | ||
2230 | #define BNX2_RPM_DEBUG5_HOLDREG_RC_EMPTY (1L<<27) | ||
2231 | #define BNX2_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28) | ||
2232 | #define BNX2_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29) | ||
2233 | #define BNX2_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30) | ||
2234 | #define BNX2_RPM_DEBUG5_HOLDREG_RD (1L<<31) | ||
2235 | |||
2236 | #define BNX2_RPM_DEBUG6 0x0000199c | ||
2237 | #define BNX2_RPM_DEBUG6_ACPI_VEC (0xffffL<<0) | ||
2238 | #define BNX2_RPM_DEBUG6_VEC (0xffffL<<16) | ||
2239 | |||
2240 | #define BNX2_RPM_DEBUG7 0x000019a0 | ||
2241 | #define BNX2_RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffL<<0) | ||
2242 | |||
2243 | #define BNX2_RPM_DEBUG8 0x000019a4 | ||
2244 | #define BNX2_RPM_DEBUG8_PS_ACPI_FSM (0xfL<<0) | ||
2245 | #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0) | ||
2246 | #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0) | ||
2247 | #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0) | ||
2248 | #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0) | ||
2249 | #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0) | ||
2250 | #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0) | ||
2251 | #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0) | ||
2252 | #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0) | ||
2253 | #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0) | ||
2254 | #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0) | ||
2255 | #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0) | ||
2256 | #define BNX2_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4) | ||
2257 | #define BNX2_RPM_DEBUG8_COMPARE_AT_W3_DATA (1L<<5) | ||
2258 | #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1L<<6) | ||
2259 | #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W3 (1L<<7) | ||
2260 | #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W2 (1L<<8) | ||
2261 | #define BNX2_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1L<<9) | ||
2262 | #define BNX2_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1L<<10) | ||
2263 | #define BNX2_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1L<<11) | ||
2264 | #define BNX2_RPM_DEBUG8_EOF_DET (1L<<12) | ||
2265 | #define BNX2_RPM_DEBUG8_SOF_DET (1L<<13) | ||
2266 | #define BNX2_RPM_DEBUG8_WAIT_4_SOF (1L<<14) | ||
2267 | #define BNX2_RPM_DEBUG8_ALL_DONE (1L<<15) | ||
2268 | #define BNX2_RPM_DEBUG8_THBUF_ADDR (0x7fL<<16) | ||
2269 | #define BNX2_RPM_DEBUG8_BYTE_CTR (0xffL<<24) | ||
2270 | |||
2271 | #define BNX2_RPM_DEBUG9 0x000019a8 | ||
2272 | #define BNX2_RPM_DEBUG9_OUTFIFO_COUNT (0x7L<<0) | ||
2273 | #define BNX2_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3) | ||
2274 | #define BNX2_RPM_DEBUG9_VLD_RD_ENTRY_CT (0x7L<<4) | ||
2275 | #define BNX2_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28) | ||
2276 | #define BNX2_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29) | ||
2277 | #define BNX2_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30) | ||
2278 | #define BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31) | ||
2279 | |||
2280 | #define BNX2_RPM_ACPI_DBG_BUF_W00 0x000019c0 | ||
2281 | #define BNX2_RPM_ACPI_DBG_BUF_W01 0x000019c4 | ||
2282 | #define BNX2_RPM_ACPI_DBG_BUF_W02 0x000019c8 | ||
2283 | #define BNX2_RPM_ACPI_DBG_BUF_W03 0x000019cc | ||
2284 | #define BNX2_RPM_ACPI_DBG_BUF_W10 0x000019d0 | ||
2285 | #define BNX2_RPM_ACPI_DBG_BUF_W11 0x000019d4 | ||
2286 | #define BNX2_RPM_ACPI_DBG_BUF_W12 0x000019d8 | ||
2287 | #define BNX2_RPM_ACPI_DBG_BUF_W13 0x000019dc | ||
2288 | #define BNX2_RPM_ACPI_DBG_BUF_W20 0x000019e0 | ||
2289 | #define BNX2_RPM_ACPI_DBG_BUF_W21 0x000019e4 | ||
2290 | #define BNX2_RPM_ACPI_DBG_BUF_W22 0x000019e8 | ||
2291 | #define BNX2_RPM_ACPI_DBG_BUF_W23 0x000019ec | ||
2292 | #define BNX2_RPM_ACPI_DBG_BUF_W30 0x000019f0 | ||
2293 | #define BNX2_RPM_ACPI_DBG_BUF_W31 0x000019f4 | ||
2294 | #define BNX2_RPM_ACPI_DBG_BUF_W32 0x000019f8 | ||
2295 | #define BNX2_RPM_ACPI_DBG_BUF_W33 0x000019fc | ||
2296 | |||
2297 | |||
2298 | /* | ||
2299 | * rbuf_reg definition | ||
2300 | * offset: 0x200000 | ||
2301 | */ | ||
2302 | #define BNX2_RBUF_COMMAND 0x00200000 | ||
2303 | #define BNX2_RBUF_COMMAND_ENABLED (1L<<0) | ||
2304 | #define BNX2_RBUF_COMMAND_FREE_INIT (1L<<1) | ||
2305 | #define BNX2_RBUF_COMMAND_RAM_INIT (1L<<2) | ||
2306 | #define BNX2_RBUF_COMMAND_OVER_FREE (1L<<4) | ||
2307 | #define BNX2_RBUF_COMMAND_ALLOC_REQ (1L<<5) | ||
2308 | |||
2309 | #define BNX2_RBUF_STATUS1 0x00200004 | ||
2310 | #define BNX2_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0) | ||
2311 | |||
2312 | #define BNX2_RBUF_STATUS2 0x00200008 | ||
2313 | #define BNX2_RBUF_STATUS2_FREE_TAIL (0x3ffL<<0) | ||
2314 | #define BNX2_RBUF_STATUS2_FREE_HEAD (0x3ffL<<16) | ||
2315 | |||
2316 | #define BNX2_RBUF_CONFIG 0x0020000c | ||
2317 | #define BNX2_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0) | ||
2318 | #define BNX2_RBUF_CONFIG_XON_TRIP (0x3ffL<<16) | ||
2319 | |||
2320 | #define BNX2_RBUF_FW_BUF_ALLOC 0x00200010 | ||
2321 | #define BNX2_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7) | ||
2322 | |||
2323 | #define BNX2_RBUF_FW_BUF_FREE 0x00200014 | ||
2324 | #define BNX2_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0) | ||
2325 | #define BNX2_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7) | ||
2326 | #define BNX2_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16) | ||
2327 | |||
2328 | #define BNX2_RBUF_FW_BUF_SEL 0x00200018 | ||
2329 | #define BNX2_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0) | ||
2330 | #define BNX2_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7) | ||
2331 | #define BNX2_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16) | ||
2332 | |||
2333 | #define BNX2_RBUF_CONFIG2 0x0020001c | ||
2334 | #define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0) | ||
2335 | #define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16) | ||
2336 | |||
2337 | #define BNX2_RBUF_CONFIG3 0x00200020 | ||
2338 | #define BNX2_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0) | ||
2339 | #define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16) | ||
2340 | |||
2341 | #define BNX2_RBUF_PKT_DATA 0x00208000 | ||
2342 | #define BNX2_RBUF_CLIST_DATA 0x00210000 | ||
2343 | #define BNX2_RBUF_BUF_DATA 0x00220000 | ||
2344 | |||
2345 | |||
2346 | /* | ||
2347 | * rv2p_reg definition | ||
2348 | * offset: 0x2800 | ||
2349 | */ | ||
2350 | #define BNX2_RV2P_COMMAND 0x00002800 | ||
2351 | #define BNX2_RV2P_COMMAND_ENABLED (1L<<0) | ||
2352 | #define BNX2_RV2P_COMMAND_PROC1_INTRPT (1L<<1) | ||
2353 | #define BNX2_RV2P_COMMAND_PROC2_INTRPT (1L<<2) | ||
2354 | #define BNX2_RV2P_COMMAND_ABORT0 (1L<<4) | ||
2355 | #define BNX2_RV2P_COMMAND_ABORT1 (1L<<5) | ||
2356 | #define BNX2_RV2P_COMMAND_ABORT2 (1L<<6) | ||
2357 | #define BNX2_RV2P_COMMAND_ABORT3 (1L<<7) | ||
2358 | #define BNX2_RV2P_COMMAND_ABORT4 (1L<<8) | ||
2359 | #define BNX2_RV2P_COMMAND_ABORT5 (1L<<9) | ||
2360 | #define BNX2_RV2P_COMMAND_PROC1_RESET (1L<<16) | ||
2361 | #define BNX2_RV2P_COMMAND_PROC2_RESET (1L<<17) | ||
2362 | #define BNX2_RV2P_COMMAND_CTXIF_RESET (1L<<18) | ||
2363 | |||
2364 | #define BNX2_RV2P_STATUS 0x00002804 | ||
2365 | #define BNX2_RV2P_STATUS_ALWAYS_0 (1L<<0) | ||
2366 | #define BNX2_RV2P_STATUS_RV2P_GEN_STAT0_CNT (1L<<8) | ||
2367 | #define BNX2_RV2P_STATUS_RV2P_GEN_STAT1_CNT (1L<<9) | ||
2368 | #define BNX2_RV2P_STATUS_RV2P_GEN_STAT2_CNT (1L<<10) | ||
2369 | #define BNX2_RV2P_STATUS_RV2P_GEN_STAT3_CNT (1L<<11) | ||
2370 | #define BNX2_RV2P_STATUS_RV2P_GEN_STAT4_CNT (1L<<12) | ||
2371 | #define BNX2_RV2P_STATUS_RV2P_GEN_STAT5_CNT (1L<<13) | ||
2372 | |||
2373 | #define BNX2_RV2P_CONFIG 0x00002808 | ||
2374 | #define BNX2_RV2P_CONFIG_STALL_PROC1 (1L<<0) | ||
2375 | #define BNX2_RV2P_CONFIG_STALL_PROC2 (1L<<1) | ||
2376 | #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1L<<8) | ||
2377 | #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1L<<9) | ||
2378 | #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1L<<10) | ||
2379 | #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1L<<11) | ||
2380 | #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1L<<12) | ||
2381 | #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1L<<13) | ||
2382 | #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1L<<16) | ||
2383 | #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1L<<17) | ||
2384 | #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1L<<18) | ||
2385 | #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1L<<19) | ||
2386 | #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1L<<20) | ||
2387 | #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1L<<21) | ||
2388 | #define BNX2_RV2P_CONFIG_PAGE_SIZE (0xfL<<24) | ||
2389 | #define BNX2_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24) | ||
2390 | #define BNX2_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24) | ||
2391 | #define BNX2_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24) | ||
2392 | #define BNX2_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24) | ||
2393 | #define BNX2_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24) | ||
2394 | #define BNX2_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24) | ||
2395 | #define BNX2_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24) | ||
2396 | #define BNX2_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24) | ||
2397 | #define BNX2_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24) | ||
2398 | #define BNX2_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24) | ||
2399 | #define BNX2_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24) | ||
2400 | #define BNX2_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24) | ||
2401 | #define BNX2_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24) | ||
2402 | |||
2403 | #define BNX2_RV2P_GEN_BFR_ADDR_0 0x00002810 | ||
2404 | #define BNX2_RV2P_GEN_BFR_ADDR_0_VALUE (0xffffL<<16) | ||
2405 | |||
2406 | #define BNX2_RV2P_GEN_BFR_ADDR_1 0x00002814 | ||
2407 | #define BNX2_RV2P_GEN_BFR_ADDR_1_VALUE (0xffffL<<16) | ||
2408 | |||
2409 | #define BNX2_RV2P_GEN_BFR_ADDR_2 0x00002818 | ||
2410 | #define BNX2_RV2P_GEN_BFR_ADDR_2_VALUE (0xffffL<<16) | ||
2411 | |||
2412 | #define BNX2_RV2P_GEN_BFR_ADDR_3 0x0000281c | ||
2413 | #define BNX2_RV2P_GEN_BFR_ADDR_3_VALUE (0xffffL<<16) | ||
2414 | |||
2415 | #define BNX2_RV2P_INSTR_HIGH 0x00002830 | ||
2416 | #define BNX2_RV2P_INSTR_HIGH_HIGH (0x1fL<<0) | ||
2417 | |||
2418 | #define BNX2_RV2P_INSTR_LOW 0x00002834 | ||
2419 | #define BNX2_RV2P_PROC1_ADDR_CMD 0x00002838 | ||
2420 | #define BNX2_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0) | ||
2421 | #define BNX2_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31) | ||
2422 | |||
2423 | #define BNX2_RV2P_PROC2_ADDR_CMD 0x0000283c | ||
2424 | #define BNX2_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0) | ||
2425 | #define BNX2_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31) | ||
2426 | |||
2427 | #define BNX2_RV2P_PROC1_GRC_DEBUG 0x00002840 | ||
2428 | #define BNX2_RV2P_PROC2_GRC_DEBUG 0x00002844 | ||
2429 | #define BNX2_RV2P_GRC_PROC_DEBUG 0x00002848 | ||
2430 | #define BNX2_RV2P_DEBUG_VECT_PEEK 0x0000284c | ||
2431 | #define BNX2_RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) | ||
2432 | #define BNX2_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) | ||
2433 | #define BNX2_RV2P_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) | ||
2434 | #define BNX2_RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) | ||
2435 | #define BNX2_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) | ||
2436 | #define BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) | ||
2437 | |||
2438 | #define BNX2_RV2P_PFTQ_DATA 0x00002b40 | ||
2439 | #define BNX2_RV2P_PFTQ_CMD 0x00002b78 | ||
2440 | #define BNX2_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0) | ||
2441 | #define BNX2_RV2P_PFTQ_CMD_WR_TOP (1L<<10) | ||
2442 | #define BNX2_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10) | ||
2443 | #define BNX2_RV2P_PFTQ_CMD_WR_TOP_1 (1L<<10) | ||
2444 | #define BNX2_RV2P_PFTQ_CMD_SFT_RESET (1L<<25) | ||
2445 | #define BNX2_RV2P_PFTQ_CMD_RD_DATA (1L<<26) | ||
2446 | #define BNX2_RV2P_PFTQ_CMD_ADD_INTERVEN (1L<<27) | ||
2447 | #define BNX2_RV2P_PFTQ_CMD_ADD_DATA (1L<<28) | ||
2448 | #define BNX2_RV2P_PFTQ_CMD_INTERVENE_CLR (1L<<29) | ||
2449 | #define BNX2_RV2P_PFTQ_CMD_POP (1L<<30) | ||
2450 | #define BNX2_RV2P_PFTQ_CMD_BUSY (1L<<31) | ||
2451 | |||
2452 | #define BNX2_RV2P_PFTQ_CTL 0x00002b7c | ||
2453 | #define BNX2_RV2P_PFTQ_CTL_INTERVENE (1L<<0) | ||
2454 | #define BNX2_RV2P_PFTQ_CTL_OVERFLOW (1L<<1) | ||
2455 | #define BNX2_RV2P_PFTQ_CTL_FORCE_INTERVENE (1L<<2) | ||
2456 | #define BNX2_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12) | ||
2457 | #define BNX2_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22) | ||
2458 | |||
2459 | #define BNX2_RV2P_TFTQ_DATA 0x00002b80 | ||
2460 | #define BNX2_RV2P_TFTQ_CMD 0x00002bb8 | ||
2461 | #define BNX2_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0) | ||
2462 | #define BNX2_RV2P_TFTQ_CMD_WR_TOP (1L<<10) | ||
2463 | #define BNX2_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10) | ||
2464 | #define BNX2_RV2P_TFTQ_CMD_WR_TOP_1 (1L<<10) | ||
2465 | #define BNX2_RV2P_TFTQ_CMD_SFT_RESET (1L<<25) | ||
2466 | #define BNX2_RV2P_TFTQ_CMD_RD_DATA (1L<<26) | ||
2467 | #define BNX2_RV2P_TFTQ_CMD_ADD_INTERVEN (1L<<27) | ||
2468 | #define BNX2_RV2P_TFTQ_CMD_ADD_DATA (1L<<28) | ||
2469 | #define BNX2_RV2P_TFTQ_CMD_INTERVENE_CLR (1L<<29) | ||
2470 | #define BNX2_RV2P_TFTQ_CMD_POP (1L<<30) | ||
2471 | #define BNX2_RV2P_TFTQ_CMD_BUSY (1L<<31) | ||
2472 | |||
2473 | #define BNX2_RV2P_TFTQ_CTL 0x00002bbc | ||
2474 | #define BNX2_RV2P_TFTQ_CTL_INTERVENE (1L<<0) | ||
2475 | #define BNX2_RV2P_TFTQ_CTL_OVERFLOW (1L<<1) | ||
2476 | #define BNX2_RV2P_TFTQ_CTL_FORCE_INTERVENE (1L<<2) | ||
2477 | #define BNX2_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12) | ||
2478 | #define BNX2_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22) | ||
2479 | |||
2480 | #define BNX2_RV2P_MFTQ_DATA 0x00002bc0 | ||
2481 | #define BNX2_RV2P_MFTQ_CMD 0x00002bf8 | ||
2482 | #define BNX2_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0) | ||
2483 | #define BNX2_RV2P_MFTQ_CMD_WR_TOP (1L<<10) | ||
2484 | #define BNX2_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10) | ||
2485 | #define BNX2_RV2P_MFTQ_CMD_WR_TOP_1 (1L<<10) | ||
2486 | #define BNX2_RV2P_MFTQ_CMD_SFT_RESET (1L<<25) | ||
2487 | #define BNX2_RV2P_MFTQ_CMD_RD_DATA (1L<<26) | ||
2488 | #define BNX2_RV2P_MFTQ_CMD_ADD_INTERVEN (1L<<27) | ||
2489 | #define BNX2_RV2P_MFTQ_CMD_ADD_DATA (1L<<28) | ||
2490 | #define BNX2_RV2P_MFTQ_CMD_INTERVENE_CLR (1L<<29) | ||
2491 | #define BNX2_RV2P_MFTQ_CMD_POP (1L<<30) | ||
2492 | #define BNX2_RV2P_MFTQ_CMD_BUSY (1L<<31) | ||
2493 | |||
2494 | #define BNX2_RV2P_MFTQ_CTL 0x00002bfc | ||
2495 | #define BNX2_RV2P_MFTQ_CTL_INTERVENE (1L<<0) | ||
2496 | #define BNX2_RV2P_MFTQ_CTL_OVERFLOW (1L<<1) | ||
2497 | #define BNX2_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2) | ||
2498 | #define BNX2_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12) | ||
2499 | #define BNX2_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22) | ||
2500 | |||
2501 | |||
2502 | |||
2503 | /* | ||
2504 | * mq_reg definition | ||
2505 | * offset: 0x3c00 | ||
2506 | */ | ||
2507 | #define BNX2_MQ_COMMAND 0x00003c00 | ||
2508 | #define BNX2_MQ_COMMAND_ENABLED (1L<<0) | ||
2509 | #define BNX2_MQ_COMMAND_OVERFLOW (1L<<4) | ||
2510 | #define BNX2_MQ_COMMAND_WR_ERROR (1L<<5) | ||
2511 | #define BNX2_MQ_COMMAND_RD_ERROR (1L<<6) | ||
2512 | |||
2513 | #define BNX2_MQ_STATUS 0x00003c04 | ||
2514 | #define BNX2_MQ_STATUS_CTX_ACCESS_STAT (1L<<16) | ||
2515 | #define BNX2_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17) | ||
2516 | #define BNX2_MQ_STATUS_PCI_STALL_STAT (1L<<18) | ||
2517 | |||
2518 | #define BNX2_MQ_CONFIG 0x00003c08 | ||
2519 | #define BNX2_MQ_CONFIG_TX_HIGH_PRI (1L<<0) | ||
2520 | #define BNX2_MQ_CONFIG_HALT_DIS (1L<<1) | ||
2521 | #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4) | ||
2522 | #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4) | ||
2523 | #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4) | ||
2524 | #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4) | ||
2525 | #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4) | ||
2526 | #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4) | ||
2527 | #define BNX2_MQ_CONFIG_MAX_DEPTH (0x7fL<<8) | ||
2528 | #define BNX2_MQ_CONFIG_CUR_DEPTH (0x7fL<<20) | ||
2529 | |||
2530 | #define BNX2_MQ_ENQUEUE1 0x00003c0c | ||
2531 | #define BNX2_MQ_ENQUEUE1_OFFSET (0x3fL<<2) | ||
2532 | #define BNX2_MQ_ENQUEUE1_CID (0x3fffL<<8) | ||
2533 | #define BNX2_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24) | ||
2534 | #define BNX2_MQ_ENQUEUE1_KNL_MODE (1L<<28) | ||
2535 | |||
2536 | #define BNX2_MQ_ENQUEUE2 0x00003c10 | ||
2537 | #define BNX2_MQ_BAD_WR_ADDR 0x00003c14 | ||
2538 | #define BNX2_MQ_BAD_RD_ADDR 0x00003c18 | ||
2539 | #define BNX2_MQ_KNL_BYP_WIND_START 0x00003c1c | ||
2540 | #define BNX2_MQ_KNL_BYP_WIND_START_VALUE (0xfffffL<<12) | ||
2541 | |||
2542 | #define BNX2_MQ_KNL_WIND_END 0x00003c20 | ||
2543 | #define BNX2_MQ_KNL_WIND_END_VALUE (0xffffffL<<8) | ||
2544 | |||
2545 | #define BNX2_MQ_KNL_WRITE_MASK1 0x00003c24 | ||
2546 | #define BNX2_MQ_KNL_TX_MASK1 0x00003c28 | ||
2547 | #define BNX2_MQ_KNL_CMD_MASK1 0x00003c2c | ||
2548 | #define BNX2_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30 | ||
2549 | #define BNX2_MQ_KNL_RX_V2P_MASK1 0x00003c34 | ||
2550 | #define BNX2_MQ_KNL_WRITE_MASK2 0x00003c38 | ||
2551 | #define BNX2_MQ_KNL_TX_MASK2 0x00003c3c | ||
2552 | #define BNX2_MQ_KNL_CMD_MASK2 0x00003c40 | ||
2553 | #define BNX2_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44 | ||
2554 | #define BNX2_MQ_KNL_RX_V2P_MASK2 0x00003c48 | ||
2555 | #define BNX2_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c | ||
2556 | #define BNX2_MQ_KNL_BYP_TX_MASK1 0x00003c50 | ||
2557 | #define BNX2_MQ_KNL_BYP_CMD_MASK1 0x00003c54 | ||
2558 | #define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK1 0x00003c58 | ||
2559 | #define BNX2_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c | ||
2560 | #define BNX2_MQ_KNL_BYP_WRITE_MASK2 0x00003c60 | ||
2561 | #define BNX2_MQ_KNL_BYP_TX_MASK2 0x00003c64 | ||
2562 | #define BNX2_MQ_KNL_BYP_CMD_MASK2 0x00003c68 | ||
2563 | #define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK2 0x00003c6c | ||
2564 | #define BNX2_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70 | ||
2565 | #define BNX2_MQ_MEM_WR_ADDR 0x00003c74 | ||
2566 | #define BNX2_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0) | ||
2567 | |||
2568 | #define BNX2_MQ_MEM_WR_DATA0 0x00003c78 | ||
2569 | #define BNX2_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0) | ||
2570 | |||
2571 | #define BNX2_MQ_MEM_WR_DATA1 0x00003c7c | ||
2572 | #define BNX2_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0) | ||
2573 | |||
2574 | #define BNX2_MQ_MEM_WR_DATA2 0x00003c80 | ||
2575 | #define BNX2_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0) | ||
2576 | |||
2577 | #define BNX2_MQ_MEM_RD_ADDR 0x00003c84 | ||
2578 | #define BNX2_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0) | ||
2579 | |||
2580 | #define BNX2_MQ_MEM_RD_DATA0 0x00003c88 | ||
2581 | #define BNX2_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0) | ||
2582 | |||
2583 | #define BNX2_MQ_MEM_RD_DATA1 0x00003c8c | ||
2584 | #define BNX2_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0) | ||
2585 | |||
2586 | #define BNX2_MQ_MEM_RD_DATA2 0x00003c90 | ||
2587 | #define BNX2_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0) | ||
2588 | |||
2589 | |||
2590 | |||
2591 | /* | ||
2592 | * tbdr_reg definition | ||
2593 | * offset: 0x5000 | ||
2594 | */ | ||
2595 | #define BNX2_TBDR_COMMAND 0x00005000 | ||
2596 | #define BNX2_TBDR_COMMAND_ENABLE (1L<<0) | ||
2597 | #define BNX2_TBDR_COMMAND_SOFT_RST (1L<<1) | ||
2598 | #define BNX2_TBDR_COMMAND_MSTR_ABORT (1L<<4) | ||
2599 | |||
2600 | #define BNX2_TBDR_STATUS 0x00005004 | ||
2601 | #define BNX2_TBDR_STATUS_DMA_WAIT (1L<<0) | ||
2602 | #define BNX2_TBDR_STATUS_FTQ_WAIT (1L<<1) | ||
2603 | #define BNX2_TBDR_STATUS_FIFO_OVERFLOW (1L<<2) | ||
2604 | #define BNX2_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3) | ||
2605 | #define BNX2_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4) | ||
2606 | #define BNX2_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5) | ||
2607 | #define BNX2_TBDR_STATUS_BURST_CNT (1L<<6) | ||
2608 | |||
2609 | #define BNX2_TBDR_CONFIG 0x00005008 | ||
2610 | #define BNX2_TBDR_CONFIG_MAX_BDS (0xffL<<0) | ||
2611 | #define BNX2_TBDR_CONFIG_SWAP_MODE (1L<<8) | ||
2612 | #define BNX2_TBDR_CONFIG_PRIORITY (1L<<9) | ||
2613 | #define BNX2_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10) | ||
2614 | #define BNX2_TBDR_CONFIG_PAGE_SIZE (0xfL<<24) | ||
2615 | #define BNX2_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24) | ||
2616 | #define BNX2_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24) | ||
2617 | #define BNX2_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24) | ||
2618 | #define BNX2_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24) | ||
2619 | #define BNX2_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24) | ||
2620 | #define BNX2_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24) | ||
2621 | #define BNX2_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24) | ||
2622 | #define BNX2_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24) | ||
2623 | #define BNX2_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24) | ||
2624 | #define BNX2_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24) | ||
2625 | #define BNX2_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24) | ||
2626 | #define BNX2_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24) | ||
2627 | #define BNX2_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24) | ||
2628 | |||
2629 | #define BNX2_TBDR_DEBUG_VECT_PEEK 0x0000500c | ||
2630 | #define BNX2_TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) | ||
2631 | #define BNX2_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) | ||
2632 | #define BNX2_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) | ||
2633 | #define BNX2_TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) | ||
2634 | #define BNX2_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) | ||
2635 | #define BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) | ||
2636 | |||
2637 | #define BNX2_TBDR_FTQ_DATA 0x000053c0 | ||
2638 | #define BNX2_TBDR_FTQ_CMD 0x000053f8 | ||
2639 | #define BNX2_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0) | ||
2640 | #define BNX2_TBDR_FTQ_CMD_WR_TOP (1L<<10) | ||
2641 | #define BNX2_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10) | ||
2642 | #define BNX2_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10) | ||
2643 | #define BNX2_TBDR_FTQ_CMD_SFT_RESET (1L<<25) | ||
2644 | #define BNX2_TBDR_FTQ_CMD_RD_DATA (1L<<26) | ||
2645 | #define BNX2_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27) | ||
2646 | #define BNX2_TBDR_FTQ_CMD_ADD_DATA (1L<<28) | ||
2647 | #define BNX2_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29) | ||
2648 | #define BNX2_TBDR_FTQ_CMD_POP (1L<<30) | ||
2649 | #define BNX2_TBDR_FTQ_CMD_BUSY (1L<<31) | ||
2650 | |||
2651 | #define BNX2_TBDR_FTQ_CTL 0x000053fc | ||
2652 | #define BNX2_TBDR_FTQ_CTL_INTERVENE (1L<<0) | ||
2653 | #define BNX2_TBDR_FTQ_CTL_OVERFLOW (1L<<1) | ||
2654 | #define BNX2_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2) | ||
2655 | #define BNX2_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) | ||
2656 | #define BNX2_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) | ||
2657 | |||
2658 | |||
2659 | |||
2660 | /* | ||
2661 | * tdma_reg definition | ||
2662 | * offset: 0x5c00 | ||
2663 | */ | ||
2664 | #define BNX2_TDMA_COMMAND 0x00005c00 | ||
2665 | #define BNX2_TDMA_COMMAND_ENABLED (1L<<0) | ||
2666 | #define BNX2_TDMA_COMMAND_MASTER_ABORT (1L<<4) | ||
2667 | #define BNX2_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7) | ||
2668 | |||
2669 | #define BNX2_TDMA_STATUS 0x00005c04 | ||
2670 | #define BNX2_TDMA_STATUS_DMA_WAIT (1L<<0) | ||
2671 | #define BNX2_TDMA_STATUS_PAYLOAD_WAIT (1L<<1) | ||
2672 | #define BNX2_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2) | ||
2673 | #define BNX2_TDMA_STATUS_LOCK_WAIT (1L<<3) | ||
2674 | #define BNX2_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16) | ||
2675 | #define BNX2_TDMA_STATUS_BURST_CNT (1L<<17) | ||
2676 | |||
2677 | #define BNX2_TDMA_CONFIG 0x00005c08 | ||
2678 | #define BNX2_TDMA_CONFIG_ONE_DMA (1L<<0) | ||
2679 | #define BNX2_TDMA_CONFIG_ONE_RECORD (1L<<1) | ||
2680 | #define BNX2_TDMA_CONFIG_LIMIT_SZ (0xfL<<4) | ||
2681 | #define BNX2_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4) | ||
2682 | #define BNX2_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4) | ||
2683 | #define BNX2_TDMA_CONFIG_LIMIT_SZ_256 (0x6L<<4) | ||
2684 | #define BNX2_TDMA_CONFIG_LIMIT_SZ_512 (0x8L<<4) | ||
2685 | #define BNX2_TDMA_CONFIG_LINE_SZ (0xfL<<8) | ||
2686 | #define BNX2_TDMA_CONFIG_LINE_SZ_64 (0L<<8) | ||
2687 | #define BNX2_TDMA_CONFIG_LINE_SZ_128 (4L<<8) | ||
2688 | #define BNX2_TDMA_CONFIG_LINE_SZ_256 (6L<<8) | ||
2689 | #define BNX2_TDMA_CONFIG_LINE_SZ_512 (8L<<8) | ||
2690 | #define BNX2_TDMA_CONFIG_ALIGN_ENA (1L<<15) | ||
2691 | #define BNX2_TDMA_CONFIG_CHK_L2_BD (1L<<16) | ||
2692 | #define BNX2_TDMA_CONFIG_FIFO_CMP (0xfL<<20) | ||
2693 | |||
2694 | #define BNX2_TDMA_PAYLOAD_PROD 0x00005c0c | ||
2695 | #define BNX2_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3) | ||
2696 | |||
2697 | #define BNX2_TDMA_DBG_WATCHDOG 0x00005c10 | ||
2698 | #define BNX2_TDMA_DBG_TRIGGER 0x00005c14 | ||
2699 | #define BNX2_TDMA_DMAD_FSM 0x00005c80 | ||
2700 | #define BNX2_TDMA_DMAD_FSM_BD_INVLD (1L<<0) | ||
2701 | #define BNX2_TDMA_DMAD_FSM_PUSH (0xfL<<4) | ||
2702 | #define BNX2_TDMA_DMAD_FSM_ARB_TBDC (0x3L<<8) | ||
2703 | #define BNX2_TDMA_DMAD_FSM_ARB_CTX (1L<<12) | ||
2704 | #define BNX2_TDMA_DMAD_FSM_DR_INTF (1L<<16) | ||
2705 | #define BNX2_TDMA_DMAD_FSM_DMAD (0x7L<<20) | ||
2706 | #define BNX2_TDMA_DMAD_FSM_BD (0xfL<<24) | ||
2707 | |||
2708 | #define BNX2_TDMA_DMAD_STATUS 0x00005c84 | ||
2709 | #define BNX2_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY (0x3L<<0) | ||
2710 | #define BNX2_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY (0x3L<<4) | ||
2711 | #define BNX2_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY (0x3L<<8) | ||
2712 | #define BNX2_TDMA_DMAD_STATUS_IFTQ_ENUM (0xfL<<12) | ||
2713 | |||
2714 | #define BNX2_TDMA_DR_INTF_FSM 0x00005c88 | ||
2715 | #define BNX2_TDMA_DR_INTF_FSM_L2_COMP (0x3L<<0) | ||
2716 | #define BNX2_TDMA_DR_INTF_FSM_TPATQ (0x7L<<4) | ||
2717 | #define BNX2_TDMA_DR_INTF_FSM_TPBUF (0x3L<<8) | ||
2718 | #define BNX2_TDMA_DR_INTF_FSM_DR_BUF (0x7L<<12) | ||
2719 | #define BNX2_TDMA_DR_INTF_FSM_DMAD (0x7L<<16) | ||
2720 | |||
2721 | #define BNX2_TDMA_DR_INTF_STATUS 0x00005c8c | ||
2722 | #define BNX2_TDMA_DR_INTF_STATUS_HOLE_PHASE (0x7L<<0) | ||
2723 | #define BNX2_TDMA_DR_INTF_STATUS_DATA_AVAIL (0x3L<<4) | ||
2724 | #define BNX2_TDMA_DR_INTF_STATUS_SHIFT_ADDR (0x7L<<8) | ||
2725 | #define BNX2_TDMA_DR_INTF_STATUS_NXT_PNTR (0xfL<<12) | ||
2726 | #define BNX2_TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7L<<16) | ||
2727 | |||
2728 | #define BNX2_TDMA_FTQ_DATA 0x00005fc0 | ||
2729 | #define BNX2_TDMA_FTQ_CMD 0x00005ff8 | ||
2730 | #define BNX2_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0) | ||
2731 | #define BNX2_TDMA_FTQ_CMD_WR_TOP (1L<<10) | ||
2732 | #define BNX2_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10) | ||
2733 | #define BNX2_TDMA_FTQ_CMD_WR_TOP_1 (1L<<10) | ||
2734 | #define BNX2_TDMA_FTQ_CMD_SFT_RESET (1L<<25) | ||
2735 | #define BNX2_TDMA_FTQ_CMD_RD_DATA (1L<<26) | ||
2736 | #define BNX2_TDMA_FTQ_CMD_ADD_INTERVEN (1L<<27) | ||
2737 | #define BNX2_TDMA_FTQ_CMD_ADD_DATA (1L<<28) | ||
2738 | #define BNX2_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29) | ||
2739 | #define BNX2_TDMA_FTQ_CMD_POP (1L<<30) | ||
2740 | #define BNX2_TDMA_FTQ_CMD_BUSY (1L<<31) | ||
2741 | |||
2742 | #define BNX2_TDMA_FTQ_CTL 0x00005ffc | ||
2743 | #define BNX2_TDMA_FTQ_CTL_INTERVENE (1L<<0) | ||
2744 | #define BNX2_TDMA_FTQ_CTL_OVERFLOW (1L<<1) | ||
2745 | #define BNX2_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2) | ||
2746 | #define BNX2_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) | ||
2747 | #define BNX2_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) | ||
2748 | |||
2749 | |||
2750 | |||
2751 | /* | ||
2752 | * hc_reg definition | ||
2753 | * offset: 0x6800 | ||
2754 | */ | ||
2755 | #define BNX2_HC_COMMAND 0x00006800 | ||
2756 | #define BNX2_HC_COMMAND_ENABLE (1L<<0) | ||
2757 | #define BNX2_HC_COMMAND_SKIP_ABORT (1L<<4) | ||
2758 | #define BNX2_HC_COMMAND_COAL_NOW (1L<<16) | ||
2759 | #define BNX2_HC_COMMAND_COAL_NOW_WO_INT (1L<<17) | ||
2760 | #define BNX2_HC_COMMAND_STATS_NOW (1L<<18) | ||
2761 | #define BNX2_HC_COMMAND_FORCE_INT (0x3L<<19) | ||
2762 | #define BNX2_HC_COMMAND_FORCE_INT_NULL (0L<<19) | ||
2763 | #define BNX2_HC_COMMAND_FORCE_INT_HIGH (1L<<19) | ||
2764 | #define BNX2_HC_COMMAND_FORCE_INT_LOW (2L<<19) | ||
2765 | #define BNX2_HC_COMMAND_FORCE_INT_FREE (3L<<19) | ||
2766 | #define BNX2_HC_COMMAND_CLR_STAT_NOW (1L<<21) | ||
2767 | |||
2768 | #define BNX2_HC_STATUS 0x00006804 | ||
2769 | #define BNX2_HC_STATUS_MASTER_ABORT (1L<<0) | ||
2770 | #define BNX2_HC_STATUS_PARITY_ERROR_STATE (1L<<1) | ||
2771 | #define BNX2_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16) | ||
2772 | #define BNX2_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17) | ||
2773 | #define BNX2_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18) | ||
2774 | #define BNX2_HC_STATUS_NUM_INT_GEN_STAT (1L<<19) | ||
2775 | #define BNX2_HC_STATUS_NUM_INT_MBOX_WR_STAT (1L<<20) | ||
2776 | #define BNX2_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1L<<23) | ||
2777 | #define BNX2_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1L<<24) | ||
2778 | #define BNX2_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1L<<25) | ||
2779 | |||
2780 | #define BNX2_HC_CONFIG 0x00006808 | ||
2781 | #define BNX2_HC_CONFIG_COLLECT_STATS (1L<<0) | ||
2782 | #define BNX2_HC_CONFIG_RX_TMR_MODE (1L<<1) | ||
2783 | #define BNX2_HC_CONFIG_TX_TMR_MODE (1L<<2) | ||
2784 | #define BNX2_HC_CONFIG_COM_TMR_MODE (1L<<3) | ||
2785 | #define BNX2_HC_CONFIG_CMD_TMR_MODE (1L<<4) | ||
2786 | #define BNX2_HC_CONFIG_STATISTIC_PRIORITY (1L<<5) | ||
2787 | #define BNX2_HC_CONFIG_STATUS_PRIORITY (1L<<6) | ||
2788 | #define BNX2_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8) | ||
2789 | |||
2790 | #define BNX2_HC_ATTN_BITS_ENABLE 0x0000680c | ||
2791 | #define BNX2_HC_STATUS_ADDR_L 0x00006810 | ||
2792 | #define BNX2_HC_STATUS_ADDR_H 0x00006814 | ||
2793 | #define BNX2_HC_STATISTICS_ADDR_L 0x00006818 | ||
2794 | #define BNX2_HC_STATISTICS_ADDR_H 0x0000681c | ||
2795 | #define BNX2_HC_TX_QUICK_CONS_TRIP 0x00006820 | ||
2796 | #define BNX2_HC_TX_QUICK_CONS_TRIP_VALUE (0xffL<<0) | ||
2797 | #define BNX2_HC_TX_QUICK_CONS_TRIP_INT (0xffL<<16) | ||
2798 | |||
2799 | #define BNX2_HC_COMP_PROD_TRIP 0x00006824 | ||
2800 | #define BNX2_HC_COMP_PROD_TRIP_VALUE (0xffL<<0) | ||
2801 | #define BNX2_HC_COMP_PROD_TRIP_INT (0xffL<<16) | ||
2802 | |||
2803 | #define BNX2_HC_RX_QUICK_CONS_TRIP 0x00006828 | ||
2804 | #define BNX2_HC_RX_QUICK_CONS_TRIP_VALUE (0xffL<<0) | ||
2805 | #define BNX2_HC_RX_QUICK_CONS_TRIP_INT (0xffL<<16) | ||
2806 | |||
2807 | #define BNX2_HC_RX_TICKS 0x0000682c | ||
2808 | #define BNX2_HC_RX_TICKS_VALUE (0x3ffL<<0) | ||
2809 | #define BNX2_HC_RX_TICKS_INT (0x3ffL<<16) | ||
2810 | |||
2811 | #define BNX2_HC_TX_TICKS 0x00006830 | ||
2812 | #define BNX2_HC_TX_TICKS_VALUE (0x3ffL<<0) | ||
2813 | #define BNX2_HC_TX_TICKS_INT (0x3ffL<<16) | ||
2814 | |||
2815 | #define BNX2_HC_COM_TICKS 0x00006834 | ||
2816 | #define BNX2_HC_COM_TICKS_VALUE (0x3ffL<<0) | ||
2817 | #define BNX2_HC_COM_TICKS_INT (0x3ffL<<16) | ||
2818 | |||
2819 | #define BNX2_HC_CMD_TICKS 0x00006838 | ||
2820 | #define BNX2_HC_CMD_TICKS_VALUE (0x3ffL<<0) | ||
2821 | #define BNX2_HC_CMD_TICKS_INT (0x3ffL<<16) | ||
2822 | |||
2823 | #define BNX2_HC_PERIODIC_TICKS 0x0000683c | ||
2824 | #define BNX2_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0) | ||
2825 | |||
2826 | #define BNX2_HC_STAT_COLLECT_TICKS 0x00006840 | ||
2827 | #define BNX2_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4) | ||
2828 | |||
2829 | #define BNX2_HC_STATS_TICKS 0x00006844 | ||
2830 | #define BNX2_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8) | ||
2831 | |||
2832 | #define BNX2_HC_STAT_MEM_DATA 0x0000684c | ||
2833 | #define BNX2_HC_STAT_GEN_SEL_0 0x00006850 | ||
2834 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0) | ||
2835 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0) | ||
2836 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0) | ||
2837 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0) | ||
2838 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0) | ||
2839 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0) | ||
2840 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5L<<0) | ||
2841 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6L<<0) | ||
2842 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7L<<0) | ||
2843 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8L<<0) | ||
2844 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9L<<0) | ||
2845 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10L<<0) | ||
2846 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11L<<0) | ||
2847 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12L<<0) | ||
2848 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13L<<0) | ||
2849 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14L<<0) | ||
2850 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15L<<0) | ||
2851 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16L<<0) | ||
2852 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17L<<0) | ||
2853 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18L<<0) | ||
2854 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19L<<0) | ||
2855 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20L<<0) | ||
2856 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21L<<0) | ||
2857 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22L<<0) | ||
2858 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23L<<0) | ||
2859 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24L<<0) | ||
2860 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25L<<0) | ||
2861 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26L<<0) | ||
2862 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27L<<0) | ||
2863 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28L<<0) | ||
2864 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29L<<0) | ||
2865 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30L<<0) | ||
2866 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31L<<0) | ||
2867 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32L<<0) | ||
2868 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33L<<0) | ||
2869 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34L<<0) | ||
2870 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35L<<0) | ||
2871 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36L<<0) | ||
2872 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37L<<0) | ||
2873 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38L<<0) | ||
2874 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39L<<0) | ||
2875 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40L<<0) | ||
2876 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41L<<0) | ||
2877 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42L<<0) | ||
2878 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43L<<0) | ||
2879 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44L<<0) | ||
2880 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45L<<0) | ||
2881 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46L<<0) | ||
2882 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47L<<0) | ||
2883 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48L<<0) | ||
2884 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49L<<0) | ||
2885 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50L<<0) | ||
2886 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51L<<0) | ||
2887 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT (52L<<0) | ||
2888 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53L<<0) | ||
2889 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54L<<0) | ||
2890 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55L<<0) | ||
2891 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56L<<0) | ||
2892 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59L<<0) | ||
2893 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60L<<0) | ||
2894 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61L<<0) | ||
2895 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62L<<0) | ||
2896 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63L<<0) | ||
2897 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64L<<0) | ||
2898 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65L<<0) | ||
2899 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66L<<0) | ||
2900 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67L<<0) | ||
2901 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68L<<0) | ||
2902 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0) | ||
2903 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0) | ||
2904 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0) | ||
2905 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72L<<0) | ||
2906 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73L<<0) | ||
2907 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74L<<0) | ||
2908 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75L<<0) | ||
2909 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76L<<0) | ||
2910 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77L<<0) | ||
2911 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78L<<0) | ||
2912 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79L<<0) | ||
2913 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80L<<0) | ||
2914 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81L<<0) | ||
2915 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82L<<0) | ||
2916 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83L<<0) | ||
2917 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84L<<0) | ||
2918 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT (85L<<0) | ||
2919 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT (86L<<0) | ||
2920 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT (87L<<0) | ||
2921 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT (88L<<0) | ||
2922 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT (89L<<0) | ||
2923 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT (90L<<0) | ||
2924 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT (91L<<0) | ||
2925 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT (92L<<0) | ||
2926 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT (93L<<0) | ||
2927 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT (94L<<0) | ||
2928 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95L<<0) | ||
2929 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96L<<0) | ||
2930 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97L<<0) | ||
2931 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98L<<0) | ||
2932 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99L<<0) | ||
2933 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100L<<0) | ||
2934 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101L<<0) | ||
2935 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102L<<0) | ||
2936 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103L<<0) | ||
2937 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104L<<0) | ||
2938 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105L<<0) | ||
2939 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106L<<0) | ||
2940 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107L<<0) | ||
2941 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108L<<0) | ||
2942 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109L<<0) | ||
2943 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110L<<0) | ||
2944 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111L<<0) | ||
2945 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112L<<0) | ||
2946 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113L<<0) | ||
2947 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114L<<0) | ||
2948 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115L<<0) | ||
2949 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116L<<0) | ||
2950 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117L<<0) | ||
2951 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118L<<0) | ||
2952 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0) | ||
2953 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0) | ||
2954 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0) | ||
2955 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0) | ||
2956 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0) | ||
2957 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8) | ||
2958 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16) | ||
2959 | #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24) | ||
2960 | |||
2961 | #define BNX2_HC_STAT_GEN_SEL_1 0x00006854 | ||
2962 | #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0) | ||
2963 | #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8) | ||
2964 | #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16) | ||
2965 | #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24) | ||
2966 | |||
2967 | #define BNX2_HC_STAT_GEN_SEL_2 0x00006858 | ||
2968 | #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0) | ||
2969 | #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8) | ||
2970 | #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16) | ||
2971 | #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24) | ||
2972 | |||
2973 | #define BNX2_HC_STAT_GEN_SEL_3 0x0000685c | ||
2974 | #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0) | ||
2975 | #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8) | ||
2976 | #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16) | ||
2977 | #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24) | ||
2978 | |||
2979 | #define BNX2_HC_STAT_GEN_STAT0 0x00006888 | ||
2980 | #define BNX2_HC_STAT_GEN_STAT1 0x0000688c | ||
2981 | #define BNX2_HC_STAT_GEN_STAT2 0x00006890 | ||
2982 | #define BNX2_HC_STAT_GEN_STAT3 0x00006894 | ||
2983 | #define BNX2_HC_STAT_GEN_STAT4 0x00006898 | ||
2984 | #define BNX2_HC_STAT_GEN_STAT5 0x0000689c | ||
2985 | #define BNX2_HC_STAT_GEN_STAT6 0x000068a0 | ||
2986 | #define BNX2_HC_STAT_GEN_STAT7 0x000068a4 | ||
2987 | #define BNX2_HC_STAT_GEN_STAT8 0x000068a8 | ||
2988 | #define BNX2_HC_STAT_GEN_STAT9 0x000068ac | ||
2989 | #define BNX2_HC_STAT_GEN_STAT10 0x000068b0 | ||
2990 | #define BNX2_HC_STAT_GEN_STAT11 0x000068b4 | ||
2991 | #define BNX2_HC_STAT_GEN_STAT12 0x000068b8 | ||
2992 | #define BNX2_HC_STAT_GEN_STAT13 0x000068bc | ||
2993 | #define BNX2_HC_STAT_GEN_STAT14 0x000068c0 | ||
2994 | #define BNX2_HC_STAT_GEN_STAT15 0x000068c4 | ||
2995 | #define BNX2_HC_STAT_GEN_STAT_AC0 0x000068c8 | ||
2996 | #define BNX2_HC_STAT_GEN_STAT_AC1 0x000068cc | ||
2997 | #define BNX2_HC_STAT_GEN_STAT_AC2 0x000068d0 | ||
2998 | #define BNX2_HC_STAT_GEN_STAT_AC3 0x000068d4 | ||
2999 | #define BNX2_HC_STAT_GEN_STAT_AC4 0x000068d8 | ||
3000 | #define BNX2_HC_STAT_GEN_STAT_AC5 0x000068dc | ||
3001 | #define BNX2_HC_STAT_GEN_STAT_AC6 0x000068e0 | ||
3002 | #define BNX2_HC_STAT_GEN_STAT_AC7 0x000068e4 | ||
3003 | #define BNX2_HC_STAT_GEN_STAT_AC8 0x000068e8 | ||
3004 | #define BNX2_HC_STAT_GEN_STAT_AC9 0x000068ec | ||
3005 | #define BNX2_HC_STAT_GEN_STAT_AC10 0x000068f0 | ||
3006 | #define BNX2_HC_STAT_GEN_STAT_AC11 0x000068f4 | ||
3007 | #define BNX2_HC_STAT_GEN_STAT_AC12 0x000068f8 | ||
3008 | #define BNX2_HC_STAT_GEN_STAT_AC13 0x000068fc | ||
3009 | #define BNX2_HC_STAT_GEN_STAT_AC14 0x00006900 | ||
3010 | #define BNX2_HC_STAT_GEN_STAT_AC15 0x00006904 | ||
3011 | #define BNX2_HC_VIS 0x00006908 | ||
3012 | #define BNX2_HC_VIS_STAT_BUILD_STATE (0xfL<<0) | ||
3013 | #define BNX2_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0) | ||
3014 | #define BNX2_HC_VIS_STAT_BUILD_STATE_START (1L<<0) | ||
3015 | #define BNX2_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0) | ||
3016 | #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0) | ||
3017 | #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0) | ||
3018 | #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0) | ||
3019 | #define BNX2_HC_VIS_STAT_BUILD_STATE_DMA (6L<<0) | ||
3020 | #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7L<<0) | ||
3021 | #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_LOW (8L<<0) | ||
3022 | #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9L<<0) | ||
3023 | #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_DATA (10L<<0) | ||
3024 | #define BNX2_HC_VIS_DMA_STAT_STATE (0xfL<<8) | ||
3025 | #define BNX2_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8) | ||
3026 | #define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1L<<8) | ||
3027 | #define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_DMA (2L<<8) | ||
3028 | #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP (3L<<8) | ||
3029 | #define BNX2_HC_VIS_DMA_STAT_STATE_COMP (4L<<8) | ||
3030 | #define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5L<<8) | ||
3031 | #define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6L<<8) | ||
3032 | #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7L<<8) | ||
3033 | #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8L<<8) | ||
3034 | #define BNX2_HC_VIS_DMA_STAT_STATE_WAIT (9L<<8) | ||
3035 | #define BNX2_HC_VIS_DMA_STAT_STATE_ABORT (15L<<8) | ||
3036 | #define BNX2_HC_VIS_DMA_MSI_STATE (0x7L<<12) | ||
3037 | #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE (0x3L<<15) | ||
3038 | #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15) | ||
3039 | #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1L<<15) | ||
3040 | #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_START (2L<<15) | ||
3041 | |||
3042 | #define BNX2_HC_VIS_1 0x0000690c | ||
3043 | #define BNX2_HC_VIS_1_HW_INTACK_STATE (1L<<4) | ||
3044 | #define BNX2_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4) | ||
3045 | #define BNX2_HC_VIS_1_HW_INTACK_STATE_COUNT (1L<<4) | ||
3046 | #define BNX2_HC_VIS_1_SW_INTACK_STATE (1L<<5) | ||
3047 | #define BNX2_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5) | ||
3048 | #define BNX2_HC_VIS_1_SW_INTACK_STATE_COUNT (1L<<5) | ||
3049 | #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE (1L<<6) | ||
3050 | #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6) | ||
3051 | #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1L<<6) | ||
3052 | #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE (1L<<7) | ||
3053 | #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7) | ||
3054 | #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1L<<7) | ||
3055 | #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE (0xfL<<17) | ||
3056 | #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17) | ||
3057 | #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_DMA (1L<<17) | ||
3058 | #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2L<<17) | ||
3059 | #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3L<<17) | ||
3060 | #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4L<<17) | ||
3061 | #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5L<<17) | ||
3062 | #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6L<<17) | ||
3063 | #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7L<<17) | ||
3064 | #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE (0x3L<<21) | ||
3065 | #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21) | ||
3066 | #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1L<<21) | ||
3067 | #define BNX2_HC_VIS_1_INT_GEN_STATE (1L<<23) | ||
3068 | #define BNX2_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23) | ||
3069 | #define BNX2_HC_VIS_1_INT_GEN_STATE_NTERRUPT (1L<<23) | ||
3070 | #define BNX2_HC_VIS_1_STAT_CHAN_ID (0x7L<<24) | ||
3071 | #define BNX2_HC_VIS_1_INT_B (1L<<27) | ||
3072 | |||
3073 | #define BNX2_HC_DEBUG_VECT_PEEK 0x00006910 | ||
3074 | #define BNX2_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) | ||
3075 | #define BNX2_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) | ||
3076 | #define BNX2_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) | ||
3077 | #define BNX2_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) | ||
3078 | #define BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) | ||
3079 | #define BNX2_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) | ||
3080 | |||
3081 | |||
3082 | |||
3083 | /* | ||
3084 | * txp_reg definition | ||
3085 | * offset: 0x40000 | ||
3086 | */ | ||
3087 | #define BNX2_TXP_CPU_MODE 0x00045000 | ||
3088 | #define BNX2_TXP_CPU_MODE_LOCAL_RST (1L<<0) | ||
3089 | #define BNX2_TXP_CPU_MODE_STEP_ENA (1L<<1) | ||
3090 | #define BNX2_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) | ||
3091 | #define BNX2_TXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) | ||
3092 | #define BNX2_TXP_CPU_MODE_MSG_BIT1 (1L<<6) | ||
3093 | #define BNX2_TXP_CPU_MODE_INTERRUPT_ENA (1L<<7) | ||
3094 | #define BNX2_TXP_CPU_MODE_SOFT_HALT (1L<<10) | ||
3095 | #define BNX2_TXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) | ||
3096 | #define BNX2_TXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) | ||
3097 | #define BNX2_TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) | ||
3098 | #define BNX2_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) | ||
3099 | |||
3100 | #define BNX2_TXP_CPU_STATE 0x00045004 | ||
3101 | #define BNX2_TXP_CPU_STATE_BREAKPOINT (1L<<0) | ||
3102 | #define BNX2_TXP_CPU_STATE_BAD_INST_HALTED (1L<<2) | ||
3103 | #define BNX2_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) | ||
3104 | #define BNX2_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) | ||
3105 | #define BNX2_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) | ||
3106 | #define BNX2_TXP_CPU_STATE_BAD_pc_HALTED (1L<<6) | ||
3107 | #define BNX2_TXP_CPU_STATE_ALIGN_HALTED (1L<<7) | ||
3108 | #define BNX2_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) | ||
3109 | #define BNX2_TXP_CPU_STATE_SOFT_HALTED (1L<<10) | ||
3110 | #define BNX2_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) | ||
3111 | #define BNX2_TXP_CPU_STATE_INTERRRUPT (1L<<12) | ||
3112 | #define BNX2_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) | ||
3113 | #define BNX2_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15) | ||
3114 | #define BNX2_TXP_CPU_STATE_BLOCKED_READ (1L<<31) | ||
3115 | |||
3116 | #define BNX2_TXP_CPU_EVENT_MASK 0x00045008 | ||
3117 | #define BNX2_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) | ||
3118 | #define BNX2_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) | ||
3119 | #define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) | ||
3120 | #define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) | ||
3121 | #define BNX2_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) | ||
3122 | #define BNX2_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) | ||
3123 | #define BNX2_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) | ||
3124 | #define BNX2_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) | ||
3125 | #define BNX2_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) | ||
3126 | #define BNX2_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) | ||
3127 | #define BNX2_TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) | ||
3128 | |||
3129 | #define BNX2_TXP_CPU_PROGRAM_COUNTER 0x0004501c | ||
3130 | #define BNX2_TXP_CPU_INSTRUCTION 0x00045020 | ||
3131 | #define BNX2_TXP_CPU_DATA_ACCESS 0x00045024 | ||
3132 | #define BNX2_TXP_CPU_INTERRUPT_ENABLE 0x00045028 | ||
3133 | #define BNX2_TXP_CPU_INTERRUPT_VECTOR 0x0004502c | ||
3134 | #define BNX2_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030 | ||
3135 | #define BNX2_TXP_CPU_HW_BREAKPOINT 0x00045034 | ||
3136 | #define BNX2_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) | ||
3137 | #define BNX2_TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) | ||
3138 | |||
3139 | #define BNX2_TXP_CPU_DEBUG_VECT_PEEK 0x00045038 | ||
3140 | #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) | ||
3141 | #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) | ||
3142 | #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) | ||
3143 | #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) | ||
3144 | #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) | ||
3145 | #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) | ||
3146 | |||
3147 | #define BNX2_TXP_CPU_LAST_BRANCH_ADDR 0x00045048 | ||
3148 | #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) | ||
3149 | #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) | ||
3150 | #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) | ||
3151 | #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) | ||
3152 | |||
3153 | #define BNX2_TXP_CPU_REG_FILE 0x00045200 | ||
3154 | #define BNX2_TXP_FTQ_DATA 0x000453c0 | ||
3155 | #define BNX2_TXP_FTQ_CMD 0x000453f8 | ||
3156 | #define BNX2_TXP_FTQ_CMD_OFFSET (0x3ffL<<0) | ||
3157 | #define BNX2_TXP_FTQ_CMD_WR_TOP (1L<<10) | ||
3158 | #define BNX2_TXP_FTQ_CMD_WR_TOP_0 (0L<<10) | ||
3159 | #define BNX2_TXP_FTQ_CMD_WR_TOP_1 (1L<<10) | ||
3160 | #define BNX2_TXP_FTQ_CMD_SFT_RESET (1L<<25) | ||
3161 | #define BNX2_TXP_FTQ_CMD_RD_DATA (1L<<26) | ||
3162 | #define BNX2_TXP_FTQ_CMD_ADD_INTERVEN (1L<<27) | ||
3163 | #define BNX2_TXP_FTQ_CMD_ADD_DATA (1L<<28) | ||
3164 | #define BNX2_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29) | ||
3165 | #define BNX2_TXP_FTQ_CMD_POP (1L<<30) | ||
3166 | #define BNX2_TXP_FTQ_CMD_BUSY (1L<<31) | ||
3167 | |||
3168 | #define BNX2_TXP_FTQ_CTL 0x000453fc | ||
3169 | #define BNX2_TXP_FTQ_CTL_INTERVENE (1L<<0) | ||
3170 | #define BNX2_TXP_FTQ_CTL_OVERFLOW (1L<<1) | ||
3171 | #define BNX2_TXP_FTQ_CTL_FORCE_INTERVENE (1L<<2) | ||
3172 | #define BNX2_TXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) | ||
3173 | #define BNX2_TXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) | ||
3174 | |||
3175 | #define BNX2_TXP_SCRATCH 0x00060000 | ||
3176 | |||
3177 | |||
3178 | /* | ||
3179 | * tpat_reg definition | ||
3180 | * offset: 0x80000 | ||
3181 | */ | ||
3182 | #define BNX2_TPAT_CPU_MODE 0x00085000 | ||
3183 | #define BNX2_TPAT_CPU_MODE_LOCAL_RST (1L<<0) | ||
3184 | #define BNX2_TPAT_CPU_MODE_STEP_ENA (1L<<1) | ||
3185 | #define BNX2_TPAT_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) | ||
3186 | #define BNX2_TPAT_CPU_MODE_PAGE_0_INST_ENA (1L<<3) | ||
3187 | #define BNX2_TPAT_CPU_MODE_MSG_BIT1 (1L<<6) | ||
3188 | #define BNX2_TPAT_CPU_MODE_INTERRUPT_ENA (1L<<7) | ||
3189 | #define BNX2_TPAT_CPU_MODE_SOFT_HALT (1L<<10) | ||
3190 | #define BNX2_TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) | ||
3191 | #define BNX2_TPAT_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) | ||
3192 | #define BNX2_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) | ||
3193 | #define BNX2_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) | ||
3194 | |||
3195 | #define BNX2_TPAT_CPU_STATE 0x00085004 | ||
3196 | #define BNX2_TPAT_CPU_STATE_BREAKPOINT (1L<<0) | ||
3197 | #define BNX2_TPAT_CPU_STATE_BAD_INST_HALTED (1L<<2) | ||
3198 | #define BNX2_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) | ||
3199 | #define BNX2_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) | ||
3200 | #define BNX2_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) | ||
3201 | #define BNX2_TPAT_CPU_STATE_BAD_pc_HALTED (1L<<6) | ||
3202 | #define BNX2_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7) | ||
3203 | #define BNX2_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8) | ||
3204 | #define BNX2_TPAT_CPU_STATE_SOFT_HALTED (1L<<10) | ||
3205 | #define BNX2_TPAT_CPU_STATE_SPAD_UNDERFLOW (1L<<11) | ||
3206 | #define BNX2_TPAT_CPU_STATE_INTERRRUPT (1L<<12) | ||
3207 | #define BNX2_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14) | ||
3208 | #define BNX2_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15) | ||
3209 | #define BNX2_TPAT_CPU_STATE_BLOCKED_READ (1L<<31) | ||
3210 | |||
3211 | #define BNX2_TPAT_CPU_EVENT_MASK 0x00085008 | ||
3212 | #define BNX2_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) | ||
3213 | #define BNX2_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) | ||
3214 | #define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) | ||
3215 | #define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) | ||
3216 | #define BNX2_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) | ||
3217 | #define BNX2_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) | ||
3218 | #define BNX2_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) | ||
3219 | #define BNX2_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) | ||
3220 | #define BNX2_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) | ||
3221 | #define BNX2_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) | ||
3222 | #define BNX2_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) | ||
3223 | |||
3224 | #define BNX2_TPAT_CPU_PROGRAM_COUNTER 0x0008501c | ||
3225 | #define BNX2_TPAT_CPU_INSTRUCTION 0x00085020 | ||
3226 | #define BNX2_TPAT_CPU_DATA_ACCESS 0x00085024 | ||
3227 | #define BNX2_TPAT_CPU_INTERRUPT_ENABLE 0x00085028 | ||
3228 | #define BNX2_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c | ||
3229 | #define BNX2_TPAT_CPU_INTERRUPT_SAVED_PC 0x00085030 | ||
3230 | #define BNX2_TPAT_CPU_HW_BREAKPOINT 0x00085034 | ||
3231 | #define BNX2_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0) | ||
3232 | #define BNX2_TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) | ||
3233 | |||
3234 | #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK 0x00085038 | ||
3235 | #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) | ||
3236 | #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) | ||
3237 | #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) | ||
3238 | #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) | ||
3239 | #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) | ||
3240 | #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) | ||
3241 | |||
3242 | #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR 0x00085048 | ||
3243 | #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) | ||
3244 | #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) | ||
3245 | #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) | ||
3246 | #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) | ||
3247 | |||
3248 | #define BNX2_TPAT_CPU_REG_FILE 0x00085200 | ||
3249 | #define BNX2_TPAT_FTQ_DATA 0x000853c0 | ||
3250 | #define BNX2_TPAT_FTQ_CMD 0x000853f8 | ||
3251 | #define BNX2_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0) | ||
3252 | #define BNX2_TPAT_FTQ_CMD_WR_TOP (1L<<10) | ||
3253 | #define BNX2_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10) | ||
3254 | #define BNX2_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10) | ||
3255 | #define BNX2_TPAT_FTQ_CMD_SFT_RESET (1L<<25) | ||
3256 | #define BNX2_TPAT_FTQ_CMD_RD_DATA (1L<<26) | ||
3257 | #define BNX2_TPAT_FTQ_CMD_ADD_INTERVEN (1L<<27) | ||
3258 | #define BNX2_TPAT_FTQ_CMD_ADD_DATA (1L<<28) | ||
3259 | #define BNX2_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29) | ||
3260 | #define BNX2_TPAT_FTQ_CMD_POP (1L<<30) | ||
3261 | #define BNX2_TPAT_FTQ_CMD_BUSY (1L<<31) | ||
3262 | |||
3263 | #define BNX2_TPAT_FTQ_CTL 0x000853fc | ||
3264 | #define BNX2_TPAT_FTQ_CTL_INTERVENE (1L<<0) | ||
3265 | #define BNX2_TPAT_FTQ_CTL_OVERFLOW (1L<<1) | ||
3266 | #define BNX2_TPAT_FTQ_CTL_FORCE_INTERVENE (1L<<2) | ||
3267 | #define BNX2_TPAT_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) | ||
3268 | #define BNX2_TPAT_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) | ||
3269 | |||
3270 | #define BNX2_TPAT_SCRATCH 0x000a0000 | ||
3271 | |||
3272 | |||
3273 | /* | ||
3274 | * rxp_reg definition | ||
3275 | * offset: 0xc0000 | ||
3276 | */ | ||
3277 | #define BNX2_RXP_CPU_MODE 0x000c5000 | ||
3278 | #define BNX2_RXP_CPU_MODE_LOCAL_RST (1L<<0) | ||
3279 | #define BNX2_RXP_CPU_MODE_STEP_ENA (1L<<1) | ||
3280 | #define BNX2_RXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) | ||
3281 | #define BNX2_RXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) | ||
3282 | #define BNX2_RXP_CPU_MODE_MSG_BIT1 (1L<<6) | ||
3283 | #define BNX2_RXP_CPU_MODE_INTERRUPT_ENA (1L<<7) | ||
3284 | #define BNX2_RXP_CPU_MODE_SOFT_HALT (1L<<10) | ||
3285 | #define BNX2_RXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) | ||
3286 | #define BNX2_RXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) | ||
3287 | #define BNX2_RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) | ||
3288 | #define BNX2_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) | ||
3289 | |||
3290 | #define BNX2_RXP_CPU_STATE 0x000c5004 | ||
3291 | #define BNX2_RXP_CPU_STATE_BREAKPOINT (1L<<0) | ||
3292 | #define BNX2_RXP_CPU_STATE_BAD_INST_HALTED (1L<<2) | ||
3293 | #define BNX2_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) | ||
3294 | #define BNX2_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) | ||
3295 | #define BNX2_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) | ||
3296 | #define BNX2_RXP_CPU_STATE_BAD_pc_HALTED (1L<<6) | ||
3297 | #define BNX2_RXP_CPU_STATE_ALIGN_HALTED (1L<<7) | ||
3298 | #define BNX2_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) | ||
3299 | #define BNX2_RXP_CPU_STATE_SOFT_HALTED (1L<<10) | ||
3300 | #define BNX2_RXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) | ||
3301 | #define BNX2_RXP_CPU_STATE_INTERRRUPT (1L<<12) | ||
3302 | #define BNX2_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) | ||
3303 | #define BNX2_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15) | ||
3304 | #define BNX2_RXP_CPU_STATE_BLOCKED_READ (1L<<31) | ||
3305 | |||
3306 | #define BNX2_RXP_CPU_EVENT_MASK 0x000c5008 | ||
3307 | #define BNX2_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) | ||
3308 | #define BNX2_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) | ||
3309 | #define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) | ||
3310 | #define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) | ||
3311 | #define BNX2_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) | ||
3312 | #define BNX2_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) | ||
3313 | #define BNX2_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) | ||
3314 | #define BNX2_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) | ||
3315 | #define BNX2_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) | ||
3316 | #define BNX2_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) | ||
3317 | #define BNX2_RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) | ||
3318 | |||
3319 | #define BNX2_RXP_CPU_PROGRAM_COUNTER 0x000c501c | ||
3320 | #define BNX2_RXP_CPU_INSTRUCTION 0x000c5020 | ||
3321 | #define BNX2_RXP_CPU_DATA_ACCESS 0x000c5024 | ||
3322 | #define BNX2_RXP_CPU_INTERRUPT_ENABLE 0x000c5028 | ||
3323 | #define BNX2_RXP_CPU_INTERRUPT_VECTOR 0x000c502c | ||
3324 | #define BNX2_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030 | ||
3325 | #define BNX2_RXP_CPU_HW_BREAKPOINT 0x000c5034 | ||
3326 | #define BNX2_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) | ||
3327 | #define BNX2_RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) | ||
3328 | |||
3329 | #define BNX2_RXP_CPU_DEBUG_VECT_PEEK 0x000c5038 | ||
3330 | #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) | ||
3331 | #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) | ||
3332 | #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) | ||
3333 | #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) | ||
3334 | #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) | ||
3335 | #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) | ||
3336 | |||
3337 | #define BNX2_RXP_CPU_LAST_BRANCH_ADDR 0x000c5048 | ||
3338 | #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) | ||
3339 | #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) | ||
3340 | #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) | ||
3341 | #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) | ||
3342 | |||
3343 | #define BNX2_RXP_CPU_REG_FILE 0x000c5200 | ||
3344 | #define BNX2_RXP_CFTQ_DATA 0x000c5380 | ||
3345 | #define BNX2_RXP_CFTQ_CMD 0x000c53b8 | ||
3346 | #define BNX2_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0) | ||
3347 | #define BNX2_RXP_CFTQ_CMD_WR_TOP (1L<<10) | ||
3348 | #define BNX2_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10) | ||
3349 | #define BNX2_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10) | ||
3350 | #define BNX2_RXP_CFTQ_CMD_SFT_RESET (1L<<25) | ||
3351 | #define BNX2_RXP_CFTQ_CMD_RD_DATA (1L<<26) | ||
3352 | #define BNX2_RXP_CFTQ_CMD_ADD_INTERVEN (1L<<27) | ||
3353 | #define BNX2_RXP_CFTQ_CMD_ADD_DATA (1L<<28) | ||
3354 | #define BNX2_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29) | ||
3355 | #define BNX2_RXP_CFTQ_CMD_POP (1L<<30) | ||
3356 | #define BNX2_RXP_CFTQ_CMD_BUSY (1L<<31) | ||
3357 | |||
3358 | #define BNX2_RXP_CFTQ_CTL 0x000c53bc | ||
3359 | #define BNX2_RXP_CFTQ_CTL_INTERVENE (1L<<0) | ||
3360 | #define BNX2_RXP_CFTQ_CTL_OVERFLOW (1L<<1) | ||
3361 | #define BNX2_RXP_CFTQ_CTL_FORCE_INTERVENE (1L<<2) | ||
3362 | #define BNX2_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12) | ||
3363 | #define BNX2_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22) | ||
3364 | |||
3365 | #define BNX2_RXP_FTQ_DATA 0x000c53c0 | ||
3366 | #define BNX2_RXP_FTQ_CMD 0x000c53f8 | ||
3367 | #define BNX2_RXP_FTQ_CMD_OFFSET (0x3ffL<<0) | ||
3368 | #define BNX2_RXP_FTQ_CMD_WR_TOP (1L<<10) | ||
3369 | #define BNX2_RXP_FTQ_CMD_WR_TOP_0 (0L<<10) | ||
3370 | #define BNX2_RXP_FTQ_CMD_WR_TOP_1 (1L<<10) | ||
3371 | #define BNX2_RXP_FTQ_CMD_SFT_RESET (1L<<25) | ||
3372 | #define BNX2_RXP_FTQ_CMD_RD_DATA (1L<<26) | ||
3373 | #define BNX2_RXP_FTQ_CMD_ADD_INTERVEN (1L<<27) | ||
3374 | #define BNX2_RXP_FTQ_CMD_ADD_DATA (1L<<28) | ||
3375 | #define BNX2_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29) | ||
3376 | #define BNX2_RXP_FTQ_CMD_POP (1L<<30) | ||
3377 | #define BNX2_RXP_FTQ_CMD_BUSY (1L<<31) | ||
3378 | |||
3379 | #define BNX2_RXP_FTQ_CTL 0x000c53fc | ||
3380 | #define BNX2_RXP_FTQ_CTL_INTERVENE (1L<<0) | ||
3381 | #define BNX2_RXP_FTQ_CTL_OVERFLOW (1L<<1) | ||
3382 | #define BNX2_RXP_FTQ_CTL_FORCE_INTERVENE (1L<<2) | ||
3383 | #define BNX2_RXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) | ||
3384 | #define BNX2_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) | ||
3385 | |||
3386 | #define BNX2_RXP_SCRATCH 0x000e0000 | ||
3387 | |||
3388 | |||
3389 | /* | ||
3390 | * com_reg definition | ||
3391 | * offset: 0x100000 | ||
3392 | */ | ||
3393 | #define BNX2_COM_CPU_MODE 0x00105000 | ||
3394 | #define BNX2_COM_CPU_MODE_LOCAL_RST (1L<<0) | ||
3395 | #define BNX2_COM_CPU_MODE_STEP_ENA (1L<<1) | ||
3396 | #define BNX2_COM_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) | ||
3397 | #define BNX2_COM_CPU_MODE_PAGE_0_INST_ENA (1L<<3) | ||
3398 | #define BNX2_COM_CPU_MODE_MSG_BIT1 (1L<<6) | ||
3399 | #define BNX2_COM_CPU_MODE_INTERRUPT_ENA (1L<<7) | ||
3400 | #define BNX2_COM_CPU_MODE_SOFT_HALT (1L<<10) | ||
3401 | #define BNX2_COM_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) | ||
3402 | #define BNX2_COM_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) | ||
3403 | #define BNX2_COM_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) | ||
3404 | #define BNX2_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) | ||
3405 | |||
3406 | #define BNX2_COM_CPU_STATE 0x00105004 | ||
3407 | #define BNX2_COM_CPU_STATE_BREAKPOINT (1L<<0) | ||
3408 | #define BNX2_COM_CPU_STATE_BAD_INST_HALTED (1L<<2) | ||
3409 | #define BNX2_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) | ||
3410 | #define BNX2_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) | ||
3411 | #define BNX2_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) | ||
3412 | #define BNX2_COM_CPU_STATE_BAD_pc_HALTED (1L<<6) | ||
3413 | #define BNX2_COM_CPU_STATE_ALIGN_HALTED (1L<<7) | ||
3414 | #define BNX2_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8) | ||
3415 | #define BNX2_COM_CPU_STATE_SOFT_HALTED (1L<<10) | ||
3416 | #define BNX2_COM_CPU_STATE_SPAD_UNDERFLOW (1L<<11) | ||
3417 | #define BNX2_COM_CPU_STATE_INTERRRUPT (1L<<12) | ||
3418 | #define BNX2_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14) | ||
3419 | #define BNX2_COM_CPU_STATE_INST_FETCH_STALL (1L<<15) | ||
3420 | #define BNX2_COM_CPU_STATE_BLOCKED_READ (1L<<31) | ||
3421 | |||
3422 | #define BNX2_COM_CPU_EVENT_MASK 0x00105008 | ||
3423 | #define BNX2_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) | ||
3424 | #define BNX2_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) | ||
3425 | #define BNX2_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) | ||
3426 | #define BNX2_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) | ||
3427 | #define BNX2_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) | ||
3428 | #define BNX2_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) | ||
3429 | #define BNX2_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) | ||
3430 | #define BNX2_COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) | ||
3431 | #define BNX2_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) | ||
3432 | #define BNX2_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) | ||
3433 | #define BNX2_COM_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) | ||
3434 | |||
3435 | #define BNX2_COM_CPU_PROGRAM_COUNTER 0x0010501c | ||
3436 | #define BNX2_COM_CPU_INSTRUCTION 0x00105020 | ||
3437 | #define BNX2_COM_CPU_DATA_ACCESS 0x00105024 | ||
3438 | #define BNX2_COM_CPU_INTERRUPT_ENABLE 0x00105028 | ||
3439 | #define BNX2_COM_CPU_INTERRUPT_VECTOR 0x0010502c | ||
3440 | #define BNX2_COM_CPU_INTERRUPT_SAVED_PC 0x00105030 | ||
3441 | #define BNX2_COM_CPU_HW_BREAKPOINT 0x00105034 | ||
3442 | #define BNX2_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0) | ||
3443 | #define BNX2_COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) | ||
3444 | |||
3445 | #define BNX2_COM_CPU_DEBUG_VECT_PEEK 0x00105038 | ||
3446 | #define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) | ||
3447 | #define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) | ||
3448 | #define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) | ||
3449 | #define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) | ||
3450 | #define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) | ||
3451 | #define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) | ||
3452 | |||
3453 | #define BNX2_COM_CPU_LAST_BRANCH_ADDR 0x00105048 | ||
3454 | #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) | ||
3455 | #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) | ||
3456 | #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) | ||
3457 | #define BNX2_COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) | ||
3458 | |||
3459 | #define BNX2_COM_CPU_REG_FILE 0x00105200 | ||
3460 | #define BNX2_COM_COMXQ_FTQ_DATA 0x00105340 | ||
3461 | #define BNX2_COM_COMXQ_FTQ_CMD 0x00105378 | ||
3462 | #define BNX2_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0) | ||
3463 | #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10) | ||
3464 | #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10) | ||
3465 | #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10) | ||
3466 | #define BNX2_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25) | ||
3467 | #define BNX2_COM_COMXQ_FTQ_CMD_RD_DATA (1L<<26) | ||
3468 | #define BNX2_COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1L<<27) | ||
3469 | #define BNX2_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28) | ||
3470 | #define BNX2_COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1L<<29) | ||
3471 | #define BNX2_COM_COMXQ_FTQ_CMD_POP (1L<<30) | ||
3472 | #define BNX2_COM_COMXQ_FTQ_CMD_BUSY (1L<<31) | ||
3473 | |||
3474 | #define BNX2_COM_COMXQ_FTQ_CTL 0x0010537c | ||
3475 | #define BNX2_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0) | ||
3476 | #define BNX2_COM_COMXQ_FTQ_CTL_OVERFLOW (1L<<1) | ||
3477 | #define BNX2_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) | ||
3478 | #define BNX2_COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) | ||
3479 | #define BNX2_COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) | ||
3480 | |||
3481 | #define BNX2_COM_COMTQ_FTQ_DATA 0x00105380 | ||
3482 | #define BNX2_COM_COMTQ_FTQ_CMD 0x001053b8 | ||
3483 | #define BNX2_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0) | ||
3484 | #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10) | ||
3485 | #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10) | ||
3486 | #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_1 (1L<<10) | ||
3487 | #define BNX2_COM_COMTQ_FTQ_CMD_SFT_RESET (1L<<25) | ||
3488 | #define BNX2_COM_COMTQ_FTQ_CMD_RD_DATA (1L<<26) | ||
3489 | #define BNX2_COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1L<<27) | ||
3490 | #define BNX2_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28) | ||
3491 | #define BNX2_COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1L<<29) | ||
3492 | #define BNX2_COM_COMTQ_FTQ_CMD_POP (1L<<30) | ||
3493 | #define BNX2_COM_COMTQ_FTQ_CMD_BUSY (1L<<31) | ||
3494 | |||
3495 | #define BNX2_COM_COMTQ_FTQ_CTL 0x001053bc | ||
3496 | #define BNX2_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0) | ||
3497 | #define BNX2_COM_COMTQ_FTQ_CTL_OVERFLOW (1L<<1) | ||
3498 | #define BNX2_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) | ||
3499 | #define BNX2_COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) | ||
3500 | #define BNX2_COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) | ||
3501 | |||
3502 | #define BNX2_COM_COMQ_FTQ_DATA 0x001053c0 | ||
3503 | #define BNX2_COM_COMQ_FTQ_CMD 0x001053f8 | ||
3504 | #define BNX2_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0) | ||
3505 | #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10) | ||
3506 | #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10) | ||
3507 | #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_1 (1L<<10) | ||
3508 | #define BNX2_COM_COMQ_FTQ_CMD_SFT_RESET (1L<<25) | ||
3509 | #define BNX2_COM_COMQ_FTQ_CMD_RD_DATA (1L<<26) | ||
3510 | #define BNX2_COM_COMQ_FTQ_CMD_ADD_INTERVEN (1L<<27) | ||
3511 | #define BNX2_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28) | ||
3512 | #define BNX2_COM_COMQ_FTQ_CMD_INTERVENE_CLR (1L<<29) | ||
3513 | #define BNX2_COM_COMQ_FTQ_CMD_POP (1L<<30) | ||
3514 | #define BNX2_COM_COMQ_FTQ_CMD_BUSY (1L<<31) | ||
3515 | |||
3516 | #define BNX2_COM_COMQ_FTQ_CTL 0x001053fc | ||
3517 | #define BNX2_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0) | ||
3518 | #define BNX2_COM_COMQ_FTQ_CTL_OVERFLOW (1L<<1) | ||
3519 | #define BNX2_COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) | ||
3520 | #define BNX2_COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) | ||
3521 | #define BNX2_COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) | ||
3522 | |||
3523 | #define BNX2_COM_SCRATCH 0x00120000 | ||
3524 | |||
3525 | |||
3526 | /* | ||
3527 | * cp_reg definition | ||
3528 | * offset: 0x180000 | ||
3529 | */ | ||
3530 | #define BNX2_CP_CPU_MODE 0x00185000 | ||
3531 | #define BNX2_CP_CPU_MODE_LOCAL_RST (1L<<0) | ||
3532 | #define BNX2_CP_CPU_MODE_STEP_ENA (1L<<1) | ||
3533 | #define BNX2_CP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) | ||
3534 | #define BNX2_CP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) | ||
3535 | #define BNX2_CP_CPU_MODE_MSG_BIT1 (1L<<6) | ||
3536 | #define BNX2_CP_CPU_MODE_INTERRUPT_ENA (1L<<7) | ||
3537 | #define BNX2_CP_CPU_MODE_SOFT_HALT (1L<<10) | ||
3538 | #define BNX2_CP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) | ||
3539 | #define BNX2_CP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) | ||
3540 | #define BNX2_CP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) | ||
3541 | #define BNX2_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) | ||
3542 | |||
3543 | #define BNX2_CP_CPU_STATE 0x00185004 | ||
3544 | #define BNX2_CP_CPU_STATE_BREAKPOINT (1L<<0) | ||
3545 | #define BNX2_CP_CPU_STATE_BAD_INST_HALTED (1L<<2) | ||
3546 | #define BNX2_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) | ||
3547 | #define BNX2_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) | ||
3548 | #define BNX2_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) | ||
3549 | #define BNX2_CP_CPU_STATE_BAD_pc_HALTED (1L<<6) | ||
3550 | #define BNX2_CP_CPU_STATE_ALIGN_HALTED (1L<<7) | ||
3551 | #define BNX2_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) | ||
3552 | #define BNX2_CP_CPU_STATE_SOFT_HALTED (1L<<10) | ||
3553 | #define BNX2_CP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) | ||
3554 | #define BNX2_CP_CPU_STATE_INTERRRUPT (1L<<12) | ||
3555 | #define BNX2_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) | ||
3556 | #define BNX2_CP_CPU_STATE_INST_FETCH_STALL (1L<<15) | ||
3557 | #define BNX2_CP_CPU_STATE_BLOCKED_READ (1L<<31) | ||
3558 | |||
3559 | #define BNX2_CP_CPU_EVENT_MASK 0x00185008 | ||
3560 | #define BNX2_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) | ||
3561 | #define BNX2_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) | ||
3562 | #define BNX2_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) | ||
3563 | #define BNX2_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) | ||
3564 | #define BNX2_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) | ||
3565 | #define BNX2_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) | ||
3566 | #define BNX2_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) | ||
3567 | #define BNX2_CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) | ||
3568 | #define BNX2_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) | ||
3569 | #define BNX2_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) | ||
3570 | #define BNX2_CP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) | ||
3571 | |||
3572 | #define BNX2_CP_CPU_PROGRAM_COUNTER 0x0018501c | ||
3573 | #define BNX2_CP_CPU_INSTRUCTION 0x00185020 | ||
3574 | #define BNX2_CP_CPU_DATA_ACCESS 0x00185024 | ||
3575 | #define BNX2_CP_CPU_INTERRUPT_ENABLE 0x00185028 | ||
3576 | #define BNX2_CP_CPU_INTERRUPT_VECTOR 0x0018502c | ||
3577 | #define BNX2_CP_CPU_INTERRUPT_SAVED_PC 0x00185030 | ||
3578 | #define BNX2_CP_CPU_HW_BREAKPOINT 0x00185034 | ||
3579 | #define BNX2_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) | ||
3580 | #define BNX2_CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) | ||
3581 | |||
3582 | #define BNX2_CP_CPU_DEBUG_VECT_PEEK 0x00185038 | ||
3583 | #define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) | ||
3584 | #define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) | ||
3585 | #define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) | ||
3586 | #define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) | ||
3587 | #define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) | ||
3588 | #define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) | ||
3589 | |||
3590 | #define BNX2_CP_CPU_LAST_BRANCH_ADDR 0x00185048 | ||
3591 | #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) | ||
3592 | #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) | ||
3593 | #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) | ||
3594 | #define BNX2_CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) | ||
3595 | |||
3596 | #define BNX2_CP_CPU_REG_FILE 0x00185200 | ||
3597 | #define BNX2_CP_CPQ_FTQ_DATA 0x001853c0 | ||
3598 | #define BNX2_CP_CPQ_FTQ_CMD 0x001853f8 | ||
3599 | #define BNX2_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0) | ||
3600 | #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10) | ||
3601 | #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10) | ||
3602 | #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10) | ||
3603 | #define BNX2_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25) | ||
3604 | #define BNX2_CP_CPQ_FTQ_CMD_RD_DATA (1L<<26) | ||
3605 | #define BNX2_CP_CPQ_FTQ_CMD_ADD_INTERVEN (1L<<27) | ||
3606 | #define BNX2_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28) | ||
3607 | #define BNX2_CP_CPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) | ||
3608 | #define BNX2_CP_CPQ_FTQ_CMD_POP (1L<<30) | ||
3609 | #define BNX2_CP_CPQ_FTQ_CMD_BUSY (1L<<31) | ||
3610 | |||
3611 | #define BNX2_CP_CPQ_FTQ_CTL 0x001853fc | ||
3612 | #define BNX2_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0) | ||
3613 | #define BNX2_CP_CPQ_FTQ_CTL_OVERFLOW (1L<<1) | ||
3614 | #define BNX2_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) | ||
3615 | #define BNX2_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) | ||
3616 | #define BNX2_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) | ||
3617 | |||
3618 | #define BNX2_CP_SCRATCH 0x001a0000 | ||
3619 | |||
3620 | |||
3621 | /* | ||
3622 | * mcp_reg definition | ||
3623 | * offset: 0x140000 | ||
3624 | */ | ||
3625 | #define BNX2_MCP_CPU_MODE 0x00145000 | ||
3626 | #define BNX2_MCP_CPU_MODE_LOCAL_RST (1L<<0) | ||
3627 | #define BNX2_MCP_CPU_MODE_STEP_ENA (1L<<1) | ||
3628 | #define BNX2_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) | ||
3629 | #define BNX2_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) | ||
3630 | #define BNX2_MCP_CPU_MODE_MSG_BIT1 (1L<<6) | ||
3631 | #define BNX2_MCP_CPU_MODE_INTERRUPT_ENA (1L<<7) | ||
3632 | #define BNX2_MCP_CPU_MODE_SOFT_HALT (1L<<10) | ||
3633 | #define BNX2_MCP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) | ||
3634 | #define BNX2_MCP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) | ||
3635 | #define BNX2_MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) | ||
3636 | #define BNX2_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) | ||
3637 | |||
3638 | #define BNX2_MCP_CPU_STATE 0x00145004 | ||
3639 | #define BNX2_MCP_CPU_STATE_BREAKPOINT (1L<<0) | ||
3640 | #define BNX2_MCP_CPU_STATE_BAD_INST_HALTED (1L<<2) | ||
3641 | #define BNX2_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) | ||
3642 | #define BNX2_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) | ||
3643 | #define BNX2_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) | ||
3644 | #define BNX2_MCP_CPU_STATE_BAD_pc_HALTED (1L<<6) | ||
3645 | #define BNX2_MCP_CPU_STATE_ALIGN_HALTED (1L<<7) | ||
3646 | #define BNX2_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) | ||
3647 | #define BNX2_MCP_CPU_STATE_SOFT_HALTED (1L<<10) | ||
3648 | #define BNX2_MCP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) | ||
3649 | #define BNX2_MCP_CPU_STATE_INTERRRUPT (1L<<12) | ||
3650 | #define BNX2_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) | ||
3651 | #define BNX2_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15) | ||
3652 | #define BNX2_MCP_CPU_STATE_BLOCKED_READ (1L<<31) | ||
3653 | |||
3654 | #define BNX2_MCP_CPU_EVENT_MASK 0x00145008 | ||
3655 | #define BNX2_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) | ||
3656 | #define BNX2_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) | ||
3657 | #define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) | ||
3658 | #define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) | ||
3659 | #define BNX2_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) | ||
3660 | #define BNX2_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) | ||
3661 | #define BNX2_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) | ||
3662 | #define BNX2_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) | ||
3663 | #define BNX2_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) | ||
3664 | #define BNX2_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) | ||
3665 | #define BNX2_MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) | ||
3666 | |||
3667 | #define BNX2_MCP_CPU_PROGRAM_COUNTER 0x0014501c | ||
3668 | #define BNX2_MCP_CPU_INSTRUCTION 0x00145020 | ||
3669 | #define BNX2_MCP_CPU_DATA_ACCESS 0x00145024 | ||
3670 | #define BNX2_MCP_CPU_INTERRUPT_ENABLE 0x00145028 | ||
3671 | #define BNX2_MCP_CPU_INTERRUPT_VECTOR 0x0014502c | ||
3672 | #define BNX2_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030 | ||
3673 | #define BNX2_MCP_CPU_HW_BREAKPOINT 0x00145034 | ||
3674 | #define BNX2_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) | ||
3675 | #define BNX2_MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) | ||
3676 | |||
3677 | #define BNX2_MCP_CPU_DEBUG_VECT_PEEK 0x00145038 | ||
3678 | #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) | ||
3679 | #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) | ||
3680 | #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) | ||
3681 | #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) | ||
3682 | #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) | ||
3683 | #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) | ||
3684 | |||
3685 | #define BNX2_MCP_CPU_LAST_BRANCH_ADDR 0x00145048 | ||
3686 | #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) | ||
3687 | #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) | ||
3688 | #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) | ||
3689 | #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) | ||
3690 | |||
3691 | #define BNX2_MCP_CPU_REG_FILE 0x00145200 | ||
3692 | #define BNX2_MCP_MCPQ_FTQ_DATA 0x001453c0 | ||
3693 | #define BNX2_MCP_MCPQ_FTQ_CMD 0x001453f8 | ||
3694 | #define BNX2_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0) | ||
3695 | #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10) | ||
3696 | #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10) | ||
3697 | #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10) | ||
3698 | #define BNX2_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25) | ||
3699 | #define BNX2_MCP_MCPQ_FTQ_CMD_RD_DATA (1L<<26) | ||
3700 | #define BNX2_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27) | ||
3701 | #define BNX2_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28) | ||
3702 | #define BNX2_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) | ||
3703 | #define BNX2_MCP_MCPQ_FTQ_CMD_POP (1L<<30) | ||
3704 | #define BNX2_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31) | ||
3705 | |||
3706 | #define BNX2_MCP_MCPQ_FTQ_CTL 0x001453fc | ||
3707 | #define BNX2_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0) | ||
3708 | #define BNX2_MCP_MCPQ_FTQ_CTL_OVERFLOW (1L<<1) | ||
3709 | #define BNX2_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) | ||
3710 | #define BNX2_MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) | ||
3711 | #define BNX2_MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) | ||
3712 | |||
3713 | #define BNX2_MCP_ROM 0x00150000 | ||
3714 | #define BNX2_MCP_SCRATCH 0x00160000 | ||
3715 | |||
3716 | |||
3717 | #define NUM_MC_HASH_REGISTERS 8 | ||
3718 | |||
3719 | |||
3720 | /* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */ | ||
3721 | #define PHY_BCM5706_PHY_ID 0x00206160 | ||
3722 | |||
3723 | #define PHY_ID(id) ((id) & 0xfffffff0) | ||
3724 | #define PHY_REV_ID(id) ((id) & 0xf) | ||
3725 | |||
3726 | #define MIN_ETHERNET_PACKET_SIZE 60 | ||
3727 | #define MAX_ETHERNET_PACKET_SIZE 1514 | ||
3728 | #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9014 | ||
3729 | |||
3730 | #define RX_COPY_THRESH 92 | ||
3731 | |||
3732 | #define DMA_READ_CHANS 5 | ||
3733 | #define DMA_WRITE_CHANS 3 | ||
3734 | |||
3735 | #define BCM_PAGE_BITS 12 | ||
3736 | #define BCM_PAGE_SIZE (1 << BCM_PAGE_BITS) | ||
3737 | |||
3738 | #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct tx_bd)) | ||
3739 | #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1) | ||
3740 | |||
3741 | #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct rx_bd)) | ||
3742 | #define MAX_RX_DESC_CNT (RX_DESC_CNT - 1) | ||
3743 | |||
3744 | #define NEXT_TX_BD(x) (((x) & (MAX_TX_DESC_CNT - 1)) == \ | ||
3745 | (MAX_TX_DESC_CNT - 1)) ? \ | ||
3746 | (x) + 2 : (x) + 1 | ||
3747 | |||
3748 | #define TX_RING_IDX(x) ((x) & MAX_TX_DESC_CNT) | ||
3749 | |||
3750 | #define NEXT_RX_BD(x) (((x) & (MAX_RX_DESC_CNT - 1)) == \ | ||
3751 | (MAX_RX_DESC_CNT - 1)) ? \ | ||
3752 | (x) + 2 : (x) + 1 | ||
3753 | |||
3754 | #define RX_RING_IDX(x) ((x) & MAX_RX_DESC_CNT) | ||
3755 | |||
3756 | |||
3757 | /* Context size. */ | ||
3758 | #define CTX_SHIFT 7 | ||
3759 | #define CTX_SIZE (1 << CTX_SHIFT) | ||
3760 | #define CTX_MASK (CTX_SIZE - 1) | ||
3761 | #define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT) | ||
3762 | #define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT) | ||
3763 | |||
3764 | #define PHY_CTX_SHIFT 6 | ||
3765 | #define PHY_CTX_SIZE (1 << PHY_CTX_SHIFT) | ||
3766 | #define PHY_CTX_MASK (PHY_CTX_SIZE - 1) | ||
3767 | #define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_CTX_SHIFT) | ||
3768 | #define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_CTX_SHIFT) | ||
3769 | |||
3770 | #define MB_KERNEL_CTX_SHIFT 8 | ||
3771 | #define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT) | ||
3772 | #define MB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1) | ||
3773 | #define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT)) | ||
3774 | |||
3775 | #define MAX_CID_CNT 0x4000 | ||
3776 | #define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT)) | ||
3777 | #define INVALID_CID_ADDR 0xffffffff | ||
3778 | |||
3779 | #define TX_CID 16 | ||
3780 | #define RX_CID 0 | ||
3781 | |||
3782 | #define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID) | ||
3783 | #define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID) | ||
3784 | |||
3785 | struct sw_bd { | ||
3786 | struct sk_buff *skb; | ||
3787 | DECLARE_PCI_UNMAP_ADDR(mapping) | ||
3788 | }; | ||
3789 | |||
3790 | /* Buffered flash (Atmel: AT45DB011B) specific information */ | ||
3791 | #define SEEPROM_PAGE_BITS 2 | ||
3792 | #define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS) | ||
3793 | #define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1) | ||
3794 | #define SEEPROM_PAGE_SIZE 4 | ||
3795 | #define SEEPROM_TOTAL_SIZE 65536 | ||
3796 | |||
3797 | #define BUFFERED_FLASH_PAGE_BITS 9 | ||
3798 | #define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS) | ||
3799 | #define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1) | ||
3800 | #define BUFFERED_FLASH_PAGE_SIZE 264 | ||
3801 | #define BUFFERED_FLASH_TOTAL_SIZE 131072 | ||
3802 | |||
3803 | #define SAIFUN_FLASH_PAGE_BITS 8 | ||
3804 | #define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS) | ||
3805 | #define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1) | ||
3806 | #define SAIFUN_FLASH_PAGE_SIZE 256 | ||
3807 | #define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536 | ||
3808 | |||
3809 | #define NVRAM_TIMEOUT_COUNT 30000 | ||
3810 | |||
3811 | |||
3812 | #define FLASH_STRAP_MASK (BNX2_NVM_CFG1_FLASH_MODE | \ | ||
3813 | BNX2_NVM_CFG1_BUFFER_MODE | \ | ||
3814 | BNX2_NVM_CFG1_PROTECT_MODE | \ | ||
3815 | BNX2_NVM_CFG1_FLASH_SIZE) | ||
3816 | |||
3817 | struct flash_spec { | ||
3818 | u32 strapping; | ||
3819 | u32 config1; | ||
3820 | u32 config2; | ||
3821 | u32 config3; | ||
3822 | u32 write1; | ||
3823 | u32 buffered; | ||
3824 | u32 page_bits; | ||
3825 | u32 page_size; | ||
3826 | u32 addr_mask; | ||
3827 | u32 total_size; | ||
3828 | u8 *name; | ||
3829 | }; | ||
3830 | |||
3831 | struct bnx2 { | ||
3832 | /* Fields used in the tx and intr/napi performance paths are grouped */ | ||
3833 | /* together in the beginning of the structure. */ | ||
3834 | void __iomem *regview; | ||
3835 | |||
3836 | struct net_device *dev; | ||
3837 | struct pci_dev *pdev; | ||
3838 | |||
3839 | atomic_t intr_sem; | ||
3840 | |||
3841 | struct status_block *status_blk; | ||
3842 | u32 last_status_idx; | ||
3843 | |||
3844 | atomic_t tx_avail_bd; | ||
3845 | struct tx_bd *tx_desc_ring; | ||
3846 | struct sw_bd *tx_buf_ring; | ||
3847 | u32 tx_prod_bseq; | ||
3848 | u16 tx_prod; | ||
3849 | u16 tx_cons; | ||
3850 | |||
3851 | #ifdef BCM_VLAN | ||
3852 | struct vlan_group *vlgrp; | ||
3853 | #endif | ||
3854 | |||
3855 | u32 rx_offset; | ||
3856 | u32 rx_buf_use_size; /* useable size */ | ||
3857 | u32 rx_buf_size; /* with alignment */ | ||
3858 | struct rx_bd *rx_desc_ring; | ||
3859 | struct sw_bd *rx_buf_ring; | ||
3860 | u32 rx_prod_bseq; | ||
3861 | u16 rx_prod; | ||
3862 | u16 rx_cons; | ||
3863 | |||
3864 | u32 rx_csum; | ||
3865 | |||
3866 | /* Only used to synchronize netif_stop_queue/wake_queue when tx */ | ||
3867 | /* ring is full */ | ||
3868 | spinlock_t tx_lock; | ||
3869 | |||
3870 | /* End of fileds used in the performance code paths. */ | ||
3871 | |||
3872 | char *name; | ||
3873 | |||
3874 | int timer_interval; | ||
3875 | struct timer_list timer; | ||
3876 | struct work_struct reset_task; | ||
3877 | |||
3878 | /* Used to synchronize phy accesses. */ | ||
3879 | spinlock_t phy_lock; | ||
3880 | |||
3881 | u32 flags; | ||
3882 | #define PCIX_FLAG 1 | ||
3883 | #define PCI_32BIT_FLAG 2 | ||
3884 | #define ONE_TDMA_FLAG 4 /* no longer used */ | ||
3885 | #define NO_WOL_FLAG 8 | ||
3886 | #define USING_DAC_FLAG 0x10 | ||
3887 | #define USING_MSI_FLAG 0x20 | ||
3888 | |||
3889 | u32 phy_flags; | ||
3890 | #define PHY_SERDES_FLAG 1 | ||
3891 | #define PHY_CRC_FIX_FLAG 2 | ||
3892 | #define PHY_PARALLEL_DETECT_FLAG 4 | ||
3893 | #define PHY_INT_MODE_MASK_FLAG 0x300 | ||
3894 | #define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100 | ||
3895 | #define PHY_INT_MODE_LINK_READY_FLAG 0x200 | ||
3896 | |||
3897 | u32 chip_id; | ||
3898 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ | ||
3899 | #define CHIP_NUM(bp) (((bp)->chip_id) & 0xffff0000) | ||
3900 | #define CHIP_NUM_5706 0x57060000 | ||
3901 | |||
3902 | #define CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000) | ||
3903 | #define CHIP_REV_Ax 0x00000000 | ||
3904 | #define CHIP_REV_Bx 0x00001000 | ||
3905 | #define CHIP_REV_Cx 0x00002000 | ||
3906 | |||
3907 | #define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0) | ||
3908 | #define CHIP_BONDING(bp) (((bp)->chip_id) & 0x0000000f) | ||
3909 | |||
3910 | #define CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0) | ||
3911 | #define CHIP_ID_5706_A0 0x57060000 | ||
3912 | #define CHIP_ID_5706_A1 0x57060010 | ||
3913 | |||
3914 | #define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0xf) | ||
3915 | |||
3916 | /* A serdes chip will have the first bit of the bond id set. */ | ||
3917 | #define CHIP_BOND_ID_SERDES_BIT 0x01 | ||
3918 | |||
3919 | u32 phy_addr; | ||
3920 | u32 phy_id; | ||
3921 | |||
3922 | u16 bus_speed_mhz; | ||
3923 | u8 wol; | ||
3924 | |||
3925 | u8 fw_timed_out; | ||
3926 | |||
3927 | u16 fw_wr_seq; | ||
3928 | u16 fw_drv_pulse_wr_seq; | ||
3929 | |||
3930 | int tx_ring_size; | ||
3931 | dma_addr_t tx_desc_mapping; | ||
3932 | |||
3933 | |||
3934 | int rx_ring_size; | ||
3935 | dma_addr_t rx_desc_mapping; | ||
3936 | |||
3937 | u16 tx_quick_cons_trip; | ||
3938 | u16 tx_quick_cons_trip_int; | ||
3939 | u16 rx_quick_cons_trip; | ||
3940 | u16 rx_quick_cons_trip_int; | ||
3941 | u16 comp_prod_trip; | ||
3942 | u16 comp_prod_trip_int; | ||
3943 | u16 tx_ticks; | ||
3944 | u16 tx_ticks_int; | ||
3945 | u16 com_ticks; | ||
3946 | u16 com_ticks_int; | ||
3947 | u16 cmd_ticks; | ||
3948 | u16 cmd_ticks_int; | ||
3949 | u16 rx_ticks; | ||
3950 | u16 rx_ticks_int; | ||
3951 | |||
3952 | u32 stats_ticks; | ||
3953 | |||
3954 | dma_addr_t status_blk_mapping; | ||
3955 | |||
3956 | struct statistics_block *stats_blk; | ||
3957 | dma_addr_t stats_blk_mapping; | ||
3958 | |||
3959 | u32 rx_mode; | ||
3960 | |||
3961 | u16 req_line_speed; | ||
3962 | u8 req_duplex; | ||
3963 | |||
3964 | u8 link_up; | ||
3965 | |||
3966 | u16 line_speed; | ||
3967 | u8 duplex; | ||
3968 | u8 flow_ctrl; /* actual flow ctrl settings */ | ||
3969 | /* may be different from */ | ||
3970 | /* req_flow_ctrl if autoneg */ | ||
3971 | #define FLOW_CTRL_TX 1 | ||
3972 | #define FLOW_CTRL_RX 2 | ||
3973 | |||
3974 | u32 advertising; | ||
3975 | |||
3976 | u8 req_flow_ctrl; /* flow ctrl advertisement */ | ||
3977 | /* settings or forced */ | ||
3978 | /* settings */ | ||
3979 | u8 autoneg; | ||
3980 | #define AUTONEG_SPEED 1 | ||
3981 | #define AUTONEG_FLOW_CTRL 2 | ||
3982 | |||
3983 | u8 loopback; | ||
3984 | #define MAC_LOOPBACK 1 | ||
3985 | #define PHY_LOOPBACK 2 | ||
3986 | |||
3987 | u8 serdes_an_pending; | ||
3988 | #define SERDES_AN_TIMEOUT (2 * HZ) | ||
3989 | |||
3990 | u8 mac_addr[8]; | ||
3991 | |||
3992 | u32 fw_ver; | ||
3993 | |||
3994 | int pm_cap; | ||
3995 | int pcix_cap; | ||
3996 | |||
3997 | struct net_device_stats net_stats; | ||
3998 | |||
3999 | struct flash_spec *flash_info; | ||
4000 | }; | ||
4001 | |||
4002 | static u32 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset); | ||
4003 | static void bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val); | ||
4004 | |||
4005 | #define REG_RD(bp, offset) \ | ||
4006 | readl(bp->regview + offset) | ||
4007 | |||
4008 | #define REG_WR(bp, offset, val) \ | ||
4009 | writel(val, bp->regview + offset) | ||
4010 | |||
4011 | #define REG_WR16(bp, offset, val) \ | ||
4012 | writew(val, bp->regview + offset) | ||
4013 | |||
4014 | #define REG_RD_IND(bp, offset) \ | ||
4015 | bnx2_reg_rd_ind(bp, offset) | ||
4016 | |||
4017 | #define REG_WR_IND(bp, offset, val) \ | ||
4018 | bnx2_reg_wr_ind(bp, offset, val) | ||
4019 | |||
4020 | /* Indirect context access. Unlike the MBQ_WR, these macros will not | ||
4021 | * trigger a chip event. */ | ||
4022 | static void bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val); | ||
4023 | |||
4024 | #define CTX_WR(bp, cid_addr, offset, val) \ | ||
4025 | bnx2_ctx_wr(bp, cid_addr, offset, val) | ||
4026 | |||
4027 | struct cpu_reg { | ||
4028 | u32 mode; | ||
4029 | u32 mode_value_halt; | ||
4030 | u32 mode_value_sstep; | ||
4031 | |||
4032 | u32 state; | ||
4033 | u32 state_value_clear; | ||
4034 | |||
4035 | u32 gpr0; | ||
4036 | u32 evmask; | ||
4037 | u32 pc; | ||
4038 | u32 inst; | ||
4039 | u32 bp; | ||
4040 | |||
4041 | u32 spad_base; | ||
4042 | |||
4043 | u32 mips_view_base; | ||
4044 | }; | ||
4045 | |||
4046 | struct fw_info { | ||
4047 | u32 ver_major; | ||
4048 | u32 ver_minor; | ||
4049 | u32 ver_fix; | ||
4050 | |||
4051 | u32 start_addr; | ||
4052 | |||
4053 | /* Text section. */ | ||
4054 | u32 text_addr; | ||
4055 | u32 text_len; | ||
4056 | u32 text_index; | ||
4057 | u32 *text; | ||
4058 | |||
4059 | /* Data section. */ | ||
4060 | u32 data_addr; | ||
4061 | u32 data_len; | ||
4062 | u32 data_index; | ||
4063 | u32 *data; | ||
4064 | |||
4065 | /* SBSS section. */ | ||
4066 | u32 sbss_addr; | ||
4067 | u32 sbss_len; | ||
4068 | u32 sbss_index; | ||
4069 | u32 *sbss; | ||
4070 | |||
4071 | /* BSS section. */ | ||
4072 | u32 bss_addr; | ||
4073 | u32 bss_len; | ||
4074 | u32 bss_index; | ||
4075 | u32 *bss; | ||
4076 | |||
4077 | /* Read-only section. */ | ||
4078 | u32 rodata_addr; | ||
4079 | u32 rodata_len; | ||
4080 | u32 rodata_index; | ||
4081 | u32 *rodata; | ||
4082 | }; | ||
4083 | |||
4084 | #define RV2P_PROC1 0 | ||
4085 | #define RV2P_PROC2 1 | ||
4086 | |||
4087 | |||
4088 | /* This value (in milliseconds) determines the frequency of the driver | ||
4089 | * issuing the PULSE message code. The firmware monitors this periodic | ||
4090 | * pulse to determine when to switch to an OS-absent mode. */ | ||
4091 | #define DRV_PULSE_PERIOD_MS 250 | ||
4092 | |||
4093 | /* This value (in milliseconds) determines how long the driver should | ||
4094 | * wait for an acknowledgement from the firmware before timing out. Once | ||
4095 | * the firmware has timed out, the driver will assume there is no firmware | ||
4096 | * running and there won't be any firmware-driver synchronization during a | ||
4097 | * driver reset. */ | ||
4098 | #define FW_ACK_TIME_OUT_MS 50 | ||
4099 | |||
4100 | |||
4101 | #define BNX2_DRV_RESET_SIGNATURE 0x00000000 | ||
4102 | #define BNX2_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */ | ||
4103 | //#define DRV_RESET_SIGNATURE_MAGIC 0x47495352 /* RSIG */ | ||
4104 | |||
4105 | #define BNX2_DRV_MB 0x00000004 | ||
4106 | #define BNX2_DRV_MSG_CODE 0xff000000 | ||
4107 | #define BNX2_DRV_MSG_CODE_RESET 0x01000000 | ||
4108 | #define BNX2_DRV_MSG_CODE_UNLOAD 0x02000000 | ||
4109 | #define BNX2_DRV_MSG_CODE_SHUTDOWN 0x03000000 | ||
4110 | #define BNX2_DRV_MSG_CODE_SUSPEND_WOL 0x04000000 | ||
4111 | #define BNX2_DRV_MSG_CODE_FW_TIMEOUT 0x05000000 | ||
4112 | #define BNX2_DRV_MSG_CODE_PULSE 0x06000000 | ||
4113 | #define BNX2_DRV_MSG_CODE_DIAG 0x07000000 | ||
4114 | #define BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000 | ||
4115 | |||
4116 | #define BNX2_DRV_MSG_DATA 0x00ff0000 | ||
4117 | #define BNX2_DRV_MSG_DATA_WAIT0 0x00010000 | ||
4118 | #define BNX2_DRV_MSG_DATA_WAIT1 0x00020000 | ||
4119 | #define BNX2_DRV_MSG_DATA_WAIT2 0x00030000 | ||
4120 | #define BNX2_DRV_MSG_DATA_WAIT3 0x00040000 | ||
4121 | |||
4122 | #define BNX2_DRV_MSG_SEQ 0x0000ffff | ||
4123 | |||
4124 | #define BNX2_FW_MB 0x00000008 | ||
4125 | #define BNX2_FW_MSG_ACK 0x0000ffff | ||
4126 | #define BNX2_FW_MSG_STATUS_MASK 0x00ff0000 | ||
4127 | #define BNX2_FW_MSG_STATUS_OK 0x00000000 | ||
4128 | #define BNX2_FW_MSG_STATUS_FAILURE 0x00ff0000 | ||
4129 | |||
4130 | #define BNX2_LINK_STATUS 0x0000000c | ||
4131 | |||
4132 | #define BNX2_DRV_PULSE_MB 0x00000010 | ||
4133 | #define BNX2_DRV_PULSE_SEQ_MASK 0x0000ffff | ||
4134 | |||
4135 | /* Indicate to the firmware not to go into the | ||
4136 | * OS absent when it is not getting driver pulse. | ||
4137 | * This is used for debugging. */ | ||
4138 | #define BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00010000 | ||
4139 | |||
4140 | #define BNX2_DEV_INFO_SIGNATURE 0x00000020 | ||
4141 | #define BNX2_DEV_INFO_SIGNATURE_MAGIC 0x44564900 | ||
4142 | #define BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00 | ||
4143 | #define BNX2_DEV_INFO_FEATURE_CFG_VALID 0x01 | ||
4144 | #define BNX2_DEV_INFO_SECONDARY_PORT 0x80 | ||
4145 | #define BNX2_DEV_INFO_DRV_ALWAYS_ALIVE 0x40 | ||
4146 | |||
4147 | #define BNX2_SHARED_HW_CFG_PART_NUM 0x00000024 | ||
4148 | |||
4149 | #define BNX2_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034 | ||
4150 | #define BNX2_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000 | ||
4151 | #define BNX2_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000 | ||
4152 | #define BNX2_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00 | ||
4153 | #define BNX2_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff | ||
4154 | |||
4155 | #define BNX2_SHARED_HW_CFG POWER_CONSUMED 0x00000038 | ||
4156 | #define BNX2_SHARED_HW_CFG_CONFIG 0x0000003c | ||
4157 | #define BNX2_SHARED_HW_CFG_DESIGN_NIC 0 | ||
4158 | #define BNX2_SHARED_HW_CFG_DESIGN_LOM 0x1 | ||
4159 | #define BNX2_SHARED_HW_CFG_PHY_COPPER 0 | ||
4160 | #define BNX2_SHARED_HW_CFG_PHY_FIBER 0x2 | ||
4161 | #define BNX2_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8 | ||
4162 | #define BNX2_SHARED_HW_CFG_LED_MODE_MASK 0x300 | ||
4163 | #define BNX2_SHARED_HW_CFG_LED_MODE_MAC 0 | ||
4164 | #define BNX2_SHARED_HW_CFG_LED_MODE_GPHY1 0x100 | ||
4165 | #define BNX2_SHARED_HW_CFG_LED_MODE_GPHY2 0x200 | ||
4166 | |||
4167 | #define BNX2_DEV_INFO_BC_REV 0x0000004c | ||
4168 | |||
4169 | #define BNX2_PORT_HW_CFG_MAC_UPPER 0x00000050 | ||
4170 | #define BNX2_PORT_HW_CFG_UPPERMAC_MASK 0xffff | ||
4171 | |||
4172 | #define BNX2_PORT_HW_CFG_MAC_LOWER 0x00000054 | ||
4173 | #define BNX2_PORT_HW_CFG_CONFIG 0x00000058 | ||
4174 | |||
4175 | #define BNX2_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068 | ||
4176 | #define BNX2_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c | ||
4177 | #define BNX2_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070 | ||
4178 | #define BNX2_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074 | ||
4179 | #define BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078 | ||
4180 | #define BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c | ||
4181 | |||
4182 | #define BNX2_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4 | ||
4183 | |||
4184 | #define BNX2_DEV_INFO_FORMAT_REV 0x000000c4 | ||
4185 | #define BNX2_DEV_INFO_FORMAT_REV_MASK 0xff000000 | ||
4186 | #define BNX2_DEV_INFO_FORMAT_REV_ID ('A' << 24) | ||
4187 | |||
4188 | #define BNX2_SHARED_FEATURE 0x000000c8 | ||
4189 | #define BNX2_SHARED_FEATURE_MASK 0xffffffff | ||
4190 | |||
4191 | #define BNX2_PORT_FEATURE 0x000000d8 | ||
4192 | #define BNX2_PORT2_FEATURE 0x00000014c | ||
4193 | #define BNX2_PORT_FEATURE_WOL_ENABLED 0x01000000 | ||
4194 | #define BNX2_PORT_FEATURE_MBA_ENABLED 0x02000000 | ||
4195 | #define BNX2_PORT_FEATURE_ASF_ENABLED 0x04000000 | ||
4196 | #define BNX2_PORT_FEATURE_IMD_ENABLED 0x08000000 | ||
4197 | #define BNX2_PORT_FEATURE_BAR1_SIZE_MASK 0xf | ||
4198 | #define BNX2_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0 | ||
4199 | #define BNX2_PORT_FEATURE_BAR1_SIZE_64K 0x1 | ||
4200 | #define BNX2_PORT_FEATURE_BAR1_SIZE_128K 0x2 | ||
4201 | #define BNX2_PORT_FEATURE_BAR1_SIZE_256K 0x3 | ||
4202 | #define BNX2_PORT_FEATURE_BAR1_SIZE_512K 0x4 | ||
4203 | #define BNX2_PORT_FEATURE_BAR1_SIZE_1M 0x5 | ||
4204 | #define BNX2_PORT_FEATURE_BAR1_SIZE_2M 0x6 | ||
4205 | #define BNX2_PORT_FEATURE_BAR1_SIZE_4M 0x7 | ||
4206 | #define BNX2_PORT_FEATURE_BAR1_SIZE_8M 0x8 | ||
4207 | #define BNX2_PORT_FEATURE_BAR1_SIZE_16M 0x9 | ||
4208 | #define BNX2_PORT_FEATURE_BAR1_SIZE_32M 0xa | ||
4209 | #define BNX2_PORT_FEATURE_BAR1_SIZE_64M 0xb | ||
4210 | #define BNX2_PORT_FEATURE_BAR1_SIZE_128M 0xc | ||
4211 | #define BNX2_PORT_FEATURE_BAR1_SIZE_256M 0xd | ||
4212 | #define BNX2_PORT_FEATURE_BAR1_SIZE_512M 0xe | ||
4213 | #define BNX2_PORT_FEATURE_BAR1_SIZE_1G 0xf | ||
4214 | |||
4215 | #define BNX2_PORT_FEATURE_WOL 0xdc | ||
4216 | #define BNX2_PORT2_FEATURE_WOL 0x150 | ||
4217 | #define BNX2_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS 4 | ||
4218 | #define BNX2_PORT_FEATURE_WOL_DEFAULT_MASK 0x30 | ||
4219 | #define BNX2_PORT_FEATURE_WOL_DEFAULT_DISABLE 0 | ||
4220 | #define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10 | ||
4221 | #define BNX2_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20 | ||
4222 | #define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30 | ||
4223 | #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf | ||
4224 | #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0 | ||
4225 | #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10HALF 1 | ||
4226 | #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10FULL 2 | ||
4227 | #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3 | ||
4228 | #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4 | ||
4229 | #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000HALF 5 | ||
4230 | #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000FULL 6 | ||
4231 | #define BNX2_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40 | ||
4232 | #define BNX2_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400 | ||
4233 | #define BNX2_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800 | ||
4234 | |||
4235 | #define BNX2_PORT_FEATURE_MBA 0xe0 | ||
4236 | #define BNX2_PORT2_FEATURE_MBA 0x154 | ||
4237 | #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0 | ||
4238 | #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3 | ||
4239 | #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0 | ||
4240 | #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1 | ||
4241 | #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2 | ||
4242 | #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2 | ||
4243 | #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c | ||
4244 | #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0 | ||
4245 | #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4 | ||
4246 | #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8 | ||
4247 | #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc | ||
4248 | #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10 | ||
4249 | #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14 | ||
4250 | #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18 | ||
4251 | #define BNX2_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40 | ||
4252 | #define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0 | ||
4253 | #define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80 | ||
4254 | #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8 | ||
4255 | #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00 | ||
4256 | #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0 | ||
4257 | #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100 | ||
4258 | #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200 | ||
4259 | #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300 | ||
4260 | #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400 | ||
4261 | #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500 | ||
4262 | #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600 | ||
4263 | #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700 | ||
4264 | #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800 | ||
4265 | #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900 | ||
4266 | #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00 | ||
4267 | #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00 | ||
4268 | #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00 | ||
4269 | #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00 | ||
4270 | #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00 | ||
4271 | #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00 | ||
4272 | #define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16 | ||
4273 | #define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000 | ||
4274 | #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20 | ||
4275 | #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000 | ||
4276 | #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0 | ||
4277 | #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000 | ||
4278 | #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000 | ||
4279 | #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000 | ||
4280 | |||
4281 | #define BNX2_PORT_FEATURE_IMD 0xe4 | ||
4282 | #define BNX2_PORT2_FEATURE_IMD 0x158 | ||
4283 | #define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0 | ||
4284 | #define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE 1 | ||
4285 | |||
4286 | #define BNX2_PORT_FEATURE_VLAN 0xe8 | ||
4287 | #define BNX2_PORT2_FEATURE_VLAN 0x15c | ||
4288 | #define BNX2_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff | ||
4289 | #define BNX2_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000 | ||
4290 | |||
4291 | #define BNX2_BC_STATE_RESET_TYPE 0x000001c0 | ||
4292 | #define BNX2_BC_STATE_RESET_TYPE_SIG 0x00005254 | ||
4293 | #define BNX2_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff | ||
4294 | #define BNX2_BC_STATE_RESET_TYPE_NONE (BNX2_BC_STATE_RESET_TYPE_SIG | \ | ||
4295 | 0x00010000) | ||
4296 | #define BNX2_BC_STATE_RESET_TYPE_PCI (BNX2_BC_STATE_RESET_TYPE_SIG | \ | ||
4297 | 0x00020000) | ||
4298 | #define BNX2_BC_STATE_RESET_TYPE_VAUX (BNX2_BC_STATE_RESET_TYPE_SIG | \ | ||
4299 | 0x00030000) | ||
4300 | #define BNX2_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE | ||
4301 | #define BNX2_BC_STATE_RESET_TYPE_DRV_RESET (BNX2_BC_STATE_RESET_TYPE_SIG | \ | ||
4302 | DRV_MSG_CODE_RESET) | ||
4303 | #define BNX2_BC_STATE_RESET_TYPE_DRV_UNLOAD (BNX2_BC_STATE_RESET_TYPE_SIG | \ | ||
4304 | DRV_MSG_CODE_UNLOAD) | ||
4305 | #define BNX2_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BNX2_BC_STATE_RESET_TYPE_SIG | \ | ||
4306 | DRV_MSG_CODE_SHUTDOWN) | ||
4307 | #define BNX2_BC_STATE_RESET_TYPE_DRV_WOL (BNX2_BC_STATE_RESET_TYPE_SIG | \ | ||
4308 | DRV_MSG_CODE_WOL) | ||
4309 | #define BNX2_BC_STATE_RESET_TYPE_DRV_DIAG (BNX2_BC_STATE_RESET_TYPE_SIG | \ | ||
4310 | DRV_MSG_CODE_DIAG) | ||
4311 | #define BNX2_BC_STATE_RESET_TYPE_VALUE(msg) (BNX2_BC_STATE_RESET_TYPE_SIG | \ | ||
4312 | (msg)) | ||
4313 | |||
4314 | #define BNX2_BC_STATE 0x000001c4 | ||
4315 | #define BNX2_BC_STATE_ERR_MASK 0x0000ff00 | ||
4316 | #define BNX2_BC_STATE_SIGN 0x42530000 | ||
4317 | #define BNX2_BC_STATE_SIGN_MASK 0xffff0000 | ||
4318 | #define BNX2_BC_STATE_BC1_START (BNX2_BC_STATE_SIGN | 0x1) | ||
4319 | #define BNX2_BC_STATE_GET_NVM_CFG1 (BNX2_BC_STATE_SIGN | 0x2) | ||
4320 | #define BNX2_BC_STATE_PROG_BAR (BNX2_BC_STATE_SIGN | 0x3) | ||
4321 | #define BNX2_BC_STATE_INIT_VID (BNX2_BC_STATE_SIGN | 0x4) | ||
4322 | #define BNX2_BC_STATE_GET_NVM_CFG2 (BNX2_BC_STATE_SIGN | 0x5) | ||
4323 | #define BNX2_BC_STATE_APPLY_WKARND (BNX2_BC_STATE_SIGN | 0x6) | ||
4324 | #define BNX2_BC_STATE_LOAD_BC2 (BNX2_BC_STATE_SIGN | 0x7) | ||
4325 | #define BNX2_BC_STATE_GOING_BC2 (BNX2_BC_STATE_SIGN | 0x8) | ||
4326 | #define BNX2_BC_STATE_GOING_DIAG (BNX2_BC_STATE_SIGN | 0x9) | ||
4327 | #define BNX2_BC_STATE_RT_FINAL_INIT (BNX2_BC_STATE_SIGN | 0x81) | ||
4328 | #define BNX2_BC_STATE_RT_WKARND (BNX2_BC_STATE_SIGN | 0x82) | ||
4329 | #define BNX2_BC_STATE_RT_DRV_PULSE (BNX2_BC_STATE_SIGN | 0x83) | ||
4330 | #define BNX2_BC_STATE_RT_FIOEVTS (BNX2_BC_STATE_SIGN | 0x84) | ||
4331 | #define BNX2_BC_STATE_RT_DRV_CMD (BNX2_BC_STATE_SIGN | 0x85) | ||
4332 | #define BNX2_BC_STATE_RT_LOW_POWER (BNX2_BC_STATE_SIGN | 0x86) | ||
4333 | #define BNX2_BC_STATE_RT_SET_WOL (BNX2_BC_STATE_SIGN | 0x87) | ||
4334 | #define BNX2_BC_STATE_RT_OTHER_FW (BNX2_BC_STATE_SIGN | 0x88) | ||
4335 | #define BNX2_BC_STATE_RT_GOING_D3 (BNX2_BC_STATE_SIGN | 0x89) | ||
4336 | #define BNX2_BC_STATE_ERR_BAD_VERSION (BNX2_BC_STATE_SIGN | 0x0100) | ||
4337 | #define BNX2_BC_STATE_ERR_BAD_BC2_CRC (BNX2_BC_STATE_SIGN | 0x0200) | ||
4338 | #define BNX2_BC_STATE_ERR_BC1_LOOP (BNX2_BC_STATE_SIGN | 0x0300) | ||
4339 | #define BNX2_BC_STATE_ERR_UNKNOWN_CMD (BNX2_BC_STATE_SIGN | 0x0400) | ||
4340 | #define BNX2_BC_STATE_ERR_DRV_DEAD (BNX2_BC_STATE_SIGN | 0x0500) | ||
4341 | #define BNX2_BC_STATE_ERR_NO_RXP (BNX2_BC_STATE_SIGN | 0x0600) | ||
4342 | #define BNX2_BC_STATE_ERR_TOO_MANY_RBUF (BNX2_BC_STATE_SIGN | 0x0700) | ||
4343 | |||
4344 | #define BNX2_BC_STATE_DEBUG_CMD 0x1dc | ||
4345 | #define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000 | ||
4346 | #define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000 | ||
4347 | #define BNX2_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff | ||
4348 | #define BNX2_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff | ||
4349 | |||
4350 | #define HOST_VIEW_SHMEM_BASE 0x167c00 | ||
4351 | |||
4352 | #endif | ||
diff --git a/drivers/net/bnx2_fw.h b/drivers/net/bnx2_fw.h new file mode 100644 index 000000000000..35f3a2ae5ef1 --- /dev/null +++ b/drivers/net/bnx2_fw.h | |||
@@ -0,0 +1,2468 @@ | |||
1 | /* bnx2_fw.h: Broadcom NX2 network driver. | ||
2 | * | ||
3 | * Copyright (c) 2004, 2005 Broadcom Corporation | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License as published by | ||
7 | * the Free Software Foundation, except as noted below. | ||
8 | * | ||
9 | * This file contains firmware data derived from proprietary unpublished | ||
10 | * source code, Copyright (c) 2004, 2005 Broadcom Corporation. | ||
11 | * | ||
12 | * Permission is hereby granted for the distribution of this firmware data | ||
13 | * in hexadecimal or equivalent format, provided this copyright notice is | ||
14 | * accompanying it. | ||
15 | */ | ||
16 | |||
17 | |||
18 | static int bnx2_COM_b06FwReleaseMajor = 0x0; | ||
19 | static int bnx2_COM_b06FwReleaseMinor = 0x0; | ||
20 | static int bnx2_COM_b06FwReleaseFix = 0x0; | ||
21 | static u32 bnx2_COM_b06FwStartAddr = 0x080004a0; | ||
22 | static u32 bnx2_COM_b06FwTextAddr = 0x08000000; | ||
23 | static int bnx2_COM_b06FwTextLen = 0x4594; | ||
24 | static u32 bnx2_COM_b06FwDataAddr = 0x080045e0; | ||
25 | static int bnx2_COM_b06FwDataLen = 0x0; | ||
26 | static u32 bnx2_COM_b06FwRodataAddr = 0x08004598; | ||
27 | static int bnx2_COM_b06FwRodataLen = 0x18; | ||
28 | static u32 bnx2_COM_b06FwBssAddr = 0x08004600; | ||
29 | static int bnx2_COM_b06FwBssLen = 0x88; | ||
30 | static u32 bnx2_COM_b06FwSbssAddr = 0x080045e0; | ||
31 | static int bnx2_COM_b06FwSbssLen = 0x1c; | ||
32 | static u32 bnx2_COM_b06FwText[(0x4594/4) + 1] = { | ||
33 | 0x0a000128, 0x00000000, 0x00000000, 0x0000000d, 0x636f6d20, 0x302e362e, | ||
34 | 0x39000000, 0x00060902, 0x00000000, 0x00000003, 0x00000014, 0x00000032, | ||
35 | 0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
36 | 0x00000010, 0x000003e8, 0x0000ea60, 0x00000001, 0x00000000, 0x00000000, | ||
37 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
38 | 0x0000ffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
39 | 0x00000000, 0x00000000, 0x00000002, 0x00000020, 0x00000000, 0x00000000, | ||
40 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
41 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
42 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
43 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
44 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
45 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
46 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
47 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
48 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
49 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
50 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
51 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
52 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
53 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
54 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
55 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
56 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
57 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
58 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
59 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
60 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
61 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
62 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
63 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
64 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
65 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
66 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
67 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
68 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
69 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
70 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
71 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
72 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
73 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
74 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
75 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
76 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
77 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
78 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
79 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
80 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
81 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
82 | 0x00000000, 0x00000000, 0x00000000, 0x10000003, 0x00000000, 0x0000000d, | ||
83 | 0x0000000d, 0x3c020800, 0x244245e0, 0x3c030800, 0x24634688, 0xac400000, | ||
84 | 0x0043202b, 0x1480fffd, 0x24420004, 0x3c1d0800, 0x37bd7ffc, 0x03a0f021, | ||
85 | 0x3c100800, 0x261004a0, 0x3c1c0800, 0x279c45e0, 0x0e0001f2, 0x00000000, | ||
86 | 0x0000000d, 0x27bdffe8, 0x3c1a8000, 0x3c020008, 0x0342d825, 0x3c036010, | ||
87 | 0xafbf0010, 0x8c655000, 0x3c020800, 0x24470ac8, 0x3c040800, 0x24864600, | ||
88 | 0x2402ff7f, 0x00a22824, 0x34a5380c, 0xac655000, 0x00002821, 0x24020037, | ||
89 | 0x24030c80, 0xaf420008, 0xaf430024, 0xacc70000, 0x24a50001, 0x2ca20016, | ||
90 | 0x1440fffc, 0x24c60004, 0x24844600, 0x3c020800, 0x24420ad4, 0x3c030800, | ||
91 | 0x246309d4, 0xac820004, 0x3c020800, 0x24420618, 0x3c050800, 0x24a50ca0, | ||
92 | 0xac82000c, 0x3c020800, 0x24423100, 0xac830008, 0x3c030800, 0x246325c8, | ||
93 | 0xac820014, 0x3c020800, 0x24422b0c, 0xac830018, 0xac83001c, 0x3c030800, | ||
94 | 0x24630adc, 0xac820024, 0x3c020800, 0x24423040, 0xac83002c, 0x3c030800, | ||
95 | 0x24633060, 0xac820030, 0x3c020800, 0x24422f6c, 0xac830034, 0x3c030800, | ||
96 | 0x24632c60, 0xac82003c, 0x3c020800, 0x24420b6c, 0xac850010, 0xac850020, | ||
97 | 0xac830040, 0x0e000bd6, 0xac820050, 0x8fbf0010, 0x03e00008, 0x27bd0018, | ||
98 | 0x27bdffe0, 0xafb00010, 0x27500100, 0xafbf0018, 0xafb10014, 0x9203000b, | ||
99 | 0x24020003, 0x1462005b, 0x96110008, 0x32220001, 0x10400009, 0x27430080, | ||
100 | 0x8e020000, 0x96040014, 0x000211c2, 0x00021040, 0x00621821, 0xa4640000, | ||
101 | 0x0a0001cb, 0x3c020800, 0x3c020800, 0x8c430020, 0x1060002a, 0x3c030800, | ||
102 | 0x0e001006, 0x00000000, 0x97420108, 0x8f850018, 0x9743010c, 0x3042003e, | ||
103 | 0x00021400, 0x00621825, 0xaca30000, 0x8f840018, 0x8f420100, 0xac820004, | ||
104 | 0x97430116, 0x9742010e, 0x8f840018, 0x00031c00, 0x00431025, 0xac820008, | ||
105 | 0x97430110, 0x97440112, 0x8f850018, 0x00031c00, 0x00832025, 0xaca4000c, | ||
106 | 0x97420114, 0x8f840018, 0x3042ffff, 0xac820010, 0x8f830018, 0xac600014, | ||
107 | 0x8f820018, 0x3c030800, 0xac400018, 0x9462466e, 0x8f840018, 0x3c032000, | ||
108 | 0x00431025, 0xac82001c, 0x0e001044, 0x24040001, 0x3c030800, 0x8c620040, | ||
109 | 0x24420001, 0xac620040, 0x3c020800, 0x8c430044, 0x32240004, 0x24630001, | ||
110 | 0x10800017, 0xac430044, 0x8f4202b8, 0x04430007, 0x8e020020, 0x3c040800, | ||
111 | 0x8c830060, 0x24020001, 0x24630001, 0x0a0001ed, 0xac830060, 0x3c060800, | ||
112 | 0x8cc4005c, 0xaf420280, 0x96030016, 0x00001021, 0xa7430284, 0x8e050004, | ||
113 | 0x24840001, 0x3c031000, 0xaf450288, 0xaf4302b8, 0x0a0001ed, 0xacc4005c, | ||
114 | 0x32220002, 0x0a0001ed, 0x0002102b, 0x3c026000, 0xac400808, 0x0000000d, | ||
115 | 0x00001021, 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, | ||
116 | 0x27bdffc8, 0xafbf0034, 0xafbe0030, 0xafb7002c, 0xafb60028, 0xafb50024, | ||
117 | 0xafb40020, 0xafb3001c, 0xafb20018, 0xafb10014, 0x0e00013f, 0xafb00010, | ||
118 | 0x24110020, 0x24150030, 0x2794000c, 0x27930008, 0x3c124000, 0x3c1e0800, | ||
119 | 0x3c170800, 0x3c160800, 0x8f820004, 0x3c040800, 0x8c830020, 0x10430004, | ||
120 | 0x00000000, 0xaf830004, 0x0e00110b, 0x00000000, 0x8f500000, 0x32020007, | ||
121 | 0x1040fff5, 0x32020001, 0x1040002b, 0x32020002, 0x8f420100, 0xaf420020, | ||
122 | 0x8f430104, 0xaf4300a8, 0x9342010b, 0x93630000, 0x306300ff, 0x10710005, | ||
123 | 0x304400ff, 0x10750006, 0x2c820016, 0x0a000227, 0x00000000, 0xaf940000, | ||
124 | 0x0a000228, 0x2c820016, 0xaf930000, 0x0a000228, 0x00000000, 0xaf800000, | ||
125 | 0x14400005, 0x00041880, 0x0e0002b2, 0x00000000, 0x0a000234, 0x00000000, | ||
126 | 0x3c020800, 0x24424600, 0x00621821, 0x8c620000, 0x0040f809, 0x00000000, | ||
127 | 0x10400005, 0x8fc20034, 0x8f420104, 0x3c016020, 0xac220014, 0x8fc20034, | ||
128 | 0xaf520138, 0x24420001, 0xafc20034, 0x32020002, 0x10400019, 0x32020004, | ||
129 | 0x8f420140, 0xaf420020, 0x93630000, 0x306300ff, 0x10710005, 0x00000000, | ||
130 | 0x10750006, 0x00000000, 0x0a000250, 0x00000000, 0xaf940000, 0x0a000251, | ||
131 | 0x00000000, 0xaf930000, 0x0a000251, 0x00000000, 0xaf800000, 0x0e0008b9, | ||
132 | 0x00000000, 0x8ee20038, 0xaf520178, 0x24420001, 0xaee20038, 0x32020004, | ||
133 | 0x1040ffad, 0x00000000, 0x8f420180, 0xaf420020, 0x93630000, 0x306300ff, | ||
134 | 0x10710005, 0x00000000, 0x10750006, 0x00000000, 0x0a00026a, 0x00000000, | ||
135 | 0xaf940000, 0x0a00026b, 0x00000000, 0xaf930000, 0x0a00026b, 0x00000000, | ||
136 | 0xaf800000, 0x93620000, 0x14510004, 0x8ec2003c, 0x0e000835, 0x00000000, | ||
137 | 0x8ec2003c, 0xaf5201b8, 0x24420001, 0x0a000206, 0xaec2003c, 0x27bdffe8, | ||
138 | 0xafbf0010, 0x97420108, 0x24033000, 0x30447000, 0x10830012, 0x28823001, | ||
139 | 0x10400007, 0x24024000, 0x1080000b, 0x24022000, 0x1082001a, 0x24020001, | ||
140 | 0x0a000299, 0x00000000, 0x1082000c, 0x24025000, 0x1082000e, 0x00000000, | ||
141 | 0x0a000299, 0x00000000, 0x0000000d, 0x0a00029b, 0x00001021, 0x0e000300, | ||
142 | 0x00000000, 0x0a00029b, 0x00001021, 0x0e00048f, 0x00000000, 0x0a00029b, | ||
143 | 0x00001021, 0x0e000fdf, 0x00000000, 0x0a00029b, 0x00001021, 0x0000000d, | ||
144 | 0x00001021, 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x93620000, 0x24030020, | ||
145 | 0x304400ff, 0x10830005, 0x24020030, 0x10820007, 0x00000000, 0x0a0002af, | ||
146 | 0x00000000, 0x2782000c, 0xaf820000, 0x03e00008, 0x00000000, 0x27820008, | ||
147 | 0xaf820000, 0x03e00008, 0x00000000, 0xaf800000, 0x03e00008, 0x00000000, | ||
148 | 0x0000000d, 0x03e00008, 0x00001021, 0x03e00008, 0x00001021, 0x27440100, | ||
149 | 0x94830008, 0x30620004, 0x10400017, 0x30620002, 0x8f4202b8, 0x04430007, | ||
150 | 0x8c820020, 0x3c040800, 0x8c830060, 0x24020001, 0x24630001, 0x03e00008, | ||
151 | 0xac830060, 0xaf420280, 0x94830016, 0x3c060800, 0xa7430284, 0x8c850004, | ||
152 | 0x8cc4005c, 0x00001021, 0x3c031000, 0x24840001, 0xaf450288, 0xaf4302b8, | ||
153 | 0x03e00008, 0xacc4005c, 0x14400003, 0x3c040800, 0x03e00008, 0x00001021, | ||
154 | 0x8c830084, 0x24020001, 0x24630001, 0x03e00008, 0xac830084, 0x27450100, | ||
155 | 0x3c040800, 0x8c820088, 0x94a3000c, 0x24420001, 0x007a1821, 0xac820088, | ||
156 | 0x8ca40018, 0x90664000, 0xaf440038, 0x8ca2001c, 0x2403fff8, 0x00063600, | ||
157 | 0x00431024, 0x34420004, 0x3c030005, 0xaf42003c, 0xaf430030, 0x00000000, | ||
158 | 0x00000000, 0x00000000, 0xaf460404, 0x00000000, 0x00000000, 0x00000000, | ||
159 | 0x3c020006, 0x34420001, 0xaf420030, 0x00000000, 0x00000000, 0x00000000, | ||
160 | 0x8f420000, 0x30420010, 0x1040fffd, 0x00001021, 0x03e00008, 0x00000000, | ||
161 | 0x3c020800, 0x8c430020, 0x27bdffe8, 0xafb00010, 0x27500100, 0x1060001e, | ||
162 | 0xafbf0014, 0x0e001006, 0x00000000, 0x8f830018, 0x8e020018, 0xac620000, | ||
163 | 0x8f840018, 0x9602000c, 0xac820004, 0x8f830018, 0xac600008, 0x8f820018, | ||
164 | 0xac40000c, 0x8f830018, 0xac600010, 0x8f820018, 0xac400014, 0x8f840018, | ||
165 | 0x3c026000, 0x8c434448, 0xac830018, 0x96020008, 0x3c030800, 0x9464466e, | ||
166 | 0x8f850018, 0x00021400, 0x00441025, 0x24040001, 0x0e001044, 0xaca2001c, | ||
167 | 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdffc8, 0xafb3001c, | ||
168 | 0x00009821, 0xafb7002c, 0x0000b821, 0xafbe0030, 0x0000f021, 0xafb50024, | ||
169 | 0x27550100, 0xafbf0034, 0xafb60028, 0xafb40020, 0xafb20018, 0xafb10014, | ||
170 | 0xafb00010, 0x96a20008, 0x8f540100, 0x8eb20018, 0x30420001, 0x10400037, | ||
171 | 0x02a0b021, 0x8f630054, 0x2642ffff, 0x00431023, 0x18400006, 0x00000000, | ||
172 | 0x0000000d, 0x00000000, 0x24000128, 0x0a000372, 0x00002021, 0x8f62004c, | ||
173 | 0x02421023, 0x18400028, 0x00002021, 0x93650120, 0x93640121, 0x3c030800, | ||
174 | 0x8c62008c, 0x308400ff, 0x24420001, 0x30a500ff, 0x00803821, 0x1485000b, | ||
175 | 0xac62008c, 0x3c040800, 0x8c830090, 0x24630001, 0xac830090, 0x93620122, | ||
176 | 0x30420001, 0x00021023, 0x30420005, 0x0a000372, 0x34440004, 0x27660100, | ||
177 | 0x00041080, 0x00c21021, 0x8c430000, 0x02431823, 0x04600004, 0x24820001, | ||
178 | 0x30440007, 0x1485fff9, 0x00041080, 0x10870007, 0x3c030800, 0xa3640121, | ||
179 | 0x8c620094, 0x24040005, 0x24420001, 0x0a000372, 0xac620094, 0x24040004, | ||
180 | 0x00809821, 0x9362003f, 0x304400ff, 0x38830016, 0x2c630001, 0x38820010, | ||
181 | 0x2c420001, 0x00621825, 0x1460000c, 0x24020001, 0x38830008, 0x2c630001, | ||
182 | 0x38820014, 0x2c420001, 0x00621825, 0x14600005, 0x24020001, 0x24020012, | ||
183 | 0x14820002, 0x00001021, 0x24020001, 0x50400007, 0x8eb10020, 0x8ea20020, | ||
184 | 0x8f630040, 0x00408821, 0x00431023, 0x5c400001, 0x8f710040, 0x9343010b, | ||
185 | 0x24020004, 0x54620005, 0x36730080, 0x96a20008, 0x36730002, 0x24170001, | ||
186 | 0x305e0020, 0x2402fffb, 0x02628024, 0x1200002a, 0x3c030800, 0x8c620030, | ||
187 | 0x02021024, 0x10400026, 0x3c020800, 0x8c430020, 0x10600024, 0x32620004, | ||
188 | 0x0e001006, 0x00000000, 0x8f830018, 0x8f420100, 0xac620000, 0x8f840018, | ||
189 | 0x02201821, 0x32620002, 0xac900004, 0x8f840018, 0x50400001, 0x8ec30014, | ||
190 | 0xac830008, 0x8f830018, 0x8ec20020, 0xac62000c, 0x8f840018, 0x8f620040, | ||
191 | 0xac820010, 0x8f830018, 0x8ec20018, 0xac620014, 0x8f840018, 0x3c026000, | ||
192 | 0x8c434448, 0x3c020800, 0xac830018, 0x9443466e, 0x8f840018, 0x3c024010, | ||
193 | 0x00621825, 0xac83001c, 0x0e001044, 0x24040001, 0x32620004, 0x10400076, | ||
194 | 0x00003821, 0x3c029000, 0x34420001, 0x3c038000, 0x02821025, 0xa360007c, | ||
195 | 0xaf420020, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93620023, | ||
196 | 0x30420080, 0x10400011, 0x00000000, 0x8f65005c, 0x8f63004c, 0x9764003c, | ||
197 | 0x8f620064, 0x00a32823, 0x00852821, 0x00a2102b, 0x54400006, 0x3c023fff, | ||
198 | 0x93620023, 0x3042007f, 0xa3620023, 0xaf720064, 0x3c023fff, 0x0a0003f1, | ||
199 | 0x3442ffff, 0x8f62005c, 0x02421023, 0x04400011, 0x00000000, 0x8f65005c, | ||
200 | 0x8f630064, 0x9764003c, 0x3c023fff, 0x3442ffff, 0xaf720064, 0x00a32823, | ||
201 | 0x00852821, 0x0045102b, 0x10400004, 0x02451021, 0x3c053fff, 0x34a5ffff, | ||
202 | 0x02451021, 0xaf62005c, 0x24070001, 0xaf72004c, 0x8f620054, 0x16420005, | ||
203 | 0x00000000, 0x93620023, 0x30420040, 0x10400017, 0x24020001, 0x9762006a, | ||
204 | 0x00022880, 0x50a00001, 0x24050001, 0x97630068, 0x93640081, 0x3c020800, | ||
205 | 0x8c46004c, 0x00652821, 0x00852804, 0x00c5102b, 0x54400001, 0x00a03021, | ||
206 | 0x3c020800, 0x8c440050, 0x00c4182b, 0x54600001, 0x00c02021, 0x8f420074, | ||
207 | 0x2403fffe, 0x00832824, 0x00a21021, 0xaf62000c, 0x3c028000, 0x34420001, | ||
208 | 0x02821025, 0xa3600081, 0xaf420020, 0x9363007e, 0x9362007a, 0x10620004, | ||
209 | 0x00000000, 0x0e000f2a, 0x00000000, 0x00403821, 0x10e00017, 0x3c029000, | ||
210 | 0x34420001, 0x02821025, 0xaf420020, 0x3c038000, 0x8f420020, 0x00431024, | ||
211 | 0x1440fffd, 0x3c028000, 0x9363007d, 0x34420001, 0x3c048000, 0x02821025, | ||
212 | 0xa363007d, 0xaf420020, 0x8f4201f8, 0x00441024, 0x1440fffd, 0x24020002, | ||
213 | 0x3c031000, 0xaf5401c0, 0xa34201c4, 0xaf4301f8, 0x8ea30014, 0x8f620040, | ||
214 | 0x14430003, 0x00431023, 0x0a000443, 0x00001021, 0x28420001, 0x10400034, | ||
215 | 0x00000000, 0x8f620040, 0xaf630040, 0x9362003e, 0x30420001, 0x1440000b, | ||
216 | 0x3c029000, 0x93620022, 0x24420001, 0xa3620022, 0x93630022, 0x3c020800, | ||
217 | 0x8c440098, 0x0064182b, 0x1460001e, 0x3c020800, 0x3c029000, 0x34420001, | ||
218 | 0x02821025, 0xaf420020, 0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd, | ||
219 | 0x00000000, 0x3c038000, 0x9362007d, 0x34630001, 0x3c048000, 0x02831825, | ||
220 | 0x34420001, 0xa362007d, 0xaf430020, 0x8f4201f8, 0x00441024, 0x1440fffd, | ||
221 | 0x24020002, 0x3c031000, 0xaf5401c0, 0xa34201c4, 0x24020001, 0xaf4301f8, | ||
222 | 0xa7620012, 0x0a000476, 0xa3600022, 0x9743007a, 0x9444002a, 0x00641821, | ||
223 | 0x3063fffe, 0xa7630012, 0x0e000b68, 0x00000000, 0x12e00003, 0x00000000, | ||
224 | 0x0e000f27, 0x00000000, 0x53c00004, 0x96a20008, 0x0e000c10, 0x00000000, | ||
225 | 0x96a20008, 0x8fbf0034, 0x8fbe0030, 0x8fb7002c, 0x8fb60028, 0x8fb50024, | ||
226 | 0x8fb40020, 0x8fb3001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x00021042, | ||
227 | 0x30420001, 0x03e00008, 0x27bd0038, 0x27bdffe8, 0xafbf0010, 0x97420108, | ||
228 | 0x2403000b, 0x304400ff, 0x1083004e, 0x2882000c, 0x10400011, 0x24020006, | ||
229 | 0x1082003e, 0x28820007, 0x10400007, 0x28820008, 0x1080002b, 0x24020001, | ||
230 | 0x1082002e, 0x3c026000, 0x0a000504, 0x00000000, 0x14400061, 0x2882000a, | ||
231 | 0x1440002b, 0x00000000, 0x0a0004ec, 0x00000000, 0x2402001c, 0x1082004e, | ||
232 | 0x2882001d, 0x1040000e, 0x24020019, 0x10820041, 0x2882001a, 0x10400005, | ||
233 | 0x2402000e, 0x10820036, 0x00000000, 0x0a000504, 0x00000000, 0x2402001b, | ||
234 | 0x1082003c, 0x00000000, 0x0a000504, 0x00000000, 0x240200c1, 0x10820040, | ||
235 | 0x288200c2, 0x10400005, 0x24020080, 0x1082001f, 0x00000000, 0x0a000504, | ||
236 | 0x00000000, 0x240200c2, 0x1082003b, 0x00000000, 0x0a000504, 0x00000000, | ||
237 | 0x3c026000, 0x0e000c7d, 0xac400808, 0x0a000506, 0x8fbf0010, 0x8c444448, | ||
238 | 0x3c030800, 0xac640064, 0x0e000c7d, 0x00000000, 0x3c026000, 0x8c444448, | ||
239 | 0x3c030800, 0x0a000505, 0xac640068, 0x8f440100, 0x0e000508, 0x00000000, | ||
240 | 0x3c026000, 0x8c444448, 0x3c030800, 0x0a000505, 0xac64006c, 0x0e000cab, | ||
241 | 0x00000000, 0x0a000506, 0x8fbf0010, 0x8f440100, 0x0e000cd5, 0x00000000, | ||
242 | 0x0a000506, 0x8fbf0010, 0x0e000d1c, 0x00000000, 0x0a000506, 0x8fbf0010, | ||
243 | 0x0000000d, 0x0a000506, 0x8fbf0010, 0x0e0005d7, 0x00000000, 0x0a000506, | ||
244 | 0x8fbf0010, 0x8f440100, 0x0e000d7e, 0x00000000, 0x0a000506, 0x8fbf0010, | ||
245 | 0x0e000e95, 0x00000000, 0x0a000506, 0x8fbf0010, 0x0e000626, 0x00000000, | ||
246 | 0x0a000506, 0x8fbf0010, 0x0e000b68, 0x00000000, 0x0a000506, 0x8fbf0010, | ||
247 | 0x0000000d, 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x27bdffe8, 0x3c029000, | ||
248 | 0x34420001, 0xafb00010, 0x00808021, 0x02021025, 0x3c038000, 0xafbf0014, | ||
249 | 0xaf420020, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93620005, | ||
250 | 0x34420001, 0xa3620005, 0x8f63004c, 0x8f620054, 0x10620019, 0x3c028000, | ||
251 | 0x9762006a, 0x00022880, 0x50a00001, 0x24050001, 0x97630068, 0x93640081, | ||
252 | 0x3c020800, 0x8c46004c, 0x00652821, 0x00852804, 0x00c5102b, 0x54400001, | ||
253 | 0x00a03021, 0x3c020800, 0x8c440050, 0x00c4182b, 0x54600001, 0x00c02021, | ||
254 | 0x8f420074, 0x2403fffe, 0x00832824, 0x00a21021, 0xaf62000c, 0x3c028000, | ||
255 | 0x34420001, 0x02021025, 0x0e000c7d, 0xaf420020, 0x3c029000, 0x34420001, | ||
256 | 0x3c038000, 0x02021025, 0xaf420020, 0x8f420020, 0x00431024, 0x1440fffd, | ||
257 | 0x3c028000, 0x9363007d, 0x34420001, 0x3c048000, 0x02021025, 0xa363007d, | ||
258 | 0xaf420020, 0x8f4201f8, 0x00441024, 0x1440fffd, 0x8fbf0014, 0xaf5001c0, | ||
259 | 0x8fb00010, 0x24020002, 0x3c031000, 0xa34201c4, 0xaf4301f8, 0x03e00008, | ||
260 | 0x27bd0018, 0x27bdffd8, 0xafbf0020, 0xafb3001c, 0xafb20018, 0xafb10014, | ||
261 | 0xafb00010, 0x93630005, 0x00809021, 0x24020030, 0x30630030, 0x14620072, | ||
262 | 0x00a09821, 0x3c020800, 0x8c430020, 0x1060006c, 0x00000000, 0x0e001006, | ||
263 | 0x00000000, 0x8f820018, 0xac520000, 0x9363003e, 0x9362003f, 0x8f840018, | ||
264 | 0x00031a00, 0x00431025, 0xac820004, 0x93630081, 0x93620082, 0x8f850018, | ||
265 | 0x00031e00, 0x00021400, 0x00621825, 0xaca30008, 0x8f840018, 0x8f620040, | ||
266 | 0xac82000c, 0x8f830018, 0x8f620048, 0xac620010, 0x8f840018, 0x8f62004c, | ||
267 | 0x3c110800, 0xac820014, 0x8f830018, 0x8f620050, 0x26304660, 0x00002021, | ||
268 | 0xac620018, 0x9602000e, 0x8f850018, 0x3c03c00b, 0x00431025, 0x0e001044, | ||
269 | 0xaca2001c, 0x8f830018, 0x8f620054, 0xac620000, 0x8f840018, 0x8f620058, | ||
270 | 0xac820004, 0x8f830018, 0x8f62005c, 0xac620008, 0x8f840018, 0x8f620060, | ||
271 | 0xac82000c, 0x8f850018, 0x8f620064, 0xaca20010, 0x97630068, 0x9762006a, | ||
272 | 0x8f840018, 0x00031c00, 0x00431025, 0xac820014, 0x8f830018, 0x00002021, | ||
273 | 0xac600018, 0x9602000e, 0x8f850018, 0x3c03c00c, 0x00431025, 0x0e001044, | ||
274 | 0xaca2001c, 0x8f840018, 0x8f630018, 0xac830000, 0x936200c4, 0x30420002, | ||
275 | 0x10400006, 0x00000000, 0x976200c8, 0x8f830018, 0x3042ffff, 0x0a0005b5, | ||
276 | 0xac620004, 0x8f820018, 0xac400004, 0x8f830018, 0x8f62006c, 0xac620008, | ||
277 | 0x8f840018, 0x8f6200dc, 0xac82000c, 0x8f830018, 0xac600010, 0x93620005, | ||
278 | 0x8f830018, 0x00021600, 0x00531025, 0xac620014, 0x8f850018, 0x3c026000, | ||
279 | 0x8c434448, 0x24040001, 0x26224660, 0xaca30018, 0x9443000e, 0x8f850018, | ||
280 | 0x3c02400d, 0x00621825, 0x0e001044, 0xaca3001c, 0x0e000d48, 0x02402021, | ||
281 | 0x8fbf0020, 0x8fb3001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, | ||
282 | 0x27bd0028, 0x27bdffe0, 0xafb00010, 0x27500100, 0xafbf0018, 0xafb10014, | ||
283 | 0x9603000c, 0x240200c1, 0x5462001d, 0x8e040000, 0x3c029000, 0x8f440100, | ||
284 | 0x34420001, 0x3c038000, 0x00821025, 0xaf420020, 0x8f420020, 0x00431024, | ||
285 | 0x1440fffd, 0x00000000, 0x3c038000, 0x9362007d, 0x34630001, 0x3c058000, | ||
286 | 0x00831825, 0x34420004, 0xa362007d, 0xaf430020, 0x8f4201f8, 0x00451024, | ||
287 | 0x1440fffd, 0x24020002, 0x3c031000, 0xaf4401c0, 0xa34201c4, 0xaf4301f8, | ||
288 | 0x0a000622, 0x8fbf0018, 0x8f65004c, 0x24060001, 0x0e000db5, 0x2407049f, | ||
289 | 0x3c020800, 0x8c430020, 0x9611000c, 0x1060001d, 0x8e100000, 0x0e001006, | ||
290 | 0x00000000, 0x8f820018, 0xac500000, 0x8f840018, 0x00111400, 0xac820004, | ||
291 | 0x8f830018, 0xac600008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010, | ||
292 | 0x8f840018, 0x240204a2, 0xac820014, 0x8f850018, 0x3c026000, 0x8c434448, | ||
293 | 0x24040001, 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018, 0x3c024019, | ||
294 | 0x00621825, 0x0e001044, 0xaca3001c, 0x8fbf0018, 0x8fb10014, 0x8fb00010, | ||
295 | 0x03e00008, 0x27bd0020, 0x27bdffb0, 0xafb1002c, 0x27510100, 0xafbf004c, | ||
296 | 0xafbe0048, 0xafb70044, 0xafb60040, 0xafb5003c, 0xafb40038, 0xafb30034, | ||
297 | 0xafb20030, 0xafb00028, 0x8e350000, 0x9634000c, 0x3c026000, 0x8c434448, | ||
298 | 0x0000f021, 0xaf630170, 0x8f620040, 0x8e230014, 0x0000b821, 0x00431023, | ||
299 | 0x044001ec, 0x0000b021, 0x32820010, 0x1040002e, 0x3c026000, 0x9363003f, | ||
300 | 0x9222000e, 0x10430006, 0x2402000c, 0x9223000f, 0x10620003, 0x24020014, | ||
301 | 0x14620025, 0x3c026000, 0x32820004, 0x10400007, 0x241e0001, 0x8f620050, | ||
302 | 0x24420001, 0xaf620050, 0x8f630054, 0x24630001, 0xaf630054, 0x32830102, | ||
303 | 0x24020002, 0x5462000d, 0x9222000f, 0x8f620040, 0x24420001, 0xaf620040, | ||
304 | 0x8f630048, 0x8f620040, 0x24630001, 0x54620005, 0x9222000f, 0x8f620048, | ||
305 | 0x24420001, 0xaf620048, 0x9222000f, 0xa362003f, 0x9223000f, 0x24020012, | ||
306 | 0x14620007, 0x3c026000, 0x3c030800, 0x8c620074, 0x24420001, 0x0e000f6e, | ||
307 | 0xac620074, 0x3c026000, 0x8c434448, 0x32820040, 0xaf630174, 0x32830020, | ||
308 | 0xafa30010, 0x32830080, 0xafa30014, 0x32830001, 0xafa3001c, 0x32830008, | ||
309 | 0xafa30020, 0x32830100, 0x104000bb, 0xafa30018, 0x8e260010, 0x8f630054, | ||
310 | 0x24c2ffff, 0x00431023, 0x18400006, 0x00000000, 0x0000000d, 0x00000000, | ||
311 | 0x24000128, 0x0a0006b2, 0x00009021, 0x8f62004c, 0x00c21023, 0x18400028, | ||
312 | 0x00009021, 0x93650120, 0x93640121, 0x3c030800, 0x8c62008c, 0x308400ff, | ||
313 | 0x24420001, 0x30a500ff, 0x00804021, 0x1485000b, 0xac62008c, 0x3c040800, | ||
314 | 0x8c830090, 0x24630001, 0xac830090, 0x93620122, 0x30420001, 0x00021023, | ||
315 | 0x30420005, 0x0a0006b2, 0x34520004, 0x27670100, 0x00041080, 0x00e21021, | ||
316 | 0x8c430000, 0x00c31823, 0x04600004, 0x24820001, 0x30440007, 0x1485fff9, | ||
317 | 0x00041080, 0x10880007, 0x3c030800, 0xa3640121, 0x8c620094, 0x24120005, | ||
318 | 0x24420001, 0x0a0006b2, 0xac620094, 0x24120004, 0x32420001, 0x10400020, | ||
319 | 0x3c020800, 0x8c430020, 0x8e300000, 0x1060001c, 0x8e330010, 0x0e001006, | ||
320 | 0x00000000, 0x8f820018, 0xac500000, 0x8f840018, 0x24020001, 0xac820004, | ||
321 | 0x8f830018, 0xac600008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010, | ||
322 | 0x8f820018, 0xac530014, 0x8f850018, 0x3c026000, 0x8c434448, 0x24040001, | ||
323 | 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018, 0x3c024010, 0x00621825, | ||
324 | 0x0e001044, 0xaca3001c, 0x32420004, 0x10400060, 0x00003821, 0x3c029000, | ||
325 | 0x8e260010, 0x34420001, 0x3c038000, 0x02a21025, 0xa360007c, 0xaf420020, | ||
326 | 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93620023, 0x30420080, | ||
327 | 0x10400011, 0x00000000, 0x8f65005c, 0x8f63004c, 0x9764003c, 0x8f620064, | ||
328 | 0x00a32823, 0x00852821, 0x00a2102b, 0x54400006, 0x3c023fff, 0x93620023, | ||
329 | 0x3042007f, 0xa3620023, 0xaf660064, 0x3c023fff, 0x0a000702, 0x3442ffff, | ||
330 | 0x8f62005c, 0x00c21023, 0x04400011, 0x00000000, 0x8f65005c, 0x8f630064, | ||
331 | 0x9764003c, 0x3c023fff, 0x3442ffff, 0xaf660064, 0x00a32823, 0x00852821, | ||
332 | 0x0045102b, 0x10400004, 0x00c51021, 0x3c053fff, 0x34a5ffff, 0x00c51021, | ||
333 | 0xaf62005c, 0x24070001, 0xaf66004c, 0x8f620054, 0x14c20005, 0x00000000, | ||
334 | 0x93620023, 0x30420040, 0x10400017, 0x24020001, 0x9762006a, 0x00022880, | ||
335 | 0x50a00001, 0x24050001, 0x97630068, 0x93640081, 0x3c020800, 0x8c46004c, | ||
336 | 0x00652821, 0x00852804, 0x00c5102b, 0x54400001, 0x00a03021, 0x3c020800, | ||
337 | 0x8c440050, 0x00c4182b, 0x54600001, 0x00c02021, 0x8f420074, 0x2403fffe, | ||
338 | 0x00832824, 0x00a21021, 0xaf62000c, 0x3c028000, 0x34420001, 0x02a21025, | ||
339 | 0xa3600081, 0xaf420020, 0x9363007e, 0x9362007a, 0x10620005, 0x00e0b021, | ||
340 | 0x0e000f2a, 0x00000000, 0x00403821, 0x00e0b021, 0x8fa20010, 0x10400008, | ||
341 | 0x00000000, 0x8e220018, 0xaf620018, 0x8e23001c, 0xaf63001c, 0x8e220020, | ||
342 | 0x24160001, 0xaf620058, 0x13c00036, 0x32820004, 0x10400035, 0x8fa30014, | ||
343 | 0x93620023, 0x30420040, 0x10400031, 0x3c020800, 0x8c430020, 0x1060001c, | ||
344 | 0x8e300000, 0x0e001006, 0x00000000, 0x8f820018, 0xac500000, 0x8f830018, | ||
345 | 0xac600004, 0x8f820018, 0xac400008, 0x8f830018, 0xac60000c, 0x8f820018, | ||
346 | 0xac400010, 0x8f830018, 0x24020587, 0xac620014, 0x8f850018, 0x3c026000, | ||
347 | 0x8c434448, 0x24040001, 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018, | ||
348 | 0x3c024019, 0x00621825, 0x0e001044, 0xaca3001c, 0x3c029000, 0x34420001, | ||
349 | 0x02a21025, 0xaf420020, 0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd, | ||
350 | 0x24020001, 0xaf62000c, 0x93630023, 0x3c028000, 0x34420001, 0x02a21025, | ||
351 | 0x306300bf, 0xa3630023, 0xaf420020, 0x8fa30014, 0x10600012, 0x8fa3001c, | ||
352 | 0x9362007c, 0x24420001, 0xa362007c, 0x9363007e, 0x9362007a, 0x1462000b, | ||
353 | 0x8fa3001c, 0x9362007c, 0x3c030800, 0x8c640024, 0x0044102b, 0x14400005, | ||
354 | 0x8fa3001c, 0x0e000f2a, 0x00000000, 0x02c2b025, 0x8fa3001c, 0x3062ffff, | ||
355 | 0x10400003, 0x32820200, 0x0a000793, 0x24170004, 0x10400003, 0x00000000, | ||
356 | 0x24170040, 0x24160001, 0x13c0005d, 0x32820002, 0x1040005c, 0x8fa20020, | ||
357 | 0x9222000a, 0x30420020, 0x10400033, 0x3c100800, 0x93620023, 0x30420040, | ||
358 | 0x1040002f, 0x8e020020, 0x1040001e, 0x3c029000, 0x0e001006, 0x00000000, | ||
359 | 0x8f820018, 0xac550000, 0x8f840018, 0x3c02008d, 0xac820004, 0x8f830018, | ||
360 | 0xac600008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010, 0x8f840018, | ||
361 | 0x240205bf, 0xac820014, 0x8f850018, 0x3c026000, 0x8c434448, 0x24040001, | ||
362 | 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018, 0x3c024019, 0x00621825, | ||
363 | 0x0e001044, 0xaca3001c, 0x3c029000, 0x34420001, 0x02a21025, 0xaf420020, | ||
364 | 0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93630023, | ||
365 | 0x3c028000, 0x34420001, 0x02a21025, 0x306300bf, 0xa3630023, 0xaf420020, | ||
366 | 0x8e020020, 0x10400023, 0x8fa20020, 0x0e001006, 0x00000000, 0x8f840018, | ||
367 | 0x8e230000, 0xac830000, 0x9222000a, 0x8f830018, 0x00021600, 0xac620004, | ||
368 | 0x8f840018, 0x8f620040, 0xac820008, 0x8f850018, 0x8f63004c, 0xaca3000c, | ||
369 | 0x9362003f, 0x8f840018, 0x304200ff, 0xac820010, 0x8f830018, 0x3c026000, | ||
370 | 0xac600014, 0x8f850018, 0x8c434448, 0x24040001, 0x3c020800, 0xaca30018, | ||
371 | 0x9443466e, 0x8f850018, 0x3c02401a, 0x00621825, 0x0e001044, 0xaca3001c, | ||
372 | 0x8fa20020, 0x1040000e, 0x8fa20018, 0x9222000a, 0xa3620082, 0x56e00005, | ||
373 | 0x36f70008, 0x8fa30018, 0x10600004, 0x00000000, 0x36f70008, 0x0a000801, | ||
374 | 0x24160001, 0x0e000de1, 0x02a02021, 0x8fa20018, 0x10400003, 0x00000000, | ||
375 | 0x36f70010, 0x24160001, 0x12c00019, 0x3c029000, 0x34420001, 0x02a21025, | ||
376 | 0xaf420020, 0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, | ||
377 | 0x3c038000, 0x9362007d, 0x34630001, 0x3c048000, 0x02a31825, 0x02e21025, | ||
378 | 0xa362007d, 0xaf430020, 0x8f4201f8, 0x00441024, 0x1440fffd, 0x24020002, | ||
379 | 0x3c031000, 0xaf5501c0, 0xa34201c4, 0xaf4301f8, 0x9363003f, 0x24020012, | ||
380 | 0x14620004, 0x3c026000, 0x0e000f6e, 0x00000000, 0x3c026000, 0x8c434448, | ||
381 | 0xaf630178, 0x8fbf004c, 0x8fbe0048, 0x8fb70044, 0x8fb60040, 0x8fb5003c, | ||
382 | 0x8fb40038, 0x8fb30034, 0x8fb20030, 0x8fb1002c, 0x8fb00028, 0x03e00008, | ||
383 | 0x27bd0050, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f500180, 0x97420184, | ||
384 | 0x30420200, 0x14400015, 0x00000000, 0x8f430188, 0x3c02ff00, 0x00621824, | ||
385 | 0x3c020200, 0x10620031, 0x0043102b, 0x14400007, 0x3c020300, 0x1060000b, | ||
386 | 0x3c020100, 0x1062000d, 0x00000000, 0x0a0008b4, 0x00000000, 0x10620027, | ||
387 | 0x3c020400, 0x1062003e, 0x02002021, 0x0a0008b4, 0x00000000, 0x0e000e1e, | ||
388 | 0x02002021, 0x0a0008b6, 0x8fbf0014, 0x93620005, 0x30420020, 0x1440005e, | ||
389 | 0x8fbf0014, 0x3c029000, 0x34420001, 0x02021025, 0xaf420020, 0x3c038000, | ||
390 | 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93620005, 0x3c038000, | ||
391 | 0x34630001, 0x02031825, 0x34420020, 0xa3620005, 0xaf430020, 0x93620005, | ||
392 | 0x30420020, 0x14400003, 0x02002021, 0x0000000d, 0x02002021, 0x0e000553, | ||
393 | 0x24055854, 0x0a0008b6, 0x8fbf0014, 0x93620005, 0x30420001, 0x1040003f, | ||
394 | 0x3c029000, 0x34420001, 0x02021025, 0xaf420020, 0x3c038000, 0x8f420020, | ||
395 | 0x00431024, 0x1440fffd, 0x00000000, 0x93620005, 0x3c048000, 0x3c030800, | ||
396 | 0x304200fe, 0xa3620005, 0x8c620020, 0x34840001, 0x02042025, 0xaf440020, | ||
397 | 0x1040002d, 0x8fbf0014, 0x0a000894, 0x00000000, 0x00002821, 0x00003021, | ||
398 | 0x0e000f78, 0x240706a4, 0x3c020800, 0x8c430020, 0x10600023, 0x8fbf0014, | ||
399 | 0x0e001006, 0x00000000, 0x8f820018, 0xac500000, 0x93630082, 0x9362003f, | ||
400 | 0x8f840018, 0x00031a00, 0x00431025, 0xac820004, 0x8f830018, 0xac600008, | ||
401 | 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010, 0x8f820018, 0xac400014, | ||
402 | 0x8f850018, 0x3c026000, 0x8c434448, 0x24040001, 0x3c020800, 0xaca30018, | ||
403 | 0x9443466e, 0x8f850018, 0x3c02400a, 0x00621825, 0x0e001044, 0xaca3001c, | ||
404 | 0x0a0008b6, 0x8fbf0014, 0x0000000d, 0x8fbf0014, 0x8fb00010, 0x03e00008, | ||
405 | 0x27bd0018, 0x27bdffe8, 0xafbf0010, 0x93420148, 0x2444ffff, 0x2c830005, | ||
406 | 0x10600047, 0x3c020800, 0x24424598, 0x00041880, 0x00621821, 0x8c640000, | ||
407 | 0x00800008, 0x00000000, 0x8f430144, 0x8f62000c, 0x14620006, 0x24020001, | ||
408 | 0xaf62000c, 0x0e000909, 0x00000000, 0x0a000907, 0x8fbf0010, 0x8f62000c, | ||
409 | 0x0a000900, 0x00000000, 0x97630010, 0x8f420144, 0x14430006, 0x24020001, | ||
410 | 0xa7620010, 0x0e000eeb, 0x00000000, 0x0a000907, 0x8fbf0010, 0x97620010, | ||
411 | 0x0a000900, 0x00000000, 0x97630012, 0x8f420144, 0x14430006, 0x24020001, | ||
412 | 0xa7620012, 0x0e000f06, 0x00000000, 0x0a000907, 0x8fbf0010, 0x97620012, | ||
413 | 0x0a000900, 0x00000000, 0x97630014, 0x8f420144, 0x14430006, 0x24020001, | ||
414 | 0xa7620014, 0x0e000f21, 0x00000000, 0x0a000907, 0x8fbf0010, 0x97620014, | ||
415 | 0x0a000900, 0x00000000, 0x97630016, 0x8f420144, 0x14430006, 0x24020001, | ||
416 | 0xa7620016, 0x0e000f24, 0x00000000, 0x0a000907, 0x8fbf0010, 0x97620016, | ||
417 | 0x14400006, 0x8fbf0010, 0x3c030800, 0x8c620070, 0x24420001, 0xac620070, | ||
418 | 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x27bdffe8, 0xafbf0010, 0x93620081, | ||
419 | 0x3c030800, 0x8c640048, 0x0044102b, 0x14400028, 0x3c029000, 0x8f460140, | ||
420 | 0x34420001, 0x3c038000, 0x00c21025, 0xaf420020, 0x8f420020, 0x00431024, | ||
421 | 0x1440fffd, 0x3c048000, 0x34840001, 0x3c059000, 0x34a50001, 0x3c078000, | ||
422 | 0x24020012, 0x24030080, 0x00c42025, 0x00c52825, 0xa362003f, 0xa3630082, | ||
423 | 0xaf440020, 0xaf450020, 0x8f420020, 0x00471024, 0x1440fffd, 0x3c038000, | ||
424 | 0x9362007d, 0x34630001, 0x3c048000, 0x00c31825, 0x34420020, 0xa362007d, | ||
425 | 0xaf430020, 0x8f4201f8, 0x00441024, 0x1440fffd, 0x24020002, 0x3c031000, | ||
426 | 0x0a00096d, 0xaf4601c0, 0x93620081, 0x24420001, 0x0e000f2a, 0xa3620081, | ||
427 | 0x9763006a, 0x00032880, 0x14a00002, 0x00403821, 0x24050001, 0x97630068, | ||
428 | 0x93640081, 0x3c020800, 0x8c46004c, 0x00652821, 0x00852804, 0x00c5102b, | ||
429 | 0x54400001, 0x00a03021, 0x3c020800, 0x8c440050, 0x00c4182b, 0x54600001, | ||
430 | 0x00c02021, 0x8f420074, 0x2403fffe, 0x00832824, 0x00a21021, 0xaf62000c, | ||
431 | 0x10e0001a, 0x3c029000, 0x8f440140, 0x34420001, 0x3c038000, 0x00821025, | ||
432 | 0xaf420020, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x3c038000, | ||
433 | 0x9362007d, 0x34630001, 0x3c058000, 0x00831825, 0x34420004, 0xa362007d, | ||
434 | 0xaf430020, 0x8f4201f8, 0x00451024, 0x1440fffd, 0x24020002, 0x3c031000, | ||
435 | 0xaf4401c0, 0xa34201c4, 0xaf4301f8, 0x8fbf0010, 0x03e00008, 0x27bd0018, | ||
436 | 0x27bdffd8, 0xafb3001c, 0x27530100, 0xafbf0024, 0xafb40020, 0xafb20018, | ||
437 | 0xafb10014, 0xafb00010, 0x96620008, 0x3c140800, 0x8f520100, 0x30420001, | ||
438 | 0x104000cf, 0x00000000, 0x8e700018, 0x8f630054, 0x2602ffff, 0x00431023, | ||
439 | 0x18400006, 0x00000000, 0x0000000d, 0x00000000, 0x24000128, 0x0a0009b6, | ||
440 | 0x00008821, 0x8f62004c, 0x02021023, 0x18400028, 0x00008821, 0x93650120, | ||
441 | 0x93640121, 0x3c030800, 0x8c62008c, 0x308400ff, 0x24420001, 0x30a500ff, | ||
442 | 0x00803821, 0x1485000b, 0xac62008c, 0x3c040800, 0x8c830090, 0x24630001, | ||
443 | 0xac830090, 0x93620122, 0x30420001, 0x00021023, 0x30420005, 0x0a0009b6, | ||
444 | 0x34510004, 0x27660100, 0x00041080, 0x00c21021, 0x8c430000, 0x02031823, | ||
445 | 0x04600004, 0x24820001, 0x30440007, 0x1485fff9, 0x00041080, 0x10870007, | ||
446 | 0x3c030800, 0xa3640121, 0x8c620094, 0x24110005, 0x24420001, 0x0a0009b6, | ||
447 | 0xac620094, 0x24110004, 0x32220001, 0x1040001e, 0x8e820020, 0x1040001d, | ||
448 | 0x32220004, 0x0e001006, 0x00000000, 0x8f820018, 0xac520000, 0x8f840018, | ||
449 | 0x24020001, 0xac820004, 0x8f830018, 0xac600008, 0x8f820018, 0xac40000c, | ||
450 | 0x8f830018, 0xac600010, 0x8f820018, 0xac500014, 0x8f850018, 0x3c026000, | ||
451 | 0x8c434448, 0x24040001, 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018, | ||
452 | 0x3c024010, 0x00621825, 0x0e001044, 0xaca3001c, 0x32220004, 0x10400076, | ||
453 | 0x00003821, 0x3c029000, 0x34420001, 0x3c038000, 0x02421025, 0xa360007c, | ||
454 | 0xaf420020, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93620023, | ||
455 | 0x30420080, 0x10400011, 0x00000000, 0x8f65005c, 0x8f63004c, 0x9764003c, | ||
456 | 0x8f620064, 0x00a32823, 0x00852821, 0x00a2102b, 0x54400006, 0x3c023fff, | ||
457 | 0x93620023, 0x3042007f, 0xa3620023, 0xaf700064, 0x3c023fff, 0x0a000a03, | ||
458 | 0x3442ffff, 0x8f62005c, 0x02021023, 0x04400011, 0x00000000, 0x8f65005c, | ||
459 | 0x8f630064, 0x9764003c, 0x3c023fff, 0x3442ffff, 0xaf700064, 0x00a32823, | ||
460 | 0x00852821, 0x0045102b, 0x10400004, 0x02051021, 0x3c053fff, 0x34a5ffff, | ||
461 | 0x02051021, 0xaf62005c, 0x24070001, 0xaf70004c, 0x8f620054, 0x16020005, | ||
462 | 0x00000000, 0x93620023, 0x30420040, 0x10400017, 0x24020001, 0x9762006a, | ||
463 | 0x00022880, 0x50a00001, 0x24050001, 0x97630068, 0x93640081, 0x3c020800, | ||
464 | 0x8c46004c, 0x00652821, 0x00852804, 0x00c5102b, 0x54400001, 0x00a03021, | ||
465 | 0x3c020800, 0x8c440050, 0x00c4182b, 0x54600001, 0x00c02021, 0x8f420074, | ||
466 | 0x2403fffe, 0x00832824, 0x00a21021, 0xaf62000c, 0x3c028000, 0x34420001, | ||
467 | 0x02421025, 0xa3600081, 0xaf420020, 0x9363007e, 0x9362007a, 0x10620004, | ||
468 | 0x00000000, 0x0e000f2a, 0x00000000, 0x00403821, 0x10e00017, 0x3c029000, | ||
469 | 0x34420001, 0x02421025, 0xaf420020, 0x3c038000, 0x8f420020, 0x00431024, | ||
470 | 0x1440fffd, 0x3c028000, 0x9363007d, 0x34420001, 0x3c048000, 0x02421025, | ||
471 | 0xa363007d, 0xaf420020, 0x8f4201f8, 0x00441024, 0x1440fffd, 0x24020002, | ||
472 | 0x3c031000, 0xaf5201c0, 0xa34201c4, 0xaf4301f8, 0x9342010b, 0x8e830020, | ||
473 | 0x27500100, 0x38420006, 0x10600029, 0x2c510001, 0x0e001006, 0x00000000, | ||
474 | 0x8f830018, 0x8e020000, 0xac620000, 0x8f840018, 0x96020008, 0xac820004, | ||
475 | 0x8f830018, 0x8e020014, 0xac620008, 0x8f850018, 0x3c026000, 0x8c434448, | ||
476 | 0xaca3000c, 0x8f840018, 0x96020012, 0xac820010, 0x8f850018, 0x8e030020, | ||
477 | 0xaca30014, 0x9602000c, 0x9603000e, 0x8f840018, 0x00021400, 0x00431025, | ||
478 | 0xac820018, 0x12200005, 0x3c020800, 0x9443466e, 0x8f840018, 0x0a000a78, | ||
479 | 0x3c024013, 0x9443466e, 0x8f840018, 0x3c024014, 0x00621825, 0xac83001c, | ||
480 | 0x0e001044, 0x24040001, 0x8e630014, 0x8f620040, 0x14430003, 0x00431023, | ||
481 | 0x0a000a83, 0x00001021, 0x28420001, 0x10400034, 0x00000000, 0x8f620040, | ||
482 | 0xaf630040, 0x9362003e, 0x30420001, 0x1440000b, 0x3c029000, 0x93620022, | ||
483 | 0x24420001, 0xa3620022, 0x93630022, 0x3c020800, 0x8c440098, 0x0064182b, | ||
484 | 0x1460001e, 0x3c020800, 0x3c029000, 0x34420001, 0x02421025, 0xaf420020, | ||
485 | 0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x3c038000, | ||
486 | 0x9362007d, 0x34630001, 0x3c048000, 0x02431825, 0x34420001, 0xa362007d, | ||
487 | 0xaf430020, 0x8f4201f8, 0x00441024, 0x1440fffd, 0x24020002, 0x3c031000, | ||
488 | 0xaf5201c0, 0xa34201c4, 0x24020001, 0xaf4301f8, 0xa7620012, 0x0a000ab6, | ||
489 | 0xa3600022, 0x9743007a, 0x9444002a, 0x00641821, 0x3063fffe, 0xa7630012, | ||
490 | 0x0e000b68, 0x00000000, 0x97420108, 0x8fbf0024, 0x8fb40020, 0x8fb3001c, | ||
491 | 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x00021042, 0x30420001, 0x03e00008, | ||
492 | 0x27bd0028, 0x27bdffe0, 0xafb20018, 0x3c120800, 0x8e420020, 0xafb00010, | ||
493 | 0x27500100, 0xafbf001c, 0x10400046, 0xafb10014, 0x0e001006, 0x00000000, | ||
494 | 0x8f840018, 0x8e020000, 0xac820000, 0x936300b1, 0x936200c5, 0x8f850018, | ||
495 | 0x00031e00, 0x00021400, 0x34420100, 0x00621825, 0xaca30004, 0x8f840018, | ||
496 | 0x8e02001c, 0xac820008, 0x8f830018, 0x8f620048, 0xac62000c, 0x8f840018, | ||
497 | 0x96020012, 0xac820010, 0x8f830018, 0x8f620040, 0x24040001, 0xac620014, | ||
498 | 0x8f850018, 0x3c026000, 0x8c434448, 0x3c020800, 0x24514660, 0xaca30018, | ||
499 | 0x9623000e, 0x8f850018, 0x3c024016, 0x00621825, 0x0e001044, 0xaca3001c, | ||
500 | 0x96030008, 0x30630010, 0x1060001c, 0x8e420020, 0x1040001a, 0x8e100000, | ||
501 | 0x0e001006, 0x00000000, 0x8f820018, 0xac500000, 0x8f830018, 0xac600004, | ||
502 | 0x8f820018, 0xac400008, 0x8f830018, 0xac60000c, 0x8f820018, 0xac400010, | ||
503 | 0x8f830018, 0xac600014, 0x8f850018, 0x3c036000, 0x8c634448, 0x24040001, | ||
504 | 0xaca30018, 0x9622000e, 0x8f850018, 0x3c034015, 0x00431025, 0x0e001044, | ||
505 | 0xaca2001c, 0x00001021, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, | ||
506 | 0x03e00008, 0x27bd0020, 0x27bdffe0, 0xafb20018, 0x3c120800, 0x8e420020, | ||
507 | 0xafb00010, 0x27500100, 0xafbf001c, 0x10400041, 0xafb10014, 0x0e001006, | ||
508 | 0x00000000, 0x8f830018, 0x8e020000, 0xac620000, 0x8f840018, 0x24020100, | ||
509 | 0xac820004, 0x8f830018, 0x8e02001c, 0xac620008, 0x8f840018, 0x8e020018, | ||
510 | 0xac82000c, 0x8f830018, 0x96020012, 0xac620010, 0x8f840018, 0x96020008, | ||
511 | 0xac820014, 0x8f850018, 0x3c026000, 0x8c434448, 0x24040001, 0x3c020800, | ||
512 | 0x24514660, 0xaca30018, 0x9623000e, 0x8f850018, 0x3c024017, 0x00621825, | ||
513 | 0x0e001044, 0xaca3001c, 0x96030008, 0x30630010, 0x1060001c, 0x8e420020, | ||
514 | 0x1040001a, 0x8e100000, 0x0e001006, 0x00000000, 0x8f820018, 0xac500000, | ||
515 | 0x8f830018, 0xac600004, 0x8f820018, 0xac400008, 0x8f830018, 0xac60000c, | ||
516 | 0x8f820018, 0xac400010, 0x8f830018, 0xac600014, 0x8f850018, 0x3c036000, | ||
517 | 0x8c634448, 0x24040001, 0xaca30018, 0x9622000e, 0x8f850018, 0x3c034015, | ||
518 | 0x00431025, 0x0e001044, 0xaca2001c, 0x00001021, 0x8fbf001c, 0x8fb20018, | ||
519 | 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x27bdffe8, 0xafbf0010, | ||
520 | 0x936200c4, 0x30420002, 0x10400019, 0x00000000, 0x936200c5, 0x936300b1, | ||
521 | 0x00431023, 0x304400ff, 0x30830080, 0x10600004, 0x00000000, 0x0000000d, | ||
522 | 0x00000000, 0x24000a6a, 0x93620004, 0x00441023, 0x304400ff, 0x30830080, | ||
523 | 0x10600004, 0x2482ffff, 0x8f650024, 0x0a000b82, 0x00000000, 0x00022b00, | ||
524 | 0x8f620024, 0x0045102b, 0x10400002, 0x00000000, 0x8f650024, 0x8f620048, | ||
525 | 0x8f630040, 0x00431823, 0x0065202b, 0x10800004, 0x00000000, 0x8f620040, | ||
526 | 0x00451021, 0xaf620048, 0x9762003c, 0x0062102b, 0x10400041, 0x8fbf0010, | ||
527 | 0x10a0003f, 0x3c029000, 0x34420001, 0x3c040800, 0x8c830080, 0x8f450100, | ||
528 | 0x3c068000, 0x24630001, 0x00a21025, 0xac830080, 0xaf420020, 0x8f420020, | ||
529 | 0x00461024, 0x1440fffd, 0x3c038000, 0x9362007d, 0x34630001, 0x3c048000, | ||
530 | 0x00a31825, 0x34420004, 0xa362007d, 0xaf430020, 0x8f4201f8, 0x00441024, | ||
531 | 0x1440fffd, 0x24020002, 0x3c030800, 0xaf4501c0, 0xa34201c4, 0x8c640020, | ||
532 | 0x3c021000, 0xaf4201f8, 0x1080001f, 0x8fbf0010, 0x0e001006, 0x00000000, | ||
533 | 0x8f830018, 0x8f420100, 0xac620000, 0x8f840018, 0x8f620040, 0xac820004, | ||
534 | 0x8f850018, 0x8f620048, 0xaca20008, 0x8f830018, 0xac60000c, 0x8f820018, | ||
535 | 0xac400010, 0x8f830018, 0x3c026000, 0xac600014, 0x8f840018, 0x8c434448, | ||
536 | 0x3c020800, 0xac830018, 0x9443466e, 0x8f840018, 0x3c0240c2, 0x00621825, | ||
537 | 0xac83001c, 0x0e001044, 0x24040001, 0x8fbf0010, 0x03e00008, 0x27bd0018, | ||
538 | 0x3c020800, 0x24423958, 0xaf82000c, 0x03e00008, 0x00000000, 0x27bdffe8, | ||
539 | 0xafb00010, 0x27500100, 0xafbf0014, 0x8e02001c, 0x14400003, 0x3c020800, | ||
540 | 0x0000000d, 0x3c020800, 0x8c430020, 0x10600026, 0x00001021, 0x0e001006, | ||
541 | 0x00000000, 0x8f830018, 0x8e020000, 0xac620000, 0x8f840018, 0x8e02001c, | ||
542 | 0xac820004, 0x8f830018, 0xac600008, 0x8f840018, 0x8e020018, 0xac82000c, | ||
543 | 0x8f850018, 0x96020012, 0xaca20010, 0x8f830018, 0x3c106000, 0xac600014, | ||
544 | 0x8f840018, 0x8e024448, 0x3c030800, 0xac820018, 0x9462466e, 0x8f840018, | ||
545 | 0x3c034012, 0x00431025, 0xac82001c, 0x0e001044, 0x24040001, 0x8e036800, | ||
546 | 0x00001021, 0x3c040001, 0x00641825, 0xae036800, 0x0a000c0d, 0x8fbf0014, | ||
547 | 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c020800, 0x97430078, | ||
548 | 0x9444002e, 0x00001021, 0x00641821, 0x3063fffe, 0x03e00008, 0xa7630010, | ||
549 | 0x27450100, 0x8f640048, 0x8ca30018, 0x00641023, 0x18400021, 0x00000000, | ||
550 | 0xaf630048, 0x8f620040, 0x9763003c, 0x00821023, 0x0043102a, 0x1040001a, | ||
551 | 0x3c029000, 0x8ca40000, 0x34420001, 0x3c038000, 0x00821025, 0xaf420020, | ||
552 | 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x3c038000, 0x9362007d, | ||
553 | 0x34630001, 0x3c058000, 0x00831825, 0x34420004, 0xa362007d, 0xaf430020, | ||
554 | 0x8f4201f8, 0x00451024, 0x1440fffd, 0x24020002, 0x3c031000, 0xaf4401c0, | ||
555 | 0xa34201c4, 0xaf4301f8, 0x03e00008, 0x00001021, 0x8f420100, 0x34420001, | ||
556 | 0xaf4200a4, 0x03e00008, 0x00001021, 0x27bdffe0, 0xafbf0018, 0xafb10014, | ||
557 | 0xafb00010, 0x9362007e, 0x30d000ff, 0x16020029, 0x00808821, 0x93620080, | ||
558 | 0x16020026, 0x00000000, 0x9362007f, 0x16020023, 0x00000000, 0x9362007a, | ||
559 | 0x16020004, 0x00000000, 0x0000000d, 0x00000000, 0x24000771, 0x0e000f49, | ||
560 | 0x00000000, 0x3c039000, 0x34630001, 0x3c048000, 0x02231825, 0xa370007a, | ||
561 | 0xaf430020, 0x8f420020, 0x00441024, 0x1440fffd, 0x3c028000, 0x9363007d, | ||
562 | 0x34420001, 0x3c048000, 0x02221025, 0xa363007d, 0xaf420020, 0x8f4201f8, | ||
563 | 0x00441024, 0x1440fffd, 0x24020002, 0x3c031000, 0xaf5101c0, 0xa34201c4, | ||
564 | 0xaf4301f8, 0x0a000c79, 0x8fbf0018, 0x0000000d, 0x00000000, 0x24000781, | ||
565 | 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c020800, | ||
566 | 0x8c430020, 0x27bdffe8, 0xafb00010, 0x27500100, 0x10600024, 0xafbf0014, | ||
567 | 0x0e001006, 0x00000000, 0x8f830018, 0x8e020000, 0xac620000, 0x8f840018, | ||
568 | 0x8e020004, 0xac820004, 0x8f830018, 0x8e020018, 0xac620008, 0x8f840018, | ||
569 | 0x8e03001c, 0xac83000c, 0x9602000c, 0x9203000a, 0x8f840018, 0x00021400, | ||
570 | 0x00431025, 0xac820010, 0x8f830018, 0x3c026000, 0xac600014, 0x8f840018, | ||
571 | 0x8c434448, 0xac830018, 0x96020008, 0x3c030800, 0x9464466e, 0x8f850018, | ||
572 | 0x00021400, 0x00441025, 0x24040001, 0x0e001044, 0xaca2001c, 0x8fbf0014, | ||
573 | 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c020800, 0x8c430020, 0x27bdffe8, | ||
574 | 0xafb00010, 0x27500100, 0x10600020, 0xafbf0014, 0x0e001006, 0x00000000, | ||
575 | 0x8f820018, 0xac400000, 0x8f830018, 0xac600004, 0x8f820018, 0xac400008, | ||
576 | 0x8f830018, 0xac60000c, 0x9602000c, 0x9603000e, 0x8f840018, 0x00021400, | ||
577 | 0x00431025, 0xac820010, 0x8f830018, 0x3c026000, 0xac600014, 0x8f840018, | ||
578 | 0x8c434448, 0xac830018, 0x96020008, 0x3c030800, 0x9464466e, 0x8f850018, | ||
579 | 0x00021400, 0x00441025, 0x24040001, 0x0e001044, 0xaca2001c, 0x8fbf0014, | ||
580 | 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdffe8, 0xafb00010, 0x27500100, | ||
581 | 0xafbf0014, 0x9602000c, 0x10400024, 0x00802821, 0x3c020800, 0x8c430020, | ||
582 | 0x1060003a, 0x8fbf0014, 0x0e001006, 0x00000000, 0x8f840018, 0x8e030000, | ||
583 | 0xac830000, 0x9602000c, 0x8f840018, 0x00021400, 0xac820004, 0x8f830018, | ||
584 | 0xac600008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010, 0x8f820018, | ||
585 | 0xac400014, 0x8f850018, 0x3c026000, 0x8c434448, 0x24040001, 0x3c020800, | ||
586 | 0xaca30018, 0x9443466e, 0x8f850018, 0x3c02400b, 0x00621825, 0x0e001044, | ||
587 | 0xaca3001c, 0x0a000d19, 0x8fbf0014, 0x93620005, 0x30420010, 0x14400015, | ||
588 | 0x3c029000, 0x34420001, 0x00a21025, 0xaf420020, 0x3c038000, 0x8f420020, | ||
589 | 0x00431024, 0x1440fffd, 0x00000000, 0x3c038000, 0x93620005, 0x34630001, | ||
590 | 0x00a02021, 0x00a31825, 0x24055852, 0x34420010, 0xa3620005, 0x0e000553, | ||
591 | 0xaf430020, 0x0a000d19, 0x8fbf0014, 0x0000000d, 0x8fbf0014, 0x8fb00010, | ||
592 | 0x03e00008, 0x27bd0018, 0x3c020800, 0x8c430020, 0x27bdffe8, 0xafb00010, | ||
593 | 0x27500100, 0x10600022, 0xafbf0014, 0x0e001006, 0x00000000, 0x8f840018, | ||
594 | 0x8e020004, 0xac820000, 0x9603000c, 0x9762002c, 0x8f840018, 0x00031c00, | ||
595 | 0x00431025, 0xac820004, 0x8f830018, 0xac600008, 0x8f820018, 0xac40000c, | ||
596 | 0x8f830018, 0xac600010, 0x8f820018, 0xac400014, 0x8f850018, 0x3c026000, | ||
597 | 0x8c434448, 0x24040001, 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018, | ||
598 | 0x3c02400e, 0x00621825, 0x0e001044, 0xaca3001c, 0x0e000d48, 0x8e040000, | ||
599 | 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c038000, 0x8f420278, | ||
600 | 0x00431024, 0x1440fffd, 0x24020002, 0x3c031000, 0xaf440240, 0xa3420244, | ||
601 | 0x03e00008, 0xaf430278, 0x3c020800, 0x8c430020, 0x27bdffe0, 0xafb10014, | ||
602 | 0x00808821, 0xafb20018, 0x00c09021, 0xafb00010, 0x30b0ffff, 0x1060001c, | ||
603 | 0xafbf001c, 0x0e001006, 0x00000000, 0x8f820018, 0xac510000, 0x8f840018, | ||
604 | 0x00101400, 0xac820004, 0x8f830018, 0xac600008, 0x8f820018, 0xac40000c, | ||
605 | 0x8f830018, 0xac600010, 0x8f820018, 0xac520014, 0x8f840018, 0x3c026000, | ||
606 | 0x8c434448, 0x3c020800, 0xac830018, 0x9443466e, 0x8f840018, 0x3c024019, | ||
607 | 0x00621825, 0xac83001c, 0x0e001044, 0x24040001, 0x8fbf001c, 0x8fb20018, | ||
608 | 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x27bdffe8, 0x27450100, | ||
609 | 0xafbf0010, 0x94a3000c, 0x240200c1, 0x14620029, 0x00803021, 0x3c029000, | ||
610 | 0x34420001, 0x00c21025, 0xaf420020, 0x3c038000, 0x8f420020, 0x00431024, | ||
611 | 0x1440fffd, 0x3c028000, 0x34420001, 0x3c049000, 0x34840001, 0x3c058000, | ||
612 | 0x24030012, 0x00c21025, 0x00c42025, 0xa363003f, 0xaf420020, 0xaf440020, | ||
613 | 0x8f420020, 0x00451024, 0x1440fffd, 0x3c038000, 0x9362007d, 0x34630001, | ||
614 | 0x3c048000, 0x00c31825, 0x34420020, 0xa362007d, 0xaf430020, 0x8f4201f8, | ||
615 | 0x00441024, 0x1440fffd, 0x24020002, 0x3c031000, 0xaf4601c0, 0xa34201c4, | ||
616 | 0xaf4301f8, 0x0a000db3, 0x8fbf0010, 0x00c02021, 0x94a5000c, 0x24060001, | ||
617 | 0x0e000f78, 0x240706d8, 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x3c020800, | ||
618 | 0x8c430020, 0x27bdffe0, 0xafb00010, 0x00808021, 0xafb20018, 0x00a09021, | ||
619 | 0xafb10014, 0x30d100ff, 0x1060001c, 0xafbf001c, 0x0e001006, 0x00000000, | ||
620 | 0x8f820018, 0xac500000, 0x8f840018, 0x24020001, 0xac820004, 0x8f830018, | ||
621 | 0xac600008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010, 0x8f820018, | ||
622 | 0xac520014, 0x8f840018, 0x3c026000, 0x8c434448, 0x3c020800, 0xac830018, | ||
623 | 0x9443466e, 0x8f840018, 0x3c024010, 0x00621825, 0xac83001c, 0x0e001044, | ||
624 | 0x02202021, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, | ||
625 | 0x27bd0020, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x93620005, 0x30420001, | ||
626 | 0x10400033, 0x00808021, 0x3c029000, 0x34420001, 0x02021025, 0xaf420020, | ||
627 | 0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93620005, | ||
628 | 0x3c048000, 0x3c030800, 0x304200fe, 0xa3620005, 0x8c620020, 0x34840001, | ||
629 | 0x02042025, 0xaf440020, 0x10400020, 0x8fbf0014, 0x0e001006, 0x00000000, | ||
630 | 0x8f820018, 0xac500000, 0x93630082, 0x9362003f, 0x8f840018, 0x00031a00, | ||
631 | 0x00431025, 0xac820004, 0x8f830018, 0xac600008, 0x8f820018, 0xac40000c, | ||
632 | 0x8f830018, 0xac600010, 0x8f820018, 0xac400014, 0x8f840018, 0x3c026000, | ||
633 | 0x8c434448, 0x3c020800, 0xac830018, 0x9443466e, 0x8f840018, 0x3c02400a, | ||
634 | 0x00621825, 0xac83001c, 0x0e001044, 0x24040001, 0x8fbf0014, 0x8fb00010, | ||
635 | 0x03e00008, 0x27bd0018, 0x27bdffe8, 0xafbf0010, 0x8f420188, 0x00803021, | ||
636 | 0x9364003f, 0x24030012, 0x00021402, 0x1483001c, 0x304500ff, 0x3c029000, | ||
637 | 0x34420001, 0x3c038000, 0x00c21025, 0xa3650080, 0xa365007a, 0xaf420020, | ||
638 | 0x8f420020, 0x00431024, 0x1440fffd, 0x3c028000, 0x9363007d, 0x34420001, | ||
639 | 0x3c048000, 0x00c21025, 0xa363007d, 0xaf420020, 0x8f4201f8, 0x00441024, | ||
640 | 0x1440fffd, 0x24020002, 0x3c031000, 0xaf4601c0, 0xa34201c4, 0xaf4301f8, | ||
641 | 0x0a000e54, 0x8fbf0010, 0x9362007e, 0x1445000e, 0x00000000, 0x93620080, | ||
642 | 0x1045000b, 0x00000000, 0xa3650080, 0x8f820000, 0x93660080, 0x8f440180, | ||
643 | 0x8f65004c, 0x8c430000, 0x0060f809, 0x00000000, 0x0a000e54, 0x8fbf0010, | ||
644 | 0xa3650080, 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x3c020800, 0x8c430020, | ||
645 | 0x27bdffe0, 0xafb10014, 0x00808821, 0xafb20018, 0x00a09021, 0xafb00010, | ||
646 | 0x30d000ff, 0x1060002f, 0xafbf001c, 0x0e001006, 0x00000000, 0x8f820018, | ||
647 | 0xac510000, 0x8f830018, 0xac700004, 0x8f820018, 0xac520008, 0x8f830018, | ||
648 | 0xac60000c, 0x8f820018, 0xac400010, 0x9763006a, 0x00032880, 0x50a00001, | ||
649 | 0x24050001, 0x97630068, 0x93640081, 0x3c020800, 0x8c46004c, 0x00652821, | ||
650 | 0x00852804, 0x00c5102b, 0x54400001, 0x00a03021, 0x3c020800, 0x8c440050, | ||
651 | 0x00c4182b, 0x54600001, 0x00c02021, 0x8f830018, 0x2402fffe, 0x00822824, | ||
652 | 0x3c026000, 0xac650014, 0x8f840018, 0x8c434448, 0x3c020800, 0xac830018, | ||
653 | 0x9443466e, 0x8f840018, 0x3c024011, 0x00621825, 0xac83001c, 0x0e001044, | ||
654 | 0x24040001, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, | ||
655 | 0x27bd0020, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f440100, 0x27500100, | ||
656 | 0x8f650050, 0x0e000c45, 0x9206001b, 0x3c020800, 0x8c430020, 0x1060001d, | ||
657 | 0x8e100018, 0x0e001006, 0x00000000, 0x8f840018, 0x8f420100, 0xac820000, | ||
658 | 0x8f830018, 0xac700004, 0x8f840018, 0x8f620050, 0xac820008, 0x8f830018, | ||
659 | 0xac60000c, 0x8f820018, 0xac400010, 0x8f830018, 0x3c026000, 0xac600014, | ||
660 | 0x8f850018, 0x8c434448, 0x24040001, 0x3c020800, 0xaca30018, 0x9443466e, | ||
661 | 0x8f850018, 0x3c02401c, 0x00621825, 0x0e001044, 0xaca3001c, 0x8fbf0014, | ||
662 | 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c029000, 0x8f460140, 0x34420001, | ||
663 | 0x3c038000, 0x00c21025, 0xaf420020, 0x8f420020, 0x00431024, 0x1440fffd, | ||
664 | 0x3c048000, 0x34840001, 0x3c059000, 0x34a50001, 0x3c078000, 0x24020012, | ||
665 | 0x24030080, 0x00c42025, 0x00c52825, 0xa362003f, 0xa3630082, 0xaf440020, | ||
666 | 0xaf450020, 0x8f420020, 0x00471024, 0x1440fffd, 0x3c038000, 0x9362007d, | ||
667 | 0x34630001, 0x3c048000, 0x00c31825, 0x34420020, 0xa362007d, 0xaf430020, | ||
668 | 0x8f4201f8, 0x00441024, 0x1440fffd, 0x24020002, 0x3c031000, 0xaf4601c0, | ||
669 | 0xa34201c4, 0x03e00008, 0xaf4301f8, 0x8f430238, 0x3c020800, 0x04610013, | ||
670 | 0x8c44009c, 0x2406fffe, 0x3c050800, 0x3c038000, 0x2484ffff, 0x14800009, | ||
671 | 0x00000000, 0x97420078, 0x8ca3007c, 0x24420001, 0x00461024, 0x24630001, | ||
672 | 0xa7620010, 0x03e00008, 0xaca3007c, 0x8f420238, 0x00431024, 0x1440fff3, | ||
673 | 0x2484ffff, 0x8f420140, 0x3c031000, 0xaf420200, 0x03e00008, 0xaf430238, | ||
674 | 0x3c029000, 0x8f440140, 0x34420001, 0x3c038000, 0x00821025, 0xaf420020, | ||
675 | 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x3c038000, 0x9362007d, | ||
676 | 0x34630001, 0x3c058000, 0x00831825, 0x34420001, 0xa362007d, 0xaf430020, | ||
677 | 0x8f4201f8, 0x00451024, 0x1440fffd, 0x24020002, 0x3c031000, 0xaf4401c0, | ||
678 | 0xa34201c4, 0x03e00008, 0xaf4301f8, 0x0000000d, 0x03e00008, 0x00000000, | ||
679 | 0x0000000d, 0x03e00008, 0x00000000, 0x24020001, 0x03e00008, 0xa7620010, | ||
680 | 0x9362003f, 0x304400ff, 0x3883000e, 0x2c630001, 0x38820010, 0x2c420001, | ||
681 | 0x00621825, 0x14600003, 0x24020012, 0x14820003, 0x00000000, 0x03e00008, | ||
682 | 0x00001021, 0x9363007e, 0x9362007a, 0x14620006, 0x00000000, 0x9363007e, | ||
683 | 0x24020001, 0x24630001, 0x03e00008, 0xa363007e, 0x9363007e, 0x93620080, | ||
684 | 0x14620004, 0x24020001, 0xa362000b, 0x03e00008, 0x24020001, 0x03e00008, | ||
685 | 0x00001021, 0x9362000b, 0x10400021, 0x00001021, 0xa360000b, 0x9362003f, | ||
686 | 0x304400ff, 0x3883000e, 0x2c630001, 0x38820010, 0x2c420001, 0x00621825, | ||
687 | 0x14600015, 0x00001821, 0x24020012, 0x10820012, 0x00000000, 0x9363007e, | ||
688 | 0x9362007a, 0x14620007, 0x00000000, 0x9362007e, 0x24030001, 0x24420001, | ||
689 | 0xa362007e, 0x03e00008, 0x00601021, 0x9363007e, 0x93620080, 0x14620004, | ||
690 | 0x00001821, 0x24020001, 0xa362000b, 0x24030001, 0x03e00008, 0x00601021, | ||
691 | 0x03e00008, 0x00000000, 0x24040001, 0xaf64000c, 0x8f6300dc, 0x8f6200cc, | ||
692 | 0x50620001, 0xa7640010, 0xa7640012, 0xa7640014, 0x03e00008, 0xa7640016, | ||
693 | 0x27bdffd8, 0xafb00010, 0x00808021, 0xafb3001c, 0x00c09821, 0xafbf0020, | ||
694 | 0xafb20018, 0xafb10014, 0x93620023, 0x00e09021, 0x30420040, 0x10400020, | ||
695 | 0x30b1ffff, 0x3c020800, 0x8c430020, 0x1060001c, 0x00000000, 0x0e001006, | ||
696 | 0x00000000, 0x8f820018, 0xac500000, 0x8f840018, 0x3c02008d, 0xac820004, | ||
697 | 0x8f830018, 0xac600008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010, | ||
698 | 0x8f820018, 0xac520014, 0x8f850018, 0x3c026000, 0x8c434448, 0x24040001, | ||
699 | 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018, 0x3c024019, 0x00621825, | ||
700 | 0x0e001044, 0xaca3001c, 0x93620023, 0x30420020, 0x14400003, 0x3c020800, | ||
701 | 0x52600020, 0x3c029000, 0x8c430020, 0x1060001d, 0x3c029000, 0x0e001006, | ||
702 | 0x00000000, 0x8f820018, 0xac500000, 0x8f840018, 0x00111400, 0xac820004, | ||
703 | 0x8f830018, 0xac720008, 0x8f820018, 0xac40000c, 0x8f830018, 0xac600010, | ||
704 | 0x8f820018, 0xac400014, 0x8f850018, 0x3c026000, 0x8c434448, 0x24040001, | ||
705 | 0x3c020800, 0xaca30018, 0x9443466e, 0x8f850018, 0x3c02401b, 0x00621825, | ||
706 | 0x0e001044, 0xaca3001c, 0x3c029000, 0x34420001, 0x02021025, 0xaf420020, | ||
707 | 0x3c038000, 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x93630023, | ||
708 | 0x3c028000, 0x34420001, 0x02021025, 0x8fbf0020, 0x8fb3001c, 0x8fb20018, | ||
709 | 0x8fb10014, 0x8fb00010, 0x3063009f, 0xa3630023, 0xaf420020, 0x03e00008, | ||
710 | 0x27bd0028, 0x3c020800, 0x8c430020, 0x27bdffe8, 0xafb00010, 0x27500100, | ||
711 | 0x1060001d, 0xafbf0014, 0x0e001006, 0x00000000, 0x8f830018, 0x8e020004, | ||
712 | 0xac620000, 0x8f840018, 0x8e020018, 0xac820004, 0x8f850018, 0x8e020000, | ||
713 | 0xaca20008, 0x8f830018, 0xac60000c, 0x8f820018, 0xac400010, 0x8f830018, | ||
714 | 0xac600014, 0x8f820018, 0xac400018, 0x96030008, 0x3c020800, 0x9444466e, | ||
715 | 0x8f850018, 0x00031c00, 0x00641825, 0x24040001, 0x0e001044, 0xaca3001c, | ||
716 | 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c060800, 0x24c54660, | ||
717 | 0x3c02000a, 0x03421821, 0x94640006, 0x94a2000a, 0x00441023, 0x00021400, | ||
718 | 0x00021c03, 0x04610006, 0xa4a40006, 0x0000000d, 0x00000000, 0x2400005a, | ||
719 | 0x0a00101b, 0x24020001, 0x8f820014, 0x0062102b, 0x14400002, 0x00001021, | ||
720 | 0x24020001, 0x304200ff, 0x1040001c, 0x274a0400, 0x3c07000a, 0x3c020800, | ||
721 | 0x24454660, 0x94a9000a, 0x8f880014, 0x03471021, 0x94430006, 0x00402021, | ||
722 | 0xa4a30006, 0x94820006, 0xa4a20006, 0x01221023, 0x00021400, 0x00021403, | ||
723 | 0x04410006, 0x0048102b, 0x0000000d, 0x00000000, 0x2400005a, 0x0a001036, | ||
724 | 0x24020001, 0x14400002, 0x00001021, 0x24020001, 0x304200ff, 0x1440ffec, | ||
725 | 0x03471021, 0x24c44660, 0x8c820010, 0xaf420038, 0x8c830014, 0x3c020005, | ||
726 | 0xaf43003c, 0xaf420030, 0xaf800010, 0xaf8a0018, 0x03e00008, 0x00000000, | ||
727 | 0x27bdffe0, 0x8f820010, 0x8f850018, 0x3c070800, 0x24e84660, 0xafbf001c, | ||
728 | 0xafb20018, 0xafb10014, 0xafb00010, 0x9503000a, 0x8d060014, 0x00009021, | ||
729 | 0x309000ff, 0x00e08821, 0x24420001, 0x24a50020, 0x24630001, 0xaf820010, | ||
730 | 0xaf850018, 0xa503000a, 0x24c30020, 0x3c028000, 0x04c10007, 0xad030014, | ||
731 | 0x00621024, 0x14400005, 0x26224660, 0x8d020010, 0x24420001, 0xad020010, | ||
732 | 0x26224660, 0x9444000a, 0x94450018, 0x0010102b, 0x00a41826, 0x2c630001, | ||
733 | 0x00621825, 0x1060001c, 0x3c030006, 0x8f820010, 0x24120001, 0x00021140, | ||
734 | 0x00431025, 0xaf420030, 0x00000000, 0x00000000, 0x00000000, 0x27450400, | ||
735 | 0x8f420000, 0x30420010, 0x1040fffd, 0x26224660, 0x9444000a, 0x94430018, | ||
736 | 0xaf800010, 0xaf850018, 0x14830012, 0x26274660, 0x0e0010d2, 0x00000000, | ||
737 | 0x1600000e, 0x26274660, 0x0e001006, 0x00000000, 0x0a00108f, 0x26274660, | ||
738 | 0x00041c00, 0x00031c03, 0x00051400, 0x00021403, 0x00621823, 0x18600002, | ||
739 | 0x3c026000, 0xac400808, 0x26274660, 0x94e2000e, 0x94e3000c, 0x24420001, | ||
740 | 0xa4e2000e, 0x3042ffff, 0x50430001, 0xa4e0000e, 0x12000005, 0x3c02000a, | ||
741 | 0x94e2000a, 0xa74200a2, 0x0a0010cc, 0x02401021, 0x03421821, 0x94640006, | ||
742 | 0x94e2000a, 0x00441023, 0x00021400, 0x00021c03, 0x04610006, 0xa4e40006, | ||
743 | 0x0000000d, 0x00000000, 0x2400005a, 0x0a0010ae, 0x24020001, 0x8f820014, | ||
744 | 0x0062102b, 0x14400002, 0x00001021, 0x24020001, 0x304200ff, 0x1040001b, | ||
745 | 0x3c020800, 0x3c06000a, 0x24454660, 0x94a8000a, 0x8f870014, 0x03461021, | ||
746 | 0x94430006, 0x00402021, 0xa4a30006, 0x94820006, 0xa4a20006, 0x01021023, | ||
747 | 0x00021400, 0x00021403, 0x04410006, 0x0047102b, 0x0000000d, 0x00000000, | ||
748 | 0x2400005a, 0x0a0010c8, 0x24020001, 0x14400002, 0x00001021, 0x24020001, | ||
749 | 0x304200ff, 0x1440ffec, 0x03461021, 0x02401021, 0x8fbf001c, 0x8fb20018, | ||
750 | 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c020800, 0x24454660, | ||
751 | 0x94a3001a, 0x8ca40024, 0x00403021, 0x000318c0, 0x00832021, 0xaf44003c, | ||
752 | 0x8ca20020, 0xaf420038, 0x3c020050, 0x34420008, 0xaf420030, 0x00000000, | ||
753 | 0x00000000, 0x00000000, 0x8f420000, 0x30420020, 0x1040fffd, 0x00000000, | ||
754 | 0x8f430400, 0x24c64660, 0xacc30010, 0x8f420404, 0x3c030020, 0xacc20014, | ||
755 | 0xaf430030, 0x94c40018, 0x94c3001c, 0x94c2001a, 0x94c5001e, 0x00832021, | ||
756 | 0x24420001, 0xa4c2001a, 0x3042ffff, 0x14450002, 0xa4c40018, 0xa4c0001a, | ||
757 | 0x03e00008, 0x00000000, 0x8f820010, 0x3c030006, 0x00021140, 0x00431025, | ||
758 | 0xaf420030, 0x00000000, 0x00000000, 0x00000000, 0x27430400, 0x8f420000, | ||
759 | 0x30420010, 0x1040fffd, 0x00000000, 0xaf800010, 0xaf830018, 0x03e00008, | ||
760 | 0x00000000, 0x27bdffe8, 0xafb00010, 0x3c100800, 0x26104660, 0x3c05000a, | ||
761 | 0x02002021, 0x03452821, 0xafbf0014, 0x0e001128, 0x2406000a, 0x96020002, | ||
762 | 0x9603001e, 0x3042000f, 0x24420003, 0x00431804, 0x24027fff, 0x0043102b, | ||
763 | 0xaf830014, 0x10400004, 0x00000000, 0x0000000d, 0x00000000, 0x24000043, | ||
764 | 0x0e0010d2, 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, | ||
765 | 0x10c00007, 0x00000000, 0x8ca20000, 0x24c6ffff, 0x24a50004, 0xac820000, | ||
766 | 0x14c0fffb, 0x24840004, 0x03e00008, 0x00000000, 0x0a001137, 0x00a01021, | ||
767 | 0xac860000, 0x24840004, 0x00a01021, 0x1440fffc, 0x24a5ffff, 0x03e00008, | ||
768 | 0x00000000, 0x3c036000, 0x8c642b7c, 0x3c036010, 0x8c6553fc, 0x00041582, | ||
769 | 0x00042302, 0x308403ff, 0x00052d82, 0x00441026, 0x0002102b, 0x0005282b, | ||
770 | 0x00451025, 0x1440000d, 0x3c020050, 0x34420004, 0xaf400038, 0xaf40003c, | ||
771 | 0xaf420030, 0x00000000, 0x00000000, 0x8f420000, 0x30420020, 0x1040fffd, | ||
772 | 0x3c020020, 0xaf420030, 0x0000000d, 0x03e00008, 0x00000000, 0x3c020050, | ||
773 | 0x34420004, 0xaf440038, 0xaf45003c, 0xaf420030, 0x00000000, 0x00000000, | ||
774 | 0x8f420000, 0x30420020, 0x1040fffd, 0x3c020020, 0xaf420030, 0x03e00008, | ||
775 | 0x00000000, 0x00000000 }; | ||
776 | |||
777 | static u32 bnx2_COM_b06FwData[(0x0/4) + 1] = { 0x00000000 }; | ||
778 | static u32 bnx2_COM_b06FwRodata[(0x18/4) + 1] = { | ||
779 | 0x08002318, 0x08002348, 0x08002378, 0x080023a8, 0x080023d8, 0x00000000, | ||
780 | 0x00000000 }; | ||
781 | |||
782 | static u32 bnx2_COM_b06FwBss[(0x88/4) + 1] = { 0x00000000 }; | ||
783 | static u32 bnx2_COM_b06FwSbss[(0x1c/4) + 1] = { 0x00000000 }; | ||
784 | |||
785 | static int bnx2_RXP_b06FwReleaseMajor = 0x0; | ||
786 | static int bnx2_RXP_b06FwReleaseMinor = 0x0; | ||
787 | static int bnx2_RXP_b06FwReleaseFix = 0x0; | ||
788 | static u32 bnx2_RXP_b06FwStartAddr = 0x08000060; | ||
789 | static u32 bnx2_RXP_b06FwTextAddr = 0x08000000; | ||
790 | static int bnx2_RXP_b06FwTextLen = 0x20b8; | ||
791 | static u32 bnx2_RXP_b06FwDataAddr = 0x080020e0; | ||
792 | static int bnx2_RXP_b06FwDataLen = 0x0; | ||
793 | static u32 bnx2_RXP_b06FwRodataAddr = 0x00000000; | ||
794 | static int bnx2_RXP_b06FwRodataLen = 0x0; | ||
795 | static u32 bnx2_RXP_b06FwBssAddr = 0x08002100; | ||
796 | static int bnx2_RXP_b06FwBssLen = 0x239c; | ||
797 | static u32 bnx2_RXP_b06FwSbssAddr = 0x080020e0; | ||
798 | static int bnx2_RXP_b06FwSbssLen = 0x14; | ||
799 | |||
800 | static u32 bnx2_RXP_b06FwText[(0x20b8/4) + 1] = { | ||
801 | 0x0a000018, 0x00000000, 0x00000000, 0x0000000d, 0x72787020, 0x302e362e, | ||
802 | 0x39000000, 0x00060903, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, | ||
803 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
804 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
805 | 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c020800, | ||
806 | 0x244220e0, 0x3c030800, 0x2463449c, 0xac400000, 0x0043202b, 0x1480fffd, | ||
807 | 0x24420004, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100060, | ||
808 | 0x3c1c0800, 0x279c20e0, 0x0e000329, 0x00000000, 0x0000000d, 0x8f870008, | ||
809 | 0x2ce20080, 0x10400018, 0x3c030800, 0x24633490, 0x8f460100, 0x00072140, | ||
810 | 0x00831021, 0xac460000, 0x8f450104, 0x00641021, 0xac450004, 0x8f460108, | ||
811 | 0xac460008, 0x8f45010c, 0xac45000c, 0x8f460114, 0xac460010, 0x8f450118, | ||
812 | 0xac450014, 0x8f460124, 0xac460018, 0x8f450128, 0x00641821, 0x24e20001, | ||
813 | 0xaf820008, 0xac65001c, 0x03e00008, 0x00000000, 0x00804021, 0x8f830000, | ||
814 | 0x24070001, 0x3c020001, 0x00621024, 0x10400037, 0x00603021, 0x9742010e, | ||
815 | 0x3c038000, 0x3045ffff, 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020003, | ||
816 | 0xa342018b, 0x8f840004, 0x24020080, 0x24030002, 0xaf420180, 0xa743018c, | ||
817 | 0x10800005, 0xa745018e, 0x9743011c, 0x9742011e, 0x0a000069, 0x00021400, | ||
818 | 0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c, | ||
819 | 0x24020003, 0x30838000, 0x1060000d, 0xa7420188, 0x93420116, 0x304200fc, | ||
820 | 0x005a1021, 0x24424004, 0x8c430000, 0x3063ffff, 0x14600005, 0x00000000, | ||
821 | 0x3c02ffff, 0x34427fff, 0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c, | ||
822 | 0x8f440104, 0x3042bfff, 0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6, | ||
823 | 0xaf4301ac, 0x3c021000, 0xaf4201b8, 0x03e00008, 0x00001021, 0x30c21000, | ||
824 | 0x1040000f, 0x00000000, 0x9742010c, 0x3042fc00, 0x5440000b, 0x24070005, | ||
825 | 0x3c021000, 0x00c21024, 0x10400007, 0x3c030dff, 0x3463ffff, 0x3c020e00, | ||
826 | 0x00c21024, 0x0062182b, 0x54600001, 0x24070005, 0x8f82000c, 0x30434000, | ||
827 | 0x10600016, 0x00404821, 0x3c020f00, 0x00c21024, 0x14400012, 0x00000000, | ||
828 | 0x93420116, 0x34424000, 0x03421821, 0x94650002, 0x2ca21389, 0x1040000b, | ||
829 | 0x3c020800, 0x24422100, 0x00051942, 0x00031880, 0x00621821, 0x30a5001f, | ||
830 | 0x8c640000, 0x24020001, 0x00a21004, 0x00822024, 0x01044025, 0x11000037, | ||
831 | 0x3c021000, 0x9742010e, 0x34e60002, 0x3c038000, 0x24420004, 0x3045ffff, | ||
832 | 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020003, 0xa342018b, 0x8f840004, | ||
833 | 0x24020180, 0x24030002, 0xaf420180, 0xa743018c, 0x10800005, 0xa745018e, | ||
834 | 0x9743011c, 0x9742011e, 0x0a0000cd, 0x00021400, 0x9743011e, 0x9742011c, | ||
835 | 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c, 0x30828000, 0x1040000c, | ||
836 | 0xa7460188, 0x93420116, 0x304200fc, 0x005a1021, 0x24424004, 0x8c430000, | ||
837 | 0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff, 0x00821024, 0xaf82000c, | ||
838 | 0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff, 0x00031c00, 0x3084ffff, | ||
839 | 0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000, 0xaf4201b8, 0x03e00008, | ||
840 | 0x00001021, 0x00c21024, 0x104000ba, 0x3c020800, 0x8c430030, 0x1060003e, | ||
841 | 0x31224000, 0x1040003c, 0x3c030f00, 0x00c31824, 0x3c020100, 0x0043102b, | ||
842 | 0x14400038, 0x3c030800, 0x9742010e, 0x34e60002, 0x3c038000, 0x24420004, | ||
843 | 0x3045ffff, 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020003, 0xa342018b, | ||
844 | 0x8f840004, 0x24020080, 0x24030002, 0xaf420180, 0xa743018c, 0x10800005, | ||
845 | 0xa745018e, 0x9743011c, 0x9742011e, 0x0a000110, 0x00021400, 0x9743011e, | ||
846 | 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c, 0x30828000, | ||
847 | 0x1040000c, 0xa7460188, 0x93420116, 0x304200fc, 0x005a1021, 0x24424004, | ||
848 | 0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff, 0x00821024, | ||
849 | 0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff, 0x00031c00, | ||
850 | 0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000, 0xaf4201b8, | ||
851 | 0x03e00008, 0x00001021, 0x3c030800, 0x8c620024, 0x30420008, 0x1040003d, | ||
852 | 0x34e80002, 0x3c020f00, 0x00c21024, 0x5440003a, 0x3107ffff, 0x9742010c, | ||
853 | 0x30420200, 0x50400036, 0x3107ffff, 0x9742010e, 0x30e6fffb, 0x3c038000, | ||
854 | 0x24420004, 0x3045ffff, 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020003, | ||
855 | 0xa342018b, 0x8f840004, 0x24020180, 0x24030002, 0xaf420180, 0xa743018c, | ||
856 | 0x10800005, 0xa745018e, 0x9743011c, 0x9742011e, 0x0a000153, 0x00021400, | ||
857 | 0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c, | ||
858 | 0x30828000, 0x1040000c, 0xa7460188, 0x93420116, 0x304200fc, 0x005a1021, | ||
859 | 0x24424004, 0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff, | ||
860 | 0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff, | ||
861 | 0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000, | ||
862 | 0xaf4201b8, 0x3107ffff, 0x8f820000, 0x3c068000, 0x9743010e, 0x00021442, | ||
863 | 0x30440780, 0x24630004, 0x3065ffff, 0x8f4201b8, 0x00461024, 0x1440fffd, | ||
864 | 0x24020003, 0xa342018b, 0x8f830004, 0x24020002, 0xaf440180, 0xa742018c, | ||
865 | 0x10600005, 0xa745018e, 0x9743011c, 0x9742011e, 0x0a000189, 0x00021400, | ||
866 | 0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c, | ||
867 | 0x30828000, 0x1040000c, 0xa7470188, 0x93420116, 0x304200fc, 0x005a1021, | ||
868 | 0x24424004, 0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff, | ||
869 | 0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff, | ||
870 | 0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000, | ||
871 | 0xaf4201b8, 0x03e00008, 0x00001021, 0x8f424000, 0x30420100, 0x104000ef, | ||
872 | 0x3c020800, 0x8c440024, 0x24030001, 0x14830036, 0x00404021, 0x9742010e, | ||
873 | 0x34e50002, 0x3c038000, 0x24420004, 0x3044ffff, 0x8f4201b8, 0x00431024, | ||
874 | 0x1440fffd, 0x24020003, 0xa342018b, 0x8f830004, 0x24020002, 0xaf400180, | ||
875 | 0xa742018c, 0x10600005, 0xa744018e, 0x9743011c, 0x9742011e, 0x0a0001c6, | ||
876 | 0x00021400, 0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, | ||
877 | 0x8f84000c, 0x30828000, 0x1040000c, 0xa7450188, 0x93420116, 0x304200fc, | ||
878 | 0x005a1021, 0x24424004, 0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff, | ||
879 | 0x34427fff, 0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104, | ||
880 | 0x3042bfff, 0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac, | ||
881 | 0x3c021000, 0xaf4201b8, 0x03e00008, 0x00001021, 0x30820001, 0x10400035, | ||
882 | 0x30e90004, 0x9742010e, 0x30e6fffb, 0x3c038000, 0x24420004, 0x3044ffff, | ||
883 | 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020003, 0xa342018b, 0x8f830004, | ||
884 | 0x24020002, 0xaf400180, 0xa742018c, 0x10600005, 0xa744018e, 0x9743011c, | ||
885 | 0x9742011e, 0x0a0001fe, 0x00021400, 0x9743011e, 0x9742011c, 0x00021400, | ||
886 | 0x00621825, 0xaf4301a8, 0x8f84000c, 0x30828000, 0x1040000c, 0xa7470188, | ||
887 | 0x93420116, 0x304200fc, 0x005a1021, 0x24424004, 0x8c430000, 0x3063ffff, | ||
888 | 0x14600004, 0x3c02ffff, 0x34427fff, 0x00821024, 0xaf82000c, 0x9782000e, | ||
889 | 0x9743010c, 0x8f440104, 0x3042bfff, 0x00031c00, 0x3084ffff, 0x00641825, | ||
890 | 0xa74201a6, 0xaf4301ac, 0x3c021000, 0xaf4201b8, 0x30c7ffff, 0x8d020024, | ||
891 | 0x30420004, 0x10400037, 0x8d020024, 0x9742010e, 0x30e6fffb, 0x3c038000, | ||
892 | 0x24420004, 0x3045ffff, 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020003, | ||
893 | 0xa342018b, 0x8f840004, 0x24020100, 0x24030002, 0xaf420180, 0xa743018c, | ||
894 | 0x10800005, 0xa745018e, 0x9743011c, 0x9742011e, 0x0a000237, 0x00021400, | ||
895 | 0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c, | ||
896 | 0x30828000, 0x1040000c, 0xa7470188, 0x93420116, 0x304200fc, 0x005a1021, | ||
897 | 0x24424004, 0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff, | ||
898 | 0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff, | ||
899 | 0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000, | ||
900 | 0xaf4201b8, 0x30c7ffff, 0x8d020024, 0x30420008, 0x10400034, 0x00000000, | ||
901 | 0x9742010e, 0x3c038000, 0x24420004, 0x3045ffff, 0x8f4201b8, 0x00431024, | ||
902 | 0x1440fffd, 0x24020003, 0xa342018b, 0x8f840004, 0x24020180, 0x24030002, | ||
903 | 0xaf420180, 0xa743018c, 0x10800005, 0xa745018e, 0x9743011c, 0x9742011e, | ||
904 | 0x0a00026f, 0x00021400, 0x9743011e, 0x9742011c, 0x00021400, 0x00621825, | ||
905 | 0xaf4301a8, 0x8f84000c, 0x30828000, 0x1040000c, 0xa7470188, 0x93420116, | ||
906 | 0x304200fc, 0x005a1021, 0x24424004, 0x8c430000, 0x3063ffff, 0x14600004, | ||
907 | 0x3c02ffff, 0x34427fff, 0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c, | ||
908 | 0x8f440104, 0x3042bfff, 0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6, | ||
909 | 0xaf4301ac, 0x3c021000, 0xaf4201b8, 0x15200046, 0x00001021, 0x3c038000, | ||
910 | 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020002, 0x24032000, 0xa342018b, | ||
911 | 0xa7430188, 0x3c021000, 0xaf4201b8, 0x03e00008, 0x00001021, 0x3c030800, | ||
912 | 0x8c620024, 0x30420001, 0x10400035, 0x00001021, 0x9742010e, 0x34e50002, | ||
913 | 0x3c038000, 0x24420004, 0x3044ffff, 0x8f4201b8, 0x00431024, 0x1440fffd, | ||
914 | 0x24020003, 0xa342018b, 0x8f830004, 0x24020002, 0xaf400180, 0xa742018c, | ||
915 | 0x10600005, 0xa744018e, 0x9743011c, 0x9742011e, 0x0a0002b5, 0x00021400, | ||
916 | 0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c, | ||
917 | 0x30828000, 0x1040000c, 0xa7450188, 0x93420116, 0x304200fc, 0x005a1021, | ||
918 | 0x24424004, 0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff, | ||
919 | 0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff, | ||
920 | 0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000, | ||
921 | 0xaf4201b8, 0x00001021, 0x03e00008, 0x00000000, 0x27bdffe0, 0xafbf0018, | ||
922 | 0xafb10014, 0xafb00010, 0x8f420140, 0xaf420020, 0x8f430148, 0x3c027000, | ||
923 | 0x00621824, 0x3c024000, 0x1062000c, 0x0043102b, 0x14400006, 0x3c025000, | ||
924 | 0x3c023000, 0x1062000b, 0x3c024000, 0x0a00031f, 0x00000000, 0x10620034, | ||
925 | 0x3c024000, 0x0a00031f, 0x00000000, 0x0e00067c, 0x00000000, 0x0a00031f, | ||
926 | 0x3c024000, 0x8f420148, 0x24030002, 0x3044ffff, 0x00021402, 0x305000ff, | ||
927 | 0x1203000c, 0x27510180, 0x2a020003, 0x10400005, 0x24020003, 0x0600001d, | ||
928 | 0x36053000, 0x0a00030a, 0x3c038000, 0x12020007, 0x00000000, 0x0a000317, | ||
929 | 0x00000000, 0x0e000423, 0x00000000, 0x0a000308, 0x00402021, 0x0e000435, | ||
930 | 0x00000000, 0x00402021, 0x36053000, 0x3c038000, 0x8f4201b8, 0x00431024, | ||
931 | 0x1440fffd, 0x24020002, 0xa6250008, 0xa222000b, 0xa6240010, 0x8f420144, | ||
932 | 0x3c031000, 0xae220024, 0xaf4301b8, 0x0a00031f, 0x3c024000, 0x0000000d, | ||
933 | 0x00000000, 0x240001c3, 0x0a00031f, 0x3c024000, 0x0e0007f7, 0x00000000, | ||
934 | 0x3c024000, 0xaf420178, 0x00000000, 0x8fbf0018, 0x8fb10014, 0x8fb00010, | ||
935 | 0x03e00008, 0x27bd0020, 0x24020800, 0x03e00008, 0xaf4201b8, 0x27bdffe8, | ||
936 | 0x3c04600c, 0xafbf0014, 0xafb00010, 0x8c825000, 0x3c1a8000, 0x2403ff7f, | ||
937 | 0x3c106000, 0x00431024, 0x3442380c, 0x24030003, 0xac825000, 0x3c040008, | ||
938 | 0xaf430008, 0x8e020808, 0x3c030800, 0xac600020, 0x3042fff0, 0x2c420001, | ||
939 | 0xaf820004, 0x0e000819, 0x0344d825, 0x0e000781, 0x00000000, 0x3c020400, | ||
940 | 0x3442000c, 0x3c03ffff, 0x34630806, 0xae021948, 0xae03194c, 0x8e021980, | ||
941 | 0x34420200, 0xae021980, 0x8f500000, 0x32020003, 0x1040fffd, 0x32020001, | ||
942 | 0x10400004, 0x32020002, 0x0e0003bd, 0x00000000, 0x32020002, 0x1040fff6, | ||
943 | 0x00000000, 0x0e0002d4, 0x00000000, 0x0a00034a, 0x00000000, 0x27bdffe8, | ||
944 | 0x3c04600c, 0xafbf0014, 0xafb00010, 0x8c825000, 0x3c1a8000, 0x2403ff7f, | ||
945 | 0x3c106000, 0x00431024, 0x3442380c, 0x24030003, 0xac825000, 0x3c040008, | ||
946 | 0xaf430008, 0x8e020808, 0x3c030800, 0xac600020, 0x3042fff0, 0x2c420001, | ||
947 | 0xaf820004, 0x0e000819, 0x0344d825, 0x0e000781, 0x00000000, 0x3c020400, | ||
948 | 0x3442000c, 0x3c03ffff, 0x34630806, 0xae021948, 0xae03194c, 0x8e021980, | ||
949 | 0x8fbf0014, 0x34420200, 0xae021980, 0x8fb00010, 0x03e00008, 0x27bd0018, | ||
950 | 0x30a5ffff, 0x30c6ffff, 0x30e7ffff, 0x3c038000, 0x8f4201b8, 0x00431024, | ||
951 | 0x1440fffd, 0x24020003, 0xa342018b, 0x8f830004, 0xaf440180, 0xa745018c, | ||
952 | 0x10600005, 0xa746018e, 0x9743011c, 0x9742011e, 0x0a000393, 0x00021400, | ||
953 | 0x9743011e, 0x9742011c, 0x00021400, 0x00621825, 0xaf4301a8, 0x8f84000c, | ||
954 | 0x30828000, 0x1040000c, 0xa7470188, 0x93420116, 0x304200fc, 0x005a1021, | ||
955 | 0x24424004, 0x8c430000, 0x3063ffff, 0x14600004, 0x3c02ffff, 0x34427fff, | ||
956 | 0x00821024, 0xaf82000c, 0x9782000e, 0x9743010c, 0x8f440104, 0x3042bfff, | ||
957 | 0x00031c00, 0x3084ffff, 0x00641825, 0xa74201a6, 0xaf4301ac, 0x3c021000, | ||
958 | 0xaf4201b8, 0x03e00008, 0x00000000, 0x3c038000, 0x8f4201b8, 0x00431024, | ||
959 | 0x1440fffd, 0x24020002, 0x24032000, 0xa342018b, 0xa7430188, 0x3c021000, | ||
960 | 0xaf4201b8, 0x03e00008, 0x00000000, 0x27bdffe8, 0xafbf0010, 0x8f460128, | ||
961 | 0xaf460020, 0x8f420104, 0x8f450100, 0x24030800, 0x3c040010, 0xaf820000, | ||
962 | 0x00441024, 0xaf85000c, 0xaf4301b8, 0x14400005, 0x3c02001f, 0x3c030800, | ||
963 | 0x8c620020, 0x0a0003d5, 0x00002021, 0x3442ff00, 0x14c20009, 0x2402bfff, | ||
964 | 0x3c030800, 0x8c620020, 0x24040001, 0x24420001, 0x0e00004c, 0xac620020, | ||
965 | 0x0a0003e4, 0x00000000, 0x00a21024, 0x14400006, 0x00000000, 0xaf400048, | ||
966 | 0x0e000448, 0xaf400040, 0x0a0003e4, 0x00000000, 0x0e000783, 0x00000000, | ||
967 | 0x10400005, 0x3c024000, 0x8f430124, 0x3c026020, 0xac430014, 0x3c024000, | ||
968 | 0xaf420138, 0x00000000, 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x27bdffe0, | ||
969 | 0xafbf0018, 0xafb10014, 0xafb00010, 0x8f420148, 0x24030002, 0x3044ffff, | ||
970 | 0x00021402, 0x305000ff, 0x1203000c, 0x27510180, 0x2a020003, 0x10400005, | ||
971 | 0x24020003, 0x0600001d, 0x36053000, 0x0a00040e, 0x3c038000, 0x12020007, | ||
972 | 0x00000000, 0x0a00041b, 0x00000000, 0x0e000423, 0x00000000, 0x0a00040c, | ||
973 | 0x00402021, 0x0e000435, 0x00000000, 0x00402021, 0x36053000, 0x3c038000, | ||
974 | 0x8f4201b8, 0x00431024, 0x1440fffd, 0x24020002, 0xa6250008, 0xa222000b, | ||
975 | 0xa6240010, 0x8f420144, 0x3c031000, 0xae220024, 0xaf4301b8, 0x0a00041f, | ||
976 | 0x8fbf0018, 0x0000000d, 0x00000000, 0x240001c3, 0x8fbf0018, 0x8fb10014, | ||
977 | 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3084ffff, 0x2c821389, 0x1040000d, | ||
978 | 0x00001021, 0x3c030800, 0x24632100, 0x00042942, 0x00052880, 0x00a32821, | ||
979 | 0x3086001f, 0x8ca40000, 0x24030001, 0x00c31804, 0x00832025, 0x03e00008, | ||
980 | 0xaca40000, 0x03e00008, 0x24020091, 0x3084ffff, 0x2c821389, 0x1040000e, | ||
981 | 0x00001021, 0x3c030800, 0x24632100, 0x00042942, 0x00052880, 0x00a32821, | ||
982 | 0x3086001f, 0x24030001, 0x8ca40000, 0x00c31804, 0x00031827, 0x00832024, | ||
983 | 0x03e00008, 0xaca40000, 0x03e00008, 0x24020091, 0x27bdffb0, 0x3c026000, | ||
984 | 0xafbf0048, 0x8c434448, 0xaf630140, 0x93620005, 0x30420001, 0x14400005, | ||
985 | 0x00000000, 0x0e0007ed, 0x00000000, 0x0a00067a, 0x8fbf0048, 0x93420116, | ||
986 | 0x93430112, 0x8f430104, 0x3c040020, 0x34424000, 0x00641824, 0x1060000d, | ||
987 | 0x03426021, 0x8f430128, 0x27420180, 0xac430000, 0x8f650040, 0x24040008, | ||
988 | 0x240340c1, 0xa4430008, 0x24030002, 0xa043000b, 0x3c031000, 0x0a000563, | ||
989 | 0xa044000a, 0x8f420104, 0x3c030040, 0x00431024, 0x10400007, 0x00000000, | ||
990 | 0x8f430128, 0x27420180, 0xac430000, 0x8f650040, 0x0a00055c, 0x24040010, | ||
991 | 0xaf400048, 0xaf400054, 0xaf400040, 0x8f630048, 0x8f620040, 0x00624823, | ||
992 | 0x05210004, 0x00000000, 0x0000000d, 0x00000000, 0x24000132, 0x9742011a, | ||
993 | 0x3046ffff, 0x10c00004, 0x8d880004, 0x01061021, 0x0a000487, 0x2445ffff, | ||
994 | 0x01002821, 0x918a000d, 0xa7a00020, 0xafa00028, 0x9364003f, 0x3c026000, | ||
995 | 0x8c434448, 0x308700ff, 0x31420004, 0x10400033, 0xaf630144, 0x24090012, | ||
996 | 0x14e90006, 0x3c040800, 0x8c830028, 0x24020001, 0x24630001, 0x0a00054e, | ||
997 | 0xac830028, 0x8f620044, 0x15020012, 0x97a20020, 0x27a60010, 0x27450180, | ||
998 | 0x3442001a, 0xa7a20020, 0x8f630040, 0x3c048000, 0x24020020, 0xa3a70022, | ||
999 | 0xa3a90023, 0xa3a2001a, 0xafa30028, 0x8f4201b8, 0x00441024, 0x1440fffd, | ||
1000 | 0x00000000, 0x0a000533, 0x00000000, 0x8f620044, 0x01021023, 0x0440009e, | ||
1001 | 0x24020001, 0x8f620048, 0x01021023, 0x0441009a, 0x24020001, 0x97a20020, | ||
1002 | 0x27a60010, 0x34420001, 0xa7a20020, 0x8f630040, 0x27450180, 0x3c048000, | ||
1003 | 0xafa30028, 0x8f4201b8, 0x00441024, 0x1440fffd, 0x00000000, 0x0a000533, | ||
1004 | 0x00000000, 0x3c026000, 0x8c424448, 0xaf620148, 0x8f630040, 0x00685823, | ||
1005 | 0x19600013, 0x00cb102a, 0x54400007, 0x314a00fe, 0x5566000c, 0x010b4021, | ||
1006 | 0x31420001, 0x54400009, 0x010b4021, 0x314a00fe, 0x24020001, 0xa7a20020, | ||
1007 | 0x8f630040, 0x00c05821, 0x00003021, 0x0a0004dd, 0xafa30028, 0x00cb1023, | ||
1008 | 0x0a0004dd, 0x3046ffff, 0x00005821, 0x8f620048, 0x2442ffff, 0x00a21823, | ||
1009 | 0x18600019, 0x0066102a, 0x14400013, 0x24020001, 0xa7a20020, 0x8f630040, | ||
1010 | 0xafa30028, 0x8f620040, 0x55020005, 0x27a60010, 0x55200003, 0x27a60010, | ||
1011 | 0x0a0004f6, 0x00c01821, 0x27450180, 0x3c038000, 0x8f4201b8, 0x00431024, | ||
1012 | 0x1440fffd, 0x00000000, 0x0a000533, 0x00000000, 0x8f650048, 0x00c31023, | ||
1013 | 0x3046ffff, 0x314a00f6, 0x3c046000, 0x8c824448, 0x31430002, 0x1060001e, | ||
1014 | 0xaf62014c, 0x8f620044, 0x1502000e, 0x97a20020, 0x27a60010, 0x34420200, | ||
1015 | 0xa7a20020, 0x8f630040, 0x27450180, 0x3c048000, 0xafa30028, 0x8f4201b8, | ||
1016 | 0x00441024, 0x1440fffd, 0x00000000, 0x0a000533, 0x00000000, 0x27a60010, | ||
1017 | 0x34420001, 0xa7a20020, 0x8f630040, 0x27450180, 0x3c048000, 0xafa30028, | ||
1018 | 0x8f4201b8, 0x00441024, 0x1440fffd, 0x00000000, 0x0a000533, 0x00000000, | ||
1019 | 0x3c026000, 0x8c424448, 0x31430010, 0xaf620150, 0x54600003, 0x8d890008, | ||
1020 | 0x0a00054e, 0x24020001, 0x8f630054, 0x2522ffff, 0x00431023, 0x1840002a, | ||
1021 | 0x24020001, 0x27a60010, 0xa7a20020, 0x8f630040, 0x27450180, 0x3c048000, | ||
1022 | 0xafa30028, 0x8f4201b8, 0x00441024, 0x1440fffd, 0x00000000, 0x8f420128, | ||
1023 | 0xaca20000, 0x8cc30018, 0x240240c1, 0xa4a20008, 0xaca30018, 0x90c4000a, | ||
1024 | 0x24020002, 0xa0a2000b, 0xa0a4000a, 0x94c20010, 0xa4a20010, 0x90c30012, | ||
1025 | 0xa0a30012, 0x90c20013, 0xa0a20013, 0x8cc30014, 0xaca30014, 0x8cc20024, | ||
1026 | 0xaca20024, 0x8cc30028, 0xaca30028, 0x8cc4002c, 0x24020001, 0x3c031000, | ||
1027 | 0xaca4002c, 0xaf4301b8, 0xaf400044, 0xaf400050, 0x0a00067a, 0x8fbf0048, | ||
1028 | 0x3c026000, 0x8c424448, 0x31430020, 0x10600019, 0xaf620154, 0x8f430128, | ||
1029 | 0x27420180, 0xac430000, 0x8f650040, 0x24040004, 0x240340c1, 0xa4430008, | ||
1030 | 0x24030002, 0xa044000a, 0x24040008, 0xa043000b, 0x3c031000, 0xa4440010, | ||
1031 | 0xa0400012, 0xa0400013, 0xac400014, 0xac400024, 0xac400028, 0xac40002c, | ||
1032 | 0xac450018, 0x0e0007ed, 0xaf4301b8, 0x0a00067a, 0x8fbf0048, 0x8f430104, | ||
1033 | 0x8c824448, 0x38e3000a, 0x2c630001, 0xaf620158, 0x38e2000c, 0x2c420001, | ||
1034 | 0x00621825, 0x14600003, 0x2402000e, 0x14e2002a, 0x00000000, 0x50c00008, | ||
1035 | 0x9584000e, 0x10c00004, 0xa7a60040, 0x01061021, 0x0a000583, 0x2445ffff, | ||
1036 | 0x01002821, 0x9584000e, 0x93630035, 0x8f62004c, 0x00642004, 0x00892021, | ||
1037 | 0x00821023, 0x1840001f, 0x3c026000, 0x8f620018, 0x01021023, 0x1c40000f, | ||
1038 | 0x97a20020, 0x8f620018, 0x15020018, 0x3c026000, 0x8f62001c, 0x01221023, | ||
1039 | 0x1c400008, 0x97a20020, 0x8f62001c, 0x15220011, 0x3c026000, 0x8f620058, | ||
1040 | 0x00821023, 0x1840000c, 0x97a20020, 0xafa50028, 0xafa80034, 0xafa90038, | ||
1041 | 0xafa4003c, 0x34420020, 0x0a0005a8, 0xa7a20020, 0x8f680040, 0x00003021, | ||
1042 | 0x8f640058, 0x01002821, 0x3c026000, 0x8c434448, 0xaf63015c, 0x8f62004c, | ||
1043 | 0x01221023, 0x18400009, 0x00000000, 0x8f620054, 0x01221023, 0x1c400005, | ||
1044 | 0x97a20020, 0xafa50028, 0xafa90024, 0x0a0005c3, 0x34420040, 0x9742011a, | ||
1045 | 0x1440000c, 0x24020014, 0x8f620058, 0x14820009, 0x24020014, 0x8f63004c, | ||
1046 | 0x8f620054, 0x10620004, 0x97a20020, 0xafa50028, 0x34420080, 0xa7a20020, | ||
1047 | 0x24020014, 0x10e2000a, 0x28e20015, 0x10400005, 0x2402000c, 0x10e20006, | ||
1048 | 0x3c026000, 0x0a000600, 0x00000000, 0x24020016, 0x14e20031, 0x3c026000, | ||
1049 | 0x8f620054, 0x24420001, 0x1522002d, 0x3c026000, 0x24020014, 0x10e2001e, | ||
1050 | 0x28e20015, 0x10400005, 0x2402000c, 0x10e20008, 0x3c026000, 0x0a000600, | ||
1051 | 0x00000000, 0x24020016, 0x10e2000c, 0x97a20020, 0x0a000600, 0x3c026000, | ||
1052 | 0x97a30020, 0x2402000e, 0xafa50028, 0xa3a70022, 0xa3a20023, 0xafa90024, | ||
1053 | 0x34630054, 0x0a0005ff, 0xa7a30020, 0x24030010, 0x24040002, 0xafa50028, | ||
1054 | 0xa3a70022, 0xa3a30023, 0xa3a4001a, 0xafa90024, 0x0a0005fe, 0x3442005d, | ||
1055 | 0x97a20020, 0x24030012, 0x24040002, 0xafa50028, 0xa3a70022, 0xa3a30023, | ||
1056 | 0xa3a4001a, 0xafa90024, 0x3042fffe, 0x3442005c, 0xa7a20020, 0x3c026000, | ||
1057 | 0x8c434448, 0x31420001, 0xaf630160, 0x1040002c, 0x2402000c, 0x10e20014, | ||
1058 | 0x28e2000d, 0x10400005, 0x2402000a, 0x10e20008, 0x97a20020, 0x0a000631, | ||
1059 | 0x3c026000, 0x2402000e, 0x10e20018, 0x3c026000, 0x0a000631, 0x00000000, | ||
1060 | 0x24030008, 0x24040002, 0xafa50028, 0xa3a70022, 0xa3a30023, 0xa3a4001a, | ||
1061 | 0x0a00062f, 0x34420013, 0x97a30020, 0x30620004, 0x1440000b, 0x97a20020, | ||
1062 | 0x3462001b, 0xa7a20020, 0x24020016, 0x24030002, 0xafa50028, 0xa3a70022, | ||
1063 | 0xa3a20023, 0x0a000630, 0xa3a3001a, 0x97a20020, 0x24030010, 0x24040002, | ||
1064 | 0xafa50028, 0xa3a70022, 0xa3a30023, 0xa3a4001a, 0x3442001b, 0xa7a20020, | ||
1065 | 0x3c026000, 0x8c434448, 0x31420009, 0x0002102b, 0x00021023, 0x30420007, | ||
1066 | 0x34440003, 0xaf630164, 0x10c00016, 0x24030800, 0x8f820010, 0x27450180, | ||
1067 | 0x24420001, 0xaf820010, 0x24020004, 0xaf4301b8, 0xa4a40008, 0xa0a2000b, | ||
1068 | 0x93440120, 0x3c031000, 0xa4a6000e, 0xaca90024, 0xaca80028, 0x008b2021, | ||
1069 | 0xa4a4000c, 0xaf4301b8, 0x97a20020, 0x00003021, 0x3042ffbf, 0x0a000650, | ||
1070 | 0xa7a20020, 0x24060001, 0x3c026000, 0x8c434448, 0xaf630168, 0x97a20020, | ||
1071 | 0x10400020, 0x27450180, 0x3c038000, 0x8f4201b8, 0x00431024, 0x1440fffd, | ||
1072 | 0x00000000, 0x8f420128, 0xaca20000, 0x8fa30028, 0x240240c1, 0xa4a20008, | ||
1073 | 0xaca30018, 0x93a4001a, 0x24020002, 0xa0a2000b, 0xa0a4000a, 0x97a20020, | ||
1074 | 0xa4a20010, 0x93a30022, 0xa0a30012, 0x93a20023, 0xa0a20013, 0x8fa30024, | ||
1075 | 0xaca30014, 0x8fa20034, 0xaca20024, 0x8fa30038, 0xaca30028, 0x8fa2003c, | ||
1076 | 0x3c031000, 0xaca2002c, 0xaf4301b8, 0x3c026000, 0x8c434448, 0x00c01021, | ||
1077 | 0xaf63016c, 0x8fbf0048, 0x03e00008, 0x27bd0050, 0x8f460140, 0x8f470148, | ||
1078 | 0x3c028000, 0x00e24024, 0x00072c02, 0x30a300ff, 0x2402000b, 0x1062008f, | ||
1079 | 0x27440180, 0x2862000c, 0x10400011, 0x24020006, 0x1062005a, 0x28620007, | ||
1080 | 0x10400007, 0x24020008, 0x10600024, 0x24020001, 0x10620037, 0x00000000, | ||
1081 | 0x0a00077e, 0x00000000, 0x106200a9, 0x24020009, 0x106200bb, 0x00071c02, | ||
1082 | 0x0a00077e, 0x00000000, 0x2402001b, 0x106200c7, 0x2862001c, 0x10400007, | ||
1083 | 0x2402000e, 0x106200b1, 0x24020019, 0x106200c2, 0x00071c02, 0x0a00077e, | ||
1084 | 0x00000000, 0x24020080, 0x10620060, 0x28620081, 0x10400005, 0x2402001c, | ||
1085 | 0x10620094, 0x00071c02, 0x0a00077e, 0x00000000, 0x240200c2, 0x106200c5, | ||
1086 | 0x00a01821, 0x0a00077e, 0x00000000, 0x00a01821, 0x3c058000, 0x8f4201b8, | ||
1087 | 0x00451024, 0x1440fffd, 0x24020001, 0xa4830008, 0x24030002, 0xac860000, | ||
1088 | 0xac800004, 0xa082000a, 0xa083000b, 0xa4870010, 0x8f430144, 0x3c021000, | ||
1089 | 0xac800028, 0xac830024, 0x3c036000, 0xaf4201b8, 0x03e00008, 0xac600808, | ||
1090 | 0x11000009, 0x00a01821, 0x3c020800, 0x24030002, 0xa0434490, 0x24424490, | ||
1091 | 0xac460008, 0x8f430144, 0x03e00008, 0xac430004, 0x3c058000, 0x8f4201b8, | ||
1092 | 0x00451024, 0x1440fffd, 0x24020002, 0xac800000, 0xac860004, 0xa4830008, | ||
1093 | 0xa082000a, 0xa082000b, 0xa4870010, 0xac800024, 0x8f420144, 0x3c031000, | ||
1094 | 0xac820028, 0x3c026000, 0xaf4301b8, 0x03e00008, 0xac400808, 0x00a01821, | ||
1095 | 0x3c080800, 0x3c058000, 0x8f4201b8, 0x00451024, 0x1440fffd, 0x00000000, | ||
1096 | 0xac860000, 0x91024490, 0x00002821, 0x10400002, 0x25064490, 0x8cc50008, | ||
1097 | 0xac850004, 0xa4830008, 0x91034490, 0x24020002, 0xa082000b, 0xa4870010, | ||
1098 | 0x34630001, 0xa083000a, 0x8f420144, 0xac820024, 0x91034490, 0x10600002, | ||
1099 | 0x00001021, 0x8cc20004, 0xac820028, 0x3c021000, 0xaf4201b8, 0x3c026000, | ||
1100 | 0xa1004490, 0x03e00008, 0xac400808, 0x00a01821, 0x3c058000, 0x8f4201b8, | ||
1101 | 0x00451024, 0x1440fffd, 0x24020002, 0xa082000b, 0xa4830008, 0xa4870010, | ||
1102 | 0x8f420144, 0x3c031000, 0xa4820012, 0x03e00008, 0xaf4301b8, 0x30e2ffff, | ||
1103 | 0x14400028, 0x00071c02, 0x93620005, 0x30420004, 0x14400020, 0x3c029000, | ||
1104 | 0x34420001, 0x00c21025, 0xaf420020, 0x3c038000, 0x8f420020, 0x00431024, | ||
1105 | 0x1440fffd, 0x00000000, 0x93620005, 0x3c038000, 0x34630001, 0x00c31825, | ||
1106 | 0x34420004, 0xa3620005, 0xaf430020, 0x93620005, 0x30420004, 0x14400003, | ||
1107 | 0x3c038000, 0x0000000d, 0x3c038000, 0x8f4201b8, 0x00431024, 0x1440fffd, | ||
1108 | 0x24020005, 0x3c031000, 0xac860000, 0xa082000b, 0xaf4301b8, 0x0a00073d, | ||
1109 | 0x00071c02, 0x0000000d, 0x03e00008, 0x00000000, 0x00071c02, 0x3c058000, | ||
1110 | 0x8f4201b8, 0x00451024, 0x1440fffd, 0x24020001, 0xa4830008, 0x24030002, | ||
1111 | 0xac860000, 0xac800004, 0xa082000a, 0xa083000b, 0xa4870010, 0x8f430144, | ||
1112 | 0x3c021000, 0xac800028, 0xac830024, 0x03e00008, 0xaf4201b8, 0x00071c02, | ||
1113 | 0x3c058000, 0x8f4201b8, 0x00451024, 0x1440fffd, 0x24020002, 0xac800000, | ||
1114 | 0xac860004, 0xa4830008, 0xa082000a, 0xa082000b, 0xa4870010, 0xac800024, | ||
1115 | 0x8f420144, 0x3c031000, 0xac820028, 0x03e00008, 0xaf4301b8, 0x00071c02, | ||
1116 | 0x3c058000, 0x8f4201b8, 0x00451024, 0x1440fffd, 0x24020001, 0xa4830008, | ||
1117 | 0x24030002, 0xa082000a, 0x3c021000, 0xac860000, 0xac800004, 0xa083000b, | ||
1118 | 0xa4870010, 0xac800024, 0xac800028, 0x03e00008, 0xaf4201b8, 0x3c058000, | ||
1119 | 0x8f4201b8, 0x00451024, 0x1440fffd, 0x24020002, 0xac860000, 0xac800004, | ||
1120 | 0xa4830008, 0xa080000a, 0x0a000748, 0xa082000b, 0x0000000d, 0x03e00008, | ||
1121 | 0x00000000, 0x03e00008, 0x00000000, 0x8f420100, 0x3042003e, 0x14400011, | ||
1122 | 0x24020001, 0xaf400048, 0x8f420100, 0x304207c0, 0x10400005, 0x00000000, | ||
1123 | 0xaf40004c, 0xaf400050, 0x03e00008, 0x24020001, 0xaf400054, 0xaf400040, | ||
1124 | 0x8f420100, 0x30423800, 0x54400001, 0xaf400044, 0x24020001, 0x03e00008, | ||
1125 | 0x00000000, 0x3c029000, 0x34420001, 0x00822025, 0xaf440020, 0x3c038000, | ||
1126 | 0x8f420020, 0x00431024, 0x1440fffd, 0x00000000, 0x03e00008, 0x00000000, | ||
1127 | 0x3c028000, 0x34420001, 0x00822025, 0x03e00008, 0xaf440020, 0x8f430128, | ||
1128 | 0x27420180, 0xac430000, 0x8f650040, 0x240340c1, 0xa4430008, 0x24030002, | ||
1129 | 0xa044000a, 0x24040008, 0xa043000b, 0x3c031000, 0xa4440010, 0xa0400012, | ||
1130 | 0xa0400013, 0xac400014, 0xac400024, 0xac400028, 0xac40002c, 0xac450018, | ||
1131 | 0x03e00008, 0xaf4301b8, 0x24020001, 0xacc40000, 0x03e00008, 0xa4e50000, | ||
1132 | 0x03e00008, 0x24020001, 0x24020001, 0xaf400044, 0x03e00008, 0xaf400050, | ||
1133 | 0x00803021, 0x27450180, 0x3c038000, 0x8f4201b8, 0x00431024, 0x1440fffd, | ||
1134 | 0x00000000, 0x8f420128, 0xaca20000, 0x8cc30018, 0x240240c1, 0xa4a20008, | ||
1135 | 0xaca30018, 0x90c4000a, 0x24020002, 0xa0a2000b, 0xa0a4000a, 0x94c20010, | ||
1136 | 0xa4a20010, 0x90c30012, 0xa0a30012, 0x90c20013, 0xa0a20013, 0x8cc30014, | ||
1137 | 0xaca30014, 0x8cc20024, 0xaca20024, 0x8cc30028, 0xaca30028, 0x8cc2002c, | ||
1138 | 0x3c031000, 0xaca2002c, 0x24020001, 0xaf4301b8, 0xaf400044, 0x03e00008, | ||
1139 | 0xaf400050, 0x27bdffe8, 0xafbf0010, 0x0e000326, 0x00000000, 0x00002021, | ||
1140 | 0x0e00004c, 0xaf400180, 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x8f460148, | ||
1141 | 0x27450180, 0x3c038000, 0x00061402, 0x304700ff, 0x8f4201b8, 0x00431024, | ||
1142 | 0x1440fffd, 0x00000000, 0x8f440140, 0x00061202, 0x304200ff, 0x00061c02, | ||
1143 | 0xaca20004, 0x24020002, 0xa4a30008, 0x30c300ff, 0xa0a2000b, 0xaca30024, | ||
1144 | 0x10e0000a, 0xaca40000, 0x28e20004, 0x14400005, 0x24020001, 0x24020005, | ||
1145 | 0x54e20005, 0xa0a0000a, 0x24020001, 0x0a000816, 0xa0a2000a, 0xa0a0000a, | ||
1146 | 0x3c021000, 0x03e00008, 0xaf4201b8, 0x03e00008, 0x00001021, 0x10c00007, | ||
1147 | 0x00000000, 0x8ca20000, 0x24c6ffff, 0x24a50004, 0xac820000, 0x14c0fffb, | ||
1148 | 0x24840004, 0x03e00008, 0x00000000, 0x0a00082a, 0x00a01021, 0xac860000, | ||
1149 | 0x24840004, 0x00a01021, 0x1440fffc, 0x24a5ffff, 0x03e00008, 0x00000000, | ||
1150 | 0x00000000 }; | ||
1151 | |||
1152 | static u32 bnx2_RXP_b06FwData[(0x0/4) + 1] = { 0x00000000 }; | ||
1153 | static u32 bnx2_RXP_b06FwRodata[(0x0/4) + 1] = { 0x00000000 }; | ||
1154 | static u32 bnx2_RXP_b06FwBss[(0x239c/4) + 1] = { 0x00000000 }; | ||
1155 | static u32 bnx2_RXP_b06FwSbss[(0x14/4) + 1] = { 0x00000000 }; | ||
1156 | |||
1157 | static u32 bnx2_rv2p_proc1[] = { | ||
1158 | 0x00000008, 0xac000001, 0x0000000c, 0x2f800001, 0x00000010, 0x213f0004, | ||
1159 | 0x00000010, 0x20bf002c, 0x00000010, 0x203f0143, 0x00000018, 0x8000fffd, | ||
1160 | 0x00000010, 0xb1b8b017, 0x0000000b, 0x2fdf0002, 0x00000000, 0x03d80000, | ||
1161 | 0x00000000, 0x2c380000, 0x00000008, 0x2c800000, 0x00000008, 0x2d000000, | ||
1162 | 0x00000010, 0x91d40000, 0x00000008, 0x2d800108, 0x00000008, 0x02000002, | ||
1163 | 0x00000010, 0x91de0000, 0x0000000f, 0x42e0001c, 0x00000010, 0x91840a08, | ||
1164 | 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008, 0x00000008, 0x2d800150, | ||
1165 | 0x00000000, 0x00000000, 0x00000010, 0x91de0000, 0x00000010, 0x2c620002, | ||
1166 | 0x00000018, 0x80000012, 0x0000000b, 0x2fdf0002, 0x0000000c, 0x1f800002, | ||
1167 | 0x00000000, 0x2c070000, 0x00000018, 0x8000ffe6, 0x00000008, 0x02000002, | ||
1168 | 0x0000000f, 0x42e0001c, 0x00000010, 0x91840a08, 0x00000008, 0x2c8000b0, | ||
1169 | 0x00000008, 0x2d000008, 0x00000010, 0x91d40000, 0x00000008, 0x2d800108, | ||
1170 | 0x00000000, 0x00000000, 0x00000010, 0x91de0000, 0x00000018, 0x80000004, | ||
1171 | 0x0000000c, 0x1f800002, 0x00000000, 0x00000000, 0x00000018, 0x8000ffd9, | ||
1172 | 0x0000000c, 0x29800002, 0x0000000c, 0x1f800002, 0x00000000, 0x2adf0000, | ||
1173 | 0x00000008, 0x2a000005, 0x00000018, 0x8000ffd4, 0x00000008, 0x02240030, | ||
1174 | 0x00000018, 0x00040000, 0x00000018, 0x80000015, 0x00000018, 0x80000017, | ||
1175 | 0x00000018, 0x8000001b, 0x00000018, 0x8000004c, 0x00000018, 0x8000008c, | ||
1176 | 0x00000018, 0x8000000f, 0x00000018, 0x8000000e, 0x00000018, 0x8000000d, | ||
1177 | 0x00000018, 0x8000000c, 0x00000018, 0x800000c2, 0x00000018, 0x8000000a, | ||
1178 | 0x00000018, 0x80000009, 0x00000018, 0x80000008, 0x00000018, 0x800000fd, | ||
1179 | 0x00000018, 0x80000006, 0x00000018, 0x80000005, 0x00000018, 0x800000ff, | ||
1180 | 0x00000018, 0x80000104, 0x00000018, 0x80000002, 0x00000018, 0x80000098, | ||
1181 | 0x00000018, 0x80000000, 0x0000000c, 0x1f800001, 0x00000000, 0x00000000, | ||
1182 | 0x00000018, 0x8000ffba, 0x00000010, 0x91d40000, 0x0000000c, 0x29800001, | ||
1183 | 0x0000000c, 0x1f800001, 0x00000008, 0x2a000002, 0x00000018, 0x8000ffb5, | ||
1184 | 0x00000010, 0xb1a0b012, 0x0000000b, 0x2fdf0002, 0x00000000, 0x2c200000, | ||
1185 | 0x00000008, 0x2c800000, 0x00000008, 0x2d000000, 0x00000010, 0x91d40000, | ||
1186 | 0x00000008, 0x2d80011c, 0x00000000, 0x00000000, 0x00000010, 0x91de0000, | ||
1187 | 0x0000000f, 0x47600008, 0x0000000f, 0x060e0001, 0x00000010, 0x001f0000, | ||
1188 | 0x00000000, 0x0f580000, 0x00000000, 0x0a640000, 0x00000000, 0x0ae50000, | ||
1189 | 0x00000000, 0x0b660000, 0x00000000, 0x0d610000, 0x00000018, 0x80000013, | ||
1190 | 0x0000000f, 0x47600008, 0x0000000b, 0x2fdf0002, 0x00000008, 0x2c800000, | ||
1191 | 0x00000008, 0x2d000000, 0x00000010, 0x91d40000, 0x00000008, 0x2d80011c, | ||
1192 | 0x0000000f, 0x060e0001, 0x00000010, 0x001f0000, 0x00000000, 0x0f580000, | ||
1193 | 0x00000010, 0x91de0000, 0x00000000, 0x0a640000, 0x00000000, 0x0ae50000, | ||
1194 | 0x00000000, 0x0b660000, 0x00000000, 0x0d610000, 0x00000000, 0x02620000, | ||
1195 | 0x0000000b, 0x2fdf0002, 0x00000000, 0x309a0000, 0x00000000, 0x31040000, | ||
1196 | 0x00000000, 0x0c961800, 0x00000009, 0x0c99ffff, 0x00000004, 0xcc993400, | ||
1197 | 0x00000010, 0xb1963202, 0x00000008, 0x0f800000, 0x0000000c, 0x29800001, | ||
1198 | 0x00000010, 0x00220002, 0x0000000c, 0x29520001, 0x0000000c, 0x29520000, | ||
1199 | 0x00000008, 0x22000001, 0x0000000c, 0x1f800001, 0x00000000, 0x2adf0000, | ||
1200 | 0x00000008, 0x2a000003, 0x00000018, 0x8000ff83, 0x00000010, 0xb1a0b01d, | ||
1201 | 0x0000000b, 0x2fdf0002, 0x00000000, 0x2c200000, 0x00000008, 0x2c8000b0, | ||
1202 | 0x00000008, 0x2d000008, 0x00000010, 0x91d40000, 0x00000008, 0x2d800150, | ||
1203 | 0x00000000, 0x00000000, 0x00000010, 0x205f0000, 0x00000008, 0x2c800000, | ||
1204 | 0x00000008, 0x2d000000, 0x00000008, 0x2d800108, 0x00000000, 0x00000000, | ||
1205 | 0x00000010, 0x91de0000, 0x0000000f, 0x47600008, 0x00000000, 0x060e0000, | ||
1206 | 0x00000010, 0x001f0000, 0x00000000, 0x0f580000, 0x00000010, 0x91de0000, | ||
1207 | 0x00000000, 0x0a640000, 0x00000000, 0x0ae50000, 0x00000000, 0x0b670000, | ||
1208 | 0x00000000, 0x0d620000, 0x00000000, 0x0ce71800, 0x00000009, 0x0c99ffff, | ||
1209 | 0x00000004, 0xcc993400, 0x00000010, 0xb1963220, 0x00000008, 0x0f800000, | ||
1210 | 0x00000018, 0x8000001e, 0x0000000f, 0x47600008, 0x0000000b, 0x2fdf0002, | ||
1211 | 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008, 0x00000010, 0x91d40000, | ||
1212 | 0x00000008, 0x2d80012c, 0x0000000f, 0x060e0001, 0x00000010, 0x001f0000, | ||
1213 | 0x00000000, 0x0f580000, 0x00000010, 0x91de0000, 0x00000000, 0x0a640000, | ||
1214 | 0x00000000, 0x0ae50000, 0x00000000, 0x0b670000, 0x00000000, 0x0d620000, | ||
1215 | 0x00000000, 0x02630000, 0x0000000f, 0x47620010, 0x00000000, 0x0ce71800, | ||
1216 | 0x0000000b, 0x2fdf0002, 0x00000000, 0x311a0000, 0x00000000, 0x31840000, | ||
1217 | 0x0000000b, 0xc20000ff, 0x00000002, 0x42040000, 0x00000001, 0x31620800, | ||
1218 | 0x0000000f, 0x020e0010, 0x00000002, 0x31620800, 0x00000009, 0x0c99ffff, | ||
1219 | 0x00000004, 0xcc993400, 0x00000010, 0xb1963202, 0x00000008, 0x0f800000, | ||
1220 | 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, 0x0000000c, 0x61420006, | ||
1221 | 0x00000008, 0x22000008, 0x00000000, 0x2adf0000, 0x00000008, 0x2a000004, | ||
1222 | 0x00000018, 0x8000ff42, 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008, | ||
1223 | 0x00000010, 0x91a0b008, 0x00000010, 0x91d40000, 0x0000000c, 0x31620018, | ||
1224 | 0x00000008, 0x2d800001, 0x00000000, 0x00000000, 0x00000010, 0x91de0000, | ||
1225 | 0x00000008, 0xac000001, 0x00000018, 0x8000000e, 0x00000000, 0x0380b000, | ||
1226 | 0x0000000b, 0x2fdf0002, 0x00000000, 0x2c004000, 0x00000010, 0x91d40000, | ||
1227 | 0x00000008, 0x2d800101, 0x00000000, 0x00000000, 0x00000010, 0x91de0000, | ||
1228 | 0x0000000c, 0x31620018, 0x00000008, 0x2d800001, 0x00000000, 0x00000000, | ||
1229 | 0x00000010, 0x91de0000, 0x0000000b, 0x2fdf0002, 0x00000000, 0x2c000e00, | ||
1230 | 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, 0x00000008, 0x2a000007, | ||
1231 | 0x00000018, 0x8000ff27, 0x00000010, 0xb1a0b016, 0x0000000b, 0x2fdf0002, | ||
1232 | 0x00000000, 0x03d80000, 0x00000000, 0x2c200000, 0x00000008, 0x2c8000b0, | ||
1233 | 0x00000008, 0x2d000008, 0x00000010, 0x91d40000, 0x00000008, 0x2d800150, | ||
1234 | 0x00000000, 0x00000000, 0x00000010, 0x205f0000, 0x00000008, 0x2c800000, | ||
1235 | 0x00000008, 0x2d000000, 0x00000008, 0x2d800108, 0x00000008, 0x07000001, | ||
1236 | 0x00000010, 0xb5de1c00, 0x00000010, 0x2c620002, 0x00000018, 0x8000000a, | ||
1237 | 0x0000000b, 0x2fdf0002, 0x00000000, 0x2c070000, 0x0000000c, 0x1f800001, | ||
1238 | 0x00000010, 0x91de0000, 0x00000018, 0x8000ff11, 0x00000008, 0x2c8000b0, | ||
1239 | 0x00000008, 0x2d000008, 0x00000010, 0x91d40000, 0x00000008, 0x2d800108, | ||
1240 | 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, 0x00000010, 0x91de0000, | ||
1241 | 0x00000000, 0x2adf0000, 0x00000008, 0x2a00000a, 0x00000018, 0x8000ff07, | ||
1242 | 0x00000000, 0x82265600, 0x0000000f, 0x47220008, 0x00000009, 0x070e000f, | ||
1243 | 0x00000008, 0x070e0008, 0x00000008, 0x02800001, 0x00000007, 0x02851c00, | ||
1244 | 0x00000008, 0x82850001, 0x00000000, 0x02840a00, 0x00000007, 0x42851c00, | ||
1245 | 0x00000003, 0xc3aa5200, 0x00000000, 0x03b10e00, 0x00000010, 0x001f0000, | ||
1246 | 0x0000000f, 0x0f280007, 0x00000007, 0x4b071c00, 0x00000000, 0x00000000, | ||
1247 | 0x0000000f, 0x0a960003, 0x00000000, 0x0a955c00, 0x00000000, 0x4a005a00, | ||
1248 | 0x00000000, 0x0c960a00, 0x00000009, 0x0c99ffff, 0x00000008, 0x0d00ffff, | ||
1249 | 0x00000010, 0xb1963202, 0x00000008, 0x0f800005, 0x00000010, 0x00220020, | ||
1250 | 0x00000000, 0x02a70000, 0x00000010, 0xb1850002, 0x00000008, 0x82850200, | ||
1251 | 0x00000000, 0x02000000, 0x00000000, 0x03a60000, 0x00000018, 0x8000004e, | ||
1252 | 0x00000000, 0x072b0000, 0x00000001, 0x878c1c00, 0x00000000, 0x870e1e00, | ||
1253 | 0x00000000, 0x860c1e00, 0x00000000, 0x03061e00, 0x00000010, 0xb18e0003, | ||
1254 | 0x00000018, 0x80000047, 0x00000018, 0x8000fffa, 0x00000010, 0x918c0003, | ||
1255 | 0x00000010, 0xb1870002, 0x00000018, 0x80000043, 0x00000010, 0x91d40000, | ||
1256 | 0x0000000c, 0x29800001, 0x00000000, 0x2a860000, 0x00000000, 0x230c0000, | ||
1257 | 0x00000000, 0x2b070000, 0x00000010, 0xb187000e, 0x00000008, 0x2a000008, | ||
1258 | 0x00000018, 0x8000003b, 0x00000010, 0x91d40000, 0x00000000, 0x28d18c00, | ||
1259 | 0x00000000, 0x2a860000, 0x00000000, 0x230c0000, 0x00000000, 0x2b070000, | ||
1260 | 0x00000018, 0x8000fff8, 0x00000010, 0x91d40000, 0x0000000c, 0x29800001, | ||
1261 | 0x00000000, 0x2aab0000, 0x00000000, 0xa3265600, 0x00000000, 0x2b000000, | ||
1262 | 0x0000000c, 0x1f800001, 0x00000008, 0x2a000008, 0x00000018, 0x8000fec8, | ||
1263 | 0x00000010, 0x91d40000, 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, | ||
1264 | 0x00000008, 0x2a000009, 0x00000018, 0x8000fec3, 0x00000010, 0x91d40000, | ||
1265 | 0x0000000c, 0x29800001, 0x0000000c, 0x1f800001, 0x00000000, 0x29420000, | ||
1266 | 0x00000008, 0x2a000002, 0x00000018, 0x8000febd, 0x00000018, 0x8000febc, | ||
1267 | 0x00000010, 0xb1bcb016, 0x0000000b, 0x2fdf0002, 0x00000000, 0x03d80000, | ||
1268 | 0x00000000, 0x2c3c0000, 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008, | ||
1269 | 0x00000010, 0x91d40000, 0x00000008, 0x2d800150, 0x00000000, 0x00000000, | ||
1270 | 0x00000010, 0x205f0000, 0x00000008, 0x2c800000, 0x00000008, 0x2d000000, | ||
1271 | 0x00000008, 0x2d800108, 0x00000008, 0x07000001, 0x00000010, 0xb5de1c00, | ||
1272 | 0x00000010, 0x2c620002, 0x00000018, 0x8000000a, 0x0000000b, 0x2fdf0002, | ||
1273 | 0x00000000, 0x2c070000, 0x0000000c, 0x1f800000, 0x00000010, 0x91de0000, | ||
1274 | 0x00000018, 0x8000fea6, 0x00000008, 0x2c8000b0, 0x00000008, 0x2d000008, | ||
1275 | 0x00000010, 0x91d40000, 0x00000008, 0x2d800108, 0x0000000c, 0x29800000, | ||
1276 | 0x0000000c, 0x1f800000, 0x00000010, 0x91de0000, 0x00000000, 0x2adf0000, | ||
1277 | 0x00000008, 0x2a000006, 0x00000018, 0x8000fe9c, 0x00000008, 0x03050004, | ||
1278 | 0x00000006, 0x83040c00, 0x00000008, 0x02850200, 0x00000000, 0x86050c00, | ||
1279 | 0x00000001, 0x860c0e00, 0x00000008, 0x02040004, 0x00000000, 0x02041800, | ||
1280 | 0x00000000, 0x83871800, 0x00000018, 0x00020000 }; | ||
1281 | |||
1282 | static u32 bnx2_rv2p_proc2[] = { | ||
1283 | 0x00000000, 0x2a000000, 0x00000010, 0xb1d40000, 0x00000008, 0x02540003, | ||
1284 | 0x00000018, 0x00040000, 0x00000018, 0x8000000a, 0x00000018, 0x8000000a, | ||
1285 | 0x00000018, 0x8000000e, 0x00000018, 0x80000056, 0x00000018, 0x800001b9, | ||
1286 | 0x00000018, 0x800001e1, 0x00000018, 0x8000019b, 0x00000018, 0x800001f9, | ||
1287 | 0x00000018, 0x8000019f, 0x00000018, 0x800001a6, 0x00000018, 0x80000000, | ||
1288 | 0x0000000c, 0x29800001, 0x00000000, 0x2a000000, 0x0000000c, 0x29800000, | ||
1289 | 0x00000010, 0x20530000, 0x00000018, 0x8000ffee, 0x0000000c, 0x29800001, | ||
1290 | 0x00000010, 0x91de0000, 0x00000010, 0x001f0000, 0x00000000, 0x2f80aa00, | ||
1291 | 0x00000000, 0x2a000000, 0x00000000, 0x0d610000, 0x00000000, 0x03620000, | ||
1292 | 0x00000000, 0x2c400000, 0x00000000, 0x02638c00, 0x00000000, 0x26460000, | ||
1293 | 0x00000010, 0x00420002, 0x00000008, 0x02040012, 0x00000010, 0xb9060836, | ||
1294 | 0x00000000, 0x0f580000, 0x00000000, 0x0a640000, 0x00000000, 0x0ae50000, | ||
1295 | 0x00000000, 0x0b660000, 0x00000000, 0x0c000000, 0x00000000, 0x0b800000, | ||
1296 | 0x00000010, 0x00420009, 0x00000008, 0x0cc60012, 0x00000008, 0x0f800003, | ||
1297 | 0x00000000, 0x00000000, 0x00000010, 0x009f0000, 0x00000008, 0x27110012, | ||
1298 | 0x00000000, 0x66900000, 0x00000008, 0xa31b0012, 0x00000018, 0x80000008, | ||
1299 | 0x00000000, 0x0cc60000, 0x00000008, 0x0f800003, 0x00000000, 0x00000000, | ||
1300 | 0x00000010, 0x009f0000, 0x00000000, 0x27110000, 0x00000000, 0x66900000, | ||
1301 | 0x00000000, 0x231b0000, 0x00000010, 0xb197320e, 0x00000000, 0x25960000, | ||
1302 | 0x00000000, 0x021b0000, 0x00000010, 0x001f0000, 0x00000008, 0x0f800003, | ||
1303 | 0x0000000c, 0x29800000, 0x00000010, 0x20530000, 0x00000000, 0x22c50800, | ||
1304 | 0x00000010, 0x009f0000, 0x00000000, 0x27002200, 0x00000000, 0x26802000, | ||
1305 | 0x00000000, 0x231b0000, 0x0000000c, 0x69520001, 0x00000018, 0x8000fff3, | ||
1306 | 0x00000010, 0x01130002, 0x00000010, 0xb1980003, 0x00000010, 0x001f0000, | ||
1307 | 0x00000008, 0x0f800004, 0x00000008, 0x22000003, 0x00000008, 0x2c80000c, | ||
1308 | 0x00000008, 0x2d00000c, 0x00000010, 0x009f0000, 0x00000000, 0x25960000, | ||
1309 | 0x0000000c, 0x29800000, 0x00000000, 0x32140000, 0x00000000, 0x32950000, | ||
1310 | 0x00000000, 0x33160000, 0x00000000, 0x31e32e00, 0x00000008, 0x2d800010, | ||
1311 | 0x00000010, 0x20530000, 0x00000018, 0x8000ffac, 0x00000000, 0x23000000, | ||
1312 | 0x00000000, 0x25e60000, 0x00000008, 0x2200000b, 0x0000000c, 0x69520000, | ||
1313 | 0x0000000c, 0x29800000, 0x00000010, 0x20530000, 0x00000018, 0x8000ffa5, | ||
1314 | 0x0000000c, 0x29800001, 0x00000010, 0x91de0000, 0x00000000, 0x2fd50000, | ||
1315 | 0x00000010, 0x001f0000, 0x00000000, 0x02700000, 0x00000000, 0x0d620000, | ||
1316 | 0x00000000, 0xbb630800, 0x00000000, 0x2a000000, 0x00000009, 0x076000ff, | ||
1317 | 0x0000000f, 0x2c0e0007, 0x00000008, 0x2c800000, 0x00000008, 0x2d000064, | ||
1318 | 0x00000008, 0x2d80011c, 0x00000009, 0x06420002, 0x0000000c, 0x61420001, | ||
1319 | 0x00000000, 0x0f400000, 0x00000000, 0x02d08c00, 0x00000000, 0x23000000, | ||
1320 | 0x00000004, 0x826da000, 0x00000000, 0x8304a000, 0x00000000, 0x22c50c00, | ||
1321 | 0x00000000, 0x03760000, 0x00000004, 0x83860a00, 0x00000000, 0x83870c00, | ||
1322 | 0x00000010, 0x91de0000, 0x00000000, 0x037c0000, 0x00000000, 0x837b0c00, | ||
1323 | 0x00000001, 0x83060e00, 0x00000000, 0x83870c00, 0x00000000, 0x82850e00, | ||
1324 | 0x00000010, 0xb1860016, 0x0000000f, 0x47610018, 0x00000000, 0x068e0000, | ||
1325 | 0x0000000f, 0x47670010, 0x0000000f, 0x47e20010, 0x00000000, 0x870e1e00, | ||
1326 | 0x00000010, 0xb70e1a10, 0x00000010, 0x0ce7000e, 0x00000008, 0x22000009, | ||
1327 | 0x00000000, 0x286d0000, 0x0000000f, 0x65680010, 0x00000003, 0xf66c9400, | ||
1328 | 0x00000010, 0xb972a003, 0x0000000c, 0x73e70019, 0x0000000c, 0x21420004, | ||
1329 | 0x00000018, 0x8000023f, 0x00000000, 0x37ed0000, 0x0000000c, 0x73e7001a, | ||
1330 | 0x00000010, 0x20530000, 0x00000008, 0x22000008, 0x0000000c, 0x61420004, | ||
1331 | 0x00000000, 0x02f60000, 0x00000004, 0x82840a00, 0x00000010, 0xb1840a2b, | ||
1332 | 0x00000010, 0x2d67000a, 0x00000010, 0xb96d0804, 0x00000004, 0xb6ed0a00, | ||
1333 | 0x00000000, 0x37ed0000, 0x00000018, 0x80000029, 0x0000000c, 0x61420000, | ||
1334 | 0x00000000, 0x37040000, 0x00000000, 0x37850000, 0x0000000c, 0x33e7001a, | ||
1335 | 0x00000018, 0x80000024, 0x00000010, 0xb96d0809, 0x00000004, 0xb6ed0a00, | ||
1336 | 0x00000000, 0x036d0000, 0x00000004, 0xb76e0c00, 0x00000010, 0x91ee0c1f, | ||
1337 | 0x0000000c, 0x73e7001a, 0x00000004, 0xb6ef0c00, 0x00000000, 0x37ed0000, | ||
1338 | 0x00000018, 0x8000001b, 0x0000000c, 0x61420000, 0x00000010, 0xb7ee0a05, | ||
1339 | 0x00000010, 0xb96f0815, 0x00000003, 0xb76e0800, 0x00000004, 0xb7ef0a00, | ||
1340 | 0x00000018, 0x80000015, 0x00000010, 0x0ce7000c, 0x00000008, 0x22000009, | ||
1341 | 0x00000000, 0x286d0000, 0x0000000f, 0x65680010, 0x00000003, 0xf66c9400, | ||
1342 | 0x00000010, 0xb972a003, 0x0000000c, 0x73e70019, 0x0000000c, 0x21420004, | ||
1343 | 0x00000018, 0x80000215, 0x00000010, 0x20530000, 0x00000008, 0x22000008, | ||
1344 | 0x0000000c, 0x61420004, 0x00000000, 0x37040000, 0x00000000, 0x37850000, | ||
1345 | 0x00000000, 0x036d0000, 0x00000003, 0xb8f10c00, 0x00000018, 0x80000004, | ||
1346 | 0x00000000, 0x02840000, 0x00000002, 0x21421800, 0x0000000c, 0x61420000, | ||
1347 | 0x00000000, 0x286d0000, 0x0000000f, 0x65ed0010, 0x00000009, 0x266dffff, | ||
1348 | 0x00000000, 0x23000000, 0x00000010, 0xb1840a3d, 0x00000010, 0x01420002, | ||
1349 | 0x00000004, 0xb8f10a00, 0x00000003, 0x83760a00, 0x00000010, 0xb8040c39, | ||
1350 | 0x00000010, 0xb7e6080a, 0x00000000, 0x0a640000, 0x00000000, 0x0ae50000, | ||
1351 | 0x00000009, 0x0c68ffff, 0x00000009, 0x0b67ffff, 0x00000000, 0x0be60000, | ||
1352 | 0x00000000, 0x0c840000, 0x00000010, 0xb197320c, 0x00000008, 0x0f800002, | ||
1353 | 0x00000018, 0x8000000a, 0x00000000, 0x0a6a0000, 0x00000000, 0x0aeb0000, | ||
1354 | 0x00000000, 0x0c000000, 0x00000009, 0x0b6cffff, 0x00000000, 0x0be90000, | ||
1355 | 0x00000000, 0x0c840000, 0x00000010, 0xb1973203, 0x00000008, 0x0f800002, | ||
1356 | 0x00000018, 0x80000001, 0x00000010, 0x001f0000, 0x00000000, 0x0c860000, | ||
1357 | 0x00000000, 0x06980000, 0x00000008, 0x0f800003, 0x00000000, 0x00000000, | ||
1358 | 0x00000010, 0x009f0000, 0x00000010, 0xb1973210, 0x00000000, 0x231b0000, | ||
1359 | 0x00000000, 0x02043600, 0x00000003, 0x8384a000, 0x0000000f, 0x65870010, | ||
1360 | 0x00000009, 0x2607ffff, 0x00000000, 0x27111a00, 0x00000000, 0x66900000, | ||
1361 | 0x0000000c, 0x29000000, 0x00000018, 0x800001de, 0x00000000, 0x06980000, | ||
1362 | 0x00000010, 0x20530000, 0x00000000, 0x22c58c00, 0x00000010, 0x001f0000, | ||
1363 | 0x00000008, 0x0f800003, 0x00000018, 0x8000fff0, 0x00000000, 0x02043600, | ||
1364 | 0x00000000, 0x231b0000, 0x00000003, 0x8384a000, 0x0000000f, 0x65870010, | ||
1365 | 0x00000009, 0x2607ffff, 0x00000000, 0x27111a00, 0x00000000, 0x66900000, | ||
1366 | 0x0000000c, 0x29000000, 0x00000010, 0x91840a02, 0x00000002, 0x21421800, | ||
1367 | 0x00000000, 0x32140000, 0x00000000, 0x32950000, 0x00000005, 0x73e72c00, | ||
1368 | 0x00000005, 0x74683000, 0x00000000, 0x33170000, 0x00000018, 0x80000138, | ||
1369 | 0x00000010, 0x91c60004, 0x00000008, 0x07000004, 0x00000010, 0xb1c41c02, | ||
1370 | 0x00000010, 0x91840a04, 0x00000018, 0x800001c3, 0x00000010, 0x20530000, | ||
1371 | 0x00000000, 0x22c58c00, 0x00000010, 0xb1840a8e, 0x0000000c, 0x21420006, | ||
1372 | 0x00000010, 0x0ce7001a, 0x0000000f, 0x43680010, 0x00000000, 0x03f30c00, | ||
1373 | 0x00000010, 0x91870850, 0x0000000f, 0x46ec0010, 0x00000010, 0xb68d0c4e, | ||
1374 | 0x00000000, 0x838d0c00, 0x00000000, 0xa3050800, 0x00000001, 0xa3460e00, | ||
1375 | 0x00000000, 0x02048c00, 0x00000010, 0x91840a02, 0x00000002, 0x21421800, | ||
1376 | 0x00000010, 0x001f0000, 0x00000008, 0x22000008, 0x00000003, 0x8384a000, | ||
1377 | 0x0000000f, 0x65870010, 0x00000009, 0x2607ffff, 0x00000000, 0x27750c00, | ||
1378 | 0x00000000, 0x66f40000, 0x0000000c, 0x29000000, 0x00000018, 0x800001aa, | ||
1379 | 0x00000000, 0x03068c00, 0x00000003, 0xf4680c00, 0x00000010, 0x20530000, | ||
1380 | 0x00000000, 0x22c58c00, 0x00000018, 0x8000ffe5, 0x00000000, 0x39760000, | ||
1381 | 0x00000000, 0x39840000, 0x0000000c, 0x33e70019, 0x00000010, 0x001f0000, | ||
1382 | 0x00000000, 0x031e0000, 0x00000000, 0x0760fe00, 0x0000000f, 0x0f0e0007, | ||
1383 | 0x00000000, 0x83850800, 0x00000000, 0x0a7d0000, 0x00000000, 0x0afe0000, | ||
1384 | 0x00000000, 0x0b7f0000, 0x00000000, 0x0d7a0000, 0x00000000, 0x0c000000, | ||
1385 | 0x00000000, 0x0bfc0000, 0x00000000, 0x0c970e00, 0x00000008, 0x0f800003, | ||
1386 | 0x0000000f, 0x47670010, 0x00000008, 0x070e0001, 0x0000000b, 0xc38000ff, | ||
1387 | 0x00000002, 0x43870000, 0x00000001, 0x33e70e00, 0x0000000f, 0x038e0010, | ||
1388 | 0x00000002, 0x33e70e00, 0x00000000, 0x28f30000, 0x00000010, 0x009f0000, | ||
1389 | 0x00000000, 0x02043600, 0x00000010, 0x91840a02, 0x00000002, 0x21421800, | ||
1390 | 0x00000008, 0x22000006, 0x00000000, 0x231b0000, 0x00000000, 0x23ff0000, | ||
1391 | 0x00000000, 0x241b0000, 0x00000003, 0x8384a000, 0x0000000f, 0x65870010, | ||
1392 | 0x00000009, 0x2607ffff, 0x00000000, 0x27110000, 0x00000000, 0x26900000, | ||
1393 | 0x0000000c, 0x29000000, 0x00000018, 0x8000017e, 0x00000003, 0xf4683600, | ||
1394 | 0x00000000, 0x3a100000, 0x00000000, 0x3a910000, 0x00000003, 0xf66c2400, | ||
1395 | 0x00000010, 0x001f0000, 0x00000010, 0xb1923604, 0x00000008, 0x0f800004, | ||
1396 | 0x00000000, 0x00000000, 0x00000010, 0x009f0000, 0x00000000, 0x3e170000, | ||
1397 | 0x00000000, 0x3e940000, 0x00000000, 0x3f150000, 0x00000000, 0x3f960000, | ||
1398 | 0x00000010, 0x001f0000, 0x00000000, 0x0f060000, 0x00000010, 0x20530000, | ||
1399 | 0x00000000, 0x22c53600, 0x00000018, 0x8000ffac, 0x00000010, 0x001f0000, | ||
1400 | 0x00000000, 0x031e0000, 0x00000000, 0x83850800, 0x00000009, 0x076000ff, | ||
1401 | 0x0000000f, 0x0f0e0007, 0x00000000, 0x0c000000, 0x00000000, 0x0a7d0000, | ||
1402 | 0x00000000, 0x0afe0000, 0x00000000, 0x0b7f0000, 0x00000000, 0x0d7a0000, | ||
1403 | 0x00000000, 0x0bfc0000, 0x00000000, 0x0c970e00, 0x00000008, 0x0f800003, | ||
1404 | 0x0000000f, 0x47670010, 0x00000008, 0x070e0001, 0x0000000b, 0xc38000ff, | ||
1405 | 0x00000002, 0x43870000, 0x00000001, 0x33e70e00, 0x0000000f, 0x038e0010, | ||
1406 | 0x00000002, 0x33e70e00, 0x00000000, 0x39840000, 0x00000003, 0xb9720800, | ||
1407 | 0x00000000, 0x28f30000, 0x0000000f, 0x65680010, 0x00000010, 0x009f0000, | ||
1408 | 0x00000000, 0x02043600, 0x00000010, 0x91840a02, 0x00000002, 0x21421800, | ||
1409 | 0x00000008, 0x22000007, 0x00000000, 0x231b0000, 0x00000000, 0x23ff0000, | ||
1410 | 0x00000000, 0x241b0000, 0x00000003, 0x8384a000, 0x0000000f, 0x65870010, | ||
1411 | 0x00000009, 0x2607ffff, 0x00000000, 0x27110000, 0x00000000, 0x26900000, | ||
1412 | 0x0000000c, 0x29000000, 0x00000018, 0x80000145, 0x00000003, 0xf4683600, | ||
1413 | 0x00000000, 0x3a100000, 0x00000000, 0x3a910000, 0x00000003, 0xf66c2400, | ||
1414 | 0x00000010, 0x001f0000, 0x00000010, 0xb1923604, 0x00000008, 0x0f800004, | ||
1415 | 0x00000000, 0x00000000, 0x00000010, 0x009f0000, 0x00000000, 0x3e170000, | ||
1416 | 0x00000000, 0x3e940000, 0x00000000, 0x3f150000, 0x00000000, 0x3f960000, | ||
1417 | 0x00000010, 0x001f0000, 0x00000000, 0x0f060000, 0x00000010, 0x20530000, | ||
1418 | 0x00000000, 0x22c53600, 0x00000018, 0x8000ff73, 0x00000010, 0x0ce70005, | ||
1419 | 0x00000008, 0x2c80000c, 0x00000008, 0x2d000070, 0x00000008, 0x2d800010, | ||
1420 | 0x00000000, 0x00000000, 0x00000010, 0x205f0000, 0x00000018, 0x8000011d, | ||
1421 | 0x00000000, 0x2c1e0000, 0x00000008, 0x2c8000b8, 0x00000008, 0x2d000010, | ||
1422 | 0x00000008, 0x2d800048, 0x00000000, 0x00000000, 0x00000010, 0x91de0000, | ||
1423 | 0x00000018, 0x8000fe5d, 0x0000000c, 0x29800001, 0x00000000, 0x2a000000, | ||
1424 | 0x00000010, 0x001f0000, 0x00000000, 0x0f008000, 0x00000008, 0x0f800007, | ||
1425 | 0x00000018, 0x80000006, 0x0000000c, 0x29800001, 0x00000000, 0x2a000000, | ||
1426 | 0x00000010, 0x001f0000, 0x0000000f, 0x0f470007, 0x00000008, 0x0f800008, | ||
1427 | 0x00000018, 0x80000119, 0x00000010, 0x20530000, 0x00000018, 0x8000fe4f, | ||
1428 | 0x0000000c, 0x29800001, 0x00000010, 0x91de0000, 0x00000000, 0x2fd50000, | ||
1429 | 0x00000000, 0x2a000000, 0x00000009, 0x0261ffff, 0x0000000d, 0x70e10001, | ||
1430 | 0x00000018, 0x80000101, 0x00000000, 0x2c400000, 0x00000008, 0x2c8000c4, | ||
1431 | 0x00000008, 0x2d00001c, 0x00000008, 0x2d800001, 0x00000005, 0x70e10800, | ||
1432 | 0x00000010, 0x91de0000, 0x00000018, 0x8000fe41, 0x0000000c, 0x29800001, | ||
1433 | 0x00000010, 0x91de0000, 0x00000000, 0x2fd50000, 0x00000010, 0x001f0000, | ||
1434 | 0x00000000, 0x02700000, 0x00000000, 0x0d620000, 0x00000000, 0xbb630800, | ||
1435 | 0x00000000, 0x2a000000, 0x00000000, 0x0f400000, 0x00000000, 0x2c400000, | ||
1436 | 0x0000000c, 0x73e7001b, 0x00000010, 0x0ce7000e, 0x00000000, 0x286d0000, | ||
1437 | 0x0000000f, 0x65ed0010, 0x00000009, 0x266dffff, 0x00000018, 0x80000069, | ||
1438 | 0x00000008, 0x02000004, 0x00000010, 0x91c40803, 0x00000018, 0x800000f6, | ||
1439 | 0x00000010, 0x20530000, 0x00000018, 0x800000e5, 0x00000008, 0x2c8000b8, | ||
1440 | 0x00000008, 0x2d000010, 0x00000008, 0x2d800048, 0x00000018, 0x80000005, | ||
1441 | 0x00000008, 0x2c8000c4, 0x00000008, 0x2d00001c, 0x00000008, 0x2d800001, | ||
1442 | 0x00000000, 0x00000000, 0x00000010, 0x205f0000, 0x00000008, 0x2c800048, | ||
1443 | 0x00000008, 0x2d000068, 0x00000008, 0x2d800104, 0x00000000, 0x00000000, | ||
1444 | 0x00000010, 0x91de0000, 0x00000000, 0x27f60000, 0x00000010, 0xb87a9e04, | ||
1445 | 0x00000008, 0x2200000d, 0x00000018, 0x800000e2, 0x00000010, 0x20530000, | ||
1446 | 0x00000018, 0x8000fe18, 0x0000000c, 0x29800001, 0x00000010, 0x91de0000, | ||
1447 | 0x00000000, 0x2fd50000, 0x00000010, 0x001f0000, 0x00000000, 0x02700000, | ||
1448 | 0x00000000, 0x0d620000, 0x00000000, 0xbb630800, 0x00000000, 0x2a000000, | ||
1449 | 0x00000010, 0x0e670011, 0x00000000, 0x286d0000, 0x0000000f, 0x65ed0010, | ||
1450 | 0x00000009, 0x266dffff, 0x00000004, 0xb8f1a000, 0x00000000, 0x0f400000, | ||
1451 | 0x0000000c, 0x73e7001c, 0x00000018, 0x80000040, 0x00000008, 0x02000004, | ||
1452 | 0x00000010, 0x91c40802, 0x00000018, 0x800000cd, 0x00000000, 0x2c1e0000, | ||
1453 | 0x00000008, 0x2c8000b8, 0x00000008, 0x2d000010, 0x00000008, 0x2d800048, | ||
1454 | 0x00000010, 0x20530000, 0x00000010, 0x91de0000, 0x00000018, 0x8000fdfe, | ||
1455 | 0x0000000c, 0x29800001, 0x00000000, 0x03550000, 0x00000000, 0x06460000, | ||
1456 | 0x00000000, 0x03d60000, 0x00000000, 0x2a000000, 0x0000000f, 0x0f480007, | ||
1457 | 0x00000010, 0xb18c0027, 0x0000000f, 0x47420008, 0x00000009, 0x070e000f, | ||
1458 | 0x00000008, 0x070e0008, 0x00000010, 0x001f0000, 0x00000008, 0x09000001, | ||
1459 | 0x00000007, 0x09121c00, 0x00000003, 0xcbca9200, 0x00000000, 0x0b97a200, | ||
1460 | 0x00000007, 0x4b171c00, 0x0000000f, 0x0a960003, 0x00000000, 0x0a959c00, | ||
1461 | 0x00000000, 0x4a009a00, 0x00000008, 0x82120001, 0x00000001, 0x0c170800, | ||
1462 | 0x00000000, 0x02180000, 0x00000000, 0x0c971800, 0x00000008, 0x0d00ffff, | ||
1463 | 0x00000008, 0x0f800006, 0x0000000c, 0x29000000, 0x00000008, 0x22000001, | ||
1464 | 0x00000000, 0x22c50c00, 0x00000010, 0x009f0000, 0x00000010, 0xb197320b, | ||
1465 | 0x00000000, 0x231b0000, 0x00000000, 0x27110800, 0x00000000, 0x66900000, | ||
1466 | 0x00000018, 0x800000a4, 0x00000000, 0x02180000, 0x00000010, 0x20530000, | ||
1467 | 0x00000000, 0x22c53600, 0x00000010, 0x001f0000, 0x00000008, 0x0f800006, | ||
1468 | 0x00000018, 0x8000fff5, 0x00000010, 0x91870002, 0x00000008, 0x2200000a, | ||
1469 | 0x00000000, 0x231b0000, 0x00000000, 0x27110800, 0x00000000, 0x66900000, | ||
1470 | 0x00000018, 0x80000098, 0x00000008, 0x0200000a, 0x00000010, 0x91c40804, | ||
1471 | 0x00000010, 0x02c20003, 0x00000010, 0x001f0000, 0x00000008, 0x0f800008, | ||
1472 | 0x00000010, 0x20530000, 0x00000018, 0x8000fdc9, 0x00000000, 0x06820000, | ||
1473 | 0x00000010, 0x001f0000, 0x00000010, 0x0ce70028, 0x00000000, 0x03720000, | ||
1474 | 0x00000000, 0xa8760c00, 0x00000000, 0x0cf60000, 0x00000010, 0xb8723224, | ||
1475 | 0x00000000, 0x03440000, 0x00000008, 0x22000010, 0x00000000, 0x03ca0000, | ||
1476 | 0x0000000f, 0x65680010, 0x00000000, 0x0bcf0000, 0x00000000, 0x27f20000, | ||
1477 | 0x00000010, 0xb7ef3203, 0x0000000c, 0x21420004, 0x0000000c, 0x73e70019, | ||
1478 | 0x00000000, 0x07520000, 0x00000000, 0x29000000, 0x00000018, 0x8000007e, | ||
1479 | 0x00000004, 0xb9723200, 0x00000010, 0x20530000, 0x00000000, 0x22060000, | ||
1480 | 0x0000000c, 0x61420004, 0x00000000, 0x25070000, 0x00000000, 0x27970000, | ||
1481 | 0x00000000, 0x290e0000, 0x00000010, 0x0ce70010, 0x00000010, 0xb873320f, | ||
1482 | 0x0000000f, 0x436c0010, 0x00000000, 0x03f30c00, 0x00000000, 0x03f30000, | ||
1483 | 0x00000000, 0x83990e00, 0x00000001, 0x83860e00, 0x00000000, 0x83060e00, | ||
1484 | 0x00000003, 0xf66c0c00, 0x00000000, 0x39f30e00, 0x00000000, 0x3af50e00, | ||
1485 | 0x00000000, 0x7a740000, 0x0000000f, 0x43680010, 0x00000001, 0x83860e00, | ||
1486 | 0x00000000, 0x83060e00, 0x00000003, 0xf4680c00, 0x00000000, 0x286d0000, | ||
1487 | 0x00000000, 0x03690000, 0x00000010, 0xb1f60c54, 0x00000000, 0x0a6a0000, | ||
1488 | 0x00000000, 0x0aeb0000, 0x00000009, 0x0b6cffff, 0x00000000, 0x0c000000, | ||
1489 | 0x00000000, 0x0be90000, 0x00000003, 0x8cf6a000, 0x0000000c, 0x09800002, | ||
1490 | 0x00000010, 0x009f0000, 0x00000010, 0xb8173209, 0x00000000, 0x35140000, | ||
1491 | 0x00000000, 0x35950000, 0x00000005, 0x766c2c00, 0x00000000, 0x34970000, | ||
1492 | 0x00000004, 0xb8f12e00, 0x00000010, 0x001f0000, 0x00000008, 0x0f800004, | ||
1493 | 0x00000018, 0x8000fff7, 0x00000000, 0x03e90000, 0x00000010, 0xb8f6a01a, | ||
1494 | 0x00000010, 0x20130019, 0x00000010, 0xb1f10e18, 0x00000000, 0x83973200, | ||
1495 | 0x00000000, 0x38700e00, 0x00000000, 0xbb760e00, 0x00000000, 0x37d00000, | ||
1496 | 0x0000000c, 0x73e7001a, 0x00000003, 0xb8f1a000, 0x00000000, 0x32140000, | ||
1497 | 0x00000000, 0x32950000, 0x00000005, 0x73e72c00, 0x00000000, 0x33190000, | ||
1498 | 0x00000005, 0x74680000, 0x00000010, 0x0ce7000d, 0x00000008, 0x22000009, | ||
1499 | 0x00000000, 0x07520000, 0x00000000, 0x29000000, 0x0000000c, 0x73e70019, | ||
1500 | 0x0000000f, 0x65680010, 0x0000000c, 0x21420004, 0x00000018, 0x8000003c, | ||
1501 | 0x00000010, 0x20530000, 0x0000000c, 0x61420004, 0x00000000, 0x290e0000, | ||
1502 | 0x00000018, 0x80000002, 0x00000010, 0x91973206, 0x00000000, 0x35140000, | ||
1503 | 0x00000000, 0x35950000, 0x00000005, 0x766c2c00, 0x00000000, 0x34990000, | ||
1504 | 0x00000004, 0xb8f13200, 0x00000000, 0x83690c00, 0x00000010, 0xb1860013, | ||
1505 | 0x00000000, 0x28e90000, 0x00000008, 0x22000004, 0x00000000, 0x23ec0000, | ||
1506 | 0x00000000, 0x03690000, 0x00000010, 0xb8660c07, 0x00000009, 0x036cffff, | ||
1507 | 0x00000000, 0x326a0000, 0x00000000, 0x32eb0000, 0x00000005, 0x73e70c00, | ||
1508 | 0x00000000, 0x33690000, 0x00000005, 0x74680000, 0x0000000c, 0x73e7001c, | ||
1509 | 0x00000000, 0x03690000, 0x00000010, 0xb1f60c12, 0x00000010, 0xb1d00c11, | ||
1510 | 0x0000000c, 0x21420005, 0x0000000c, 0x33e7001c, 0x00000018, 0x8000000e, | ||
1511 | 0x00000010, 0x2e67000d, 0x00000000, 0x03690000, 0x00000010, 0xb1f60c0b, | ||
1512 | 0x00000010, 0xb1d00c0a, 0x00000000, 0x03440000, 0x00000008, 0x2200000c, | ||
1513 | 0x00000000, 0x07520000, 0x00000000, 0x29000000, 0x00000018, 0x80000015, | ||
1514 | 0x0000000c, 0x33e7001c, 0x00000010, 0x20530000, 0x00000000, 0x22060000, | ||
1515 | 0x00000000, 0x290e0000, 0x00000018, 0x000d0000, 0x00000000, 0x06820000, | ||
1516 | 0x00000010, 0x2de7000d, 0x00000010, 0x0ce7000c, 0x00000000, 0x27f20000, | ||
1517 | 0x00000010, 0xb96d9e0a, 0x00000000, 0xa86d9e00, 0x00000009, 0x0361ffff, | ||
1518 | 0x00000010, 0xb7500c07, 0x00000008, 0x2200000f, 0x0000000f, 0x65680010, | ||
1519 | 0x00000000, 0x29000000, 0x00000018, 0x80000004, 0x0000000c, 0x33e7001b, | ||
1520 | 0x00000010, 0x20530000, 0x00000018, 0x000d0000, 0x00000000, 0x2b820000, | ||
1521 | 0x00000010, 0x20d2002f, 0x00000010, 0x0052002e, 0x00000009, 0x054e0007, | ||
1522 | 0x00000010, 0xb18a002c, 0x00000000, 0x050a8c00, 0x00000008, 0x850a0008, | ||
1523 | 0x00000010, 0x918a0029, 0x00000003, 0xc5008800, 0x00000008, 0xa3460001, | ||
1524 | 0x00000010, 0xb1c60007, 0x00000008, 0x22000001, 0x0000000c, 0x29800000, | ||
1525 | 0x00000010, 0x20530000, 0x00000000, 0x274e8c00, 0x00000000, 0x66cd0000, | ||
1526 | 0x00000000, 0x22c58c00, 0x00000008, 0x22000014, 0x00000003, 0x22c58e00, | ||
1527 | 0x00000003, 0x23c58e00, 0x00000003, 0x22c58e00, 0x00000003, 0x26cd9e00, | ||
1528 | 0x00000003, 0x27cd9e00, 0x00000003, 0x26cd9e00, 0x00000003, 0x274ea000, | ||
1529 | 0x00000003, 0x284ea000, 0x00000003, 0x274ea000, 0x0000000c, 0x69520000, | ||
1530 | 0x0000000c, 0x29800000, 0x00000010, 0x20530000, 0x00000003, 0x22c58e00, | ||
1531 | 0x00000003, 0x23c58e00, 0x00000003, 0x22c58e00, 0x00000003, 0x26cd9e00, | ||
1532 | 0x00000003, 0x27cd9e00, 0x00000003, 0x26cd9e00, 0x00000003, 0x274ea000, | ||
1533 | 0x00000003, 0x284ea000, 0x00000003, 0x274ea000, 0x00000000, 0xa2c58c00, | ||
1534 | 0x00000000, 0xa74e8c00, 0x00000000, 0xe6cd0000, 0x0000000f, 0x620a0010, | ||
1535 | 0x00000008, 0x23460001, 0x0000000c, 0x29800000, 0x00000010, 0x20530000, | ||
1536 | 0x0000000c, 0x29520000, 0x00000018, 0x80000002, 0x0000000c, 0x29800000, | ||
1537 | 0x00000018, 0x00570000 }; | ||
1538 | |||
1539 | static int bnx2_TPAT_b06FwReleaseMajor = 0x0; | ||
1540 | static int bnx2_TPAT_b06FwReleaseMinor = 0x0; | ||
1541 | static int bnx2_TPAT_b06FwReleaseFix = 0x0; | ||
1542 | static u32 bnx2_TPAT_b06FwStartAddr = 0x08000858; | ||
1543 | static u32 bnx2_TPAT_b06FwTextAddr = 0x08000800; | ||
1544 | static int bnx2_TPAT_b06FwTextLen = 0x1314; | ||
1545 | static u32 bnx2_TPAT_b06FwDataAddr = 0x08001b40; | ||
1546 | static int bnx2_TPAT_b06FwDataLen = 0x0; | ||
1547 | static u32 bnx2_TPAT_b06FwRodataAddr = 0x00000000; | ||
1548 | static int bnx2_TPAT_b06FwRodataLen = 0x0; | ||
1549 | static u32 bnx2_TPAT_b06FwBssAddr = 0x08001b90; | ||
1550 | static int bnx2_TPAT_b06FwBssLen = 0x80; | ||
1551 | static u32 bnx2_TPAT_b06FwSbssAddr = 0x08001b40; | ||
1552 | static int bnx2_TPAT_b06FwSbssLen = 0x48; | ||
1553 | |||
1554 | static u32 bnx2_TPAT_b06FwText[(0x1314/4) + 1] = { | ||
1555 | 0x0a000216, 0x00000000, 0x00000000, 0x0000000d, 0x74706174, 0x20302e36, | ||
1556 | 0x2e390000, 0x00060901, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1557 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1558 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x10000003, | ||
1559 | 0x00000000, 0x0000000d, 0x0000000d, 0x3c020800, 0x24421b40, 0x3c030800, | ||
1560 | 0x24631c10, 0xac400000, 0x0043202b, 0x1480fffd, 0x24420004, 0x3c1d0800, | ||
1561 | 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100858, 0x3c1c0800, 0x279c1b40, | ||
1562 | 0x0e00051f, 0x00000000, 0x0000000d, 0x8f820024, 0x27bdffe8, 0xafbf0014, | ||
1563 | 0x10400004, 0xafb00010, 0x0000000d, 0x00000000, 0x2400015f, 0x8f82001c, | ||
1564 | 0x8c450008, 0x24030800, 0xaf430178, 0x97430104, 0x3c020008, 0xaf420140, | ||
1565 | 0x8f820034, 0x30420001, 0x10400006, 0x3070ffff, 0x24020002, 0x2603fffe, | ||
1566 | 0xa7420146, 0x0a000246, 0xa7430148, 0xa7400146, 0x8f850034, 0x30a20020, | ||
1567 | 0x0002102b, 0x00021023, 0x30460009, 0x30a30c00, 0x24020400, 0x14620002, | ||
1568 | 0x34c40001, 0x34c40005, 0xa744014a, 0x3c020800, 0x8c440820, 0x3c030048, | ||
1569 | 0x24020002, 0x00832025, 0x30a30006, 0x1062000d, 0x2c620003, 0x50400005, | ||
1570 | 0x24020004, 0x10600012, 0x3c020001, 0x0a000271, 0x00000000, 0x10620007, | ||
1571 | 0x24020006, 0x1462000f, 0x3c020111, 0x0a000269, 0x00821025, 0x0a000268, | ||
1572 | 0x3c020101, 0x3c020011, 0x00821025, 0x24030001, 0xaf421000, 0xaf830030, | ||
1573 | 0x0a000271, 0x00000000, 0x00821025, 0xaf421000, 0xaf800030, 0x00000000, | ||
1574 | 0x00000000, 0x00000000, 0x00000000, 0x8f830030, 0x1060003f, 0x3c048000, | ||
1575 | 0x8f421000, 0x00441024, 0x1040fffd, 0x00000000, 0x10600039, 0x00000000, | ||
1576 | 0x8f421000, 0x3c030020, 0x00431024, 0x10400034, 0x00000000, 0x97421014, | ||
1577 | 0x14400031, 0x00000000, 0x97421008, 0x8f84001c, 0x24420006, 0x00024082, | ||
1578 | 0x00081880, 0x00643821, 0x8ce50000, 0x30430003, 0x30420001, 0x10400004, | ||
1579 | 0x00000000, 0x0000000d, 0x0a0002b0, 0x00081080, 0x5460000f, 0x30a5ffff, | ||
1580 | 0x3c06ffff, 0x00a62824, 0x0005182b, 0x00a61026, 0x0002102b, 0x00621824, | ||
1581 | 0x10600004, 0x00000000, 0x0000000d, 0x00000000, 0x240001fc, 0x8ce20000, | ||
1582 | 0x0a0002af, 0x00462825, 0x0005182b, 0x38a2ffff, 0x0002102b, 0x00621824, | ||
1583 | 0x10600004, 0x00000000, 0x0000000d, 0x00000000, 0x24000206, 0x8ce20000, | ||
1584 | 0x3445ffff, 0x00081080, 0x00441021, 0x3c030800, 0xac450000, 0x8c620840, | ||
1585 | 0x24420001, 0xac620840, 0x8f820008, 0x10400003, 0x00000000, 0x0e000660, | ||
1586 | 0x00000000, 0x8f840028, 0x02002821, 0x24820008, 0x30421fff, 0x24434000, | ||
1587 | 0x0343d821, 0x30a30007, 0xaf840018, 0xaf820028, 0xaf420084, 0x10600002, | ||
1588 | 0x24a20007, 0x3045fff8, 0x8f820044, 0x8f840004, 0x00451821, 0xaf82002c, | ||
1589 | 0x0064102b, 0xaf830044, 0x14400002, 0x00641023, 0xaf820044, 0x8f840044, | ||
1590 | 0x34028000, 0x8fbf0014, 0x8fb00010, 0x00821021, 0x03421821, 0x3c021000, | ||
1591 | 0xaf83001c, 0xaf440080, 0xaf420178, 0x03e00008, 0x27bd0018, 0x8f820024, | ||
1592 | 0x27bdffe8, 0xafbf0014, 0x10400004, 0xafb00010, 0x0000000d, 0x00000000, | ||
1593 | 0x24000249, 0x8f85001c, 0x24020001, 0xaf820024, 0x8ca70008, 0xa3800023, | ||
1594 | 0x8f620004, 0x3c100800, 0x26041b90, 0x00021402, 0xa3820010, 0x304600ff, | ||
1595 | 0x24c60005, 0x0e00064a, 0x00063082, 0x8f640004, 0x8f430108, 0x3c021000, | ||
1596 | 0x00621824, 0xa7840020, 0x10600008, 0x00000000, 0x97420104, 0x93830023, | ||
1597 | 0x2442ffec, 0x34630002, 0xa3830023, 0x0a000304, 0x3045ffff, 0x97420104, | ||
1598 | 0x2442fff0, 0x3045ffff, 0x8f620004, 0x3042ffff, 0x2c420013, 0x14400004, | ||
1599 | 0x00000000, 0x93820023, 0x34420001, 0xa3820023, 0x93830023, 0x24020001, | ||
1600 | 0x10620009, 0x28620002, 0x14400014, 0x24020002, 0x10620012, 0x24020003, | ||
1601 | 0x1062000a, 0x00000000, 0x0a000325, 0x00000000, 0x8f82001c, 0x8c43000c, | ||
1602 | 0x3c04ffff, 0x00641824, 0x00651825, 0x0a000325, 0xac43000c, 0x8f82001c, | ||
1603 | 0x8c430010, 0x3c04ffff, 0x00641824, 0x00651825, 0xac430010, 0x8f620004, | ||
1604 | 0x3042ffff, 0x24420002, 0x00021083, 0xa3820038, 0x304500ff, 0x8f82001c, | ||
1605 | 0x3c04ffff, 0x00052880, 0x00a22821, 0x8ca70000, 0x97820020, 0x97430104, | ||
1606 | 0x00e42024, 0x24420002, 0x00621823, 0x00833825, 0xaca70000, 0x93840038, | ||
1607 | 0x26061b90, 0x00041080, 0x00461021, 0x90430000, 0x3063000f, 0x00832021, | ||
1608 | 0xa3840022, 0x308200ff, 0x3c04fff6, 0x24420003, 0x00021080, 0x00461021, | ||
1609 | 0x8c450000, 0x93830022, 0x8f82001c, 0x3484ffff, 0x00a43824, 0x00031880, | ||
1610 | 0x00621821, 0xaf850000, 0xac67000c, 0x93820022, 0x93830022, 0x8f84001c, | ||
1611 | 0x24420003, 0x00021080, 0x00461021, 0x24630004, 0x00031880, 0xac470000, | ||
1612 | 0x93820022, 0x00661821, 0x94670002, 0x00021080, 0x00441021, 0xac670000, | ||
1613 | 0x24030010, 0xac470010, 0xa7430140, 0x24030002, 0xa7400142, 0xa7400144, | ||
1614 | 0xa7430146, 0x97420104, 0x8f840034, 0x24030001, 0x2442fffe, 0x30840006, | ||
1615 | 0xa7420148, 0x24020002, 0xa743014a, 0x1082000d, 0x2c820003, 0x10400005, | ||
1616 | 0x24020004, 0x10800011, 0x3c020009, 0x0a000383, 0x00000000, 0x10820007, | ||
1617 | 0x24020006, 0x1482000d, 0x3c020119, 0x0a00037d, 0x24030001, 0x0a00037c, | ||
1618 | 0x3c020109, 0x3c020019, 0x24030001, 0xaf421000, 0xaf830030, 0x0a000383, | ||
1619 | 0x00000000, 0xaf421000, 0xaf800030, 0x00000000, 0x00000000, 0x00000000, | ||
1620 | 0x00000000, 0x93820010, 0x24030008, 0x8f840030, 0x24420002, 0x30420007, | ||
1621 | 0x00621823, 0x30630007, 0xaf83000c, 0x10800005, 0x3c038000, 0x8f421000, | ||
1622 | 0x00431024, 0x1040fffd, 0x00000000, 0x8f820028, 0xaf820018, 0x24420010, | ||
1623 | 0x30421fff, 0xaf820028, 0xaf420084, 0x97430104, 0x24424000, 0x0342d821, | ||
1624 | 0x3063ffff, 0x30620007, 0x10400002, 0x24620007, 0x3043fff8, 0x8f820044, | ||
1625 | 0x8f840004, 0x00431821, 0xaf82002c, 0x0064102b, 0xaf830044, 0x14400002, | ||
1626 | 0x00641023, 0xaf820044, 0x8f840044, 0x34028000, 0x8fbf0014, 0x8fb00010, | ||
1627 | 0x00821021, 0x03421821, 0x3c021000, 0xaf83001c, 0xaf440080, 0xaf420178, | ||
1628 | 0x03e00008, 0x27bd0018, 0x8f820024, 0x27bdffe8, 0xafbf0014, 0x14400004, | ||
1629 | 0xafb00010, 0x0000000d, 0x00000000, 0x240002db, 0x8f620004, 0x04410009, | ||
1630 | 0x3c050800, 0x93820022, 0x8f830000, 0x24a41b90, 0xaf800024, 0x24420003, | ||
1631 | 0x00021080, 0x00441021, 0xac430000, 0x93820038, 0x24a51b90, 0x93860010, | ||
1632 | 0x3c040001, 0x27700008, 0x24420001, 0x00021080, 0x00451021, 0x8c430000, | ||
1633 | 0x24c60005, 0x00063082, 0x00641821, 0x02002021, 0x0e00064a, 0xac430000, | ||
1634 | 0x93840022, 0x3c057fff, 0x8f620004, 0x00042080, 0x00902021, 0x8c830004, | ||
1635 | 0x34a5ffff, 0x00451024, 0x00621821, 0xac830004, 0x93850038, 0x3c07ffff, | ||
1636 | 0x93840010, 0x00052880, 0x00b02821, 0x8ca30000, 0x97420104, 0x97860020, | ||
1637 | 0x00671824, 0x00441021, 0x00461023, 0x3042ffff, 0x00621825, 0xaca30000, | ||
1638 | 0x93830023, 0x24020001, 0x10620009, 0x28620002, 0x1440001a, 0x24020002, | ||
1639 | 0x10620018, 0x24020003, 0x1062000d, 0x00000000, 0x0a000411, 0x00000000, | ||
1640 | 0x93820010, 0x97430104, 0x8e04000c, 0x00621821, 0x2463fff2, 0x3063ffff, | ||
1641 | 0x00872024, 0x00832025, 0x0a000411, 0xae04000c, 0x93820010, 0x97430104, | ||
1642 | 0x8e040010, 0x00621821, 0x2463ffee, 0x3063ffff, 0x00872024, 0x00832025, | ||
1643 | 0xae040010, 0x9783000e, 0x8f840034, 0x2402000a, 0xa7420140, 0xa7430142, | ||
1644 | 0x93820010, 0xa7420144, 0xa7400146, 0x97430104, 0x30840006, 0x24020001, | ||
1645 | 0xa7430148, 0xa742014a, 0x24020002, 0x1082000d, 0x2c820003, 0x10400005, | ||
1646 | 0x24020004, 0x10800011, 0x3c020041, 0x0a000437, 0x00000000, 0x10820007, | ||
1647 | 0x24020006, 0x1482000d, 0x3c020151, 0x0a000431, 0x24030001, 0x0a000430, | ||
1648 | 0x3c020141, 0x3c020051, 0x24030001, 0xaf421000, 0xaf830030, 0x0a000437, | ||
1649 | 0x00000000, 0xaf421000, 0xaf800030, 0x00000000, 0x00000000, 0x00000000, | ||
1650 | 0x00000000, 0x8f820030, 0x93840010, 0x8f850028, 0x10400005, 0x3c038000, | ||
1651 | 0x8f421000, 0x00431024, 0x1040fffd, 0x00000000, 0x2483000a, 0x30620007, | ||
1652 | 0x10400002, 0x24620007, 0x304303f8, 0x00a31021, 0x30421fff, 0xaf850018, | ||
1653 | 0xaf820028, 0xaf420084, 0x97430104, 0x24424000, 0x0342d821, 0x3063ffff, | ||
1654 | 0x30620007, 0x10400002, 0x24620007, 0x3043fff8, 0x8f820044, 0x8f840004, | ||
1655 | 0x00431821, 0xaf82002c, 0x0064102b, 0xaf830044, 0x14400002, 0x00641023, | ||
1656 | 0xaf820044, 0x8f840044, 0x34028000, 0x8fbf0014, 0x8fb00010, 0x00821021, | ||
1657 | 0x03421821, 0x3c021000, 0xaf83001c, 0xaf440080, 0xaf420178, 0x03e00008, | ||
1658 | 0x27bd0018, 0x3c026000, 0x8c444448, 0x3c030800, 0xac64082c, 0x8f620000, | ||
1659 | 0x97430104, 0x3c048000, 0x3046ffff, 0x3067ffff, 0x8f420178, 0x00441024, | ||
1660 | 0x1440fffd, 0x2402000a, 0x30c30007, 0xa7420140, 0x24020008, 0x00431023, | ||
1661 | 0x30420007, 0x24c3fffe, 0xa7420142, 0xa7430144, 0xa7400146, 0xa7470148, | ||
1662 | 0x8f420108, 0x3c036000, 0x8f850034, 0x30420020, 0x0002102b, 0x00021023, | ||
1663 | 0x30420009, 0x34420001, 0xa742014a, 0x8c644448, 0x3c020800, 0x30a50006, | ||
1664 | 0xac440830, 0x24020002, 0x10a2000d, 0x2ca20003, 0x10400005, 0x24020004, | ||
1665 | 0x10a00011, 0x3c020041, 0x0a0004a8, 0x00000000, 0x10a20007, 0x24020006, | ||
1666 | 0x14a2000d, 0x3c020151, 0x0a0004a2, 0x24030001, 0x0a0004a1, 0x3c020141, | ||
1667 | 0x3c020051, 0x24030001, 0xaf421000, 0xaf830030, 0x0a0004a8, 0x00000000, | ||
1668 | 0xaf421000, 0xaf800030, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1669 | 0x8f820030, 0x24c30008, 0x10400006, 0x30e6ffff, 0x3c048000, 0x8f421000, | ||
1670 | 0x00441024, 0x1040fffd, 0x00000000, 0x3c026000, 0x8c444448, 0x3065ffff, | ||
1671 | 0x3c020800, 0x30a30007, 0x10600003, 0xac440834, 0x24a20007, 0x3045fff8, | ||
1672 | 0x8f840028, 0x00851021, 0x30421fff, 0x24434000, 0x0343d821, 0x30c30007, | ||
1673 | 0xaf840018, 0xaf820028, 0xaf420084, 0x10600002, 0x24c20007, 0x3046fff8, | ||
1674 | 0x8f820044, 0x8f840004, 0x00461821, 0xaf82002c, 0x0064102b, 0xaf830044, | ||
1675 | 0x14400002, 0x00641023, 0xaf820044, 0x8f840044, 0x34028000, 0x3c030800, | ||
1676 | 0x8c650844, 0x00821021, 0x03421821, 0xaf83001c, 0xaf440080, 0x10a00006, | ||
1677 | 0x2402000e, 0x93830043, 0x14620004, 0x3c021000, 0x2402043f, 0xa7420148, | ||
1678 | 0x3c021000, 0x3c036000, 0xaf420178, 0x8c644448, 0x3c020800, 0x03e00008, | ||
1679 | 0xac440838, 0x8f820034, 0x30424000, 0x10400005, 0x24020800, 0x0000000d, | ||
1680 | 0x00000000, 0x24000405, 0x24020800, 0xaf420178, 0x97440104, 0x3c030008, | ||
1681 | 0xaf430140, 0x8f820034, 0x30420001, 0x10400006, 0x3085ffff, 0x24020002, | ||
1682 | 0x24a3fffe, 0xa7420146, 0x0a0004ff, 0xa7430148, 0xa7400146, 0x8f840028, | ||
1683 | 0x2402000d, 0xa742014a, 0x24830008, 0x30631fff, 0x24624000, 0x0342d821, | ||
1684 | 0x30a20007, 0xaf840018, 0xaf830028, 0xaf430084, 0x10400002, 0x24a20007, | ||
1685 | 0x3045fff8, 0x8f820044, 0x8f840004, 0x00451821, 0xaf82002c, 0x0064102b, | ||
1686 | 0xaf830044, 0x14400002, 0x00641023, 0xaf820044, 0x8f840044, 0x34028000, | ||
1687 | 0x00821021, 0x03421821, 0x3c021000, 0xaf83001c, 0xaf440080, 0x03e00008, | ||
1688 | 0xaf420178, 0x27bdffe8, 0x3c046008, 0xafbf0014, 0xafb00010, 0x8c825000, | ||
1689 | 0x3c1a8000, 0x2403ff7f, 0x375b4000, 0x00431024, 0x3442380c, 0xac825000, | ||
1690 | 0x8f430008, 0x3c100800, 0x37428000, 0x34630001, 0xaf430008, 0xaf82001c, | ||
1691 | 0x3c02601c, 0xaf800028, 0xaf400080, 0xaf400084, 0x8c450008, 0x3c036000, | ||
1692 | 0x8c620808, 0x3c040800, 0x3c030080, 0xac830820, 0x3042fff0, 0x38420010, | ||
1693 | 0x2c420001, 0xaf850004, 0xaf820008, 0x0e00062f, 0x00000000, 0x8f420000, | ||
1694 | 0x30420001, 0x1040fffb, 0x00000000, 0x8f440108, 0x30822000, 0xaf840034, | ||
1695 | 0x10400004, 0x8e02083c, 0x24420001, 0x0a00059d, 0xae02083c, 0x30820200, | ||
1696 | 0x10400027, 0x00000000, 0x97420104, 0x1040001c, 0x30824000, 0x14400005, | ||
1697 | 0x00000000, 0x0e00022d, 0x00000000, 0x0a000592, 0x00000000, 0x8f620008, | ||
1698 | 0x8f630000, 0x24020030, 0x00031e02, 0x306300f0, 0x10620007, 0x28620031, | ||
1699 | 0x14400031, 0x24020040, 0x10620007, 0x00000000, 0x0a000592, 0x00000000, | ||
1700 | 0x0e0002dd, 0x00000000, 0x0a000592, 0x00000000, 0x0e0003b8, 0x00000000, | ||
1701 | 0x0a000592, 0x00000000, 0x30820040, 0x1440002d, 0x00000000, 0x0000000d, | ||
1702 | 0x00000000, 0x240004a6, 0x0a00059d, 0x00000000, 0x8f430100, 0x24020d00, | ||
1703 | 0x1462000f, 0x30820006, 0x97420104, 0x10400005, 0x30820040, 0x0e0004e9, | ||
1704 | 0x00000000, 0x0a000592, 0x00000000, 0x1440001b, 0x00000000, 0x0000000d, | ||
1705 | 0x00000000, 0x240004b8, 0x0a00059d, 0x00000000, 0x1040000e, 0x30821000, | ||
1706 | 0x10400005, 0x00000000, 0x0e00065d, 0x00000000, 0x0a000592, 0x00000000, | ||
1707 | 0x0e00046b, 0x00000000, 0x8f820040, 0x24420001, 0xaf820040, 0x0a00059d, | ||
1708 | 0x00000000, 0x30820040, 0x14400004, 0x00000000, 0x0000000d, 0x00000000, | ||
1709 | 0x240004cf, 0x8f420138, 0x3c034000, 0x00431025, 0xaf420138, 0x0a00053f, | ||
1710 | 0x00000000, 0x3c046008, 0x8c835000, 0x3c1a8000, 0x2402ff7f, 0x375b4000, | ||
1711 | 0x00621824, 0x3463380c, 0xac835000, 0x8f420008, 0x3c056000, 0x3c03601c, | ||
1712 | 0x34420001, 0xaf420008, 0x37428000, 0xaf800028, 0xaf82001c, 0xaf400080, | ||
1713 | 0xaf400084, 0x8c660008, 0x8ca20808, 0x3c040800, 0x3c030080, 0xac830820, | ||
1714 | 0x3042fff0, 0x38420010, 0x2c420001, 0xaf860004, 0xaf820008, 0x03e00008, | ||
1715 | 0x00000000, 0x3084ffff, 0x30820007, 0x10400002, 0x24820007, 0x3044fff8, | ||
1716 | 0x8f820028, 0x00441821, 0x30631fff, 0x24644000, 0x0344d821, 0xaf820018, | ||
1717 | 0xaf830028, 0x03e00008, 0xaf430084, 0x3084ffff, 0x30820007, 0x10400002, | ||
1718 | 0x24820007, 0x3044fff8, 0x8f820044, 0x8f830004, 0x00442021, 0xaf82002c, | ||
1719 | 0x0083102b, 0xaf840044, 0x14400002, 0x00831023, 0xaf820044, 0x8f820044, | ||
1720 | 0x34038000, 0x00431821, 0x03432021, 0xaf84001c, 0x03e00008, 0xaf420080, | ||
1721 | 0x8f830034, 0x24020002, 0x30630006, 0x1062000d, 0x2c620003, 0x50400005, | ||
1722 | 0x24020004, 0x10600012, 0x3c020001, 0x0a000601, 0x00000000, 0x10620007, | ||
1723 | 0x24020006, 0x1462000f, 0x3c020111, 0x0a0005f9, 0x00821025, 0x0a0005f8, | ||
1724 | 0x3c020101, 0x3c020011, 0x00821025, 0x24030001, 0xaf421000, 0xaf830030, | ||
1725 | 0x0a000601, 0x00000000, 0x00821025, 0xaf421000, 0xaf800030, 0x00000000, | ||
1726 | 0x00000000, 0x00000000, 0x03e00008, 0x00000000, 0x8f820030, 0x10400005, | ||
1727 | 0x3c038000, 0x8f421000, 0x00431024, 0x1040fffd, 0x00000000, 0x03e00008, | ||
1728 | 0x00000000, 0x8f820034, 0x27bdffe8, 0x30424000, 0x14400005, 0xafbf0010, | ||
1729 | 0x0e00022d, 0x00000000, 0x0a00062d, 0x8fbf0010, 0x8f620008, 0x8f630000, | ||
1730 | 0x24020030, 0x00031e02, 0x306300f0, 0x10620008, 0x28620031, 0x1440000d, | ||
1731 | 0x8fbf0010, 0x24020040, 0x10620007, 0x00000000, 0x0a00062d, 0x00000000, | ||
1732 | 0x0e0002dd, 0x00000000, 0x0a00062d, 0x8fbf0010, 0x0e0003b8, 0x00000000, | ||
1733 | 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x8f84003c, 0x1080000f, 0x3c026000, | ||
1734 | 0x8c430c3c, 0x30630fff, 0xaf830014, 0x14600011, 0x3082000f, 0x10400005, | ||
1735 | 0x308200f0, 0x10400003, 0x30820f00, 0x14400006, 0x00000000, 0x0000000d, | ||
1736 | 0x00000000, 0x2400050e, 0x03e00008, 0x00000000, 0x0000000d, 0x00000000, | ||
1737 | 0x24000513, 0x03e00008, 0x00000000, 0xaf83003c, 0x03e00008, 0x00000000, | ||
1738 | 0x10c00007, 0x00000000, 0x8ca20000, 0x24c6ffff, 0x24a50004, 0xac820000, | ||
1739 | 0x14c0fffb, 0x24840004, 0x03e00008, 0x00000000, 0x0a000659, 0x00a01021, | ||
1740 | 0xac860000, 0x24840004, 0x00a01021, 0x1440fffc, 0x24a5ffff, 0x03e00008, | ||
1741 | 0x00000000, 0x0000000d, 0x03e00008, 0x00000000, 0x3c040800, 0x8c82084c, | ||
1742 | 0x54400007, 0xac80084c, 0x8f820034, 0x24030400, 0x30420c00, 0x1443005b, | ||
1743 | 0x00000000, 0xac80084c, 0x0000000d, 0x00000000, 0x2400003c, 0x3c026000, | ||
1744 | 0x8c444448, 0x3c030800, 0xac640850, 0x24000043, 0x97420104, 0x3045ffff, | ||
1745 | 0x000530c2, 0x24a2007f, 0x000239c2, 0x2400004e, 0x3c046020, 0x24030020, | ||
1746 | 0xac830000, 0x8c820000, 0x30420020, 0x10400005, 0x3c036020, 0x8c620000, | ||
1747 | 0x30420020, 0x1440fffd, 0x00000000, 0x3c026020, 0x8c430010, 0x24040001, | ||
1748 | 0x0087102b, 0x30ea007f, 0x24abfffe, 0x10400010, 0x00034240, 0x3c056020, | ||
1749 | 0x24090020, 0xaca90000, 0x8ca20000, 0x30420020, 0x10400006, 0x24840001, | ||
1750 | 0x3c036020, 0x8c620000, 0x30420020, 0x1440fffd, 0x00000000, 0x0087102b, | ||
1751 | 0x1440fff4, 0x00000000, 0x8f85001c, 0x3c026020, 0x8c430010, 0x3c046020, | ||
1752 | 0x34848000, 0x006a1825, 0x01034025, 0x2400006b, 0x10c0000b, 0x00000000, | ||
1753 | 0x8ca30000, 0x24a50004, 0x8ca20000, 0x24a50004, 0x24c6ffff, 0xac820000, | ||
1754 | 0x24840004, 0xac830000, 0x14c0fff7, 0x24840004, 0x24000077, 0x3c020007, | ||
1755 | 0x34427700, 0x3c036000, 0xac6223c8, 0xac6b23cc, 0xac6823e4, 0x24000086, | ||
1756 | 0x3c046000, 0x3c038000, 0x8c8223f8, 0x00431024, 0x1440fffd, 0x3c021000, | ||
1757 | 0x3c056000, 0x24030019, 0xaca223f8, 0xa743014a, 0x8ca44448, 0x3c020800, | ||
1758 | 0xac440854, 0x03e00008, 0x00000000, 0x00000000 }; | ||
1759 | |||
1760 | static u32 bnx2_TPAT_b06FwData[(0x0/4) + 1] = { 0x00000000 }; | ||
1761 | static u32 bnx2_TPAT_b06FwRodata[(0x0/4) + 1] = { 0x00000000 }; | ||
1762 | static u32 bnx2_TPAT_b06FwBss[(0x80/4) + 1] = { 0x00000000 }; | ||
1763 | static u32 bnx2_TPAT_b06FwSbss[(0x48/4) + 1] = { 0x00000000 }; | ||
1764 | |||
1765 | static int bnx2_TXP_b06FwReleaseMajor = 0x0; | ||
1766 | static int bnx2_TXP_b06FwReleaseMinor = 0x0; | ||
1767 | static int bnx2_TXP_b06FwReleaseFix = 0x0; | ||
1768 | static u32 bnx2_TXP_b06FwStartAddr = 0x08002090; | ||
1769 | static u32 bnx2_TXP_b06FwTextAddr = 0x08000000; | ||
1770 | static int bnx2_TXP_b06FwTextLen = 0x3ffc; | ||
1771 | static u32 bnx2_TXP_b06FwDataAddr = 0x08004020; | ||
1772 | static int bnx2_TXP_b06FwDataLen = 0x0; | ||
1773 | static u32 bnx2_TXP_b06FwRodataAddr = 0x00000000; | ||
1774 | static int bnx2_TXP_b06FwRodataLen = 0x0; | ||
1775 | static u32 bnx2_TXP_b06FwBssAddr = 0x08004060; | ||
1776 | static int bnx2_TXP_b06FwBssLen = 0x194; | ||
1777 | static u32 bnx2_TXP_b06FwSbssAddr = 0x08004020; | ||
1778 | static int bnx2_TXP_b06FwSbssLen = 0x34; | ||
1779 | static u32 bnx2_TXP_b06FwText[(0x3ffc/4) + 1] = { | ||
1780 | 0x0a000824, 0x00000000, 0x00000000, 0x0000000d, 0x74787020, 0x302e362e, | ||
1781 | 0x39000000, 0x00060900, 0x0000000a, 0x000003e8, 0x0000ea60, 0x00000000, | ||
1782 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1783 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1784 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1785 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1786 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1787 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1788 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1789 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1790 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1791 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1792 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1793 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1794 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1795 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1796 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1797 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1798 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1799 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1800 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1801 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1802 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1803 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1804 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1805 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1806 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1807 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1808 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1809 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1810 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1811 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1812 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1813 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1814 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1815 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1816 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1817 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1818 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1819 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1820 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1821 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1822 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1823 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1824 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1825 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1826 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1827 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1828 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1829 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1830 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1831 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1832 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1833 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1834 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1835 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1836 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1837 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1838 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1839 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1840 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1841 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1842 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1843 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1844 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1845 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1846 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1847 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1848 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1849 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1850 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1851 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1852 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1853 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1854 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1855 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1856 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1857 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1858 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1859 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1860 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1861 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1862 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1863 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1864 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1865 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1866 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1867 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1868 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1869 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1870 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1871 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1872 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1873 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1874 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1875 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1876 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1877 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1878 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1879 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1880 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1881 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1882 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1883 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1884 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1885 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1886 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1887 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1888 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1889 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1890 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1891 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1892 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1893 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1894 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1895 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1896 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1897 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1898 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1899 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1900 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1901 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1902 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1903 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1904 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1905 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1906 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1907 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1908 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1909 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1910 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1911 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1912 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1913 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1914 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1915 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1916 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1917 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1918 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1919 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1920 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1921 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1922 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1923 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1924 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1925 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1926 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1927 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1928 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1929 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1930 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1931 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1932 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1933 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1934 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1935 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1936 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1937 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1938 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1939 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1940 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1941 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1942 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1943 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1944 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1945 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1946 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1947 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1948 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1949 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1950 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1951 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1952 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1953 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1954 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1955 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1956 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1957 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1958 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1959 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1960 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1961 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1962 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1963 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1964 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1965 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1966 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1967 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1968 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1969 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1970 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1971 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1972 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1973 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1974 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1975 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1976 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1977 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1978 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1979 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1980 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1981 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1982 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1983 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1984 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1985 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1986 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1987 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1988 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1989 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1990 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1991 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1992 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1993 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1994 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1995 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1996 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1997 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1998 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
1999 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2000 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2001 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2002 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2003 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2004 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2005 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2006 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2007 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2008 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2009 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2010 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2011 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2012 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2013 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2014 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2015 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2016 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2017 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2018 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2019 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2020 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2021 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2022 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2023 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2024 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2025 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2026 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2027 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2028 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2029 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2030 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2031 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2032 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2033 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2034 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2035 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2036 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2037 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2038 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2039 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2040 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2041 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2042 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2043 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2044 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2045 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2046 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2047 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2048 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2049 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2050 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2051 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2052 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2053 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2054 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2055 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2056 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2057 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2058 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2059 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2060 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2061 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2062 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2063 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2064 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2065 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2066 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2067 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2068 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2069 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2070 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2071 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2072 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2073 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2074 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2075 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2076 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2077 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2078 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2079 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2080 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2081 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2082 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2083 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2084 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2085 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2086 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2087 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2088 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2089 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2090 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2091 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2092 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2093 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2094 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2095 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2096 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2097 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2098 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2099 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2100 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2101 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2102 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2103 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2104 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2105 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2106 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2107 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2108 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2109 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2110 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2111 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2112 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2113 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2114 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2115 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2116 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2117 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2118 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2119 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2120 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2121 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2122 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2123 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2124 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2125 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2126 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2127 | 0x00000000, 0x00000000, 0x00000000, 0x10000003, 0x00000000, 0x0000000d, | ||
2128 | 0x0000000d, 0x3c020800, 0x24424020, 0x3c030800, 0x246341f4, 0xac400000, | ||
2129 | 0x0043202b, 0x1480fffd, 0x24420004, 0x3c1d0800, 0x37bd7ffc, 0x03a0f021, | ||
2130 | 0x3c100800, 0x26102090, 0x3c1c0800, 0x279c4020, 0x0e000a0e, 0x00000000, | ||
2131 | 0x0000000d, 0x8f840014, 0x27bdffe8, 0xafb00010, 0x8f460104, 0x8f830008, | ||
2132 | 0x8c8500ac, 0xaf430080, 0x948200a8, 0xa7420e10, 0x948300aa, 0xa7430e12, | ||
2133 | 0x8c8200ac, 0xaf420e18, 0x97430e10, 0xa7430e14, 0x97420e12, 0xa7420e16, | ||
2134 | 0x8f430e18, 0x00005021, 0x00c53023, 0x10c001a3, 0xaf430e1c, 0x240f0800, | ||
2135 | 0x3c0e1000, 0x2419fff8, 0x24100010, 0x3c188100, 0x93620008, 0x10400009, | ||
2136 | 0x00000000, 0x97620010, 0x00c2102b, 0x14400005, 0x00000000, 0x97620010, | ||
2137 | 0x3042ffff, 0x0a000862, 0xaf420e00, 0xaf460e00, 0x8f420000, 0x30420008, | ||
2138 | 0x1040fffd, 0x00000000, 0x97420e08, 0x8f450e04, 0x3044ffff, 0x30820001, | ||
2139 | 0x14400005, 0x00000000, 0x14a00005, 0x3083a040, 0x0a0009e6, 0x00000000, | ||
2140 | 0x0000000d, 0x3083a040, 0x24020040, 0x14620049, 0x3082a000, 0x8f87000c, | ||
2141 | 0x30880036, 0x30890008, 0xaf4f0178, 0x00e01821, 0x9742008a, 0x00431023, | ||
2142 | 0x2442ffff, 0x30421fff, 0x2c420008, 0x1440fffa, 0x00000000, 0x8f830018, | ||
2143 | 0x00a05021, 0x00c53023, 0x24e24000, 0x03422821, 0x306b00ff, 0x24630001, | ||
2144 | 0xaf830018, 0x93840012, 0x000b1400, 0x3c030100, 0x00431025, 0xaca20000, | ||
2145 | 0x8f820018, 0x30840007, 0x00042240, 0x34870001, 0x00e83825, 0x1120000f, | ||
2146 | 0xaca20004, 0x97430e0a, 0x8f84000c, 0x00ee3825, 0x2402000e, 0x00781825, | ||
2147 | 0xaf430160, 0x25430006, 0x24840008, 0x30841fff, 0xa742015a, 0xa7430158, | ||
2148 | 0xaf84000c, 0x0a0008a9, 0x00000000, 0x8f83000c, 0x25420002, 0xa7420158, | ||
2149 | 0x24630008, 0x30631fff, 0xaf83000c, 0x54c0000c, 0x8f420e14, 0x97420e10, | ||
2150 | 0x97430e12, 0x8f840014, 0x00021400, 0x00621825, 0xac8300a8, 0x8f850014, | ||
2151 | 0x8f420e18, 0x34e70040, 0xaca200ac, 0x8f420e14, 0x8f430e1c, 0xaf420144, | ||
2152 | 0xaf430148, 0xa34b0152, 0xaf470154, 0x0a0009f1, 0xaf4e0178, 0x10400128, | ||
2153 | 0x00000000, 0x97620010, 0x00a2102b, 0x10400003, 0x30820040, 0x10400122, | ||
2154 | 0x00000000, 0xafa60008, 0xa7840010, 0xaf850004, 0x93620008, 0x1440005e, | ||
2155 | 0x27ac0008, 0xaf60000c, 0x97820010, 0x30424000, 0x10400002, 0x2403000e, | ||
2156 | 0x24030016, 0xa363000a, 0x24034007, 0xaf630014, 0x93820012, 0x8f630014, | ||
2157 | 0x30420007, 0x00021240, 0x00621825, 0xaf630014, 0x97820010, 0x8f630014, | ||
2158 | 0x30420010, 0x00621825, 0xaf630014, 0x97820010, 0x30420008, 0x5040000e, | ||
2159 | 0x00002821, 0x8f620014, 0x004e1025, 0xaf620014, 0x97430e0a, 0x2402000e, | ||
2160 | 0x00781825, 0xaf630004, 0xa3620002, 0x9363000a, 0x3405fffc, 0x24630004, | ||
2161 | 0x0a0008f2, 0xa363000a, 0xaf600004, 0xa3600002, 0x97820010, 0x9363000a, | ||
2162 | 0x30421f00, 0x00021182, 0x24420028, 0x00621821, 0xa3630009, 0x97420e0c, | ||
2163 | 0xa7620010, 0x93630009, 0x24020008, 0x24630002, 0x30630007, 0x00431023, | ||
2164 | 0x30420007, 0xa362000b, 0x93640009, 0x97620010, 0x8f890004, 0x97830010, | ||
2165 | 0x00441021, 0x00a21021, 0x30630040, 0x10600006, 0x3045ffff, 0x15250005, | ||
2166 | 0x0125102b, 0x3c068000, 0x0a000925, 0x00005821, 0x0125102b, 0x144000c8, | ||
2167 | 0x00005021, 0x97420e14, 0xa7420e10, 0x97430e16, 0xa7430e12, 0x8f420e1c, | ||
2168 | 0xaf420e18, 0xaf450e00, 0x8f420000, 0x30420008, 0x1040fffd, 0x00000000, | ||
2169 | 0x97420e08, 0x00a04821, 0xa7820010, 0x8f430e04, 0x00003021, 0x240b0001, | ||
2170 | 0xaf830004, 0x97620010, 0x0a000936, 0x304dffff, 0x8f890004, 0x97820010, | ||
2171 | 0x30420040, 0x10400004, 0x01206821, 0x3c068000, 0x0a000936, 0x00005821, | ||
2172 | 0x97630010, 0x8f820004, 0x144300a7, 0x00005021, 0x00003021, 0x240b0001, | ||
2173 | 0x8d820000, 0x00491023, 0x1440000d, 0xad820000, 0x8f620014, 0x34420040, | ||
2174 | 0xaf620014, 0x97430e10, 0x97420e12, 0x8f840014, 0x00031c00, 0x00431025, | ||
2175 | 0xac8200a8, 0x8f830014, 0x8f420e18, 0xac6200ac, 0x93620008, 0x1440003f, | ||
2176 | 0x00000000, 0x25260002, 0x8f84000c, 0x9743008a, 0x3063ffff, 0xafa30000, | ||
2177 | 0x8fa20000, 0x00441023, 0x2442ffff, 0x30421fff, 0x2c420010, 0x1440fff7, | ||
2178 | 0x00000000, 0x8f82000c, 0x8f830018, 0x00021082, 0x00021080, 0x24424000, | ||
2179 | 0x03422821, 0x00605021, 0x24630001, 0x314200ff, 0x00021400, 0xaf830018, | ||
2180 | 0x3c033200, 0x00431025, 0xaca20000, 0x93630009, 0x9362000a, 0x00031c00, | ||
2181 | 0x00431025, 0xaca20004, 0x8f830018, 0xaca30008, 0x97820010, 0x30420008, | ||
2182 | 0x10400002, 0x00c04021, 0x25280006, 0x97430e14, 0x93640002, 0x8f450e1c, | ||
2183 | 0x8f660004, 0x8f670014, 0xaf4f0178, 0x3063ffff, 0xa7430144, 0x97420e16, | ||
2184 | 0xa7420146, 0xaf450148, 0xa34a0152, 0x8f82000c, 0x308400ff, 0xa744015a, | ||
2185 | 0xaf460160, 0xa7480158, 0xaf470154, 0xaf4e0178, 0x00501021, 0x30421fff, | ||
2186 | 0xaf82000c, 0x0a0009c5, 0x8d820000, 0x93620009, 0x9363000b, 0x8f85000c, | ||
2187 | 0x2463000a, 0x00435021, 0x25440007, 0x00992024, 0x9743008a, 0x3063ffff, | ||
2188 | 0xafa30000, 0x8fa20000, 0x00451023, 0x2442ffff, 0x30421fff, 0x0044102b, | ||
2189 | 0x1440fff7, 0x00000000, 0x8f82000c, 0x8f840018, 0x00021082, 0x00021080, | ||
2190 | 0x24424000, 0x03422821, 0x00804021, 0x24840001, 0xaf840018, 0x93630009, | ||
2191 | 0x310200ff, 0x00022400, 0x3c024100, 0x24630002, 0x00621825, 0x00832025, | ||
2192 | 0xaca40000, 0x8f62000c, 0x00461025, 0xaca20004, 0x97430e14, 0x93640002, | ||
2193 | 0x8f450e1c, 0x8f660004, 0x8f670014, 0xaf4f0178, 0x3063ffff, 0xa7430144, | ||
2194 | 0x97420e16, 0x308400ff, 0xa7420146, 0xaf450148, 0xa3480152, 0x8f83000c, | ||
2195 | 0x25420007, 0x00591024, 0xa744015a, 0xaf460160, 0xa7490158, 0xaf470154, | ||
2196 | 0xaf4e0178, 0x00621821, 0x30631fff, 0xaf83000c, 0x8d820000, 0x14400005, | ||
2197 | 0x00000000, 0x8f620014, 0x2403ffbf, 0x00431024, 0xaf620014, 0x8f62000c, | ||
2198 | 0x004d1021, 0xaf62000c, 0x93630008, 0x14600008, 0x00000000, 0x11600006, | ||
2199 | 0x00000000, 0x8f630014, 0x3c02efff, 0x3442fffe, 0x00621824, 0xaf630014, | ||
2200 | 0xa36b0008, 0x01205021, 0x15400016, 0x8fa60008, 0x97420e14, 0x97430e16, | ||
2201 | 0x8f850014, 0x00021400, 0x00621825, 0xaca300a8, 0x8f840014, 0x8f420e1c, | ||
2202 | 0x0a0009f3, 0xac8200ac, 0x97420e14, 0x97430e16, 0x8f840014, 0x00021400, | ||
2203 | 0x00621825, 0xac8300a8, 0x8f850014, 0x8f420e1c, 0x00005021, 0x0a0009f3, | ||
2204 | 0xaca200ac, 0x14c0fe64, 0x00000000, 0x55400018, 0x8fb00010, 0x3c038000, | ||
2205 | 0x8f420178, 0x00431024, 0x1440fffd, 0x00000000, 0x97430e14, 0x8f440e1c, | ||
2206 | 0x24020800, 0xaf420178, 0x3063ffff, 0xa7430144, 0x97420e16, 0x3c031000, | ||
2207 | 0xa7420146, 0x24020240, 0xaf440148, 0xa3400152, 0xa740015a, 0xaf400160, | ||
2208 | 0xa7400158, 0xaf420154, 0xaf430178, 0x8fb00010, 0x03e00008, 0x27bd0018, | ||
2209 | 0x27bdffd8, 0x3c1a8000, 0x3c0420ff, 0x3484fffd, 0x3c020008, 0x03421821, | ||
2210 | 0xafbf0020, 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0xaf830014, | ||
2211 | 0xaf440e00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, | ||
2212 | 0x3c0200ff, 0x3442fffd, 0x3c046004, 0xaf420e00, 0x8c835000, 0x24130d00, | ||
2213 | 0x3c120800, 0x3c114000, 0x2402ff7f, 0x00621824, 0x3463380c, 0x24020009, | ||
2214 | 0xac835000, 0xaf420008, 0xaf800018, 0xaf80000c, 0x0e000fa1, 0x00000000, | ||
2215 | 0x0e000a96, 0x00000000, 0x3c020800, 0x24504080, 0x8f420000, 0x30420001, | ||
2216 | 0x1040fffd, 0x00000000, 0x8f440100, 0xaf840008, 0xaf440020, 0x93430108, | ||
2217 | 0xa3830012, 0x93820012, 0x30420001, 0x10400008, 0x00000000, 0x93820012, | ||
2218 | 0x30420006, 0x00021100, 0x0e00083b, 0x0050d821, 0x0a000a52, 0x00000000, | ||
2219 | 0x14930005, 0x00000000, 0x0e00083b, 0x265b4100, 0x0a000a52, 0x00000000, | ||
2220 | 0x0e000ba3, 0x00000000, 0xaf510138, 0x0a000a36, 0x00000000, 0x27bdfff8, | ||
2221 | 0x3084ffff, 0x24820007, 0x3044fff8, 0x8f85000c, 0x9743008a, 0x3063ffff, | ||
2222 | 0xafa30000, 0x8fa20000, 0x00451023, 0x2442ffff, 0x30421fff, 0x0044102b, | ||
2223 | 0x1440fff7, 0x00000000, 0x8f82000c, 0x00021082, 0x00021080, 0x24424000, | ||
2224 | 0x03421021, 0x03e00008, 0x27bd0008, 0x3084ffff, 0x8f82000c, 0x24840007, | ||
2225 | 0x3084fff8, 0x00441021, 0x30421fff, 0xaf82000c, 0x03e00008, 0x00000000, | ||
2226 | 0x27bdffe8, 0x3c1a8000, 0x3c0420ff, 0x3484fffd, 0x3c020008, 0x03421821, | ||
2227 | 0xafbf0010, 0xaf830014, 0xaf440e00, 0x00000000, 0x00000000, 0x00000000, | ||
2228 | 0x00000000, 0x00000000, 0x3c0200ff, 0x3442fffd, 0x3c046004, 0xaf420e00, | ||
2229 | 0x8c825000, 0x2403ff7f, 0x00431024, 0x3442380c, 0x24030009, 0xac825000, | ||
2230 | 0xaf430008, 0xaf800018, 0xaf80000c, 0x0e000fa1, 0x00000000, 0x0e000a96, | ||
2231 | 0x00000000, 0x8fbf0010, 0x03e00008, 0x27bd0018, 0x27bdffe8, 0x3c02000a, | ||
2232 | 0x03421821, 0x3c040800, 0x24844120, 0x24050018, 0xafbf0010, 0xaf830024, | ||
2233 | 0x0e000fad, 0x00003021, 0x3c050800, 0x3c020800, 0x24423d60, 0xaca24180, | ||
2234 | 0x24a54180, 0x3c020800, 0x24423e18, 0x3c030800, 0x24633e2c, 0x3c040800, | ||
2235 | 0xaca20004, 0x3c020800, 0x24423d68, 0xaca30008, 0xac824190, 0x24844190, | ||
2236 | 0x3c020800, 0x24423da4, 0x3c070800, 0x24e73de4, 0x3c060800, 0x24c63e40, | ||
2237 | 0x3c050800, 0x24a52b28, 0x3c030800, 0xac820004, 0x3c020800, 0x24423e48, | ||
2238 | 0xac870008, 0xac86000c, 0xac850010, 0xac6241b0, 0x246341b0, 0x8fbf0010, | ||
2239 | 0x3c020800, 0x24423e60, 0xac620004, 0xac670008, 0xac66000c, 0xac650010, | ||
2240 | 0x03e00008, 0x27bd0018, 0x27bdffc8, 0x3c020800, 0x24424120, 0xafbf0030, | ||
2241 | 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x90470021, 0x8c510008, | ||
2242 | 0x8c45001c, 0x8f900020, 0x3c060800, 0x3c038000, 0x8f420178, 0x00431024, | ||
2243 | 0x1440fffd, 0x8cc2414c, 0x24c3414c, 0x2473ffd4, 0xaf420144, 0x8e620030, | ||
2244 | 0x30b22000, 0xaf420148, 0x3c021000, 0xaf50014c, 0xa3470152, 0xa7510158, | ||
2245 | 0xaf450154, 0xaf420178, 0x12400004, 0x3c030800, 0x8c620030, 0x24420001, | ||
2246 | 0xac620030, 0x93420109, 0x9344010a, 0x00111c00, 0xafa30018, 0x00071a00, | ||
2247 | 0xafa50014, 0x8cc5414c, 0x00021600, 0x00042400, 0x00441025, 0x00431025, | ||
2248 | 0xafa20010, 0x8f440100, 0x8e660030, 0x0e000fe1, 0x02003821, 0x1640000e, | ||
2249 | 0x8fbf0030, 0x8f820000, 0x8e630030, 0x8c44017c, 0x02031823, 0x00711823, | ||
2250 | 0x00641823, 0x2c630002, 0x14600006, 0x8fb3002c, 0x0000000d, 0x00000000, | ||
2251 | 0x240000ca, 0x8fbf0030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020, | ||
2252 | 0x03e00008, 0x27bd0038, 0x974309da, 0x00804021, 0xad030000, 0x8f4209dc, | ||
2253 | 0xad020004, 0x8f4309e0, 0xad030008, 0x934409d9, 0x24020001, 0x30840003, | ||
2254 | 0x1082001f, 0x30a900ff, 0x28820002, 0x10400005, 0x24020002, 0x10800009, | ||
2255 | 0x3c0a0800, 0x0a000b64, 0x93420934, 0x1082000b, 0x24020003, 0x10820026, | ||
2256 | 0x3c0a0800, 0x0a000b64, 0x93420934, 0x974209e4, 0x00021400, 0x34420800, | ||
2257 | 0xad02000c, 0x0a000b63, 0x25080010, 0x974209e4, 0x00021400, 0x34428100, | ||
2258 | 0xad02000c, 0x974309e8, 0x3c0a0800, 0x00031c00, 0x34630800, 0xad030010, | ||
2259 | 0x0a000b63, 0x25080014, 0x974409e4, 0x3c050800, 0x24a24120, 0x94430018, | ||
2260 | 0x94460010, 0x9447000c, 0x00a05021, 0x24020800, 0xad000010, 0xad020014, | ||
2261 | 0x00042400, 0x00661821, 0x00671823, 0x2463fff2, 0x00832025, 0xad04000c, | ||
2262 | 0x0a000b63, 0x25080018, 0x974209e4, 0x3c050800, 0x00021400, 0x34428100, | ||
2263 | 0xad02000c, 0x974409e8, 0x24a24120, 0x94430018, 0x94460010, 0x9447000c, | ||
2264 | 0x00a05021, 0x24020800, 0xad000014, 0xad020018, 0x00042400, 0x00661821, | ||
2265 | 0x00671823, 0x2463ffee, 0x00832025, 0xad040010, 0x2508001c, 0x93420934, | ||
2266 | 0x93450921, 0x3c074000, 0x25444120, 0x94830014, 0x94860010, 0x00021082, | ||
2267 | 0x00021600, 0x00052c00, 0x00a72825, 0x00451025, 0x00661821, 0x00431025, | ||
2268 | 0xad020000, 0x97830028, 0x974209ea, 0x00621821, 0x00031c00, 0xad030004, | ||
2269 | 0x97820028, 0x24420001, 0x30427fff, 0xa7820028, 0x93430920, 0x3c020006, | ||
2270 | 0x00031e00, 0x00621825, 0xad030008, 0x8f42092c, 0xad02000c, 0x8f430930, | ||
2271 | 0xad030010, 0x8f440938, 0x25080014, 0xad040000, 0x8f820020, 0x11200004, | ||
2272 | 0xad020004, 0x8f420940, 0x0a000b8d, 0x2442ffff, 0x8f420940, 0xad020008, | ||
2273 | 0x8f440948, 0x8f420940, 0x93430936, 0x00822823, 0x00652806, 0x3402ffff, | ||
2274 | 0x0045102b, 0x54400001, 0x3405ffff, 0x93420937, 0x25444120, 0x90830020, | ||
2275 | 0xad000010, 0x00021700, 0x34630010, 0x00031c00, 0x00431025, 0x00451025, | ||
2276 | 0xad02000c, 0x03e00008, 0x25020014, 0x27bdffb0, 0x3c020008, 0x03421821, | ||
2277 | 0xafbf004c, 0xafbe0048, 0xafb70044, 0xafb60040, 0xafb5003c, 0xafb40038, | ||
2278 | 0xafb30034, 0xafb20030, 0xafb1002c, 0xafb00028, 0xaf830000, 0x24020040, | ||
2279 | 0xaf420814, 0xaf400810, 0x8f420944, 0x8f430950, 0x8f440954, 0x8f45095c, | ||
2280 | 0xaf820030, 0xaf830020, 0xaf84001c, 0xaf85002c, 0x93430900, 0x24020020, | ||
2281 | 0x10620005, 0x24020030, 0x10620022, 0x3c030800, 0x0a000bf1, 0x8c62002c, | ||
2282 | 0x24020088, 0xaf420818, 0x3c020800, 0x24424180, 0xafa20020, 0x93430109, | ||
2283 | 0x3c020800, 0x10600009, 0x24574190, 0x3c026000, 0x24030100, 0xac43081c, | ||
2284 | 0x3c030001, 0xac43081c, 0x0000000d, 0x00000000, 0x2400031d, 0x9342010a, | ||
2285 | 0x30420080, 0x1440001c, 0x00000000, 0x3c026000, 0x24030100, 0xac43081c, | ||
2286 | 0x3c030001, 0xac43081c, 0x0000000d, 0x00000000, 0x24000324, 0x0a000bf4, | ||
2287 | 0x00000000, 0x93430109, 0x3063007f, 0x00031140, 0x000318c0, 0x00431021, | ||
2288 | 0x24430088, 0xaf430818, 0x0000000d, 0x3c020800, 0x244241d0, 0x3c030800, | ||
2289 | 0x247741e0, 0x0a000bf4, 0xafa20020, 0x24420001, 0x0a000f4c, 0xac62002c, | ||
2290 | 0x8f840000, 0x8f850020, 0x24020800, 0xaf420178, 0x8f4209a4, 0x8c83017c, | ||
2291 | 0x00a21023, 0x00431023, 0x2c420002, 0x14400004, 0x00000000, 0x0000000d, | ||
2292 | 0x00000000, 0x24000349, 0x8f420104, 0x8f430988, 0x00431023, 0x58400005, | ||
2293 | 0x8f4209a0, 0x0000000d, 0x00000000, 0x2400034d, 0x8f4209a0, 0x3c100800, | ||
2294 | 0xae02414c, 0x8f4309a4, 0x2604414c, 0x2491ffd4, 0xae230030, 0x8f420104, | ||
2295 | 0xae250024, 0x00431023, 0xac82ffd4, 0x8fa30020, 0x8c620000, 0x0040f809, | ||
2296 | 0x0200b021, 0x00409021, 0x32440010, 0x32420002, 0x10400007, 0xafa40024, | ||
2297 | 0x8e22001c, 0x32500040, 0x2403ffbf, 0x00431024, 0x0a000f13, 0xae22001c, | ||
2298 | 0x32420020, 0x10400002, 0x3c020800, 0x245741b0, 0x32420001, 0x14400007, | ||
2299 | 0x00000000, 0x8f820008, 0xaf420080, 0x8ec3414c, 0xaf430e10, 0x8e220030, | ||
2300 | 0xaf420e18, 0x9343010b, 0x93420905, 0x30420008, 0x1040003c, 0x307400ff, | ||
2301 | 0x8f820000, 0x8c430074, 0x0460000a, 0x00000000, 0x3c026000, 0x24030100, | ||
2302 | 0xac43081c, 0x3c030001, 0xac43081c, 0x0000000d, 0x00000000, 0x24000384, | ||
2303 | 0x8f820000, 0x9044007b, 0x9343010a, 0x14830027, 0x32500040, 0x24072000, | ||
2304 | 0x3c090800, 0x3c038000, 0x8f420178, 0x00431024, 0x1440fffd, 0x8ec2414c, | ||
2305 | 0x26c4414c, 0x2484ffd4, 0xaf420144, 0x8c820030, 0x3c030100, 0xaf420148, | ||
2306 | 0x24020047, 0xaf43014c, 0x00001821, 0xa3420152, 0x3c021000, 0xa7430158, | ||
2307 | 0xaf470154, 0xaf420178, 0x8ec5414c, 0x8d230030, 0x8c860030, 0x24630001, | ||
2308 | 0xad230030, 0x93420109, 0x9343010a, 0xafa70014, 0xafa00018, 0x00021600, | ||
2309 | 0x00031c00, 0x00431025, 0x34424700, 0xafa20010, 0x8f440100, 0x0e000fe1, | ||
2310 | 0x3c070100, 0x3c030800, 0x24624120, 0x0a000d01, 0x8c43001c, 0x32820002, | ||
2311 | 0x10400047, 0x3c039000, 0x34630001, 0x8f820008, 0x32500040, 0x3c048000, | ||
2312 | 0x00431025, 0xaf420020, 0x8f420020, 0x00441024, 0x1440fffd, 0x00000000, | ||
2313 | 0x8f830000, 0x90620005, 0x3c058000, 0x34420008, 0xa0620005, 0x8f860000, | ||
2314 | 0x34a50001, 0x8f840008, 0x8cc20074, 0x3c038000, 0x00852025, 0x00431025, | ||
2315 | 0xacc20074, 0xaf440020, 0x90c3007b, 0x9342010a, 0x14620028, 0x3c040800, | ||
2316 | 0x24072000, 0x3c090800, 0x3c038000, 0x8f420178, 0x00431024, 0x1440fffd, | ||
2317 | 0x8ec2414c, 0x26c4414c, 0x2484ffd4, 0xaf420144, 0x8c820030, 0x3c030100, | ||
2318 | 0xaf420148, 0x24020046, 0xaf43014c, 0x00001821, 0xa3420152, 0x3c021000, | ||
2319 | 0xa7430158, 0xaf470154, 0xaf420178, 0x8ec5414c, 0x8d230030, 0x8c860030, | ||
2320 | 0x24630001, 0xad230030, 0x93420109, 0x9343010a, 0xafa70014, 0xafa00018, | ||
2321 | 0x00021600, 0x00031c00, 0x00431025, 0x34424600, 0xafa20010, 0x8f440100, | ||
2322 | 0x0e000fe1, 0x3c070100, 0x3c040800, 0x24824120, 0x0a000d01, 0x8c43001c, | ||
2323 | 0x93420108, 0x30420010, 0x50400050, 0x9343093f, 0x8f860000, 0x90c3007f, | ||
2324 | 0x90c2007e, 0x90c40080, 0x306800ff, 0x00021600, 0x00081c00, 0x00431025, | ||
2325 | 0x00042200, 0x90c3007a, 0x90c5000a, 0x00441025, 0x11050028, 0x00623825, | ||
2326 | 0xa0c8000a, 0x24086000, 0x3c090800, 0x3c038000, 0x8f420178, 0x00431024, | ||
2327 | 0x1440fffd, 0x8ec2414c, 0x26c4414c, 0x2484ffd4, 0xaf420144, 0x8c820030, | ||
2328 | 0x00001821, 0xaf420148, 0x24020052, 0xaf47014c, 0xa3420152, 0x3c021000, | ||
2329 | 0xa7430158, 0xaf480154, 0xaf420178, 0x8ec5414c, 0x8d230030, 0x8c860030, | ||
2330 | 0x24630001, 0xad230030, 0x93420109, 0x9343010a, 0xafa80014, 0xafa00018, | ||
2331 | 0x00021600, 0x00031c00, 0x00431025, 0x34425200, 0xafa20010, 0x0e000fe1, | ||
2332 | 0x8f440100, 0x0a000cfb, 0x00000000, 0x3c026000, 0x24030100, 0xac43081c, | ||
2333 | 0x3c030001, 0xac43081c, 0x0000000d, 0x00000000, 0x240003cd, 0x16800009, | ||
2334 | 0x3c040800, 0x3c030800, 0x24624120, 0x8c43001c, 0x32500040, 0x2404ffbf, | ||
2335 | 0x00641824, 0x0a000f13, 0xac43001c, 0x8c824120, 0x10400005, 0x3c030800, | ||
2336 | 0x8c620034, 0xac804120, 0x24420001, 0xac620034, 0x9343093f, 0x24020012, | ||
2337 | 0x1462000f, 0x329e0038, 0x17c0000c, 0x3c030800, 0x8f830000, 0x8c62004c, | ||
2338 | 0xac62005c, 0x3c020800, 0x24444120, 0x8c82001c, 0x32500040, 0x2403ffbf, | ||
2339 | 0x00431024, 0x0a000f13, 0xac82001c, 0xac604120, 0x97420908, 0x000211c0, | ||
2340 | 0xaf420024, 0x97420908, 0x3c030080, 0x34630003, 0x000211c0, 0xaf42080c, | ||
2341 | 0xaf43081c, 0x974209ec, 0x8f4309a4, 0xa7820028, 0x3c020800, 0x24444120, | ||
2342 | 0xac830028, 0x93420937, 0x93430934, 0x00021080, 0x00621821, 0xa4830014, | ||
2343 | 0x934209d8, 0x00621821, 0xa4830016, 0x934209d8, 0x93430934, 0x00809821, | ||
2344 | 0x00431021, 0x24420010, 0xa4820012, 0x0000a821, 0x24020006, 0x13c00003, | ||
2345 | 0xae62001c, 0x0a000d82, 0x24120008, 0x8f420958, 0x8f830020, 0x8f84002c, | ||
2346 | 0x00431023, 0x00832023, 0x04800003, 0xae620004, 0x04410003, 0x0082102b, | ||
2347 | 0x0a000d4e, 0xae600004, 0x54400001, 0xae640004, 0x8ee20000, 0x0040f809, | ||
2348 | 0x00000000, 0x00409021, 0x32420001, 0x5440001e, 0x8ee20004, 0x8e630008, | ||
2349 | 0x1060002b, 0x3c02c000, 0x00621025, 0xaf420e00, 0x8f420000, 0x30420008, | ||
2350 | 0x1040fffd, 0x00000000, 0x97420e08, 0xa7820010, 0x8f430e04, 0x8e620008, | ||
2351 | 0xaf830004, 0x8f840004, 0x0044102b, 0x1040000b, 0x24150001, 0x24020100, | ||
2352 | 0x3c016000, 0xac22081c, 0x3c020001, 0x3c016000, 0xac22081c, 0x0000000d, | ||
2353 | 0x00000000, 0x24000449, 0x24150001, 0x8ee20004, 0x0040f809, 0x00000000, | ||
2354 | 0x02429025, 0x32420002, 0x5040001d, 0x8f470940, 0x12a00006, 0x8ec2414c, | ||
2355 | 0x8f830000, 0xac6200a8, 0x8f840000, 0x8e620030, 0xac8200ac, 0x32420004, | ||
2356 | 0x50400013, 0x8f470940, 0x3c020800, 0x3283007d, 0x106000fe, 0x245741b0, | ||
2357 | 0x32820001, 0x50400006, 0x36520002, 0x8f830030, 0x8f420940, 0x106200f7, | ||
2358 | 0x00000000, 0x36520002, 0x24020008, 0xa660000c, 0xa662000e, 0xae600008, | ||
2359 | 0xa2600020, 0x8f470940, 0x3c030800, 0x24684120, 0x8d020028, 0x8d050008, | ||
2360 | 0x9504000c, 0x9506000a, 0x95030022, 0x00451021, 0x00862021, 0x00641821, | ||
2361 | 0xaf870030, 0xad020028, 0x32820030, 0x10400006, 0xa5030010, 0x91020020, | ||
2362 | 0x32910040, 0x34420004, 0x0a000dd4, 0xa1020020, 0x93420923, 0x30420040, | ||
2363 | 0x10400029, 0x32910040, 0x8f830000, 0x8f840020, 0x8c620084, 0x00441023, | ||
2364 | 0x0442000a, 0x3c039000, 0x95020010, 0x8c630084, 0x00821021, 0x00621823, | ||
2365 | 0x1c600004, 0x3c039000, 0x91020020, 0x34420001, 0xa1020020, 0x34630001, | ||
2366 | 0x8f820008, 0x32910040, 0x3c048000, 0x00431025, 0xaf420020, 0x8f420020, | ||
2367 | 0x00441024, 0x1440fffd, 0x00000000, 0x8f840000, 0x9083003f, 0x2402000a, | ||
2368 | 0x10620005, 0x2402000c, 0x9083003f, 0x24020008, 0x14620002, 0x24020014, | ||
2369 | 0xa082003f, 0x8f830008, 0x3c028000, 0x34420001, 0x00621825, 0xaf430020, | ||
2370 | 0x3c040800, 0x24904120, 0x9602000c, 0x96030016, 0x9604000e, 0x00431021, | ||
2371 | 0x00442021, 0x24840002, 0x3084ffff, 0x0e000a55, 0xa6020018, 0x8f850018, | ||
2372 | 0x00a01821, 0xa2030021, 0x8ee60008, 0x00402021, 0x24a50001, 0xaf850018, | ||
2373 | 0x00c0f809, 0x00000000, 0x00402021, 0x0e000b12, 0x02202821, 0x8ee3000c, | ||
2374 | 0x0060f809, 0x00402021, 0x96040018, 0x9602000e, 0x00822021, 0x24840002, | ||
2375 | 0x0e000a6b, 0x3084ffff, 0x3c030800, 0x8c624120, 0x8e030008, 0x3c040800, | ||
2376 | 0x00431023, 0x14400012, 0xac824120, 0x54600006, 0x8e02001c, 0x3243004a, | ||
2377 | 0x24020002, 0x14620005, 0x00000000, 0x8e02001c, 0x34420040, 0x0a000e0b, | ||
2378 | 0xae02001c, 0x52a00006, 0x36520002, 0x8e02002c, 0xaf420e10, 0x8e030030, | ||
2379 | 0xaf430e18, 0x36520002, 0x52a00008, 0x96670010, 0x8f830000, 0x8f420e10, | ||
2380 | 0xac6200a8, 0x8f840000, 0x8f420e18, 0xac8200ac, 0x96670010, 0x92680020, | ||
2381 | 0x24020040, 0xaf420814, 0x8f830020, 0x8f82001c, 0x00671821, 0x00621023, | ||
2382 | 0xaf830020, 0x58400005, 0x8f42095c, 0x8f820000, 0xaf83001c, 0xac430054, | ||
2383 | 0x8f42095c, 0x31030008, 0xaf82002c, 0x1060001a, 0x00000000, 0x8f840000, | ||
2384 | 0x90820120, 0x90830121, 0x304600ff, 0x00c31823, 0x30630007, 0x24020007, | ||
2385 | 0x1062000e, 0x00000000, 0x90820122, 0x304200fe, 0xa0820122, 0x8f850000, | ||
2386 | 0x00061880, 0x8f840020, 0x24a20100, 0x00431021, 0x24c30001, 0x30630007, | ||
2387 | 0xac440000, 0x0a000e40, 0xa0a30120, 0x90820122, 0x34420001, 0xa0820122, | ||
2388 | 0x14e00003, 0x31020001, 0x10400031, 0x32510002, 0x8f820000, 0x8c43000c, | ||
2389 | 0x30630001, 0x1060002c, 0x32510002, 0x3c029000, 0x8f830008, 0x34420001, | ||
2390 | 0x3c048000, 0x00621825, 0xaf430020, 0x8f420020, 0x00441024, 0x1440fffd, | ||
2391 | 0x00000000, 0x8f870000, 0x8ce2000c, 0x30420001, 0x10400018, 0x00000000, | ||
2392 | 0x94e2006a, 0x00022880, 0x50a00001, 0x24050001, 0x94e30068, 0x90e40081, | ||
2393 | 0x3c020800, 0x8c460024, 0x00652821, 0x00852804, 0x00c5102b, 0x54400001, | ||
2394 | 0x00a03021, 0x3c020800, 0x8c440028, 0x00c4182b, 0x54600001, 0x00c02021, | ||
2395 | 0x8f430074, 0x2402fffe, 0x00822824, 0x00a31821, 0xace3000c, 0x8f830008, | ||
2396 | 0x3c028000, 0x34420001, 0x00621825, 0xaf430020, 0x8f830020, 0x3c020800, | ||
2397 | 0x24504120, 0xae030024, 0x8ee20010, 0x0040f809, 0x00000000, 0x12a00005, | ||
2398 | 0x00000000, 0x8f420e10, 0xae02002c, 0x8f430e18, 0xae030030, 0x1220feba, | ||
2399 | 0x0000a821, 0x8f870024, 0x97860028, 0x8f830000, 0x8f820030, 0x8f840020, | ||
2400 | 0x8f85001c, 0x32500040, 0xa4e6002c, 0xac620044, 0x32420008, 0xac640050, | ||
2401 | 0xac650054, 0x1040007a, 0x32820020, 0x10400027, 0x32910010, 0x24072000, | ||
2402 | 0x3c090800, 0x3c038000, 0x8f420178, 0x00431024, 0x1440fffd, 0x8ec2414c, | ||
2403 | 0x26c4414c, 0x2484ffd4, 0xaf420144, 0x8c820030, 0x3c030400, 0xaf420148, | ||
2404 | 0x24020041, 0xaf43014c, 0x00001821, 0xa3420152, 0x3c021000, 0xa7430158, | ||
2405 | 0xaf470154, 0xaf420178, 0x8ec5414c, 0x8d230030, 0x8c860030, 0x24630001, | ||
2406 | 0xad230030, 0x93420109, 0x9343010a, 0xafa70014, 0xafa00018, 0x00021600, | ||
2407 | 0x00031c00, 0x00431025, 0x34424100, 0xafa20010, 0x8f440100, 0x0e000fe1, | ||
2408 | 0x3c070400, 0x12200028, 0x24072000, 0x3c090800, 0x3c038000, 0x8f420178, | ||
2409 | 0x00431024, 0x1440fffd, 0x8ec2414c, 0x26c4414c, 0x2484ffd4, 0xaf420144, | ||
2410 | 0x8c820030, 0x3c030300, 0xaf420148, 0x2402004e, 0xaf43014c, 0x00001821, | ||
2411 | 0xa3420152, 0x3c021000, 0xa7430158, 0xaf470154, 0xaf420178, 0x8ec5414c, | ||
2412 | 0x8d230030, 0x8c860030, 0x24630001, 0xad230030, 0x93420109, 0x9343010a, | ||
2413 | 0xafa70014, 0xafa00018, 0x00021600, 0x00031c00, 0x00431025, 0x34424e00, | ||
2414 | 0xafa20010, 0x8f440100, 0x0e000fe1, 0x3c070300, 0x0a000f0b, 0x8fa30024, | ||
2415 | 0x32820008, 0x10400026, 0x3c090800, 0x24072000, 0x3c038000, 0x8f420178, | ||
2416 | 0x00431024, 0x1440fffd, 0x8ec2414c, 0x26c4414c, 0x2484ffd4, 0xaf420144, | ||
2417 | 0x8c820030, 0x3c030200, 0xaf420148, 0x2402004b, 0xaf43014c, 0x00001821, | ||
2418 | 0xa3420152, 0x3c021000, 0xa7430158, 0xaf470154, 0xaf420178, 0x8ec5414c, | ||
2419 | 0x8d230030, 0x8c860030, 0x24630001, 0xad230030, 0x93420109, 0x9343010a, | ||
2420 | 0xafa70014, 0xafa00018, 0x00021600, 0x00031c00, 0x00431025, 0x34424b00, | ||
2421 | 0xafa20010, 0x8f440100, 0x0e000fe1, 0x3c070200, 0x8fa30024, 0x14600004, | ||
2422 | 0x8fa40020, 0x32420010, 0x10400004, 0x00000000, 0x8c820004, 0x0040f809, | ||
2423 | 0x00000000, 0x12000006, 0x8fa30020, 0x8c620008, 0x0040f809, 0x00000000, | ||
2424 | 0x0a000f4d, 0x8fbf004c, 0x3c030800, 0x8c62413c, 0x30420040, 0x1440002f, | ||
2425 | 0x8fbf004c, 0x24040040, 0x8f910020, 0x3c038000, 0x8f420178, 0x00431024, | ||
2426 | 0x1440fffd, 0x8ec2414c, 0x26d0414c, 0x2610ffd4, 0xaf420144, 0x8e020030, | ||
2427 | 0x00001821, 0xaf420148, 0x24020049, 0xaf51014c, 0xa3420152, 0x3c021000, | ||
2428 | 0xa7430158, 0xaf440154, 0xaf420178, 0x8ec5414c, 0x8e060030, 0x93420109, | ||
2429 | 0x9343010a, 0xafa40014, 0xafa00018, 0x00021600, 0x00031c00, 0x00431025, | ||
2430 | 0x34424900, 0xafa20010, 0x8f440100, 0x0e000fe1, 0x02203821, 0x8f830000, | ||
2431 | 0x8e020030, 0x8c64017c, 0x02221023, 0x00441023, 0x2c420002, 0x14400005, | ||
2432 | 0x8fbf004c, 0x0000000d, 0x00000000, 0x240000ca, 0x8fbf004c, 0x8fbe0048, | ||
2433 | 0x8fb70044, 0x8fb60040, 0x8fb5003c, 0x8fb40038, 0x8fb30034, 0x8fb20030, | ||
2434 | 0x8fb1002c, 0x8fb00028, 0x03e00008, 0x27bd0050, 0x03e00008, 0x00001021, | ||
2435 | 0x3c030800, 0x24654120, 0x8ca40004, 0x8c634120, 0x0064102b, 0x54400001, | ||
2436 | 0x00602021, 0x9743093c, 0x0083102b, 0x54400001, 0x00801821, 0x00001021, | ||
2437 | 0xaca30008, 0x03e00008, 0xa4a00022, 0x8f850004, 0x97840010, 0x3c030800, | ||
2438 | 0x24634120, 0x24020008, 0xa462000e, 0x8f820004, 0xa460000c, 0x000420c2, | ||
2439 | 0x30840008, 0x2c420001, 0x00021023, 0x30420006, 0xac650008, 0x03e00008, | ||
2440 | 0xa0640020, 0x3c020800, 0x24424120, 0x90450021, 0x94430018, 0x3c021100, | ||
2441 | 0xac800004, 0x00052c00, 0x24630002, 0x00621825, 0x00a32825, 0x24820008, | ||
2442 | 0x03e00008, 0xac850000, 0x0000000d, 0x00000000, 0x2400016f, 0x03e00008, | ||
2443 | 0x00000000, 0x0000000d, 0x00000000, 0x2400017b, 0x03e00008, 0x00000000, | ||
2444 | 0x03e00008, 0x00000000, 0x3c020800, 0x24424120, 0xac400008, 0xa4400022, | ||
2445 | 0x03e00008, 0x24020001, 0x3c020800, 0x24424120, 0x24030008, 0xac400008, | ||
2446 | 0xa440000c, 0xa443000e, 0xa0400020, 0x03e00008, 0x24020004, 0x03e00008, | ||
2447 | 0x00001021, 0x10c00007, 0x00000000, 0x8ca20000, 0x24c6ffff, 0x24a50004, | ||
2448 | 0xac820000, 0x14c0fffb, 0x24840004, 0x03e00008, 0x00000000, 0x0a000fb2, | ||
2449 | 0x00a01021, 0xac860000, 0x24840004, 0x00a01021, 0x1440fffc, 0x24a5ffff, | ||
2450 | 0x03e00008, 0x00000000, 0x3c0a0800, 0x8d490068, 0x3c050800, 0x24a51090, | ||
2451 | 0x00093140, 0x00c51021, 0xac440000, 0x8f440e04, 0x00a61021, 0xac440004, | ||
2452 | 0x97430e08, 0x97420e0c, 0x00a62021, 0x00031c00, 0x00431025, 0xac820008, | ||
2453 | 0x8f430e10, 0x00801021, 0xac43000c, 0x8f440e14, 0xac440010, 0x8f430e18, | ||
2454 | 0x3c0800ff, 0xac430014, 0x8f470e1c, 0x3508ffff, 0x25290001, 0xac470018, | ||
2455 | 0x3c070800, 0x8ce3006c, 0x9344010a, 0x3c026000, 0x24630001, 0xace3006c, | ||
2456 | 0x8c434448, 0x3129007f, 0x00a62821, 0xad490068, 0x00042600, 0x00681824, | ||
2457 | 0x00832025, 0x03e00008, 0xaca4001c, 0x8fac0010, 0x8fad0014, 0x8fae0018, | ||
2458 | 0x3c0b0800, 0x8d6a0060, 0x3c080800, 0x25080078, 0x000a4940, 0x01281021, | ||
2459 | 0x01091821, 0xac440000, 0x00601021, 0xac650004, 0xac460008, 0xac67000c, | ||
2460 | 0xac4c0010, 0xac6d0014, 0x3c036000, 0xac4e0018, 0x8c654448, 0x3c040800, | ||
2461 | 0x8c820064, 0x254a0001, 0x314a007f, 0x01094021, 0xad6a0060, 0x24420001, | ||
2462 | 0xac820064, 0x03e00008, 0xad05001c, 0x00000000 }; | ||
2463 | |||
2464 | static u32 bnx2_TXP_b06FwData[(0x0/4) + 1] = { 0x00000000 }; | ||
2465 | static u32 bnx2_TXP_b06FwRodata[(0x0/4) + 1] = { 0x00000000 }; | ||
2466 | static u32 bnx2_TXP_b06FwBss[(0x194/4) + 1] = { 0x00000000 }; | ||
2467 | static u32 bnx2_TXP_b06FwSbss[(0x34/4) + 1] = { 0x00000000 }; | ||
2468 | |||
diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c index 770e28f98fd5..269a5e407349 100644 --- a/drivers/net/bonding/bond_main.c +++ b/drivers/net/bonding/bond_main.c | |||
@@ -3037,7 +3037,7 @@ static void bond_activebackup_arp_mon(struct net_device *bond_dev) | |||
3037 | bond_set_slave_inactive_flags(bond->current_arp_slave); | 3037 | bond_set_slave_inactive_flags(bond->current_arp_slave); |
3038 | 3038 | ||
3039 | /* search for next candidate */ | 3039 | /* search for next candidate */ |
3040 | bond_for_each_slave_from(bond, slave, i, bond->current_arp_slave) { | 3040 | bond_for_each_slave_from(bond, slave, i, bond->current_arp_slave->next) { |
3041 | if (IS_UP(slave->dev)) { | 3041 | if (IS_UP(slave->dev)) { |
3042 | slave->link = BOND_LINK_BACK; | 3042 | slave->link = BOND_LINK_BACK; |
3043 | bond_set_slave_active_flags(slave); | 3043 | bond_set_slave_active_flags(slave); |
diff --git a/drivers/net/e100.c b/drivers/net/e100.c index 1b68dd5a49b6..4a47df5a9ff9 100644 --- a/drivers/net/e100.c +++ b/drivers/net/e100.c | |||
@@ -155,9 +155,9 @@ | |||
155 | 155 | ||
156 | #define DRV_NAME "e100" | 156 | #define DRV_NAME "e100" |
157 | #define DRV_EXT "-NAPI" | 157 | #define DRV_EXT "-NAPI" |
158 | #define DRV_VERSION "3.3.6-k2"DRV_EXT | 158 | #define DRV_VERSION "3.4.8-k2"DRV_EXT |
159 | #define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver" | 159 | #define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver" |
160 | #define DRV_COPYRIGHT "Copyright(c) 1999-2004 Intel Corporation" | 160 | #define DRV_COPYRIGHT "Copyright(c) 1999-2005 Intel Corporation" |
161 | #define PFX DRV_NAME ": " | 161 | #define PFX DRV_NAME ": " |
162 | 162 | ||
163 | #define E100_WATCHDOG_PERIOD (2 * HZ) | 163 | #define E100_WATCHDOG_PERIOD (2 * HZ) |
@@ -210,11 +210,17 @@ static struct pci_device_id e100_id_table[] = { | |||
210 | INTEL_8255X_ETHERNET_DEVICE(0x1069, 6), | 210 | INTEL_8255X_ETHERNET_DEVICE(0x1069, 6), |
211 | INTEL_8255X_ETHERNET_DEVICE(0x106A, 6), | 211 | INTEL_8255X_ETHERNET_DEVICE(0x106A, 6), |
212 | INTEL_8255X_ETHERNET_DEVICE(0x106B, 6), | 212 | INTEL_8255X_ETHERNET_DEVICE(0x106B, 6), |
213 | INTEL_8255X_ETHERNET_DEVICE(0x1091, 7), | ||
214 | INTEL_8255X_ETHERNET_DEVICE(0x1092, 7), | ||
215 | INTEL_8255X_ETHERNET_DEVICE(0x1093, 7), | ||
216 | INTEL_8255X_ETHERNET_DEVICE(0x1094, 7), | ||
217 | INTEL_8255X_ETHERNET_DEVICE(0x1095, 7), | ||
213 | INTEL_8255X_ETHERNET_DEVICE(0x1209, 0), | 218 | INTEL_8255X_ETHERNET_DEVICE(0x1209, 0), |
214 | INTEL_8255X_ETHERNET_DEVICE(0x1229, 0), | 219 | INTEL_8255X_ETHERNET_DEVICE(0x1229, 0), |
215 | INTEL_8255X_ETHERNET_DEVICE(0x2449, 2), | 220 | INTEL_8255X_ETHERNET_DEVICE(0x2449, 2), |
216 | INTEL_8255X_ETHERNET_DEVICE(0x2459, 2), | 221 | INTEL_8255X_ETHERNET_DEVICE(0x2459, 2), |
217 | INTEL_8255X_ETHERNET_DEVICE(0x245D, 2), | 222 | INTEL_8255X_ETHERNET_DEVICE(0x245D, 2), |
223 | INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7), | ||
218 | { 0, } | 224 | { 0, } |
219 | }; | 225 | }; |
220 | MODULE_DEVICE_TABLE(pci, e100_id_table); | 226 | MODULE_DEVICE_TABLE(pci, e100_id_table); |
@@ -269,6 +275,12 @@ enum scb_status { | |||
269 | rus_mask = 0x3C, | 275 | rus_mask = 0x3C, |
270 | }; | 276 | }; |
271 | 277 | ||
278 | enum ru_state { | ||
279 | RU_SUSPENDED = 0, | ||
280 | RU_RUNNING = 1, | ||
281 | RU_UNINITIALIZED = -1, | ||
282 | }; | ||
283 | |||
272 | enum scb_stat_ack { | 284 | enum scb_stat_ack { |
273 | stat_ack_not_ours = 0x00, | 285 | stat_ack_not_ours = 0x00, |
274 | stat_ack_sw_gen = 0x04, | 286 | stat_ack_sw_gen = 0x04, |
@@ -510,7 +522,7 @@ struct nic { | |||
510 | struct rx *rx_to_use; | 522 | struct rx *rx_to_use; |
511 | struct rx *rx_to_clean; | 523 | struct rx *rx_to_clean; |
512 | struct rfd blank_rfd; | 524 | struct rfd blank_rfd; |
513 | int ru_running; | 525 | enum ru_state ru_running; |
514 | 526 | ||
515 | spinlock_t cb_lock ____cacheline_aligned; | 527 | spinlock_t cb_lock ____cacheline_aligned; |
516 | spinlock_t cmd_lock; | 528 | spinlock_t cmd_lock; |
@@ -539,6 +551,7 @@ struct nic { | |||
539 | struct timer_list watchdog; | 551 | struct timer_list watchdog; |
540 | struct timer_list blink_timer; | 552 | struct timer_list blink_timer; |
541 | struct mii_if_info mii; | 553 | struct mii_if_info mii; |
554 | struct work_struct tx_timeout_task; | ||
542 | enum loopback loopback; | 555 | enum loopback loopback; |
543 | 556 | ||
544 | struct mem *mem; | 557 | struct mem *mem; |
@@ -770,7 +783,7 @@ static int e100_eeprom_save(struct nic *nic, u16 start, u16 count) | |||
770 | return 0; | 783 | return 0; |
771 | } | 784 | } |
772 | 785 | ||
773 | #define E100_WAIT_SCB_TIMEOUT 40 | 786 | #define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */ |
774 | static inline int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr) | 787 | static inline int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr) |
775 | { | 788 | { |
776 | unsigned long flags; | 789 | unsigned long flags; |
@@ -840,6 +853,10 @@ static inline int e100_exec_cb(struct nic *nic, struct sk_buff *skb, | |||
840 | * because the controller is too busy, so | 853 | * because the controller is too busy, so |
841 | * let's just queue the command and try again | 854 | * let's just queue the command and try again |
842 | * when another command is scheduled. */ | 855 | * when another command is scheduled. */ |
856 | if(err == -ENOSPC) { | ||
857 | //request a reset | ||
858 | schedule_work(&nic->tx_timeout_task); | ||
859 | } | ||
843 | break; | 860 | break; |
844 | } else { | 861 | } else { |
845 | nic->cuc_cmd = cuc_resume; | 862 | nic->cuc_cmd = cuc_resume; |
@@ -884,7 +901,7 @@ static void mdio_write(struct net_device *netdev, int addr, int reg, int data) | |||
884 | 901 | ||
885 | static void e100_get_defaults(struct nic *nic) | 902 | static void e100_get_defaults(struct nic *nic) |
886 | { | 903 | { |
887 | struct param_range rfds = { .min = 64, .max = 256, .count = 64 }; | 904 | struct param_range rfds = { .min = 16, .max = 256, .count = 64 }; |
888 | struct param_range cbs = { .min = 64, .max = 256, .count = 64 }; | 905 | struct param_range cbs = { .min = 64, .max = 256, .count = 64 }; |
889 | 906 | ||
890 | pci_read_config_byte(nic->pdev, PCI_REVISION_ID, &nic->rev_id); | 907 | pci_read_config_byte(nic->pdev, PCI_REVISION_ID, &nic->rev_id); |
@@ -899,8 +916,9 @@ static void e100_get_defaults(struct nic *nic) | |||
899 | /* Quadwords to DMA into FIFO before starting frame transmit */ | 916 | /* Quadwords to DMA into FIFO before starting frame transmit */ |
900 | nic->tx_threshold = 0xE0; | 917 | nic->tx_threshold = 0xE0; |
901 | 918 | ||
902 | nic->tx_command = cpu_to_le16(cb_tx | cb_i | cb_tx_sf | | 919 | /* no interrupt for every tx completion, delay = 256us if not 557*/ |
903 | ((nic->mac >= mac_82558_D101_A4) ? cb_cid : 0)); | 920 | nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf | |
921 | ((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i)); | ||
904 | 922 | ||
905 | /* Template for a freshly allocated RFD */ | 923 | /* Template for a freshly allocated RFD */ |
906 | nic->blank_rfd.command = cpu_to_le16(cb_el); | 924 | nic->blank_rfd.command = cpu_to_le16(cb_el); |
@@ -964,7 +982,8 @@ static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb) | |||
964 | if(nic->flags & multicast_all) | 982 | if(nic->flags & multicast_all) |
965 | config->multicast_all = 0x1; /* 1=accept, 0=no */ | 983 | config->multicast_all = 0x1; /* 1=accept, 0=no */ |
966 | 984 | ||
967 | if(!(nic->flags & wol_magic)) | 985 | /* disable WoL when up */ |
986 | if(netif_running(nic->netdev) || !(nic->flags & wol_magic)) | ||
968 | config->magic_packet_disable = 0x1; /* 1=off, 0=on */ | 987 | config->magic_packet_disable = 0x1; /* 1=off, 0=on */ |
969 | 988 | ||
970 | if(nic->mac >= mac_82558_D101_A4) { | 989 | if(nic->mac >= mac_82558_D101_A4) { |
@@ -1203,7 +1222,9 @@ static void e100_update_stats(struct nic *nic) | |||
1203 | } | 1222 | } |
1204 | } | 1223 | } |
1205 | 1224 | ||
1206 | e100_exec_cmd(nic, cuc_dump_reset, 0); | 1225 | |
1226 | if(e100_exec_cmd(nic, cuc_dump_reset, 0)) | ||
1227 | DPRINTK(TX_ERR, DEBUG, "exec cuc_dump_reset failed\n"); | ||
1207 | } | 1228 | } |
1208 | 1229 | ||
1209 | static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex) | 1230 | static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex) |
@@ -1279,12 +1300,15 @@ static inline void e100_xmit_prepare(struct nic *nic, struct cb *cb, | |||
1279 | struct sk_buff *skb) | 1300 | struct sk_buff *skb) |
1280 | { | 1301 | { |
1281 | cb->command = nic->tx_command; | 1302 | cb->command = nic->tx_command; |
1303 | /* interrupt every 16 packets regardless of delay */ | ||
1304 | if((nic->cbs_avail & ~15) == nic->cbs_avail) cb->command |= cb_i; | ||
1282 | cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd); | 1305 | cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd); |
1283 | cb->u.tcb.tcb_byte_count = 0; | 1306 | cb->u.tcb.tcb_byte_count = 0; |
1284 | cb->u.tcb.threshold = nic->tx_threshold; | 1307 | cb->u.tcb.threshold = nic->tx_threshold; |
1285 | cb->u.tcb.tbd_count = 1; | 1308 | cb->u.tcb.tbd_count = 1; |
1286 | cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev, | 1309 | cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev, |
1287 | skb->data, skb->len, PCI_DMA_TODEVICE)); | 1310 | skb->data, skb->len, PCI_DMA_TODEVICE)); |
1311 | // check for mapping failure? | ||
1288 | cb->u.tcb.tbd.size = cpu_to_le16(skb->len); | 1312 | cb->u.tcb.tbd.size = cpu_to_le16(skb->len); |
1289 | } | 1313 | } |
1290 | 1314 | ||
@@ -1297,7 +1321,8 @@ static int e100_xmit_frame(struct sk_buff *skb, struct net_device *netdev) | |||
1297 | /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang. | 1321 | /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang. |
1298 | Issue a NOP command followed by a 1us delay before | 1322 | Issue a NOP command followed by a 1us delay before |
1299 | issuing the Tx command. */ | 1323 | issuing the Tx command. */ |
1300 | e100_exec_cmd(nic, cuc_nop, 0); | 1324 | if(e100_exec_cmd(nic, cuc_nop, 0)) |
1325 | DPRINTK(TX_ERR, DEBUG, "exec cuc_nop failed\n"); | ||
1301 | udelay(1); | 1326 | udelay(1); |
1302 | } | 1327 | } |
1303 | 1328 | ||
@@ -1415,12 +1440,18 @@ static int e100_alloc_cbs(struct nic *nic) | |||
1415 | return 0; | 1440 | return 0; |
1416 | } | 1441 | } |
1417 | 1442 | ||
1418 | static inline void e100_start_receiver(struct nic *nic) | 1443 | static inline void e100_start_receiver(struct nic *nic, struct rx *rx) |
1419 | { | 1444 | { |
1445 | if(!nic->rxs) return; | ||
1446 | if(RU_SUSPENDED != nic->ru_running) return; | ||
1447 | |||
1448 | /* handle init time starts */ | ||
1449 | if(!rx) rx = nic->rxs; | ||
1450 | |||
1420 | /* (Re)start RU if suspended or idle and RFA is non-NULL */ | 1451 | /* (Re)start RU if suspended or idle and RFA is non-NULL */ |
1421 | if(!nic->ru_running && nic->rx_to_clean->skb) { | 1452 | if(rx->skb) { |
1422 | e100_exec_cmd(nic, ruc_start, nic->rx_to_clean->dma_addr); | 1453 | e100_exec_cmd(nic, ruc_start, rx->dma_addr); |
1423 | nic->ru_running = 1; | 1454 | nic->ru_running = RU_RUNNING; |
1424 | } | 1455 | } |
1425 | } | 1456 | } |
1426 | 1457 | ||
@@ -1437,6 +1468,13 @@ static inline int e100_rx_alloc_skb(struct nic *nic, struct rx *rx) | |||
1437 | rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data, | 1468 | rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data, |
1438 | RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL); | 1469 | RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL); |
1439 | 1470 | ||
1471 | if(pci_dma_mapping_error(rx->dma_addr)) { | ||
1472 | dev_kfree_skb_any(rx->skb); | ||
1473 | rx->skb = 0; | ||
1474 | rx->dma_addr = 0; | ||
1475 | return -ENOMEM; | ||
1476 | } | ||
1477 | |||
1440 | /* Link the RFD to end of RFA by linking previous RFD to | 1478 | /* Link the RFD to end of RFA by linking previous RFD to |
1441 | * this one, and clearing EL bit of previous. */ | 1479 | * this one, and clearing EL bit of previous. */ |
1442 | if(rx->prev->skb) { | 1480 | if(rx->prev->skb) { |
@@ -1471,7 +1509,7 @@ static inline int e100_rx_indicate(struct nic *nic, struct rx *rx, | |||
1471 | 1509 | ||
1472 | /* If data isn't ready, nothing to indicate */ | 1510 | /* If data isn't ready, nothing to indicate */ |
1473 | if(unlikely(!(rfd_status & cb_complete))) | 1511 | if(unlikely(!(rfd_status & cb_complete))) |
1474 | return -EAGAIN; | 1512 | return -ENODATA; |
1475 | 1513 | ||
1476 | /* Get actual data size */ | 1514 | /* Get actual data size */ |
1477 | actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF; | 1515 | actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF; |
@@ -1482,6 +1520,10 @@ static inline int e100_rx_indicate(struct nic *nic, struct rx *rx, | |||
1482 | pci_unmap_single(nic->pdev, rx->dma_addr, | 1520 | pci_unmap_single(nic->pdev, rx->dma_addr, |
1483 | RFD_BUF_LEN, PCI_DMA_FROMDEVICE); | 1521 | RFD_BUF_LEN, PCI_DMA_FROMDEVICE); |
1484 | 1522 | ||
1523 | /* this allows for a fast restart without re-enabling interrupts */ | ||
1524 | if(le16_to_cpu(rfd->command) & cb_el) | ||
1525 | nic->ru_running = RU_SUSPENDED; | ||
1526 | |||
1485 | /* Pull off the RFD and put the actual data (minus eth hdr) */ | 1527 | /* Pull off the RFD and put the actual data (minus eth hdr) */ |
1486 | skb_reserve(skb, sizeof(struct rfd)); | 1528 | skb_reserve(skb, sizeof(struct rfd)); |
1487 | skb_put(skb, actual_size); | 1529 | skb_put(skb, actual_size); |
@@ -1514,20 +1556,45 @@ static inline void e100_rx_clean(struct nic *nic, unsigned int *work_done, | |||
1514 | unsigned int work_to_do) | 1556 | unsigned int work_to_do) |
1515 | { | 1557 | { |
1516 | struct rx *rx; | 1558 | struct rx *rx; |
1559 | int restart_required = 0; | ||
1560 | struct rx *rx_to_start = NULL; | ||
1561 | |||
1562 | /* are we already rnr? then pay attention!!! this ensures that | ||
1563 | * the state machine progression never allows a start with a | ||
1564 | * partially cleaned list, avoiding a race between hardware | ||
1565 | * and rx_to_clean when in NAPI mode */ | ||
1566 | if(RU_SUSPENDED == nic->ru_running) | ||
1567 | restart_required = 1; | ||
1517 | 1568 | ||
1518 | /* Indicate newly arrived packets */ | 1569 | /* Indicate newly arrived packets */ |
1519 | for(rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) { | 1570 | for(rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) { |
1520 | if(e100_rx_indicate(nic, rx, work_done, work_to_do)) | 1571 | int err = e100_rx_indicate(nic, rx, work_done, work_to_do); |
1572 | if(-EAGAIN == err) { | ||
1573 | /* hit quota so have more work to do, restart once | ||
1574 | * cleanup is complete */ | ||
1575 | restart_required = 0; | ||
1576 | break; | ||
1577 | } else if(-ENODATA == err) | ||
1521 | break; /* No more to clean */ | 1578 | break; /* No more to clean */ |
1522 | } | 1579 | } |
1523 | 1580 | ||
1581 | /* save our starting point as the place we'll restart the receiver */ | ||
1582 | if(restart_required) | ||
1583 | rx_to_start = nic->rx_to_clean; | ||
1584 | |||
1524 | /* Alloc new skbs to refill list */ | 1585 | /* Alloc new skbs to refill list */ |
1525 | for(rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) { | 1586 | for(rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) { |
1526 | if(unlikely(e100_rx_alloc_skb(nic, rx))) | 1587 | if(unlikely(e100_rx_alloc_skb(nic, rx))) |
1527 | break; /* Better luck next time (see watchdog) */ | 1588 | break; /* Better luck next time (see watchdog) */ |
1528 | } | 1589 | } |
1529 | 1590 | ||
1530 | e100_start_receiver(nic); | 1591 | if(restart_required) { |
1592 | // ack the rnr? | ||
1593 | writeb(stat_ack_rnr, &nic->csr->scb.stat_ack); | ||
1594 | e100_start_receiver(nic, rx_to_start); | ||
1595 | if(work_done) | ||
1596 | (*work_done)++; | ||
1597 | } | ||
1531 | } | 1598 | } |
1532 | 1599 | ||
1533 | static void e100_rx_clean_list(struct nic *nic) | 1600 | static void e100_rx_clean_list(struct nic *nic) |
@@ -1535,6 +1602,8 @@ static void e100_rx_clean_list(struct nic *nic) | |||
1535 | struct rx *rx; | 1602 | struct rx *rx; |
1536 | unsigned int i, count = nic->params.rfds.count; | 1603 | unsigned int i, count = nic->params.rfds.count; |
1537 | 1604 | ||
1605 | nic->ru_running = RU_UNINITIALIZED; | ||
1606 | |||
1538 | if(nic->rxs) { | 1607 | if(nic->rxs) { |
1539 | for(rx = nic->rxs, i = 0; i < count; rx++, i++) { | 1608 | for(rx = nic->rxs, i = 0; i < count; rx++, i++) { |
1540 | if(rx->skb) { | 1609 | if(rx->skb) { |
@@ -1548,7 +1617,6 @@ static void e100_rx_clean_list(struct nic *nic) | |||
1548 | } | 1617 | } |
1549 | 1618 | ||
1550 | nic->rx_to_use = nic->rx_to_clean = NULL; | 1619 | nic->rx_to_use = nic->rx_to_clean = NULL; |
1551 | nic->ru_running = 0; | ||
1552 | } | 1620 | } |
1553 | 1621 | ||
1554 | static int e100_rx_alloc_list(struct nic *nic) | 1622 | static int e100_rx_alloc_list(struct nic *nic) |
@@ -1557,6 +1625,7 @@ static int e100_rx_alloc_list(struct nic *nic) | |||
1557 | unsigned int i, count = nic->params.rfds.count; | 1625 | unsigned int i, count = nic->params.rfds.count; |
1558 | 1626 | ||
1559 | nic->rx_to_use = nic->rx_to_clean = NULL; | 1627 | nic->rx_to_use = nic->rx_to_clean = NULL; |
1628 | nic->ru_running = RU_UNINITIALIZED; | ||
1560 | 1629 | ||
1561 | if(!(nic->rxs = kmalloc(sizeof(struct rx) * count, GFP_ATOMIC))) | 1630 | if(!(nic->rxs = kmalloc(sizeof(struct rx) * count, GFP_ATOMIC))) |
1562 | return -ENOMEM; | 1631 | return -ENOMEM; |
@@ -1572,6 +1641,7 @@ static int e100_rx_alloc_list(struct nic *nic) | |||
1572 | } | 1641 | } |
1573 | 1642 | ||
1574 | nic->rx_to_use = nic->rx_to_clean = nic->rxs; | 1643 | nic->rx_to_use = nic->rx_to_clean = nic->rxs; |
1644 | nic->ru_running = RU_SUSPENDED; | ||
1575 | 1645 | ||
1576 | return 0; | 1646 | return 0; |
1577 | } | 1647 | } |
@@ -1593,7 +1663,7 @@ static irqreturn_t e100_intr(int irq, void *dev_id, struct pt_regs *regs) | |||
1593 | 1663 | ||
1594 | /* We hit Receive No Resource (RNR); restart RU after cleaning */ | 1664 | /* We hit Receive No Resource (RNR); restart RU after cleaning */ |
1595 | if(stat_ack & stat_ack_rnr) | 1665 | if(stat_ack & stat_ack_rnr) |
1596 | nic->ru_running = 0; | 1666 | nic->ru_running = RU_SUSPENDED; |
1597 | 1667 | ||
1598 | e100_disable_irq(nic); | 1668 | e100_disable_irq(nic); |
1599 | netif_rx_schedule(netdev); | 1669 | netif_rx_schedule(netdev); |
@@ -1663,6 +1733,7 @@ static int e100_change_mtu(struct net_device *netdev, int new_mtu) | |||
1663 | return 0; | 1733 | return 0; |
1664 | } | 1734 | } |
1665 | 1735 | ||
1736 | #ifdef CONFIG_PM | ||
1666 | static int e100_asf(struct nic *nic) | 1737 | static int e100_asf(struct nic *nic) |
1667 | { | 1738 | { |
1668 | /* ASF can be enabled from eeprom */ | 1739 | /* ASF can be enabled from eeprom */ |
@@ -1671,6 +1742,7 @@ static int e100_asf(struct nic *nic) | |||
1671 | !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) && | 1742 | !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) && |
1672 | ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE)); | 1743 | ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE)); |
1673 | } | 1744 | } |
1745 | #endif | ||
1674 | 1746 | ||
1675 | static int e100_up(struct nic *nic) | 1747 | static int e100_up(struct nic *nic) |
1676 | { | 1748 | { |
@@ -1683,13 +1755,16 @@ static int e100_up(struct nic *nic) | |||
1683 | if((err = e100_hw_init(nic))) | 1755 | if((err = e100_hw_init(nic))) |
1684 | goto err_clean_cbs; | 1756 | goto err_clean_cbs; |
1685 | e100_set_multicast_list(nic->netdev); | 1757 | e100_set_multicast_list(nic->netdev); |
1686 | e100_start_receiver(nic); | 1758 | e100_start_receiver(nic, 0); |
1687 | mod_timer(&nic->watchdog, jiffies); | 1759 | mod_timer(&nic->watchdog, jiffies); |
1688 | if((err = request_irq(nic->pdev->irq, e100_intr, SA_SHIRQ, | 1760 | if((err = request_irq(nic->pdev->irq, e100_intr, SA_SHIRQ, |
1689 | nic->netdev->name, nic->netdev))) | 1761 | nic->netdev->name, nic->netdev))) |
1690 | goto err_no_irq; | 1762 | goto err_no_irq; |
1691 | e100_enable_irq(nic); | ||
1692 | netif_wake_queue(nic->netdev); | 1763 | netif_wake_queue(nic->netdev); |
1764 | netif_poll_enable(nic->netdev); | ||
1765 | /* enable ints _after_ enabling poll, preventing a race between | ||
1766 | * disable ints+schedule */ | ||
1767 | e100_enable_irq(nic); | ||
1693 | return 0; | 1768 | return 0; |
1694 | 1769 | ||
1695 | err_no_irq: | 1770 | err_no_irq: |
@@ -1703,11 +1778,13 @@ err_rx_clean_list: | |||
1703 | 1778 | ||
1704 | static void e100_down(struct nic *nic) | 1779 | static void e100_down(struct nic *nic) |
1705 | { | 1780 | { |
1781 | /* wait here for poll to complete */ | ||
1782 | netif_poll_disable(nic->netdev); | ||
1783 | netif_stop_queue(nic->netdev); | ||
1706 | e100_hw_reset(nic); | 1784 | e100_hw_reset(nic); |
1707 | free_irq(nic->pdev->irq, nic->netdev); | 1785 | free_irq(nic->pdev->irq, nic->netdev); |
1708 | del_timer_sync(&nic->watchdog); | 1786 | del_timer_sync(&nic->watchdog); |
1709 | netif_carrier_off(nic->netdev); | 1787 | netif_carrier_off(nic->netdev); |
1710 | netif_stop_queue(nic->netdev); | ||
1711 | e100_clean_cbs(nic); | 1788 | e100_clean_cbs(nic); |
1712 | e100_rx_clean_list(nic); | 1789 | e100_rx_clean_list(nic); |
1713 | } | 1790 | } |
@@ -1716,6 +1793,15 @@ static void e100_tx_timeout(struct net_device *netdev) | |||
1716 | { | 1793 | { |
1717 | struct nic *nic = netdev_priv(netdev); | 1794 | struct nic *nic = netdev_priv(netdev); |
1718 | 1795 | ||
1796 | /* Reset outside of interrupt context, to avoid request_irq | ||
1797 | * in interrupt context */ | ||
1798 | schedule_work(&nic->tx_timeout_task); | ||
1799 | } | ||
1800 | |||
1801 | static void e100_tx_timeout_task(struct net_device *netdev) | ||
1802 | { | ||
1803 | struct nic *nic = netdev_priv(netdev); | ||
1804 | |||
1719 | DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n", | 1805 | DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n", |
1720 | readb(&nic->csr->scb.status)); | 1806 | readb(&nic->csr->scb.status)); |
1721 | e100_down(netdev_priv(netdev)); | 1807 | e100_down(netdev_priv(netdev)); |
@@ -1749,7 +1835,7 @@ static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode) | |||
1749 | mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, | 1835 | mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, |
1750 | BMCR_LOOPBACK); | 1836 | BMCR_LOOPBACK); |
1751 | 1837 | ||
1752 | e100_start_receiver(nic); | 1838 | e100_start_receiver(nic, 0); |
1753 | 1839 | ||
1754 | if(!(skb = dev_alloc_skb(ETH_DATA_LEN))) { | 1840 | if(!(skb = dev_alloc_skb(ETH_DATA_LEN))) { |
1755 | err = -ENOMEM; | 1841 | err = -ENOMEM; |
@@ -1869,7 +1955,6 @@ static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) | |||
1869 | else | 1955 | else |
1870 | nic->flags &= ~wol_magic; | 1956 | nic->flags &= ~wol_magic; |
1871 | 1957 | ||
1872 | pci_enable_wake(nic->pdev, 0, nic->flags & (wol_magic | e100_asf(nic))); | ||
1873 | e100_exec_cb(nic, NULL, e100_configure); | 1958 | e100_exec_cb(nic, NULL, e100_configure); |
1874 | 1959 | ||
1875 | return 0; | 1960 | return 0; |
@@ -2223,6 +2308,7 @@ static int __devinit e100_probe(struct pci_dev *pdev, | |||
2223 | 2308 | ||
2224 | e100_get_defaults(nic); | 2309 | e100_get_defaults(nic); |
2225 | 2310 | ||
2311 | /* locks must be initialized before calling hw_reset */ | ||
2226 | spin_lock_init(&nic->cb_lock); | 2312 | spin_lock_init(&nic->cb_lock); |
2227 | spin_lock_init(&nic->cmd_lock); | 2313 | spin_lock_init(&nic->cmd_lock); |
2228 | 2314 | ||
@@ -2240,6 +2326,9 @@ static int __devinit e100_probe(struct pci_dev *pdev, | |||
2240 | nic->blink_timer.function = e100_blink_led; | 2326 | nic->blink_timer.function = e100_blink_led; |
2241 | nic->blink_timer.data = (unsigned long)nic; | 2327 | nic->blink_timer.data = (unsigned long)nic; |
2242 | 2328 | ||
2329 | INIT_WORK(&nic->tx_timeout_task, | ||
2330 | (void (*)(void *))e100_tx_timeout_task, netdev); | ||
2331 | |||
2243 | if((err = e100_alloc(nic))) { | 2332 | if((err = e100_alloc(nic))) { |
2244 | DPRINTK(PROBE, ERR, "Cannot alloc driver memory, aborting.\n"); | 2333 | DPRINTK(PROBE, ERR, "Cannot alloc driver memory, aborting.\n"); |
2245 | goto err_out_iounmap; | 2334 | goto err_out_iounmap; |
@@ -2263,7 +2352,8 @@ static int __devinit e100_probe(struct pci_dev *pdev, | |||
2263 | (nic->eeprom[eeprom_id] & eeprom_id_wol)) | 2352 | (nic->eeprom[eeprom_id] & eeprom_id_wol)) |
2264 | nic->flags |= wol_magic; | 2353 | nic->flags |= wol_magic; |
2265 | 2354 | ||
2266 | pci_enable_wake(pdev, 0, nic->flags & (wol_magic | e100_asf(nic))); | 2355 | /* ack any pending wake events, disable PME */ |
2356 | pci_enable_wake(pdev, 0, 0); | ||
2267 | 2357 | ||
2268 | strcpy(netdev->name, "eth%d"); | 2358 | strcpy(netdev->name, "eth%d"); |
2269 | if((err = register_netdev(netdev))) { | 2359 | if((err = register_netdev(netdev))) { |
@@ -2335,7 +2425,10 @@ static int e100_resume(struct pci_dev *pdev) | |||
2335 | 2425 | ||
2336 | pci_set_power_state(pdev, PCI_D0); | 2426 | pci_set_power_state(pdev, PCI_D0); |
2337 | pci_restore_state(pdev); | 2427 | pci_restore_state(pdev); |
2338 | e100_hw_init(nic); | 2428 | /* ack any pending wake events, disable PME */ |
2429 | pci_enable_wake(pdev, 0, 0); | ||
2430 | if(e100_hw_init(nic)) | ||
2431 | DPRINTK(HW, ERR, "e100_hw_init failed\n"); | ||
2339 | 2432 | ||
2340 | netif_device_attach(netdev); | 2433 | netif_device_attach(netdev); |
2341 | if(netif_running(netdev)) | 2434 | if(netif_running(netdev)) |
@@ -2345,6 +2438,21 @@ static int e100_resume(struct pci_dev *pdev) | |||
2345 | } | 2438 | } |
2346 | #endif | 2439 | #endif |
2347 | 2440 | ||
2441 | |||
2442 | static void e100_shutdown(struct device *dev) | ||
2443 | { | ||
2444 | struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); | ||
2445 | struct net_device *netdev = pci_get_drvdata(pdev); | ||
2446 | struct nic *nic = netdev_priv(netdev); | ||
2447 | |||
2448 | #ifdef CONFIG_PM | ||
2449 | pci_enable_wake(pdev, 0, nic->flags & (wol_magic | e100_asf(nic))); | ||
2450 | #else | ||
2451 | pci_enable_wake(pdev, 0, nic->flags & (wol_magic)); | ||
2452 | #endif | ||
2453 | } | ||
2454 | |||
2455 | |||
2348 | static struct pci_driver e100_driver = { | 2456 | static struct pci_driver e100_driver = { |
2349 | .name = DRV_NAME, | 2457 | .name = DRV_NAME, |
2350 | .id_table = e100_id_table, | 2458 | .id_table = e100_id_table, |
@@ -2354,6 +2462,11 @@ static struct pci_driver e100_driver = { | |||
2354 | .suspend = e100_suspend, | 2462 | .suspend = e100_suspend, |
2355 | .resume = e100_resume, | 2463 | .resume = e100_resume, |
2356 | #endif | 2464 | #endif |
2465 | |||
2466 | .driver = { | ||
2467 | .shutdown = e100_shutdown, | ||
2468 | } | ||
2469 | |||
2357 | }; | 2470 | }; |
2358 | 2471 | ||
2359 | static int __init e100_init_module(void) | 2472 | static int __init e100_init_module(void) |
diff --git a/drivers/net/e1000/e1000.h b/drivers/net/e1000/e1000.h index 148930d4e9bd..af1e82c5b808 100644 --- a/drivers/net/e1000/e1000.h +++ b/drivers/net/e1000/e1000.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /******************************************************************************* | 1 | /******************************************************************************* |
2 | 2 | ||
3 | 3 | ||
4 | Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved. | 4 | Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. |
5 | 5 | ||
6 | This program is free software; you can redistribute it and/or modify it | 6 | This program is free software; you can redistribute it and/or modify it |
7 | under the terms of the GNU General Public License as published by the Free | 7 | under the terms of the GNU General Public License as published by the Free |
@@ -112,6 +112,8 @@ struct e1000_adapter; | |||
112 | #define E1000_MAX_82544_RXD 4096 | 112 | #define E1000_MAX_82544_RXD 4096 |
113 | 113 | ||
114 | /* Supported Rx Buffer Sizes */ | 114 | /* Supported Rx Buffer Sizes */ |
115 | #define E1000_RXBUFFER_128 128 /* Used for packet split */ | ||
116 | #define E1000_RXBUFFER_256 256 /* Used for packet split */ | ||
115 | #define E1000_RXBUFFER_2048 2048 | 117 | #define E1000_RXBUFFER_2048 2048 |
116 | #define E1000_RXBUFFER_4096 4096 | 118 | #define E1000_RXBUFFER_4096 4096 |
117 | #define E1000_RXBUFFER_8192 8192 | 119 | #define E1000_RXBUFFER_8192 8192 |
@@ -137,15 +139,19 @@ struct e1000_adapter; | |||
137 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ | 139 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ |
138 | #define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */ | 140 | #define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */ |
139 | 141 | ||
140 | #define AUTO_ALL_MODES 0 | 142 | #define AUTO_ALL_MODES 0 |
141 | #define E1000_EEPROM_82544_APM 0x0004 | 143 | #define E1000_EEPROM_82544_APM 0x0400 |
142 | #define E1000_EEPROM_APME 0x0400 | 144 | #define E1000_EEPROM_APME 0x0400 |
143 | 145 | ||
144 | #ifndef E1000_MASTER_SLAVE | 146 | #ifndef E1000_MASTER_SLAVE |
145 | /* Switch to override PHY master/slave setting */ | 147 | /* Switch to override PHY master/slave setting */ |
146 | #define E1000_MASTER_SLAVE e1000_ms_hw_default | 148 | #define E1000_MASTER_SLAVE e1000_ms_hw_default |
147 | #endif | 149 | #endif |
148 | 150 | ||
151 | #define E1000_MNG_VLAN_NONE -1 | ||
152 | /* Number of packet split data buffers (not including the header buffer) */ | ||
153 | #define PS_PAGE_BUFFERS MAX_PS_BUFFERS-1 | ||
154 | |||
149 | /* only works for sizes that are powers of 2 */ | 155 | /* only works for sizes that are powers of 2 */ |
150 | #define E1000_ROUNDUP(i, size) ((i) = (((i) + (size) - 1) & ~((size) - 1))) | 156 | #define E1000_ROUNDUP(i, size) ((i) = (((i) + (size) - 1) & ~((size) - 1))) |
151 | 157 | ||
@@ -159,6 +165,9 @@ struct e1000_buffer { | |||
159 | uint16_t next_to_watch; | 165 | uint16_t next_to_watch; |
160 | }; | 166 | }; |
161 | 167 | ||
168 | struct e1000_ps_page { struct page *ps_page[MAX_PS_BUFFERS]; }; | ||
169 | struct e1000_ps_page_dma { uint64_t ps_page_dma[MAX_PS_BUFFERS]; }; | ||
170 | |||
162 | struct e1000_desc_ring { | 171 | struct e1000_desc_ring { |
163 | /* pointer to the descriptor ring memory */ | 172 | /* pointer to the descriptor ring memory */ |
164 | void *desc; | 173 | void *desc; |
@@ -174,12 +183,19 @@ struct e1000_desc_ring { | |||
174 | unsigned int next_to_clean; | 183 | unsigned int next_to_clean; |
175 | /* array of buffer information structs */ | 184 | /* array of buffer information structs */ |
176 | struct e1000_buffer *buffer_info; | 185 | struct e1000_buffer *buffer_info; |
186 | /* arrays of page information for packet split */ | ||
187 | struct e1000_ps_page *ps_page; | ||
188 | struct e1000_ps_page_dma *ps_page_dma; | ||
177 | }; | 189 | }; |
178 | 190 | ||
179 | #define E1000_DESC_UNUSED(R) \ | 191 | #define E1000_DESC_UNUSED(R) \ |
180 | ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ | 192 | ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ |
181 | (R)->next_to_clean - (R)->next_to_use - 1) | 193 | (R)->next_to_clean - (R)->next_to_use - 1) |
182 | 194 | ||
195 | #define E1000_RX_DESC_PS(R, i) \ | ||
196 | (&(((union e1000_rx_desc_packet_split *)((R).desc))[i])) | ||
197 | #define E1000_RX_DESC_EXT(R, i) \ | ||
198 | (&(((union e1000_rx_desc_extended *)((R).desc))[i])) | ||
183 | #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) | 199 | #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) |
184 | #define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc) | 200 | #define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc) |
185 | #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc) | 201 | #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc) |
@@ -192,6 +208,7 @@ struct e1000_adapter { | |||
192 | struct timer_list watchdog_timer; | 208 | struct timer_list watchdog_timer; |
193 | struct timer_list phy_info_timer; | 209 | struct timer_list phy_info_timer; |
194 | struct vlan_group *vlgrp; | 210 | struct vlan_group *vlgrp; |
211 | uint16_t mng_vlan_id; | ||
195 | uint32_t bd_number; | 212 | uint32_t bd_number; |
196 | uint32_t rx_buffer_len; | 213 | uint32_t rx_buffer_len; |
197 | uint32_t part_num; | 214 | uint32_t part_num; |
@@ -228,14 +245,23 @@ struct e1000_adapter { | |||
228 | boolean_t detect_tx_hung; | 245 | boolean_t detect_tx_hung; |
229 | 246 | ||
230 | /* RX */ | 247 | /* RX */ |
248 | #ifdef CONFIG_E1000_NAPI | ||
249 | boolean_t (*clean_rx) (struct e1000_adapter *adapter, int *work_done, | ||
250 | int work_to_do); | ||
251 | #else | ||
252 | boolean_t (*clean_rx) (struct e1000_adapter *adapter); | ||
253 | #endif | ||
254 | void (*alloc_rx_buf) (struct e1000_adapter *adapter); | ||
231 | struct e1000_desc_ring rx_ring; | 255 | struct e1000_desc_ring rx_ring; |
232 | uint64_t hw_csum_err; | 256 | uint64_t hw_csum_err; |
233 | uint64_t hw_csum_good; | 257 | uint64_t hw_csum_good; |
234 | uint32_t rx_int_delay; | 258 | uint32_t rx_int_delay; |
235 | uint32_t rx_abs_int_delay; | 259 | uint32_t rx_abs_int_delay; |
236 | boolean_t rx_csum; | 260 | boolean_t rx_csum; |
261 | boolean_t rx_ps; | ||
237 | uint32_t gorcl; | 262 | uint32_t gorcl; |
238 | uint64_t gorcl_old; | 263 | uint64_t gorcl_old; |
264 | uint16_t rx_ps_bsize0; | ||
239 | 265 | ||
240 | /* Interrupt Throttle Rate */ | 266 | /* Interrupt Throttle Rate */ |
241 | uint32_t itr; | 267 | uint32_t itr; |
@@ -257,5 +283,8 @@ struct e1000_adapter { | |||
257 | 283 | ||
258 | 284 | ||
259 | int msg_enable; | 285 | int msg_enable; |
286 | #ifdef CONFIG_PCI_MSI | ||
287 | boolean_t have_msi; | ||
288 | #endif | ||
260 | }; | 289 | }; |
261 | #endif /* _E1000_H_ */ | 290 | #endif /* _E1000_H_ */ |
diff --git a/drivers/net/e1000/e1000_ethtool.c b/drivers/net/e1000/e1000_ethtool.c index 0a2ca7c73a41..237247f74df4 100644 --- a/drivers/net/e1000/e1000_ethtool.c +++ b/drivers/net/e1000/e1000_ethtool.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /******************************************************************************* | 1 | /******************************************************************************* |
2 | 2 | ||
3 | 3 | ||
4 | Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved. | 4 | Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. |
5 | 5 | ||
6 | This program is free software; you can redistribute it and/or modify it | 6 | This program is free software; you can redistribute it and/or modify it |
7 | under the terms of the GNU General Public License as published by the Free | 7 | under the terms of the GNU General Public License as published by the Free |
@@ -69,6 +69,7 @@ static const struct e1000_stats e1000_gstrings_stats[] = { | |||
69 | { "rx_crc_errors", E1000_STAT(net_stats.rx_crc_errors) }, | 69 | { "rx_crc_errors", E1000_STAT(net_stats.rx_crc_errors) }, |
70 | { "rx_frame_errors", E1000_STAT(net_stats.rx_frame_errors) }, | 70 | { "rx_frame_errors", E1000_STAT(net_stats.rx_frame_errors) }, |
71 | { "rx_fifo_errors", E1000_STAT(net_stats.rx_fifo_errors) }, | 71 | { "rx_fifo_errors", E1000_STAT(net_stats.rx_fifo_errors) }, |
72 | { "rx_no_buffer_count", E1000_STAT(stats.rnbc) }, | ||
72 | { "rx_missed_errors", E1000_STAT(net_stats.rx_missed_errors) }, | 73 | { "rx_missed_errors", E1000_STAT(net_stats.rx_missed_errors) }, |
73 | { "tx_aborted_errors", E1000_STAT(net_stats.tx_aborted_errors) }, | 74 | { "tx_aborted_errors", E1000_STAT(net_stats.tx_aborted_errors) }, |
74 | { "tx_carrier_errors", E1000_STAT(net_stats.tx_carrier_errors) }, | 75 | { "tx_carrier_errors", E1000_STAT(net_stats.tx_carrier_errors) }, |
@@ -593,7 +594,7 @@ e1000_set_ringparam(struct net_device *netdev, | |||
593 | tx_old = adapter->tx_ring; | 594 | tx_old = adapter->tx_ring; |
594 | rx_old = adapter->rx_ring; | 595 | rx_old = adapter->rx_ring; |
595 | 596 | ||
596 | if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) | 597 | if((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) |
597 | return -EINVAL; | 598 | return -EINVAL; |
598 | 599 | ||
599 | if(netif_running(adapter->netdev)) | 600 | if(netif_running(adapter->netdev)) |
@@ -784,8 +785,8 @@ e1000_intr_test(struct e1000_adapter *adapter, uint64_t *data) | |||
784 | /* Hook up test interrupt handler just for this test */ | 785 | /* Hook up test interrupt handler just for this test */ |
785 | if(!request_irq(irq, &e1000_test_intr, 0, netdev->name, netdev)) { | 786 | if(!request_irq(irq, &e1000_test_intr, 0, netdev->name, netdev)) { |
786 | shared_int = FALSE; | 787 | shared_int = FALSE; |
787 | } else if(request_irq(irq, &e1000_test_intr, SA_SHIRQ, | 788 | } else if(request_irq(irq, &e1000_test_intr, SA_SHIRQ, |
788 | netdev->name, netdev)){ | 789 | netdev->name, netdev)){ |
789 | *data = 1; | 790 | *data = 1; |
790 | return -1; | 791 | return -1; |
791 | } | 792 | } |
@@ -842,10 +843,8 @@ e1000_intr_test(struct e1000_adapter *adapter, uint64_t *data) | |||
842 | * test failed. | 843 | * test failed. |
843 | */ | 844 | */ |
844 | adapter->test_icr = 0; | 845 | adapter->test_icr = 0; |
845 | E1000_WRITE_REG(&adapter->hw, IMC, | 846 | E1000_WRITE_REG(&adapter->hw, IMC, ~mask & 0x00007FFF); |
846 | (~mask & 0x00007FFF)); | 847 | E1000_WRITE_REG(&adapter->hw, ICS, ~mask & 0x00007FFF); |
847 | E1000_WRITE_REG(&adapter->hw, ICS, | ||
848 | (~mask & 0x00007FFF)); | ||
849 | msec_delay(10); | 848 | msec_delay(10); |
850 | 849 | ||
851 | if(adapter->test_icr) { | 850 | if(adapter->test_icr) { |
@@ -919,7 +918,8 @@ e1000_setup_desc_rings(struct e1000_adapter *adapter) | |||
919 | 918 | ||
920 | /* Setup Tx descriptor ring and Tx buffers */ | 919 | /* Setup Tx descriptor ring and Tx buffers */ |
921 | 920 | ||
922 | txdr->count = 80; | 921 | if(!txdr->count) |
922 | txdr->count = E1000_DEFAULT_TXD; | ||
923 | 923 | ||
924 | size = txdr->count * sizeof(struct e1000_buffer); | 924 | size = txdr->count * sizeof(struct e1000_buffer); |
925 | if(!(txdr->buffer_info = kmalloc(size, GFP_KERNEL))) { | 925 | if(!(txdr->buffer_info = kmalloc(size, GFP_KERNEL))) { |
@@ -974,7 +974,8 @@ e1000_setup_desc_rings(struct e1000_adapter *adapter) | |||
974 | 974 | ||
975 | /* Setup Rx descriptor ring and Rx buffers */ | 975 | /* Setup Rx descriptor ring and Rx buffers */ |
976 | 976 | ||
977 | rxdr->count = 80; | 977 | if(!rxdr->count) |
978 | rxdr->count = E1000_DEFAULT_RXD; | ||
978 | 979 | ||
979 | size = rxdr->count * sizeof(struct e1000_buffer); | 980 | size = rxdr->count * sizeof(struct e1000_buffer); |
980 | if(!(rxdr->buffer_info = kmalloc(size, GFP_KERNEL))) { | 981 | if(!(rxdr->buffer_info = kmalloc(size, GFP_KERNEL))) { |
@@ -1008,7 +1009,7 @@ e1000_setup_desc_rings(struct e1000_adapter *adapter) | |||
1008 | struct e1000_rx_desc *rx_desc = E1000_RX_DESC(*rxdr, i); | 1009 | struct e1000_rx_desc *rx_desc = E1000_RX_DESC(*rxdr, i); |
1009 | struct sk_buff *skb; | 1010 | struct sk_buff *skb; |
1010 | 1011 | ||
1011 | if(!(skb = alloc_skb(E1000_RXBUFFER_2048 + NET_IP_ALIGN, | 1012 | if(!(skb = alloc_skb(E1000_RXBUFFER_2048 + NET_IP_ALIGN, |
1012 | GFP_KERNEL))) { | 1013 | GFP_KERNEL))) { |
1013 | ret_val = 6; | 1014 | ret_val = 6; |
1014 | goto err_nomem; | 1015 | goto err_nomem; |
@@ -1310,31 +1311,62 @@ e1000_run_loopback_test(struct e1000_adapter *adapter) | |||
1310 | struct e1000_desc_ring *txdr = &adapter->test_tx_ring; | 1311 | struct e1000_desc_ring *txdr = &adapter->test_tx_ring; |
1311 | struct e1000_desc_ring *rxdr = &adapter->test_rx_ring; | 1312 | struct e1000_desc_ring *rxdr = &adapter->test_rx_ring; |
1312 | struct pci_dev *pdev = adapter->pdev; | 1313 | struct pci_dev *pdev = adapter->pdev; |
1313 | int i, ret_val; | 1314 | int i, j, k, l, lc, good_cnt, ret_val=0; |
1315 | unsigned long time; | ||
1314 | 1316 | ||
1315 | E1000_WRITE_REG(&adapter->hw, RDT, rxdr->count - 1); | 1317 | E1000_WRITE_REG(&adapter->hw, RDT, rxdr->count - 1); |
1316 | 1318 | ||
1317 | for(i = 0; i < 64; i++) { | 1319 | /* Calculate the loop count based on the largest descriptor ring |
1318 | e1000_create_lbtest_frame(txdr->buffer_info[i].skb, 1024); | 1320 | * The idea is to wrap the largest ring a number of times using 64 |
1319 | pci_dma_sync_single_for_device(pdev, txdr->buffer_info[i].dma, | 1321 | * send/receive pairs during each loop |
1320 | txdr->buffer_info[i].length, | 1322 | */ |
1321 | PCI_DMA_TODEVICE); | ||
1322 | } | ||
1323 | E1000_WRITE_REG(&adapter->hw, TDT, i); | ||
1324 | |||
1325 | msec_delay(200); | ||
1326 | |||
1327 | i = 0; | ||
1328 | do { | ||
1329 | pci_dma_sync_single_for_cpu(pdev, rxdr->buffer_info[i].dma, | ||
1330 | rxdr->buffer_info[i].length, | ||
1331 | PCI_DMA_FROMDEVICE); | ||
1332 | |||
1333 | ret_val = e1000_check_lbtest_frame(rxdr->buffer_info[i].skb, | ||
1334 | 1024); | ||
1335 | i++; | ||
1336 | } while (ret_val != 0 && i < 64); | ||
1337 | 1323 | ||
1324 | if(rxdr->count <= txdr->count) | ||
1325 | lc = ((txdr->count / 64) * 2) + 1; | ||
1326 | else | ||
1327 | lc = ((rxdr->count / 64) * 2) + 1; | ||
1328 | |||
1329 | k = l = 0; | ||
1330 | for(j = 0; j <= lc; j++) { /* loop count loop */ | ||
1331 | for(i = 0; i < 64; i++) { /* send the packets */ | ||
1332 | e1000_create_lbtest_frame(txdr->buffer_info[i].skb, | ||
1333 | 1024); | ||
1334 | pci_dma_sync_single_for_device(pdev, | ||
1335 | txdr->buffer_info[k].dma, | ||
1336 | txdr->buffer_info[k].length, | ||
1337 | PCI_DMA_TODEVICE); | ||
1338 | if(unlikely(++k == txdr->count)) k = 0; | ||
1339 | } | ||
1340 | E1000_WRITE_REG(&adapter->hw, TDT, k); | ||
1341 | msec_delay(200); | ||
1342 | time = jiffies; /* set the start time for the receive */ | ||
1343 | good_cnt = 0; | ||
1344 | do { /* receive the sent packets */ | ||
1345 | pci_dma_sync_single_for_cpu(pdev, | ||
1346 | rxdr->buffer_info[l].dma, | ||
1347 | rxdr->buffer_info[l].length, | ||
1348 | PCI_DMA_FROMDEVICE); | ||
1349 | |||
1350 | ret_val = e1000_check_lbtest_frame( | ||
1351 | rxdr->buffer_info[l].skb, | ||
1352 | 1024); | ||
1353 | if(!ret_val) | ||
1354 | good_cnt++; | ||
1355 | if(unlikely(++l == rxdr->count)) l = 0; | ||
1356 | /* time + 20 msecs (200 msecs on 2.4) is more than | ||
1357 | * enough time to complete the receives, if it's | ||
1358 | * exceeded, break and error off | ||
1359 | */ | ||
1360 | } while (good_cnt < 64 && jiffies < (time + 20)); | ||
1361 | if(good_cnt != 64) { | ||
1362 | ret_val = 13; /* ret_val is the same as mis-compare */ | ||
1363 | break; | ||
1364 | } | ||
1365 | if(jiffies >= (time + 2)) { | ||
1366 | ret_val = 14; /* error code for time out error */ | ||
1367 | break; | ||
1368 | } | ||
1369 | } /* end loop count loop */ | ||
1338 | return ret_val; | 1370 | return ret_val; |
1339 | } | 1371 | } |
1340 | 1372 | ||
@@ -1354,13 +1386,12 @@ static int | |||
1354 | e1000_link_test(struct e1000_adapter *adapter, uint64_t *data) | 1386 | e1000_link_test(struct e1000_adapter *adapter, uint64_t *data) |
1355 | { | 1387 | { |
1356 | *data = 0; | 1388 | *data = 0; |
1357 | |||
1358 | if (adapter->hw.media_type == e1000_media_type_internal_serdes) { | 1389 | if (adapter->hw.media_type == e1000_media_type_internal_serdes) { |
1359 | int i = 0; | 1390 | int i = 0; |
1360 | adapter->hw.serdes_link_down = TRUE; | 1391 | adapter->hw.serdes_link_down = TRUE; |
1361 | 1392 | ||
1362 | /* on some blade server designs link establishment */ | 1393 | /* On some blade server designs, link establishment |
1363 | /* could take as long as 2-3 minutes. */ | 1394 | * could take as long as 2-3 minutes */ |
1364 | do { | 1395 | do { |
1365 | e1000_check_for_link(&adapter->hw); | 1396 | e1000_check_for_link(&adapter->hw); |
1366 | if (adapter->hw.serdes_link_down == FALSE) | 1397 | if (adapter->hw.serdes_link_down == FALSE) |
@@ -1368,9 +1399,11 @@ e1000_link_test(struct e1000_adapter *adapter, uint64_t *data) | |||
1368 | msec_delay(20); | 1399 | msec_delay(20); |
1369 | } while (i++ < 3750); | 1400 | } while (i++ < 3750); |
1370 | 1401 | ||
1371 | *data = 1; | 1402 | *data = 1; |
1372 | } else { | 1403 | } else { |
1373 | e1000_check_for_link(&adapter->hw); | 1404 | e1000_check_for_link(&adapter->hw); |
1405 | if(adapter->hw.autoneg) /* if auto_neg is set wait for it */ | ||
1406 | msec_delay(4000); | ||
1374 | 1407 | ||
1375 | if(!(E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU)) { | 1408 | if(!(E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU)) { |
1376 | *data = 1; | 1409 | *data = 1; |
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c index 786a9b935659..723589b28be5 100644 --- a/drivers/net/e1000/e1000_hw.c +++ b/drivers/net/e1000/e1000_hw.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /******************************************************************************* | 1 | /******************************************************************************* |
2 | 2 | ||
3 | 3 | ||
4 | Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved. | 4 | Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. |
5 | 5 | ||
6 | This program is free software; you can redistribute it and/or modify it | 6 | This program is free software; you can redistribute it and/or modify it |
7 | under the terms of the GNU General Public License as published by the Free | 7 | under the terms of the GNU General Public License as published by the Free |
@@ -63,10 +63,11 @@ static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count); | |||
63 | static int32_t e1000_acquire_eeprom(struct e1000_hw *hw); | 63 | static int32_t e1000_acquire_eeprom(struct e1000_hw *hw); |
64 | static void e1000_release_eeprom(struct e1000_hw *hw); | 64 | static void e1000_release_eeprom(struct e1000_hw *hw); |
65 | static void e1000_standby_eeprom(struct e1000_hw *hw); | 65 | static void e1000_standby_eeprom(struct e1000_hw *hw); |
66 | static int32_t e1000_id_led_init(struct e1000_hw * hw); | ||
67 | static int32_t e1000_set_vco_speed(struct e1000_hw *hw); | 66 | static int32_t e1000_set_vco_speed(struct e1000_hw *hw); |
68 | static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw); | 67 | static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw); |
69 | static int32_t e1000_set_phy_mode(struct e1000_hw *hw); | 68 | static int32_t e1000_set_phy_mode(struct e1000_hw *hw); |
69 | static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer); | ||
70 | static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length); | ||
70 | 71 | ||
71 | /* IGP cable length table */ | 72 | /* IGP cable length table */ |
72 | static const | 73 | static const |
@@ -80,6 +81,17 @@ uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = | |||
80 | 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, | 81 | 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, |
81 | 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; | 82 | 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; |
82 | 83 | ||
84 | static const | ||
85 | uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = | ||
86 | { 8, 13, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, | ||
87 | 22, 24, 27, 30, 32, 35, 37, 40, 42, 44, 47, 49, 51, 54, 56, 58, | ||
88 | 32, 35, 38, 41, 44, 47, 50, 53, 55, 58, 61, 63, 66, 69, 71, 74, | ||
89 | 43, 47, 51, 54, 58, 61, 64, 67, 71, 74, 77, 80, 82, 85, 88, 90, | ||
90 | 57, 62, 66, 70, 74, 77, 81, 85, 88, 91, 94, 97, 100, 103, 106, 108, | ||
91 | 73, 78, 82, 87, 91, 95, 98, 102, 105, 109, 112, 114, 117, 119, 122, 124, | ||
92 | 91, 96, 101, 105, 109, 113, 116, 119, 122, 125, 127, 128, 128, 128, 128, 128, | ||
93 | 108, 113, 117, 121, 124, 127, 128, 128, 128, 128, 128, 128, 128, 128, 128, 128}; | ||
94 | |||
83 | 95 | ||
84 | /****************************************************************************** | 96 | /****************************************************************************** |
85 | * Set the phy type member in the hw struct. | 97 | * Set the phy type member in the hw struct. |
@@ -91,10 +103,14 @@ e1000_set_phy_type(struct e1000_hw *hw) | |||
91 | { | 103 | { |
92 | DEBUGFUNC("e1000_set_phy_type"); | 104 | DEBUGFUNC("e1000_set_phy_type"); |
93 | 105 | ||
106 | if(hw->mac_type == e1000_undefined) | ||
107 | return -E1000_ERR_PHY_TYPE; | ||
108 | |||
94 | switch(hw->phy_id) { | 109 | switch(hw->phy_id) { |
95 | case M88E1000_E_PHY_ID: | 110 | case M88E1000_E_PHY_ID: |
96 | case M88E1000_I_PHY_ID: | 111 | case M88E1000_I_PHY_ID: |
97 | case M88E1011_I_PHY_ID: | 112 | case M88E1011_I_PHY_ID: |
113 | case M88E1111_I_PHY_ID: | ||
98 | hw->phy_type = e1000_phy_m88; | 114 | hw->phy_type = e1000_phy_m88; |
99 | break; | 115 | break; |
100 | case IGP01E1000_I_PHY_ID: | 116 | case IGP01E1000_I_PHY_ID: |
@@ -128,7 +144,6 @@ e1000_phy_init_script(struct e1000_hw *hw) | |||
128 | 144 | ||
129 | DEBUGFUNC("e1000_phy_init_script"); | 145 | DEBUGFUNC("e1000_phy_init_script"); |
130 | 146 | ||
131 | |||
132 | if(hw->phy_init_script) { | 147 | if(hw->phy_init_script) { |
133 | msec_delay(20); | 148 | msec_delay(20); |
134 | 149 | ||
@@ -271,6 +286,7 @@ e1000_set_mac_type(struct e1000_hw *hw) | |||
271 | case E1000_DEV_ID_82546GB_FIBER: | 286 | case E1000_DEV_ID_82546GB_FIBER: |
272 | case E1000_DEV_ID_82546GB_SERDES: | 287 | case E1000_DEV_ID_82546GB_SERDES: |
273 | case E1000_DEV_ID_82546GB_PCIE: | 288 | case E1000_DEV_ID_82546GB_PCIE: |
289 | case E1000_DEV_ID_82546GB_QUAD_COPPER: | ||
274 | hw->mac_type = e1000_82546_rev_3; | 290 | hw->mac_type = e1000_82546_rev_3; |
275 | break; | 291 | break; |
276 | case E1000_DEV_ID_82541EI: | 292 | case E1000_DEV_ID_82541EI: |
@@ -289,12 +305,19 @@ e1000_set_mac_type(struct e1000_hw *hw) | |||
289 | case E1000_DEV_ID_82547GI: | 305 | case E1000_DEV_ID_82547GI: |
290 | hw->mac_type = e1000_82547_rev_2; | 306 | hw->mac_type = e1000_82547_rev_2; |
291 | break; | 307 | break; |
308 | case E1000_DEV_ID_82573E: | ||
309 | case E1000_DEV_ID_82573E_IAMT: | ||
310 | hw->mac_type = e1000_82573; | ||
311 | break; | ||
292 | default: | 312 | default: |
293 | /* Should never have loaded on this device */ | 313 | /* Should never have loaded on this device */ |
294 | return -E1000_ERR_MAC_TYPE; | 314 | return -E1000_ERR_MAC_TYPE; |
295 | } | 315 | } |
296 | 316 | ||
297 | switch(hw->mac_type) { | 317 | switch(hw->mac_type) { |
318 | case e1000_82573: | ||
319 | hw->eeprom_semaphore_present = TRUE; | ||
320 | /* fall through */ | ||
298 | case e1000_82541: | 321 | case e1000_82541: |
299 | case e1000_82547: | 322 | case e1000_82547: |
300 | case e1000_82541_rev_2: | 323 | case e1000_82541_rev_2: |
@@ -360,6 +383,9 @@ e1000_reset_hw(struct e1000_hw *hw) | |||
360 | uint32_t icr; | 383 | uint32_t icr; |
361 | uint32_t manc; | 384 | uint32_t manc; |
362 | uint32_t led_ctrl; | 385 | uint32_t led_ctrl; |
386 | uint32_t timeout; | ||
387 | uint32_t extcnf_ctrl; | ||
388 | int32_t ret_val; | ||
363 | 389 | ||
364 | DEBUGFUNC("e1000_reset_hw"); | 390 | DEBUGFUNC("e1000_reset_hw"); |
365 | 391 | ||
@@ -369,6 +395,15 @@ e1000_reset_hw(struct e1000_hw *hw) | |||
369 | e1000_pci_clear_mwi(hw); | 395 | e1000_pci_clear_mwi(hw); |
370 | } | 396 | } |
371 | 397 | ||
398 | if(hw->bus_type == e1000_bus_type_pci_express) { | ||
399 | /* Prevent the PCI-E bus from sticking if there is no TLP connection | ||
400 | * on the last TLP read/write transaction when MAC is reset. | ||
401 | */ | ||
402 | if(e1000_disable_pciex_master(hw) != E1000_SUCCESS) { | ||
403 | DEBUGOUT("PCI-E Master disable polling has failed.\n"); | ||
404 | } | ||
405 | } | ||
406 | |||
372 | /* Clear interrupt mask to stop board from generating interrupts */ | 407 | /* Clear interrupt mask to stop board from generating interrupts */ |
373 | DEBUGOUT("Masking off all interrupts\n"); | 408 | DEBUGOUT("Masking off all interrupts\n"); |
374 | E1000_WRITE_REG(hw, IMC, 0xffffffff); | 409 | E1000_WRITE_REG(hw, IMC, 0xffffffff); |
@@ -393,10 +428,32 @@ e1000_reset_hw(struct e1000_hw *hw) | |||
393 | 428 | ||
394 | /* Must reset the PHY before resetting the MAC */ | 429 | /* Must reset the PHY before resetting the MAC */ |
395 | if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { | 430 | if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
396 | E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); | 431 | E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); |
397 | msec_delay(5); | 432 | msec_delay(5); |
398 | } | 433 | } |
399 | 434 | ||
435 | /* Must acquire the MDIO ownership before MAC reset. | ||
436 | * Ownership defaults to firmware after a reset. */ | ||
437 | if(hw->mac_type == e1000_82573) { | ||
438 | timeout = 10; | ||
439 | |||
440 | extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); | ||
441 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | ||
442 | |||
443 | do { | ||
444 | E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); | ||
445 | extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); | ||
446 | |||
447 | if(extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) | ||
448 | break; | ||
449 | else | ||
450 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | ||
451 | |||
452 | msec_delay(2); | ||
453 | timeout--; | ||
454 | } while(timeout); | ||
455 | } | ||
456 | |||
400 | /* Issue a global reset to the MAC. This will reset the chip's | 457 | /* Issue a global reset to the MAC. This will reset the chip's |
401 | * transmit, receive, DMA, and link units. It will not effect | 458 | * transmit, receive, DMA, and link units. It will not effect |
402 | * the current PCI configuration. The global reset bit is self- | 459 | * the current PCI configuration. The global reset bit is self- |
@@ -450,6 +507,18 @@ e1000_reset_hw(struct e1000_hw *hw) | |||
450 | /* Wait for EEPROM reload */ | 507 | /* Wait for EEPROM reload */ |
451 | msec_delay(20); | 508 | msec_delay(20); |
452 | break; | 509 | break; |
510 | case e1000_82573: | ||
511 | udelay(10); | ||
512 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); | ||
513 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | ||
514 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); | ||
515 | E1000_WRITE_FLUSH(hw); | ||
516 | /* fall through */ | ||
517 | ret_val = e1000_get_auto_rd_done(hw); | ||
518 | if(ret_val) | ||
519 | /* We don't want to continue accessing MAC registers. */ | ||
520 | return ret_val; | ||
521 | break; | ||
453 | default: | 522 | default: |
454 | /* Wait for EEPROM reload (it happens automatically) */ | 523 | /* Wait for EEPROM reload (it happens automatically) */ |
455 | msec_delay(5); | 524 | msec_delay(5); |
@@ -457,7 +526,7 @@ e1000_reset_hw(struct e1000_hw *hw) | |||
457 | } | 526 | } |
458 | 527 | ||
459 | /* Disable HW ARPs on ASF enabled adapters */ | 528 | /* Disable HW ARPs on ASF enabled adapters */ |
460 | if(hw->mac_type >= e1000_82540) { | 529 | if(hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) { |
461 | manc = E1000_READ_REG(hw, MANC); | 530 | manc = E1000_READ_REG(hw, MANC); |
462 | manc &= ~(E1000_MANC_ARP_EN); | 531 | manc &= ~(E1000_MANC_ARP_EN); |
463 | E1000_WRITE_REG(hw, MANC, manc); | 532 | E1000_WRITE_REG(hw, MANC, manc); |
@@ -510,6 +579,8 @@ e1000_init_hw(struct e1000_hw *hw) | |||
510 | uint16_t pcix_stat_hi_word; | 579 | uint16_t pcix_stat_hi_word; |
511 | uint16_t cmd_mmrbc; | 580 | uint16_t cmd_mmrbc; |
512 | uint16_t stat_mmrbc; | 581 | uint16_t stat_mmrbc; |
582 | uint32_t mta_size; | ||
583 | |||
513 | DEBUGFUNC("e1000_init_hw"); | 584 | DEBUGFUNC("e1000_init_hw"); |
514 | 585 | ||
515 | /* Initialize Identification LED */ | 586 | /* Initialize Identification LED */ |
@@ -524,8 +595,8 @@ e1000_init_hw(struct e1000_hw *hw) | |||
524 | 595 | ||
525 | /* Disabling VLAN filtering. */ | 596 | /* Disabling VLAN filtering. */ |
526 | DEBUGOUT("Initializing the IEEE VLAN\n"); | 597 | DEBUGOUT("Initializing the IEEE VLAN\n"); |
527 | E1000_WRITE_REG(hw, VET, 0); | 598 | if (hw->mac_type < e1000_82545_rev_3) |
528 | 599 | E1000_WRITE_REG(hw, VET, 0); | |
529 | e1000_clear_vfta(hw); | 600 | e1000_clear_vfta(hw); |
530 | 601 | ||
531 | /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ | 602 | /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ |
@@ -553,14 +624,16 @@ e1000_init_hw(struct e1000_hw *hw) | |||
553 | 624 | ||
554 | /* Zero out the Multicast HASH table */ | 625 | /* Zero out the Multicast HASH table */ |
555 | DEBUGOUT("Zeroing the MTA\n"); | 626 | DEBUGOUT("Zeroing the MTA\n"); |
556 | for(i = 0; i < E1000_MC_TBL_SIZE; i++) | 627 | mta_size = E1000_MC_TBL_SIZE; |
628 | for(i = 0; i < mta_size; i++) | ||
557 | E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); | 629 | E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); |
558 | 630 | ||
559 | /* Set the PCI priority bit correctly in the CTRL register. This | 631 | /* Set the PCI priority bit correctly in the CTRL register. This |
560 | * determines if the adapter gives priority to receives, or if it | 632 | * determines if the adapter gives priority to receives, or if it |
561 | * gives equal priority to transmits and receives. | 633 | * gives equal priority to transmits and receives. Valid only on |
634 | * 82542 and 82543 silicon. | ||
562 | */ | 635 | */ |
563 | if(hw->dma_fairness) { | 636 | if(hw->dma_fairness && hw->mac_type <= e1000_82543) { |
564 | ctrl = E1000_READ_REG(hw, CTRL); | 637 | ctrl = E1000_READ_REG(hw, CTRL); |
565 | E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); | 638 | E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); |
566 | } | 639 | } |
@@ -598,9 +671,21 @@ e1000_init_hw(struct e1000_hw *hw) | |||
598 | if(hw->mac_type > e1000_82544) { | 671 | if(hw->mac_type > e1000_82544) { |
599 | ctrl = E1000_READ_REG(hw, TXDCTL); | 672 | ctrl = E1000_READ_REG(hw, TXDCTL); |
600 | ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; | 673 | ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; |
674 | switch (hw->mac_type) { | ||
675 | default: | ||
676 | break; | ||
677 | case e1000_82573: | ||
678 | ctrl |= E1000_TXDCTL_COUNT_DESC; | ||
679 | break; | ||
680 | } | ||
601 | E1000_WRITE_REG(hw, TXDCTL, ctrl); | 681 | E1000_WRITE_REG(hw, TXDCTL, ctrl); |
602 | } | 682 | } |
603 | 683 | ||
684 | if (hw->mac_type == e1000_82573) { | ||
685 | e1000_enable_tx_pkt_filtering(hw); | ||
686 | } | ||
687 | |||
688 | |||
604 | /* Clear all of the statistics registers (clear on read). It is | 689 | /* Clear all of the statistics registers (clear on read). It is |
605 | * important that we do this after we have tried to establish link | 690 | * important that we do this after we have tried to establish link |
606 | * because the symbol error count will increment wildly if there | 691 | * because the symbol error count will increment wildly if there |
@@ -679,7 +764,7 @@ e1000_setup_link(struct e1000_hw *hw) | |||
679 | * control setting, then the variable hw->fc will | 764 | * control setting, then the variable hw->fc will |
680 | * be initialized based on a value in the EEPROM. | 765 | * be initialized based on a value in the EEPROM. |
681 | */ | 766 | */ |
682 | if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) { | 767 | if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data)) { |
683 | DEBUGOUT("EEPROM Read Error\n"); | 768 | DEBUGOUT("EEPROM Read Error\n"); |
684 | return -E1000_ERR_EEPROM; | 769 | return -E1000_ERR_EEPROM; |
685 | } | 770 | } |
@@ -736,6 +821,7 @@ e1000_setup_link(struct e1000_hw *hw) | |||
736 | E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); | 821 | E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); |
737 | E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); | 822 | E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); |
738 | E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); | 823 | E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); |
824 | |||
739 | E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); | 825 | E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); |
740 | 826 | ||
741 | /* Set the flow control receive threshold registers. Normally, | 827 | /* Set the flow control receive threshold registers. Normally, |
@@ -906,20 +992,18 @@ e1000_setup_fiber_serdes_link(struct e1000_hw *hw) | |||
906 | } | 992 | } |
907 | 993 | ||
908 | /****************************************************************************** | 994 | /****************************************************************************** |
909 | * Detects which PHY is present and the speed and duplex | 995 | * Make sure we have a valid PHY and change PHY mode before link setup. |
910 | * | 996 | * |
911 | * hw - Struct containing variables accessed by shared code | 997 | * hw - Struct containing variables accessed by shared code |
912 | ******************************************************************************/ | 998 | ******************************************************************************/ |
913 | static int32_t | 999 | static int32_t |
914 | e1000_setup_copper_link(struct e1000_hw *hw) | 1000 | e1000_copper_link_preconfig(struct e1000_hw *hw) |
915 | { | 1001 | { |
916 | uint32_t ctrl; | 1002 | uint32_t ctrl; |
917 | uint32_t led_ctrl; | ||
918 | int32_t ret_val; | 1003 | int32_t ret_val; |
919 | uint16_t i; | ||
920 | uint16_t phy_data; | 1004 | uint16_t phy_data; |
921 | 1005 | ||
922 | DEBUGFUNC("e1000_setup_copper_link"); | 1006 | DEBUGFUNC("e1000_copper_link_preconfig"); |
923 | 1007 | ||
924 | ctrl = E1000_READ_REG(hw, CTRL); | 1008 | ctrl = E1000_READ_REG(hw, CTRL); |
925 | /* With 82543, we need to force speed and duplex on the MAC equal to what | 1009 | /* With 82543, we need to force speed and duplex on the MAC equal to what |
@@ -933,7 +1017,9 @@ e1000_setup_copper_link(struct e1000_hw *hw) | |||
933 | } else { | 1017 | } else { |
934 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); | 1018 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); |
935 | E1000_WRITE_REG(hw, CTRL, ctrl); | 1019 | E1000_WRITE_REG(hw, CTRL, ctrl); |
936 | e1000_phy_hw_reset(hw); | 1020 | ret_val = e1000_phy_hw_reset(hw); |
1021 | if(ret_val) | ||
1022 | return ret_val; | ||
937 | } | 1023 | } |
938 | 1024 | ||
939 | /* Make sure we have a valid PHY */ | 1025 | /* Make sure we have a valid PHY */ |
@@ -961,274 +1047,398 @@ e1000_setup_copper_link(struct e1000_hw *hw) | |||
961 | hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) | 1047 | hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) |
962 | hw->phy_reset_disable = FALSE; | 1048 | hw->phy_reset_disable = FALSE; |
963 | 1049 | ||
964 | if(!hw->phy_reset_disable) { | 1050 | return E1000_SUCCESS; |
965 | if (hw->phy_type == e1000_phy_igp) { | 1051 | } |
966 | 1052 | ||
967 | ret_val = e1000_phy_reset(hw); | ||
968 | if(ret_val) { | ||
969 | DEBUGOUT("Error Resetting the PHY\n"); | ||
970 | return ret_val; | ||
971 | } | ||
972 | 1053 | ||
973 | /* Wait 10ms for MAC to configure PHY from eeprom settings */ | 1054 | /******************************************************************** |
974 | msec_delay(15); | 1055 | * Copper link setup for e1000_phy_igp series. |
1056 | * | ||
1057 | * hw - Struct containing variables accessed by shared code | ||
1058 | *********************************************************************/ | ||
1059 | static int32_t | ||
1060 | e1000_copper_link_igp_setup(struct e1000_hw *hw) | ||
1061 | { | ||
1062 | uint32_t led_ctrl; | ||
1063 | int32_t ret_val; | ||
1064 | uint16_t phy_data; | ||
975 | 1065 | ||
976 | /* Configure activity LED after PHY reset */ | 1066 | DEBUGFUNC("e1000_copper_link_igp_setup"); |
977 | led_ctrl = E1000_READ_REG(hw, LEDCTL); | ||
978 | led_ctrl &= IGP_ACTIVITY_LED_MASK; | ||
979 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | ||
980 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); | ||
981 | 1067 | ||
982 | /* disable lplu d3 during driver init */ | 1068 | if (hw->phy_reset_disable) |
983 | ret_val = e1000_set_d3_lplu_state(hw, FALSE); | 1069 | return E1000_SUCCESS; |
984 | if(ret_val) { | 1070 | |
985 | DEBUGOUT("Error Disabling LPLU D3\n"); | 1071 | ret_val = e1000_phy_reset(hw); |
986 | return ret_val; | 1072 | if (ret_val) { |
987 | } | 1073 | DEBUGOUT("Error Resetting the PHY\n"); |
1074 | return ret_val; | ||
1075 | } | ||
988 | 1076 | ||
989 | /* Configure mdi-mdix settings */ | 1077 | /* Wait 10ms for MAC to configure PHY from eeprom settings */ |
990 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, | 1078 | msec_delay(15); |
991 | &phy_data); | ||
992 | if(ret_val) | ||
993 | return ret_val; | ||
994 | 1079 | ||
995 | if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { | 1080 | /* Configure activity LED after PHY reset */ |
996 | hw->dsp_config_state = e1000_dsp_config_disabled; | 1081 | led_ctrl = E1000_READ_REG(hw, LEDCTL); |
997 | /* Force MDI for earlier revs of the IGP PHY */ | 1082 | led_ctrl &= IGP_ACTIVITY_LED_MASK; |
998 | phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | | 1083 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
999 | IGP01E1000_PSCR_FORCE_MDI_MDIX); | 1084 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); |
1000 | hw->mdix = 1; | ||
1001 | 1085 | ||
1002 | } else { | 1086 | /* disable lplu d3 during driver init */ |
1003 | hw->dsp_config_state = e1000_dsp_config_enabled; | 1087 | ret_val = e1000_set_d3_lplu_state(hw, FALSE); |
1004 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; | 1088 | if (ret_val) { |
1005 | 1089 | DEBUGOUT("Error Disabling LPLU D3\n"); | |
1006 | switch (hw->mdix) { | 1090 | return ret_val; |
1007 | case 1: | 1091 | } |
1008 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | ||
1009 | break; | ||
1010 | case 2: | ||
1011 | phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; | ||
1012 | break; | ||
1013 | case 0: | ||
1014 | default: | ||
1015 | phy_data |= IGP01E1000_PSCR_AUTO_MDIX; | ||
1016 | break; | ||
1017 | } | ||
1018 | } | ||
1019 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, | ||
1020 | phy_data); | ||
1021 | if(ret_val) | ||
1022 | return ret_val; | ||
1023 | 1092 | ||
1024 | /* set auto-master slave resolution settings */ | 1093 | /* disable lplu d0 during driver init */ |
1025 | if(hw->autoneg) { | 1094 | ret_val = e1000_set_d0_lplu_state(hw, FALSE); |
1026 | e1000_ms_type phy_ms_setting = hw->master_slave; | 1095 | if (ret_val) { |
1096 | DEBUGOUT("Error Disabling LPLU D0\n"); | ||
1097 | return ret_val; | ||
1098 | } | ||
1099 | /* Configure mdi-mdix settings */ | ||
1100 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); | ||
1101 | if (ret_val) | ||
1102 | return ret_val; | ||
1027 | 1103 | ||
1028 | if(hw->ffe_config_state == e1000_ffe_config_active) | 1104 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
1029 | hw->ffe_config_state = e1000_ffe_config_enabled; | 1105 | hw->dsp_config_state = e1000_dsp_config_disabled; |
1106 | /* Force MDI for earlier revs of the IGP PHY */ | ||
1107 | phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX); | ||
1108 | hw->mdix = 1; | ||
1030 | 1109 | ||
1031 | if(hw->dsp_config_state == e1000_dsp_config_activated) | 1110 | } else { |
1032 | hw->dsp_config_state = e1000_dsp_config_enabled; | 1111 | hw->dsp_config_state = e1000_dsp_config_enabled; |
1112 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; | ||
1033 | 1113 | ||
1034 | /* when autonegotiation advertisment is only 1000Mbps then we | 1114 | switch (hw->mdix) { |
1035 | * should disable SmartSpeed and enable Auto MasterSlave | 1115 | case 1: |
1036 | * resolution as hardware default. */ | 1116 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
1037 | if(hw->autoneg_advertised == ADVERTISE_1000_FULL) { | 1117 | break; |
1038 | /* Disable SmartSpeed */ | 1118 | case 2: |
1039 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | 1119 | phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; |
1040 | &phy_data); | 1120 | break; |
1041 | if(ret_val) | 1121 | case 0: |
1042 | return ret_val; | 1122 | default: |
1043 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | 1123 | phy_data |= IGP01E1000_PSCR_AUTO_MDIX; |
1044 | ret_val = e1000_write_phy_reg(hw, | 1124 | break; |
1045 | IGP01E1000_PHY_PORT_CONFIG, | 1125 | } |
1046 | phy_data); | 1126 | } |
1047 | if(ret_val) | 1127 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
1048 | return ret_val; | 1128 | if(ret_val) |
1049 | /* Set auto Master/Slave resolution process */ | 1129 | return ret_val; |
1050 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); | ||
1051 | if(ret_val) | ||
1052 | return ret_val; | ||
1053 | phy_data &= ~CR_1000T_MS_ENABLE; | ||
1054 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); | ||
1055 | if(ret_val) | ||
1056 | return ret_val; | ||
1057 | } | ||
1058 | 1130 | ||
1059 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); | 1131 | /* set auto-master slave resolution settings */ |
1060 | if(ret_val) | 1132 | if(hw->autoneg) { |
1061 | return ret_val; | 1133 | e1000_ms_type phy_ms_setting = hw->master_slave; |
1062 | 1134 | ||
1063 | /* load defaults for future use */ | 1135 | if(hw->ffe_config_state == e1000_ffe_config_active) |
1064 | hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? | 1136 | hw->ffe_config_state = e1000_ffe_config_enabled; |
1065 | ((phy_data & CR_1000T_MS_VALUE) ? | 1137 | |
1066 | e1000_ms_force_master : | 1138 | if(hw->dsp_config_state == e1000_dsp_config_activated) |
1067 | e1000_ms_force_slave) : | 1139 | hw->dsp_config_state = e1000_dsp_config_enabled; |
1068 | e1000_ms_auto; | 1140 | |
1069 | 1141 | /* when autonegotiation advertisment is only 1000Mbps then we | |
1070 | switch (phy_ms_setting) { | 1142 | * should disable SmartSpeed and enable Auto MasterSlave |
1071 | case e1000_ms_force_master: | 1143 | * resolution as hardware default. */ |
1072 | phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); | 1144 | if(hw->autoneg_advertised == ADVERTISE_1000_FULL) { |
1073 | break; | 1145 | /* Disable SmartSpeed */ |
1074 | case e1000_ms_force_slave: | 1146 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); |
1075 | phy_data |= CR_1000T_MS_ENABLE; | 1147 | if(ret_val) |
1076 | phy_data &= ~(CR_1000T_MS_VALUE); | 1148 | return ret_val; |
1077 | break; | 1149 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
1078 | case e1000_ms_auto: | 1150 | ret_val = e1000_write_phy_reg(hw, |
1079 | phy_data &= ~CR_1000T_MS_ENABLE; | 1151 | IGP01E1000_PHY_PORT_CONFIG, |
1080 | default: | 1152 | phy_data); |
1081 | break; | 1153 | if(ret_val) |
1082 | } | 1154 | return ret_val; |
1083 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); | 1155 | /* Set auto Master/Slave resolution process */ |
1084 | if(ret_val) | 1156 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); |
1085 | return ret_val; | 1157 | if(ret_val) |
1086 | } | 1158 | return ret_val; |
1087 | } else { | 1159 | phy_data &= ~CR_1000T_MS_ENABLE; |
1088 | /* Enable CRS on TX. This must be set for half-duplex operation. */ | 1160 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); |
1089 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, | ||
1090 | &phy_data); | ||
1091 | if(ret_val) | 1161 | if(ret_val) |
1092 | return ret_val; | 1162 | return ret_val; |
1163 | } | ||
1093 | 1164 | ||
1094 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; | 1165 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); |
1166 | if(ret_val) | ||
1167 | return ret_val; | ||
1095 | 1168 | ||
1096 | /* Options: | 1169 | /* load defaults for future use */ |
1097 | * MDI/MDI-X = 0 (default) | 1170 | hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? |
1098 | * 0 - Auto for all speeds | 1171 | ((phy_data & CR_1000T_MS_VALUE) ? |
1099 | * 1 - MDI mode | 1172 | e1000_ms_force_master : |
1100 | * 2 - MDI-X mode | 1173 | e1000_ms_force_slave) : |
1101 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | 1174 | e1000_ms_auto; |
1102 | */ | ||
1103 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | ||
1104 | 1175 | ||
1105 | switch (hw->mdix) { | 1176 | switch (phy_ms_setting) { |
1106 | case 1: | 1177 | case e1000_ms_force_master: |
1107 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; | 1178 | phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); |
1108 | break; | 1179 | break; |
1109 | case 2: | 1180 | case e1000_ms_force_slave: |
1110 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; | 1181 | phy_data |= CR_1000T_MS_ENABLE; |
1111 | break; | 1182 | phy_data &= ~(CR_1000T_MS_VALUE); |
1112 | case 3: | 1183 | break; |
1113 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; | 1184 | case e1000_ms_auto: |
1114 | break; | 1185 | phy_data &= ~CR_1000T_MS_ENABLE; |
1115 | case 0: | ||
1116 | default: | 1186 | default: |
1117 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; | 1187 | break; |
1118 | break; | 1188 | } |
1119 | } | 1189 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); |
1190 | if(ret_val) | ||
1191 | return ret_val; | ||
1192 | } | ||
1120 | 1193 | ||
1121 | /* Options: | 1194 | return E1000_SUCCESS; |
1122 | * disable_polarity_correction = 0 (default) | 1195 | } |
1123 | * Automatic Correction for Reversed Cable Polarity | ||
1124 | * 0 - Disabled | ||
1125 | * 1 - Enabled | ||
1126 | */ | ||
1127 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; | ||
1128 | if(hw->disable_polarity_correction == 1) | ||
1129 | phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; | ||
1130 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, | ||
1131 | phy_data); | ||
1132 | if(ret_val) | ||
1133 | return ret_val; | ||
1134 | 1196 | ||
1135 | /* Force TX_CLK in the Extended PHY Specific Control Register | ||
1136 | * to 25MHz clock. | ||
1137 | */ | ||
1138 | ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, | ||
1139 | &phy_data); | ||
1140 | if(ret_val) | ||
1141 | return ret_val; | ||
1142 | 1197 | ||
1143 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | 1198 | /******************************************************************** |
1199 | * Copper link setup for e1000_phy_m88 series. | ||
1200 | * | ||
1201 | * hw - Struct containing variables accessed by shared code | ||
1202 | *********************************************************************/ | ||
1203 | static int32_t | ||
1204 | e1000_copper_link_mgp_setup(struct e1000_hw *hw) | ||
1205 | { | ||
1206 | int32_t ret_val; | ||
1207 | uint16_t phy_data; | ||
1208 | |||
1209 | DEBUGFUNC("e1000_copper_link_mgp_setup"); | ||
1210 | |||
1211 | if(hw->phy_reset_disable) | ||
1212 | return E1000_SUCCESS; | ||
1213 | |||
1214 | /* Enable CRS on TX. This must be set for half-duplex operation. */ | ||
1215 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | ||
1216 | if(ret_val) | ||
1217 | return ret_val; | ||
1218 | |||
1219 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; | ||
1220 | |||
1221 | /* Options: | ||
1222 | * MDI/MDI-X = 0 (default) | ||
1223 | * 0 - Auto for all speeds | ||
1224 | * 1 - MDI mode | ||
1225 | * 2 - MDI-X mode | ||
1226 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | ||
1227 | */ | ||
1228 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | ||
1229 | |||
1230 | switch (hw->mdix) { | ||
1231 | case 1: | ||
1232 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; | ||
1233 | break; | ||
1234 | case 2: | ||
1235 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; | ||
1236 | break; | ||
1237 | case 3: | ||
1238 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; | ||
1239 | break; | ||
1240 | case 0: | ||
1241 | default: | ||
1242 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; | ||
1243 | break; | ||
1244 | } | ||
1245 | |||
1246 | /* Options: | ||
1247 | * disable_polarity_correction = 0 (default) | ||
1248 | * Automatic Correction for Reversed Cable Polarity | ||
1249 | * 0 - Disabled | ||
1250 | * 1 - Enabled | ||
1251 | */ | ||
1252 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; | ||
1253 | if(hw->disable_polarity_correction == 1) | ||
1254 | phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; | ||
1255 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | ||
1256 | if(ret_val) | ||
1257 | return ret_val; | ||
1144 | 1258 | ||
1145 | if (hw->phy_revision < M88E1011_I_REV_4) { | 1259 | /* Force TX_CLK in the Extended PHY Specific Control Register |
1146 | /* Configure Master and Slave downshift values */ | 1260 | * to 25MHz clock. |
1147 | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | | 1261 | */ |
1262 | ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); | ||
1263 | if(ret_val) | ||
1264 | return ret_val; | ||
1265 | |||
1266 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | ||
1267 | |||
1268 | if (hw->phy_revision < M88E1011_I_REV_4) { | ||
1269 | /* Configure Master and Slave downshift values */ | ||
1270 | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | | ||
1148 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); | 1271 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); |
1149 | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | | 1272 | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | |
1150 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); | 1273 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); |
1151 | ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, | 1274 | ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
1152 | phy_data); | 1275 | if(ret_val) |
1153 | if(ret_val) | 1276 | return ret_val; |
1154 | return ret_val; | 1277 | } |
1155 | } | ||
1156 | 1278 | ||
1157 | /* SW Reset the PHY so all changes take effect */ | 1279 | /* SW Reset the PHY so all changes take effect */ |
1158 | ret_val = e1000_phy_reset(hw); | 1280 | ret_val = e1000_phy_reset(hw); |
1159 | if(ret_val) { | 1281 | if(ret_val) { |
1160 | DEBUGOUT("Error Resetting the PHY\n"); | 1282 | DEBUGOUT("Error Resetting the PHY\n"); |
1161 | return ret_val; | 1283 | return ret_val; |
1162 | } | 1284 | } |
1285 | |||
1286 | return E1000_SUCCESS; | ||
1287 | } | ||
1288 | |||
1289 | /******************************************************************** | ||
1290 | * Setup auto-negotiation and flow control advertisements, | ||
1291 | * and then perform auto-negotiation. | ||
1292 | * | ||
1293 | * hw - Struct containing variables accessed by shared code | ||
1294 | *********************************************************************/ | ||
1295 | static int32_t | ||
1296 | e1000_copper_link_autoneg(struct e1000_hw *hw) | ||
1297 | { | ||
1298 | int32_t ret_val; | ||
1299 | uint16_t phy_data; | ||
1300 | |||
1301 | DEBUGFUNC("e1000_copper_link_autoneg"); | ||
1302 | |||
1303 | /* Perform some bounds checking on the hw->autoneg_advertised | ||
1304 | * parameter. If this variable is zero, then set it to the default. | ||
1305 | */ | ||
1306 | hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; | ||
1307 | |||
1308 | /* If autoneg_advertised is zero, we assume it was not defaulted | ||
1309 | * by the calling code so we set to advertise full capability. | ||
1310 | */ | ||
1311 | if(hw->autoneg_advertised == 0) | ||
1312 | hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; | ||
1313 | |||
1314 | DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); | ||
1315 | ret_val = e1000_phy_setup_autoneg(hw); | ||
1316 | if(ret_val) { | ||
1317 | DEBUGOUT("Error Setting up Auto-Negotiation\n"); | ||
1318 | return ret_val; | ||
1319 | } | ||
1320 | DEBUGOUT("Restarting Auto-Neg\n"); | ||
1321 | |||
1322 | /* Restart auto-negotiation by setting the Auto Neg Enable bit and | ||
1323 | * the Auto Neg Restart bit in the PHY control register. | ||
1324 | */ | ||
1325 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); | ||
1326 | if(ret_val) | ||
1327 | return ret_val; | ||
1328 | |||
1329 | phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); | ||
1330 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); | ||
1331 | if(ret_val) | ||
1332 | return ret_val; | ||
1333 | |||
1334 | /* Does the user want to wait for Auto-Neg to complete here, or | ||
1335 | * check at a later time (for example, callback routine). | ||
1336 | */ | ||
1337 | if(hw->wait_autoneg_complete) { | ||
1338 | ret_val = e1000_wait_autoneg(hw); | ||
1339 | if(ret_val) { | ||
1340 | DEBUGOUT("Error while waiting for autoneg to complete\n"); | ||
1341 | return ret_val; | ||
1163 | } | 1342 | } |
1343 | } | ||
1164 | 1344 | ||
1165 | /* Options: | 1345 | hw->get_link_status = TRUE; |
1166 | * autoneg = 1 (default) | ||
1167 | * PHY will advertise value(s) parsed from | ||
1168 | * autoneg_advertised and fc | ||
1169 | * autoneg = 0 | ||
1170 | * PHY will be set to 10H, 10F, 100H, or 100F | ||
1171 | * depending on value parsed from forced_speed_duplex. | ||
1172 | */ | ||
1173 | 1346 | ||
1174 | /* Is autoneg enabled? This is enabled by default or by software | 1347 | return E1000_SUCCESS; |
1175 | * override. If so, call e1000_phy_setup_autoneg routine to parse the | 1348 | } |
1176 | * autoneg_advertised and fc options. If autoneg is NOT enabled, then | ||
1177 | * the user should have provided a speed/duplex override. If so, then | ||
1178 | * call e1000_phy_force_speed_duplex to parse and set this up. | ||
1179 | */ | ||
1180 | if(hw->autoneg) { | ||
1181 | /* Perform some bounds checking on the hw->autoneg_advertised | ||
1182 | * parameter. If this variable is zero, then set it to the default. | ||
1183 | */ | ||
1184 | hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; | ||
1185 | 1349 | ||
1186 | /* If autoneg_advertised is zero, we assume it was not defaulted | ||
1187 | * by the calling code so we set to advertise full capability. | ||
1188 | */ | ||
1189 | if(hw->autoneg_advertised == 0) | ||
1190 | hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; | ||
1191 | 1350 | ||
1192 | DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); | 1351 | /****************************************************************************** |
1193 | ret_val = e1000_phy_setup_autoneg(hw); | 1352 | * Config the MAC and the PHY after link is up. |
1194 | if(ret_val) { | 1353 | * 1) Set up the MAC to the current PHY speed/duplex |
1195 | DEBUGOUT("Error Setting up Auto-Negotiation\n"); | 1354 | * if we are on 82543. If we |
1196 | return ret_val; | 1355 | * are on newer silicon, we only need to configure |
1197 | } | 1356 | * collision distance in the Transmit Control Register. |
1198 | DEBUGOUT("Restarting Auto-Neg\n"); | 1357 | * 2) Set up flow control on the MAC to that established with |
1358 | * the link partner. | ||
1359 | * 3) Config DSP to improve Gigabit link quality for some PHY revisions. | ||
1360 | * | ||
1361 | * hw - Struct containing variables accessed by shared code | ||
1362 | ******************************************************************************/ | ||
1363 | static int32_t | ||
1364 | e1000_copper_link_postconfig(struct e1000_hw *hw) | ||
1365 | { | ||
1366 | int32_t ret_val; | ||
1367 | DEBUGFUNC("e1000_copper_link_postconfig"); | ||
1368 | |||
1369 | if(hw->mac_type >= e1000_82544) { | ||
1370 | e1000_config_collision_dist(hw); | ||
1371 | } else { | ||
1372 | ret_val = e1000_config_mac_to_phy(hw); | ||
1373 | if(ret_val) { | ||
1374 | DEBUGOUT("Error configuring MAC to PHY settings\n"); | ||
1375 | return ret_val; | ||
1376 | } | ||
1377 | } | ||
1378 | ret_val = e1000_config_fc_after_link_up(hw); | ||
1379 | if(ret_val) { | ||
1380 | DEBUGOUT("Error Configuring Flow Control\n"); | ||
1381 | return ret_val; | ||
1382 | } | ||
1199 | 1383 | ||
1200 | /* Restart auto-negotiation by setting the Auto Neg Enable bit and | 1384 | /* Config DSP to improve Giga link quality */ |
1201 | * the Auto Neg Restart bit in the PHY control register. | 1385 | if(hw->phy_type == e1000_phy_igp) { |
1202 | */ | 1386 | ret_val = e1000_config_dsp_after_link_change(hw, TRUE); |
1203 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); | 1387 | if(ret_val) { |
1204 | if(ret_val) | 1388 | DEBUGOUT("Error Configuring DSP after link up\n"); |
1205 | return ret_val; | 1389 | return ret_val; |
1390 | } | ||
1391 | } | ||
1392 | |||
1393 | return E1000_SUCCESS; | ||
1394 | } | ||
1206 | 1395 | ||
1207 | phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); | 1396 | /****************************************************************************** |
1208 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); | 1397 | * Detects which PHY is present and setup the speed and duplex |
1209 | if(ret_val) | 1398 | * |
1210 | return ret_val; | 1399 | * hw - Struct containing variables accessed by shared code |
1400 | ******************************************************************************/ | ||
1401 | static int32_t | ||
1402 | e1000_setup_copper_link(struct e1000_hw *hw) | ||
1403 | { | ||
1404 | int32_t ret_val; | ||
1405 | uint16_t i; | ||
1406 | uint16_t phy_data; | ||
1211 | 1407 | ||
1212 | /* Does the user want to wait for Auto-Neg to complete here, or | 1408 | DEBUGFUNC("e1000_setup_copper_link"); |
1213 | * check at a later time (for example, callback routine). | 1409 | |
1214 | */ | 1410 | /* Check if it is a valid PHY and set PHY mode if necessary. */ |
1215 | if(hw->wait_autoneg_complete) { | 1411 | ret_val = e1000_copper_link_preconfig(hw); |
1216 | ret_val = e1000_wait_autoneg(hw); | 1412 | if(ret_val) |
1217 | if(ret_val) { | 1413 | return ret_val; |
1218 | DEBUGOUT("Error while waiting for autoneg to complete\n"); | 1414 | |
1219 | return ret_val; | 1415 | if (hw->phy_type == e1000_phy_igp || |
1220 | } | 1416 | hw->phy_type == e1000_phy_igp_2) { |
1221 | } | 1417 | ret_val = e1000_copper_link_igp_setup(hw); |
1222 | hw->get_link_status = TRUE; | 1418 | if(ret_val) |
1223 | } else { | 1419 | return ret_val; |
1224 | DEBUGOUT("Forcing speed and duplex\n"); | 1420 | } else if (hw->phy_type == e1000_phy_m88) { |
1225 | ret_val = e1000_phy_force_speed_duplex(hw); | 1421 | ret_val = e1000_copper_link_mgp_setup(hw); |
1226 | if(ret_val) { | 1422 | if(ret_val) |
1227 | DEBUGOUT("Error Forcing Speed and Duplex\n"); | 1423 | return ret_val; |
1228 | return ret_val; | 1424 | } |
1229 | } | 1425 | |
1426 | if(hw->autoneg) { | ||
1427 | /* Setup autoneg and flow control advertisement | ||
1428 | * and perform autonegotiation */ | ||
1429 | ret_val = e1000_copper_link_autoneg(hw); | ||
1430 | if(ret_val) | ||
1431 | return ret_val; | ||
1432 | } else { | ||
1433 | /* PHY will be set to 10H, 10F, 100H,or 100F | ||
1434 | * depending on value from forced_speed_duplex. */ | ||
1435 | DEBUGOUT("Forcing speed and duplex\n"); | ||
1436 | ret_val = e1000_phy_force_speed_duplex(hw); | ||
1437 | if(ret_val) { | ||
1438 | DEBUGOUT("Error Forcing Speed and Duplex\n"); | ||
1439 | return ret_val; | ||
1230 | } | 1440 | } |
1231 | } /* !hw->phy_reset_disable */ | 1441 | } |
1232 | 1442 | ||
1233 | /* Check link status. Wait up to 100 microseconds for link to become | 1443 | /* Check link status. Wait up to 100 microseconds for link to become |
1234 | * valid. | 1444 | * valid. |
@@ -1242,37 +1452,11 @@ e1000_setup_copper_link(struct e1000_hw *hw) | |||
1242 | return ret_val; | 1452 | return ret_val; |
1243 | 1453 | ||
1244 | if(phy_data & MII_SR_LINK_STATUS) { | 1454 | if(phy_data & MII_SR_LINK_STATUS) { |
1245 | /* We have link, so we need to finish the config process: | 1455 | /* Config the MAC and PHY after link is up */ |
1246 | * 1) Set up the MAC to the current PHY speed/duplex | 1456 | ret_val = e1000_copper_link_postconfig(hw); |
1247 | * if we are on 82543. If we | 1457 | if(ret_val) |
1248 | * are on newer silicon, we only need to configure | ||
1249 | * collision distance in the Transmit Control Register. | ||
1250 | * 2) Set up flow control on the MAC to that established with | ||
1251 | * the link partner. | ||
1252 | */ | ||
1253 | if(hw->mac_type >= e1000_82544) { | ||
1254 | e1000_config_collision_dist(hw); | ||
1255 | } else { | ||
1256 | ret_val = e1000_config_mac_to_phy(hw); | ||
1257 | if(ret_val) { | ||
1258 | DEBUGOUT("Error configuring MAC to PHY settings\n"); | ||
1259 | return ret_val; | ||
1260 | } | ||
1261 | } | ||
1262 | ret_val = e1000_config_fc_after_link_up(hw); | ||
1263 | if(ret_val) { | ||
1264 | DEBUGOUT("Error Configuring Flow Control\n"); | ||
1265 | return ret_val; | 1458 | return ret_val; |
1266 | } | 1459 | |
1267 | DEBUGOUT("Valid link established!!!\n"); | ||
1268 | |||
1269 | if(hw->phy_type == e1000_phy_igp) { | ||
1270 | ret_val = e1000_config_dsp_after_link_change(hw, TRUE); | ||
1271 | if(ret_val) { | ||
1272 | DEBUGOUT("Error Configuring DSP after link up\n"); | ||
1273 | return ret_val; | ||
1274 | } | ||
1275 | } | ||
1276 | DEBUGOUT("Valid link established!!!\n"); | 1460 | DEBUGOUT("Valid link established!!!\n"); |
1277 | return E1000_SUCCESS; | 1461 | return E1000_SUCCESS; |
1278 | } | 1462 | } |
@@ -1302,10 +1486,10 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw) | |||
1302 | if(ret_val) | 1486 | if(ret_val) |
1303 | return ret_val; | 1487 | return ret_val; |
1304 | 1488 | ||
1305 | /* Read the MII 1000Base-T Control Register (Address 9). */ | 1489 | /* Read the MII 1000Base-T Control Register (Address 9). */ |
1306 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); | 1490 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); |
1307 | if(ret_val) | 1491 | if(ret_val) |
1308 | return ret_val; | 1492 | return ret_val; |
1309 | 1493 | ||
1310 | /* Need to parse both autoneg_advertised and fc and set up | 1494 | /* Need to parse both autoneg_advertised and fc and set up |
1311 | * the appropriate PHY registers. First we will parse for | 1495 | * the appropriate PHY registers. First we will parse for |
@@ -1417,7 +1601,7 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw) | |||
1417 | 1601 | ||
1418 | DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); | 1602 | DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); |
1419 | 1603 | ||
1420 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); | 1604 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); |
1421 | if(ret_val) | 1605 | if(ret_val) |
1422 | return ret_val; | 1606 | return ret_val; |
1423 | 1607 | ||
@@ -1678,6 +1862,11 @@ e1000_config_mac_to_phy(struct e1000_hw *hw) | |||
1678 | 1862 | ||
1679 | DEBUGFUNC("e1000_config_mac_to_phy"); | 1863 | DEBUGFUNC("e1000_config_mac_to_phy"); |
1680 | 1864 | ||
1865 | /* 82544 or newer MAC, Auto Speed Detection takes care of | ||
1866 | * MAC speed/duplex configuration.*/ | ||
1867 | if (hw->mac_type >= e1000_82544) | ||
1868 | return E1000_SUCCESS; | ||
1869 | |||
1681 | /* Read the Device Control Register and set the bits to Force Speed | 1870 | /* Read the Device Control Register and set the bits to Force Speed |
1682 | * and Duplex. | 1871 | * and Duplex. |
1683 | */ | 1872 | */ |
@@ -1688,45 +1877,25 @@ e1000_config_mac_to_phy(struct e1000_hw *hw) | |||
1688 | /* Set up duplex in the Device Control and Transmit Control | 1877 | /* Set up duplex in the Device Control and Transmit Control |
1689 | * registers depending on negotiated values. | 1878 | * registers depending on negotiated values. |
1690 | */ | 1879 | */ |
1691 | if (hw->phy_type == e1000_phy_igp) { | 1880 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
1692 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, | 1881 | if(ret_val) |
1693 | &phy_data); | 1882 | return ret_val; |
1694 | if(ret_val) | ||
1695 | return ret_val; | ||
1696 | |||
1697 | if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD; | ||
1698 | else ctrl &= ~E1000_CTRL_FD; | ||
1699 | |||
1700 | e1000_config_collision_dist(hw); | ||
1701 | 1883 | ||
1702 | /* Set up speed in the Device Control register depending on | 1884 | if(phy_data & M88E1000_PSSR_DPLX) |
1703 | * negotiated values. | 1885 | ctrl |= E1000_CTRL_FD; |
1704 | */ | 1886 | else |
1705 | if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == | 1887 | ctrl &= ~E1000_CTRL_FD; |
1706 | IGP01E1000_PSSR_SPEED_1000MBPS) | ||
1707 | ctrl |= E1000_CTRL_SPD_1000; | ||
1708 | else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) == | ||
1709 | IGP01E1000_PSSR_SPEED_100MBPS) | ||
1710 | ctrl |= E1000_CTRL_SPD_100; | ||
1711 | } else { | ||
1712 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, | ||
1713 | &phy_data); | ||
1714 | if(ret_val) | ||
1715 | return ret_val; | ||
1716 | 1888 | ||
1717 | if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD; | 1889 | e1000_config_collision_dist(hw); |
1718 | else ctrl &= ~E1000_CTRL_FD; | ||
1719 | 1890 | ||
1720 | e1000_config_collision_dist(hw); | 1891 | /* Set up speed in the Device Control register depending on |
1892 | * negotiated values. | ||
1893 | */ | ||
1894 | if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) | ||
1895 | ctrl |= E1000_CTRL_SPD_1000; | ||
1896 | else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) | ||
1897 | ctrl |= E1000_CTRL_SPD_100; | ||
1721 | 1898 | ||
1722 | /* Set up speed in the Device Control register depending on | ||
1723 | * negotiated values. | ||
1724 | */ | ||
1725 | if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) | ||
1726 | ctrl |= E1000_CTRL_SPD_1000; | ||
1727 | else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) | ||
1728 | ctrl |= E1000_CTRL_SPD_100; | ||
1729 | } | ||
1730 | /* Write the configured values back to the Device Control Reg. */ | 1899 | /* Write the configured values back to the Device Control Reg. */ |
1731 | E1000_WRITE_REG(hw, CTRL, ctrl); | 1900 | E1000_WRITE_REG(hw, CTRL, ctrl); |
1732 | return E1000_SUCCESS; | 1901 | return E1000_SUCCESS; |
@@ -2494,8 +2663,8 @@ e1000_read_phy_reg(struct e1000_hw *hw, | |||
2494 | 2663 | ||
2495 | DEBUGFUNC("e1000_read_phy_reg"); | 2664 | DEBUGFUNC("e1000_read_phy_reg"); |
2496 | 2665 | ||
2497 | 2666 | if((hw->phy_type == e1000_phy_igp || | |
2498 | if(hw->phy_type == e1000_phy_igp && | 2667 | hw->phy_type == e1000_phy_igp_2) && |
2499 | (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { | 2668 | (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { |
2500 | ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, | 2669 | ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, |
2501 | (uint16_t)reg_addr); | 2670 | (uint16_t)reg_addr); |
@@ -2600,8 +2769,8 @@ e1000_write_phy_reg(struct e1000_hw *hw, | |||
2600 | 2769 | ||
2601 | DEBUGFUNC("e1000_write_phy_reg"); | 2770 | DEBUGFUNC("e1000_write_phy_reg"); |
2602 | 2771 | ||
2603 | 2772 | if((hw->phy_type == e1000_phy_igp || | |
2604 | if(hw->phy_type == e1000_phy_igp && | 2773 | hw->phy_type == e1000_phy_igp_2) && |
2605 | (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { | 2774 | (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { |
2606 | ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, | 2775 | ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, |
2607 | (uint16_t)reg_addr); | 2776 | (uint16_t)reg_addr); |
@@ -2679,19 +2848,27 @@ e1000_write_phy_reg_ex(struct e1000_hw *hw, | |||
2679 | return E1000_SUCCESS; | 2848 | return E1000_SUCCESS; |
2680 | } | 2849 | } |
2681 | 2850 | ||
2851 | |||
2682 | /****************************************************************************** | 2852 | /****************************************************************************** |
2683 | * Returns the PHY to the power-on reset state | 2853 | * Returns the PHY to the power-on reset state |
2684 | * | 2854 | * |
2685 | * hw - Struct containing variables accessed by shared code | 2855 | * hw - Struct containing variables accessed by shared code |
2686 | ******************************************************************************/ | 2856 | ******************************************************************************/ |
2687 | void | 2857 | int32_t |
2688 | e1000_phy_hw_reset(struct e1000_hw *hw) | 2858 | e1000_phy_hw_reset(struct e1000_hw *hw) |
2689 | { | 2859 | { |
2690 | uint32_t ctrl, ctrl_ext; | 2860 | uint32_t ctrl, ctrl_ext; |
2691 | uint32_t led_ctrl; | 2861 | uint32_t led_ctrl; |
2862 | int32_t ret_val; | ||
2692 | 2863 | ||
2693 | DEBUGFUNC("e1000_phy_hw_reset"); | 2864 | DEBUGFUNC("e1000_phy_hw_reset"); |
2694 | 2865 | ||
2866 | /* In the case of the phy reset being blocked, it's not an error, we | ||
2867 | * simply return success without performing the reset. */ | ||
2868 | ret_val = e1000_check_phy_reset_block(hw); | ||
2869 | if (ret_val) | ||
2870 | return E1000_SUCCESS; | ||
2871 | |||
2695 | DEBUGOUT("Resetting Phy...\n"); | 2872 | DEBUGOUT("Resetting Phy...\n"); |
2696 | 2873 | ||
2697 | if(hw->mac_type > e1000_82543) { | 2874 | if(hw->mac_type > e1000_82543) { |
@@ -2727,6 +2904,11 @@ e1000_phy_hw_reset(struct e1000_hw *hw) | |||
2727 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | 2904 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
2728 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); | 2905 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); |
2729 | } | 2906 | } |
2907 | |||
2908 | /* Wait for FW to finish PHY configuration. */ | ||
2909 | ret_val = e1000_get_phy_cfg_done(hw); | ||
2910 | |||
2911 | return ret_val; | ||
2730 | } | 2912 | } |
2731 | 2913 | ||
2732 | /****************************************************************************** | 2914 | /****************************************************************************** |
@@ -2744,7 +2926,19 @@ e1000_phy_reset(struct e1000_hw *hw) | |||
2744 | 2926 | ||
2745 | DEBUGFUNC("e1000_phy_reset"); | 2927 | DEBUGFUNC("e1000_phy_reset"); |
2746 | 2928 | ||
2747 | if(hw->mac_type != e1000_82541_rev_2) { | 2929 | /* In the case of the phy reset being blocked, it's not an error, we |
2930 | * simply return success without performing the reset. */ | ||
2931 | ret_val = e1000_check_phy_reset_block(hw); | ||
2932 | if (ret_val) | ||
2933 | return E1000_SUCCESS; | ||
2934 | |||
2935 | switch (hw->mac_type) { | ||
2936 | case e1000_82541_rev_2: | ||
2937 | ret_val = e1000_phy_hw_reset(hw); | ||
2938 | if(ret_val) | ||
2939 | return ret_val; | ||
2940 | break; | ||
2941 | default: | ||
2748 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); | 2942 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); |
2749 | if(ret_val) | 2943 | if(ret_val) |
2750 | return ret_val; | 2944 | return ret_val; |
@@ -2755,9 +2949,10 @@ e1000_phy_reset(struct e1000_hw *hw) | |||
2755 | return ret_val; | 2949 | return ret_val; |
2756 | 2950 | ||
2757 | udelay(1); | 2951 | udelay(1); |
2758 | } else e1000_phy_hw_reset(hw); | 2952 | break; |
2953 | } | ||
2759 | 2954 | ||
2760 | if(hw->phy_type == e1000_phy_igp) | 2955 | if(hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) |
2761 | e1000_phy_init_script(hw); | 2956 | e1000_phy_init_script(hw); |
2762 | 2957 | ||
2763 | return E1000_SUCCESS; | 2958 | return E1000_SUCCESS; |
@@ -2811,6 +3006,9 @@ e1000_detect_gig_phy(struct e1000_hw *hw) | |||
2811 | case e1000_82547_rev_2: | 3006 | case e1000_82547_rev_2: |
2812 | if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE; | 3007 | if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE; |
2813 | break; | 3008 | break; |
3009 | case e1000_82573: | ||
3010 | if(hw->phy_id == M88E1111_I_PHY_ID) match = TRUE; | ||
3011 | break; | ||
2814 | default: | 3012 | default: |
2815 | DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); | 3013 | DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); |
2816 | return -E1000_ERR_CONFIG; | 3014 | return -E1000_ERR_CONFIG; |
@@ -2866,7 +3064,7 @@ e1000_phy_igp_get_info(struct e1000_hw *hw, | |||
2866 | 3064 | ||
2867 | /* The downshift status is checked only once, after link is established, | 3065 | /* The downshift status is checked only once, after link is established, |
2868 | * and it stored in the hw->speed_downgraded parameter. */ | 3066 | * and it stored in the hw->speed_downgraded parameter. */ |
2869 | phy_info->downshift = hw->speed_downgraded; | 3067 | phy_info->downshift = (e1000_downshift)hw->speed_downgraded; |
2870 | 3068 | ||
2871 | /* IGP01E1000 does not need to support it. */ | 3069 | /* IGP01E1000 does not need to support it. */ |
2872 | phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; | 3070 | phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; |
@@ -2905,7 +3103,7 @@ e1000_phy_igp_get_info(struct e1000_hw *hw, | |||
2905 | if(ret_val) | 3103 | if(ret_val) |
2906 | return ret_val; | 3104 | return ret_val; |
2907 | 3105 | ||
2908 | /* transalte to old method */ | 3106 | /* Translate to old method */ |
2909 | average = (max_length + min_length) / 2; | 3107 | average = (max_length + min_length) / 2; |
2910 | 3108 | ||
2911 | if(average <= e1000_igp_cable_length_50) | 3109 | if(average <= e1000_igp_cable_length_50) |
@@ -2940,7 +3138,7 @@ e1000_phy_m88_get_info(struct e1000_hw *hw, | |||
2940 | 3138 | ||
2941 | /* The downshift status is checked only once, after link is established, | 3139 | /* The downshift status is checked only once, after link is established, |
2942 | * and it stored in the hw->speed_downgraded parameter. */ | 3140 | * and it stored in the hw->speed_downgraded parameter. */ |
2943 | phy_info->downshift = hw->speed_downgraded; | 3141 | phy_info->downshift = (e1000_downshift)hw->speed_downgraded; |
2944 | 3142 | ||
2945 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | 3143 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
2946 | if(ret_val) | 3144 | if(ret_val) |
@@ -3029,7 +3227,8 @@ e1000_phy_get_info(struct e1000_hw *hw, | |||
3029 | return -E1000_ERR_CONFIG; | 3227 | return -E1000_ERR_CONFIG; |
3030 | } | 3228 | } |
3031 | 3229 | ||
3032 | if(hw->phy_type == e1000_phy_igp) | 3230 | if(hw->phy_type == e1000_phy_igp || |
3231 | hw->phy_type == e1000_phy_igp_2) | ||
3033 | return e1000_phy_igp_get_info(hw, phy_info); | 3232 | return e1000_phy_igp_get_info(hw, phy_info); |
3034 | else | 3233 | else |
3035 | return e1000_phy_m88_get_info(hw, phy_info); | 3234 | return e1000_phy_m88_get_info(hw, phy_info); |
@@ -3055,11 +3254,12 @@ e1000_validate_mdi_setting(struct e1000_hw *hw) | |||
3055 | * | 3254 | * |
3056 | * hw - Struct containing variables accessed by shared code | 3255 | * hw - Struct containing variables accessed by shared code |
3057 | *****************************************************************************/ | 3256 | *****************************************************************************/ |
3058 | void | 3257 | int32_t |
3059 | e1000_init_eeprom_params(struct e1000_hw *hw) | 3258 | e1000_init_eeprom_params(struct e1000_hw *hw) |
3060 | { | 3259 | { |
3061 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | 3260 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
3062 | uint32_t eecd = E1000_READ_REG(hw, EECD); | 3261 | uint32_t eecd = E1000_READ_REG(hw, EECD); |
3262 | int32_t ret_val = E1000_SUCCESS; | ||
3063 | uint16_t eeprom_size; | 3263 | uint16_t eeprom_size; |
3064 | 3264 | ||
3065 | DEBUGFUNC("e1000_init_eeprom_params"); | 3265 | DEBUGFUNC("e1000_init_eeprom_params"); |
@@ -3074,6 +3274,8 @@ e1000_init_eeprom_params(struct e1000_hw *hw) | |||
3074 | eeprom->opcode_bits = 3; | 3274 | eeprom->opcode_bits = 3; |
3075 | eeprom->address_bits = 6; | 3275 | eeprom->address_bits = 6; |
3076 | eeprom->delay_usec = 50; | 3276 | eeprom->delay_usec = 50; |
3277 | eeprom->use_eerd = FALSE; | ||
3278 | eeprom->use_eewr = FALSE; | ||
3077 | break; | 3279 | break; |
3078 | case e1000_82540: | 3280 | case e1000_82540: |
3079 | case e1000_82545: | 3281 | case e1000_82545: |
@@ -3090,6 +3292,8 @@ e1000_init_eeprom_params(struct e1000_hw *hw) | |||
3090 | eeprom->word_size = 64; | 3292 | eeprom->word_size = 64; |
3091 | eeprom->address_bits = 6; | 3293 | eeprom->address_bits = 6; |
3092 | } | 3294 | } |
3295 | eeprom->use_eerd = FALSE; | ||
3296 | eeprom->use_eewr = FALSE; | ||
3093 | break; | 3297 | break; |
3094 | case e1000_82541: | 3298 | case e1000_82541: |
3095 | case e1000_82541_rev_2: | 3299 | case e1000_82541_rev_2: |
@@ -3118,42 +3322,60 @@ e1000_init_eeprom_params(struct e1000_hw *hw) | |||
3118 | eeprom->address_bits = 6; | 3322 | eeprom->address_bits = 6; |
3119 | } | 3323 | } |
3120 | } | 3324 | } |
3325 | eeprom->use_eerd = FALSE; | ||
3326 | eeprom->use_eewr = FALSE; | ||
3327 | break; | ||
3328 | case e1000_82573: | ||
3329 | eeprom->type = e1000_eeprom_spi; | ||
3330 | eeprom->opcode_bits = 8; | ||
3331 | eeprom->delay_usec = 1; | ||
3332 | if (eecd & E1000_EECD_ADDR_BITS) { | ||
3333 | eeprom->page_size = 32; | ||
3334 | eeprom->address_bits = 16; | ||
3335 | } else { | ||
3336 | eeprom->page_size = 8; | ||
3337 | eeprom->address_bits = 8; | ||
3338 | } | ||
3339 | eeprom->use_eerd = TRUE; | ||
3340 | eeprom->use_eewr = TRUE; | ||
3341 | if(e1000_is_onboard_nvm_eeprom(hw) == FALSE) { | ||
3342 | eeprom->type = e1000_eeprom_flash; | ||
3343 | eeprom->word_size = 2048; | ||
3344 | |||
3345 | /* Ensure that the Autonomous FLASH update bit is cleared due to | ||
3346 | * Flash update issue on parts which use a FLASH for NVM. */ | ||
3347 | eecd &= ~E1000_EECD_AUPDEN; | ||
3348 | E1000_WRITE_REG(hw, EECD, eecd); | ||
3349 | } | ||
3121 | break; | 3350 | break; |
3122 | default: | 3351 | default: |
3123 | break; | 3352 | break; |
3124 | } | 3353 | } |
3125 | 3354 | ||
3126 | if (eeprom->type == e1000_eeprom_spi) { | 3355 | if (eeprom->type == e1000_eeprom_spi) { |
3127 | eeprom->word_size = 64; | 3356 | /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to |
3128 | if (e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) { | 3357 | * 32KB (incremented by powers of 2). |
3129 | eeprom_size &= EEPROM_SIZE_MASK; | 3358 | */ |
3130 | 3359 | if(hw->mac_type <= e1000_82547_rev_2) { | |
3131 | switch (eeprom_size) { | 3360 | /* Set to default value for initial eeprom read. */ |
3132 | case EEPROM_SIZE_16KB: | 3361 | eeprom->word_size = 64; |
3133 | eeprom->word_size = 8192; | 3362 | ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); |
3134 | break; | 3363 | if(ret_val) |
3135 | case EEPROM_SIZE_8KB: | 3364 | return ret_val; |
3136 | eeprom->word_size = 4096; | 3365 | eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; |
3137 | break; | 3366 | /* 256B eeprom size was not supported in earlier hardware, so we |
3138 | case EEPROM_SIZE_4KB: | 3367 | * bump eeprom_size up one to ensure that "1" (which maps to 256B) |
3139 | eeprom->word_size = 2048; | 3368 | * is never the result used in the shifting logic below. */ |
3140 | break; | 3369 | if(eeprom_size) |
3141 | case EEPROM_SIZE_2KB: | 3370 | eeprom_size++; |
3142 | eeprom->word_size = 1024; | 3371 | } else { |
3143 | break; | 3372 | eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >> |
3144 | case EEPROM_SIZE_1KB: | 3373 | E1000_EECD_SIZE_EX_SHIFT); |
3145 | eeprom->word_size = 512; | ||
3146 | break; | ||
3147 | case EEPROM_SIZE_512B: | ||
3148 | eeprom->word_size = 256; | ||
3149 | break; | ||
3150 | case EEPROM_SIZE_128B: | ||
3151 | default: | ||
3152 | eeprom->word_size = 64; | ||
3153 | break; | ||
3154 | } | ||
3155 | } | 3374 | } |
3375 | |||
3376 | eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); | ||
3156 | } | 3377 | } |
3378 | return ret_val; | ||
3157 | } | 3379 | } |
3158 | 3380 | ||
3159 | /****************************************************************************** | 3381 | /****************************************************************************** |
@@ -3306,8 +3528,12 @@ e1000_acquire_eeprom(struct e1000_hw *hw) | |||
3306 | 3528 | ||
3307 | DEBUGFUNC("e1000_acquire_eeprom"); | 3529 | DEBUGFUNC("e1000_acquire_eeprom"); |
3308 | 3530 | ||
3531 | if(e1000_get_hw_eeprom_semaphore(hw)) | ||
3532 | return -E1000_ERR_EEPROM; | ||
3533 | |||
3309 | eecd = E1000_READ_REG(hw, EECD); | 3534 | eecd = E1000_READ_REG(hw, EECD); |
3310 | 3535 | ||
3536 | if (hw->mac_type != e1000_82573) { | ||
3311 | /* Request EEPROM Access */ | 3537 | /* Request EEPROM Access */ |
3312 | if(hw->mac_type > e1000_82544) { | 3538 | if(hw->mac_type > e1000_82544) { |
3313 | eecd |= E1000_EECD_REQ; | 3539 | eecd |= E1000_EECD_REQ; |
@@ -3326,6 +3552,7 @@ e1000_acquire_eeprom(struct e1000_hw *hw) | |||
3326 | return -E1000_ERR_EEPROM; | 3552 | return -E1000_ERR_EEPROM; |
3327 | } | 3553 | } |
3328 | } | 3554 | } |
3555 | } | ||
3329 | 3556 | ||
3330 | /* Setup EEPROM for Read/Write */ | 3557 | /* Setup EEPROM for Read/Write */ |
3331 | 3558 | ||
@@ -3443,6 +3670,8 @@ e1000_release_eeprom(struct e1000_hw *hw) | |||
3443 | eecd &= ~E1000_EECD_REQ; | 3670 | eecd &= ~E1000_EECD_REQ; |
3444 | E1000_WRITE_REG(hw, EECD, eecd); | 3671 | E1000_WRITE_REG(hw, EECD, eecd); |
3445 | } | 3672 | } |
3673 | |||
3674 | e1000_put_hw_eeprom_semaphore(hw); | ||
3446 | } | 3675 | } |
3447 | 3676 | ||
3448 | /****************************************************************************** | 3677 | /****************************************************************************** |
@@ -3504,8 +3733,10 @@ e1000_read_eeprom(struct e1000_hw *hw, | |||
3504 | { | 3733 | { |
3505 | struct e1000_eeprom_info *eeprom = &hw->eeprom; | 3734 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
3506 | uint32_t i = 0; | 3735 | uint32_t i = 0; |
3736 | int32_t ret_val; | ||
3507 | 3737 | ||
3508 | DEBUGFUNC("e1000_read_eeprom"); | 3738 | DEBUGFUNC("e1000_read_eeprom"); |
3739 | |||
3509 | /* A check for invalid values: offset too large, too many words, and not | 3740 | /* A check for invalid values: offset too large, too many words, and not |
3510 | * enough words. | 3741 | * enough words. |
3511 | */ | 3742 | */ |
@@ -3515,9 +3746,23 @@ e1000_read_eeprom(struct e1000_hw *hw, | |||
3515 | return -E1000_ERR_EEPROM; | 3746 | return -E1000_ERR_EEPROM; |
3516 | } | 3747 | } |
3517 | 3748 | ||
3518 | /* Prepare the EEPROM for reading */ | 3749 | /* FLASH reads without acquiring the semaphore are safe in 82573-based |
3519 | if(e1000_acquire_eeprom(hw) != E1000_SUCCESS) | 3750 | * controllers. |
3520 | return -E1000_ERR_EEPROM; | 3751 | */ |
3752 | if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) || | ||
3753 | (hw->mac_type != e1000_82573)) { | ||
3754 | /* Prepare the EEPROM for reading */ | ||
3755 | if(e1000_acquire_eeprom(hw) != E1000_SUCCESS) | ||
3756 | return -E1000_ERR_EEPROM; | ||
3757 | } | ||
3758 | |||
3759 | if(eeprom->use_eerd == TRUE) { | ||
3760 | ret_val = e1000_read_eeprom_eerd(hw, offset, words, data); | ||
3761 | if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) || | ||
3762 | (hw->mac_type != e1000_82573)) | ||
3763 | e1000_release_eeprom(hw); | ||
3764 | return ret_val; | ||
3765 | } | ||
3521 | 3766 | ||
3522 | if(eeprom->type == e1000_eeprom_spi) { | 3767 | if(eeprom->type == e1000_eeprom_spi) { |
3523 | uint16_t word_in; | 3768 | uint16_t word_in; |
@@ -3569,6 +3814,132 @@ e1000_read_eeprom(struct e1000_hw *hw, | |||
3569 | } | 3814 | } |
3570 | 3815 | ||
3571 | /****************************************************************************** | 3816 | /****************************************************************************** |
3817 | * Reads a 16 bit word from the EEPROM using the EERD register. | ||
3818 | * | ||
3819 | * hw - Struct containing variables accessed by shared code | ||
3820 | * offset - offset of word in the EEPROM to read | ||
3821 | * data - word read from the EEPROM | ||
3822 | * words - number of words to read | ||
3823 | *****************************************************************************/ | ||
3824 | int32_t | ||
3825 | e1000_read_eeprom_eerd(struct e1000_hw *hw, | ||
3826 | uint16_t offset, | ||
3827 | uint16_t words, | ||
3828 | uint16_t *data) | ||
3829 | { | ||
3830 | uint32_t i, eerd = 0; | ||
3831 | int32_t error = 0; | ||
3832 | |||
3833 | for (i = 0; i < words; i++) { | ||
3834 | eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + | ||
3835 | E1000_EEPROM_RW_REG_START; | ||
3836 | |||
3837 | E1000_WRITE_REG(hw, EERD, eerd); | ||
3838 | error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); | ||
3839 | |||
3840 | if(error) { | ||
3841 | break; | ||
3842 | } | ||
3843 | data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA); | ||
3844 | |||
3845 | } | ||
3846 | |||
3847 | return error; | ||
3848 | } | ||
3849 | |||
3850 | /****************************************************************************** | ||
3851 | * Writes a 16 bit word from the EEPROM using the EEWR register. | ||
3852 | * | ||
3853 | * hw - Struct containing variables accessed by shared code | ||
3854 | * offset - offset of word in the EEPROM to read | ||
3855 | * data - word read from the EEPROM | ||
3856 | * words - number of words to read | ||
3857 | *****************************************************************************/ | ||
3858 | int32_t | ||
3859 | e1000_write_eeprom_eewr(struct e1000_hw *hw, | ||
3860 | uint16_t offset, | ||
3861 | uint16_t words, | ||
3862 | uint16_t *data) | ||
3863 | { | ||
3864 | uint32_t register_value = 0; | ||
3865 | uint32_t i = 0; | ||
3866 | int32_t error = 0; | ||
3867 | |||
3868 | for (i = 0; i < words; i++) { | ||
3869 | register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | | ||
3870 | ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) | | ||
3871 | E1000_EEPROM_RW_REG_START; | ||
3872 | |||
3873 | error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); | ||
3874 | if(error) { | ||
3875 | break; | ||
3876 | } | ||
3877 | |||
3878 | E1000_WRITE_REG(hw, EEWR, register_value); | ||
3879 | |||
3880 | error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); | ||
3881 | |||
3882 | if(error) { | ||
3883 | break; | ||
3884 | } | ||
3885 | } | ||
3886 | |||
3887 | return error; | ||
3888 | } | ||
3889 | |||
3890 | /****************************************************************************** | ||
3891 | * Polls the status bit (bit 1) of the EERD to determine when the read is done. | ||
3892 | * | ||
3893 | * hw - Struct containing variables accessed by shared code | ||
3894 | *****************************************************************************/ | ||
3895 | int32_t | ||
3896 | e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) | ||
3897 | { | ||
3898 | uint32_t attempts = 100000; | ||
3899 | uint32_t i, reg = 0; | ||
3900 | int32_t done = E1000_ERR_EEPROM; | ||
3901 | |||
3902 | for(i = 0; i < attempts; i++) { | ||
3903 | if(eerd == E1000_EEPROM_POLL_READ) | ||
3904 | reg = E1000_READ_REG(hw, EERD); | ||
3905 | else | ||
3906 | reg = E1000_READ_REG(hw, EEWR); | ||
3907 | |||
3908 | if(reg & E1000_EEPROM_RW_REG_DONE) { | ||
3909 | done = E1000_SUCCESS; | ||
3910 | break; | ||
3911 | } | ||
3912 | udelay(5); | ||
3913 | } | ||
3914 | |||
3915 | return done; | ||
3916 | } | ||
3917 | |||
3918 | /*************************************************************************** | ||
3919 | * Description: Determines if the onboard NVM is FLASH or EEPROM. | ||
3920 | * | ||
3921 | * hw - Struct containing variables accessed by shared code | ||
3922 | ****************************************************************************/ | ||
3923 | boolean_t | ||
3924 | e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) | ||
3925 | { | ||
3926 | uint32_t eecd = 0; | ||
3927 | |||
3928 | if(hw->mac_type == e1000_82573) { | ||
3929 | eecd = E1000_READ_REG(hw, EECD); | ||
3930 | |||
3931 | /* Isolate bits 15 & 16 */ | ||
3932 | eecd = ((eecd >> 15) & 0x03); | ||
3933 | |||
3934 | /* If both bits are set, device is Flash type */ | ||
3935 | if(eecd == 0x03) { | ||
3936 | return FALSE; | ||
3937 | } | ||
3938 | } | ||
3939 | return TRUE; | ||
3940 | } | ||
3941 | |||
3942 | /****************************************************************************** | ||
3572 | * Verifies that the EEPROM has a valid checksum | 3943 | * Verifies that the EEPROM has a valid checksum |
3573 | * | 3944 | * |
3574 | * hw - Struct containing variables accessed by shared code | 3945 | * hw - Struct containing variables accessed by shared code |
@@ -3585,6 +3956,25 @@ e1000_validate_eeprom_checksum(struct e1000_hw *hw) | |||
3585 | 3956 | ||
3586 | DEBUGFUNC("e1000_validate_eeprom_checksum"); | 3957 | DEBUGFUNC("e1000_validate_eeprom_checksum"); |
3587 | 3958 | ||
3959 | if ((hw->mac_type == e1000_82573) && | ||
3960 | (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) { | ||
3961 | /* Check bit 4 of word 10h. If it is 0, firmware is done updating | ||
3962 | * 10h-12h. Checksum may need to be fixed. */ | ||
3963 | e1000_read_eeprom(hw, 0x10, 1, &eeprom_data); | ||
3964 | if ((eeprom_data & 0x10) == 0) { | ||
3965 | /* Read 0x23 and check bit 15. This bit is a 1 when the checksum | ||
3966 | * has already been fixed. If the checksum is still wrong and this | ||
3967 | * bit is a 1, we need to return bad checksum. Otherwise, we need | ||
3968 | * to set this bit to a 1 and update the checksum. */ | ||
3969 | e1000_read_eeprom(hw, 0x23, 1, &eeprom_data); | ||
3970 | if ((eeprom_data & 0x8000) == 0) { | ||
3971 | eeprom_data |= 0x8000; | ||
3972 | e1000_write_eeprom(hw, 0x23, 1, &eeprom_data); | ||
3973 | e1000_update_eeprom_checksum(hw); | ||
3974 | } | ||
3975 | } | ||
3976 | } | ||
3977 | |||
3588 | for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { | 3978 | for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { |
3589 | if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { | 3979 | if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { |
3590 | DEBUGOUT("EEPROM Read Error\n"); | 3980 | DEBUGOUT("EEPROM Read Error\n"); |
@@ -3628,6 +4018,8 @@ e1000_update_eeprom_checksum(struct e1000_hw *hw) | |||
3628 | if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { | 4018 | if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { |
3629 | DEBUGOUT("EEPROM Write Error\n"); | 4019 | DEBUGOUT("EEPROM Write Error\n"); |
3630 | return -E1000_ERR_EEPROM; | 4020 | return -E1000_ERR_EEPROM; |
4021 | } else if (hw->eeprom.type == e1000_eeprom_flash) { | ||
4022 | e1000_commit_shadow_ram(hw); | ||
3631 | } | 4023 | } |
3632 | return E1000_SUCCESS; | 4024 | return E1000_SUCCESS; |
3633 | } | 4025 | } |
@@ -3663,6 +4055,10 @@ e1000_write_eeprom(struct e1000_hw *hw, | |||
3663 | return -E1000_ERR_EEPROM; | 4055 | return -E1000_ERR_EEPROM; |
3664 | } | 4056 | } |
3665 | 4057 | ||
4058 | /* 82573 reads only through eerd */ | ||
4059 | if(eeprom->use_eewr == TRUE) | ||
4060 | return e1000_write_eeprom_eewr(hw, offset, words, data); | ||
4061 | |||
3666 | /* Prepare the EEPROM for writing */ | 4062 | /* Prepare the EEPROM for writing */ |
3667 | if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) | 4063 | if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) |
3668 | return -E1000_ERR_EEPROM; | 4064 | return -E1000_ERR_EEPROM; |
@@ -3833,6 +4229,65 @@ e1000_write_eeprom_microwire(struct e1000_hw *hw, | |||
3833 | } | 4229 | } |
3834 | 4230 | ||
3835 | /****************************************************************************** | 4231 | /****************************************************************************** |
4232 | * Flushes the cached eeprom to NVM. This is done by saving the modified values | ||
4233 | * in the eeprom cache and the non modified values in the currently active bank | ||
4234 | * to the new bank. | ||
4235 | * | ||
4236 | * hw - Struct containing variables accessed by shared code | ||
4237 | * offset - offset of word in the EEPROM to read | ||
4238 | * data - word read from the EEPROM | ||
4239 | * words - number of words to read | ||
4240 | *****************************************************************************/ | ||
4241 | int32_t | ||
4242 | e1000_commit_shadow_ram(struct e1000_hw *hw) | ||
4243 | { | ||
4244 | uint32_t attempts = 100000; | ||
4245 | uint32_t eecd = 0; | ||
4246 | uint32_t flop = 0; | ||
4247 | uint32_t i = 0; | ||
4248 | int32_t error = E1000_SUCCESS; | ||
4249 | |||
4250 | /* The flop register will be used to determine if flash type is STM */ | ||
4251 | flop = E1000_READ_REG(hw, FLOP); | ||
4252 | |||
4253 | if (hw->mac_type == e1000_82573) { | ||
4254 | for (i=0; i < attempts; i++) { | ||
4255 | eecd = E1000_READ_REG(hw, EECD); | ||
4256 | if ((eecd & E1000_EECD_FLUPD) == 0) { | ||
4257 | break; | ||
4258 | } | ||
4259 | udelay(5); | ||
4260 | } | ||
4261 | |||
4262 | if (i == attempts) { | ||
4263 | return -E1000_ERR_EEPROM; | ||
4264 | } | ||
4265 | |||
4266 | /* If STM opcode located in bits 15:8 of flop, reset firmware */ | ||
4267 | if ((flop & 0xFF00) == E1000_STM_OPCODE) { | ||
4268 | E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); | ||
4269 | } | ||
4270 | |||
4271 | /* Perform the flash update */ | ||
4272 | E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); | ||
4273 | |||
4274 | for (i=0; i < attempts; i++) { | ||
4275 | eecd = E1000_READ_REG(hw, EECD); | ||
4276 | if ((eecd & E1000_EECD_FLUPD) == 0) { | ||
4277 | break; | ||
4278 | } | ||
4279 | udelay(5); | ||
4280 | } | ||
4281 | |||
4282 | if (i == attempts) { | ||
4283 | return -E1000_ERR_EEPROM; | ||
4284 | } | ||
4285 | } | ||
4286 | |||
4287 | return error; | ||
4288 | } | ||
4289 | |||
4290 | /****************************************************************************** | ||
3836 | * Reads the adapter's part number from the EEPROM | 4291 | * Reads the adapter's part number from the EEPROM |
3837 | * | 4292 | * |
3838 | * hw - Struct containing variables accessed by shared code | 4293 | * hw - Struct containing variables accessed by shared code |
@@ -3911,6 +4366,7 @@ void | |||
3911 | e1000_init_rx_addrs(struct e1000_hw *hw) | 4366 | e1000_init_rx_addrs(struct e1000_hw *hw) |
3912 | { | 4367 | { |
3913 | uint32_t i; | 4368 | uint32_t i; |
4369 | uint32_t rar_num; | ||
3914 | 4370 | ||
3915 | DEBUGFUNC("e1000_init_rx_addrs"); | 4371 | DEBUGFUNC("e1000_init_rx_addrs"); |
3916 | 4372 | ||
@@ -3919,9 +4375,10 @@ e1000_init_rx_addrs(struct e1000_hw *hw) | |||
3919 | 4375 | ||
3920 | e1000_rar_set(hw, hw->mac_addr, 0); | 4376 | e1000_rar_set(hw, hw->mac_addr, 0); |
3921 | 4377 | ||
4378 | rar_num = E1000_RAR_ENTRIES; | ||
3922 | /* Zero out the other 15 receive addresses. */ | 4379 | /* Zero out the other 15 receive addresses. */ |
3923 | DEBUGOUT("Clearing RAR[1-15]\n"); | 4380 | DEBUGOUT("Clearing RAR[1-15]\n"); |
3924 | for(i = 1; i < E1000_RAR_ENTRIES; i++) { | 4381 | for(i = 1; i < rar_num; i++) { |
3925 | E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); | 4382 | E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); |
3926 | E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); | 4383 | E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); |
3927 | } | 4384 | } |
@@ -3950,7 +4407,9 @@ e1000_mc_addr_list_update(struct e1000_hw *hw, | |||
3950 | { | 4407 | { |
3951 | uint32_t hash_value; | 4408 | uint32_t hash_value; |
3952 | uint32_t i; | 4409 | uint32_t i; |
3953 | 4410 | uint32_t num_rar_entry; | |
4411 | uint32_t num_mta_entry; | ||
4412 | |||
3954 | DEBUGFUNC("e1000_mc_addr_list_update"); | 4413 | DEBUGFUNC("e1000_mc_addr_list_update"); |
3955 | 4414 | ||
3956 | /* Set the new number of MC addresses that we are being requested to use. */ | 4415 | /* Set the new number of MC addresses that we are being requested to use. */ |
@@ -3958,14 +4417,16 @@ e1000_mc_addr_list_update(struct e1000_hw *hw, | |||
3958 | 4417 | ||
3959 | /* Clear RAR[1-15] */ | 4418 | /* Clear RAR[1-15] */ |
3960 | DEBUGOUT(" Clearing RAR[1-15]\n"); | 4419 | DEBUGOUT(" Clearing RAR[1-15]\n"); |
3961 | for(i = rar_used_count; i < E1000_RAR_ENTRIES; i++) { | 4420 | num_rar_entry = E1000_RAR_ENTRIES; |
4421 | for(i = rar_used_count; i < num_rar_entry; i++) { | ||
3962 | E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); | 4422 | E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); |
3963 | E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); | 4423 | E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); |
3964 | } | 4424 | } |
3965 | 4425 | ||
3966 | /* Clear the MTA */ | 4426 | /* Clear the MTA */ |
3967 | DEBUGOUT(" Clearing MTA\n"); | 4427 | DEBUGOUT(" Clearing MTA\n"); |
3968 | for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++) { | 4428 | num_mta_entry = E1000_NUM_MTA_REGISTERS; |
4429 | for(i = 0; i < num_mta_entry; i++) { | ||
3969 | E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); | 4430 | E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); |
3970 | } | 4431 | } |
3971 | 4432 | ||
@@ -3989,7 +4450,7 @@ e1000_mc_addr_list_update(struct e1000_hw *hw, | |||
3989 | /* Place this multicast address in the RAR if there is room, * | 4450 | /* Place this multicast address in the RAR if there is room, * |
3990 | * else put it in the MTA | 4451 | * else put it in the MTA |
3991 | */ | 4452 | */ |
3992 | if(rar_used_count < E1000_RAR_ENTRIES) { | 4453 | if (rar_used_count < num_rar_entry) { |
3993 | e1000_rar_set(hw, | 4454 | e1000_rar_set(hw, |
3994 | mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)), | 4455 | mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)), |
3995 | rar_used_count); | 4456 | rar_used_count); |
@@ -4040,6 +4501,7 @@ e1000_hash_mc_addr(struct e1000_hw *hw, | |||
4040 | } | 4501 | } |
4041 | 4502 | ||
4042 | hash_value &= 0xFFF; | 4503 | hash_value &= 0xFFF; |
4504 | |||
4043 | return hash_value; | 4505 | return hash_value; |
4044 | } | 4506 | } |
4045 | 4507 | ||
@@ -4144,12 +4606,33 @@ void | |||
4144 | e1000_clear_vfta(struct e1000_hw *hw) | 4606 | e1000_clear_vfta(struct e1000_hw *hw) |
4145 | { | 4607 | { |
4146 | uint32_t offset; | 4608 | uint32_t offset; |
4147 | 4609 | uint32_t vfta_value = 0; | |
4148 | for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) | 4610 | uint32_t vfta_offset = 0; |
4149 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); | 4611 | uint32_t vfta_bit_in_reg = 0; |
4612 | |||
4613 | if (hw->mac_type == e1000_82573) { | ||
4614 | if (hw->mng_cookie.vlan_id != 0) { | ||
4615 | /* The VFTA is a 4096b bit-field, each identifying a single VLAN | ||
4616 | * ID. The following operations determine which 32b entry | ||
4617 | * (i.e. offset) into the array we want to set the VLAN ID | ||
4618 | * (i.e. bit) of the manageability unit. */ | ||
4619 | vfta_offset = (hw->mng_cookie.vlan_id >> | ||
4620 | E1000_VFTA_ENTRY_SHIFT) & | ||
4621 | E1000_VFTA_ENTRY_MASK; | ||
4622 | vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & | ||
4623 | E1000_VFTA_ENTRY_BIT_SHIFT_MASK); | ||
4624 | } | ||
4625 | } | ||
4626 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { | ||
4627 | /* If the offset we want to clear is the same offset of the | ||
4628 | * manageability VLAN ID, then clear all bits except that of the | ||
4629 | * manageability unit */ | ||
4630 | vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; | ||
4631 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); | ||
4632 | } | ||
4150 | } | 4633 | } |
4151 | 4634 | ||
4152 | static int32_t | 4635 | int32_t |
4153 | e1000_id_led_init(struct e1000_hw * hw) | 4636 | e1000_id_led_init(struct e1000_hw * hw) |
4154 | { | 4637 | { |
4155 | uint32_t ledctl; | 4638 | uint32_t ledctl; |
@@ -4480,6 +4963,19 @@ e1000_clear_hw_cntrs(struct e1000_hw *hw) | |||
4480 | temp = E1000_READ_REG(hw, MGTPRC); | 4963 | temp = E1000_READ_REG(hw, MGTPRC); |
4481 | temp = E1000_READ_REG(hw, MGTPDC); | 4964 | temp = E1000_READ_REG(hw, MGTPDC); |
4482 | temp = E1000_READ_REG(hw, MGTPTC); | 4965 | temp = E1000_READ_REG(hw, MGTPTC); |
4966 | |||
4967 | if(hw->mac_type <= e1000_82547_rev_2) return; | ||
4968 | |||
4969 | temp = E1000_READ_REG(hw, IAC); | ||
4970 | temp = E1000_READ_REG(hw, ICRXOC); | ||
4971 | temp = E1000_READ_REG(hw, ICRXPTC); | ||
4972 | temp = E1000_READ_REG(hw, ICRXATC); | ||
4973 | temp = E1000_READ_REG(hw, ICTXPTC); | ||
4974 | temp = E1000_READ_REG(hw, ICTXATC); | ||
4975 | temp = E1000_READ_REG(hw, ICTXQEC); | ||
4976 | temp = E1000_READ_REG(hw, ICTXQMTC); | ||
4977 | temp = E1000_READ_REG(hw, ICRXDMTC); | ||
4978 | |||
4483 | } | 4979 | } |
4484 | 4980 | ||
4485 | /****************************************************************************** | 4981 | /****************************************************************************** |
@@ -4646,6 +5142,11 @@ e1000_get_bus_info(struct e1000_hw *hw) | |||
4646 | hw->bus_speed = e1000_bus_speed_unknown; | 5142 | hw->bus_speed = e1000_bus_speed_unknown; |
4647 | hw->bus_width = e1000_bus_width_unknown; | 5143 | hw->bus_width = e1000_bus_width_unknown; |
4648 | break; | 5144 | break; |
5145 | case e1000_82573: | ||
5146 | hw->bus_type = e1000_bus_type_pci_express; | ||
5147 | hw->bus_speed = e1000_bus_speed_2500; | ||
5148 | hw->bus_width = e1000_bus_width_pciex_4; | ||
5149 | break; | ||
4649 | default: | 5150 | default: |
4650 | status = E1000_READ_REG(hw, STATUS); | 5151 | status = E1000_READ_REG(hw, STATUS); |
4651 | hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? | 5152 | hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? |
@@ -4749,6 +5250,7 @@ e1000_get_cable_length(struct e1000_hw *hw, | |||
4749 | 5250 | ||
4750 | /* Use old method for Phy older than IGP */ | 5251 | /* Use old method for Phy older than IGP */ |
4751 | if(hw->phy_type == e1000_phy_m88) { | 5252 | if(hw->phy_type == e1000_phy_m88) { |
5253 | |||
4752 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, | 5254 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
4753 | &phy_data); | 5255 | &phy_data); |
4754 | if(ret_val) | 5256 | if(ret_val) |
@@ -4865,7 +5367,8 @@ e1000_check_polarity(struct e1000_hw *hw, | |||
4865 | return ret_val; | 5367 | return ret_val; |
4866 | *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >> | 5368 | *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >> |
4867 | M88E1000_PSSR_REV_POLARITY_SHIFT; | 5369 | M88E1000_PSSR_REV_POLARITY_SHIFT; |
4868 | } else if(hw->phy_type == e1000_phy_igp) { | 5370 | } else if(hw->phy_type == e1000_phy_igp || |
5371 | hw->phy_type == e1000_phy_igp_2) { | ||
4869 | /* Read the Status register to check the speed */ | 5372 | /* Read the Status register to check the speed */ |
4870 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, | 5373 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, |
4871 | &phy_data); | 5374 | &phy_data); |
@@ -4917,7 +5420,8 @@ e1000_check_downshift(struct e1000_hw *hw) | |||
4917 | 5420 | ||
4918 | DEBUGFUNC("e1000_check_downshift"); | 5421 | DEBUGFUNC("e1000_check_downshift"); |
4919 | 5422 | ||
4920 | if(hw->phy_type == e1000_phy_igp) { | 5423 | if(hw->phy_type == e1000_phy_igp || |
5424 | hw->phy_type == e1000_phy_igp_2) { | ||
4921 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, | 5425 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, |
4922 | &phy_data); | 5426 | &phy_data); |
4923 | if(ret_val) | 5427 | if(ret_val) |
@@ -4933,6 +5437,7 @@ e1000_check_downshift(struct e1000_hw *hw) | |||
4933 | hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> | 5437 | hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> |
4934 | M88E1000_PSSR_DOWNSHIFT_SHIFT; | 5438 | M88E1000_PSSR_DOWNSHIFT_SHIFT; |
4935 | } | 5439 | } |
5440 | |||
4936 | return E1000_SUCCESS; | 5441 | return E1000_SUCCESS; |
4937 | } | 5442 | } |
4938 | 5443 | ||
@@ -5047,7 +5552,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw, | |||
5047 | if(ret_val) | 5552 | if(ret_val) |
5048 | return ret_val; | 5553 | return ret_val; |
5049 | 5554 | ||
5050 | msec_delay(20); | 5555 | msec_delay_irq(20); |
5051 | 5556 | ||
5052 | ret_val = e1000_write_phy_reg(hw, 0x0000, | 5557 | ret_val = e1000_write_phy_reg(hw, 0x0000, |
5053 | IGP01E1000_IEEE_FORCE_GIGA); | 5558 | IGP01E1000_IEEE_FORCE_GIGA); |
@@ -5071,7 +5576,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw, | |||
5071 | if(ret_val) | 5576 | if(ret_val) |
5072 | return ret_val; | 5577 | return ret_val; |
5073 | 5578 | ||
5074 | msec_delay(20); | 5579 | msec_delay_irq(20); |
5075 | 5580 | ||
5076 | /* Now enable the transmitter */ | 5581 | /* Now enable the transmitter */ |
5077 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); | 5582 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
@@ -5096,7 +5601,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw, | |||
5096 | if(ret_val) | 5601 | if(ret_val) |
5097 | return ret_val; | 5602 | return ret_val; |
5098 | 5603 | ||
5099 | msec_delay(20); | 5604 | msec_delay_irq(20); |
5100 | 5605 | ||
5101 | ret_val = e1000_write_phy_reg(hw, 0x0000, | 5606 | ret_val = e1000_write_phy_reg(hw, 0x0000, |
5102 | IGP01E1000_IEEE_FORCE_GIGA); | 5607 | IGP01E1000_IEEE_FORCE_GIGA); |
@@ -5112,7 +5617,7 @@ e1000_config_dsp_after_link_change(struct e1000_hw *hw, | |||
5112 | if(ret_val) | 5617 | if(ret_val) |
5113 | return ret_val; | 5618 | return ret_val; |
5114 | 5619 | ||
5115 | msec_delay(20); | 5620 | msec_delay_irq(20); |
5116 | 5621 | ||
5117 | /* Now enable the transmitter */ | 5622 | /* Now enable the transmitter */ |
5118 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); | 5623 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
@@ -5187,22 +5692,36 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw, | |||
5187 | uint16_t phy_data; | 5692 | uint16_t phy_data; |
5188 | DEBUGFUNC("e1000_set_d3_lplu_state"); | 5693 | DEBUGFUNC("e1000_set_d3_lplu_state"); |
5189 | 5694 | ||
5190 | if(!((hw->mac_type == e1000_82541_rev_2) || | 5695 | if(hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2) |
5191 | (hw->mac_type == e1000_82547_rev_2))) | ||
5192 | return E1000_SUCCESS; | 5696 | return E1000_SUCCESS; |
5193 | 5697 | ||
5194 | /* During driver activity LPLU should not be used or it will attain link | 5698 | /* During driver activity LPLU should not be used or it will attain link |
5195 | * from the lowest speeds starting from 10Mbps. The capability is used for | 5699 | * from the lowest speeds starting from 10Mbps. The capability is used for |
5196 | * Dx transitions and states */ | 5700 | * Dx transitions and states */ |
5197 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); | 5701 | if(hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) { |
5198 | if(ret_val) | 5702 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); |
5199 | return ret_val; | ||
5200 | |||
5201 | if(!active) { | ||
5202 | phy_data &= ~IGP01E1000_GMII_FLEX_SPD; | ||
5203 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); | ||
5204 | if(ret_val) | 5703 | if(ret_val) |
5205 | return ret_val; | 5704 | return ret_val; |
5705 | } else { | ||
5706 | ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); | ||
5707 | if(ret_val) | ||
5708 | return ret_val; | ||
5709 | } | ||
5710 | |||
5711 | if(!active) { | ||
5712 | if(hw->mac_type == e1000_82541_rev_2 || | ||
5713 | hw->mac_type == e1000_82547_rev_2) { | ||
5714 | phy_data &= ~IGP01E1000_GMII_FLEX_SPD; | ||
5715 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); | ||
5716 | if(ret_val) | ||
5717 | return ret_val; | ||
5718 | } else { | ||
5719 | phy_data &= ~IGP02E1000_PM_D3_LPLU; | ||
5720 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, | ||
5721 | phy_data); | ||
5722 | if (ret_val) | ||
5723 | return ret_val; | ||
5724 | } | ||
5206 | 5725 | ||
5207 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during | 5726 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during |
5208 | * Dx states where the power conservation is most important. During | 5727 | * Dx states where the power conservation is most important. During |
@@ -5236,11 +5755,105 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw, | |||
5236 | (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) || | 5755 | (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) || |
5237 | (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { | 5756 | (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { |
5238 | 5757 | ||
5239 | phy_data |= IGP01E1000_GMII_FLEX_SPD; | 5758 | if(hw->mac_type == e1000_82541_rev_2 || |
5240 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); | 5759 | hw->mac_type == e1000_82547_rev_2) { |
5760 | phy_data |= IGP01E1000_GMII_FLEX_SPD; | ||
5761 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); | ||
5762 | if(ret_val) | ||
5763 | return ret_val; | ||
5764 | } else { | ||
5765 | phy_data |= IGP02E1000_PM_D3_LPLU; | ||
5766 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, | ||
5767 | phy_data); | ||
5768 | if (ret_val) | ||
5769 | return ret_val; | ||
5770 | } | ||
5771 | |||
5772 | /* When LPLU is enabled we should disable SmartSpeed */ | ||
5773 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); | ||
5774 | if(ret_val) | ||
5775 | return ret_val; | ||
5776 | |||
5777 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | ||
5778 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); | ||
5241 | if(ret_val) | 5779 | if(ret_val) |
5242 | return ret_val; | 5780 | return ret_val; |
5243 | 5781 | ||
5782 | } | ||
5783 | return E1000_SUCCESS; | ||
5784 | } | ||
5785 | |||
5786 | /***************************************************************************** | ||
5787 | * | ||
5788 | * This function sets the lplu d0 state according to the active flag. When | ||
5789 | * activating lplu this function also disables smart speed and vise versa. | ||
5790 | * lplu will not be activated unless the device autonegotiation advertisment | ||
5791 | * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. | ||
5792 | * hw: Struct containing variables accessed by shared code | ||
5793 | * active - true to enable lplu false to disable lplu. | ||
5794 | * | ||
5795 | * returns: - E1000_ERR_PHY if fail to read/write the PHY | ||
5796 | * E1000_SUCCESS at any other case. | ||
5797 | * | ||
5798 | ****************************************************************************/ | ||
5799 | |||
5800 | int32_t | ||
5801 | e1000_set_d0_lplu_state(struct e1000_hw *hw, | ||
5802 | boolean_t active) | ||
5803 | { | ||
5804 | int32_t ret_val; | ||
5805 | uint16_t phy_data; | ||
5806 | DEBUGFUNC("e1000_set_d0_lplu_state"); | ||
5807 | |||
5808 | if(hw->mac_type <= e1000_82547_rev_2) | ||
5809 | return E1000_SUCCESS; | ||
5810 | |||
5811 | ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); | ||
5812 | if(ret_val) | ||
5813 | return ret_val; | ||
5814 | |||
5815 | if (!active) { | ||
5816 | phy_data &= ~IGP02E1000_PM_D0_LPLU; | ||
5817 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); | ||
5818 | if (ret_val) | ||
5819 | return ret_val; | ||
5820 | |||
5821 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during | ||
5822 | * Dx states where the power conservation is most important. During | ||
5823 | * driver activity we should enable SmartSpeed, so performance is | ||
5824 | * maintained. */ | ||
5825 | if (hw->smart_speed == e1000_smart_speed_on) { | ||
5826 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | ||
5827 | &phy_data); | ||
5828 | if(ret_val) | ||
5829 | return ret_val; | ||
5830 | |||
5831 | phy_data |= IGP01E1000_PSCFR_SMART_SPEED; | ||
5832 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | ||
5833 | phy_data); | ||
5834 | if(ret_val) | ||
5835 | return ret_val; | ||
5836 | } else if (hw->smart_speed == e1000_smart_speed_off) { | ||
5837 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | ||
5838 | &phy_data); | ||
5839 | if (ret_val) | ||
5840 | return ret_val; | ||
5841 | |||
5842 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; | ||
5843 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, | ||
5844 | phy_data); | ||
5845 | if(ret_val) | ||
5846 | return ret_val; | ||
5847 | } | ||
5848 | |||
5849 | |||
5850 | } else { | ||
5851 | |||
5852 | phy_data |= IGP02E1000_PM_D0_LPLU; | ||
5853 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); | ||
5854 | if (ret_val) | ||
5855 | return ret_val; | ||
5856 | |||
5244 | /* When LPLU is enabled we should disable SmartSpeed */ | 5857 | /* When LPLU is enabled we should disable SmartSpeed */ |
5245 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); | 5858 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); |
5246 | if(ret_val) | 5859 | if(ret_val) |
@@ -5318,6 +5931,338 @@ e1000_set_vco_speed(struct e1000_hw *hw) | |||
5318 | return E1000_SUCCESS; | 5931 | return E1000_SUCCESS; |
5319 | } | 5932 | } |
5320 | 5933 | ||
5934 | |||
5935 | /***************************************************************************** | ||
5936 | * This function reads the cookie from ARC ram. | ||
5937 | * | ||
5938 | * returns: - E1000_SUCCESS . | ||
5939 | ****************************************************************************/ | ||
5940 | int32_t | ||
5941 | e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer) | ||
5942 | { | ||
5943 | uint8_t i; | ||
5944 | uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; | ||
5945 | uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; | ||
5946 | |||
5947 | length = (length >> 2); | ||
5948 | offset = (offset >> 2); | ||
5949 | |||
5950 | for (i = 0; i < length; i++) { | ||
5951 | *((uint32_t *) buffer + i) = | ||
5952 | E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); | ||
5953 | } | ||
5954 | return E1000_SUCCESS; | ||
5955 | } | ||
5956 | |||
5957 | |||
5958 | /***************************************************************************** | ||
5959 | * This function checks whether the HOST IF is enabled for command operaton | ||
5960 | * and also checks whether the previous command is completed. | ||
5961 | * It busy waits in case of previous command is not completed. | ||
5962 | * | ||
5963 | * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or | ||
5964 | * timeout | ||
5965 | * - E1000_SUCCESS for success. | ||
5966 | ****************************************************************************/ | ||
5967 | int32_t | ||
5968 | e1000_mng_enable_host_if(struct e1000_hw * hw) | ||
5969 | { | ||
5970 | uint32_t hicr; | ||
5971 | uint8_t i; | ||
5972 | |||
5973 | /* Check that the host interface is enabled. */ | ||
5974 | hicr = E1000_READ_REG(hw, HICR); | ||
5975 | if ((hicr & E1000_HICR_EN) == 0) { | ||
5976 | DEBUGOUT("E1000_HOST_EN bit disabled.\n"); | ||
5977 | return -E1000_ERR_HOST_INTERFACE_COMMAND; | ||
5978 | } | ||
5979 | /* check the previous command is completed */ | ||
5980 | for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { | ||
5981 | hicr = E1000_READ_REG(hw, HICR); | ||
5982 | if (!(hicr & E1000_HICR_C)) | ||
5983 | break; | ||
5984 | msec_delay_irq(1); | ||
5985 | } | ||
5986 | |||
5987 | if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { | ||
5988 | DEBUGOUT("Previous command timeout failed .\n"); | ||
5989 | return -E1000_ERR_HOST_INTERFACE_COMMAND; | ||
5990 | } | ||
5991 | return E1000_SUCCESS; | ||
5992 | } | ||
5993 | |||
5994 | /***************************************************************************** | ||
5995 | * This function writes the buffer content at the offset given on the host if. | ||
5996 | * It also does alignment considerations to do the writes in most efficient way. | ||
5997 | * Also fills up the sum of the buffer in *buffer parameter. | ||
5998 | * | ||
5999 | * returns - E1000_SUCCESS for success. | ||
6000 | ****************************************************************************/ | ||
6001 | int32_t | ||
6002 | e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer, | ||
6003 | uint16_t length, uint16_t offset, uint8_t *sum) | ||
6004 | { | ||
6005 | uint8_t *tmp; | ||
6006 | uint8_t *bufptr = buffer; | ||
6007 | uint32_t data; | ||
6008 | uint16_t remaining, i, j, prev_bytes; | ||
6009 | |||
6010 | /* sum = only sum of the data and it is not checksum */ | ||
6011 | |||
6012 | if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) { | ||
6013 | return -E1000_ERR_PARAM; | ||
6014 | } | ||
6015 | |||
6016 | tmp = (uint8_t *)&data; | ||
6017 | prev_bytes = offset & 0x3; | ||
6018 | offset &= 0xFFFC; | ||
6019 | offset >>= 2; | ||
6020 | |||
6021 | if (prev_bytes) { | ||
6022 | data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset); | ||
6023 | for (j = prev_bytes; j < sizeof(uint32_t); j++) { | ||
6024 | *(tmp + j) = *bufptr++; | ||
6025 | *sum += *(tmp + j); | ||
6026 | } | ||
6027 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data); | ||
6028 | length -= j - prev_bytes; | ||
6029 | offset++; | ||
6030 | } | ||
6031 | |||
6032 | remaining = length & 0x3; | ||
6033 | length -= remaining; | ||
6034 | |||
6035 | /* Calculate length in DWORDs */ | ||
6036 | length >>= 2; | ||
6037 | |||
6038 | /* The device driver writes the relevant command block into the | ||
6039 | * ram area. */ | ||
6040 | for (i = 0; i < length; i++) { | ||
6041 | for (j = 0; j < sizeof(uint32_t); j++) { | ||
6042 | *(tmp + j) = *bufptr++; | ||
6043 | *sum += *(tmp + j); | ||
6044 | } | ||
6045 | |||
6046 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); | ||
6047 | } | ||
6048 | if (remaining) { | ||
6049 | for (j = 0; j < sizeof(uint32_t); j++) { | ||
6050 | if (j < remaining) | ||
6051 | *(tmp + j) = *bufptr++; | ||
6052 | else | ||
6053 | *(tmp + j) = 0; | ||
6054 | |||
6055 | *sum += *(tmp + j); | ||
6056 | } | ||
6057 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); | ||
6058 | } | ||
6059 | |||
6060 | return E1000_SUCCESS; | ||
6061 | } | ||
6062 | |||
6063 | |||
6064 | /***************************************************************************** | ||
6065 | * This function writes the command header after does the checksum calculation. | ||
6066 | * | ||
6067 | * returns - E1000_SUCCESS for success. | ||
6068 | ****************************************************************************/ | ||
6069 | int32_t | ||
6070 | e1000_mng_write_cmd_header(struct e1000_hw * hw, | ||
6071 | struct e1000_host_mng_command_header * hdr) | ||
6072 | { | ||
6073 | uint16_t i; | ||
6074 | uint8_t sum; | ||
6075 | uint8_t *buffer; | ||
6076 | |||
6077 | /* Write the whole command header structure which includes sum of | ||
6078 | * the buffer */ | ||
6079 | |||
6080 | uint16_t length = sizeof(struct e1000_host_mng_command_header); | ||
6081 | |||
6082 | sum = hdr->checksum; | ||
6083 | hdr->checksum = 0; | ||
6084 | |||
6085 | buffer = (uint8_t *) hdr; | ||
6086 | i = length; | ||
6087 | while(i--) | ||
6088 | sum += buffer[i]; | ||
6089 | |||
6090 | hdr->checksum = 0 - sum; | ||
6091 | |||
6092 | length >>= 2; | ||
6093 | /* The device driver writes the relevant command block into the ram area. */ | ||
6094 | for (i = 0; i < length; i++) | ||
6095 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i)); | ||
6096 | |||
6097 | return E1000_SUCCESS; | ||
6098 | } | ||
6099 | |||
6100 | |||
6101 | /***************************************************************************** | ||
6102 | * This function indicates to ARC that a new command is pending which completes | ||
6103 | * one write operation by the driver. | ||
6104 | * | ||
6105 | * returns - E1000_SUCCESS for success. | ||
6106 | ****************************************************************************/ | ||
6107 | int32_t | ||
6108 | e1000_mng_write_commit( | ||
6109 | struct e1000_hw * hw) | ||
6110 | { | ||
6111 | uint32_t hicr; | ||
6112 | |||
6113 | hicr = E1000_READ_REG(hw, HICR); | ||
6114 | /* Setting this bit tells the ARC that a new command is pending. */ | ||
6115 | E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C); | ||
6116 | |||
6117 | return E1000_SUCCESS; | ||
6118 | } | ||
6119 | |||
6120 | |||
6121 | /***************************************************************************** | ||
6122 | * This function checks the mode of the firmware. | ||
6123 | * | ||
6124 | * returns - TRUE when the mode is IAMT or FALSE. | ||
6125 | ****************************************************************************/ | ||
6126 | boolean_t | ||
6127 | e1000_check_mng_mode( | ||
6128 | struct e1000_hw *hw) | ||
6129 | { | ||
6130 | uint32_t fwsm; | ||
6131 | |||
6132 | fwsm = E1000_READ_REG(hw, FWSM); | ||
6133 | |||
6134 | if((fwsm & E1000_FWSM_MODE_MASK) == | ||
6135 | (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) | ||
6136 | return TRUE; | ||
6137 | |||
6138 | return FALSE; | ||
6139 | } | ||
6140 | |||
6141 | |||
6142 | /***************************************************************************** | ||
6143 | * This function writes the dhcp info . | ||
6144 | ****************************************************************************/ | ||
6145 | int32_t | ||
6146 | e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer, | ||
6147 | uint16_t length) | ||
6148 | { | ||
6149 | int32_t ret_val; | ||
6150 | struct e1000_host_mng_command_header hdr; | ||
6151 | |||
6152 | hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; | ||
6153 | hdr.command_length = length; | ||
6154 | hdr.reserved1 = 0; | ||
6155 | hdr.reserved2 = 0; | ||
6156 | hdr.checksum = 0; | ||
6157 | |||
6158 | ret_val = e1000_mng_enable_host_if(hw); | ||
6159 | if (ret_val == E1000_SUCCESS) { | ||
6160 | ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr), | ||
6161 | &(hdr.checksum)); | ||
6162 | if (ret_val == E1000_SUCCESS) { | ||
6163 | ret_val = e1000_mng_write_cmd_header(hw, &hdr); | ||
6164 | if (ret_val == E1000_SUCCESS) | ||
6165 | ret_val = e1000_mng_write_commit(hw); | ||
6166 | } | ||
6167 | } | ||
6168 | return ret_val; | ||
6169 | } | ||
6170 | |||
6171 | |||
6172 | /***************************************************************************** | ||
6173 | * This function calculates the checksum. | ||
6174 | * | ||
6175 | * returns - checksum of buffer contents. | ||
6176 | ****************************************************************************/ | ||
6177 | uint8_t | ||
6178 | e1000_calculate_mng_checksum(char *buffer, uint32_t length) | ||
6179 | { | ||
6180 | uint8_t sum = 0; | ||
6181 | uint32_t i; | ||
6182 | |||
6183 | if (!buffer) | ||
6184 | return 0; | ||
6185 | |||
6186 | for (i=0; i < length; i++) | ||
6187 | sum += buffer[i]; | ||
6188 | |||
6189 | return (uint8_t) (0 - sum); | ||
6190 | } | ||
6191 | |||
6192 | /***************************************************************************** | ||
6193 | * This function checks whether tx pkt filtering needs to be enabled or not. | ||
6194 | * | ||
6195 | * returns - TRUE for packet filtering or FALSE. | ||
6196 | ****************************************************************************/ | ||
6197 | boolean_t | ||
6198 | e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) | ||
6199 | { | ||
6200 | /* called in init as well as watchdog timer functions */ | ||
6201 | |||
6202 | int32_t ret_val, checksum; | ||
6203 | boolean_t tx_filter = FALSE; | ||
6204 | struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); | ||
6205 | uint8_t *buffer = (uint8_t *) &(hw->mng_cookie); | ||
6206 | |||
6207 | if (e1000_check_mng_mode(hw)) { | ||
6208 | ret_val = e1000_mng_enable_host_if(hw); | ||
6209 | if (ret_val == E1000_SUCCESS) { | ||
6210 | ret_val = e1000_host_if_read_cookie(hw, buffer); | ||
6211 | if (ret_val == E1000_SUCCESS) { | ||
6212 | checksum = hdr->checksum; | ||
6213 | hdr->checksum = 0; | ||
6214 | if ((hdr->signature == E1000_IAMT_SIGNATURE) && | ||
6215 | checksum == e1000_calculate_mng_checksum((char *)buffer, | ||
6216 | E1000_MNG_DHCP_COOKIE_LENGTH)) { | ||
6217 | if (hdr->status & | ||
6218 | E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) | ||
6219 | tx_filter = TRUE; | ||
6220 | } else | ||
6221 | tx_filter = TRUE; | ||
6222 | } else | ||
6223 | tx_filter = TRUE; | ||
6224 | } | ||
6225 | } | ||
6226 | |||
6227 | hw->tx_pkt_filtering = tx_filter; | ||
6228 | return tx_filter; | ||
6229 | } | ||
6230 | |||
6231 | /****************************************************************************** | ||
6232 | * Verifies the hardware needs to allow ARPs to be processed by the host | ||
6233 | * | ||
6234 | * hw - Struct containing variables accessed by shared code | ||
6235 | * | ||
6236 | * returns: - TRUE/FALSE | ||
6237 | * | ||
6238 | *****************************************************************************/ | ||
6239 | uint32_t | ||
6240 | e1000_enable_mng_pass_thru(struct e1000_hw *hw) | ||
6241 | { | ||
6242 | uint32_t manc; | ||
6243 | uint32_t fwsm, factps; | ||
6244 | |||
6245 | if (hw->asf_firmware_present) { | ||
6246 | manc = E1000_READ_REG(hw, MANC); | ||
6247 | |||
6248 | if (!(manc & E1000_MANC_RCV_TCO_EN) || | ||
6249 | !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) | ||
6250 | return FALSE; | ||
6251 | if (e1000_arc_subsystem_valid(hw) == TRUE) { | ||
6252 | fwsm = E1000_READ_REG(hw, FWSM); | ||
6253 | factps = E1000_READ_REG(hw, FACTPS); | ||
6254 | |||
6255 | if (((fwsm & E1000_FWSM_MODE_MASK) == | ||
6256 | (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) && | ||
6257 | (factps & E1000_FACTPS_MNGCG)) | ||
6258 | return TRUE; | ||
6259 | } else | ||
6260 | if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) | ||
6261 | return TRUE; | ||
6262 | } | ||
6263 | return FALSE; | ||
6264 | } | ||
6265 | |||
5321 | static int32_t | 6266 | static int32_t |
5322 | e1000_polarity_reversal_workaround(struct e1000_hw *hw) | 6267 | e1000_polarity_reversal_workaround(struct e1000_hw *hw) |
5323 | { | 6268 | { |
@@ -5403,3 +6348,265 @@ e1000_polarity_reversal_workaround(struct e1000_hw *hw) | |||
5403 | return E1000_SUCCESS; | 6348 | return E1000_SUCCESS; |
5404 | } | 6349 | } |
5405 | 6350 | ||
6351 | /*************************************************************************** | ||
6352 | * | ||
6353 | * Disables PCI-Express master access. | ||
6354 | * | ||
6355 | * hw: Struct containing variables accessed by shared code | ||
6356 | * | ||
6357 | * returns: - none. | ||
6358 | * | ||
6359 | ***************************************************************************/ | ||
6360 | void | ||
6361 | e1000_set_pci_express_master_disable(struct e1000_hw *hw) | ||
6362 | { | ||
6363 | uint32_t ctrl; | ||
6364 | |||
6365 | DEBUGFUNC("e1000_set_pci_express_master_disable"); | ||
6366 | |||
6367 | if (hw->bus_type != e1000_bus_type_pci_express) | ||
6368 | return; | ||
6369 | |||
6370 | ctrl = E1000_READ_REG(hw, CTRL); | ||
6371 | ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; | ||
6372 | E1000_WRITE_REG(hw, CTRL, ctrl); | ||
6373 | } | ||
6374 | |||
6375 | /*************************************************************************** | ||
6376 | * | ||
6377 | * Enables PCI-Express master access. | ||
6378 | * | ||
6379 | * hw: Struct containing variables accessed by shared code | ||
6380 | * | ||
6381 | * returns: - none. | ||
6382 | * | ||
6383 | ***************************************************************************/ | ||
6384 | void | ||
6385 | e1000_enable_pciex_master(struct e1000_hw *hw) | ||
6386 | { | ||
6387 | uint32_t ctrl; | ||
6388 | |||
6389 | DEBUGFUNC("e1000_enable_pciex_master"); | ||
6390 | |||
6391 | if (hw->bus_type != e1000_bus_type_pci_express) | ||
6392 | return; | ||
6393 | |||
6394 | ctrl = E1000_READ_REG(hw, CTRL); | ||
6395 | ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE; | ||
6396 | E1000_WRITE_REG(hw, CTRL, ctrl); | ||
6397 | } | ||
6398 | |||
6399 | /******************************************************************************* | ||
6400 | * | ||
6401 | * Disables PCI-Express master access and verifies there are no pending requests | ||
6402 | * | ||
6403 | * hw: Struct containing variables accessed by shared code | ||
6404 | * | ||
6405 | * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't | ||
6406 | * caused the master requests to be disabled. | ||
6407 | * E1000_SUCCESS master requests disabled. | ||
6408 | * | ||
6409 | ******************************************************************************/ | ||
6410 | int32_t | ||
6411 | e1000_disable_pciex_master(struct e1000_hw *hw) | ||
6412 | { | ||
6413 | int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ | ||
6414 | |||
6415 | DEBUGFUNC("e1000_disable_pciex_master"); | ||
6416 | |||
6417 | if (hw->bus_type != e1000_bus_type_pci_express) | ||
6418 | return E1000_SUCCESS; | ||
6419 | |||
6420 | e1000_set_pci_express_master_disable(hw); | ||
6421 | |||
6422 | while(timeout) { | ||
6423 | if(!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) | ||
6424 | break; | ||
6425 | else | ||
6426 | udelay(100); | ||
6427 | timeout--; | ||
6428 | } | ||
6429 | |||
6430 | if(!timeout) { | ||
6431 | DEBUGOUT("Master requests are pending.\n"); | ||
6432 | return -E1000_ERR_MASTER_REQUESTS_PENDING; | ||
6433 | } | ||
6434 | |||
6435 | return E1000_SUCCESS; | ||
6436 | } | ||
6437 | |||
6438 | /******************************************************************************* | ||
6439 | * | ||
6440 | * Check for EEPROM Auto Read bit done. | ||
6441 | * | ||
6442 | * hw: Struct containing variables accessed by shared code | ||
6443 | * | ||
6444 | * returns: - E1000_ERR_RESET if fail to reset MAC | ||
6445 | * E1000_SUCCESS at any other case. | ||
6446 | * | ||
6447 | ******************************************************************************/ | ||
6448 | int32_t | ||
6449 | e1000_get_auto_rd_done(struct e1000_hw *hw) | ||
6450 | { | ||
6451 | int32_t timeout = AUTO_READ_DONE_TIMEOUT; | ||
6452 | |||
6453 | DEBUGFUNC("e1000_get_auto_rd_done"); | ||
6454 | |||
6455 | switch (hw->mac_type) { | ||
6456 | default: | ||
6457 | msec_delay(5); | ||
6458 | break; | ||
6459 | case e1000_82573: | ||
6460 | while(timeout) { | ||
6461 | if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) break; | ||
6462 | else msec_delay(1); | ||
6463 | timeout--; | ||
6464 | } | ||
6465 | |||
6466 | if(!timeout) { | ||
6467 | DEBUGOUT("Auto read by HW from EEPROM has not completed.\n"); | ||
6468 | return -E1000_ERR_RESET; | ||
6469 | } | ||
6470 | break; | ||
6471 | } | ||
6472 | |||
6473 | return E1000_SUCCESS; | ||
6474 | } | ||
6475 | |||
6476 | /*************************************************************************** | ||
6477 | * Checks if the PHY configuration is done | ||
6478 | * | ||
6479 | * hw: Struct containing variables accessed by shared code | ||
6480 | * | ||
6481 | * returns: - E1000_ERR_RESET if fail to reset MAC | ||
6482 | * E1000_SUCCESS at any other case. | ||
6483 | * | ||
6484 | ***************************************************************************/ | ||
6485 | int32_t | ||
6486 | e1000_get_phy_cfg_done(struct e1000_hw *hw) | ||
6487 | { | ||
6488 | DEBUGFUNC("e1000_get_phy_cfg_done"); | ||
6489 | |||
6490 | /* Simply wait for 10ms */ | ||
6491 | msec_delay(10); | ||
6492 | |||
6493 | return E1000_SUCCESS; | ||
6494 | } | ||
6495 | |||
6496 | /*************************************************************************** | ||
6497 | * | ||
6498 | * Using the combination of SMBI and SWESMBI semaphore bits when resetting | ||
6499 | * adapter or Eeprom access. | ||
6500 | * | ||
6501 | * hw: Struct containing variables accessed by shared code | ||
6502 | * | ||
6503 | * returns: - E1000_ERR_EEPROM if fail to access EEPROM. | ||
6504 | * E1000_SUCCESS at any other case. | ||
6505 | * | ||
6506 | ***************************************************************************/ | ||
6507 | int32_t | ||
6508 | e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) | ||
6509 | { | ||
6510 | int32_t timeout; | ||
6511 | uint32_t swsm; | ||
6512 | |||
6513 | DEBUGFUNC("e1000_get_hw_eeprom_semaphore"); | ||
6514 | |||
6515 | if(!hw->eeprom_semaphore_present) | ||
6516 | return E1000_SUCCESS; | ||
6517 | |||
6518 | |||
6519 | /* Get the FW semaphore. */ | ||
6520 | timeout = hw->eeprom.word_size + 1; | ||
6521 | while(timeout) { | ||
6522 | swsm = E1000_READ_REG(hw, SWSM); | ||
6523 | swsm |= E1000_SWSM_SWESMBI; | ||
6524 | E1000_WRITE_REG(hw, SWSM, swsm); | ||
6525 | /* if we managed to set the bit we got the semaphore. */ | ||
6526 | swsm = E1000_READ_REG(hw, SWSM); | ||
6527 | if(swsm & E1000_SWSM_SWESMBI) | ||
6528 | break; | ||
6529 | |||
6530 | udelay(50); | ||
6531 | timeout--; | ||
6532 | } | ||
6533 | |||
6534 | if(!timeout) { | ||
6535 | /* Release semaphores */ | ||
6536 | e1000_put_hw_eeprom_semaphore(hw); | ||
6537 | DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n"); | ||
6538 | return -E1000_ERR_EEPROM; | ||
6539 | } | ||
6540 | |||
6541 | return E1000_SUCCESS; | ||
6542 | } | ||
6543 | |||
6544 | /*************************************************************************** | ||
6545 | * This function clears HW semaphore bits. | ||
6546 | * | ||
6547 | * hw: Struct containing variables accessed by shared code | ||
6548 | * | ||
6549 | * returns: - None. | ||
6550 | * | ||
6551 | ***************************************************************************/ | ||
6552 | void | ||
6553 | e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) | ||
6554 | { | ||
6555 | uint32_t swsm; | ||
6556 | |||
6557 | DEBUGFUNC("e1000_put_hw_eeprom_semaphore"); | ||
6558 | |||
6559 | if(!hw->eeprom_semaphore_present) | ||
6560 | return; | ||
6561 | |||
6562 | swsm = E1000_READ_REG(hw, SWSM); | ||
6563 | /* Release both semaphores. */ | ||
6564 | swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); | ||
6565 | E1000_WRITE_REG(hw, SWSM, swsm); | ||
6566 | } | ||
6567 | |||
6568 | /****************************************************************************** | ||
6569 | * Checks if PHY reset is blocked due to SOL/IDER session, for example. | ||
6570 | * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to | ||
6571 | * the caller to figure out how to deal with it. | ||
6572 | * | ||
6573 | * hw - Struct containing variables accessed by shared code | ||
6574 | * | ||
6575 | * returns: - E1000_BLK_PHY_RESET | ||
6576 | * E1000_SUCCESS | ||
6577 | * | ||
6578 | *****************************************************************************/ | ||
6579 | int32_t | ||
6580 | e1000_check_phy_reset_block(struct e1000_hw *hw) | ||
6581 | { | ||
6582 | uint32_t manc = 0; | ||
6583 | if(hw->mac_type > e1000_82547_rev_2) | ||
6584 | manc = E1000_READ_REG(hw, MANC); | ||
6585 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? | ||
6586 | E1000_BLK_PHY_RESET : E1000_SUCCESS; | ||
6587 | } | ||
6588 | |||
6589 | uint8_t | ||
6590 | e1000_arc_subsystem_valid(struct e1000_hw *hw) | ||
6591 | { | ||
6592 | uint32_t fwsm; | ||
6593 | |||
6594 | /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC | ||
6595 | * may not be provided a DMA clock when no manageability features are | ||
6596 | * enabled. We do not want to perform any reads/writes to these registers | ||
6597 | * if this is the case. We read FWSM to determine the manageability mode. | ||
6598 | */ | ||
6599 | switch (hw->mac_type) { | ||
6600 | case e1000_82573: | ||
6601 | fwsm = E1000_READ_REG(hw, FWSM); | ||
6602 | if((fwsm & E1000_FWSM_MODE_MASK) != 0) | ||
6603 | return TRUE; | ||
6604 | break; | ||
6605 | default: | ||
6606 | break; | ||
6607 | } | ||
6608 | return FALSE; | ||
6609 | } | ||
6610 | |||
6611 | |||
6612 | |||
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h index f397e637a3c5..a0263ee96c6b 100644 --- a/drivers/net/e1000/e1000_hw.h +++ b/drivers/net/e1000/e1000_hw.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /******************************************************************************* | 1 | /******************************************************************************* |
2 | 2 | ||
3 | 3 | ||
4 | Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved. | 4 | Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. |
5 | 5 | ||
6 | This program is free software; you can redistribute it and/or modify it | 6 | This program is free software; you can redistribute it and/or modify it |
7 | under the terms of the GNU General Public License as published by the Free | 7 | under the terms of the GNU General Public License as published by the Free |
@@ -57,6 +57,7 @@ typedef enum { | |||
57 | e1000_82541_rev_2, | 57 | e1000_82541_rev_2, |
58 | e1000_82547, | 58 | e1000_82547, |
59 | e1000_82547_rev_2, | 59 | e1000_82547_rev_2, |
60 | e1000_82573, | ||
60 | e1000_num_macs | 61 | e1000_num_macs |
61 | } e1000_mac_type; | 62 | } e1000_mac_type; |
62 | 63 | ||
@@ -64,6 +65,7 @@ typedef enum { | |||
64 | e1000_eeprom_uninitialized = 0, | 65 | e1000_eeprom_uninitialized = 0, |
65 | e1000_eeprom_spi, | 66 | e1000_eeprom_spi, |
66 | e1000_eeprom_microwire, | 67 | e1000_eeprom_microwire, |
68 | e1000_eeprom_flash, | ||
67 | e1000_num_eeprom_types | 69 | e1000_num_eeprom_types |
68 | } e1000_eeprom_type; | 70 | } e1000_eeprom_type; |
69 | 71 | ||
@@ -96,6 +98,7 @@ typedef enum { | |||
96 | e1000_bus_type_unknown = 0, | 98 | e1000_bus_type_unknown = 0, |
97 | e1000_bus_type_pci, | 99 | e1000_bus_type_pci, |
98 | e1000_bus_type_pcix, | 100 | e1000_bus_type_pcix, |
101 | e1000_bus_type_pci_express, | ||
99 | e1000_bus_type_reserved | 102 | e1000_bus_type_reserved |
100 | } e1000_bus_type; | 103 | } e1000_bus_type; |
101 | 104 | ||
@@ -107,6 +110,7 @@ typedef enum { | |||
107 | e1000_bus_speed_100, | 110 | e1000_bus_speed_100, |
108 | e1000_bus_speed_120, | 111 | e1000_bus_speed_120, |
109 | e1000_bus_speed_133, | 112 | e1000_bus_speed_133, |
113 | e1000_bus_speed_2500, | ||
110 | e1000_bus_speed_reserved | 114 | e1000_bus_speed_reserved |
111 | } e1000_bus_speed; | 115 | } e1000_bus_speed; |
112 | 116 | ||
@@ -115,6 +119,8 @@ typedef enum { | |||
115 | e1000_bus_width_unknown = 0, | 119 | e1000_bus_width_unknown = 0, |
116 | e1000_bus_width_32, | 120 | e1000_bus_width_32, |
117 | e1000_bus_width_64, | 121 | e1000_bus_width_64, |
122 | e1000_bus_width_pciex_1, | ||
123 | e1000_bus_width_pciex_4, | ||
118 | e1000_bus_width_reserved | 124 | e1000_bus_width_reserved |
119 | } e1000_bus_width; | 125 | } e1000_bus_width; |
120 | 126 | ||
@@ -196,6 +202,7 @@ typedef enum { | |||
196 | typedef enum { | 202 | typedef enum { |
197 | e1000_phy_m88 = 0, | 203 | e1000_phy_m88 = 0, |
198 | e1000_phy_igp, | 204 | e1000_phy_igp, |
205 | e1000_phy_igp_2, | ||
199 | e1000_phy_undefined = 0xFF | 206 | e1000_phy_undefined = 0xFF |
200 | } e1000_phy_type; | 207 | } e1000_phy_type; |
201 | 208 | ||
@@ -242,8 +249,19 @@ struct e1000_eeprom_info { | |||
242 | uint16_t address_bits; | 249 | uint16_t address_bits; |
243 | uint16_t delay_usec; | 250 | uint16_t delay_usec; |
244 | uint16_t page_size; | 251 | uint16_t page_size; |
252 | boolean_t use_eerd; | ||
253 | boolean_t use_eewr; | ||
245 | }; | 254 | }; |
246 | 255 | ||
256 | /* Flex ASF Information */ | ||
257 | #define E1000_HOST_IF_MAX_SIZE 2048 | ||
258 | |||
259 | typedef enum { | ||
260 | e1000_byte_align = 0, | ||
261 | e1000_word_align = 1, | ||
262 | e1000_dword_align = 2 | ||
263 | } e1000_align_type; | ||
264 | |||
247 | 265 | ||
248 | 266 | ||
249 | /* Error Codes */ | 267 | /* Error Codes */ |
@@ -254,11 +272,16 @@ struct e1000_eeprom_info { | |||
254 | #define E1000_ERR_PARAM 4 | 272 | #define E1000_ERR_PARAM 4 |
255 | #define E1000_ERR_MAC_TYPE 5 | 273 | #define E1000_ERR_MAC_TYPE 5 |
256 | #define E1000_ERR_PHY_TYPE 6 | 274 | #define E1000_ERR_PHY_TYPE 6 |
275 | #define E1000_ERR_RESET 9 | ||
276 | #define E1000_ERR_MASTER_REQUESTS_PENDING 10 | ||
277 | #define E1000_ERR_HOST_INTERFACE_COMMAND 11 | ||
278 | #define E1000_BLK_PHY_RESET 12 | ||
257 | 279 | ||
258 | /* Function prototypes */ | 280 | /* Function prototypes */ |
259 | /* Initialization */ | 281 | /* Initialization */ |
260 | int32_t e1000_reset_hw(struct e1000_hw *hw); | 282 | int32_t e1000_reset_hw(struct e1000_hw *hw); |
261 | int32_t e1000_init_hw(struct e1000_hw *hw); | 283 | int32_t e1000_init_hw(struct e1000_hw *hw); |
284 | int32_t e1000_id_led_init(struct e1000_hw * hw); | ||
262 | int32_t e1000_set_mac_type(struct e1000_hw *hw); | 285 | int32_t e1000_set_mac_type(struct e1000_hw *hw); |
263 | void e1000_set_media_type(struct e1000_hw *hw); | 286 | void e1000_set_media_type(struct e1000_hw *hw); |
264 | 287 | ||
@@ -275,7 +298,7 @@ int32_t e1000_force_mac_fc(struct e1000_hw *hw); | |||
275 | /* PHY */ | 298 | /* PHY */ |
276 | int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data); | 299 | int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data); |
277 | int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data); | 300 | int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data); |
278 | void e1000_phy_hw_reset(struct e1000_hw *hw); | 301 | int32_t e1000_phy_hw_reset(struct e1000_hw *hw); |
279 | int32_t e1000_phy_reset(struct e1000_hw *hw); | 302 | int32_t e1000_phy_reset(struct e1000_hw *hw); |
280 | int32_t e1000_detect_gig_phy(struct e1000_hw *hw); | 303 | int32_t e1000_detect_gig_phy(struct e1000_hw *hw); |
281 | int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); | 304 | int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); |
@@ -287,13 +310,86 @@ int32_t e1000_check_downshift(struct e1000_hw *hw); | |||
287 | int32_t e1000_validate_mdi_setting(struct e1000_hw *hw); | 310 | int32_t e1000_validate_mdi_setting(struct e1000_hw *hw); |
288 | 311 | ||
289 | /* EEPROM Functions */ | 312 | /* EEPROM Functions */ |
290 | void e1000_init_eeprom_params(struct e1000_hw *hw); | 313 | int32_t e1000_init_eeprom_params(struct e1000_hw *hw); |
314 | boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw); | ||
315 | int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); | ||
316 | int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); | ||
317 | int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd); | ||
318 | |||
319 | /* MNG HOST IF functions */ | ||
320 | uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw); | ||
321 | |||
322 | #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 | ||
323 | #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */ | ||
324 | |||
325 | #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */ | ||
326 | #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */ | ||
327 | #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */ | ||
328 | #define E1000_MNG_IAMT_MODE 0x3 | ||
329 | #define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */ | ||
330 | |||
331 | #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */ | ||
332 | #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2 /* DHCP parsing enabled */ | ||
333 | #define E1000_VFTA_ENTRY_SHIFT 0x5 | ||
334 | #define E1000_VFTA_ENTRY_MASK 0x7F | ||
335 | #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F | ||
336 | |||
337 | struct e1000_host_mng_command_header { | ||
338 | uint8_t command_id; | ||
339 | uint8_t checksum; | ||
340 | uint16_t reserved1; | ||
341 | uint16_t reserved2; | ||
342 | uint16_t command_length; | ||
343 | }; | ||
344 | |||
345 | struct e1000_host_mng_command_info { | ||
346 | struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ | ||
347 | uint8_t command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658*/ | ||
348 | }; | ||
349 | #ifdef __BIG_ENDIAN | ||
350 | struct e1000_host_mng_dhcp_cookie{ | ||
351 | uint32_t signature; | ||
352 | uint16_t vlan_id; | ||
353 | uint8_t reserved0; | ||
354 | uint8_t status; | ||
355 | uint32_t reserved1; | ||
356 | uint8_t checksum; | ||
357 | uint8_t reserved3; | ||
358 | uint16_t reserved2; | ||
359 | }; | ||
360 | #else | ||
361 | struct e1000_host_mng_dhcp_cookie{ | ||
362 | uint32_t signature; | ||
363 | uint8_t status; | ||
364 | uint8_t reserved0; | ||
365 | uint16_t vlan_id; | ||
366 | uint32_t reserved1; | ||
367 | uint16_t reserved2; | ||
368 | uint8_t reserved3; | ||
369 | uint8_t checksum; | ||
370 | }; | ||
371 | #endif | ||
372 | |||
373 | int32_t e1000_mng_write_dhcp_info(struct e1000_hw *hw, uint8_t *buffer, | ||
374 | uint16_t length); | ||
375 | boolean_t e1000_check_mng_mode(struct e1000_hw *hw); | ||
376 | boolean_t e1000_enable_tx_pkt_filtering(struct e1000_hw *hw); | ||
377 | int32_t e1000_mng_enable_host_if(struct e1000_hw *hw); | ||
378 | int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer, | ||
379 | uint16_t length, uint16_t offset, uint8_t *sum); | ||
380 | int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw, | ||
381 | struct e1000_host_mng_command_header* hdr); | ||
382 | |||
383 | int32_t e1000_mng_write_commit(struct e1000_hw *hw); | ||
384 | |||
291 | int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); | 385 | int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); |
292 | int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw); | 386 | int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw); |
293 | int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw); | 387 | int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw); |
294 | int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); | 388 | int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); |
295 | int32_t e1000_read_part_num(struct e1000_hw *hw, uint32_t * part_num); | 389 | int32_t e1000_read_part_num(struct e1000_hw *hw, uint32_t * part_num); |
296 | int32_t e1000_read_mac_addr(struct e1000_hw * hw); | 390 | int32_t e1000_read_mac_addr(struct e1000_hw * hw); |
391 | int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); | ||
392 | void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask); | ||
297 | 393 | ||
298 | /* Filters (multicast, vlan, receive) */ | 394 | /* Filters (multicast, vlan, receive) */ |
299 | void e1000_init_rx_addrs(struct e1000_hw *hw); | 395 | void e1000_init_rx_addrs(struct e1000_hw *hw); |
@@ -313,7 +409,6 @@ int32_t e1000_led_off(struct e1000_hw *hw); | |||
313 | /* Adaptive IFS Functions */ | 409 | /* Adaptive IFS Functions */ |
314 | 410 | ||
315 | /* Everything else */ | 411 | /* Everything else */ |
316 | uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw); | ||
317 | void e1000_clear_hw_cntrs(struct e1000_hw *hw); | 412 | void e1000_clear_hw_cntrs(struct e1000_hw *hw); |
318 | void e1000_reset_adaptive(struct e1000_hw *hw); | 413 | void e1000_reset_adaptive(struct e1000_hw *hw); |
319 | void e1000_update_adaptive(struct e1000_hw *hw); | 414 | void e1000_update_adaptive(struct e1000_hw *hw); |
@@ -330,6 +425,19 @@ void e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value); | |||
330 | void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value); | 425 | void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value); |
331 | int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up); | 426 | int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up); |
332 | int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active); | 427 | int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active); |
428 | int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active); | ||
429 | void e1000_set_pci_express_master_disable(struct e1000_hw *hw); | ||
430 | void e1000_enable_pciex_master(struct e1000_hw *hw); | ||
431 | int32_t e1000_disable_pciex_master(struct e1000_hw *hw); | ||
432 | int32_t e1000_get_auto_rd_done(struct e1000_hw *hw); | ||
433 | int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw); | ||
434 | int32_t e1000_get_software_semaphore(struct e1000_hw *hw); | ||
435 | void e1000_release_software_semaphore(struct e1000_hw *hw); | ||
436 | int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); | ||
437 | int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw); | ||
438 | void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); | ||
439 | int32_t e1000_commit_shadow_ram(struct e1000_hw *hw); | ||
440 | uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw); | ||
333 | 441 | ||
334 | #define E1000_READ_REG_IO(a, reg) \ | 442 | #define E1000_READ_REG_IO(a, reg) \ |
335 | e1000_read_reg_io((a), E1000_##reg) | 443 | e1000_read_reg_io((a), E1000_##reg) |
@@ -369,6 +477,10 @@ int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active); | |||
369 | #define E1000_DEV_ID_82546GB_SERDES 0x107B | 477 | #define E1000_DEV_ID_82546GB_SERDES 0x107B |
370 | #define E1000_DEV_ID_82546GB_PCIE 0x108A | 478 | #define E1000_DEV_ID_82546GB_PCIE 0x108A |
371 | #define E1000_DEV_ID_82547EI 0x1019 | 479 | #define E1000_DEV_ID_82547EI 0x1019 |
480 | #define E1000_DEV_ID_82573E 0x108B | ||
481 | #define E1000_DEV_ID_82573E_IAMT 0x108C | ||
482 | |||
483 | #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 | ||
372 | 484 | ||
373 | #define NODE_ADDRESS_SIZE 6 | 485 | #define NODE_ADDRESS_SIZE 6 |
374 | #define ETH_LENGTH_OF_ADDRESS 6 | 486 | #define ETH_LENGTH_OF_ADDRESS 6 |
@@ -381,6 +493,7 @@ int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active); | |||
381 | #define E1000_REVISION_0 0 | 493 | #define E1000_REVISION_0 0 |
382 | #define E1000_REVISION_1 1 | 494 | #define E1000_REVISION_1 1 |
383 | #define E1000_REVISION_2 2 | 495 | #define E1000_REVISION_2 2 |
496 | #define E1000_REVISION_3 3 | ||
384 | 497 | ||
385 | #define SPEED_10 10 | 498 | #define SPEED_10 10 |
386 | #define SPEED_100 100 | 499 | #define SPEED_100 100 |
@@ -437,6 +550,7 @@ int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active); | |||
437 | E1000_IMS_RXSEQ | \ | 550 | E1000_IMS_RXSEQ | \ |
438 | E1000_IMS_LSC) | 551 | E1000_IMS_LSC) |
439 | 552 | ||
553 | |||
440 | /* Number of high/low register pairs in the RAR. The RAR (Receive Address | 554 | /* Number of high/low register pairs in the RAR. The RAR (Receive Address |
441 | * Registers) holds the directed and multicast addresses that we monitor. We | 555 | * Registers) holds the directed and multicast addresses that we monitor. We |
442 | * reserve one of these spots for our directed address, allowing us room for | 556 | * reserve one of these spots for our directed address, allowing us room for |
@@ -457,14 +571,74 @@ struct e1000_rx_desc { | |||
457 | uint16_t special; | 571 | uint16_t special; |
458 | }; | 572 | }; |
459 | 573 | ||
574 | /* Receive Descriptor - Extended */ | ||
575 | union e1000_rx_desc_extended { | ||
576 | struct { | ||
577 | uint64_t buffer_addr; | ||
578 | uint64_t reserved; | ||
579 | } read; | ||
580 | struct { | ||
581 | struct { | ||
582 | uint32_t mrq; /* Multiple Rx Queues */ | ||
583 | union { | ||
584 | uint32_t rss; /* RSS Hash */ | ||
585 | struct { | ||
586 | uint16_t ip_id; /* IP id */ | ||
587 | uint16_t csum; /* Packet Checksum */ | ||
588 | } csum_ip; | ||
589 | } hi_dword; | ||
590 | } lower; | ||
591 | struct { | ||
592 | uint32_t status_error; /* ext status/error */ | ||
593 | uint16_t length; | ||
594 | uint16_t vlan; /* VLAN tag */ | ||
595 | } upper; | ||
596 | } wb; /* writeback */ | ||
597 | }; | ||
598 | |||
599 | #define MAX_PS_BUFFERS 4 | ||
600 | /* Receive Descriptor - Packet Split */ | ||
601 | union e1000_rx_desc_packet_split { | ||
602 | struct { | ||
603 | /* one buffer for protocol header(s), three data buffers */ | ||
604 | uint64_t buffer_addr[MAX_PS_BUFFERS]; | ||
605 | } read; | ||
606 | struct { | ||
607 | struct { | ||
608 | uint32_t mrq; /* Multiple Rx Queues */ | ||
609 | union { | ||
610 | uint32_t rss; /* RSS Hash */ | ||
611 | struct { | ||
612 | uint16_t ip_id; /* IP id */ | ||
613 | uint16_t csum; /* Packet Checksum */ | ||
614 | } csum_ip; | ||
615 | } hi_dword; | ||
616 | } lower; | ||
617 | struct { | ||
618 | uint32_t status_error; /* ext status/error */ | ||
619 | uint16_t length0; /* length of buffer 0 */ | ||
620 | uint16_t vlan; /* VLAN tag */ | ||
621 | } middle; | ||
622 | struct { | ||
623 | uint16_t header_status; | ||
624 | uint16_t length[3]; /* length of buffers 1-3 */ | ||
625 | } upper; | ||
626 | uint64_t reserved; | ||
627 | } wb; /* writeback */ | ||
628 | }; | ||
629 | |||
460 | /* Receive Decriptor bit definitions */ | 630 | /* Receive Decriptor bit definitions */ |
461 | #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ | 631 | #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ |
462 | #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ | 632 | #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ |
463 | #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ | 633 | #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ |
464 | #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ | 634 | #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ |
635 | #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */ | ||
465 | #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ | 636 | #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ |
466 | #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ | 637 | #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ |
467 | #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ | 638 | #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ |
639 | #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ | ||
640 | #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ | ||
641 | #define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ | ||
468 | #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ | 642 | #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ |
469 | #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ | 643 | #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ |
470 | #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ | 644 | #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ |
@@ -474,9 +648,20 @@ struct e1000_rx_desc { | |||
474 | #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ | 648 | #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ |
475 | #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ | 649 | #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ |
476 | #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ | 650 | #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ |
477 | #define E1000_RXD_SPC_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */ | 651 | #define E1000_RXD_SPC_PRI_SHIFT 13 |
478 | #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ | 652 | #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ |
479 | #define E1000_RXD_SPC_CFI_SHIFT 0x000C /* CFI is bit 12 */ | 653 | #define E1000_RXD_SPC_CFI_SHIFT 12 |
654 | |||
655 | #define E1000_RXDEXT_STATERR_CE 0x01000000 | ||
656 | #define E1000_RXDEXT_STATERR_SE 0x02000000 | ||
657 | #define E1000_RXDEXT_STATERR_SEQ 0x04000000 | ||
658 | #define E1000_RXDEXT_STATERR_CXE 0x10000000 | ||
659 | #define E1000_RXDEXT_STATERR_TCPE 0x20000000 | ||
660 | #define E1000_RXDEXT_STATERR_IPE 0x40000000 | ||
661 | #define E1000_RXDEXT_STATERR_RXE 0x80000000 | ||
662 | |||
663 | #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 | ||
664 | #define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF | ||
480 | 665 | ||
481 | /* mask to determine if packets should be dropped due to frame errors */ | 666 | /* mask to determine if packets should be dropped due to frame errors */ |
482 | #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ | 667 | #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ |
@@ -486,6 +671,15 @@ struct e1000_rx_desc { | |||
486 | E1000_RXD_ERR_CXE | \ | 671 | E1000_RXD_ERR_CXE | \ |
487 | E1000_RXD_ERR_RXE) | 672 | E1000_RXD_ERR_RXE) |
488 | 673 | ||
674 | |||
675 | /* Same mask, but for extended and packet split descriptors */ | ||
676 | #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ | ||
677 | E1000_RXDEXT_STATERR_CE | \ | ||
678 | E1000_RXDEXT_STATERR_SE | \ | ||
679 | E1000_RXDEXT_STATERR_SEQ | \ | ||
680 | E1000_RXDEXT_STATERR_CXE | \ | ||
681 | E1000_RXDEXT_STATERR_RXE) | ||
682 | |||
489 | /* Transmit Descriptor */ | 683 | /* Transmit Descriptor */ |
490 | struct e1000_tx_desc { | 684 | struct e1000_tx_desc { |
491 | uint64_t buffer_addr; /* Address of the descriptor's data buffer */ | 685 | uint64_t buffer_addr; /* Address of the descriptor's data buffer */ |
@@ -667,6 +861,7 @@ struct e1000_ffvt_entry { | |||
667 | #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ | 861 | #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ |
668 | #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ | 862 | #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ |
669 | #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ | 863 | #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ |
864 | #define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ | ||
670 | #define E1000_RCTL 0x00100 /* RX Control - RW */ | 865 | #define E1000_RCTL 0x00100 /* RX Control - RW */ |
671 | #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ | 866 | #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ |
672 | #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ | 867 | #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ |
@@ -676,9 +871,23 @@ struct e1000_ffvt_entry { | |||
676 | #define E1000_TBT 0x00448 /* TX Burst Timer - RW */ | 871 | #define E1000_TBT 0x00448 /* TX Burst Timer - RW */ |
677 | #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ | 872 | #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ |
678 | #define E1000_LEDCTL 0x00E00 /* LED Control - RW */ | 873 | #define E1000_LEDCTL 0x00E00 /* LED Control - RW */ |
874 | #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ | ||
875 | #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ | ||
679 | #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ | 876 | #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ |
877 | #define E1000_PBS 0x01008 /* Packet Buffer Size */ | ||
878 | #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ | ||
879 | #define E1000_FLASH_UPDATES 1000 | ||
880 | #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ | ||
881 | #define E1000_FLASHT 0x01028 /* FLASH Timer Register */ | ||
882 | #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ | ||
883 | #define E1000_FLSWCTL 0x01030 /* FLASH control register */ | ||
884 | #define E1000_FLSWDATA 0x01034 /* FLASH data register */ | ||
885 | #define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ | ||
886 | #define E1000_FLOP 0x0103C /* FLASH Opcode Register */ | ||
887 | #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ | ||
680 | #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ | 888 | #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ |
681 | #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ | 889 | #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ |
890 | #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ | ||
682 | #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */ | 891 | #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */ |
683 | #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */ | 892 | #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */ |
684 | #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */ | 893 | #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */ |
@@ -688,6 +897,7 @@ struct e1000_ffvt_entry { | |||
688 | #define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */ | 897 | #define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */ |
689 | #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ | 898 | #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ |
690 | #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ | 899 | #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ |
900 | #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ | ||
691 | #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ | 901 | #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ |
692 | #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ | 902 | #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ |
693 | #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ | 903 | #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ |
@@ -703,6 +913,14 @@ struct e1000_ffvt_entry { | |||
703 | #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ | 913 | #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ |
704 | #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ | 914 | #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ |
705 | #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ | 915 | #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ |
916 | #define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */ | ||
917 | #define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */ | ||
918 | #define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */ | ||
919 | #define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */ | ||
920 | #define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */ | ||
921 | #define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */ | ||
922 | #define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */ | ||
923 | #define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */ | ||
706 | #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ | 924 | #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ |
707 | #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ | 925 | #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ |
708 | #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ | 926 | #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ |
@@ -761,7 +979,17 @@ struct e1000_ffvt_entry { | |||
761 | #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ | 979 | #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ |
762 | #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ | 980 | #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ |
763 | #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ | 981 | #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ |
982 | #define E1000_IAC 0x4100 /* Interrupt Assertion Count */ | ||
983 | #define E1000_ICRXPTC 0x4104 /* Interrupt Cause Rx Packet Timer Expire Count */ | ||
984 | #define E1000_ICRXATC 0x4108 /* Interrupt Cause Rx Absolute Timer Expire Count */ | ||
985 | #define E1000_ICTXPTC 0x410C /* Interrupt Cause Tx Packet Timer Expire Count */ | ||
986 | #define E1000_ICTXATC 0x4110 /* Interrupt Cause Tx Absolute Timer Expire Count */ | ||
987 | #define E1000_ICTXQEC 0x4118 /* Interrupt Cause Tx Queue Empty Count */ | ||
988 | #define E1000_ICTXQMTC 0x411C /* Interrupt Cause Tx Queue Minimum Threshold Count */ | ||
989 | #define E1000_ICRXDMTC 0x4120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */ | ||
990 | #define E1000_ICRXOC 0x4124 /* Interrupt Cause Receiver Overrun Count */ | ||
764 | #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ | 991 | #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ |
992 | #define E1000_RFCTL 0x05008 /* Receive Filter Control*/ | ||
765 | #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ | 993 | #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ |
766 | #define E1000_RA 0x05400 /* Receive Address - RW Array */ | 994 | #define E1000_RA 0x05400 /* Receive Address - RW Array */ |
767 | #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ | 995 | #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ |
@@ -779,6 +1007,16 @@ struct e1000_ffvt_entry { | |||
779 | #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ | 1007 | #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ |
780 | #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ | 1008 | #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ |
781 | 1009 | ||
1010 | #define E1000_GCR 0x05B00 /* PCI-Ex Control */ | ||
1011 | #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ | ||
1012 | #define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ | ||
1013 | #define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ | ||
1014 | #define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ | ||
1015 | #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ | ||
1016 | #define E1000_SWSM 0x05B50 /* SW Semaphore */ | ||
1017 | #define E1000_FWSM 0x05B54 /* FW Semaphore */ | ||
1018 | #define E1000_FFLT_DBG 0x05F04 /* Debug Register */ | ||
1019 | #define E1000_HICR 0x08F00 /* Host Inteface Control */ | ||
782 | /* Register Set (82542) | 1020 | /* Register Set (82542) |
783 | * | 1021 | * |
784 | * Some of the 82542 registers are located at different offsets than they are | 1022 | * Some of the 82542 registers are located at different offsets than they are |
@@ -829,6 +1067,18 @@ struct e1000_ffvt_entry { | |||
829 | #define E1000_82542_VFTA 0x00600 | 1067 | #define E1000_82542_VFTA 0x00600 |
830 | #define E1000_82542_LEDCTL E1000_LEDCTL | 1068 | #define E1000_82542_LEDCTL E1000_LEDCTL |
831 | #define E1000_82542_PBA E1000_PBA | 1069 | #define E1000_82542_PBA E1000_PBA |
1070 | #define E1000_82542_PBS E1000_PBS | ||
1071 | #define E1000_82542_EEMNGCTL E1000_EEMNGCTL | ||
1072 | #define E1000_82542_EEARBC E1000_EEARBC | ||
1073 | #define E1000_82542_FLASHT E1000_FLASHT | ||
1074 | #define E1000_82542_EEWR E1000_EEWR | ||
1075 | #define E1000_82542_FLSWCTL E1000_FLSWCTL | ||
1076 | #define E1000_82542_FLSWDATA E1000_FLSWDATA | ||
1077 | #define E1000_82542_FLSWCNT E1000_FLSWCNT | ||
1078 | #define E1000_82542_FLOP E1000_FLOP | ||
1079 | #define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL | ||
1080 | #define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE | ||
1081 | #define E1000_82542_ERT E1000_ERT | ||
832 | #define E1000_82542_RXDCTL E1000_RXDCTL | 1082 | #define E1000_82542_RXDCTL E1000_RXDCTL |
833 | #define E1000_82542_RADV E1000_RADV | 1083 | #define E1000_82542_RADV E1000_RADV |
834 | #define E1000_82542_RSRPD E1000_RSRPD | 1084 | #define E1000_82542_RSRPD E1000_RSRPD |
@@ -913,6 +1163,38 @@ struct e1000_ffvt_entry { | |||
913 | #define E1000_82542_FFMT E1000_FFMT | 1163 | #define E1000_82542_FFMT E1000_FFMT |
914 | #define E1000_82542_FFVT E1000_FFVT | 1164 | #define E1000_82542_FFVT E1000_FFVT |
915 | #define E1000_82542_HOST_IF E1000_HOST_IF | 1165 | #define E1000_82542_HOST_IF E1000_HOST_IF |
1166 | #define E1000_82542_IAM E1000_IAM | ||
1167 | #define E1000_82542_EEMNGCTL E1000_EEMNGCTL | ||
1168 | #define E1000_82542_PSRCTL E1000_PSRCTL | ||
1169 | #define E1000_82542_RAID E1000_RAID | ||
1170 | #define E1000_82542_TARC0 E1000_TARC0 | ||
1171 | #define E1000_82542_TDBAL1 E1000_TDBAL1 | ||
1172 | #define E1000_82542_TDBAH1 E1000_TDBAH1 | ||
1173 | #define E1000_82542_TDLEN1 E1000_TDLEN1 | ||
1174 | #define E1000_82542_TDH1 E1000_TDH1 | ||
1175 | #define E1000_82542_TDT1 E1000_TDT1 | ||
1176 | #define E1000_82542_TXDCTL1 E1000_TXDCTL1 | ||
1177 | #define E1000_82542_TARC1 E1000_TARC1 | ||
1178 | #define E1000_82542_RFCTL E1000_RFCTL | ||
1179 | #define E1000_82542_GCR E1000_GCR | ||
1180 | #define E1000_82542_GSCL_1 E1000_GSCL_1 | ||
1181 | #define E1000_82542_GSCL_2 E1000_GSCL_2 | ||
1182 | #define E1000_82542_GSCL_3 E1000_GSCL_3 | ||
1183 | #define E1000_82542_GSCL_4 E1000_GSCL_4 | ||
1184 | #define E1000_82542_FACTPS E1000_FACTPS | ||
1185 | #define E1000_82542_SWSM E1000_SWSM | ||
1186 | #define E1000_82542_FWSM E1000_FWSM | ||
1187 | #define E1000_82542_FFLT_DBG E1000_FFLT_DBG | ||
1188 | #define E1000_82542_IAC E1000_IAC | ||
1189 | #define E1000_82542_ICRXPTC E1000_ICRXPTC | ||
1190 | #define E1000_82542_ICRXATC E1000_ICRXATC | ||
1191 | #define E1000_82542_ICTXPTC E1000_ICTXPTC | ||
1192 | #define E1000_82542_ICTXATC E1000_ICTXATC | ||
1193 | #define E1000_82542_ICTXQEC E1000_ICTXQEC | ||
1194 | #define E1000_82542_ICTXQMTC E1000_ICTXQMTC | ||
1195 | #define E1000_82542_ICRXDMTC E1000_ICRXDMTC | ||
1196 | #define E1000_82542_ICRXOC E1000_ICRXOC | ||
1197 | #define E1000_82542_HICR E1000_HICR | ||
916 | 1198 | ||
917 | /* Statistics counters collected by the MAC */ | 1199 | /* Statistics counters collected by the MAC */ |
918 | struct e1000_hw_stats { | 1200 | struct e1000_hw_stats { |
@@ -974,11 +1256,21 @@ struct e1000_hw_stats { | |||
974 | uint64_t bptc; | 1256 | uint64_t bptc; |
975 | uint64_t tsctc; | 1257 | uint64_t tsctc; |
976 | uint64_t tsctfc; | 1258 | uint64_t tsctfc; |
1259 | uint64_t iac; | ||
1260 | uint64_t icrxptc; | ||
1261 | uint64_t icrxatc; | ||
1262 | uint64_t ictxptc; | ||
1263 | uint64_t ictxatc; | ||
1264 | uint64_t ictxqec; | ||
1265 | uint64_t ictxqmtc; | ||
1266 | uint64_t icrxdmtc; | ||
1267 | uint64_t icrxoc; | ||
977 | }; | 1268 | }; |
978 | 1269 | ||
979 | /* Structure containing variables used by the shared code (e1000_hw.c) */ | 1270 | /* Structure containing variables used by the shared code (e1000_hw.c) */ |
980 | struct e1000_hw { | 1271 | struct e1000_hw { |
981 | uint8_t __iomem *hw_addr; | 1272 | uint8_t *hw_addr; |
1273 | uint8_t *flash_address; | ||
982 | e1000_mac_type mac_type; | 1274 | e1000_mac_type mac_type; |
983 | e1000_phy_type phy_type; | 1275 | e1000_phy_type phy_type; |
984 | uint32_t phy_init_script; | 1276 | uint32_t phy_init_script; |
@@ -993,6 +1285,7 @@ struct e1000_hw { | |||
993 | e1000_ms_type original_master_slave; | 1285 | e1000_ms_type original_master_slave; |
994 | e1000_ffe_config ffe_config_state; | 1286 | e1000_ffe_config ffe_config_state; |
995 | uint32_t asf_firmware_present; | 1287 | uint32_t asf_firmware_present; |
1288 | uint32_t eeprom_semaphore_present; | ||
996 | unsigned long io_base; | 1289 | unsigned long io_base; |
997 | uint32_t phy_id; | 1290 | uint32_t phy_id; |
998 | uint32_t phy_revision; | 1291 | uint32_t phy_revision; |
@@ -1009,6 +1302,8 @@ struct e1000_hw { | |||
1009 | uint32_t ledctl_default; | 1302 | uint32_t ledctl_default; |
1010 | uint32_t ledctl_mode1; | 1303 | uint32_t ledctl_mode1; |
1011 | uint32_t ledctl_mode2; | 1304 | uint32_t ledctl_mode2; |
1305 | boolean_t tx_pkt_filtering; | ||
1306 | struct e1000_host_mng_dhcp_cookie mng_cookie; | ||
1012 | uint16_t phy_spd_default; | 1307 | uint16_t phy_spd_default; |
1013 | uint16_t autoneg_advertised; | 1308 | uint16_t autoneg_advertised; |
1014 | uint16_t pci_cmd_word; | 1309 | uint16_t pci_cmd_word; |
@@ -1047,16 +1342,24 @@ struct e1000_hw { | |||
1047 | boolean_t adaptive_ifs; | 1342 | boolean_t adaptive_ifs; |
1048 | boolean_t ifs_params_forced; | 1343 | boolean_t ifs_params_forced; |
1049 | boolean_t in_ifs_mode; | 1344 | boolean_t in_ifs_mode; |
1345 | boolean_t mng_reg_access_disabled; | ||
1050 | }; | 1346 | }; |
1051 | 1347 | ||
1052 | 1348 | ||
1053 | #define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ | 1349 | #define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ |
1054 | #define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ | 1350 | #define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ |
1351 | #define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */ | ||
1352 | #define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ | ||
1353 | #define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */ | ||
1354 | #define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ | ||
1355 | #define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */ | ||
1356 | #define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */ | ||
1055 | /* Register Bit Masks */ | 1357 | /* Register Bit Masks */ |
1056 | /* Device Control */ | 1358 | /* Device Control */ |
1057 | #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ | 1359 | #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ |
1058 | #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ | 1360 | #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ |
1059 | #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ | 1361 | #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ |
1362 | #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ | ||
1060 | #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ | 1363 | #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ |
1061 | #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ | 1364 | #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ |
1062 | #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ | 1365 | #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ |
@@ -1070,6 +1373,7 @@ struct e1000_hw { | |||
1070 | #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ | 1373 | #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ |
1071 | #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ | 1374 | #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ |
1072 | #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ | 1375 | #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ |
1376 | #define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */ | ||
1073 | #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ | 1377 | #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ |
1074 | #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ | 1378 | #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ |
1075 | #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ | 1379 | #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ |
@@ -1089,6 +1393,7 @@ struct e1000_hw { | |||
1089 | #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ | 1393 | #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ |
1090 | #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ | 1394 | #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ |
1091 | #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ | 1395 | #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ |
1396 | #define E1000_STATUS_FUNC_SHIFT 2 | ||
1092 | #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ | 1397 | #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ |
1093 | #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ | 1398 | #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ |
1094 | #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ | 1399 | #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ |
@@ -1098,6 +1403,8 @@ struct e1000_hw { | |||
1098 | #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ | 1403 | #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ |
1099 | #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ | 1404 | #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ |
1100 | #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ | 1405 | #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ |
1406 | #define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */ | ||
1407 | #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ | ||
1101 | #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ | 1408 | #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ |
1102 | #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ | 1409 | #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ |
1103 | #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ | 1410 | #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ |
@@ -1128,6 +1435,18 @@ struct e1000_hw { | |||
1128 | #ifndef E1000_EEPROM_GRANT_ATTEMPTS | 1435 | #ifndef E1000_EEPROM_GRANT_ATTEMPTS |
1129 | #define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ | 1436 | #define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ |
1130 | #endif | 1437 | #endif |
1438 | #define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */ | ||
1439 | #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */ | ||
1440 | #define E1000_EECD_SIZE_EX_SHIFT 11 | ||
1441 | #define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ | ||
1442 | #define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ | ||
1443 | #define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ | ||
1444 | #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ | ||
1445 | #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ | ||
1446 | #define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ | ||
1447 | #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ | ||
1448 | #define E1000_STM_OPCODE 0xDB00 | ||
1449 | #define E1000_HICR_FW_RESET 0xC0 | ||
1131 | 1450 | ||
1132 | /* EEPROM Read */ | 1451 | /* EEPROM Read */ |
1133 | #define E1000_EERD_START 0x00000001 /* Start Read */ | 1452 | #define E1000_EERD_START 0x00000001 /* Start Read */ |
@@ -1171,6 +1490,8 @@ struct e1000_hw { | |||
1171 | #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 | 1490 | #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 |
1172 | #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 | 1491 | #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 |
1173 | #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 | 1492 | #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 |
1493 | #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ | ||
1494 | #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ | ||
1174 | 1495 | ||
1175 | /* MDI Control */ | 1496 | /* MDI Control */ |
1176 | #define E1000_MDIC_DATA_MASK 0x0000FFFF | 1497 | #define E1000_MDIC_DATA_MASK 0x0000FFFF |
@@ -1187,14 +1508,17 @@ struct e1000_hw { | |||
1187 | /* LED Control */ | 1508 | /* LED Control */ |
1188 | #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F | 1509 | #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F |
1189 | #define E1000_LEDCTL_LED0_MODE_SHIFT 0 | 1510 | #define E1000_LEDCTL_LED0_MODE_SHIFT 0 |
1511 | #define E1000_LEDCTL_LED0_BLINK_RATE 0x0000020 | ||
1190 | #define E1000_LEDCTL_LED0_IVRT 0x00000040 | 1512 | #define E1000_LEDCTL_LED0_IVRT 0x00000040 |
1191 | #define E1000_LEDCTL_LED0_BLINK 0x00000080 | 1513 | #define E1000_LEDCTL_LED0_BLINK 0x00000080 |
1192 | #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 | 1514 | #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 |
1193 | #define E1000_LEDCTL_LED1_MODE_SHIFT 8 | 1515 | #define E1000_LEDCTL_LED1_MODE_SHIFT 8 |
1516 | #define E1000_LEDCTL_LED1_BLINK_RATE 0x0002000 | ||
1194 | #define E1000_LEDCTL_LED1_IVRT 0x00004000 | 1517 | #define E1000_LEDCTL_LED1_IVRT 0x00004000 |
1195 | #define E1000_LEDCTL_LED1_BLINK 0x00008000 | 1518 | #define E1000_LEDCTL_LED1_BLINK 0x00008000 |
1196 | #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 | 1519 | #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 |
1197 | #define E1000_LEDCTL_LED2_MODE_SHIFT 16 | 1520 | #define E1000_LEDCTL_LED2_MODE_SHIFT 16 |
1521 | #define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000 | ||
1198 | #define E1000_LEDCTL_LED2_IVRT 0x00400000 | 1522 | #define E1000_LEDCTL_LED2_IVRT 0x00400000 |
1199 | #define E1000_LEDCTL_LED2_BLINK 0x00800000 | 1523 | #define E1000_LEDCTL_LED2_BLINK 0x00800000 |
1200 | #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 | 1524 | #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 |
@@ -1238,6 +1562,10 @@ struct e1000_hw { | |||
1238 | #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ | 1562 | #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ |
1239 | #define E1000_ICR_TXD_LOW 0x00008000 | 1563 | #define E1000_ICR_TXD_LOW 0x00008000 |
1240 | #define E1000_ICR_SRPD 0x00010000 | 1564 | #define E1000_ICR_SRPD 0x00010000 |
1565 | #define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ | ||
1566 | #define E1000_ICR_MNG 0x00040000 /* Manageability event */ | ||
1567 | #define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ | ||
1568 | #define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ | ||
1241 | 1569 | ||
1242 | /* Interrupt Cause Set */ | 1570 | /* Interrupt Cause Set */ |
1243 | #define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ | 1571 | #define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ |
@@ -1255,6 +1583,9 @@ struct e1000_hw { | |||
1255 | #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ | 1583 | #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ |
1256 | #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW | 1584 | #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW |
1257 | #define E1000_ICS_SRPD E1000_ICR_SRPD | 1585 | #define E1000_ICS_SRPD E1000_ICR_SRPD |
1586 | #define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ | ||
1587 | #define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ | ||
1588 | #define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ | ||
1258 | 1589 | ||
1259 | /* Interrupt Mask Set */ | 1590 | /* Interrupt Mask Set */ |
1260 | #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ | 1591 | #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ |
@@ -1272,6 +1603,9 @@ struct e1000_hw { | |||
1272 | #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ | 1603 | #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ |
1273 | #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW | 1604 | #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW |
1274 | #define E1000_IMS_SRPD E1000_ICR_SRPD | 1605 | #define E1000_IMS_SRPD E1000_ICR_SRPD |
1606 | #define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ | ||
1607 | #define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ | ||
1608 | #define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ | ||
1275 | 1609 | ||
1276 | /* Interrupt Mask Clear */ | 1610 | /* Interrupt Mask Clear */ |
1277 | #define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ | 1611 | #define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ |
@@ -1289,6 +1623,9 @@ struct e1000_hw { | |||
1289 | #define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ | 1623 | #define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ |
1290 | #define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW | 1624 | #define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW |
1291 | #define E1000_IMC_SRPD E1000_ICR_SRPD | 1625 | #define E1000_IMC_SRPD E1000_ICR_SRPD |
1626 | #define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */ | ||
1627 | #define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */ | ||
1628 | #define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */ | ||
1292 | 1629 | ||
1293 | /* Receive Control */ | 1630 | /* Receive Control */ |
1294 | #define E1000_RCTL_RST 0x00000001 /* Software reset */ | 1631 | #define E1000_RCTL_RST 0x00000001 /* Software reset */ |
@@ -1301,6 +1638,8 @@ struct e1000_hw { | |||
1301 | #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ | 1638 | #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ |
1302 | #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ | 1639 | #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ |
1303 | #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ | 1640 | #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ |
1641 | #define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ | ||
1642 | #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ | ||
1304 | #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ | 1643 | #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ |
1305 | #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ | 1644 | #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ |
1306 | #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ | 1645 | #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ |
@@ -1327,6 +1666,34 @@ struct e1000_hw { | |||
1327 | #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ | 1666 | #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ |
1328 | #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ | 1667 | #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ |
1329 | #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ | 1668 | #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ |
1669 | #define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */ | ||
1670 | #define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */ | ||
1671 | |||
1672 | /* Use byte values for the following shift parameters | ||
1673 | * Usage: | ||
1674 | * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & | ||
1675 | * E1000_PSRCTL_BSIZE0_MASK) | | ||
1676 | * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & | ||
1677 | * E1000_PSRCTL_BSIZE1_MASK) | | ||
1678 | * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & | ||
1679 | * E1000_PSRCTL_BSIZE2_MASK) | | ||
1680 | * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; | ||
1681 | * E1000_PSRCTL_BSIZE3_MASK)) | ||
1682 | * where value0 = [128..16256], default=256 | ||
1683 | * value1 = [1024..64512], default=4096 | ||
1684 | * value2 = [0..64512], default=4096 | ||
1685 | * value3 = [0..64512], default=0 | ||
1686 | */ | ||
1687 | |||
1688 | #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F | ||
1689 | #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 | ||
1690 | #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 | ||
1691 | #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 | ||
1692 | |||
1693 | #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ | ||
1694 | #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ | ||
1695 | #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ | ||
1696 | #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ | ||
1330 | 1697 | ||
1331 | /* Receive Descriptor */ | 1698 | /* Receive Descriptor */ |
1332 | #define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */ | 1699 | #define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */ |
@@ -1341,6 +1708,23 @@ struct e1000_hw { | |||
1341 | #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ | 1708 | #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ |
1342 | #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ | 1709 | #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ |
1343 | 1710 | ||
1711 | /* Header split receive */ | ||
1712 | #define E1000_RFCTL_ISCSI_DIS 0x00000001 | ||
1713 | #define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E | ||
1714 | #define E1000_RFCTL_ISCSI_DWC_SHIFT 1 | ||
1715 | #define E1000_RFCTL_NFSW_DIS 0x00000040 | ||
1716 | #define E1000_RFCTL_NFSR_DIS 0x00000080 | ||
1717 | #define E1000_RFCTL_NFS_VER_MASK 0x00000300 | ||
1718 | #define E1000_RFCTL_NFS_VER_SHIFT 8 | ||
1719 | #define E1000_RFCTL_IPV6_DIS 0x00000400 | ||
1720 | #define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800 | ||
1721 | #define E1000_RFCTL_ACK_DIS 0x00001000 | ||
1722 | #define E1000_RFCTL_ACKD_DIS 0x00002000 | ||
1723 | #define E1000_RFCTL_IPFRSP_DIS 0x00004000 | ||
1724 | #define E1000_RFCTL_EXTEN 0x00008000 | ||
1725 | #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 | ||
1726 | #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 | ||
1727 | |||
1344 | /* Receive Descriptor Control */ | 1728 | /* Receive Descriptor Control */ |
1345 | #define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */ | 1729 | #define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */ |
1346 | #define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */ | 1730 | #define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */ |
@@ -1354,6 +1738,8 @@ struct e1000_hw { | |||
1354 | #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ | 1738 | #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ |
1355 | #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ | 1739 | #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ |
1356 | #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ | 1740 | #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ |
1741 | #define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc. | ||
1742 | still to be processed. */ | ||
1357 | 1743 | ||
1358 | /* Transmit Configuration Word */ | 1744 | /* Transmit Configuration Word */ |
1359 | #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ | 1745 | #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ |
@@ -1387,12 +1773,16 @@ struct e1000_hw { | |||
1387 | #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ | 1773 | #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ |
1388 | #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ | 1774 | #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ |
1389 | #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ | 1775 | #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ |
1776 | #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ | ||
1390 | 1777 | ||
1391 | /* Receive Checksum Control */ | 1778 | /* Receive Checksum Control */ |
1392 | #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ | 1779 | #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ |
1393 | #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ | 1780 | #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ |
1394 | #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ | 1781 | #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ |
1395 | #define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ | 1782 | #define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ |
1783 | #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ | ||
1784 | #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ | ||
1785 | |||
1396 | 1786 | ||
1397 | /* Definitions for power management and wakeup registers */ | 1787 | /* Definitions for power management and wakeup registers */ |
1398 | /* Wake Up Control */ | 1788 | /* Wake Up Control */ |
@@ -1411,6 +1801,7 @@ struct e1000_hw { | |||
1411 | #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ | 1801 | #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ |
1412 | #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ | 1802 | #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ |
1413 | #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ | 1803 | #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ |
1804 | #define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ | ||
1414 | #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ | 1805 | #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ |
1415 | #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ | 1806 | #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ |
1416 | #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ | 1807 | #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ |
@@ -1446,13 +1837,19 @@ struct e1000_hw { | |||
1446 | #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ | 1837 | #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ |
1447 | #define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery | 1838 | #define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery |
1448 | * Filtering */ | 1839 | * Filtering */ |
1840 | #define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */ | ||
1449 | #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ | 1841 | #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ |
1450 | #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ | 1842 | #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ |
1451 | #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ | 1843 | #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ |
1844 | #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ | ||
1452 | #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address | 1845 | #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address |
1453 | * filtering */ | 1846 | * filtering */ |
1454 | #define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host | 1847 | #define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host |
1455 | * memory */ | 1848 | * memory */ |
1849 | #define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address | ||
1850 | * filtering */ | ||
1851 | #define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ | ||
1852 | #define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ | ||
1456 | #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ | 1853 | #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ |
1457 | #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ | 1854 | #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ |
1458 | #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ | 1855 | #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ |
@@ -1463,11 +1860,97 @@ struct e1000_hw { | |||
1463 | #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ | 1860 | #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ |
1464 | #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ | 1861 | #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ |
1465 | 1862 | ||
1863 | /* SW Semaphore Register */ | ||
1864 | #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ | ||
1865 | #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ | ||
1866 | #define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ | ||
1867 | #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ | ||
1868 | |||
1869 | /* FW Semaphore Register */ | ||
1870 | #define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */ | ||
1871 | #define E1000_FWSM_MODE_SHIFT 1 | ||
1872 | #define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */ | ||
1873 | |||
1874 | /* FFLT Debug Register */ | ||
1875 | #define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */ | ||
1876 | |||
1877 | typedef enum { | ||
1878 | e1000_mng_mode_none = 0, | ||
1879 | e1000_mng_mode_asf, | ||
1880 | e1000_mng_mode_pt, | ||
1881 | e1000_mng_mode_ipmi, | ||
1882 | e1000_mng_mode_host_interface_only | ||
1883 | } e1000_mng_mode; | ||
1884 | |||
1885 | /* Host Inteface Control Register */ | ||
1886 | #define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */ | ||
1887 | #define E1000_HICR_C 0x00000002 /* Driver sets this bit when done | ||
1888 | * to put command in RAM */ | ||
1889 | #define E1000_HICR_SV 0x00000004 /* Status Validity */ | ||
1890 | #define E1000_HICR_FWR 0x00000080 /* FW reset. Set by the Host */ | ||
1891 | |||
1892 | /* Host Interface Command Interface - Address range 0x8800-0x8EFF */ | ||
1893 | #define E1000_HI_MAX_DATA_LENGTH 252 /* Host Interface data length */ | ||
1894 | #define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */ | ||
1895 | #define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */ | ||
1896 | #define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */ | ||
1897 | |||
1898 | struct e1000_host_command_header { | ||
1899 | uint8_t command_id; | ||
1900 | uint8_t command_length; | ||
1901 | uint8_t command_options; /* I/F bits for command, status for return */ | ||
1902 | uint8_t checksum; | ||
1903 | }; | ||
1904 | struct e1000_host_command_info { | ||
1905 | struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ | ||
1906 | uint8_t command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */ | ||
1907 | }; | ||
1908 | |||
1909 | /* Host SMB register #0 */ | ||
1910 | #define E1000_HSMC0R_CLKIN 0x00000001 /* SMB Clock in */ | ||
1911 | #define E1000_HSMC0R_DATAIN 0x00000002 /* SMB Data in */ | ||
1912 | #define E1000_HSMC0R_DATAOUT 0x00000004 /* SMB Data out */ | ||
1913 | #define E1000_HSMC0R_CLKOUT 0x00000008 /* SMB Clock out */ | ||
1914 | |||
1915 | /* Host SMB register #1 */ | ||
1916 | #define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN | ||
1917 | #define E1000_HSMC1R_DATAIN E1000_HSMC0R_DATAIN | ||
1918 | #define E1000_HSMC1R_DATAOUT E1000_HSMC0R_DATAOUT | ||
1919 | #define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT | ||
1920 | |||
1921 | /* FW Status Register */ | ||
1922 | #define E1000_FWSTS_FWS_MASK 0x000000FF /* FW Status */ | ||
1923 | |||
1466 | /* Wake Up Packet Length */ | 1924 | /* Wake Up Packet Length */ |
1467 | #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ | 1925 | #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ |
1468 | 1926 | ||
1469 | #define E1000_MDALIGN 4096 | 1927 | #define E1000_MDALIGN 4096 |
1470 | 1928 | ||
1929 | #define E1000_GCR_BEM32 0x00400000 | ||
1930 | /* Function Active and Power State to MNG */ | ||
1931 | #define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003 | ||
1932 | #define E1000_FACTPS_LAN0_VALID 0x00000004 | ||
1933 | #define E1000_FACTPS_FUNC0_AUX_EN 0x00000008 | ||
1934 | #define E1000_FACTPS_FUNC1_POWER_STATE_MASK 0x000000C0 | ||
1935 | #define E1000_FACTPS_FUNC1_POWER_STATE_SHIFT 6 | ||
1936 | #define E1000_FACTPS_LAN1_VALID 0x00000100 | ||
1937 | #define E1000_FACTPS_FUNC1_AUX_EN 0x00000200 | ||
1938 | #define E1000_FACTPS_FUNC2_POWER_STATE_MASK 0x00003000 | ||
1939 | #define E1000_FACTPS_FUNC2_POWER_STATE_SHIFT 12 | ||
1940 | #define E1000_FACTPS_IDE_ENABLE 0x00004000 | ||
1941 | #define E1000_FACTPS_FUNC2_AUX_EN 0x00008000 | ||
1942 | #define E1000_FACTPS_FUNC3_POWER_STATE_MASK 0x000C0000 | ||
1943 | #define E1000_FACTPS_FUNC3_POWER_STATE_SHIFT 18 | ||
1944 | #define E1000_FACTPS_SP_ENABLE 0x00100000 | ||
1945 | #define E1000_FACTPS_FUNC3_AUX_EN 0x00200000 | ||
1946 | #define E1000_FACTPS_FUNC4_POWER_STATE_MASK 0x03000000 | ||
1947 | #define E1000_FACTPS_FUNC4_POWER_STATE_SHIFT 24 | ||
1948 | #define E1000_FACTPS_IPMI_ENABLE 0x04000000 | ||
1949 | #define E1000_FACTPS_FUNC4_AUX_EN 0x08000000 | ||
1950 | #define E1000_FACTPS_MNGCG 0x20000000 | ||
1951 | #define E1000_FACTPS_LAN_FUNC_SEL 0x40000000 | ||
1952 | #define E1000_FACTPS_PM_STATE_CHANGED 0x80000000 | ||
1953 | |||
1471 | /* EEPROM Commands - Microwire */ | 1954 | /* EEPROM Commands - Microwire */ |
1472 | #define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */ | 1955 | #define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */ |
1473 | #define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */ | 1956 | #define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */ |
@@ -1477,22 +1960,20 @@ struct e1000_hw { | |||
1477 | 1960 | ||
1478 | /* EEPROM Commands - SPI */ | 1961 | /* EEPROM Commands - SPI */ |
1479 | #define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ | 1962 | #define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ |
1480 | #define EEPROM_READ_OPCODE_SPI 0x3 /* EEPROM read opcode */ | 1963 | #define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ |
1481 | #define EEPROM_WRITE_OPCODE_SPI 0x2 /* EEPROM write opcode */ | 1964 | #define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ |
1482 | #define EEPROM_A8_OPCODE_SPI 0x8 /* opcode bit-3 = address bit-8 */ | 1965 | #define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ |
1483 | #define EEPROM_WREN_OPCODE_SPI 0x6 /* EEPROM set Write Enable latch */ | 1966 | #define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */ |
1484 | #define EEPROM_WRDI_OPCODE_SPI 0x4 /* EEPROM reset Write Enable latch */ | 1967 | #define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */ |
1485 | #define EEPROM_RDSR_OPCODE_SPI 0x5 /* EEPROM read Status register */ | 1968 | #define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */ |
1486 | #define EEPROM_WRSR_OPCODE_SPI 0x1 /* EEPROM write Status register */ | 1969 | #define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */ |
1970 | #define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ | ||
1971 | #define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ | ||
1972 | #define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ | ||
1487 | 1973 | ||
1488 | /* EEPROM Size definitions */ | 1974 | /* EEPROM Size definitions */ |
1489 | #define EEPROM_SIZE_16KB 0x1800 | 1975 | #define EEPROM_WORD_SIZE_SHIFT 6 |
1490 | #define EEPROM_SIZE_8KB 0x1400 | 1976 | #define EEPROM_SIZE_SHIFT 10 |
1491 | #define EEPROM_SIZE_4KB 0x1000 | ||
1492 | #define EEPROM_SIZE_2KB 0x0C00 | ||
1493 | #define EEPROM_SIZE_1KB 0x0800 | ||
1494 | #define EEPROM_SIZE_512B 0x0400 | ||
1495 | #define EEPROM_SIZE_128B 0x0000 | ||
1496 | #define EEPROM_SIZE_MASK 0x1C00 | 1977 | #define EEPROM_SIZE_MASK 0x1C00 |
1497 | 1978 | ||
1498 | /* EEPROM Word Offsets */ | 1979 | /* EEPROM Word Offsets */ |
@@ -1606,7 +2087,22 @@ struct e1000_hw { | |||
1606 | #define IFS_MIN 40 | 2087 | #define IFS_MIN 40 |
1607 | #define IFS_RATIO 4 | 2088 | #define IFS_RATIO 4 |
1608 | 2089 | ||
2090 | /* Extended Configuration Control and Size */ | ||
2091 | #define E1000_EXTCNF_CTRL_PCIE_WRITE_ENABLE 0x00000001 | ||
2092 | #define E1000_EXTCNF_CTRL_PHY_WRITE_ENABLE 0x00000002 | ||
2093 | #define E1000_EXTCNF_CTRL_D_UD_ENABLE 0x00000004 | ||
2094 | #define E1000_EXTCNF_CTRL_D_UD_LATENCY 0x00000008 | ||
2095 | #define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010 | ||
2096 | #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 | ||
2097 | #define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040 | ||
2098 | #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x1FFF0000 | ||
2099 | |||
2100 | #define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF | ||
2101 | #define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00 | ||
2102 | #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000 | ||
2103 | |||
1609 | /* PBA constants */ | 2104 | /* PBA constants */ |
2105 | #define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */ | ||
1610 | #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ | 2106 | #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ |
1611 | #define E1000_PBA_22K 0x0016 | 2107 | #define E1000_PBA_22K 0x0016 |
1612 | #define E1000_PBA_24K 0x0018 | 2108 | #define E1000_PBA_24K 0x0018 |
@@ -1663,6 +2159,13 @@ struct e1000_hw { | |||
1663 | /* Number of milliseconds we wait for auto-negotiation to complete */ | 2159 | /* Number of milliseconds we wait for auto-negotiation to complete */ |
1664 | #define LINK_UP_TIMEOUT 500 | 2160 | #define LINK_UP_TIMEOUT 500 |
1665 | 2161 | ||
2162 | /* Number of 100 microseconds we wait for PCI Express master disable */ | ||
2163 | #define MASTER_DISABLE_TIMEOUT 800 | ||
2164 | /* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */ | ||
2165 | #define AUTO_READ_DONE_TIMEOUT 10 | ||
2166 | /* Number of milliseconds we wait for PHY configuration done after MAC reset */ | ||
2167 | #define PHY_CFG_TIMEOUT 40 | ||
2168 | |||
1666 | #define E1000_TX_BUFFER_SIZE ((uint32_t)1514) | 2169 | #define E1000_TX_BUFFER_SIZE ((uint32_t)1514) |
1667 | 2170 | ||
1668 | /* The carrier extension symbol, as received by the NIC. */ | 2171 | /* The carrier extension symbol, as received by the NIC. */ |
@@ -1763,6 +2266,7 @@ struct e1000_hw { | |||
1763 | #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */ | 2266 | #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */ |
1764 | #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */ | 2267 | #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */ |
1765 | #define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */ | 2268 | #define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */ |
2269 | #define IGP02E1000_PHY_POWER_MGMT 0x19 | ||
1766 | #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */ | 2270 | #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */ |
1767 | 2271 | ||
1768 | /* IGP01E1000 AGC Registers - stores the cable length values*/ | 2272 | /* IGP01E1000 AGC Registers - stores the cable length values*/ |
@@ -1771,12 +2275,20 @@ struct e1000_hw { | |||
1771 | #define IGP01E1000_PHY_AGC_C 0x1472 | 2275 | #define IGP01E1000_PHY_AGC_C 0x1472 |
1772 | #define IGP01E1000_PHY_AGC_D 0x1872 | 2276 | #define IGP01E1000_PHY_AGC_D 0x1872 |
1773 | 2277 | ||
2278 | /* IGP02E1000 AGC Registers for cable length values */ | ||
2279 | #define IGP02E1000_PHY_AGC_A 0x11B1 | ||
2280 | #define IGP02E1000_PHY_AGC_B 0x12B1 | ||
2281 | #define IGP02E1000_PHY_AGC_C 0x14B1 | ||
2282 | #define IGP02E1000_PHY_AGC_D 0x18B1 | ||
2283 | |||
1774 | /* IGP01E1000 DSP Reset Register */ | 2284 | /* IGP01E1000 DSP Reset Register */ |
1775 | #define IGP01E1000_PHY_DSP_RESET 0x1F33 | 2285 | #define IGP01E1000_PHY_DSP_RESET 0x1F33 |
1776 | #define IGP01E1000_PHY_DSP_SET 0x1F71 | 2286 | #define IGP01E1000_PHY_DSP_SET 0x1F71 |
1777 | #define IGP01E1000_PHY_DSP_FFE 0x1F35 | 2287 | #define IGP01E1000_PHY_DSP_FFE 0x1F35 |
1778 | 2288 | ||
1779 | #define IGP01E1000_PHY_CHANNEL_NUM 4 | 2289 | #define IGP01E1000_PHY_CHANNEL_NUM 4 |
2290 | #define IGP02E1000_PHY_CHANNEL_NUM 4 | ||
2291 | |||
1780 | #define IGP01E1000_PHY_AGC_PARAM_A 0x1171 | 2292 | #define IGP01E1000_PHY_AGC_PARAM_A 0x1171 |
1781 | #define IGP01E1000_PHY_AGC_PARAM_B 0x1271 | 2293 | #define IGP01E1000_PHY_AGC_PARAM_B 0x1271 |
1782 | #define IGP01E1000_PHY_AGC_PARAM_C 0x1471 | 2294 | #define IGP01E1000_PHY_AGC_PARAM_C 0x1471 |
@@ -2060,20 +2572,30 @@ struct e1000_hw { | |||
2060 | #define IGP01E1000_MSE_CHANNEL_B 0x0F00 | 2572 | #define IGP01E1000_MSE_CHANNEL_B 0x0F00 |
2061 | #define IGP01E1000_MSE_CHANNEL_A 0xF000 | 2573 | #define IGP01E1000_MSE_CHANNEL_A 0xF000 |
2062 | 2574 | ||
2575 | #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ | ||
2576 | #define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */ | ||
2577 | #define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in D0a mode */ | ||
2578 | |||
2063 | /* IGP01E1000 DSP reset macros */ | 2579 | /* IGP01E1000 DSP reset macros */ |
2064 | #define DSP_RESET_ENABLE 0x0 | 2580 | #define DSP_RESET_ENABLE 0x0 |
2065 | #define DSP_RESET_DISABLE 0x2 | 2581 | #define DSP_RESET_DISABLE 0x2 |
2066 | #define E1000_MAX_DSP_RESETS 10 | 2582 | #define E1000_MAX_DSP_RESETS 10 |
2067 | 2583 | ||
2068 | /* IGP01E1000 AGC Registers */ | 2584 | /* IGP01E1000 & IGP02E1000 AGC Registers */ |
2069 | 2585 | ||
2070 | #define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */ | 2586 | #define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */ |
2587 | #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */ | ||
2588 | |||
2589 | /* IGP02E1000 AGC Register Length 9-bit mask */ | ||
2590 | #define IGP02E1000_AGC_LENGTH_MASK 0x7F | ||
2071 | 2591 | ||
2072 | /* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */ | 2592 | /* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */ |
2073 | #define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128 | 2593 | #define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128 |
2594 | #define IGP02E1000_AGC_LENGTH_TABLE_SIZE 128 | ||
2074 | 2595 | ||
2075 | /* The precision of the length is +/- 10 meters */ | 2596 | /* The precision error of the cable length is +/- 10 meters */ |
2076 | #define IGP01E1000_AGC_RANGE 10 | 2597 | #define IGP01E1000_AGC_RANGE 10 |
2598 | #define IGP02E1000_AGC_RANGE 10 | ||
2077 | 2599 | ||
2078 | /* IGP01E1000 PCS Initialization register */ | 2600 | /* IGP01E1000 PCS Initialization register */ |
2079 | /* bits 3:6 in the PCS registers stores the channels polarity */ | 2601 | /* bits 3:6 in the PCS registers stores the channels polarity */ |
@@ -2113,6 +2635,8 @@ struct e1000_hw { | |||
2113 | #define M88E1000_12_PHY_ID M88E1000_E_PHY_ID | 2635 | #define M88E1000_12_PHY_ID M88E1000_E_PHY_ID |
2114 | #define M88E1000_14_PHY_ID M88E1000_E_PHY_ID | 2636 | #define M88E1000_14_PHY_ID M88E1000_E_PHY_ID |
2115 | #define M88E1011_I_REV_4 0x04 | 2637 | #define M88E1011_I_REV_4 0x04 |
2638 | #define M88E1111_I_PHY_ID 0x01410CC0 | ||
2639 | #define L1LXT971A_PHY_ID 0x001378E0 | ||
2116 | 2640 | ||
2117 | /* Miscellaneous PHY bit definitions. */ | 2641 | /* Miscellaneous PHY bit definitions. */ |
2118 | #define PHY_PREAMBLE 0xFFFFFFFF | 2642 | #define PHY_PREAMBLE 0xFFFFFFFF |
diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c index 82549a6fcfb3..325495b8b60c 100644 --- a/drivers/net/e1000/e1000_main.c +++ b/drivers/net/e1000/e1000_main.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /******************************************************************************* | 1 | /******************************************************************************* |
2 | 2 | ||
3 | 3 | ||
4 | Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved. | 4 | Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. |
5 | 5 | ||
6 | This program is free software; you can redistribute it and/or modify it | 6 | This program is free software; you can redistribute it and/or modify it |
7 | under the terms of the GNU General Public License as published by the Free | 7 | under the terms of the GNU General Public License as published by the Free |
@@ -29,33 +29,9 @@ | |||
29 | #include "e1000.h" | 29 | #include "e1000.h" |
30 | 30 | ||
31 | /* Change Log | 31 | /* Change Log |
32 | * 5.3.12 6/7/04 | 32 | * 6.0.44+ 2/15/05 |
33 | * - kcompat NETIF_MSG for older kernels (2.4.9) <sean.p.mcdermott@intel.com> | 33 | * o applied Anton's patch to resolve tx hang in hardware |
34 | * - if_mii support and associated kcompat for older kernels | 34 | * o Applied Andrew Mortons patch - e1000 stops working after resume |
35 | * - More errlogging support from Jon Mason <jonmason@us.ibm.com> | ||
36 | * - Fix TSO issues on PPC64 machines -- Jon Mason <jonmason@us.ibm.com> | ||
37 | * | ||
38 | * 5.7.1 12/16/04 | ||
39 | * - Resurrect 82547EI/GI related fix in e1000_intr to avoid deadlocks. This | ||
40 | * fix was removed as it caused system instability. The suspected cause of | ||
41 | * this is the called to e1000_irq_disable in e1000_intr. Inlined the | ||
42 | * required piece of e1000_irq_disable into e1000_intr - Anton Blanchard | ||
43 | * 5.7.0 12/10/04 | ||
44 | * - include fix to the condition that determines when to quit NAPI - Robert Olsson | ||
45 | * - use netif_poll_{disable/enable} to synchronize between NAPI and i/f up/down | ||
46 | * 5.6.5 11/01/04 | ||
47 | * - Enabling NETIF_F_SG without checksum offload is illegal - | ||
48 | John Mason <jdmason@us.ibm.com> | ||
49 | * 5.6.3 10/26/04 | ||
50 | * - Remove redundant initialization - Jamal Hadi | ||
51 | * - Reset buffer_info->dma in tx resource cleanup logic | ||
52 | * 5.6.2 10/12/04 | ||
53 | * - Avoid filling tx_ring completely - shemminger@osdl.org | ||
54 | * - Replace schedule_timeout() with msleep()/msleep_interruptible() - | ||
55 | * nacc@us.ibm.com | ||
56 | * - Sparse cleanup - shemminger@osdl.org | ||
57 | * - Fix tx resource cleanup logic | ||
58 | * - LLTX support - ak@suse.de and hadi@cyberus.ca | ||
59 | */ | 35 | */ |
60 | 36 | ||
61 | char e1000_driver_name[] = "e1000"; | 37 | char e1000_driver_name[] = "e1000"; |
@@ -65,7 +41,7 @@ char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver"; | |||
65 | #else | 41 | #else |
66 | #define DRIVERNAPI "-NAPI" | 42 | #define DRIVERNAPI "-NAPI" |
67 | #endif | 43 | #endif |
68 | #define DRV_VERSION "5.7.6-k2"DRIVERNAPI | 44 | #define DRV_VERSION "6.0.54-k2"DRIVERNAPI |
69 | char e1000_driver_version[] = DRV_VERSION; | 45 | char e1000_driver_version[] = DRV_VERSION; |
70 | char e1000_copyright[] = "Copyright (c) 1999-2004 Intel Corporation."; | 46 | char e1000_copyright[] = "Copyright (c) 1999-2004 Intel Corporation."; |
71 | 47 | ||
@@ -96,6 +72,7 @@ static struct pci_device_id e1000_pci_tbl[] = { | |||
96 | INTEL_E1000_ETHERNET_DEVICE(0x1017), | 72 | INTEL_E1000_ETHERNET_DEVICE(0x1017), |
97 | INTEL_E1000_ETHERNET_DEVICE(0x1018), | 73 | INTEL_E1000_ETHERNET_DEVICE(0x1018), |
98 | INTEL_E1000_ETHERNET_DEVICE(0x1019), | 74 | INTEL_E1000_ETHERNET_DEVICE(0x1019), |
75 | INTEL_E1000_ETHERNET_DEVICE(0x101A), | ||
99 | INTEL_E1000_ETHERNET_DEVICE(0x101D), | 76 | INTEL_E1000_ETHERNET_DEVICE(0x101D), |
100 | INTEL_E1000_ETHERNET_DEVICE(0x101E), | 77 | INTEL_E1000_ETHERNET_DEVICE(0x101E), |
101 | INTEL_E1000_ETHERNET_DEVICE(0x1026), | 78 | INTEL_E1000_ETHERNET_DEVICE(0x1026), |
@@ -110,6 +87,9 @@ static struct pci_device_id e1000_pci_tbl[] = { | |||
110 | INTEL_E1000_ETHERNET_DEVICE(0x107B), | 87 | INTEL_E1000_ETHERNET_DEVICE(0x107B), |
111 | INTEL_E1000_ETHERNET_DEVICE(0x107C), | 88 | INTEL_E1000_ETHERNET_DEVICE(0x107C), |
112 | INTEL_E1000_ETHERNET_DEVICE(0x108A), | 89 | INTEL_E1000_ETHERNET_DEVICE(0x108A), |
90 | INTEL_E1000_ETHERNET_DEVICE(0x108B), | ||
91 | INTEL_E1000_ETHERNET_DEVICE(0x108C), | ||
92 | INTEL_E1000_ETHERNET_DEVICE(0x1099), | ||
113 | /* required last entry */ | 93 | /* required last entry */ |
114 | {0,} | 94 | {0,} |
115 | }; | 95 | }; |
@@ -155,10 +135,14 @@ static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter); | |||
155 | static int e1000_clean(struct net_device *netdev, int *budget); | 135 | static int e1000_clean(struct net_device *netdev, int *budget); |
156 | static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter, | 136 | static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter, |
157 | int *work_done, int work_to_do); | 137 | int *work_done, int work_to_do); |
138 | static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter, | ||
139 | int *work_done, int work_to_do); | ||
158 | #else | 140 | #else |
159 | static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter); | 141 | static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter); |
142 | static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter); | ||
160 | #endif | 143 | #endif |
161 | static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter); | 144 | static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter); |
145 | static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter); | ||
162 | static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd); | 146 | static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd); |
163 | static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, | 147 | static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, |
164 | int cmd); | 148 | int cmd); |
@@ -286,7 +270,29 @@ e1000_irq_enable(struct e1000_adapter *adapter) | |||
286 | E1000_WRITE_FLUSH(&adapter->hw); | 270 | E1000_WRITE_FLUSH(&adapter->hw); |
287 | } | 271 | } |
288 | } | 272 | } |
289 | 273 | void | |
274 | e1000_update_mng_vlan(struct e1000_adapter *adapter) | ||
275 | { | ||
276 | struct net_device *netdev = adapter->netdev; | ||
277 | uint16_t vid = adapter->hw.mng_cookie.vlan_id; | ||
278 | uint16_t old_vid = adapter->mng_vlan_id; | ||
279 | if(adapter->vlgrp) { | ||
280 | if(!adapter->vlgrp->vlan_devices[vid]) { | ||
281 | if(adapter->hw.mng_cookie.status & | ||
282 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) { | ||
283 | e1000_vlan_rx_add_vid(netdev, vid); | ||
284 | adapter->mng_vlan_id = vid; | ||
285 | } else | ||
286 | adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; | ||
287 | |||
288 | if((old_vid != (uint16_t)E1000_MNG_VLAN_NONE) && | ||
289 | (vid != old_vid) && | ||
290 | !adapter->vlgrp->vlan_devices[old_vid]) | ||
291 | e1000_vlan_rx_kill_vid(netdev, old_vid); | ||
292 | } | ||
293 | } | ||
294 | } | ||
295 | |||
290 | int | 296 | int |
291 | e1000_up(struct e1000_adapter *adapter) | 297 | e1000_up(struct e1000_adapter *adapter) |
292 | { | 298 | { |
@@ -310,19 +316,33 @@ e1000_up(struct e1000_adapter *adapter) | |||
310 | e1000_configure_tx(adapter); | 316 | e1000_configure_tx(adapter); |
311 | e1000_setup_rctl(adapter); | 317 | e1000_setup_rctl(adapter); |
312 | e1000_configure_rx(adapter); | 318 | e1000_configure_rx(adapter); |
313 | e1000_alloc_rx_buffers(adapter); | 319 | adapter->alloc_rx_buf(adapter); |
314 | 320 | ||
321 | #ifdef CONFIG_PCI_MSI | ||
322 | if(adapter->hw.mac_type > e1000_82547_rev_2) { | ||
323 | adapter->have_msi = TRUE; | ||
324 | if((err = pci_enable_msi(adapter->pdev))) { | ||
325 | DPRINTK(PROBE, ERR, | ||
326 | "Unable to allocate MSI interrupt Error: %d\n", err); | ||
327 | adapter->have_msi = FALSE; | ||
328 | } | ||
329 | } | ||
330 | #endif | ||
315 | if((err = request_irq(adapter->pdev->irq, &e1000_intr, | 331 | if((err = request_irq(adapter->pdev->irq, &e1000_intr, |
316 | SA_SHIRQ | SA_SAMPLE_RANDOM, | 332 | SA_SHIRQ | SA_SAMPLE_RANDOM, |
317 | netdev->name, netdev))) | 333 | netdev->name, netdev))) { |
334 | DPRINTK(PROBE, ERR, | ||
335 | "Unable to allocate interrupt Error: %d\n", err); | ||
318 | return err; | 336 | return err; |
337 | } | ||
319 | 338 | ||
320 | mod_timer(&adapter->watchdog_timer, jiffies); | 339 | mod_timer(&adapter->watchdog_timer, jiffies); |
321 | e1000_irq_enable(adapter); | ||
322 | 340 | ||
323 | #ifdef CONFIG_E1000_NAPI | 341 | #ifdef CONFIG_E1000_NAPI |
324 | netif_poll_enable(netdev); | 342 | netif_poll_enable(netdev); |
325 | #endif | 343 | #endif |
344 | e1000_irq_enable(adapter); | ||
345 | |||
326 | return 0; | 346 | return 0; |
327 | } | 347 | } |
328 | 348 | ||
@@ -333,6 +353,11 @@ e1000_down(struct e1000_adapter *adapter) | |||
333 | 353 | ||
334 | e1000_irq_disable(adapter); | 354 | e1000_irq_disable(adapter); |
335 | free_irq(adapter->pdev->irq, netdev); | 355 | free_irq(adapter->pdev->irq, netdev); |
356 | #ifdef CONFIG_PCI_MSI | ||
357 | if(adapter->hw.mac_type > e1000_82547_rev_2 && | ||
358 | adapter->have_msi == TRUE) | ||
359 | pci_disable_msi(adapter->pdev); | ||
360 | #endif | ||
336 | del_timer_sync(&adapter->tx_fifo_stall_timer); | 361 | del_timer_sync(&adapter->tx_fifo_stall_timer); |
337 | del_timer_sync(&adapter->watchdog_timer); | 362 | del_timer_sync(&adapter->watchdog_timer); |
338 | del_timer_sync(&adapter->phy_info_timer); | 363 | del_timer_sync(&adapter->phy_info_timer); |
@@ -350,62 +375,93 @@ e1000_down(struct e1000_adapter *adapter) | |||
350 | e1000_clean_rx_ring(adapter); | 375 | e1000_clean_rx_ring(adapter); |
351 | 376 | ||
352 | /* If WoL is not enabled | 377 | /* If WoL is not enabled |
378 | * and management mode is not IAMT | ||
353 | * Power down the PHY so no link is implied when interface is down */ | 379 | * Power down the PHY so no link is implied when interface is down */ |
354 | if(!adapter->wol && adapter->hw.media_type == e1000_media_type_copper) { | 380 | if(!adapter->wol && adapter->hw.mac_type >= e1000_82540 && |
381 | adapter->hw.media_type == e1000_media_type_copper && | ||
382 | !e1000_check_mng_mode(&adapter->hw) && | ||
383 | !(E1000_READ_REG(&adapter->hw, MANC) & E1000_MANC_SMBUS_EN)) { | ||
355 | uint16_t mii_reg; | 384 | uint16_t mii_reg; |
356 | e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg); | 385 | e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg); |
357 | mii_reg |= MII_CR_POWER_DOWN; | 386 | mii_reg |= MII_CR_POWER_DOWN; |
358 | e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg); | 387 | e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg); |
388 | mdelay(1); | ||
359 | } | 389 | } |
360 | } | 390 | } |
361 | 391 | ||
362 | void | 392 | void |
363 | e1000_reset(struct e1000_adapter *adapter) | 393 | e1000_reset(struct e1000_adapter *adapter) |
364 | { | 394 | { |
365 | uint32_t pba; | 395 | struct net_device *netdev = adapter->netdev; |
396 | uint32_t pba, manc; | ||
397 | uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF; | ||
398 | uint16_t fc_low_water_mark = E1000_FC_LOW_DIFF; | ||
366 | 399 | ||
367 | /* Repartition Pba for greater than 9k mtu | 400 | /* Repartition Pba for greater than 9k mtu |
368 | * To take effect CTRL.RST is required. | 401 | * To take effect CTRL.RST is required. |
369 | */ | 402 | */ |
370 | 403 | ||
371 | if(adapter->hw.mac_type < e1000_82547) { | 404 | switch (adapter->hw.mac_type) { |
372 | if(adapter->rx_buffer_len > E1000_RXBUFFER_8192) | 405 | case e1000_82547: |
373 | pba = E1000_PBA_40K; | 406 | case e1000_82547_rev_2: |
374 | else | 407 | pba = E1000_PBA_30K; |
375 | pba = E1000_PBA_48K; | 408 | break; |
376 | } else { | 409 | case e1000_82573: |
377 | if(adapter->rx_buffer_len > E1000_RXBUFFER_8192) | 410 | pba = E1000_PBA_12K; |
378 | pba = E1000_PBA_22K; | 411 | break; |
379 | else | 412 | default: |
380 | pba = E1000_PBA_30K; | 413 | pba = E1000_PBA_48K; |
414 | break; | ||
415 | } | ||
416 | |||
417 | if((adapter->hw.mac_type != e1000_82573) && | ||
418 | (adapter->rx_buffer_len > E1000_RXBUFFER_8192)) { | ||
419 | pba -= 8; /* allocate more FIFO for Tx */ | ||
420 | /* send an XOFF when there is enough space in the | ||
421 | * Rx FIFO to hold one extra full size Rx packet | ||
422 | */ | ||
423 | fc_high_water_mark = netdev->mtu + ENET_HEADER_SIZE + | ||
424 | ETHERNET_FCS_SIZE + 1; | ||
425 | fc_low_water_mark = fc_high_water_mark + 8; | ||
426 | } | ||
427 | |||
428 | |||
429 | if(adapter->hw.mac_type == e1000_82547) { | ||
381 | adapter->tx_fifo_head = 0; | 430 | adapter->tx_fifo_head = 0; |
382 | adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT; | 431 | adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT; |
383 | adapter->tx_fifo_size = | 432 | adapter->tx_fifo_size = |
384 | (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT; | 433 | (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT; |
385 | atomic_set(&adapter->tx_fifo_stall, 0); | 434 | atomic_set(&adapter->tx_fifo_stall, 0); |
386 | } | 435 | } |
436 | |||
387 | E1000_WRITE_REG(&adapter->hw, PBA, pba); | 437 | E1000_WRITE_REG(&adapter->hw, PBA, pba); |
388 | 438 | ||
389 | /* flow control settings */ | 439 | /* flow control settings */ |
390 | adapter->hw.fc_high_water = (pba << E1000_PBA_BYTES_SHIFT) - | 440 | adapter->hw.fc_high_water = (pba << E1000_PBA_BYTES_SHIFT) - |
391 | E1000_FC_HIGH_DIFF; | 441 | fc_high_water_mark; |
392 | adapter->hw.fc_low_water = (pba << E1000_PBA_BYTES_SHIFT) - | 442 | adapter->hw.fc_low_water = (pba << E1000_PBA_BYTES_SHIFT) - |
393 | E1000_FC_LOW_DIFF; | 443 | fc_low_water_mark; |
394 | adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME; | 444 | adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME; |
395 | adapter->hw.fc_send_xon = 1; | 445 | adapter->hw.fc_send_xon = 1; |
396 | adapter->hw.fc = adapter->hw.original_fc; | 446 | adapter->hw.fc = adapter->hw.original_fc; |
397 | 447 | ||
448 | /* Allow time for pending master requests to run */ | ||
398 | e1000_reset_hw(&adapter->hw); | 449 | e1000_reset_hw(&adapter->hw); |
399 | if(adapter->hw.mac_type >= e1000_82544) | 450 | if(adapter->hw.mac_type >= e1000_82544) |
400 | E1000_WRITE_REG(&adapter->hw, WUC, 0); | 451 | E1000_WRITE_REG(&adapter->hw, WUC, 0); |
401 | if(e1000_init_hw(&adapter->hw)) | 452 | if(e1000_init_hw(&adapter->hw)) |
402 | DPRINTK(PROBE, ERR, "Hardware Error\n"); | 453 | DPRINTK(PROBE, ERR, "Hardware Error\n"); |
403 | 454 | e1000_update_mng_vlan(adapter); | |
404 | /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ | 455 | /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ |
405 | E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE); | 456 | E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE); |
406 | 457 | ||
407 | e1000_reset_adaptive(&adapter->hw); | 458 | e1000_reset_adaptive(&adapter->hw); |
408 | e1000_phy_get_info(&adapter->hw, &adapter->phy_info); | 459 | e1000_phy_get_info(&adapter->hw, &adapter->phy_info); |
460 | if (adapter->en_mng_pt) { | ||
461 | manc = E1000_READ_REG(&adapter->hw, MANC); | ||
462 | manc |= (E1000_MANC_ARP_EN | E1000_MANC_EN_MNG2HOST); | ||
463 | E1000_WRITE_REG(&adapter->hw, MANC, manc); | ||
464 | } | ||
409 | } | 465 | } |
410 | 466 | ||
411 | /** | 467 | /** |
@@ -426,15 +482,13 @@ e1000_probe(struct pci_dev *pdev, | |||
426 | { | 482 | { |
427 | struct net_device *netdev; | 483 | struct net_device *netdev; |
428 | struct e1000_adapter *adapter; | 484 | struct e1000_adapter *adapter; |
485 | unsigned long mmio_start, mmio_len; | ||
486 | uint32_t swsm; | ||
487 | |||
429 | static int cards_found = 0; | 488 | static int cards_found = 0; |
430 | unsigned long mmio_start; | 489 | int i, err, pci_using_dac; |
431 | int mmio_len; | ||
432 | int pci_using_dac; | ||
433 | int i; | ||
434 | int err; | ||
435 | uint16_t eeprom_data; | 490 | uint16_t eeprom_data; |
436 | uint16_t eeprom_apme_mask = E1000_EEPROM_APME; | 491 | uint16_t eeprom_apme_mask = E1000_EEPROM_APME; |
437 | |||
438 | if((err = pci_enable_device(pdev))) | 492 | if((err = pci_enable_device(pdev))) |
439 | return err; | 493 | return err; |
440 | 494 | ||
@@ -521,6 +575,9 @@ e1000_probe(struct pci_dev *pdev, | |||
521 | if((err = e1000_sw_init(adapter))) | 575 | if((err = e1000_sw_init(adapter))) |
522 | goto err_sw_init; | 576 | goto err_sw_init; |
523 | 577 | ||
578 | if((err = e1000_check_phy_reset_block(&adapter->hw))) | ||
579 | DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n"); | ||
580 | |||
524 | if(adapter->hw.mac_type >= e1000_82543) { | 581 | if(adapter->hw.mac_type >= e1000_82543) { |
525 | netdev->features = NETIF_F_SG | | 582 | netdev->features = NETIF_F_SG | |
526 | NETIF_F_HW_CSUM | | 583 | NETIF_F_HW_CSUM | |
@@ -533,6 +590,11 @@ e1000_probe(struct pci_dev *pdev, | |||
533 | if((adapter->hw.mac_type >= e1000_82544) && | 590 | if((adapter->hw.mac_type >= e1000_82544) && |
534 | (adapter->hw.mac_type != e1000_82547)) | 591 | (adapter->hw.mac_type != e1000_82547)) |
535 | netdev->features |= NETIF_F_TSO; | 592 | netdev->features |= NETIF_F_TSO; |
593 | |||
594 | #ifdef NETIF_F_TSO_IPV6 | ||
595 | if(adapter->hw.mac_type > e1000_82547_rev_2) | ||
596 | netdev->features |= NETIF_F_TSO_IPV6; | ||
597 | #endif | ||
536 | #endif | 598 | #endif |
537 | if(pci_using_dac) | 599 | if(pci_using_dac) |
538 | netdev->features |= NETIF_F_HIGHDMA; | 600 | netdev->features |= NETIF_F_HIGHDMA; |
@@ -540,6 +602,8 @@ e1000_probe(struct pci_dev *pdev, | |||
540 | /* hard_start_xmit is safe against parallel locking */ | 602 | /* hard_start_xmit is safe against parallel locking */ |
541 | netdev->features |= NETIF_F_LLTX; | 603 | netdev->features |= NETIF_F_LLTX; |
542 | 604 | ||
605 | adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw); | ||
606 | |||
543 | /* before reading the EEPROM, reset the controller to | 607 | /* before reading the EEPROM, reset the controller to |
544 | * put the device in a known good starting state */ | 608 | * put the device in a known good starting state */ |
545 | 609 | ||
@@ -555,7 +619,7 @@ e1000_probe(struct pci_dev *pdev, | |||
555 | 619 | ||
556 | /* copy the MAC address out of the EEPROM */ | 620 | /* copy the MAC address out of the EEPROM */ |
557 | 621 | ||
558 | if (e1000_read_mac_addr(&adapter->hw)) | 622 | if(e1000_read_mac_addr(&adapter->hw)) |
559 | DPRINTK(PROBE, ERR, "EEPROM Read Error\n"); | 623 | DPRINTK(PROBE, ERR, "EEPROM Read Error\n"); |
560 | memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len); | 624 | memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len); |
561 | 625 | ||
@@ -629,6 +693,17 @@ e1000_probe(struct pci_dev *pdev, | |||
629 | /* reset the hardware with the new settings */ | 693 | /* reset the hardware with the new settings */ |
630 | e1000_reset(adapter); | 694 | e1000_reset(adapter); |
631 | 695 | ||
696 | /* Let firmware know the driver has taken over */ | ||
697 | switch(adapter->hw.mac_type) { | ||
698 | case e1000_82573: | ||
699 | swsm = E1000_READ_REG(&adapter->hw, SWSM); | ||
700 | E1000_WRITE_REG(&adapter->hw, SWSM, | ||
701 | swsm | E1000_SWSM_DRV_LOAD); | ||
702 | break; | ||
703 | default: | ||
704 | break; | ||
705 | } | ||
706 | |||
632 | strcpy(netdev->name, "eth%d"); | 707 | strcpy(netdev->name, "eth%d"); |
633 | if((err = register_netdev(netdev))) | 708 | if((err = register_netdev(netdev))) |
634 | goto err_register; | 709 | goto err_register; |
@@ -664,7 +739,7 @@ e1000_remove(struct pci_dev *pdev) | |||
664 | { | 739 | { |
665 | struct net_device *netdev = pci_get_drvdata(pdev); | 740 | struct net_device *netdev = pci_get_drvdata(pdev); |
666 | struct e1000_adapter *adapter = netdev->priv; | 741 | struct e1000_adapter *adapter = netdev->priv; |
667 | uint32_t manc; | 742 | uint32_t manc, swsm; |
668 | 743 | ||
669 | flush_scheduled_work(); | 744 | flush_scheduled_work(); |
670 | 745 | ||
@@ -677,9 +752,21 @@ e1000_remove(struct pci_dev *pdev) | |||
677 | } | 752 | } |
678 | } | 753 | } |
679 | 754 | ||
755 | switch(adapter->hw.mac_type) { | ||
756 | case e1000_82573: | ||
757 | swsm = E1000_READ_REG(&adapter->hw, SWSM); | ||
758 | E1000_WRITE_REG(&adapter->hw, SWSM, | ||
759 | swsm & ~E1000_SWSM_DRV_LOAD); | ||
760 | break; | ||
761 | |||
762 | default: | ||
763 | break; | ||
764 | } | ||
765 | |||
680 | unregister_netdev(netdev); | 766 | unregister_netdev(netdev); |
681 | 767 | ||
682 | e1000_phy_hw_reset(&adapter->hw); | 768 | if(!e1000_check_phy_reset_block(&adapter->hw)) |
769 | e1000_phy_hw_reset(&adapter->hw); | ||
683 | 770 | ||
684 | iounmap(adapter->hw.hw_addr); | 771 | iounmap(adapter->hw.hw_addr); |
685 | pci_release_regions(pdev); | 772 | pci_release_regions(pdev); |
@@ -717,6 +804,7 @@ e1000_sw_init(struct e1000_adapter *adapter) | |||
717 | pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word); | 804 | pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word); |
718 | 805 | ||
719 | adapter->rx_buffer_len = E1000_RXBUFFER_2048; | 806 | adapter->rx_buffer_len = E1000_RXBUFFER_2048; |
807 | adapter->rx_ps_bsize0 = E1000_RXBUFFER_256; | ||
720 | hw->max_frame_size = netdev->mtu + | 808 | hw->max_frame_size = netdev->mtu + |
721 | ENET_HEADER_SIZE + ETHERNET_FCS_SIZE; | 809 | ENET_HEADER_SIZE + ETHERNET_FCS_SIZE; |
722 | hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE; | 810 | hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE; |
@@ -730,7 +818,10 @@ e1000_sw_init(struct e1000_adapter *adapter) | |||
730 | 818 | ||
731 | /* initialize eeprom parameters */ | 819 | /* initialize eeprom parameters */ |
732 | 820 | ||
733 | e1000_init_eeprom_params(hw); | 821 | if(e1000_init_eeprom_params(hw)) { |
822 | E1000_ERR("EEPROM initialization failed\n"); | ||
823 | return -EIO; | ||
824 | } | ||
734 | 825 | ||
735 | switch(hw->mac_type) { | 826 | switch(hw->mac_type) { |
736 | default: | 827 | default: |
@@ -795,6 +886,11 @@ e1000_open(struct net_device *netdev) | |||
795 | 886 | ||
796 | if((err = e1000_up(adapter))) | 887 | if((err = e1000_up(adapter))) |
797 | goto err_up; | 888 | goto err_up; |
889 | adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; | ||
890 | if((adapter->hw.mng_cookie.status & | ||
891 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) { | ||
892 | e1000_update_mng_vlan(adapter); | ||
893 | } | ||
798 | 894 | ||
799 | return E1000_SUCCESS; | 895 | return E1000_SUCCESS; |
800 | 896 | ||
@@ -830,14 +926,18 @@ e1000_close(struct net_device *netdev) | |||
830 | e1000_free_tx_resources(adapter); | 926 | e1000_free_tx_resources(adapter); |
831 | e1000_free_rx_resources(adapter); | 927 | e1000_free_rx_resources(adapter); |
832 | 928 | ||
929 | if((adapter->hw.mng_cookie.status & | ||
930 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) { | ||
931 | e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); | ||
932 | } | ||
833 | return 0; | 933 | return 0; |
834 | } | 934 | } |
835 | 935 | ||
836 | /** | 936 | /** |
837 | * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary | 937 | * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary |
838 | * @adapter: address of board private structure | 938 | * @adapter: address of board private structure |
839 | * @begin: address of beginning of memory | 939 | * @start: address of beginning of memory |
840 | * @end: address of end of memory | 940 | * @len: length of memory |
841 | **/ | 941 | **/ |
842 | static inline boolean_t | 942 | static inline boolean_t |
843 | e1000_check_64k_bound(struct e1000_adapter *adapter, | 943 | e1000_check_64k_bound(struct e1000_adapter *adapter, |
@@ -846,12 +946,10 @@ e1000_check_64k_bound(struct e1000_adapter *adapter, | |||
846 | unsigned long begin = (unsigned long) start; | 946 | unsigned long begin = (unsigned long) start; |
847 | unsigned long end = begin + len; | 947 | unsigned long end = begin + len; |
848 | 948 | ||
849 | /* first rev 82545 and 82546 need to not allow any memory | 949 | /* First rev 82545 and 82546 need to not allow any memory |
850 | * write location to cross a 64k boundary due to errata 23 */ | 950 | * write location to cross 64k boundary due to errata 23 */ |
851 | if (adapter->hw.mac_type == e1000_82545 || | 951 | if (adapter->hw.mac_type == e1000_82545 || |
852 | adapter->hw.mac_type == e1000_82546 ) { | 952 | adapter->hw.mac_type == e1000_82546) { |
853 | |||
854 | /* check buffer doesn't cross 64kB */ | ||
855 | return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE; | 953 | return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE; |
856 | } | 954 | } |
857 | 955 | ||
@@ -875,8 +973,8 @@ e1000_setup_tx_resources(struct e1000_adapter *adapter) | |||
875 | size = sizeof(struct e1000_buffer) * txdr->count; | 973 | size = sizeof(struct e1000_buffer) * txdr->count; |
876 | txdr->buffer_info = vmalloc(size); | 974 | txdr->buffer_info = vmalloc(size); |
877 | if(!txdr->buffer_info) { | 975 | if(!txdr->buffer_info) { |
878 | DPRINTK(PROBE, ERR, | 976 | DPRINTK(PROBE, ERR, |
879 | "Unable to Allocate Memory for the Transmit descriptor ring\n"); | 977 | "Unable to allocate memory for the transmit descriptor ring\n"); |
880 | return -ENOMEM; | 978 | return -ENOMEM; |
881 | } | 979 | } |
882 | memset(txdr->buffer_info, 0, size); | 980 | memset(txdr->buffer_info, 0, size); |
@@ -889,38 +987,38 @@ e1000_setup_tx_resources(struct e1000_adapter *adapter) | |||
889 | txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma); | 987 | txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma); |
890 | if(!txdr->desc) { | 988 | if(!txdr->desc) { |
891 | setup_tx_desc_die: | 989 | setup_tx_desc_die: |
892 | DPRINTK(PROBE, ERR, | ||
893 | "Unable to Allocate Memory for the Transmit descriptor ring\n"); | ||
894 | vfree(txdr->buffer_info); | 990 | vfree(txdr->buffer_info); |
991 | DPRINTK(PROBE, ERR, | ||
992 | "Unable to allocate memory for the transmit descriptor ring\n"); | ||
895 | return -ENOMEM; | 993 | return -ENOMEM; |
896 | } | 994 | } |
897 | 995 | ||
898 | /* fix for errata 23, cant cross 64kB boundary */ | 996 | /* Fix for errata 23, can't cross 64kB boundary */ |
899 | if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) { | 997 | if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) { |
900 | void *olddesc = txdr->desc; | 998 | void *olddesc = txdr->desc; |
901 | dma_addr_t olddma = txdr->dma; | 999 | dma_addr_t olddma = txdr->dma; |
902 | DPRINTK(TX_ERR,ERR,"txdr align check failed: %u bytes at %p\n", | 1000 | DPRINTK(TX_ERR, ERR, "txdr align check failed: %u bytes " |
903 | txdr->size, txdr->desc); | 1001 | "at %p\n", txdr->size, txdr->desc); |
904 | /* try again, without freeing the previous */ | 1002 | /* Try again, without freeing the previous */ |
905 | txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma); | 1003 | txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma); |
906 | /* failed allocation, critial failure */ | ||
907 | if(!txdr->desc) { | 1004 | if(!txdr->desc) { |
1005 | /* Failed allocation, critical failure */ | ||
908 | pci_free_consistent(pdev, txdr->size, olddesc, olddma); | 1006 | pci_free_consistent(pdev, txdr->size, olddesc, olddma); |
909 | goto setup_tx_desc_die; | 1007 | goto setup_tx_desc_die; |
910 | } | 1008 | } |
911 | 1009 | ||
912 | if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) { | 1010 | if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) { |
913 | /* give up */ | 1011 | /* give up */ |
914 | pci_free_consistent(pdev, txdr->size, | 1012 | pci_free_consistent(pdev, txdr->size, txdr->desc, |
915 | txdr->desc, txdr->dma); | 1013 | txdr->dma); |
916 | pci_free_consistent(pdev, txdr->size, olddesc, olddma); | 1014 | pci_free_consistent(pdev, txdr->size, olddesc, olddma); |
917 | DPRINTK(PROBE, ERR, | 1015 | DPRINTK(PROBE, ERR, |
918 | "Unable to Allocate aligned Memory for the Transmit" | 1016 | "Unable to allocate aligned memory " |
919 | " descriptor ring\n"); | 1017 | "for the transmit descriptor ring\n"); |
920 | vfree(txdr->buffer_info); | 1018 | vfree(txdr->buffer_info); |
921 | return -ENOMEM; | 1019 | return -ENOMEM; |
922 | } else { | 1020 | } else { |
923 | /* free old, move on with the new one since its okay */ | 1021 | /* Free old allocation, new allocation was successful */ |
924 | pci_free_consistent(pdev, txdr->size, olddesc, olddma); | 1022 | pci_free_consistent(pdev, txdr->size, olddesc, olddma); |
925 | } | 1023 | } |
926 | } | 1024 | } |
@@ -1022,59 +1120,88 @@ e1000_setup_rx_resources(struct e1000_adapter *adapter) | |||
1022 | { | 1120 | { |
1023 | struct e1000_desc_ring *rxdr = &adapter->rx_ring; | 1121 | struct e1000_desc_ring *rxdr = &adapter->rx_ring; |
1024 | struct pci_dev *pdev = adapter->pdev; | 1122 | struct pci_dev *pdev = adapter->pdev; |
1025 | int size; | 1123 | int size, desc_len; |
1026 | 1124 | ||
1027 | size = sizeof(struct e1000_buffer) * rxdr->count; | 1125 | size = sizeof(struct e1000_buffer) * rxdr->count; |
1028 | rxdr->buffer_info = vmalloc(size); | 1126 | rxdr->buffer_info = vmalloc(size); |
1029 | if(!rxdr->buffer_info) { | 1127 | if(!rxdr->buffer_info) { |
1030 | DPRINTK(PROBE, ERR, | 1128 | DPRINTK(PROBE, ERR, |
1031 | "Unable to Allocate Memory for the Recieve descriptor ring\n"); | 1129 | "Unable to allocate memory for the receive descriptor ring\n"); |
1032 | return -ENOMEM; | 1130 | return -ENOMEM; |
1033 | } | 1131 | } |
1034 | memset(rxdr->buffer_info, 0, size); | 1132 | memset(rxdr->buffer_info, 0, size); |
1035 | 1133 | ||
1134 | size = sizeof(struct e1000_ps_page) * rxdr->count; | ||
1135 | rxdr->ps_page = kmalloc(size, GFP_KERNEL); | ||
1136 | if(!rxdr->ps_page) { | ||
1137 | vfree(rxdr->buffer_info); | ||
1138 | DPRINTK(PROBE, ERR, | ||
1139 | "Unable to allocate memory for the receive descriptor ring\n"); | ||
1140 | return -ENOMEM; | ||
1141 | } | ||
1142 | memset(rxdr->ps_page, 0, size); | ||
1143 | |||
1144 | size = sizeof(struct e1000_ps_page_dma) * rxdr->count; | ||
1145 | rxdr->ps_page_dma = kmalloc(size, GFP_KERNEL); | ||
1146 | if(!rxdr->ps_page_dma) { | ||
1147 | vfree(rxdr->buffer_info); | ||
1148 | kfree(rxdr->ps_page); | ||
1149 | DPRINTK(PROBE, ERR, | ||
1150 | "Unable to allocate memory for the receive descriptor ring\n"); | ||
1151 | return -ENOMEM; | ||
1152 | } | ||
1153 | memset(rxdr->ps_page_dma, 0, size); | ||
1154 | |||
1155 | if(adapter->hw.mac_type <= e1000_82547_rev_2) | ||
1156 | desc_len = sizeof(struct e1000_rx_desc); | ||
1157 | else | ||
1158 | desc_len = sizeof(union e1000_rx_desc_packet_split); | ||
1159 | |||
1036 | /* Round up to nearest 4K */ | 1160 | /* Round up to nearest 4K */ |
1037 | 1161 | ||
1038 | rxdr->size = rxdr->count * sizeof(struct e1000_rx_desc); | 1162 | rxdr->size = rxdr->count * desc_len; |
1039 | E1000_ROUNDUP(rxdr->size, 4096); | 1163 | E1000_ROUNDUP(rxdr->size, 4096); |
1040 | 1164 | ||
1041 | rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma); | 1165 | rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma); |
1042 | 1166 | ||
1043 | if(!rxdr->desc) { | 1167 | if(!rxdr->desc) { |
1044 | setup_rx_desc_die: | 1168 | setup_rx_desc_die: |
1045 | DPRINTK(PROBE, ERR, | ||
1046 | "Unble to Allocate Memory for the Recieve descriptor ring\n"); | ||
1047 | vfree(rxdr->buffer_info); | 1169 | vfree(rxdr->buffer_info); |
1170 | kfree(rxdr->ps_page); | ||
1171 | kfree(rxdr->ps_page_dma); | ||
1172 | DPRINTK(PROBE, ERR, | ||
1173 | "Unable to allocate memory for the receive descriptor ring\n"); | ||
1048 | return -ENOMEM; | 1174 | return -ENOMEM; |
1049 | } | 1175 | } |
1050 | 1176 | ||
1051 | /* fix for errata 23, cant cross 64kB boundary */ | 1177 | /* Fix for errata 23, can't cross 64kB boundary */ |
1052 | if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) { | 1178 | if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) { |
1053 | void *olddesc = rxdr->desc; | 1179 | void *olddesc = rxdr->desc; |
1054 | dma_addr_t olddma = rxdr->dma; | 1180 | dma_addr_t olddma = rxdr->dma; |
1055 | DPRINTK(RX_ERR,ERR, | 1181 | DPRINTK(RX_ERR, ERR, "rxdr align check failed: %u bytes " |
1056 | "rxdr align check failed: %u bytes at %p\n", | 1182 | "at %p\n", rxdr->size, rxdr->desc); |
1057 | rxdr->size, rxdr->desc); | 1183 | /* Try again, without freeing the previous */ |
1058 | /* try again, without freeing the previous */ | ||
1059 | rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma); | 1184 | rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma); |
1060 | /* failed allocation, critial failure */ | ||
1061 | if(!rxdr->desc) { | 1185 | if(!rxdr->desc) { |
1186 | /* Failed allocation, critical failure */ | ||
1062 | pci_free_consistent(pdev, rxdr->size, olddesc, olddma); | 1187 | pci_free_consistent(pdev, rxdr->size, olddesc, olddma); |
1063 | goto setup_rx_desc_die; | 1188 | goto setup_rx_desc_die; |
1064 | } | 1189 | } |
1065 | 1190 | ||
1066 | if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) { | 1191 | if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) { |
1067 | /* give up */ | 1192 | /* give up */ |
1068 | pci_free_consistent(pdev, rxdr->size, | 1193 | pci_free_consistent(pdev, rxdr->size, rxdr->desc, |
1069 | rxdr->desc, rxdr->dma); | 1194 | rxdr->dma); |
1070 | pci_free_consistent(pdev, rxdr->size, olddesc, olddma); | 1195 | pci_free_consistent(pdev, rxdr->size, olddesc, olddma); |
1071 | DPRINTK(PROBE, ERR, | 1196 | DPRINTK(PROBE, ERR, |
1072 | "Unable to Allocate aligned Memory for the" | 1197 | "Unable to allocate aligned memory " |
1073 | " Receive descriptor ring\n"); | 1198 | "for the receive descriptor ring\n"); |
1074 | vfree(rxdr->buffer_info); | 1199 | vfree(rxdr->buffer_info); |
1200 | kfree(rxdr->ps_page); | ||
1201 | kfree(rxdr->ps_page_dma); | ||
1075 | return -ENOMEM; | 1202 | return -ENOMEM; |
1076 | } else { | 1203 | } else { |
1077 | /* free old, move on with the new one since its okay */ | 1204 | /* Free old allocation, new allocation was successful */ |
1078 | pci_free_consistent(pdev, rxdr->size, olddesc, olddma); | 1205 | pci_free_consistent(pdev, rxdr->size, olddesc, olddma); |
1079 | } | 1206 | } |
1080 | } | 1207 | } |
@@ -1087,14 +1214,15 @@ setup_rx_desc_die: | |||
1087 | } | 1214 | } |
1088 | 1215 | ||
1089 | /** | 1216 | /** |
1090 | * e1000_setup_rctl - configure the receive control register | 1217 | * e1000_setup_rctl - configure the receive control registers |
1091 | * @adapter: Board private structure | 1218 | * @adapter: Board private structure |
1092 | **/ | 1219 | **/ |
1093 | 1220 | ||
1094 | static void | 1221 | static void |
1095 | e1000_setup_rctl(struct e1000_adapter *adapter) | 1222 | e1000_setup_rctl(struct e1000_adapter *adapter) |
1096 | { | 1223 | { |
1097 | uint32_t rctl; | 1224 | uint32_t rctl, rfctl; |
1225 | uint32_t psrctl = 0; | ||
1098 | 1226 | ||
1099 | rctl = E1000_READ_REG(&adapter->hw, RCTL); | 1227 | rctl = E1000_READ_REG(&adapter->hw, RCTL); |
1100 | 1228 | ||
@@ -1109,24 +1237,69 @@ e1000_setup_rctl(struct e1000_adapter *adapter) | |||
1109 | else | 1237 | else |
1110 | rctl &= ~E1000_RCTL_SBP; | 1238 | rctl &= ~E1000_RCTL_SBP; |
1111 | 1239 | ||
1240 | if (adapter->netdev->mtu <= ETH_DATA_LEN) | ||
1241 | rctl &= ~E1000_RCTL_LPE; | ||
1242 | else | ||
1243 | rctl |= E1000_RCTL_LPE; | ||
1244 | |||
1112 | /* Setup buffer sizes */ | 1245 | /* Setup buffer sizes */ |
1113 | rctl &= ~(E1000_RCTL_SZ_4096); | 1246 | if(adapter->hw.mac_type == e1000_82573) { |
1114 | rctl |= (E1000_RCTL_BSEX | E1000_RCTL_LPE); | 1247 | /* We can now specify buffers in 1K increments. |
1115 | switch (adapter->rx_buffer_len) { | 1248 | * BSIZE and BSEX are ignored in this case. */ |
1116 | case E1000_RXBUFFER_2048: | 1249 | rctl |= adapter->rx_buffer_len << 0x11; |
1117 | default: | 1250 | } else { |
1118 | rctl |= E1000_RCTL_SZ_2048; | 1251 | rctl &= ~E1000_RCTL_SZ_4096; |
1119 | rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE); | 1252 | rctl |= E1000_RCTL_BSEX; |
1120 | break; | 1253 | switch (adapter->rx_buffer_len) { |
1121 | case E1000_RXBUFFER_4096: | 1254 | case E1000_RXBUFFER_2048: |
1122 | rctl |= E1000_RCTL_SZ_4096; | 1255 | default: |
1123 | break; | 1256 | rctl |= E1000_RCTL_SZ_2048; |
1124 | case E1000_RXBUFFER_8192: | 1257 | rctl &= ~E1000_RCTL_BSEX; |
1125 | rctl |= E1000_RCTL_SZ_8192; | 1258 | break; |
1126 | break; | 1259 | case E1000_RXBUFFER_4096: |
1127 | case E1000_RXBUFFER_16384: | 1260 | rctl |= E1000_RCTL_SZ_4096; |
1128 | rctl |= E1000_RCTL_SZ_16384; | 1261 | break; |
1129 | break; | 1262 | case E1000_RXBUFFER_8192: |
1263 | rctl |= E1000_RCTL_SZ_8192; | ||
1264 | break; | ||
1265 | case E1000_RXBUFFER_16384: | ||
1266 | rctl |= E1000_RCTL_SZ_16384; | ||
1267 | break; | ||
1268 | } | ||
1269 | } | ||
1270 | |||
1271 | #ifdef CONFIG_E1000_PACKET_SPLIT | ||
1272 | /* 82571 and greater support packet-split where the protocol | ||
1273 | * header is placed in skb->data and the packet data is | ||
1274 | * placed in pages hanging off of skb_shinfo(skb)->nr_frags. | ||
1275 | * In the case of a non-split, skb->data is linearly filled, | ||
1276 | * followed by the page buffers. Therefore, skb->data is | ||
1277 | * sized to hold the largest protocol header. | ||
1278 | */ | ||
1279 | adapter->rx_ps = (adapter->hw.mac_type > e1000_82547_rev_2) | ||
1280 | && (adapter->netdev->mtu | ||
1281 | < ((3 * PAGE_SIZE) + adapter->rx_ps_bsize0)); | ||
1282 | #endif | ||
1283 | if(adapter->rx_ps) { | ||
1284 | /* Configure extra packet-split registers */ | ||
1285 | rfctl = E1000_READ_REG(&adapter->hw, RFCTL); | ||
1286 | rfctl |= E1000_RFCTL_EXTEN; | ||
1287 | /* disable IPv6 packet split support */ | ||
1288 | rfctl |= E1000_RFCTL_IPV6_DIS; | ||
1289 | E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl); | ||
1290 | |||
1291 | rctl |= E1000_RCTL_DTYP_PS | E1000_RCTL_SECRC; | ||
1292 | |||
1293 | psrctl |= adapter->rx_ps_bsize0 >> | ||
1294 | E1000_PSRCTL_BSIZE0_SHIFT; | ||
1295 | psrctl |= PAGE_SIZE >> | ||
1296 | E1000_PSRCTL_BSIZE1_SHIFT; | ||
1297 | psrctl |= PAGE_SIZE << | ||
1298 | E1000_PSRCTL_BSIZE2_SHIFT; | ||
1299 | psrctl |= PAGE_SIZE << | ||
1300 | E1000_PSRCTL_BSIZE3_SHIFT; | ||
1301 | |||
1302 | E1000_WRITE_REG(&adapter->hw, PSRCTL, psrctl); | ||
1130 | } | 1303 | } |
1131 | 1304 | ||
1132 | E1000_WRITE_REG(&adapter->hw, RCTL, rctl); | 1305 | E1000_WRITE_REG(&adapter->hw, RCTL, rctl); |
@@ -1143,9 +1316,18 @@ static void | |||
1143 | e1000_configure_rx(struct e1000_adapter *adapter) | 1316 | e1000_configure_rx(struct e1000_adapter *adapter) |
1144 | { | 1317 | { |
1145 | uint64_t rdba = adapter->rx_ring.dma; | 1318 | uint64_t rdba = adapter->rx_ring.dma; |
1146 | uint32_t rdlen = adapter->rx_ring.count * sizeof(struct e1000_rx_desc); | 1319 | uint32_t rdlen, rctl, rxcsum; |
1147 | uint32_t rctl; | 1320 | |
1148 | uint32_t rxcsum; | 1321 | if(adapter->rx_ps) { |
1322 | rdlen = adapter->rx_ring.count * | ||
1323 | sizeof(union e1000_rx_desc_packet_split); | ||
1324 | adapter->clean_rx = e1000_clean_rx_irq_ps; | ||
1325 | adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps; | ||
1326 | } else { | ||
1327 | rdlen = adapter->rx_ring.count * sizeof(struct e1000_rx_desc); | ||
1328 | adapter->clean_rx = e1000_clean_rx_irq; | ||
1329 | adapter->alloc_rx_buf = e1000_alloc_rx_buffers; | ||
1330 | } | ||
1149 | 1331 | ||
1150 | /* disable receives while setting up the descriptors */ | 1332 | /* disable receives while setting up the descriptors */ |
1151 | rctl = E1000_READ_REG(&adapter->hw, RCTL); | 1333 | rctl = E1000_READ_REG(&adapter->hw, RCTL); |
@@ -1172,13 +1354,27 @@ e1000_configure_rx(struct e1000_adapter *adapter) | |||
1172 | E1000_WRITE_REG(&adapter->hw, RDT, 0); | 1354 | E1000_WRITE_REG(&adapter->hw, RDT, 0); |
1173 | 1355 | ||
1174 | /* Enable 82543 Receive Checksum Offload for TCP and UDP */ | 1356 | /* Enable 82543 Receive Checksum Offload for TCP and UDP */ |
1175 | if((adapter->hw.mac_type >= e1000_82543) && | 1357 | if(adapter->hw.mac_type >= e1000_82543) { |
1176 | (adapter->rx_csum == TRUE)) { | ||
1177 | rxcsum = E1000_READ_REG(&adapter->hw, RXCSUM); | 1358 | rxcsum = E1000_READ_REG(&adapter->hw, RXCSUM); |
1178 | rxcsum |= E1000_RXCSUM_TUOFL; | 1359 | if(adapter->rx_csum == TRUE) { |
1360 | rxcsum |= E1000_RXCSUM_TUOFL; | ||
1361 | |||
1362 | /* Enable 82573 IPv4 payload checksum for UDP fragments | ||
1363 | * Must be used in conjunction with packet-split. */ | ||
1364 | if((adapter->hw.mac_type > e1000_82547_rev_2) && | ||
1365 | (adapter->rx_ps)) { | ||
1366 | rxcsum |= E1000_RXCSUM_IPPCSE; | ||
1367 | } | ||
1368 | } else { | ||
1369 | rxcsum &= ~E1000_RXCSUM_TUOFL; | ||
1370 | /* don't need to clear IPPCSE as it defaults to 0 */ | ||
1371 | } | ||
1179 | E1000_WRITE_REG(&adapter->hw, RXCSUM, rxcsum); | 1372 | E1000_WRITE_REG(&adapter->hw, RXCSUM, rxcsum); |
1180 | } | 1373 | } |
1181 | 1374 | ||
1375 | if (adapter->hw.mac_type == e1000_82573) | ||
1376 | E1000_WRITE_REG(&adapter->hw, ERT, 0x0100); | ||
1377 | |||
1182 | /* Enable Receives */ | 1378 | /* Enable Receives */ |
1183 | E1000_WRITE_REG(&adapter->hw, RCTL, rctl); | 1379 | E1000_WRITE_REG(&adapter->hw, RCTL, rctl); |
1184 | } | 1380 | } |
@@ -1210,13 +1406,11 @@ static inline void | |||
1210 | e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter, | 1406 | e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter, |
1211 | struct e1000_buffer *buffer_info) | 1407 | struct e1000_buffer *buffer_info) |
1212 | { | 1408 | { |
1213 | struct pci_dev *pdev = adapter->pdev; | ||
1214 | |||
1215 | if(buffer_info->dma) { | 1409 | if(buffer_info->dma) { |
1216 | pci_unmap_page(pdev, | 1410 | pci_unmap_page(adapter->pdev, |
1217 | buffer_info->dma, | 1411 | buffer_info->dma, |
1218 | buffer_info->length, | 1412 | buffer_info->length, |
1219 | PCI_DMA_TODEVICE); | 1413 | PCI_DMA_TODEVICE); |
1220 | buffer_info->dma = 0; | 1414 | buffer_info->dma = 0; |
1221 | } | 1415 | } |
1222 | if(buffer_info->skb) { | 1416 | if(buffer_info->skb) { |
@@ -1241,7 +1435,7 @@ e1000_clean_tx_ring(struct e1000_adapter *adapter) | |||
1241 | /* Free all the Tx ring sk_buffs */ | 1435 | /* Free all the Tx ring sk_buffs */ |
1242 | 1436 | ||
1243 | if (likely(adapter->previous_buffer_info.skb != NULL)) { | 1437 | if (likely(adapter->previous_buffer_info.skb != NULL)) { |
1244 | e1000_unmap_and_free_tx_resource(adapter, | 1438 | e1000_unmap_and_free_tx_resource(adapter, |
1245 | &adapter->previous_buffer_info); | 1439 | &adapter->previous_buffer_info); |
1246 | } | 1440 | } |
1247 | 1441 | ||
@@ -1281,6 +1475,10 @@ e1000_free_rx_resources(struct e1000_adapter *adapter) | |||
1281 | 1475 | ||
1282 | vfree(rx_ring->buffer_info); | 1476 | vfree(rx_ring->buffer_info); |
1283 | rx_ring->buffer_info = NULL; | 1477 | rx_ring->buffer_info = NULL; |
1478 | kfree(rx_ring->ps_page); | ||
1479 | rx_ring->ps_page = NULL; | ||
1480 | kfree(rx_ring->ps_page_dma); | ||
1481 | rx_ring->ps_page_dma = NULL; | ||
1284 | 1482 | ||
1285 | pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); | 1483 | pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma); |
1286 | 1484 | ||
@@ -1297,16 +1495,19 @@ e1000_clean_rx_ring(struct e1000_adapter *adapter) | |||
1297 | { | 1495 | { |
1298 | struct e1000_desc_ring *rx_ring = &adapter->rx_ring; | 1496 | struct e1000_desc_ring *rx_ring = &adapter->rx_ring; |
1299 | struct e1000_buffer *buffer_info; | 1497 | struct e1000_buffer *buffer_info; |
1498 | struct e1000_ps_page *ps_page; | ||
1499 | struct e1000_ps_page_dma *ps_page_dma; | ||
1300 | struct pci_dev *pdev = adapter->pdev; | 1500 | struct pci_dev *pdev = adapter->pdev; |
1301 | unsigned long size; | 1501 | unsigned long size; |
1302 | unsigned int i; | 1502 | unsigned int i, j; |
1303 | 1503 | ||
1304 | /* Free all the Rx ring sk_buffs */ | 1504 | /* Free all the Rx ring sk_buffs */ |
1305 | 1505 | ||
1306 | for(i = 0; i < rx_ring->count; i++) { | 1506 | for(i = 0; i < rx_ring->count; i++) { |
1307 | buffer_info = &rx_ring->buffer_info[i]; | 1507 | buffer_info = &rx_ring->buffer_info[i]; |
1308 | if(buffer_info->skb) { | 1508 | if(buffer_info->skb) { |
1309 | 1509 | ps_page = &rx_ring->ps_page[i]; | |
1510 | ps_page_dma = &rx_ring->ps_page_dma[i]; | ||
1310 | pci_unmap_single(pdev, | 1511 | pci_unmap_single(pdev, |
1311 | buffer_info->dma, | 1512 | buffer_info->dma, |
1312 | buffer_info->length, | 1513 | buffer_info->length, |
@@ -1314,11 +1515,25 @@ e1000_clean_rx_ring(struct e1000_adapter *adapter) | |||
1314 | 1515 | ||
1315 | dev_kfree_skb(buffer_info->skb); | 1516 | dev_kfree_skb(buffer_info->skb); |
1316 | buffer_info->skb = NULL; | 1517 | buffer_info->skb = NULL; |
1518 | |||
1519 | for(j = 0; j < PS_PAGE_BUFFERS; j++) { | ||
1520 | if(!ps_page->ps_page[j]) break; | ||
1521 | pci_unmap_single(pdev, | ||
1522 | ps_page_dma->ps_page_dma[j], | ||
1523 | PAGE_SIZE, PCI_DMA_FROMDEVICE); | ||
1524 | ps_page_dma->ps_page_dma[j] = 0; | ||
1525 | put_page(ps_page->ps_page[j]); | ||
1526 | ps_page->ps_page[j] = NULL; | ||
1527 | } | ||
1317 | } | 1528 | } |
1318 | } | 1529 | } |
1319 | 1530 | ||
1320 | size = sizeof(struct e1000_buffer) * rx_ring->count; | 1531 | size = sizeof(struct e1000_buffer) * rx_ring->count; |
1321 | memset(rx_ring->buffer_info, 0, size); | 1532 | memset(rx_ring->buffer_info, 0, size); |
1533 | size = sizeof(struct e1000_ps_page) * rx_ring->count; | ||
1534 | memset(rx_ring->ps_page, 0, size); | ||
1535 | size = sizeof(struct e1000_ps_page_dma) * rx_ring->count; | ||
1536 | memset(rx_ring->ps_page_dma, 0, size); | ||
1322 | 1537 | ||
1323 | /* Zero out the descriptor ring */ | 1538 | /* Zero out the descriptor ring */ |
1324 | 1539 | ||
@@ -1422,15 +1637,15 @@ e1000_set_multi(struct net_device *netdev) | |||
1422 | struct e1000_adapter *adapter = netdev->priv; | 1637 | struct e1000_adapter *adapter = netdev->priv; |
1423 | struct e1000_hw *hw = &adapter->hw; | 1638 | struct e1000_hw *hw = &adapter->hw; |
1424 | struct dev_mc_list *mc_ptr; | 1639 | struct dev_mc_list *mc_ptr; |
1640 | unsigned long flags; | ||
1425 | uint32_t rctl; | 1641 | uint32_t rctl; |
1426 | uint32_t hash_value; | 1642 | uint32_t hash_value; |
1427 | int i; | 1643 | int i; |
1428 | unsigned long flags; | ||
1429 | |||
1430 | /* Check for Promiscuous and All Multicast modes */ | ||
1431 | 1644 | ||
1432 | spin_lock_irqsave(&adapter->tx_lock, flags); | 1645 | spin_lock_irqsave(&adapter->tx_lock, flags); |
1433 | 1646 | ||
1647 | /* Check for Promiscuous and All Multicast modes */ | ||
1648 | |||
1434 | rctl = E1000_READ_REG(hw, RCTL); | 1649 | rctl = E1000_READ_REG(hw, RCTL); |
1435 | 1650 | ||
1436 | if(netdev->flags & IFF_PROMISC) { | 1651 | if(netdev->flags & IFF_PROMISC) { |
@@ -1556,6 +1771,11 @@ e1000_watchdog_task(struct e1000_adapter *adapter) | |||
1556 | uint32_t link; | 1771 | uint32_t link; |
1557 | 1772 | ||
1558 | e1000_check_for_link(&adapter->hw); | 1773 | e1000_check_for_link(&adapter->hw); |
1774 | if (adapter->hw.mac_type == e1000_82573) { | ||
1775 | e1000_enable_tx_pkt_filtering(&adapter->hw); | ||
1776 | if(adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id) | ||
1777 | e1000_update_mng_vlan(adapter); | ||
1778 | } | ||
1559 | 1779 | ||
1560 | if((adapter->hw.media_type == e1000_media_type_internal_serdes) && | 1780 | if((adapter->hw.media_type == e1000_media_type_internal_serdes) && |
1561 | !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE)) | 1781 | !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE)) |
@@ -1632,7 +1852,7 @@ e1000_watchdog_task(struct e1000_adapter *adapter) | |||
1632 | /* Cause software interrupt to ensure rx ring is cleaned */ | 1852 | /* Cause software interrupt to ensure rx ring is cleaned */ |
1633 | E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0); | 1853 | E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0); |
1634 | 1854 | ||
1635 | /* Force detection of hung controller every watchdog period*/ | 1855 | /* Force detection of hung controller every watchdog period */ |
1636 | adapter->detect_tx_hung = TRUE; | 1856 | adapter->detect_tx_hung = TRUE; |
1637 | 1857 | ||
1638 | /* Reset the timer */ | 1858 | /* Reset the timer */ |
@@ -1642,6 +1862,7 @@ e1000_watchdog_task(struct e1000_adapter *adapter) | |||
1642 | #define E1000_TX_FLAGS_CSUM 0x00000001 | 1862 | #define E1000_TX_FLAGS_CSUM 0x00000001 |
1643 | #define E1000_TX_FLAGS_VLAN 0x00000002 | 1863 | #define E1000_TX_FLAGS_VLAN 0x00000002 |
1644 | #define E1000_TX_FLAGS_TSO 0x00000004 | 1864 | #define E1000_TX_FLAGS_TSO 0x00000004 |
1865 | #define E1000_TX_FLAGS_IPV4 0x00000008 | ||
1645 | #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000 | 1866 | #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000 |
1646 | #define E1000_TX_FLAGS_VLAN_SHIFT 16 | 1867 | #define E1000_TX_FLAGS_VLAN_SHIFT 16 |
1647 | 1868 | ||
@@ -1652,7 +1873,7 @@ e1000_tso(struct e1000_adapter *adapter, struct sk_buff *skb) | |||
1652 | struct e1000_context_desc *context_desc; | 1873 | struct e1000_context_desc *context_desc; |
1653 | unsigned int i; | 1874 | unsigned int i; |
1654 | uint32_t cmd_length = 0; | 1875 | uint32_t cmd_length = 0; |
1655 | uint16_t ipcse, tucse, mss; | 1876 | uint16_t ipcse = 0, tucse, mss; |
1656 | uint8_t ipcss, ipcso, tucss, tucso, hdr_len; | 1877 | uint8_t ipcss, ipcso, tucss, tucso, hdr_len; |
1657 | int err; | 1878 | int err; |
1658 | 1879 | ||
@@ -1665,23 +1886,37 @@ e1000_tso(struct e1000_adapter *adapter, struct sk_buff *skb) | |||
1665 | 1886 | ||
1666 | hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2)); | 1887 | hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2)); |
1667 | mss = skb_shinfo(skb)->tso_size; | 1888 | mss = skb_shinfo(skb)->tso_size; |
1668 | skb->nh.iph->tot_len = 0; | 1889 | if(skb->protocol == ntohs(ETH_P_IP)) { |
1669 | skb->nh.iph->check = 0; | 1890 | skb->nh.iph->tot_len = 0; |
1670 | skb->h.th->check = ~csum_tcpudp_magic(skb->nh.iph->saddr, | 1891 | skb->nh.iph->check = 0; |
1671 | skb->nh.iph->daddr, | 1892 | skb->h.th->check = |
1672 | 0, | 1893 | ~csum_tcpudp_magic(skb->nh.iph->saddr, |
1673 | IPPROTO_TCP, | 1894 | skb->nh.iph->daddr, |
1674 | 0); | 1895 | 0, |
1896 | IPPROTO_TCP, | ||
1897 | 0); | ||
1898 | cmd_length = E1000_TXD_CMD_IP; | ||
1899 | ipcse = skb->h.raw - skb->data - 1; | ||
1900 | #ifdef NETIF_F_TSO_IPV6 | ||
1901 | } else if(skb->protocol == ntohs(ETH_P_IPV6)) { | ||
1902 | skb->nh.ipv6h->payload_len = 0; | ||
1903 | skb->h.th->check = | ||
1904 | ~csum_ipv6_magic(&skb->nh.ipv6h->saddr, | ||
1905 | &skb->nh.ipv6h->daddr, | ||
1906 | 0, | ||
1907 | IPPROTO_TCP, | ||
1908 | 0); | ||
1909 | ipcse = 0; | ||
1910 | #endif | ||
1911 | } | ||
1675 | ipcss = skb->nh.raw - skb->data; | 1912 | ipcss = skb->nh.raw - skb->data; |
1676 | ipcso = (void *)&(skb->nh.iph->check) - (void *)skb->data; | 1913 | ipcso = (void *)&(skb->nh.iph->check) - (void *)skb->data; |
1677 | ipcse = skb->h.raw - skb->data - 1; | ||
1678 | tucss = skb->h.raw - skb->data; | 1914 | tucss = skb->h.raw - skb->data; |
1679 | tucso = (void *)&(skb->h.th->check) - (void *)skb->data; | 1915 | tucso = (void *)&(skb->h.th->check) - (void *)skb->data; |
1680 | tucse = 0; | 1916 | tucse = 0; |
1681 | 1917 | ||
1682 | cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE | | 1918 | cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE | |
1683 | E1000_TXD_CMD_IP | E1000_TXD_CMD_TCP | | 1919 | E1000_TXD_CMD_TCP | (skb->len - (hdr_len))); |
1684 | (skb->len - (hdr_len))); | ||
1685 | 1920 | ||
1686 | i = adapter->tx_ring.next_to_use; | 1921 | i = adapter->tx_ring.next_to_use; |
1687 | context_desc = E1000_CONTEXT_DESC(adapter->tx_ring, i); | 1922 | context_desc = E1000_CONTEXT_DESC(adapter->tx_ring, i); |
@@ -1760,6 +1995,15 @@ e1000_tx_map(struct e1000_adapter *adapter, struct sk_buff *skb, | |||
1760 | if(unlikely(mss && !nr_frags && size == len && size > 8)) | 1995 | if(unlikely(mss && !nr_frags && size == len && size > 8)) |
1761 | size -= 4; | 1996 | size -= 4; |
1762 | #endif | 1997 | #endif |
1998 | /* work-around for errata 10 and it applies | ||
1999 | * to all controllers in PCI-X mode | ||
2000 | * The fix is to make sure that the first descriptor of a | ||
2001 | * packet is smaller than 2048 - 16 - 16 (or 2016) bytes | ||
2002 | */ | ||
2003 | if(unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) && | ||
2004 | (size > 2015) && count == 0)) | ||
2005 | size = 2015; | ||
2006 | |||
1763 | /* Workaround for potential 82544 hang in PCI-X. Avoid | 2007 | /* Workaround for potential 82544 hang in PCI-X. Avoid |
1764 | * terminating buffers within evenly-aligned dwords. */ | 2008 | * terminating buffers within evenly-aligned dwords. */ |
1765 | if(unlikely(adapter->pcix_82544 && | 2009 | if(unlikely(adapter->pcix_82544 && |
@@ -1840,7 +2084,10 @@ e1000_tx_queue(struct e1000_adapter *adapter, int count, int tx_flags) | |||
1840 | if(likely(tx_flags & E1000_TX_FLAGS_TSO)) { | 2084 | if(likely(tx_flags & E1000_TX_FLAGS_TSO)) { |
1841 | txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D | | 2085 | txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D | |
1842 | E1000_TXD_CMD_TSE; | 2086 | E1000_TXD_CMD_TSE; |
1843 | txd_upper |= (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8; | 2087 | txd_upper |= E1000_TXD_POPTS_TXSM << 8; |
2088 | |||
2089 | if(likely(tx_flags & E1000_TX_FLAGS_IPV4)) | ||
2090 | txd_upper |= E1000_TXD_POPTS_IXSM << 8; | ||
1844 | } | 2091 | } |
1845 | 2092 | ||
1846 | if(likely(tx_flags & E1000_TX_FLAGS_CSUM)) { | 2093 | if(likely(tx_flags & E1000_TX_FLAGS_CSUM)) { |
@@ -1915,6 +2162,53 @@ no_fifo_stall_required: | |||
1915 | return 0; | 2162 | return 0; |
1916 | } | 2163 | } |
1917 | 2164 | ||
2165 | #define MINIMUM_DHCP_PACKET_SIZE 282 | ||
2166 | static inline int | ||
2167 | e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb) | ||
2168 | { | ||
2169 | struct e1000_hw *hw = &adapter->hw; | ||
2170 | uint16_t length, offset; | ||
2171 | if(vlan_tx_tag_present(skb)) { | ||
2172 | if(!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) && | ||
2173 | ( adapter->hw.mng_cookie.status & | ||
2174 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) ) | ||
2175 | return 0; | ||
2176 | } | ||
2177 | if(htons(ETH_P_IP) == skb->protocol) { | ||
2178 | const struct iphdr *ip = skb->nh.iph; | ||
2179 | if(IPPROTO_UDP == ip->protocol) { | ||
2180 | struct udphdr *udp = (struct udphdr *)(skb->h.uh); | ||
2181 | if(ntohs(udp->dest) == 67) { | ||
2182 | offset = (uint8_t *)udp + 8 - skb->data; | ||
2183 | length = skb->len - offset; | ||
2184 | |||
2185 | return e1000_mng_write_dhcp_info(hw, | ||
2186 | (uint8_t *)udp + 8, length); | ||
2187 | } | ||
2188 | } | ||
2189 | } else if((skb->len > MINIMUM_DHCP_PACKET_SIZE) && (!skb->protocol)) { | ||
2190 | struct ethhdr *eth = (struct ethhdr *) skb->data; | ||
2191 | if((htons(ETH_P_IP) == eth->h_proto)) { | ||
2192 | const struct iphdr *ip = | ||
2193 | (struct iphdr *)((uint8_t *)skb->data+14); | ||
2194 | if(IPPROTO_UDP == ip->protocol) { | ||
2195 | struct udphdr *udp = | ||
2196 | (struct udphdr *)((uint8_t *)ip + | ||
2197 | (ip->ihl << 2)); | ||
2198 | if(ntohs(udp->dest) == 67) { | ||
2199 | offset = (uint8_t *)udp + 8 - skb->data; | ||
2200 | length = skb->len - offset; | ||
2201 | |||
2202 | return e1000_mng_write_dhcp_info(hw, | ||
2203 | (uint8_t *)udp + 8, | ||
2204 | length); | ||
2205 | } | ||
2206 | } | ||
2207 | } | ||
2208 | } | ||
2209 | return 0; | ||
2210 | } | ||
2211 | |||
1918 | #define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 ) | 2212 | #define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 ) |
1919 | static int | 2213 | static int |
1920 | e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev) | 2214 | e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev) |
@@ -1939,7 +2233,7 @@ e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev) | |||
1939 | 2233 | ||
1940 | #ifdef NETIF_F_TSO | 2234 | #ifdef NETIF_F_TSO |
1941 | mss = skb_shinfo(skb)->tso_size; | 2235 | mss = skb_shinfo(skb)->tso_size; |
1942 | /* The controller does a simple calculation to | 2236 | /* The controller does a simple calculation to |
1943 | * make sure there is enough room in the FIFO before | 2237 | * make sure there is enough room in the FIFO before |
1944 | * initiating the DMA for each buffer. The calc is: | 2238 | * initiating the DMA for each buffer. The calc is: |
1945 | * 4 = ceil(buffer len/mss). To make sure we don't | 2239 | * 4 = ceil(buffer len/mss). To make sure we don't |
@@ -1952,7 +2246,7 @@ e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev) | |||
1952 | 2246 | ||
1953 | if((mss) || (skb->ip_summed == CHECKSUM_HW)) | 2247 | if((mss) || (skb->ip_summed == CHECKSUM_HW)) |
1954 | count++; | 2248 | count++; |
1955 | count++; /* for sentinel desc */ | 2249 | count++; |
1956 | #else | 2250 | #else |
1957 | if(skb->ip_summed == CHECKSUM_HW) | 2251 | if(skb->ip_summed == CHECKSUM_HW) |
1958 | count++; | 2252 | count++; |
@@ -1962,6 +2256,13 @@ e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev) | |||
1962 | if(adapter->pcix_82544) | 2256 | if(adapter->pcix_82544) |
1963 | count++; | 2257 | count++; |
1964 | 2258 | ||
2259 | /* work-around for errata 10 and it applies to all controllers | ||
2260 | * in PCI-X mode, so add one more descriptor to the count | ||
2261 | */ | ||
2262 | if(unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) && | ||
2263 | (len > 2015))) | ||
2264 | count++; | ||
2265 | |||
1965 | nr_frags = skb_shinfo(skb)->nr_frags; | 2266 | nr_frags = skb_shinfo(skb)->nr_frags; |
1966 | for(f = 0; f < nr_frags; f++) | 2267 | for(f = 0; f < nr_frags; f++) |
1967 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size, | 2268 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size, |
@@ -1975,6 +2276,9 @@ e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev) | |||
1975 | local_irq_restore(flags); | 2276 | local_irq_restore(flags); |
1976 | return NETDEV_TX_LOCKED; | 2277 | return NETDEV_TX_LOCKED; |
1977 | } | 2278 | } |
2279 | if(adapter->hw.tx_pkt_filtering && (adapter->hw.mac_type == e1000_82573) ) | ||
2280 | e1000_transfer_dhcp_info(adapter, skb); | ||
2281 | |||
1978 | 2282 | ||
1979 | /* need: count + 2 desc gap to keep tail from touching | 2283 | /* need: count + 2 desc gap to keep tail from touching |
1980 | * head, otherwise try next time */ | 2284 | * head, otherwise try next time */ |
@@ -2011,6 +2315,12 @@ e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev) | |||
2011 | else if(likely(e1000_tx_csum(adapter, skb))) | 2315 | else if(likely(e1000_tx_csum(adapter, skb))) |
2012 | tx_flags |= E1000_TX_FLAGS_CSUM; | 2316 | tx_flags |= E1000_TX_FLAGS_CSUM; |
2013 | 2317 | ||
2318 | /* Old method was to assume IPv4 packet by default if TSO was enabled. | ||
2319 | * 82573 hardware supports TSO capabilities for IPv6 as well... | ||
2320 | * no longer assume, we must. */ | ||
2321 | if(likely(skb->protocol == ntohs(ETH_P_IP))) | ||
2322 | tx_flags |= E1000_TX_FLAGS_IPV4; | ||
2323 | |||
2014 | e1000_tx_queue(adapter, | 2324 | e1000_tx_queue(adapter, |
2015 | e1000_tx_map(adapter, skb, first, max_per_txd, nr_frags, mss), | 2325 | e1000_tx_map(adapter, skb, first, max_per_txd, nr_frags, mss), |
2016 | tx_flags); | 2326 | tx_flags); |
@@ -2077,7 +2387,6 @@ static int | |||
2077 | e1000_change_mtu(struct net_device *netdev, int new_mtu) | 2387 | e1000_change_mtu(struct net_device *netdev, int new_mtu) |
2078 | { | 2388 | { |
2079 | struct e1000_adapter *adapter = netdev->priv; | 2389 | struct e1000_adapter *adapter = netdev->priv; |
2080 | int old_mtu = adapter->rx_buffer_len; | ||
2081 | int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE; | 2390 | int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE; |
2082 | 2391 | ||
2083 | if((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) || | 2392 | if((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) || |
@@ -2086,29 +2395,45 @@ e1000_change_mtu(struct net_device *netdev, int new_mtu) | |||
2086 | return -EINVAL; | 2395 | return -EINVAL; |
2087 | } | 2396 | } |
2088 | 2397 | ||
2089 | if(max_frame <= MAXIMUM_ETHERNET_FRAME_SIZE) { | 2398 | #define MAX_STD_JUMBO_FRAME_SIZE 9216 |
2090 | adapter->rx_buffer_len = E1000_RXBUFFER_2048; | 2399 | /* might want this to be bigger enum check... */ |
2091 | 2400 | if (adapter->hw.mac_type == e1000_82573 && | |
2092 | } else if(adapter->hw.mac_type < e1000_82543) { | 2401 | max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) { |
2093 | DPRINTK(PROBE, ERR, "Jumbo Frames not supported on 82542\n"); | 2402 | DPRINTK(PROBE, ERR, "Jumbo Frames not supported " |
2403 | "on 82573\n"); | ||
2094 | return -EINVAL; | 2404 | return -EINVAL; |
2405 | } | ||
2095 | 2406 | ||
2096 | } else if(max_frame <= E1000_RXBUFFER_4096) { | 2407 | if(adapter->hw.mac_type > e1000_82547_rev_2) { |
2097 | adapter->rx_buffer_len = E1000_RXBUFFER_4096; | 2408 | adapter->rx_buffer_len = max_frame; |
2098 | 2409 | E1000_ROUNDUP(adapter->rx_buffer_len, 1024); | |
2099 | } else if(max_frame <= E1000_RXBUFFER_8192) { | ||
2100 | adapter->rx_buffer_len = E1000_RXBUFFER_8192; | ||
2101 | |||
2102 | } else { | 2410 | } else { |
2103 | adapter->rx_buffer_len = E1000_RXBUFFER_16384; | 2411 | if(unlikely((adapter->hw.mac_type < e1000_82543) && |
2412 | (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE))) { | ||
2413 | DPRINTK(PROBE, ERR, "Jumbo Frames not supported " | ||
2414 | "on 82542\n"); | ||
2415 | return -EINVAL; | ||
2416 | |||
2417 | } else { | ||
2418 | if(max_frame <= E1000_RXBUFFER_2048) { | ||
2419 | adapter->rx_buffer_len = E1000_RXBUFFER_2048; | ||
2420 | } else if(max_frame <= E1000_RXBUFFER_4096) { | ||
2421 | adapter->rx_buffer_len = E1000_RXBUFFER_4096; | ||
2422 | } else if(max_frame <= E1000_RXBUFFER_8192) { | ||
2423 | adapter->rx_buffer_len = E1000_RXBUFFER_8192; | ||
2424 | } else if(max_frame <= E1000_RXBUFFER_16384) { | ||
2425 | adapter->rx_buffer_len = E1000_RXBUFFER_16384; | ||
2426 | } | ||
2427 | } | ||
2104 | } | 2428 | } |
2105 | 2429 | ||
2106 | if(old_mtu != adapter->rx_buffer_len && netif_running(netdev)) { | 2430 | netdev->mtu = new_mtu; |
2431 | |||
2432 | if(netif_running(netdev)) { | ||
2107 | e1000_down(adapter); | 2433 | e1000_down(adapter); |
2108 | e1000_up(adapter); | 2434 | e1000_up(adapter); |
2109 | } | 2435 | } |
2110 | 2436 | ||
2111 | netdev->mtu = new_mtu; | ||
2112 | adapter->hw.max_frame_size = max_frame; | 2437 | adapter->hw.max_frame_size = max_frame; |
2113 | 2438 | ||
2114 | return 0; | 2439 | return 0; |
@@ -2199,6 +2524,17 @@ e1000_update_stats(struct e1000_adapter *adapter) | |||
2199 | adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC); | 2524 | adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC); |
2200 | adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC); | 2525 | adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC); |
2201 | } | 2526 | } |
2527 | if(hw->mac_type > e1000_82547_rev_2) { | ||
2528 | adapter->stats.iac += E1000_READ_REG(hw, IAC); | ||
2529 | adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC); | ||
2530 | adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC); | ||
2531 | adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC); | ||
2532 | adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC); | ||
2533 | adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC); | ||
2534 | adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC); | ||
2535 | adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC); | ||
2536 | adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC); | ||
2537 | } | ||
2202 | 2538 | ||
2203 | /* Fill out the OS statistics structure */ | 2539 | /* Fill out the OS statistics structure */ |
2204 | 2540 | ||
@@ -2213,9 +2549,9 @@ e1000_update_stats(struct e1000_adapter *adapter) | |||
2213 | 2549 | ||
2214 | adapter->net_stats.rx_errors = adapter->stats.rxerrc + | 2550 | adapter->net_stats.rx_errors = adapter->stats.rxerrc + |
2215 | adapter->stats.crcerrs + adapter->stats.algnerrc + | 2551 | adapter->stats.crcerrs + adapter->stats.algnerrc + |
2216 | adapter->stats.rlec + adapter->stats.rnbc + | 2552 | adapter->stats.rlec + adapter->stats.mpc + |
2217 | adapter->stats.mpc + adapter->stats.cexterr; | 2553 | adapter->stats.cexterr; |
2218 | adapter->net_stats.rx_dropped = adapter->stats.rnbc; | 2554 | adapter->net_stats.rx_dropped = adapter->stats.mpc; |
2219 | adapter->net_stats.rx_length_errors = adapter->stats.rlec; | 2555 | adapter->net_stats.rx_length_errors = adapter->stats.rlec; |
2220 | adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs; | 2556 | adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs; |
2221 | adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc; | 2557 | adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc; |
@@ -2300,11 +2636,11 @@ e1000_intr(int irq, void *data, struct pt_regs *regs) | |||
2300 | */ | 2636 | */ |
2301 | if(hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2){ | 2637 | if(hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2){ |
2302 | atomic_inc(&adapter->irq_sem); | 2638 | atomic_inc(&adapter->irq_sem); |
2303 | E1000_WRITE_REG(&adapter->hw, IMC, ~0); | 2639 | E1000_WRITE_REG(hw, IMC, ~0); |
2304 | } | 2640 | } |
2305 | 2641 | ||
2306 | for(i = 0; i < E1000_MAX_INTR; i++) | 2642 | for(i = 0; i < E1000_MAX_INTR; i++) |
2307 | if(unlikely(!e1000_clean_rx_irq(adapter) & | 2643 | if(unlikely(!adapter->clean_rx(adapter) & |
2308 | !e1000_clean_tx_irq(adapter))) | 2644 | !e1000_clean_tx_irq(adapter))) |
2309 | break; | 2645 | break; |
2310 | 2646 | ||
@@ -2328,16 +2664,15 @@ e1000_clean(struct net_device *netdev, int *budget) | |||
2328 | int work_to_do = min(*budget, netdev->quota); | 2664 | int work_to_do = min(*budget, netdev->quota); |
2329 | int tx_cleaned; | 2665 | int tx_cleaned; |
2330 | int work_done = 0; | 2666 | int work_done = 0; |
2331 | 2667 | ||
2332 | tx_cleaned = e1000_clean_tx_irq(adapter); | 2668 | tx_cleaned = e1000_clean_tx_irq(adapter); |
2333 | e1000_clean_rx_irq(adapter, &work_done, work_to_do); | 2669 | adapter->clean_rx(adapter, &work_done, work_to_do); |
2334 | 2670 | ||
2335 | *budget -= work_done; | 2671 | *budget -= work_done; |
2336 | netdev->quota -= work_done; | 2672 | netdev->quota -= work_done; |
2337 | 2673 | ||
2338 | /* if no Tx and not enough Rx work done, exit the polling mode */ | 2674 | /* If no Tx and no Rx work done, exit the polling mode */ |
2339 | if((!tx_cleaned && (work_done < work_to_do)) || | 2675 | if ((!tx_cleaned && (work_done == 0)) || !netif_running(netdev)) { |
2340 | !netif_running(netdev)) { | ||
2341 | netif_rx_complete(netdev); | 2676 | netif_rx_complete(netdev); |
2342 | e1000_irq_enable(adapter); | 2677 | e1000_irq_enable(adapter); |
2343 | return 0; | 2678 | return 0; |
@@ -2367,11 +2702,10 @@ e1000_clean_tx_irq(struct e1000_adapter *adapter) | |||
2367 | eop_desc = E1000_TX_DESC(*tx_ring, eop); | 2702 | eop_desc = E1000_TX_DESC(*tx_ring, eop); |
2368 | 2703 | ||
2369 | while(eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) { | 2704 | while(eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) { |
2370 | /* pre-mature writeback of Tx descriptors */ | 2705 | /* Premature writeback of Tx descriptors clear (free buffers |
2371 | /* clear (free buffers and unmap pci_mapping) */ | 2706 | * and unmap pci_mapping) previous_buffer_info */ |
2372 | /* previous_buffer_info */ | ||
2373 | if (likely(adapter->previous_buffer_info.skb != NULL)) { | 2707 | if (likely(adapter->previous_buffer_info.skb != NULL)) { |
2374 | e1000_unmap_and_free_tx_resource(adapter, | 2708 | e1000_unmap_and_free_tx_resource(adapter, |
2375 | &adapter->previous_buffer_info); | 2709 | &adapter->previous_buffer_info); |
2376 | } | 2710 | } |
2377 | 2711 | ||
@@ -2380,26 +2714,30 @@ e1000_clean_tx_irq(struct e1000_adapter *adapter) | |||
2380 | buffer_info = &tx_ring->buffer_info[i]; | 2714 | buffer_info = &tx_ring->buffer_info[i]; |
2381 | cleaned = (i == eop); | 2715 | cleaned = (i == eop); |
2382 | 2716 | ||
2383 | /* pre-mature writeback of Tx descriptors */ | 2717 | #ifdef NETIF_F_TSO |
2384 | /* save the cleaning of the this for the */ | 2718 | if (!(netdev->features & NETIF_F_TSO)) { |
2385 | /* next iteration */ | 2719 | #endif |
2386 | if (cleaned) { | 2720 | e1000_unmap_and_free_tx_resource(adapter, |
2387 | memcpy(&adapter->previous_buffer_info, | 2721 | buffer_info); |
2388 | buffer_info, | 2722 | #ifdef NETIF_F_TSO |
2389 | sizeof(struct e1000_buffer)); | ||
2390 | memset(buffer_info, | ||
2391 | 0, | ||
2392 | sizeof(struct e1000_buffer)); | ||
2393 | } else { | 2723 | } else { |
2394 | e1000_unmap_and_free_tx_resource(adapter, | 2724 | if (cleaned) { |
2395 | buffer_info); | 2725 | memcpy(&adapter->previous_buffer_info, |
2726 | buffer_info, | ||
2727 | sizeof(struct e1000_buffer)); | ||
2728 | memset(buffer_info, 0, | ||
2729 | sizeof(struct e1000_buffer)); | ||
2730 | } else { | ||
2731 | e1000_unmap_and_free_tx_resource( | ||
2732 | adapter, buffer_info); | ||
2733 | } | ||
2396 | } | 2734 | } |
2735 | #endif | ||
2397 | 2736 | ||
2398 | tx_desc->buffer_addr = 0; | 2737 | tx_desc->buffer_addr = 0; |
2399 | tx_desc->lower.data = 0; | 2738 | tx_desc->lower.data = 0; |
2400 | tx_desc->upper.data = 0; | 2739 | tx_desc->upper.data = 0; |
2401 | 2740 | ||
2402 | cleaned = (i == eop); | ||
2403 | if(unlikely(++i == tx_ring->count)) i = 0; | 2741 | if(unlikely(++i == tx_ring->count)) i = 0; |
2404 | } | 2742 | } |
2405 | 2743 | ||
@@ -2416,57 +2754,107 @@ e1000_clean_tx_irq(struct e1000_adapter *adapter) | |||
2416 | netif_wake_queue(netdev); | 2754 | netif_wake_queue(netdev); |
2417 | 2755 | ||
2418 | spin_unlock(&adapter->tx_lock); | 2756 | spin_unlock(&adapter->tx_lock); |
2419 | |||
2420 | if(adapter->detect_tx_hung) { | 2757 | if(adapter->detect_tx_hung) { |
2421 | /* detect a transmit hang in hardware, this serializes the | 2758 | |
2759 | /* Detect a transmit hang in hardware, this serializes the | ||
2422 | * check with the clearing of time_stamp and movement of i */ | 2760 | * check with the clearing of time_stamp and movement of i */ |
2423 | adapter->detect_tx_hung = FALSE; | 2761 | adapter->detect_tx_hung = FALSE; |
2424 | if(tx_ring->buffer_info[i].dma && | 2762 | if (tx_ring->buffer_info[i].dma && |
2425 | time_after(jiffies, tx_ring->buffer_info[i].time_stamp + HZ) && | 2763 | time_after(jiffies, tx_ring->buffer_info[i].time_stamp + HZ) |
2426 | !(E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_TXOFF)) | 2764 | && !(E1000_READ_REG(&adapter->hw, STATUS) & |
2765 | E1000_STATUS_TXOFF)) { | ||
2766 | |||
2767 | /* detected Tx unit hang */ | ||
2768 | i = tx_ring->next_to_clean; | ||
2769 | eop = tx_ring->buffer_info[i].next_to_watch; | ||
2770 | eop_desc = E1000_TX_DESC(*tx_ring, eop); | ||
2771 | DPRINTK(TX_ERR, ERR, "Detected Tx Unit Hang\n" | ||
2772 | " TDH <%x>\n" | ||
2773 | " TDT <%x>\n" | ||
2774 | " next_to_use <%x>\n" | ||
2775 | " next_to_clean <%x>\n" | ||
2776 | "buffer_info[next_to_clean]\n" | ||
2777 | " dma <%llx>\n" | ||
2778 | " time_stamp <%lx>\n" | ||
2779 | " next_to_watch <%x>\n" | ||
2780 | " jiffies <%lx>\n" | ||
2781 | " next_to_watch.status <%x>\n", | ||
2782 | E1000_READ_REG(&adapter->hw, TDH), | ||
2783 | E1000_READ_REG(&adapter->hw, TDT), | ||
2784 | tx_ring->next_to_use, | ||
2785 | i, | ||
2786 | tx_ring->buffer_info[i].dma, | ||
2787 | tx_ring->buffer_info[i].time_stamp, | ||
2788 | eop, | ||
2789 | jiffies, | ||
2790 | eop_desc->upper.fields.status); | ||
2427 | netif_stop_queue(netdev); | 2791 | netif_stop_queue(netdev); |
2792 | } | ||
2428 | } | 2793 | } |
2794 | #ifdef NETIF_F_TSO | ||
2795 | |||
2796 | if( unlikely(!(eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) && | ||
2797 | time_after(jiffies, adapter->previous_buffer_info.time_stamp + HZ))) | ||
2798 | e1000_unmap_and_free_tx_resource( | ||
2799 | adapter, &adapter->previous_buffer_info); | ||
2429 | 2800 | ||
2801 | #endif | ||
2430 | return cleaned; | 2802 | return cleaned; |
2431 | } | 2803 | } |
2432 | 2804 | ||
2433 | /** | 2805 | /** |
2434 | * e1000_rx_checksum - Receive Checksum Offload for 82543 | 2806 | * e1000_rx_checksum - Receive Checksum Offload for 82543 |
2435 | * @adapter: board private structure | 2807 | * @adapter: board private structure |
2436 | * @rx_desc: receive descriptor | 2808 | * @status_err: receive descriptor status and error fields |
2437 | * @sk_buff: socket buffer with received data | 2809 | * @csum: receive descriptor csum field |
2810 | * @sk_buff: socket buffer with received data | ||
2438 | **/ | 2811 | **/ |
2439 | 2812 | ||
2440 | static inline void | 2813 | static inline void |
2441 | e1000_rx_checksum(struct e1000_adapter *adapter, | 2814 | e1000_rx_checksum(struct e1000_adapter *adapter, |
2442 | struct e1000_rx_desc *rx_desc, | 2815 | uint32_t status_err, uint32_t csum, |
2443 | struct sk_buff *skb) | 2816 | struct sk_buff *skb) |
2444 | { | 2817 | { |
2818 | uint16_t status = (uint16_t)status_err; | ||
2819 | uint8_t errors = (uint8_t)(status_err >> 24); | ||
2820 | skb->ip_summed = CHECKSUM_NONE; | ||
2821 | |||
2445 | /* 82543 or newer only */ | 2822 | /* 82543 or newer only */ |
2446 | if(unlikely((adapter->hw.mac_type < e1000_82543) || | 2823 | if(unlikely(adapter->hw.mac_type < e1000_82543)) return; |
2447 | /* Ignore Checksum bit is set */ | 2824 | /* Ignore Checksum bit is set */ |
2448 | (rx_desc->status & E1000_RXD_STAT_IXSM) || | 2825 | if(unlikely(status & E1000_RXD_STAT_IXSM)) return; |
2449 | /* TCP Checksum has not been calculated */ | 2826 | /* TCP/UDP checksum error bit is set */ |
2450 | (!(rx_desc->status & E1000_RXD_STAT_TCPCS)))) { | 2827 | if(unlikely(errors & E1000_RXD_ERR_TCPE)) { |
2451 | skb->ip_summed = CHECKSUM_NONE; | ||
2452 | return; | ||
2453 | } | ||
2454 | |||
2455 | /* At this point we know the hardware did the TCP checksum */ | ||
2456 | /* now look at the TCP checksum error bit */ | ||
2457 | if(rx_desc->errors & E1000_RXD_ERR_TCPE) { | ||
2458 | /* let the stack verify checksum errors */ | 2828 | /* let the stack verify checksum errors */ |
2459 | skb->ip_summed = CHECKSUM_NONE; | ||
2460 | adapter->hw_csum_err++; | 2829 | adapter->hw_csum_err++; |
2830 | return; | ||
2831 | } | ||
2832 | /* TCP/UDP Checksum has not been calculated */ | ||
2833 | if(adapter->hw.mac_type <= e1000_82547_rev_2) { | ||
2834 | if(!(status & E1000_RXD_STAT_TCPCS)) | ||
2835 | return; | ||
2461 | } else { | 2836 | } else { |
2837 | if(!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))) | ||
2838 | return; | ||
2839 | } | ||
2840 | /* It must be a TCP or UDP packet with a valid checksum */ | ||
2841 | if (likely(status & E1000_RXD_STAT_TCPCS)) { | ||
2462 | /* TCP checksum is good */ | 2842 | /* TCP checksum is good */ |
2463 | skb->ip_summed = CHECKSUM_UNNECESSARY; | 2843 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
2464 | adapter->hw_csum_good++; | 2844 | } else if (adapter->hw.mac_type > e1000_82547_rev_2) { |
2845 | /* IP fragment with UDP payload */ | ||
2846 | /* Hardware complements the payload checksum, so we undo it | ||
2847 | * and then put the value in host order for further stack use. | ||
2848 | */ | ||
2849 | csum = ntohl(csum ^ 0xFFFF); | ||
2850 | skb->csum = csum; | ||
2851 | skb->ip_summed = CHECKSUM_HW; | ||
2465 | } | 2852 | } |
2853 | adapter->hw_csum_good++; | ||
2466 | } | 2854 | } |
2467 | 2855 | ||
2468 | /** | 2856 | /** |
2469 | * e1000_clean_rx_irq - Send received data up the network stack | 2857 | * e1000_clean_rx_irq - Send received data up the network stack; legacy |
2470 | * @adapter: board private structure | 2858 | * @adapter: board private structure |
2471 | **/ | 2859 | **/ |
2472 | 2860 | ||
@@ -2513,7 +2901,7 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter) | |||
2513 | if(unlikely(!(rx_desc->status & E1000_RXD_STAT_EOP))) { | 2901 | if(unlikely(!(rx_desc->status & E1000_RXD_STAT_EOP))) { |
2514 | /* All receives must fit into a single buffer */ | 2902 | /* All receives must fit into a single buffer */ |
2515 | E1000_DBG("%s: Receive packet consumed multiple" | 2903 | E1000_DBG("%s: Receive packet consumed multiple" |
2516 | " buffers\n", netdev->name); | 2904 | " buffers\n", netdev->name); |
2517 | dev_kfree_skb_irq(skb); | 2905 | dev_kfree_skb_irq(skb); |
2518 | goto next_desc; | 2906 | goto next_desc; |
2519 | } | 2907 | } |
@@ -2539,15 +2927,17 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter) | |||
2539 | skb_put(skb, length - ETHERNET_FCS_SIZE); | 2927 | skb_put(skb, length - ETHERNET_FCS_SIZE); |
2540 | 2928 | ||
2541 | /* Receive Checksum Offload */ | 2929 | /* Receive Checksum Offload */ |
2542 | e1000_rx_checksum(adapter, rx_desc, skb); | 2930 | e1000_rx_checksum(adapter, |
2543 | 2931 | (uint32_t)(rx_desc->status) | | |
2932 | ((uint32_t)(rx_desc->errors) << 24), | ||
2933 | rx_desc->csum, skb); | ||
2544 | skb->protocol = eth_type_trans(skb, netdev); | 2934 | skb->protocol = eth_type_trans(skb, netdev); |
2545 | #ifdef CONFIG_E1000_NAPI | 2935 | #ifdef CONFIG_E1000_NAPI |
2546 | if(unlikely(adapter->vlgrp && | 2936 | if(unlikely(adapter->vlgrp && |
2547 | (rx_desc->status & E1000_RXD_STAT_VP))) { | 2937 | (rx_desc->status & E1000_RXD_STAT_VP))) { |
2548 | vlan_hwaccel_receive_skb(skb, adapter->vlgrp, | 2938 | vlan_hwaccel_receive_skb(skb, adapter->vlgrp, |
2549 | le16_to_cpu(rx_desc->special) & | 2939 | le16_to_cpu(rx_desc->special) & |
2550 | E1000_RXD_SPC_VLAN_MASK); | 2940 | E1000_RXD_SPC_VLAN_MASK); |
2551 | } else { | 2941 | } else { |
2552 | netif_receive_skb(skb); | 2942 | netif_receive_skb(skb); |
2553 | } | 2943 | } |
@@ -2570,16 +2960,142 @@ next_desc: | |||
2570 | 2960 | ||
2571 | rx_desc = E1000_RX_DESC(*rx_ring, i); | 2961 | rx_desc = E1000_RX_DESC(*rx_ring, i); |
2572 | } | 2962 | } |
2573 | |||
2574 | rx_ring->next_to_clean = i; | 2963 | rx_ring->next_to_clean = i; |
2964 | adapter->alloc_rx_buf(adapter); | ||
2965 | |||
2966 | return cleaned; | ||
2967 | } | ||
2968 | |||
2969 | /** | ||
2970 | * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split | ||
2971 | * @adapter: board private structure | ||
2972 | **/ | ||
2973 | |||
2974 | static boolean_t | ||
2975 | #ifdef CONFIG_E1000_NAPI | ||
2976 | e1000_clean_rx_irq_ps(struct e1000_adapter *adapter, int *work_done, | ||
2977 | int work_to_do) | ||
2978 | #else | ||
2979 | e1000_clean_rx_irq_ps(struct e1000_adapter *adapter) | ||
2980 | #endif | ||
2981 | { | ||
2982 | struct e1000_desc_ring *rx_ring = &adapter->rx_ring; | ||
2983 | union e1000_rx_desc_packet_split *rx_desc; | ||
2984 | struct net_device *netdev = adapter->netdev; | ||
2985 | struct pci_dev *pdev = adapter->pdev; | ||
2986 | struct e1000_buffer *buffer_info; | ||
2987 | struct e1000_ps_page *ps_page; | ||
2988 | struct e1000_ps_page_dma *ps_page_dma; | ||
2989 | struct sk_buff *skb; | ||
2990 | unsigned int i, j; | ||
2991 | uint32_t length, staterr; | ||
2992 | boolean_t cleaned = FALSE; | ||
2993 | |||
2994 | i = rx_ring->next_to_clean; | ||
2995 | rx_desc = E1000_RX_DESC_PS(*rx_ring, i); | ||
2996 | staterr = rx_desc->wb.middle.status_error; | ||
2997 | |||
2998 | while(staterr & E1000_RXD_STAT_DD) { | ||
2999 | buffer_info = &rx_ring->buffer_info[i]; | ||
3000 | ps_page = &rx_ring->ps_page[i]; | ||
3001 | ps_page_dma = &rx_ring->ps_page_dma[i]; | ||
3002 | #ifdef CONFIG_E1000_NAPI | ||
3003 | if(unlikely(*work_done >= work_to_do)) | ||
3004 | break; | ||
3005 | (*work_done)++; | ||
3006 | #endif | ||
3007 | cleaned = TRUE; | ||
3008 | pci_unmap_single(pdev, buffer_info->dma, | ||
3009 | buffer_info->length, | ||
3010 | PCI_DMA_FROMDEVICE); | ||
3011 | |||
3012 | skb = buffer_info->skb; | ||
3013 | |||
3014 | if(unlikely(!(staterr & E1000_RXD_STAT_EOP))) { | ||
3015 | E1000_DBG("%s: Packet Split buffers didn't pick up" | ||
3016 | " the full packet\n", netdev->name); | ||
3017 | dev_kfree_skb_irq(skb); | ||
3018 | goto next_desc; | ||
3019 | } | ||
3020 | |||
3021 | if(unlikely(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) { | ||
3022 | dev_kfree_skb_irq(skb); | ||
3023 | goto next_desc; | ||
3024 | } | ||
3025 | |||
3026 | length = le16_to_cpu(rx_desc->wb.middle.length0); | ||
3027 | |||
3028 | if(unlikely(!length)) { | ||
3029 | E1000_DBG("%s: Last part of the packet spanning" | ||
3030 | " multiple descriptors\n", netdev->name); | ||
3031 | dev_kfree_skb_irq(skb); | ||
3032 | goto next_desc; | ||
3033 | } | ||
3034 | |||
3035 | /* Good Receive */ | ||
3036 | skb_put(skb, length); | ||
3037 | |||
3038 | for(j = 0; j < PS_PAGE_BUFFERS; j++) { | ||
3039 | if(!(length = le16_to_cpu(rx_desc->wb.upper.length[j]))) | ||
3040 | break; | ||
3041 | |||
3042 | pci_unmap_page(pdev, ps_page_dma->ps_page_dma[j], | ||
3043 | PAGE_SIZE, PCI_DMA_FROMDEVICE); | ||
3044 | ps_page_dma->ps_page_dma[j] = 0; | ||
3045 | skb_shinfo(skb)->frags[j].page = | ||
3046 | ps_page->ps_page[j]; | ||
3047 | ps_page->ps_page[j] = NULL; | ||
3048 | skb_shinfo(skb)->frags[j].page_offset = 0; | ||
3049 | skb_shinfo(skb)->frags[j].size = length; | ||
3050 | skb_shinfo(skb)->nr_frags++; | ||
3051 | skb->len += length; | ||
3052 | skb->data_len += length; | ||
3053 | } | ||
2575 | 3054 | ||
2576 | e1000_alloc_rx_buffers(adapter); | 3055 | e1000_rx_checksum(adapter, staterr, |
3056 | rx_desc->wb.lower.hi_dword.csum_ip.csum, skb); | ||
3057 | skb->protocol = eth_type_trans(skb, netdev); | ||
3058 | |||
3059 | #ifdef HAVE_RX_ZERO_COPY | ||
3060 | if(likely(rx_desc->wb.upper.header_status & | ||
3061 | E1000_RXDPS_HDRSTAT_HDRSP)) | ||
3062 | skb_shinfo(skb)->zero_copy = TRUE; | ||
3063 | #endif | ||
3064 | #ifdef CONFIG_E1000_NAPI | ||
3065 | if(unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) { | ||
3066 | vlan_hwaccel_receive_skb(skb, adapter->vlgrp, | ||
3067 | le16_to_cpu(rx_desc->wb.middle.vlan & | ||
3068 | E1000_RXD_SPC_VLAN_MASK)); | ||
3069 | } else { | ||
3070 | netif_receive_skb(skb); | ||
3071 | } | ||
3072 | #else /* CONFIG_E1000_NAPI */ | ||
3073 | if(unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) { | ||
3074 | vlan_hwaccel_rx(skb, adapter->vlgrp, | ||
3075 | le16_to_cpu(rx_desc->wb.middle.vlan & | ||
3076 | E1000_RXD_SPC_VLAN_MASK)); | ||
3077 | } else { | ||
3078 | netif_rx(skb); | ||
3079 | } | ||
3080 | #endif /* CONFIG_E1000_NAPI */ | ||
3081 | netdev->last_rx = jiffies; | ||
3082 | |||
3083 | next_desc: | ||
3084 | rx_desc->wb.middle.status_error &= ~0xFF; | ||
3085 | buffer_info->skb = NULL; | ||
3086 | if(unlikely(++i == rx_ring->count)) i = 0; | ||
3087 | |||
3088 | rx_desc = E1000_RX_DESC_PS(*rx_ring, i); | ||
3089 | staterr = rx_desc->wb.middle.status_error; | ||
3090 | } | ||
3091 | rx_ring->next_to_clean = i; | ||
3092 | adapter->alloc_rx_buf(adapter); | ||
2577 | 3093 | ||
2578 | return cleaned; | 3094 | return cleaned; |
2579 | } | 3095 | } |
2580 | 3096 | ||
2581 | /** | 3097 | /** |
2582 | * e1000_alloc_rx_buffers - Replace used receive buffers | 3098 | * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended |
2583 | * @adapter: address of board private structure | 3099 | * @adapter: address of board private structure |
2584 | **/ | 3100 | **/ |
2585 | 3101 | ||
@@ -2592,43 +3108,43 @@ e1000_alloc_rx_buffers(struct e1000_adapter *adapter) | |||
2592 | struct e1000_rx_desc *rx_desc; | 3108 | struct e1000_rx_desc *rx_desc; |
2593 | struct e1000_buffer *buffer_info; | 3109 | struct e1000_buffer *buffer_info; |
2594 | struct sk_buff *skb; | 3110 | struct sk_buff *skb; |
2595 | unsigned int i, bufsz; | 3111 | unsigned int i; |
3112 | unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN; | ||
2596 | 3113 | ||
2597 | i = rx_ring->next_to_use; | 3114 | i = rx_ring->next_to_use; |
2598 | buffer_info = &rx_ring->buffer_info[i]; | 3115 | buffer_info = &rx_ring->buffer_info[i]; |
2599 | 3116 | ||
2600 | while(!buffer_info->skb) { | 3117 | while(!buffer_info->skb) { |
2601 | bufsz = adapter->rx_buffer_len + NET_IP_ALIGN; | ||
2602 | |||
2603 | skb = dev_alloc_skb(bufsz); | 3118 | skb = dev_alloc_skb(bufsz); |
3119 | |||
2604 | if(unlikely(!skb)) { | 3120 | if(unlikely(!skb)) { |
2605 | /* Better luck next round */ | 3121 | /* Better luck next round */ |
2606 | break; | 3122 | break; |
2607 | } | 3123 | } |
2608 | 3124 | ||
2609 | /* fix for errata 23, cant cross 64kB boundary */ | 3125 | /* Fix for errata 23, can't cross 64kB boundary */ |
2610 | if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) { | 3126 | if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) { |
2611 | struct sk_buff *oldskb = skb; | 3127 | struct sk_buff *oldskb = skb; |
2612 | DPRINTK(RX_ERR,ERR, | 3128 | DPRINTK(RX_ERR, ERR, "skb align check failed: %u bytes " |
2613 | "skb align check failed: %u bytes at %p\n", | 3129 | "at %p\n", bufsz, skb->data); |
2614 | bufsz, skb->data); | 3130 | /* Try again, without freeing the previous */ |
2615 | /* try again, without freeing the previous */ | ||
2616 | skb = dev_alloc_skb(bufsz); | 3131 | skb = dev_alloc_skb(bufsz); |
3132 | /* Failed allocation, critical failure */ | ||
2617 | if (!skb) { | 3133 | if (!skb) { |
2618 | dev_kfree_skb(oldskb); | 3134 | dev_kfree_skb(oldskb); |
2619 | break; | 3135 | break; |
2620 | } | 3136 | } |
3137 | |||
2621 | if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) { | 3138 | if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) { |
2622 | /* give up */ | 3139 | /* give up */ |
2623 | dev_kfree_skb(skb); | 3140 | dev_kfree_skb(skb); |
2624 | dev_kfree_skb(oldskb); | 3141 | dev_kfree_skb(oldskb); |
2625 | break; /* while !buffer_info->skb */ | 3142 | break; /* while !buffer_info->skb */ |
2626 | } else { | 3143 | } else { |
2627 | /* move on with the new one */ | 3144 | /* Use new allocation */ |
2628 | dev_kfree_skb(oldskb); | 3145 | dev_kfree_skb(oldskb); |
2629 | } | 3146 | } |
2630 | } | 3147 | } |
2631 | |||
2632 | /* Make buffer alignment 2 beyond a 16 byte boundary | 3148 | /* Make buffer alignment 2 beyond a 16 byte boundary |
2633 | * this will result in a 16 byte aligned IP header after | 3149 | * this will result in a 16 byte aligned IP header after |
2634 | * the 14 byte MAC header is removed | 3150 | * the 14 byte MAC header is removed |
@@ -2644,25 +3160,23 @@ e1000_alloc_rx_buffers(struct e1000_adapter *adapter) | |||
2644 | adapter->rx_buffer_len, | 3160 | adapter->rx_buffer_len, |
2645 | PCI_DMA_FROMDEVICE); | 3161 | PCI_DMA_FROMDEVICE); |
2646 | 3162 | ||
2647 | /* fix for errata 23, cant cross 64kB boundary */ | 3163 | /* Fix for errata 23, can't cross 64kB boundary */ |
2648 | if(!e1000_check_64k_bound(adapter, | 3164 | if (!e1000_check_64k_bound(adapter, |
2649 | (void *)(unsigned long)buffer_info->dma, | 3165 | (void *)(unsigned long)buffer_info->dma, |
2650 | adapter->rx_buffer_len)) { | 3166 | adapter->rx_buffer_len)) { |
2651 | DPRINTK(RX_ERR,ERR, | 3167 | DPRINTK(RX_ERR, ERR, |
2652 | "dma align check failed: %u bytes at %ld\n", | 3168 | "dma align check failed: %u bytes at %p\n", |
2653 | adapter->rx_buffer_len, (unsigned long)buffer_info->dma); | 3169 | adapter->rx_buffer_len, |
2654 | 3170 | (void *)(unsigned long)buffer_info->dma); | |
2655 | dev_kfree_skb(skb); | 3171 | dev_kfree_skb(skb); |
2656 | buffer_info->skb = NULL; | 3172 | buffer_info->skb = NULL; |
2657 | 3173 | ||
2658 | pci_unmap_single(pdev, | 3174 | pci_unmap_single(pdev, buffer_info->dma, |
2659 | buffer_info->dma, | ||
2660 | adapter->rx_buffer_len, | 3175 | adapter->rx_buffer_len, |
2661 | PCI_DMA_FROMDEVICE); | 3176 | PCI_DMA_FROMDEVICE); |
2662 | 3177 | ||
2663 | break; /* while !buffer_info->skb */ | 3178 | break; /* while !buffer_info->skb */ |
2664 | } | 3179 | } |
2665 | |||
2666 | rx_desc = E1000_RX_DESC(*rx_ring, i); | 3180 | rx_desc = E1000_RX_DESC(*rx_ring, i); |
2667 | rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); | 3181 | rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); |
2668 | 3182 | ||
@@ -2672,7 +3186,6 @@ e1000_alloc_rx_buffers(struct e1000_adapter *adapter) | |||
2672 | * applicable for weak-ordered memory model archs, | 3186 | * applicable for weak-ordered memory model archs, |
2673 | * such as IA-64). */ | 3187 | * such as IA-64). */ |
2674 | wmb(); | 3188 | wmb(); |
2675 | |||
2676 | E1000_WRITE_REG(&adapter->hw, RDT, i); | 3189 | E1000_WRITE_REG(&adapter->hw, RDT, i); |
2677 | } | 3190 | } |
2678 | 3191 | ||
@@ -2684,6 +3197,95 @@ e1000_alloc_rx_buffers(struct e1000_adapter *adapter) | |||
2684 | } | 3197 | } |
2685 | 3198 | ||
2686 | /** | 3199 | /** |
3200 | * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split | ||
3201 | * @adapter: address of board private structure | ||
3202 | **/ | ||
3203 | |||
3204 | static void | ||
3205 | e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter) | ||
3206 | { | ||
3207 | struct e1000_desc_ring *rx_ring = &adapter->rx_ring; | ||
3208 | struct net_device *netdev = adapter->netdev; | ||
3209 | struct pci_dev *pdev = adapter->pdev; | ||
3210 | union e1000_rx_desc_packet_split *rx_desc; | ||
3211 | struct e1000_buffer *buffer_info; | ||
3212 | struct e1000_ps_page *ps_page; | ||
3213 | struct e1000_ps_page_dma *ps_page_dma; | ||
3214 | struct sk_buff *skb; | ||
3215 | unsigned int i, j; | ||
3216 | |||
3217 | i = rx_ring->next_to_use; | ||
3218 | buffer_info = &rx_ring->buffer_info[i]; | ||
3219 | ps_page = &rx_ring->ps_page[i]; | ||
3220 | ps_page_dma = &rx_ring->ps_page_dma[i]; | ||
3221 | |||
3222 | while(!buffer_info->skb) { | ||
3223 | rx_desc = E1000_RX_DESC_PS(*rx_ring, i); | ||
3224 | |||
3225 | for(j = 0; j < PS_PAGE_BUFFERS; j++) { | ||
3226 | if(unlikely(!ps_page->ps_page[j])) { | ||
3227 | ps_page->ps_page[j] = | ||
3228 | alloc_page(GFP_ATOMIC); | ||
3229 | if(unlikely(!ps_page->ps_page[j])) | ||
3230 | goto no_buffers; | ||
3231 | ps_page_dma->ps_page_dma[j] = | ||
3232 | pci_map_page(pdev, | ||
3233 | ps_page->ps_page[j], | ||
3234 | 0, PAGE_SIZE, | ||
3235 | PCI_DMA_FROMDEVICE); | ||
3236 | } | ||
3237 | /* Refresh the desc even if buffer_addrs didn't | ||
3238 | * change because each write-back erases this info. | ||
3239 | */ | ||
3240 | rx_desc->read.buffer_addr[j+1] = | ||
3241 | cpu_to_le64(ps_page_dma->ps_page_dma[j]); | ||
3242 | } | ||
3243 | |||
3244 | skb = dev_alloc_skb(adapter->rx_ps_bsize0 + NET_IP_ALIGN); | ||
3245 | |||
3246 | if(unlikely(!skb)) | ||
3247 | break; | ||
3248 | |||
3249 | /* Make buffer alignment 2 beyond a 16 byte boundary | ||
3250 | * this will result in a 16 byte aligned IP header after | ||
3251 | * the 14 byte MAC header is removed | ||
3252 | */ | ||
3253 | skb_reserve(skb, NET_IP_ALIGN); | ||
3254 | |||
3255 | skb->dev = netdev; | ||
3256 | |||
3257 | buffer_info->skb = skb; | ||
3258 | buffer_info->length = adapter->rx_ps_bsize0; | ||
3259 | buffer_info->dma = pci_map_single(pdev, skb->data, | ||
3260 | adapter->rx_ps_bsize0, | ||
3261 | PCI_DMA_FROMDEVICE); | ||
3262 | |||
3263 | rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma); | ||
3264 | |||
3265 | if(unlikely((i & ~(E1000_RX_BUFFER_WRITE - 1)) == i)) { | ||
3266 | /* Force memory writes to complete before letting h/w | ||
3267 | * know there are new descriptors to fetch. (Only | ||
3268 | * applicable for weak-ordered memory model archs, | ||
3269 | * such as IA-64). */ | ||
3270 | wmb(); | ||
3271 | /* Hardware increments by 16 bytes, but packet split | ||
3272 | * descriptors are 32 bytes...so we increment tail | ||
3273 | * twice as much. | ||
3274 | */ | ||
3275 | E1000_WRITE_REG(&adapter->hw, RDT, i<<1); | ||
3276 | } | ||
3277 | |||
3278 | if(unlikely(++i == rx_ring->count)) i = 0; | ||
3279 | buffer_info = &rx_ring->buffer_info[i]; | ||
3280 | ps_page = &rx_ring->ps_page[i]; | ||
3281 | ps_page_dma = &rx_ring->ps_page_dma[i]; | ||
3282 | } | ||
3283 | |||
3284 | no_buffers: | ||
3285 | rx_ring->next_to_use = i; | ||
3286 | } | ||
3287 | |||
3288 | /** | ||
2687 | * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers. | 3289 | * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers. |
2688 | * @adapter: | 3290 | * @adapter: |
2689 | **/ | 3291 | **/ |
@@ -2856,9 +3458,10 @@ void | |||
2856 | e1000_pci_set_mwi(struct e1000_hw *hw) | 3458 | e1000_pci_set_mwi(struct e1000_hw *hw) |
2857 | { | 3459 | { |
2858 | struct e1000_adapter *adapter = hw->back; | 3460 | struct e1000_adapter *adapter = hw->back; |
3461 | int ret_val = pci_set_mwi(adapter->pdev); | ||
2859 | 3462 | ||
2860 | int ret; | 3463 | if(ret_val) |
2861 | ret = pci_set_mwi(adapter->pdev); | 3464 | DPRINTK(PROBE, ERR, "Error in setting MWI\n"); |
2862 | } | 3465 | } |
2863 | 3466 | ||
2864 | void | 3467 | void |
@@ -2917,6 +3520,7 @@ e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp) | |||
2917 | rctl |= E1000_RCTL_VFE; | 3520 | rctl |= E1000_RCTL_VFE; |
2918 | rctl &= ~E1000_RCTL_CFIEN; | 3521 | rctl &= ~E1000_RCTL_CFIEN; |
2919 | E1000_WRITE_REG(&adapter->hw, RCTL, rctl); | 3522 | E1000_WRITE_REG(&adapter->hw, RCTL, rctl); |
3523 | e1000_update_mng_vlan(adapter); | ||
2920 | } else { | 3524 | } else { |
2921 | /* disable VLAN tag insert/strip */ | 3525 | /* disable VLAN tag insert/strip */ |
2922 | ctrl = E1000_READ_REG(&adapter->hw, CTRL); | 3526 | ctrl = E1000_READ_REG(&adapter->hw, CTRL); |
@@ -2927,6 +3531,10 @@ e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp) | |||
2927 | rctl = E1000_READ_REG(&adapter->hw, RCTL); | 3531 | rctl = E1000_READ_REG(&adapter->hw, RCTL); |
2928 | rctl &= ~E1000_RCTL_VFE; | 3532 | rctl &= ~E1000_RCTL_VFE; |
2929 | E1000_WRITE_REG(&adapter->hw, RCTL, rctl); | 3533 | E1000_WRITE_REG(&adapter->hw, RCTL, rctl); |
3534 | if(adapter->mng_vlan_id != (uint16_t)E1000_MNG_VLAN_NONE) { | ||
3535 | e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); | ||
3536 | adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; | ||
3537 | } | ||
2930 | } | 3538 | } |
2931 | 3539 | ||
2932 | e1000_irq_enable(adapter); | 3540 | e1000_irq_enable(adapter); |
@@ -2937,7 +3545,10 @@ e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid) | |||
2937 | { | 3545 | { |
2938 | struct e1000_adapter *adapter = netdev->priv; | 3546 | struct e1000_adapter *adapter = netdev->priv; |
2939 | uint32_t vfta, index; | 3547 | uint32_t vfta, index; |
2940 | 3548 | if((adapter->hw.mng_cookie.status & | |
3549 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) && | ||
3550 | (vid == adapter->mng_vlan_id)) | ||
3551 | return; | ||
2941 | /* add VID to filter table */ | 3552 | /* add VID to filter table */ |
2942 | index = (vid >> 5) & 0x7F; | 3553 | index = (vid >> 5) & 0x7F; |
2943 | vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index); | 3554 | vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index); |
@@ -2958,6 +3569,10 @@ e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid) | |||
2958 | 3569 | ||
2959 | e1000_irq_enable(adapter); | 3570 | e1000_irq_enable(adapter); |
2960 | 3571 | ||
3572 | if((adapter->hw.mng_cookie.status & | ||
3573 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) && | ||
3574 | (vid == adapter->mng_vlan_id)) | ||
3575 | return; | ||
2961 | /* remove VID from filter table */ | 3576 | /* remove VID from filter table */ |
2962 | index = (vid >> 5) & 0x7F; | 3577 | index = (vid >> 5) & 0x7F; |
2963 | vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index); | 3578 | vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index); |
@@ -3004,8 +3619,7 @@ e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx) | |||
3004 | break; | 3619 | break; |
3005 | case SPEED_1000 + DUPLEX_HALF: /* not supported */ | 3620 | case SPEED_1000 + DUPLEX_HALF: /* not supported */ |
3006 | default: | 3621 | default: |
3007 | DPRINTK(PROBE, ERR, | 3622 | DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n"); |
3008 | "Unsupported Speed/Duplexity configuration\n"); | ||
3009 | return -EINVAL; | 3623 | return -EINVAL; |
3010 | } | 3624 | } |
3011 | return 0; | 3625 | return 0; |
@@ -3033,7 +3647,7 @@ e1000_suspend(struct pci_dev *pdev, uint32_t state) | |||
3033 | { | 3647 | { |
3034 | struct net_device *netdev = pci_get_drvdata(pdev); | 3648 | struct net_device *netdev = pci_get_drvdata(pdev); |
3035 | struct e1000_adapter *adapter = netdev->priv; | 3649 | struct e1000_adapter *adapter = netdev->priv; |
3036 | uint32_t ctrl, ctrl_ext, rctl, manc, status; | 3650 | uint32_t ctrl, ctrl_ext, rctl, manc, status, swsm; |
3037 | uint32_t wufc = adapter->wol; | 3651 | uint32_t wufc = adapter->wol; |
3038 | 3652 | ||
3039 | netif_device_detach(netdev); | 3653 | netif_device_detach(netdev); |
@@ -3075,6 +3689,9 @@ e1000_suspend(struct pci_dev *pdev, uint32_t state) | |||
3075 | E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext); | 3689 | E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext); |
3076 | } | 3690 | } |
3077 | 3691 | ||
3692 | /* Allow time for pending master requests to run */ | ||
3693 | e1000_disable_pciex_master(&adapter->hw); | ||
3694 | |||
3078 | E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN); | 3695 | E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN); |
3079 | E1000_WRITE_REG(&adapter->hw, WUFC, wufc); | 3696 | E1000_WRITE_REG(&adapter->hw, WUFC, wufc); |
3080 | pci_enable_wake(pdev, 3, 1); | 3697 | pci_enable_wake(pdev, 3, 1); |
@@ -3099,6 +3716,16 @@ e1000_suspend(struct pci_dev *pdev, uint32_t state) | |||
3099 | } | 3716 | } |
3100 | } | 3717 | } |
3101 | 3718 | ||
3719 | switch(adapter->hw.mac_type) { | ||
3720 | case e1000_82573: | ||
3721 | swsm = E1000_READ_REG(&adapter->hw, SWSM); | ||
3722 | E1000_WRITE_REG(&adapter->hw, SWSM, | ||
3723 | swsm & ~E1000_SWSM_DRV_LOAD); | ||
3724 | break; | ||
3725 | default: | ||
3726 | break; | ||
3727 | } | ||
3728 | |||
3102 | pci_disable_device(pdev); | 3729 | pci_disable_device(pdev); |
3103 | 3730 | ||
3104 | state = (state > 0) ? 3 : 0; | 3731 | state = (state > 0) ? 3 : 0; |
@@ -3113,13 +3740,12 @@ e1000_resume(struct pci_dev *pdev) | |||
3113 | { | 3740 | { |
3114 | struct net_device *netdev = pci_get_drvdata(pdev); | 3741 | struct net_device *netdev = pci_get_drvdata(pdev); |
3115 | struct e1000_adapter *adapter = netdev->priv; | 3742 | struct e1000_adapter *adapter = netdev->priv; |
3116 | uint32_t manc, ret; | 3743 | uint32_t manc, ret, swsm; |
3117 | 3744 | ||
3118 | pci_set_power_state(pdev, 0); | 3745 | pci_set_power_state(pdev, 0); |
3119 | pci_restore_state(pdev); | 3746 | pci_restore_state(pdev); |
3120 | ret = pci_enable_device(pdev); | 3747 | ret = pci_enable_device(pdev); |
3121 | if (pdev->is_busmaster) | 3748 | pci_set_master(pdev); |
3122 | pci_set_master(pdev); | ||
3123 | 3749 | ||
3124 | pci_enable_wake(pdev, 3, 0); | 3750 | pci_enable_wake(pdev, 3, 0); |
3125 | pci_enable_wake(pdev, 4, 0); /* 4 == D3 cold */ | 3751 | pci_enable_wake(pdev, 4, 0); /* 4 == D3 cold */ |
@@ -3139,10 +3765,19 @@ e1000_resume(struct pci_dev *pdev) | |||
3139 | E1000_WRITE_REG(&adapter->hw, MANC, manc); | 3765 | E1000_WRITE_REG(&adapter->hw, MANC, manc); |
3140 | } | 3766 | } |
3141 | 3767 | ||
3768 | switch(adapter->hw.mac_type) { | ||
3769 | case e1000_82573: | ||
3770 | swsm = E1000_READ_REG(&adapter->hw, SWSM); | ||
3771 | E1000_WRITE_REG(&adapter->hw, SWSM, | ||
3772 | swsm | E1000_SWSM_DRV_LOAD); | ||
3773 | break; | ||
3774 | default: | ||
3775 | break; | ||
3776 | } | ||
3777 | |||
3142 | return 0; | 3778 | return 0; |
3143 | } | 3779 | } |
3144 | #endif | 3780 | #endif |
3145 | |||
3146 | #ifdef CONFIG_NET_POLL_CONTROLLER | 3781 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3147 | /* | 3782 | /* |
3148 | * Polling 'interrupt' - used by things like netconsole to send skbs | 3783 | * Polling 'interrupt' - used by things like netconsole to send skbs |
@@ -3150,7 +3785,7 @@ e1000_resume(struct pci_dev *pdev) | |||
3150 | * the interrupt routine is executing. | 3785 | * the interrupt routine is executing. |
3151 | */ | 3786 | */ |
3152 | static void | 3787 | static void |
3153 | e1000_netpoll (struct net_device *netdev) | 3788 | e1000_netpoll(struct net_device *netdev) |
3154 | { | 3789 | { |
3155 | struct e1000_adapter *adapter = netdev->priv; | 3790 | struct e1000_adapter *adapter = netdev->priv; |
3156 | disable_irq(adapter->pdev->irq); | 3791 | disable_irq(adapter->pdev->irq); |
diff --git a/drivers/net/e1000/e1000_osdep.h b/drivers/net/e1000/e1000_osdep.h index 970c656a517c..aac64de61437 100644 --- a/drivers/net/e1000/e1000_osdep.h +++ b/drivers/net/e1000/e1000_osdep.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /******************************************************************************* | 1 | /******************************************************************************* |
2 | 2 | ||
3 | 3 | ||
4 | Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved. | 4 | Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. |
5 | 5 | ||
6 | This program is free software; you can redistribute it and/or modify it | 6 | This program is free software; you can redistribute it and/or modify it |
7 | under the terms of the GNU General Public License as published by the Free | 7 | under the terms of the GNU General Public License as published by the Free |
@@ -42,7 +42,12 @@ | |||
42 | #include <linux/sched.h> | 42 | #include <linux/sched.h> |
43 | 43 | ||
44 | #ifndef msec_delay | 44 | #ifndef msec_delay |
45 | #define msec_delay(x) msleep(x) | 45 | #define msec_delay(x) do { if(in_interrupt()) { \ |
46 | /* Don't mdelay in interrupt context! */ \ | ||
47 | BUG(); \ | ||
48 | } else { \ | ||
49 | msleep(x); \ | ||
50 | } } while(0) | ||
46 | 51 | ||
47 | /* Some workarounds require millisecond delays and are run during interrupt | 52 | /* Some workarounds require millisecond delays and are run during interrupt |
48 | * context. Most notably, when establishing link, the phy may need tweaking | 53 | * context. Most notably, when establishing link, the phy may need tweaking |
@@ -96,6 +101,29 @@ typedef enum { | |||
96 | (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ | 101 | (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ |
97 | ((offset) << 2))) | 102 | ((offset) << 2))) |
98 | 103 | ||
104 | #define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY | ||
105 | #define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY | ||
106 | |||
107 | #define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \ | ||
108 | writew((value), ((a)->hw_addr + \ | ||
109 | (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ | ||
110 | ((offset) << 1)))) | ||
111 | |||
112 | #define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \ | ||
113 | readw((a)->hw_addr + \ | ||
114 | (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ | ||
115 | ((offset) << 1))) | ||
116 | |||
117 | #define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \ | ||
118 | writeb((value), ((a)->hw_addr + \ | ||
119 | (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ | ||
120 | (offset)))) | ||
121 | |||
122 | #define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \ | ||
123 | readb((a)->hw_addr + \ | ||
124 | (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \ | ||
125 | (offset))) | ||
126 | |||
99 | #define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS) | 127 | #define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS) |
100 | 128 | ||
101 | #endif /* _E1000_OSDEP_H_ */ | 129 | #endif /* _E1000_OSDEP_H_ */ |
diff --git a/drivers/net/e1000/e1000_param.c b/drivers/net/e1000/e1000_param.c index e914d09fe6f9..676247f9f1cc 100644 --- a/drivers/net/e1000/e1000_param.c +++ b/drivers/net/e1000/e1000_param.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /******************************************************************************* | 1 | /******************************************************************************* |
2 | 2 | ||
3 | 3 | ||
4 | Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved. | 4 | Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. |
5 | 5 | ||
6 | This program is free software; you can redistribute it and/or modify it | 6 | This program is free software; you can redistribute it and/or modify it |
7 | under the terms of the GNU General Public License as published by the Free | 7 | under the terms of the GNU General Public License as published by the Free |
@@ -478,7 +478,6 @@ e1000_check_options(struct e1000_adapter *adapter) | |||
478 | DPRINTK(PROBE, INFO, "%s set to dynamic mode\n", | 478 | DPRINTK(PROBE, INFO, "%s set to dynamic mode\n", |
479 | opt.name); | 479 | opt.name); |
480 | break; | 480 | break; |
481 | case -1: | ||
482 | default: | 481 | default: |
483 | e1000_validate_option(&adapter->itr, &opt, | 482 | e1000_validate_option(&adapter->itr, &opt, |
484 | adapter); | 483 | adapter); |
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c index cda48c5d72a9..4ebcd052e150 100644 --- a/drivers/net/forcedeth.c +++ b/drivers/net/forcedeth.c | |||
@@ -81,6 +81,7 @@ | |||
81 | * cause DMA to kfree'd memory. | 81 | * cause DMA to kfree'd memory. |
82 | * 0.31: 14 Nov 2004: ethtool support for getting/setting link | 82 | * 0.31: 14 Nov 2004: ethtool support for getting/setting link |
83 | * capabilities. | 83 | * capabilities. |
84 | * 0.32: 16 Apr 2005: RX_ERROR4 handling added. | ||
84 | * | 85 | * |
85 | * Known bugs: | 86 | * Known bugs: |
86 | * We suspect that on some hardware no TX done interrupts are generated. | 87 | * We suspect that on some hardware no TX done interrupts are generated. |
@@ -92,7 +93,7 @@ | |||
92 | * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few | 93 | * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few |
93 | * superfluous timer interrupts from the nic. | 94 | * superfluous timer interrupts from the nic. |
94 | */ | 95 | */ |
95 | #define FORCEDETH_VERSION "0.31" | 96 | #define FORCEDETH_VERSION "0.32" |
96 | #define DRV_NAME "forcedeth" | 97 | #define DRV_NAME "forcedeth" |
97 | 98 | ||
98 | #include <linux/module.h> | 99 | #include <linux/module.h> |
@@ -109,6 +110,7 @@ | |||
109 | #include <linux/mii.h> | 110 | #include <linux/mii.h> |
110 | #include <linux/random.h> | 111 | #include <linux/random.h> |
111 | #include <linux/init.h> | 112 | #include <linux/init.h> |
113 | #include <linux/if_vlan.h> | ||
112 | 114 | ||
113 | #include <asm/irq.h> | 115 | #include <asm/irq.h> |
114 | #include <asm/io.h> | 116 | #include <asm/io.h> |
@@ -1013,6 +1015,59 @@ static void nv_tx_timeout(struct net_device *dev) | |||
1013 | spin_unlock_irq(&np->lock); | 1015 | spin_unlock_irq(&np->lock); |
1014 | } | 1016 | } |
1015 | 1017 | ||
1018 | /* | ||
1019 | * Called when the nic notices a mismatch between the actual data len on the | ||
1020 | * wire and the len indicated in the 802 header | ||
1021 | */ | ||
1022 | static int nv_getlen(struct net_device *dev, void *packet, int datalen) | ||
1023 | { | ||
1024 | int hdrlen; /* length of the 802 header */ | ||
1025 | int protolen; /* length as stored in the proto field */ | ||
1026 | |||
1027 | /* 1) calculate len according to header */ | ||
1028 | if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) { | ||
1029 | protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto ); | ||
1030 | hdrlen = VLAN_HLEN; | ||
1031 | } else { | ||
1032 | protolen = ntohs( ((struct ethhdr *)packet)->h_proto); | ||
1033 | hdrlen = ETH_HLEN; | ||
1034 | } | ||
1035 | dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n", | ||
1036 | dev->name, datalen, protolen, hdrlen); | ||
1037 | if (protolen > ETH_DATA_LEN) | ||
1038 | return datalen; /* Value in proto field not a len, no checks possible */ | ||
1039 | |||
1040 | protolen += hdrlen; | ||
1041 | /* consistency checks: */ | ||
1042 | if (datalen > ETH_ZLEN) { | ||
1043 | if (datalen >= protolen) { | ||
1044 | /* more data on wire than in 802 header, trim of | ||
1045 | * additional data. | ||
1046 | */ | ||
1047 | dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n", | ||
1048 | dev->name, protolen); | ||
1049 | return protolen; | ||
1050 | } else { | ||
1051 | /* less data on wire than mentioned in header. | ||
1052 | * Discard the packet. | ||
1053 | */ | ||
1054 | dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n", | ||
1055 | dev->name); | ||
1056 | return -1; | ||
1057 | } | ||
1058 | } else { | ||
1059 | /* short packet. Accept only if 802 values are also short */ | ||
1060 | if (protolen > ETH_ZLEN) { | ||
1061 | dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n", | ||
1062 | dev->name); | ||
1063 | return -1; | ||
1064 | } | ||
1065 | dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n", | ||
1066 | dev->name, datalen); | ||
1067 | return datalen; | ||
1068 | } | ||
1069 | } | ||
1070 | |||
1016 | static void nv_rx_process(struct net_device *dev) | 1071 | static void nv_rx_process(struct net_device *dev) |
1017 | { | 1072 | { |
1018 | struct fe_priv *np = get_nvpriv(dev); | 1073 | struct fe_priv *np = get_nvpriv(dev); |
@@ -1064,7 +1119,7 @@ static void nv_rx_process(struct net_device *dev) | |||
1064 | np->stats.rx_errors++; | 1119 | np->stats.rx_errors++; |
1065 | goto next_pkt; | 1120 | goto next_pkt; |
1066 | } | 1121 | } |
1067 | if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4)) { | 1122 | if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) { |
1068 | np->stats.rx_errors++; | 1123 | np->stats.rx_errors++; |
1069 | goto next_pkt; | 1124 | goto next_pkt; |
1070 | } | 1125 | } |
@@ -1078,22 +1133,24 @@ static void nv_rx_process(struct net_device *dev) | |||
1078 | np->stats.rx_errors++; | 1133 | np->stats.rx_errors++; |
1079 | goto next_pkt; | 1134 | goto next_pkt; |
1080 | } | 1135 | } |
1081 | if (Flags & NV_RX_ERROR) { | 1136 | if (Flags & NV_RX_ERROR4) { |
1082 | /* framing errors are soft errors, the rest is fatal. */ | 1137 | len = nv_getlen(dev, np->rx_skbuff[i]->data, len); |
1083 | if (Flags & NV_RX_FRAMINGERR) { | 1138 | if (len < 0) { |
1084 | if (Flags & NV_RX_SUBSTRACT1) { | ||
1085 | len--; | ||
1086 | } | ||
1087 | } else { | ||
1088 | np->stats.rx_errors++; | 1139 | np->stats.rx_errors++; |
1089 | goto next_pkt; | 1140 | goto next_pkt; |
1090 | } | 1141 | } |
1091 | } | 1142 | } |
1143 | /* framing errors are soft errors. */ | ||
1144 | if (Flags & NV_RX_FRAMINGERR) { | ||
1145 | if (Flags & NV_RX_SUBSTRACT1) { | ||
1146 | len--; | ||
1147 | } | ||
1148 | } | ||
1092 | } else { | 1149 | } else { |
1093 | if (!(Flags & NV_RX2_DESCRIPTORVALID)) | 1150 | if (!(Flags & NV_RX2_DESCRIPTORVALID)) |
1094 | goto next_pkt; | 1151 | goto next_pkt; |
1095 | 1152 | ||
1096 | if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4)) { | 1153 | if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) { |
1097 | np->stats.rx_errors++; | 1154 | np->stats.rx_errors++; |
1098 | goto next_pkt; | 1155 | goto next_pkt; |
1099 | } | 1156 | } |
@@ -1107,17 +1164,19 @@ static void nv_rx_process(struct net_device *dev) | |||
1107 | np->stats.rx_errors++; | 1164 | np->stats.rx_errors++; |
1108 | goto next_pkt; | 1165 | goto next_pkt; |
1109 | } | 1166 | } |
1110 | if (Flags & NV_RX2_ERROR) { | 1167 | if (Flags & NV_RX2_ERROR4) { |
1111 | /* framing errors are soft errors, the rest is fatal. */ | 1168 | len = nv_getlen(dev, np->rx_skbuff[i]->data, len); |
1112 | if (Flags & NV_RX2_FRAMINGERR) { | 1169 | if (len < 0) { |
1113 | if (Flags & NV_RX2_SUBSTRACT1) { | ||
1114 | len--; | ||
1115 | } | ||
1116 | } else { | ||
1117 | np->stats.rx_errors++; | 1170 | np->stats.rx_errors++; |
1118 | goto next_pkt; | 1171 | goto next_pkt; |
1119 | } | 1172 | } |
1120 | } | 1173 | } |
1174 | /* framing errors are soft errors */ | ||
1175 | if (Flags & NV_RX2_FRAMINGERR) { | ||
1176 | if (Flags & NV_RX2_SUBSTRACT1) { | ||
1177 | len--; | ||
1178 | } | ||
1179 | } | ||
1121 | Flags &= NV_RX2_CHECKSUMMASK; | 1180 | Flags &= NV_RX2_CHECKSUMMASK; |
1122 | if (Flags == NV_RX2_CHECKSUMOK1 || | 1181 | if (Flags == NV_RX2_CHECKSUMOK1 || |
1123 | Flags == NV_RX2_CHECKSUMOK2 || | 1182 | Flags == NV_RX2_CHECKSUMOK2 || |
@@ -1480,6 +1539,13 @@ static void nv_do_nic_poll(unsigned long data) | |||
1480 | enable_irq(dev->irq); | 1539 | enable_irq(dev->irq); |
1481 | } | 1540 | } |
1482 | 1541 | ||
1542 | #ifdef CONFIG_NET_POLL_CONTROLLER | ||
1543 | static void nv_poll_controller(struct net_device *dev) | ||
1544 | { | ||
1545 | nv_do_nic_poll((unsigned long) dev); | ||
1546 | } | ||
1547 | #endif | ||
1548 | |||
1483 | static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | 1549 | static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
1484 | { | 1550 | { |
1485 | struct fe_priv *np = get_nvpriv(dev); | 1551 | struct fe_priv *np = get_nvpriv(dev); |
@@ -1962,6 +2028,9 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i | |||
1962 | dev->get_stats = nv_get_stats; | 2028 | dev->get_stats = nv_get_stats; |
1963 | dev->change_mtu = nv_change_mtu; | 2029 | dev->change_mtu = nv_change_mtu; |
1964 | dev->set_multicast_list = nv_set_multicast; | 2030 | dev->set_multicast_list = nv_set_multicast; |
2031 | #ifdef CONFIG_NET_POLL_CONTROLLER | ||
2032 | dev->poll_controller = nv_poll_controller; | ||
2033 | #endif | ||
1965 | SET_ETHTOOL_OPS(dev, &ops); | 2034 | SET_ETHTOOL_OPS(dev, &ops); |
1966 | dev->tx_timeout = nv_tx_timeout; | 2035 | dev->tx_timeout = nv_tx_timeout; |
1967 | dev->watchdog_timeo = NV_WATCHDOG_TIMEO; | 2036 | dev->watchdog_timeo = NV_WATCHDOG_TIMEO; |
diff --git a/drivers/net/ibm_emac/ibm_emac_core.c b/drivers/net/ibm_emac/ibm_emac_core.c index ab44358ddbfc..6482d994d489 100644 --- a/drivers/net/ibm_emac/ibm_emac_core.c +++ b/drivers/net/ibm_emac/ibm_emac_core.c | |||
@@ -1595,7 +1595,7 @@ static struct ethtool_ops emac_ethtool_ops = { | |||
1595 | static int emac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | 1595 | static int emac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
1596 | { | 1596 | { |
1597 | struct ocp_enet_private *fep = dev->priv; | 1597 | struct ocp_enet_private *fep = dev->priv; |
1598 | uint *data = (uint *) & rq->ifr_ifru; | 1598 | uint16_t *data = (uint16_t *) & rq->ifr_ifru; |
1599 | 1599 | ||
1600 | switch (cmd) { | 1600 | switch (cmd) { |
1601 | case SIOCGMIIPHY: | 1601 | case SIOCGMIIPHY: |
diff --git a/drivers/net/iseries_veth.c b/drivers/net/iseries_veth.c index 855f8b2cf13b..13ed8dc1e91d 100644 --- a/drivers/net/iseries_veth.c +++ b/drivers/net/iseries_veth.c | |||
@@ -924,7 +924,7 @@ static int veth_transmit_to_one(struct sk_buff *skb, HvLpIndex rlp, | |||
924 | 924 | ||
925 | spin_lock_irqsave(&cnx->lock, flags); | 925 | spin_lock_irqsave(&cnx->lock, flags); |
926 | 926 | ||
927 | if (! cnx->state & VETH_STATE_READY) | 927 | if (! (cnx->state & VETH_STATE_READY)) |
928 | goto drop; | 928 | goto drop; |
929 | 929 | ||
930 | if ((skb->len - 14) > VETH_MAX_MTU) | 930 | if ((skb->len - 14) > VETH_MAX_MTU) |
@@ -1023,6 +1023,8 @@ static int veth_start_xmit(struct sk_buff *skb, struct net_device *dev) | |||
1023 | 1023 | ||
1024 | lpmask = veth_transmit_to_many(skb, lpmask, dev); | 1024 | lpmask = veth_transmit_to_many(skb, lpmask, dev); |
1025 | 1025 | ||
1026 | dev->trans_start = jiffies; | ||
1027 | |||
1026 | if (! lpmask) { | 1028 | if (! lpmask) { |
1027 | dev_kfree_skb(skb); | 1029 | dev_kfree_skb(skb); |
1028 | } else { | 1030 | } else { |
@@ -1262,13 +1264,18 @@ static void veth_receive(struct veth_lpar_connection *cnx, | |||
1262 | 1264 | ||
1263 | vlan = skb->data[9]; | 1265 | vlan = skb->data[9]; |
1264 | dev = veth_dev[vlan]; | 1266 | dev = veth_dev[vlan]; |
1265 | if (! dev) | 1267 | if (! dev) { |
1266 | /* Some earlier versions of the driver sent | 1268 | /* |
1267 | broadcasts down all connections, even to | 1269 | * Some earlier versions of the driver sent |
1268 | lpars that weren't on the relevant vlan. | 1270 | * broadcasts down all connections, even to lpars |
1269 | So ignore packets belonging to a vlan we're | 1271 | * that weren't on the relevant vlan. So ignore |
1270 | not on. */ | 1272 | * packets belonging to a vlan we're not on. |
1273 | * We can also be here if we receive packets while | ||
1274 | * the driver is going down, because then dev is NULL. | ||
1275 | */ | ||
1276 | dev_kfree_skb_irq(skb); | ||
1271 | continue; | 1277 | continue; |
1278 | } | ||
1272 | 1279 | ||
1273 | port = (struct veth_port *)dev->priv; | 1280 | port = (struct veth_port *)dev->priv; |
1274 | dest = *((u64 *) skb->data) & 0xFFFFFFFFFFFF0000; | 1281 | dest = *((u64 *) skb->data) & 0xFFFFFFFFFFFF0000; |
@@ -1381,18 +1388,25 @@ void __exit veth_module_cleanup(void) | |||
1381 | { | 1388 | { |
1382 | int i; | 1389 | int i; |
1383 | 1390 | ||
1384 | vio_unregister_driver(&veth_driver); | 1391 | /* Stop the queues first to stop any new packets being sent. */ |
1392 | for (i = 0; i < HVMAXARCHITECTEDVIRTUALLANS; i++) | ||
1393 | if (veth_dev[i]) | ||
1394 | netif_stop_queue(veth_dev[i]); | ||
1385 | 1395 | ||
1396 | /* Stop the connections before we unregister the driver. This | ||
1397 | * ensures there's no skbs lying around holding the device open. */ | ||
1386 | for (i = 0; i < HVMAXARCHITECTEDLPS; ++i) | 1398 | for (i = 0; i < HVMAXARCHITECTEDLPS; ++i) |
1387 | veth_stop_connection(i); | 1399 | veth_stop_connection(i); |
1388 | 1400 | ||
1389 | HvLpEvent_unregisterHandler(HvLpEvent_Type_VirtualLan); | 1401 | HvLpEvent_unregisterHandler(HvLpEvent_Type_VirtualLan); |
1390 | 1402 | ||
1391 | /* Hypervisor callbacks may have scheduled more work while we | 1403 | /* Hypervisor callbacks may have scheduled more work while we |
1392 | * were destroying connections. Now that we've disconnected from | 1404 | * were stoping connections. Now that we've disconnected from |
1393 | * the hypervisor make sure everything's finished. */ | 1405 | * the hypervisor make sure everything's finished. */ |
1394 | flush_scheduled_work(); | 1406 | flush_scheduled_work(); |
1395 | 1407 | ||
1408 | vio_unregister_driver(&veth_driver); | ||
1409 | |||
1396 | for (i = 0; i < HVMAXARCHITECTEDLPS; ++i) | 1410 | for (i = 0; i < HVMAXARCHITECTEDLPS; ++i) |
1397 | veth_destroy_connection(i); | 1411 | veth_destroy_connection(i); |
1398 | 1412 | ||
diff --git a/drivers/net/ixgb/ixgb.h b/drivers/net/ixgb/ixgb.h index 26c4f15f7fc0..f8d3385c7842 100644 --- a/drivers/net/ixgb/ixgb.h +++ b/drivers/net/ixgb/ixgb.h | |||
@@ -110,7 +110,7 @@ struct ixgb_adapter; | |||
110 | #define IXGB_TX_QUEUE_WAKE 16 | 110 | #define IXGB_TX_QUEUE_WAKE 16 |
111 | 111 | ||
112 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ | 112 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ |
113 | #define IXGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */ | 113 | #define IXGB_RX_BUFFER_WRITE 4 /* Must be power of 2 */ |
114 | 114 | ||
115 | /* only works for sizes that are powers of 2 */ | 115 | /* only works for sizes that are powers of 2 */ |
116 | #define IXGB_ROUNDUP(i, size) ((i) = (((i) + (size) - 1) & ~((size) - 1))) | 116 | #define IXGB_ROUNDUP(i, size) ((i) = (((i) + (size) - 1) & ~((size) - 1))) |
diff --git a/drivers/net/ixgb/ixgb_ee.c b/drivers/net/ixgb/ixgb_ee.c index 653e99f919ce..3aae110c5560 100644 --- a/drivers/net/ixgb/ixgb_ee.c +++ b/drivers/net/ixgb/ixgb_ee.c | |||
@@ -411,7 +411,7 @@ ixgb_write_eeprom(struct ixgb_hw *hw, uint16_t offset, uint16_t data) | |||
411 | ixgb_cleanup_eeprom(hw); | 411 | ixgb_cleanup_eeprom(hw); |
412 | 412 | ||
413 | /* clear the init_ctrl_reg_1 to signify that the cache is invalidated */ | 413 | /* clear the init_ctrl_reg_1 to signify that the cache is invalidated */ |
414 | ee_map->init_ctrl_reg_1 = EEPROM_ICW1_SIGNATURE_CLEAR; | 414 | ee_map->init_ctrl_reg_1 = le16_to_cpu(EEPROM_ICW1_SIGNATURE_CLEAR); |
415 | 415 | ||
416 | return; | 416 | return; |
417 | } | 417 | } |
@@ -483,7 +483,7 @@ ixgb_get_eeprom_data(struct ixgb_hw *hw) | |||
483 | DEBUGOUT("ixgb_ee: Checksum invalid.\n"); | 483 | DEBUGOUT("ixgb_ee: Checksum invalid.\n"); |
484 | /* clear the init_ctrl_reg_1 to signify that the cache is | 484 | /* clear the init_ctrl_reg_1 to signify that the cache is |
485 | * invalidated */ | 485 | * invalidated */ |
486 | ee_map->init_ctrl_reg_1 = EEPROM_ICW1_SIGNATURE_CLEAR; | 486 | ee_map->init_ctrl_reg_1 = le16_to_cpu(EEPROM_ICW1_SIGNATURE_CLEAR); |
487 | return (FALSE); | 487 | return (FALSE); |
488 | } | 488 | } |
489 | 489 | ||
@@ -579,7 +579,7 @@ ixgb_get_ee_compatibility(struct ixgb_hw *hw) | |||
579 | struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; | 579 | struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; |
580 | 580 | ||
581 | if(ixgb_check_and_get_eeprom_data(hw) == TRUE) | 581 | if(ixgb_check_and_get_eeprom_data(hw) == TRUE) |
582 | return(ee_map->compatibility); | 582 | return (le16_to_cpu(ee_map->compatibility)); |
583 | 583 | ||
584 | return(0); | 584 | return(0); |
585 | } | 585 | } |
@@ -616,7 +616,7 @@ ixgb_get_ee_init_ctrl_reg_1(struct ixgb_hw *hw) | |||
616 | struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; | 616 | struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; |
617 | 617 | ||
618 | if(ixgb_check_and_get_eeprom_data(hw) == TRUE) | 618 | if(ixgb_check_and_get_eeprom_data(hw) == TRUE) |
619 | return(ee_map->init_ctrl_reg_1); | 619 | return (le16_to_cpu(ee_map->init_ctrl_reg_1)); |
620 | 620 | ||
621 | return(0); | 621 | return(0); |
622 | } | 622 | } |
@@ -635,7 +635,7 @@ ixgb_get_ee_init_ctrl_reg_2(struct ixgb_hw *hw) | |||
635 | struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; | 635 | struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; |
636 | 636 | ||
637 | if(ixgb_check_and_get_eeprom_data(hw) == TRUE) | 637 | if(ixgb_check_and_get_eeprom_data(hw) == TRUE) |
638 | return(ee_map->init_ctrl_reg_2); | 638 | return (le16_to_cpu(ee_map->init_ctrl_reg_2)); |
639 | 639 | ||
640 | return(0); | 640 | return(0); |
641 | } | 641 | } |
@@ -654,7 +654,7 @@ ixgb_get_ee_subsystem_id(struct ixgb_hw *hw) | |||
654 | struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; | 654 | struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; |
655 | 655 | ||
656 | if(ixgb_check_and_get_eeprom_data(hw) == TRUE) | 656 | if(ixgb_check_and_get_eeprom_data(hw) == TRUE) |
657 | return(ee_map->subsystem_id); | 657 | return (le16_to_cpu(ee_map->subsystem_id)); |
658 | 658 | ||
659 | return(0); | 659 | return(0); |
660 | } | 660 | } |
@@ -673,7 +673,7 @@ ixgb_get_ee_subvendor_id(struct ixgb_hw *hw) | |||
673 | struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; | 673 | struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; |
674 | 674 | ||
675 | if(ixgb_check_and_get_eeprom_data(hw) == TRUE) | 675 | if(ixgb_check_and_get_eeprom_data(hw) == TRUE) |
676 | return(ee_map->subvendor_id); | 676 | return (le16_to_cpu(ee_map->subvendor_id)); |
677 | 677 | ||
678 | return(0); | 678 | return(0); |
679 | } | 679 | } |
@@ -692,7 +692,7 @@ ixgb_get_ee_device_id(struct ixgb_hw *hw) | |||
692 | struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; | 692 | struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; |
693 | 693 | ||
694 | if(ixgb_check_and_get_eeprom_data(hw) == TRUE) | 694 | if(ixgb_check_and_get_eeprom_data(hw) == TRUE) |
695 | return(ee_map->device_id); | 695 | return (le16_to_cpu(ee_map->device_id)); |
696 | 696 | ||
697 | return(0); | 697 | return(0); |
698 | } | 698 | } |
@@ -711,7 +711,7 @@ ixgb_get_ee_vendor_id(struct ixgb_hw *hw) | |||
711 | struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; | 711 | struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; |
712 | 712 | ||
713 | if(ixgb_check_and_get_eeprom_data(hw) == TRUE) | 713 | if(ixgb_check_and_get_eeprom_data(hw) == TRUE) |
714 | return(ee_map->vendor_id); | 714 | return (le16_to_cpu(ee_map->vendor_id)); |
715 | 715 | ||
716 | return(0); | 716 | return(0); |
717 | } | 717 | } |
@@ -730,7 +730,7 @@ ixgb_get_ee_swdpins_reg(struct ixgb_hw *hw) | |||
730 | struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; | 730 | struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; |
731 | 731 | ||
732 | if(ixgb_check_and_get_eeprom_data(hw) == TRUE) | 732 | if(ixgb_check_and_get_eeprom_data(hw) == TRUE) |
733 | return(ee_map->swdpins_reg); | 733 | return (le16_to_cpu(ee_map->swdpins_reg)); |
734 | 734 | ||
735 | return(0); | 735 | return(0); |
736 | } | 736 | } |
@@ -749,7 +749,7 @@ ixgb_get_ee_d3_power(struct ixgb_hw *hw) | |||
749 | struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; | 749 | struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; |
750 | 750 | ||
751 | if(ixgb_check_and_get_eeprom_data(hw) == TRUE) | 751 | if(ixgb_check_and_get_eeprom_data(hw) == TRUE) |
752 | return(ee_map->d3_power); | 752 | return (le16_to_cpu(ee_map->d3_power)); |
753 | 753 | ||
754 | return(0); | 754 | return(0); |
755 | } | 755 | } |
@@ -768,7 +768,7 @@ ixgb_get_ee_d0_power(struct ixgb_hw *hw) | |||
768 | struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; | 768 | struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom; |
769 | 769 | ||
770 | if(ixgb_check_and_get_eeprom_data(hw) == TRUE) | 770 | if(ixgb_check_and_get_eeprom_data(hw) == TRUE) |
771 | return(ee_map->d0_power); | 771 | return (le16_to_cpu(ee_map->d0_power)); |
772 | 772 | ||
773 | return(0); | 773 | return(0); |
774 | } | 774 | } |
diff --git a/drivers/net/ixgb/ixgb_ethtool.c b/drivers/net/ixgb/ixgb_ethtool.c index aea10e8aaa72..3fa113854eeb 100644 --- a/drivers/net/ixgb/ixgb_ethtool.c +++ b/drivers/net/ixgb/ixgb_ethtool.c | |||
@@ -252,7 +252,9 @@ ixgb_get_regs(struct net_device *netdev, | |||
252 | uint32_t *reg_start = reg; | 252 | uint32_t *reg_start = reg; |
253 | uint8_t i; | 253 | uint8_t i; |
254 | 254 | ||
255 | regs->version = (adapter->hw.device_id << 16) | adapter->hw.subsystem_id; | 255 | /* the 1 (one) below indicates an attempt at versioning, if the |
256 | * interface in ethtool or the driver this 1 should be incremented */ | ||
257 | regs->version = (1<<24) | hw->revision_id << 16 | hw->device_id; | ||
256 | 258 | ||
257 | /* General Registers */ | 259 | /* General Registers */ |
258 | *reg++ = IXGB_READ_REG(hw, CTRL0); /* 0 */ | 260 | *reg++ = IXGB_READ_REG(hw, CTRL0); /* 0 */ |
diff --git a/drivers/net/ixgb/ixgb_main.c b/drivers/net/ixgb/ixgb_main.c index 7d26623d8592..35f6a7c271a2 100644 --- a/drivers/net/ixgb/ixgb_main.c +++ b/drivers/net/ixgb/ixgb_main.c | |||
@@ -47,7 +47,7 @@ char ixgb_driver_string[] = "Intel(R) PRO/10GbE Network Driver"; | |||
47 | #else | 47 | #else |
48 | #define DRIVERNAPI "-NAPI" | 48 | #define DRIVERNAPI "-NAPI" |
49 | #endif | 49 | #endif |
50 | char ixgb_driver_version[] = "1.0.90-k2"DRIVERNAPI; | 50 | char ixgb_driver_version[] = "1.0.95-k2"DRIVERNAPI; |
51 | char ixgb_copyright[] = "Copyright (c) 1999-2005 Intel Corporation."; | 51 | char ixgb_copyright[] = "Copyright (c) 1999-2005 Intel Corporation."; |
52 | 52 | ||
53 | /* ixgb_pci_tbl - PCI Device ID Table | 53 | /* ixgb_pci_tbl - PCI Device ID Table |
@@ -103,6 +103,7 @@ static int ixgb_change_mtu(struct net_device *netdev, int new_mtu); | |||
103 | static int ixgb_set_mac(struct net_device *netdev, void *p); | 103 | static int ixgb_set_mac(struct net_device *netdev, void *p); |
104 | static irqreturn_t ixgb_intr(int irq, void *data, struct pt_regs *regs); | 104 | static irqreturn_t ixgb_intr(int irq, void *data, struct pt_regs *regs); |
105 | static boolean_t ixgb_clean_tx_irq(struct ixgb_adapter *adapter); | 105 | static boolean_t ixgb_clean_tx_irq(struct ixgb_adapter *adapter); |
106 | |||
106 | #ifdef CONFIG_IXGB_NAPI | 107 | #ifdef CONFIG_IXGB_NAPI |
107 | static int ixgb_clean(struct net_device *netdev, int *budget); | 108 | static int ixgb_clean(struct net_device *netdev, int *budget); |
108 | static boolean_t ixgb_clean_rx_irq(struct ixgb_adapter *adapter, | 109 | static boolean_t ixgb_clean_rx_irq(struct ixgb_adapter *adapter, |
@@ -120,33 +121,20 @@ static void ixgb_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid); | |||
120 | static void ixgb_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid); | 121 | static void ixgb_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid); |
121 | static void ixgb_restore_vlan(struct ixgb_adapter *adapter); | 122 | static void ixgb_restore_vlan(struct ixgb_adapter *adapter); |
122 | 123 | ||
123 | static int ixgb_notify_reboot(struct notifier_block *, unsigned long event, | ||
124 | void *ptr); | ||
125 | static int ixgb_suspend(struct pci_dev *pdev, uint32_t state); | ||
126 | |||
127 | #ifdef CONFIG_NET_POLL_CONTROLLER | 124 | #ifdef CONFIG_NET_POLL_CONTROLLER |
128 | /* for netdump / net console */ | 125 | /* for netdump / net console */ |
129 | static void ixgb_netpoll(struct net_device *dev); | 126 | static void ixgb_netpoll(struct net_device *dev); |
130 | #endif | 127 | #endif |
131 | 128 | ||
132 | struct notifier_block ixgb_notifier_reboot = { | ||
133 | .notifier_call = ixgb_notify_reboot, | ||
134 | .next = NULL, | ||
135 | .priority = 0 | ||
136 | }; | ||
137 | |||
138 | /* Exported from other modules */ | 129 | /* Exported from other modules */ |
139 | 130 | ||
140 | extern void ixgb_check_options(struct ixgb_adapter *adapter); | 131 | extern void ixgb_check_options(struct ixgb_adapter *adapter); |
141 | 132 | ||
142 | static struct pci_driver ixgb_driver = { | 133 | static struct pci_driver ixgb_driver = { |
143 | .name = ixgb_driver_name, | 134 | .name = ixgb_driver_name, |
144 | .id_table = ixgb_pci_tbl, | 135 | .id_table = ixgb_pci_tbl, |
145 | .probe = ixgb_probe, | 136 | .probe = ixgb_probe, |
146 | .remove = __devexit_p(ixgb_remove), | 137 | .remove = __devexit_p(ixgb_remove), |
147 | /* Power Managment Hooks */ | ||
148 | .suspend = NULL, | ||
149 | .resume = NULL | ||
150 | }; | 138 | }; |
151 | 139 | ||
152 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); | 140 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
@@ -169,17 +157,12 @@ MODULE_LICENSE("GPL"); | |||
169 | static int __init | 157 | static int __init |
170 | ixgb_init_module(void) | 158 | ixgb_init_module(void) |
171 | { | 159 | { |
172 | int ret; | ||
173 | printk(KERN_INFO "%s - version %s\n", | 160 | printk(KERN_INFO "%s - version %s\n", |
174 | ixgb_driver_string, ixgb_driver_version); | 161 | ixgb_driver_string, ixgb_driver_version); |
175 | 162 | ||
176 | printk(KERN_INFO "%s\n", ixgb_copyright); | 163 | printk(KERN_INFO "%s\n", ixgb_copyright); |
177 | 164 | ||
178 | ret = pci_module_init(&ixgb_driver); | 165 | return pci_module_init(&ixgb_driver); |
179 | if(ret >= 0) { | ||
180 | register_reboot_notifier(&ixgb_notifier_reboot); | ||
181 | } | ||
182 | return ret; | ||
183 | } | 166 | } |
184 | 167 | ||
185 | module_init(ixgb_init_module); | 168 | module_init(ixgb_init_module); |
@@ -194,7 +177,6 @@ module_init(ixgb_init_module); | |||
194 | static void __exit | 177 | static void __exit |
195 | ixgb_exit_module(void) | 178 | ixgb_exit_module(void) |
196 | { | 179 | { |
197 | unregister_reboot_notifier(&ixgb_notifier_reboot); | ||
198 | pci_unregister_driver(&ixgb_driver); | 180 | pci_unregister_driver(&ixgb_driver); |
199 | } | 181 | } |
200 | 182 | ||
@@ -224,8 +206,8 @@ ixgb_irq_enable(struct ixgb_adapter *adapter) | |||
224 | { | 206 | { |
225 | if(atomic_dec_and_test(&adapter->irq_sem)) { | 207 | if(atomic_dec_and_test(&adapter->irq_sem)) { |
226 | IXGB_WRITE_REG(&adapter->hw, IMS, | 208 | IXGB_WRITE_REG(&adapter->hw, IMS, |
227 | IXGB_INT_RXT0 | IXGB_INT_RXDMT0 | IXGB_INT_TXDW | | 209 | IXGB_INT_RXT0 | IXGB_INT_RXDMT0 | IXGB_INT_TXDW | |
228 | IXGB_INT_RXO | IXGB_INT_LSC); | 210 | IXGB_INT_LSC); |
229 | IXGB_WRITE_FLUSH(&adapter->hw); | 211 | IXGB_WRITE_FLUSH(&adapter->hw); |
230 | } | 212 | } |
231 | } | 213 | } |
@@ -1209,10 +1191,10 @@ ixgb_tso(struct ixgb_adapter *adapter, struct sk_buff *skb) | |||
1209 | | IXGB_CONTEXT_DESC_CMD_TSE | 1191 | | IXGB_CONTEXT_DESC_CMD_TSE |
1210 | | IXGB_CONTEXT_DESC_CMD_IP | 1192 | | IXGB_CONTEXT_DESC_CMD_IP |
1211 | | IXGB_CONTEXT_DESC_CMD_TCP | 1193 | | IXGB_CONTEXT_DESC_CMD_TCP |
1212 | | IXGB_CONTEXT_DESC_CMD_RS | ||
1213 | | IXGB_CONTEXT_DESC_CMD_IDE | 1194 | | IXGB_CONTEXT_DESC_CMD_IDE |
1214 | | (skb->len - (hdr_len))); | 1195 | | (skb->len - (hdr_len))); |
1215 | 1196 | ||
1197 | |||
1216 | if(++i == adapter->tx_ring.count) i = 0; | 1198 | if(++i == adapter->tx_ring.count) i = 0; |
1217 | adapter->tx_ring.next_to_use = i; | 1199 | adapter->tx_ring.next_to_use = i; |
1218 | 1200 | ||
@@ -1247,8 +1229,7 @@ ixgb_tx_csum(struct ixgb_adapter *adapter, struct sk_buff *skb) | |||
1247 | context_desc->mss = 0; | 1229 | context_desc->mss = 0; |
1248 | context_desc->cmd_type_len = | 1230 | context_desc->cmd_type_len = |
1249 | cpu_to_le32(IXGB_CONTEXT_DESC_TYPE | 1231 | cpu_to_le32(IXGB_CONTEXT_DESC_TYPE |
1250 | | IXGB_TX_DESC_CMD_RS | 1232 | | IXGB_TX_DESC_CMD_IDE); |
1251 | | IXGB_TX_DESC_CMD_IDE); | ||
1252 | 1233 | ||
1253 | if(++i == adapter->tx_ring.count) i = 0; | 1234 | if(++i == adapter->tx_ring.count) i = 0; |
1254 | adapter->tx_ring.next_to_use = i; | 1235 | adapter->tx_ring.next_to_use = i; |
@@ -1273,6 +1254,7 @@ ixgb_tx_map(struct ixgb_adapter *adapter, struct sk_buff *skb, | |||
1273 | 1254 | ||
1274 | unsigned int nr_frags = skb_shinfo(skb)->nr_frags; | 1255 | unsigned int nr_frags = skb_shinfo(skb)->nr_frags; |
1275 | unsigned int f; | 1256 | unsigned int f; |
1257 | |||
1276 | len -= skb->data_len; | 1258 | len -= skb->data_len; |
1277 | 1259 | ||
1278 | i = tx_ring->next_to_use; | 1260 | i = tx_ring->next_to_use; |
@@ -1526,14 +1508,33 @@ ixgb_change_mtu(struct net_device *netdev, int new_mtu) | |||
1526 | void | 1508 | void |
1527 | ixgb_update_stats(struct ixgb_adapter *adapter) | 1509 | ixgb_update_stats(struct ixgb_adapter *adapter) |
1528 | { | 1510 | { |
1511 | struct net_device *netdev = adapter->netdev; | ||
1512 | |||
1513 | if((netdev->flags & IFF_PROMISC) || (netdev->flags & IFF_ALLMULTI) || | ||
1514 | (netdev->mc_count > IXGB_MAX_NUM_MULTICAST_ADDRESSES)) { | ||
1515 | u64 multi = IXGB_READ_REG(&adapter->hw, MPRCL); | ||
1516 | u32 bcast_l = IXGB_READ_REG(&adapter->hw, BPRCL); | ||
1517 | u32 bcast_h = IXGB_READ_REG(&adapter->hw, BPRCH); | ||
1518 | u64 bcast = ((u64)bcast_h << 32) | bcast_l; | ||
1519 | |||
1520 | multi |= ((u64)IXGB_READ_REG(&adapter->hw, MPRCH) << 32); | ||
1521 | /* fix up multicast stats by removing broadcasts */ | ||
1522 | multi -= bcast; | ||
1523 | |||
1524 | adapter->stats.mprcl += (multi & 0xFFFFFFFF); | ||
1525 | adapter->stats.mprch += (multi >> 32); | ||
1526 | adapter->stats.bprcl += bcast_l; | ||
1527 | adapter->stats.bprch += bcast_h; | ||
1528 | } else { | ||
1529 | adapter->stats.mprcl += IXGB_READ_REG(&adapter->hw, MPRCL); | ||
1530 | adapter->stats.mprch += IXGB_READ_REG(&adapter->hw, MPRCH); | ||
1531 | adapter->stats.bprcl += IXGB_READ_REG(&adapter->hw, BPRCL); | ||
1532 | adapter->stats.bprch += IXGB_READ_REG(&adapter->hw, BPRCH); | ||
1533 | } | ||
1529 | adapter->stats.tprl += IXGB_READ_REG(&adapter->hw, TPRL); | 1534 | adapter->stats.tprl += IXGB_READ_REG(&adapter->hw, TPRL); |
1530 | adapter->stats.tprh += IXGB_READ_REG(&adapter->hw, TPRH); | 1535 | adapter->stats.tprh += IXGB_READ_REG(&adapter->hw, TPRH); |
1531 | adapter->stats.gprcl += IXGB_READ_REG(&adapter->hw, GPRCL); | 1536 | adapter->stats.gprcl += IXGB_READ_REG(&adapter->hw, GPRCL); |
1532 | adapter->stats.gprch += IXGB_READ_REG(&adapter->hw, GPRCH); | 1537 | adapter->stats.gprch += IXGB_READ_REG(&adapter->hw, GPRCH); |
1533 | adapter->stats.bprcl += IXGB_READ_REG(&adapter->hw, BPRCL); | ||
1534 | adapter->stats.bprch += IXGB_READ_REG(&adapter->hw, BPRCH); | ||
1535 | adapter->stats.mprcl += IXGB_READ_REG(&adapter->hw, MPRCL); | ||
1536 | adapter->stats.mprch += IXGB_READ_REG(&adapter->hw, MPRCH); | ||
1537 | adapter->stats.uprcl += IXGB_READ_REG(&adapter->hw, UPRCL); | 1538 | adapter->stats.uprcl += IXGB_READ_REG(&adapter->hw, UPRCL); |
1538 | adapter->stats.uprch += IXGB_READ_REG(&adapter->hw, UPRCH); | 1539 | adapter->stats.uprch += IXGB_READ_REG(&adapter->hw, UPRCH); |
1539 | adapter->stats.vprcl += IXGB_READ_REG(&adapter->hw, VPRCL); | 1540 | adapter->stats.vprcl += IXGB_READ_REG(&adapter->hw, VPRCL); |
@@ -1823,7 +1824,6 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter) | |||
1823 | struct pci_dev *pdev = adapter->pdev; | 1824 | struct pci_dev *pdev = adapter->pdev; |
1824 | struct ixgb_rx_desc *rx_desc, *next_rxd; | 1825 | struct ixgb_rx_desc *rx_desc, *next_rxd; |
1825 | struct ixgb_buffer *buffer_info, *next_buffer, *next2_buffer; | 1826 | struct ixgb_buffer *buffer_info, *next_buffer, *next2_buffer; |
1826 | struct sk_buff *skb, *next_skb; | ||
1827 | uint32_t length; | 1827 | uint32_t length; |
1828 | unsigned int i, j; | 1828 | unsigned int i, j; |
1829 | boolean_t cleaned = FALSE; | 1829 | boolean_t cleaned = FALSE; |
@@ -1833,6 +1833,8 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter) | |||
1833 | buffer_info = &rx_ring->buffer_info[i]; | 1833 | buffer_info = &rx_ring->buffer_info[i]; |
1834 | 1834 | ||
1835 | while(rx_desc->status & IXGB_RX_DESC_STATUS_DD) { | 1835 | while(rx_desc->status & IXGB_RX_DESC_STATUS_DD) { |
1836 | struct sk_buff *skb, *next_skb; | ||
1837 | u8 status; | ||
1836 | 1838 | ||
1837 | #ifdef CONFIG_IXGB_NAPI | 1839 | #ifdef CONFIG_IXGB_NAPI |
1838 | if(*work_done >= work_to_do) | 1840 | if(*work_done >= work_to_do) |
@@ -1840,7 +1842,9 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter) | |||
1840 | 1842 | ||
1841 | (*work_done)++; | 1843 | (*work_done)++; |
1842 | #endif | 1844 | #endif |
1845 | status = rx_desc->status; | ||
1843 | skb = buffer_info->skb; | 1846 | skb = buffer_info->skb; |
1847 | |||
1844 | prefetch(skb->data); | 1848 | prefetch(skb->data); |
1845 | 1849 | ||
1846 | if(++i == rx_ring->count) i = 0; | 1850 | if(++i == rx_ring->count) i = 0; |
@@ -1855,7 +1859,6 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter) | |||
1855 | next_skb = next_buffer->skb; | 1859 | next_skb = next_buffer->skb; |
1856 | prefetch(next_skb); | 1860 | prefetch(next_skb); |
1857 | 1861 | ||
1858 | |||
1859 | cleaned = TRUE; | 1862 | cleaned = TRUE; |
1860 | 1863 | ||
1861 | pci_unmap_single(pdev, | 1864 | pci_unmap_single(pdev, |
@@ -1865,7 +1868,7 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter) | |||
1865 | 1868 | ||
1866 | length = le16_to_cpu(rx_desc->length); | 1869 | length = le16_to_cpu(rx_desc->length); |
1867 | 1870 | ||
1868 | if(unlikely(!(rx_desc->status & IXGB_RX_DESC_STATUS_EOP))) { | 1871 | if(unlikely(!(status & IXGB_RX_DESC_STATUS_EOP))) { |
1869 | 1872 | ||
1870 | /* All receives must fit into a single buffer */ | 1873 | /* All receives must fit into a single buffer */ |
1871 | 1874 | ||
@@ -1873,12 +1876,7 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter) | |||
1873 | "length<%x>\n", length); | 1876 | "length<%x>\n", length); |
1874 | 1877 | ||
1875 | dev_kfree_skb_irq(skb); | 1878 | dev_kfree_skb_irq(skb); |
1876 | rx_desc->status = 0; | 1879 | goto rxdesc_done; |
1877 | buffer_info->skb = NULL; | ||
1878 | |||
1879 | rx_desc = next_rxd; | ||
1880 | buffer_info = next_buffer; | ||
1881 | continue; | ||
1882 | } | 1880 | } |
1883 | 1881 | ||
1884 | if (unlikely(rx_desc->errors | 1882 | if (unlikely(rx_desc->errors |
@@ -1887,12 +1885,7 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter) | |||
1887 | IXGB_RX_DESC_ERRORS_RXE))) { | 1885 | IXGB_RX_DESC_ERRORS_RXE))) { |
1888 | 1886 | ||
1889 | dev_kfree_skb_irq(skb); | 1887 | dev_kfree_skb_irq(skb); |
1890 | rx_desc->status = 0; | 1888 | goto rxdesc_done; |
1891 | buffer_info->skb = NULL; | ||
1892 | |||
1893 | rx_desc = next_rxd; | ||
1894 | buffer_info = next_buffer; | ||
1895 | continue; | ||
1896 | } | 1889 | } |
1897 | 1890 | ||
1898 | /* Good Receive */ | 1891 | /* Good Receive */ |
@@ -1903,7 +1896,7 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter) | |||
1903 | 1896 | ||
1904 | skb->protocol = eth_type_trans(skb, netdev); | 1897 | skb->protocol = eth_type_trans(skb, netdev); |
1905 | #ifdef CONFIG_IXGB_NAPI | 1898 | #ifdef CONFIG_IXGB_NAPI |
1906 | if(adapter->vlgrp && (rx_desc->status & IXGB_RX_DESC_STATUS_VP)) { | 1899 | if(adapter->vlgrp && (status & IXGB_RX_DESC_STATUS_VP)) { |
1907 | vlan_hwaccel_receive_skb(skb, adapter->vlgrp, | 1900 | vlan_hwaccel_receive_skb(skb, adapter->vlgrp, |
1908 | le16_to_cpu(rx_desc->special) & | 1901 | le16_to_cpu(rx_desc->special) & |
1909 | IXGB_RX_DESC_SPECIAL_VLAN_MASK); | 1902 | IXGB_RX_DESC_SPECIAL_VLAN_MASK); |
@@ -1911,7 +1904,7 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter) | |||
1911 | netif_receive_skb(skb); | 1904 | netif_receive_skb(skb); |
1912 | } | 1905 | } |
1913 | #else /* CONFIG_IXGB_NAPI */ | 1906 | #else /* CONFIG_IXGB_NAPI */ |
1914 | if(adapter->vlgrp && (rx_desc->status & IXGB_RX_DESC_STATUS_VP)) { | 1907 | if(adapter->vlgrp && (status & IXGB_RX_DESC_STATUS_VP)) { |
1915 | vlan_hwaccel_rx(skb, adapter->vlgrp, | 1908 | vlan_hwaccel_rx(skb, adapter->vlgrp, |
1916 | le16_to_cpu(rx_desc->special) & | 1909 | le16_to_cpu(rx_desc->special) & |
1917 | IXGB_RX_DESC_SPECIAL_VLAN_MASK); | 1910 | IXGB_RX_DESC_SPECIAL_VLAN_MASK); |
@@ -1921,9 +1914,12 @@ ixgb_clean_rx_irq(struct ixgb_adapter *adapter) | |||
1921 | #endif /* CONFIG_IXGB_NAPI */ | 1914 | #endif /* CONFIG_IXGB_NAPI */ |
1922 | netdev->last_rx = jiffies; | 1915 | netdev->last_rx = jiffies; |
1923 | 1916 | ||
1917 | rxdesc_done: | ||
1918 | /* clean up descriptor, might be written over by hw */ | ||
1924 | rx_desc->status = 0; | 1919 | rx_desc->status = 0; |
1925 | buffer_info->skb = NULL; | 1920 | buffer_info->skb = NULL; |
1926 | 1921 | ||
1922 | /* use prefetched values */ | ||
1927 | rx_desc = next_rxd; | 1923 | rx_desc = next_rxd; |
1928 | buffer_info = next_buffer; | 1924 | buffer_info = next_buffer; |
1929 | } | 1925 | } |
@@ -1959,8 +1955,8 @@ ixgb_alloc_rx_buffers(struct ixgb_adapter *adapter) | |||
1959 | 1955 | ||
1960 | num_group_tail_writes = IXGB_RX_BUFFER_WRITE; | 1956 | num_group_tail_writes = IXGB_RX_BUFFER_WRITE; |
1961 | 1957 | ||
1962 | /* leave one descriptor unused */ | 1958 | /* leave three descriptors unused */ |
1963 | while(--cleancount > 0) { | 1959 | while(--cleancount > 2) { |
1964 | rx_desc = IXGB_RX_DESC(*rx_ring, i); | 1960 | rx_desc = IXGB_RX_DESC(*rx_ring, i); |
1965 | 1961 | ||
1966 | skb = dev_alloc_skb(adapter->rx_buffer_len + NET_IP_ALIGN); | 1962 | skb = dev_alloc_skb(adapter->rx_buffer_len + NET_IP_ALIGN); |
@@ -1987,6 +1983,10 @@ ixgb_alloc_rx_buffers(struct ixgb_adapter *adapter) | |||
1987 | PCI_DMA_FROMDEVICE); | 1983 | PCI_DMA_FROMDEVICE); |
1988 | 1984 | ||
1989 | rx_desc->buff_addr = cpu_to_le64(buffer_info->dma); | 1985 | rx_desc->buff_addr = cpu_to_le64(buffer_info->dma); |
1986 | /* guarantee DD bit not set now before h/w gets descriptor | ||
1987 | * this is the rest of the workaround for h/w double | ||
1988 | * writeback. */ | ||
1989 | rx_desc->status = 0; | ||
1990 | 1990 | ||
1991 | if((i & ~(num_group_tail_writes- 1)) == i) { | 1991 | if((i & ~(num_group_tail_writes- 1)) == i) { |
1992 | /* Force memory writes to complete before letting h/w | 1992 | /* Force memory writes to complete before letting h/w |
@@ -2099,54 +2099,6 @@ ixgb_restore_vlan(struct ixgb_adapter *adapter) | |||
2099 | } | 2099 | } |
2100 | } | 2100 | } |
2101 | 2101 | ||
2102 | /** | ||
2103 | * ixgb_notify_reboot - handles OS notification of reboot event. | ||
2104 | * @param nb notifier block, unused | ||
2105 | * @param event Event being passed to driver to act upon | ||
2106 | * @param p A pointer to our net device | ||
2107 | **/ | ||
2108 | static int | ||
2109 | ixgb_notify_reboot(struct notifier_block *nb, unsigned long event, void *p) | ||
2110 | { | ||
2111 | struct pci_dev *pdev = NULL; | ||
2112 | |||
2113 | switch(event) { | ||
2114 | case SYS_DOWN: | ||
2115 | case SYS_HALT: | ||
2116 | case SYS_POWER_OFF: | ||
2117 | while ((pdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pdev))) { | ||
2118 | if (pci_dev_driver(pdev) == &ixgb_driver) | ||
2119 | ixgb_suspend(pdev, 3); | ||
2120 | } | ||
2121 | } | ||
2122 | return NOTIFY_DONE; | ||
2123 | } | ||
2124 | |||
2125 | /** | ||
2126 | * ixgb_suspend - driver suspend function called from notify. | ||
2127 | * @param pdev pci driver structure used for passing to | ||
2128 | * @param state power state to enter | ||
2129 | **/ | ||
2130 | static int | ||
2131 | ixgb_suspend(struct pci_dev *pdev, uint32_t state) | ||
2132 | { | ||
2133 | struct net_device *netdev = pci_get_drvdata(pdev); | ||
2134 | struct ixgb_adapter *adapter = netdev->priv; | ||
2135 | |||
2136 | netif_device_detach(netdev); | ||
2137 | |||
2138 | if(netif_running(netdev)) | ||
2139 | ixgb_down(adapter, TRUE); | ||
2140 | |||
2141 | pci_save_state(pdev); | ||
2142 | |||
2143 | state = (state > 0) ? 3 : 0; | ||
2144 | pci_set_power_state(pdev, state); | ||
2145 | msec_delay(200); | ||
2146 | |||
2147 | return 0; | ||
2148 | } | ||
2149 | |||
2150 | #ifdef CONFIG_NET_POLL_CONTROLLER | 2102 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2151 | /* | 2103 | /* |
2152 | * Polling 'interrupt' - used by things like netconsole to send skbs | 2104 | * Polling 'interrupt' - used by things like netconsole to send skbs |
@@ -2157,6 +2109,7 @@ ixgb_suspend(struct pci_dev *pdev, uint32_t state) | |||
2157 | static void ixgb_netpoll(struct net_device *dev) | 2109 | static void ixgb_netpoll(struct net_device *dev) |
2158 | { | 2110 | { |
2159 | struct ixgb_adapter *adapter = dev->priv; | 2111 | struct ixgb_adapter *adapter = dev->priv; |
2112 | |||
2160 | disable_irq(adapter->pdev->irq); | 2113 | disable_irq(adapter->pdev->irq); |
2161 | ixgb_intr(adapter->pdev->irq, dev, NULL); | 2114 | ixgb_intr(adapter->pdev->irq, dev, NULL); |
2162 | enable_irq(adapter->pdev->irq); | 2115 | enable_irq(adapter->pdev->irq); |
diff --git a/drivers/net/ixgb/ixgb_osdep.h b/drivers/net/ixgb/ixgb_osdep.h index 9eba92891901..dba20481ee80 100644 --- a/drivers/net/ixgb/ixgb_osdep.h +++ b/drivers/net/ixgb/ixgb_osdep.h | |||
@@ -45,8 +45,7 @@ | |||
45 | /* Don't mdelay in interrupt context! */ \ | 45 | /* Don't mdelay in interrupt context! */ \ |
46 | BUG(); \ | 46 | BUG(); \ |
47 | } else { \ | 47 | } else { \ |
48 | set_current_state(TASK_UNINTERRUPTIBLE); \ | 48 | msleep(x); \ |
49 | schedule_timeout((x * HZ)/1000 + 2); \ | ||
50 | } } while(0) | 49 | } } while(0) |
51 | #endif | 50 | #endif |
52 | 51 | ||
diff --git a/drivers/net/natsemi.c b/drivers/net/natsemi.c index 223bdadd4c0d..babb59e146ea 100644 --- a/drivers/net/natsemi.c +++ b/drivers/net/natsemi.c | |||
@@ -2433,9 +2433,9 @@ static void __set_rx_mode(struct net_device *dev) | |||
2433 | rx_mode = RxFilterEnable | AcceptBroadcast | 2433 | rx_mode = RxFilterEnable | AcceptBroadcast |
2434 | | AcceptMulticast | AcceptMyPhys; | 2434 | | AcceptMulticast | AcceptMyPhys; |
2435 | for (i = 0; i < 64; i += 2) { | 2435 | for (i = 0; i < 64; i += 2) { |
2436 | writew(HASH_TABLE + i, ioaddr + RxFilterAddr); | 2436 | writel(HASH_TABLE + i, ioaddr + RxFilterAddr); |
2437 | writew((mc_filter[i+1]<<8) + mc_filter[i], | 2437 | writel((mc_filter[i + 1] << 8) + mc_filter[i], |
2438 | ioaddr + RxFilterData); | 2438 | ioaddr + RxFilterData); |
2439 | } | 2439 | } |
2440 | } | 2440 | } |
2441 | writel(rx_mode, ioaddr + RxFilterAddr); | 2441 | writel(rx_mode, ioaddr + RxFilterAddr); |
diff --git a/drivers/net/ns83820.c b/drivers/net/ns83820.c index 2fcc181a8624..c336b46bd332 100644 --- a/drivers/net/ns83820.c +++ b/drivers/net/ns83820.c | |||
@@ -1,4 +1,4 @@ | |||
1 | #define _VERSION "0.20" | 1 | #define VERSION "0.22" |
2 | /* ns83820.c by Benjamin LaHaise with contributions. | 2 | /* ns83820.c by Benjamin LaHaise with contributions. |
3 | * | 3 | * |
4 | * Questions/comments/discussion to linux-ns83820@kvack.org. | 4 | * Questions/comments/discussion to linux-ns83820@kvack.org. |
@@ -63,9 +63,11 @@ | |||
63 | * - fix missed txok introduced during performance | 63 | * - fix missed txok introduced during performance |
64 | * tuning | 64 | * tuning |
65 | * 0.20 - fix stupid RFEN thinko. i am such a smurf. | 65 | * 0.20 - fix stupid RFEN thinko. i am such a smurf. |
66 | * | ||
67 | * 20040828 0.21 - add hardware vlan accleration | 66 | * 20040828 0.21 - add hardware vlan accleration |
68 | * by Neil Horman <nhorman@redhat.com> | 67 | * by Neil Horman <nhorman@redhat.com> |
68 | * 20050406 0.22 - improved DAC ifdefs from Andi Kleen | ||
69 | * - removal of dead code from Adrian Bunk | ||
70 | * - fix half duplex collision behaviour | ||
69 | * Driver Overview | 71 | * Driver Overview |
70 | * =============== | 72 | * =============== |
71 | * | 73 | * |
@@ -129,18 +131,6 @@ static int lnksts = 0; /* CFG_LNKSTS bit polarity */ | |||
129 | #undef Dprintk | 131 | #undef Dprintk |
130 | #define Dprintk dprintk | 132 | #define Dprintk dprintk |
131 | 133 | ||
132 | #if defined(CONFIG_HIGHMEM64G) || defined(__ia64__) | ||
133 | #define USE_64BIT_ADDR "+" | ||
134 | #endif | ||
135 | |||
136 | #if defined(USE_64BIT_ADDR) | ||
137 | #define VERSION _VERSION USE_64BIT_ADDR | ||
138 | #define TRY_DAC 1 | ||
139 | #else | ||
140 | #define VERSION _VERSION | ||
141 | #define TRY_DAC 0 | ||
142 | #endif | ||
143 | |||
144 | /* tunables */ | 134 | /* tunables */ |
145 | #define RX_BUF_SIZE 1500 /* 8192 */ | 135 | #define RX_BUF_SIZE 1500 /* 8192 */ |
146 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) | 136 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) |
@@ -386,22 +376,16 @@ static int lnksts = 0; /* CFG_LNKSTS bit polarity */ | |||
386 | #define LINK_DOWN 0x02 | 376 | #define LINK_DOWN 0x02 |
387 | #define LINK_UP 0x04 | 377 | #define LINK_UP 0x04 |
388 | 378 | ||
389 | #ifdef USE_64BIT_ADDR | 379 | #define HW_ADDR_LEN sizeof(dma_addr_t) |
390 | #define HW_ADDR_LEN 8 | ||
391 | #define desc_addr_set(desc, addr) \ | 380 | #define desc_addr_set(desc, addr) \ |
392 | do { \ | 381 | do { \ |
393 | u64 __addr = (addr); \ | 382 | ((desc)[0] = cpu_to_le32(addr)); \ |
394 | (desc)[0] = cpu_to_le32(__addr); \ | 383 | if (HW_ADDR_LEN == 8) \ |
395 | (desc)[1] = cpu_to_le32(__addr >> 32); \ | 384 | (desc)[1] = cpu_to_le32(((u64)addr) >> 32); \ |
396 | } while(0) | 385 | } while(0) |
397 | #define desc_addr_get(desc) \ | 386 | #define desc_addr_get(desc) \ |
398 | (((u64)le32_to_cpu((desc)[1]) << 32) \ | 387 | (le32_to_cpu((desc)[0]) | \ |
399 | | le32_to_cpu((desc)[0])) | 388 | (HW_ADDR_LEN == 8 ? ((dma_addr_t)le32_to_cpu((desc)[1]))<<32 : 0)) |
400 | #else | ||
401 | #define HW_ADDR_LEN 4 | ||
402 | #define desc_addr_set(desc, addr) ((desc)[0] = cpu_to_le32(addr)) | ||
403 | #define desc_addr_get(desc) (le32_to_cpu((desc)[0])) | ||
404 | #endif | ||
405 | 389 | ||
406 | #define DESC_LINK 0 | 390 | #define DESC_LINK 0 |
407 | #define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4) | 391 | #define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4) |
@@ -727,11 +711,23 @@ static void fastcall phy_intr(struct net_device *ndev) | |||
727 | speed = ((cfg / CFG_SPDSTS0) & 3); | 711 | speed = ((cfg / CFG_SPDSTS0) & 3); |
728 | fullduplex = (cfg & CFG_DUPSTS); | 712 | fullduplex = (cfg & CFG_DUPSTS); |
729 | 713 | ||
730 | if (fullduplex) | 714 | if (fullduplex) { |
731 | new_cfg |= CFG_SB; | 715 | new_cfg |= CFG_SB; |
716 | writel(readl(dev->base + TXCFG) | ||
717 | | TXCFG_CSI | TXCFG_HBI, | ||
718 | dev->base + TXCFG); | ||
719 | writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, | ||
720 | dev->base + RXCFG); | ||
721 | } else { | ||
722 | writel(readl(dev->base + TXCFG) | ||
723 | & ~(TXCFG_CSI | TXCFG_HBI), | ||
724 | dev->base + TXCFG); | ||
725 | writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD), | ||
726 | dev->base + RXCFG); | ||
727 | } | ||
732 | 728 | ||
733 | if ((cfg & CFG_LNKSTS) && | 729 | if ((cfg & CFG_LNKSTS) && |
734 | ((new_cfg ^ dev->CFG_cache) & CFG_MODE_1000)) { | 730 | ((new_cfg ^ dev->CFG_cache) != 0)) { |
735 | writel(new_cfg, dev->base + CFG); | 731 | writel(new_cfg, dev->base + CFG); |
736 | dev->CFG_cache = new_cfg; | 732 | dev->CFG_cache = new_cfg; |
737 | } | 733 | } |
@@ -1189,7 +1185,6 @@ again: | |||
1189 | 1185 | ||
1190 | for (;;) { | 1186 | for (;;) { |
1191 | volatile u32 *desc = dev->tx_descs + (free_idx * DESC_SIZE); | 1187 | volatile u32 *desc = dev->tx_descs + (free_idx * DESC_SIZE); |
1192 | u32 residue = 0; | ||
1193 | 1188 | ||
1194 | dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len, | 1189 | dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len, |
1195 | (unsigned long long)buf); | 1190 | (unsigned long long)buf); |
@@ -1199,17 +1194,11 @@ again: | |||
1199 | desc_addr_set(desc + DESC_BUFPTR, buf); | 1194 | desc_addr_set(desc + DESC_BUFPTR, buf); |
1200 | desc[DESC_EXTSTS] = cpu_to_le32(extsts); | 1195 | desc[DESC_EXTSTS] = cpu_to_le32(extsts); |
1201 | 1196 | ||
1202 | cmdsts = ((nr_frags|residue) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0); | 1197 | cmdsts = ((nr_frags) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0); |
1203 | cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN; | 1198 | cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN; |
1204 | cmdsts |= len; | 1199 | cmdsts |= len; |
1205 | desc[DESC_CMDSTS] = cpu_to_le32(cmdsts); | 1200 | desc[DESC_CMDSTS] = cpu_to_le32(cmdsts); |
1206 | 1201 | ||
1207 | if (residue) { | ||
1208 | buf += len; | ||
1209 | len = residue; | ||
1210 | continue; | ||
1211 | } | ||
1212 | |||
1213 | if (!nr_frags) | 1202 | if (!nr_frags) |
1214 | break; | 1203 | break; |
1215 | 1204 | ||
@@ -1841,7 +1830,8 @@ static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_ | |||
1841 | int using_dac = 0; | 1830 | int using_dac = 0; |
1842 | 1831 | ||
1843 | /* See if we can set the dma mask early on; failure is fatal. */ | 1832 | /* See if we can set the dma mask early on; failure is fatal. */ |
1844 | if (TRY_DAC && !pci_set_dma_mask(pci_dev, 0xffffffffffffffffULL)) { | 1833 | if (sizeof(dma_addr_t) == 8 && |
1834 | !pci_set_dma_mask(pci_dev, 0xffffffffffffffffULL)) { | ||
1845 | using_dac = 1; | 1835 | using_dac = 1; |
1846 | } else if (!pci_set_dma_mask(pci_dev, 0xffffffff)) { | 1836 | } else if (!pci_set_dma_mask(pci_dev, 0xffffffff)) { |
1847 | using_dac = 0; | 1837 | using_dac = 0; |
@@ -1972,9 +1962,8 @@ static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_ | |||
1972 | /* When compiled with 64 bit addressing, we must always enable | 1962 | /* When compiled with 64 bit addressing, we must always enable |
1973 | * the 64 bit descriptor format. | 1963 | * the 64 bit descriptor format. |
1974 | */ | 1964 | */ |
1975 | #ifdef USE_64BIT_ADDR | 1965 | if (sizeof(dma_addr_t) == 8) |
1976 | dev->CFG_cache |= CFG_M64ADDR; | 1966 | dev->CFG_cache |= CFG_M64ADDR; |
1977 | #endif | ||
1978 | if (using_dac) | 1967 | if (using_dac) |
1979 | dev->CFG_cache |= CFG_T64ADDR; | 1968 | dev->CFG_cache |= CFG_T64ADDR; |
1980 | 1969 | ||
diff --git a/drivers/net/pcnet32.c b/drivers/net/pcnet32.c index 17947e6c8793..13f114876965 100644 --- a/drivers/net/pcnet32.c +++ b/drivers/net/pcnet32.c | |||
@@ -22,8 +22,8 @@ | |||
22 | *************************************************************************/ | 22 | *************************************************************************/ |
23 | 23 | ||
24 | #define DRV_NAME "pcnet32" | 24 | #define DRV_NAME "pcnet32" |
25 | #define DRV_VERSION "1.30i" | 25 | #define DRV_VERSION "1.30j" |
26 | #define DRV_RELDATE "06.28.2004" | 26 | #define DRV_RELDATE "29.04.2005" |
27 | #define PFX DRV_NAME ": " | 27 | #define PFX DRV_NAME ": " |
28 | 28 | ||
29 | static const char *version = | 29 | static const char *version = |
@@ -256,6 +256,7 @@ static int homepna[MAX_UNITS]; | |||
256 | * homepna for selecting HomePNA mode for PCNet/Home 79C978. | 256 | * homepna for selecting HomePNA mode for PCNet/Home 79C978. |
257 | * v1.30h 24 Jun 2004 Don Fry correctly select auto, speed, duplex in bcr32. | 257 | * v1.30h 24 Jun 2004 Don Fry correctly select auto, speed, duplex in bcr32. |
258 | * v1.30i 28 Jun 2004 Don Fry change to use module_param. | 258 | * v1.30i 28 Jun 2004 Don Fry change to use module_param. |
259 | * v1.30j 29 Apr 2005 Don Fry fix skb/map leak with loopback test. | ||
259 | */ | 260 | */ |
260 | 261 | ||
261 | 262 | ||
@@ -395,6 +396,7 @@ static void pcnet32_led_blink_callback(struct net_device *dev); | |||
395 | static int pcnet32_get_regs_len(struct net_device *dev); | 396 | static int pcnet32_get_regs_len(struct net_device *dev); |
396 | static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs, | 397 | static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs, |
397 | void *ptr); | 398 | void *ptr); |
399 | static void pcnet32_purge_tx_ring(struct net_device *dev); | ||
398 | 400 | ||
399 | enum pci_flags_bit { | 401 | enum pci_flags_bit { |
400 | PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4, | 402 | PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4, |
@@ -785,6 +787,7 @@ static int pcnet32_loopback_test(struct net_device *dev, uint64_t *data1) | |||
785 | } | 787 | } |
786 | 788 | ||
787 | clean_up: | 789 | clean_up: |
790 | pcnet32_purge_tx_ring(dev); | ||
788 | x = a->read_csr(ioaddr, 15) & 0xFFFF; | 791 | x = a->read_csr(ioaddr, 15) & 0xFFFF; |
789 | a->write_csr(ioaddr, 15, (x & ~0x0044)); /* reset bits 6 and 2 */ | 792 | a->write_csr(ioaddr, 15, (x & ~0x0044)); /* reset bits 6 and 2 */ |
790 | 793 | ||
diff --git a/drivers/net/sis900.c b/drivers/net/sis900.c index 3e9d9aab0588..3107aed0fb51 100644 --- a/drivers/net/sis900.c +++ b/drivers/net/sis900.c | |||
@@ -162,6 +162,7 @@ struct sis900_private { | |||
162 | struct mii_phy * mii; | 162 | struct mii_phy * mii; |
163 | struct mii_phy * first_mii; /* record the first mii structure */ | 163 | struct mii_phy * first_mii; /* record the first mii structure */ |
164 | unsigned int cur_phy; | 164 | unsigned int cur_phy; |
165 | struct mii_if_info mii_info; | ||
165 | 166 | ||
166 | struct timer_list timer; /* Link status detection timer. */ | 167 | struct timer_list timer; /* Link status detection timer. */ |
167 | u8 autong_complete; /* 1: auto-negotiate complete */ | 168 | u8 autong_complete; /* 1: auto-negotiate complete */ |
@@ -203,7 +204,7 @@ static int sis900_open(struct net_device *net_dev); | |||
203 | static int sis900_mii_probe (struct net_device * net_dev); | 204 | static int sis900_mii_probe (struct net_device * net_dev); |
204 | static void sis900_init_rxfilter (struct net_device * net_dev); | 205 | static void sis900_init_rxfilter (struct net_device * net_dev); |
205 | static u16 read_eeprom(long ioaddr, int location); | 206 | static u16 read_eeprom(long ioaddr, int location); |
206 | static u16 mdio_read(struct net_device *net_dev, int phy_id, int location); | 207 | static int mdio_read(struct net_device *net_dev, int phy_id, int location); |
207 | static void mdio_write(struct net_device *net_dev, int phy_id, int location, int val); | 208 | static void mdio_write(struct net_device *net_dev, int phy_id, int location, int val); |
208 | static void sis900_timer(unsigned long data); | 209 | static void sis900_timer(unsigned long data); |
209 | static void sis900_check_mode (struct net_device *net_dev, struct mii_phy *mii_phy); | 210 | static void sis900_check_mode (struct net_device *net_dev, struct mii_phy *mii_phy); |
@@ -478,7 +479,13 @@ static int __devinit sis900_probe(struct pci_dev *pci_dev, | |||
478 | sis_priv->msg_enable = sis900_debug; | 479 | sis_priv->msg_enable = sis900_debug; |
479 | else | 480 | else |
480 | sis_priv->msg_enable = SIS900_DEF_MSG; | 481 | sis_priv->msg_enable = SIS900_DEF_MSG; |
481 | 482 | ||
483 | sis_priv->mii_info.dev = net_dev; | ||
484 | sis_priv->mii_info.mdio_read = mdio_read; | ||
485 | sis_priv->mii_info.mdio_write = mdio_write; | ||
486 | sis_priv->mii_info.phy_id_mask = 0x1f; | ||
487 | sis_priv->mii_info.reg_num_mask = 0x1f; | ||
488 | |||
482 | /* Get Mac address according to the chip revision */ | 489 | /* Get Mac address according to the chip revision */ |
483 | pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &(sis_priv->chipset_rev)); | 490 | pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &(sis_priv->chipset_rev)); |
484 | if(netif_msg_probe(sis_priv)) | 491 | if(netif_msg_probe(sis_priv)) |
@@ -725,6 +732,8 @@ static u16 sis900_default_phy(struct net_device * net_dev) | |||
725 | pci_name(sis_priv->pci_dev), sis_priv->cur_phy); | 732 | pci_name(sis_priv->pci_dev), sis_priv->cur_phy); |
726 | } | 733 | } |
727 | 734 | ||
735 | sis_priv->mii_info.phy_id = sis_priv->cur_phy; | ||
736 | |||
728 | status = mdio_read(net_dev, sis_priv->cur_phy, MII_CONTROL); | 737 | status = mdio_read(net_dev, sis_priv->cur_phy, MII_CONTROL); |
729 | status &= (~MII_CNTL_ISOLATE); | 738 | status &= (~MII_CNTL_ISOLATE); |
730 | 739 | ||
@@ -852,7 +861,7 @@ static void mdio_reset(long mdio_addr) | |||
852 | * Please see SiS7014 or ICS spec | 861 | * Please see SiS7014 or ICS spec |
853 | */ | 862 | */ |
854 | 863 | ||
855 | static u16 mdio_read(struct net_device *net_dev, int phy_id, int location) | 864 | static int mdio_read(struct net_device *net_dev, int phy_id, int location) |
856 | { | 865 | { |
857 | long mdio_addr = net_dev->base_addr + mear; | 866 | long mdio_addr = net_dev->base_addr + mear; |
858 | int mii_cmd = MIIread|(phy_id<<MIIpmdShift)|(location<<MIIregShift); | 867 | int mii_cmd = MIIread|(phy_id<<MIIpmdShift)|(location<<MIIregShift); |
@@ -1966,10 +1975,47 @@ static void sis900_set_msglevel(struct net_device *net_dev, u32 value) | |||
1966 | sis_priv->msg_enable = value; | 1975 | sis_priv->msg_enable = value; |
1967 | } | 1976 | } |
1968 | 1977 | ||
1978 | static u32 sis900_get_link(struct net_device *net_dev) | ||
1979 | { | ||
1980 | struct sis900_private *sis_priv = net_dev->priv; | ||
1981 | return mii_link_ok(&sis_priv->mii_info); | ||
1982 | } | ||
1983 | |||
1984 | static int sis900_get_settings(struct net_device *net_dev, | ||
1985 | struct ethtool_cmd *cmd) | ||
1986 | { | ||
1987 | struct sis900_private *sis_priv = net_dev->priv; | ||
1988 | spin_lock_irq(&sis_priv->lock); | ||
1989 | mii_ethtool_gset(&sis_priv->mii_info, cmd); | ||
1990 | spin_unlock_irq(&sis_priv->lock); | ||
1991 | return 0; | ||
1992 | } | ||
1993 | |||
1994 | static int sis900_set_settings(struct net_device *net_dev, | ||
1995 | struct ethtool_cmd *cmd) | ||
1996 | { | ||
1997 | struct sis900_private *sis_priv = net_dev->priv; | ||
1998 | int rt; | ||
1999 | spin_lock_irq(&sis_priv->lock); | ||
2000 | rt = mii_ethtool_sset(&sis_priv->mii_info, cmd); | ||
2001 | spin_unlock_irq(&sis_priv->lock); | ||
2002 | return rt; | ||
2003 | } | ||
2004 | |||
2005 | static int sis900_nway_reset(struct net_device *net_dev) | ||
2006 | { | ||
2007 | struct sis900_private *sis_priv = net_dev->priv; | ||
2008 | return mii_nway_restart(&sis_priv->mii_info); | ||
2009 | } | ||
2010 | |||
1969 | static struct ethtool_ops sis900_ethtool_ops = { | 2011 | static struct ethtool_ops sis900_ethtool_ops = { |
1970 | .get_drvinfo = sis900_get_drvinfo, | 2012 | .get_drvinfo = sis900_get_drvinfo, |
1971 | .get_msglevel = sis900_get_msglevel, | 2013 | .get_msglevel = sis900_get_msglevel, |
1972 | .set_msglevel = sis900_set_msglevel, | 2014 | .set_msglevel = sis900_set_msglevel, |
2015 | .get_link = sis900_get_link, | ||
2016 | .get_settings = sis900_get_settings, | ||
2017 | .set_settings = sis900_set_settings, | ||
2018 | .nway_reset = sis900_nway_reset, | ||
1973 | }; | 2019 | }; |
1974 | 2020 | ||
1975 | /** | 2021 | /** |
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index f79b02e80e75..f10dd74988c4 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -61,8 +61,8 @@ | |||
61 | 61 | ||
62 | #define DRV_MODULE_NAME "tg3" | 62 | #define DRV_MODULE_NAME "tg3" |
63 | #define PFX DRV_MODULE_NAME ": " | 63 | #define PFX DRV_MODULE_NAME ": " |
64 | #define DRV_MODULE_VERSION "3.27" | 64 | #define DRV_MODULE_VERSION "3.29" |
65 | #define DRV_MODULE_RELDATE "May 5, 2005" | 65 | #define DRV_MODULE_RELDATE "May 23, 2005" |
66 | 66 | ||
67 | #define TG3_DEF_MAC_MODE 0 | 67 | #define TG3_DEF_MAC_MODE 0 |
68 | #define TG3_DEF_RX_MODE 0 | 68 | #define TG3_DEF_RX_MODE 0 |
@@ -206,6 +206,8 @@ static struct pci_device_id tg3_pci_tbl[] = { | |||
206 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, | 206 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, |
207 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752, | 207 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752, |
208 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, | 208 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, |
209 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M, | ||
210 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, | ||
209 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753, | 211 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753, |
210 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, | 212 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, |
211 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M, | 213 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M, |
@@ -420,7 +422,8 @@ static void tg3_enable_ints(struct tg3 *tp) | |||
420 | { | 422 | { |
421 | tw32(TG3PCI_MISC_HOST_CTRL, | 423 | tw32(TG3PCI_MISC_HOST_CTRL, |
422 | (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); | 424 | (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); |
423 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000000); | 425 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, |
426 | (tp->last_tag << 24)); | ||
424 | tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW); | 427 | tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW); |
425 | 428 | ||
426 | tg3_cond_int(tp); | 429 | tg3_cond_int(tp); |
@@ -455,10 +458,16 @@ static void tg3_restart_ints(struct tg3 *tp) | |||
455 | { | 458 | { |
456 | tw32(TG3PCI_MISC_HOST_CTRL, | 459 | tw32(TG3PCI_MISC_HOST_CTRL, |
457 | (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); | 460 | (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); |
458 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000000); | 461 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, |
462 | tp->last_tag << 24); | ||
459 | mmiowb(); | 463 | mmiowb(); |
460 | 464 | ||
461 | if (tg3_has_work(tp)) | 465 | /* When doing tagged status, this work check is unnecessary. |
466 | * The last_tag we write above tells the chip which piece of | ||
467 | * work we've completed. | ||
468 | */ | ||
469 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) && | ||
470 | tg3_has_work(tp)) | ||
462 | tw32(HOSTCC_MODE, tp->coalesce_mode | | 471 | tw32(HOSTCC_MODE, tp->coalesce_mode | |
463 | (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW)); | 472 | (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW)); |
464 | } | 473 | } |
@@ -2500,7 +2509,7 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset) | |||
2500 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | 2509 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { |
2501 | if (netif_carrier_ok(tp->dev)) { | 2510 | if (netif_carrier_ok(tp->dev)) { |
2502 | tw32(HOSTCC_STAT_COAL_TICKS, | 2511 | tw32(HOSTCC_STAT_COAL_TICKS, |
2503 | DEFAULT_STAT_COAL_TICKS); | 2512 | tp->coal.stats_block_coalesce_usecs); |
2504 | } else { | 2513 | } else { |
2505 | tw32(HOSTCC_STAT_COAL_TICKS, 0); | 2514 | tw32(HOSTCC_STAT_COAL_TICKS, 0); |
2506 | } | 2515 | } |
@@ -2886,7 +2895,6 @@ static int tg3_poll(struct net_device *netdev, int *budget) | |||
2886 | * All RX "locking" is done by ensuring outside | 2895 | * All RX "locking" is done by ensuring outside |
2887 | * code synchronizes with dev->poll() | 2896 | * code synchronizes with dev->poll() |
2888 | */ | 2897 | */ |
2889 | done = 1; | ||
2890 | if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) { | 2898 | if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) { |
2891 | int orig_budget = *budget; | 2899 | int orig_budget = *budget; |
2892 | int work_done; | 2900 | int work_done; |
@@ -2898,12 +2906,14 @@ static int tg3_poll(struct net_device *netdev, int *budget) | |||
2898 | 2906 | ||
2899 | *budget -= work_done; | 2907 | *budget -= work_done; |
2900 | netdev->quota -= work_done; | 2908 | netdev->quota -= work_done; |
2901 | |||
2902 | if (work_done >= orig_budget) | ||
2903 | done = 0; | ||
2904 | } | 2909 | } |
2905 | 2910 | ||
2911 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) | ||
2912 | tp->last_tag = sblk->status_tag; | ||
2913 | rmb(); | ||
2914 | |||
2906 | /* if no more work, tell net stack and NIC we're done */ | 2915 | /* if no more work, tell net stack and NIC we're done */ |
2916 | done = !tg3_has_work(tp); | ||
2907 | if (done) { | 2917 | if (done) { |
2908 | spin_lock_irqsave(&tp->lock, flags); | 2918 | spin_lock_irqsave(&tp->lock, flags); |
2909 | __netif_rx_complete(netdev); | 2919 | __netif_rx_complete(netdev); |
@@ -2928,22 +2938,21 @@ static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs) | |||
2928 | spin_lock_irqsave(&tp->lock, flags); | 2938 | spin_lock_irqsave(&tp->lock, flags); |
2929 | 2939 | ||
2930 | /* | 2940 | /* |
2931 | * writing any value to intr-mbox-0 clears PCI INTA# and | 2941 | * Writing any value to intr-mbox-0 clears PCI INTA# and |
2932 | * chip-internal interrupt pending events. | 2942 | * chip-internal interrupt pending events. |
2933 | * writing non-zero to intr-mbox-0 additional tells the | 2943 | * Writing non-zero to intr-mbox-0 additional tells the |
2934 | * NIC to stop sending us irqs, engaging "in-intr-handler" | 2944 | * NIC to stop sending us irqs, engaging "in-intr-handler" |
2935 | * event coalescing. | 2945 | * event coalescing. |
2936 | */ | 2946 | */ |
2937 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); | 2947 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
2948 | tp->last_tag = sblk->status_tag; | ||
2938 | sblk->status &= ~SD_STATUS_UPDATED; | 2949 | sblk->status &= ~SD_STATUS_UPDATED; |
2939 | |||
2940 | if (likely(tg3_has_work(tp))) | 2950 | if (likely(tg3_has_work(tp))) |
2941 | netif_rx_schedule(dev); /* schedule NAPI poll */ | 2951 | netif_rx_schedule(dev); /* schedule NAPI poll */ |
2942 | else { | 2952 | else { |
2943 | /* no work, re-enable interrupts | 2953 | /* No work, re-enable interrupts. */ |
2944 | */ | ||
2945 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | 2954 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, |
2946 | 0x00000000); | 2955 | tp->last_tag << 24); |
2947 | } | 2956 | } |
2948 | 2957 | ||
2949 | spin_unlock_irqrestore(&tp->lock, flags); | 2958 | spin_unlock_irqrestore(&tp->lock, flags); |
@@ -2969,21 +2978,62 @@ static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |||
2969 | if ((sblk->status & SD_STATUS_UPDATED) || | 2978 | if ((sblk->status & SD_STATUS_UPDATED) || |
2970 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | 2979 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { |
2971 | /* | 2980 | /* |
2972 | * writing any value to intr-mbox-0 clears PCI INTA# and | 2981 | * Writing any value to intr-mbox-0 clears PCI INTA# and |
2973 | * chip-internal interrupt pending events. | 2982 | * chip-internal interrupt pending events. |
2974 | * writing non-zero to intr-mbox-0 additional tells the | 2983 | * Writing non-zero to intr-mbox-0 additional tells the |
2975 | * NIC to stop sending us irqs, engaging "in-intr-handler" | 2984 | * NIC to stop sending us irqs, engaging "in-intr-handler" |
2976 | * event coalescing. | 2985 | * event coalescing. |
2977 | */ | 2986 | */ |
2978 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | 2987 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, |
2979 | 0x00000001); | 2988 | 0x00000001); |
2989 | sblk->status &= ~SD_STATUS_UPDATED; | ||
2990 | if (likely(tg3_has_work(tp))) | ||
2991 | netif_rx_schedule(dev); /* schedule NAPI poll */ | ||
2992 | else { | ||
2993 | /* No work, shared interrupt perhaps? re-enable | ||
2994 | * interrupts, and flush that PCI write | ||
2995 | */ | ||
2996 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | ||
2997 | 0x00000000); | ||
2998 | tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW); | ||
2999 | } | ||
3000 | } else { /* shared interrupt */ | ||
3001 | handled = 0; | ||
3002 | } | ||
3003 | |||
3004 | spin_unlock_irqrestore(&tp->lock, flags); | ||
3005 | |||
3006 | return IRQ_RETVAL(handled); | ||
3007 | } | ||
3008 | |||
3009 | static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs *regs) | ||
3010 | { | ||
3011 | struct net_device *dev = dev_id; | ||
3012 | struct tg3 *tp = netdev_priv(dev); | ||
3013 | struct tg3_hw_status *sblk = tp->hw_status; | ||
3014 | unsigned long flags; | ||
3015 | unsigned int handled = 1; | ||
3016 | |||
3017 | spin_lock_irqsave(&tp->lock, flags); | ||
3018 | |||
3019 | /* In INTx mode, it is possible for the interrupt to arrive at | ||
3020 | * the CPU before the status block posted prior to the interrupt. | ||
3021 | * Reading the PCI State register will confirm whether the | ||
3022 | * interrupt is ours and will flush the status block. | ||
3023 | */ | ||
3024 | if ((sblk->status & SD_STATUS_UPDATED) || | ||
3025 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | ||
2980 | /* | 3026 | /* |
2981 | * Flush PCI write. This also guarantees that our | 3027 | * writing any value to intr-mbox-0 clears PCI INTA# and |
2982 | * status block has been flushed to host memory. | 3028 | * chip-internal interrupt pending events. |
3029 | * writing non-zero to intr-mbox-0 additional tells the | ||
3030 | * NIC to stop sending us irqs, engaging "in-intr-handler" | ||
3031 | * event coalescing. | ||
2983 | */ | 3032 | */ |
2984 | tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW); | 3033 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, |
3034 | 0x00000001); | ||
3035 | tp->last_tag = sblk->status_tag; | ||
2985 | sblk->status &= ~SD_STATUS_UPDATED; | 3036 | sblk->status &= ~SD_STATUS_UPDATED; |
2986 | |||
2987 | if (likely(tg3_has_work(tp))) | 3037 | if (likely(tg3_has_work(tp))) |
2988 | netif_rx_schedule(dev); /* schedule NAPI poll */ | 3038 | netif_rx_schedule(dev); /* schedule NAPI poll */ |
2989 | else { | 3039 | else { |
@@ -2991,7 +3041,7 @@ static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |||
2991 | * interrupts, and flush that PCI write | 3041 | * interrupts, and flush that PCI write |
2992 | */ | 3042 | */ |
2993 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | 3043 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, |
2994 | 0x00000000); | 3044 | tp->last_tag << 24); |
2995 | tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW); | 3045 | tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW); |
2996 | } | 3046 | } |
2997 | } else { /* shared interrupt */ | 3047 | } else { /* shared interrupt */ |
@@ -5044,6 +5094,27 @@ static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, | |||
5044 | } | 5094 | } |
5045 | 5095 | ||
5046 | static void __tg3_set_rx_mode(struct net_device *); | 5096 | static void __tg3_set_rx_mode(struct net_device *); |
5097 | static void tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) | ||
5098 | { | ||
5099 | tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); | ||
5100 | tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); | ||
5101 | tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); | ||
5102 | tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); | ||
5103 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | ||
5104 | tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); | ||
5105 | tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); | ||
5106 | } | ||
5107 | tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); | ||
5108 | tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); | ||
5109 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | ||
5110 | u32 val = ec->stats_block_coalesce_usecs; | ||
5111 | |||
5112 | if (!netif_carrier_ok(tp->dev)) | ||
5113 | val = 0; | ||
5114 | |||
5115 | tw32(HOSTCC_STAT_COAL_TICKS, val); | ||
5116 | } | ||
5117 | } | ||
5047 | 5118 | ||
5048 | /* tp->lock is held. */ | 5119 | /* tp->lock is held. */ |
5049 | static int tg3_reset_hw(struct tg3 *tp) | 5120 | static int tg3_reset_hw(struct tg3 *tp) |
@@ -5366,16 +5437,7 @@ static int tg3_reset_hw(struct tg3 *tp) | |||
5366 | udelay(10); | 5437 | udelay(10); |
5367 | } | 5438 | } |
5368 | 5439 | ||
5369 | tw32(HOSTCC_RXCOL_TICKS, 0); | 5440 | tg3_set_coalesce(tp, &tp->coal); |
5370 | tw32(HOSTCC_TXCOL_TICKS, LOW_TXCOL_TICKS); | ||
5371 | tw32(HOSTCC_RXMAX_FRAMES, 1); | ||
5372 | tw32(HOSTCC_TXMAX_FRAMES, LOW_RXMAX_FRAMES); | ||
5373 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | ||
5374 | tw32(HOSTCC_RXCOAL_TICK_INT, 0); | ||
5375 | tw32(HOSTCC_TXCOAL_TICK_INT, 0); | ||
5376 | } | ||
5377 | tw32(HOSTCC_RXCOAL_MAXF_INT, 1); | ||
5378 | tw32(HOSTCC_TXCOAL_MAXF_INT, 0); | ||
5379 | 5441 | ||
5380 | /* set status block DMA address */ | 5442 | /* set status block DMA address */ |
5381 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, | 5443 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, |
@@ -5388,8 +5450,6 @@ static int tg3_reset_hw(struct tg3 *tp) | |||
5388 | * the tg3_periodic_fetch_stats call there, and | 5450 | * the tg3_periodic_fetch_stats call there, and |
5389 | * tg3_get_stats to see how this works for 5705/5750 chips. | 5451 | * tg3_get_stats to see how this works for 5705/5750 chips. |
5390 | */ | 5452 | */ |
5391 | tw32(HOSTCC_STAT_COAL_TICKS, | ||
5392 | DEFAULT_STAT_COAL_TICKS); | ||
5393 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, | 5453 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, |
5394 | ((u64) tp->stats_mapping >> 32)); | 5454 | ((u64) tp->stats_mapping >> 32)); |
5395 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | 5455 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, |
@@ -5445,7 +5505,8 @@ static int tg3_reset_hw(struct tg3 *tp) | |||
5445 | udelay(100); | 5505 | udelay(100); |
5446 | 5506 | ||
5447 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0); | 5507 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0); |
5448 | tr32(MAILBOX_INTERRUPT_0); | 5508 | tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW); |
5509 | tp->last_tag = 0; | ||
5449 | 5510 | ||
5450 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | 5511 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { |
5451 | tw32_f(DMAC_MODE, DMAC_MODE_ENABLE); | 5512 | tw32_f(DMAC_MODE, DMAC_MODE_ENABLE); |
@@ -5723,31 +5784,33 @@ static void tg3_timer(unsigned long __opaque) | |||
5723 | spin_lock_irqsave(&tp->lock, flags); | 5784 | spin_lock_irqsave(&tp->lock, flags); |
5724 | spin_lock(&tp->tx_lock); | 5785 | spin_lock(&tp->tx_lock); |
5725 | 5786 | ||
5726 | /* All of this garbage is because when using non-tagged | 5787 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) { |
5727 | * IRQ status the mailbox/status_block protocol the chip | 5788 | /* All of this garbage is because when using non-tagged |
5728 | * uses with the cpu is race prone. | 5789 | * IRQ status the mailbox/status_block protocol the chip |
5729 | */ | 5790 | * uses with the cpu is race prone. |
5730 | if (tp->hw_status->status & SD_STATUS_UPDATED) { | 5791 | */ |
5731 | tw32(GRC_LOCAL_CTRL, | 5792 | if (tp->hw_status->status & SD_STATUS_UPDATED) { |
5732 | tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | 5793 | tw32(GRC_LOCAL_CTRL, |
5733 | } else { | 5794 | tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); |
5734 | tw32(HOSTCC_MODE, tp->coalesce_mode | | 5795 | } else { |
5735 | (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW)); | 5796 | tw32(HOSTCC_MODE, tp->coalesce_mode | |
5736 | } | 5797 | (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW)); |
5798 | } | ||
5737 | 5799 | ||
5738 | if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { | 5800 | if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { |
5739 | tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER; | 5801 | tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER; |
5740 | spin_unlock(&tp->tx_lock); | 5802 | spin_unlock(&tp->tx_lock); |
5741 | spin_unlock_irqrestore(&tp->lock, flags); | 5803 | spin_unlock_irqrestore(&tp->lock, flags); |
5742 | schedule_work(&tp->reset_task); | 5804 | schedule_work(&tp->reset_task); |
5743 | return; | 5805 | return; |
5806 | } | ||
5744 | } | 5807 | } |
5745 | 5808 | ||
5746 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) | ||
5747 | tg3_periodic_fetch_stats(tp); | ||
5748 | |||
5749 | /* This part only runs once per second. */ | 5809 | /* This part only runs once per second. */ |
5750 | if (!--tp->timer_counter) { | 5810 | if (!--tp->timer_counter) { |
5811 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) | ||
5812 | tg3_periodic_fetch_stats(tp); | ||
5813 | |||
5751 | if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) { | 5814 | if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) { |
5752 | u32 mac_stat; | 5815 | u32 mac_stat; |
5753 | int phy_event; | 5816 | int phy_event; |
@@ -5846,9 +5909,13 @@ static int tg3_test_interrupt(struct tg3 *tp) | |||
5846 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) | 5909 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) |
5847 | err = request_irq(tp->pdev->irq, tg3_msi, | 5910 | err = request_irq(tp->pdev->irq, tg3_msi, |
5848 | SA_SAMPLE_RANDOM, dev->name, dev); | 5911 | SA_SAMPLE_RANDOM, dev->name, dev); |
5849 | else | 5912 | else { |
5850 | err = request_irq(tp->pdev->irq, tg3_interrupt, | 5913 | irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt; |
5914 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) | ||
5915 | fn = tg3_interrupt_tagged; | ||
5916 | err = request_irq(tp->pdev->irq, fn, | ||
5851 | SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev); | 5917 | SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev); |
5918 | } | ||
5852 | 5919 | ||
5853 | if (err) | 5920 | if (err) |
5854 | return err; | 5921 | return err; |
@@ -5900,9 +5967,14 @@ static int tg3_test_msi(struct tg3 *tp) | |||
5900 | 5967 | ||
5901 | tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI; | 5968 | tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI; |
5902 | 5969 | ||
5903 | err = request_irq(tp->pdev->irq, tg3_interrupt, | 5970 | { |
5904 | SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev); | 5971 | irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt; |
5972 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) | ||
5973 | fn = tg3_interrupt_tagged; | ||
5905 | 5974 | ||
5975 | err = request_irq(tp->pdev->irq, fn, | ||
5976 | SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev); | ||
5977 | } | ||
5906 | if (err) | 5978 | if (err) |
5907 | return err; | 5979 | return err; |
5908 | 5980 | ||
@@ -5948,7 +6020,13 @@ static int tg3_open(struct net_device *dev) | |||
5948 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | 6020 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && |
5949 | (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) && | 6021 | (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) && |
5950 | (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX)) { | 6022 | (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX)) { |
5951 | if (pci_enable_msi(tp->pdev) == 0) { | 6023 | /* All MSI supporting chips should support tagged |
6024 | * status. Assert that this is the case. | ||
6025 | */ | ||
6026 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) { | ||
6027 | printk(KERN_WARNING PFX "%s: MSI without TAGGED? " | ||
6028 | "Not using MSI.\n", tp->dev->name); | ||
6029 | } else if (pci_enable_msi(tp->pdev) == 0) { | ||
5952 | u32 msi_mode; | 6030 | u32 msi_mode; |
5953 | 6031 | ||
5954 | msi_mode = tr32(MSGINT_MODE); | 6032 | msi_mode = tr32(MSGINT_MODE); |
@@ -5959,9 +6037,14 @@ static int tg3_open(struct net_device *dev) | |||
5959 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) | 6037 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) |
5960 | err = request_irq(tp->pdev->irq, tg3_msi, | 6038 | err = request_irq(tp->pdev->irq, tg3_msi, |
5961 | SA_SAMPLE_RANDOM, dev->name, dev); | 6039 | SA_SAMPLE_RANDOM, dev->name, dev); |
5962 | else | 6040 | else { |
5963 | err = request_irq(tp->pdev->irq, tg3_interrupt, | 6041 | irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt; |
6042 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) | ||
6043 | fn = tg3_interrupt_tagged; | ||
6044 | |||
6045 | err = request_irq(tp->pdev->irq, fn, | ||
5964 | SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev); | 6046 | SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev); |
6047 | } | ||
5965 | 6048 | ||
5966 | if (err) { | 6049 | if (err) { |
5967 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { | 6050 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { |
@@ -5980,9 +6063,16 @@ static int tg3_open(struct net_device *dev) | |||
5980 | tg3_halt(tp, 1); | 6063 | tg3_halt(tp, 1); |
5981 | tg3_free_rings(tp); | 6064 | tg3_free_rings(tp); |
5982 | } else { | 6065 | } else { |
5983 | tp->timer_offset = HZ / 10; | 6066 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) |
5984 | tp->timer_counter = tp->timer_multiplier = 10; | 6067 | tp->timer_offset = HZ; |
5985 | tp->asf_counter = tp->asf_multiplier = (10 * 120); | 6068 | else |
6069 | tp->timer_offset = HZ / 10; | ||
6070 | |||
6071 | BUG_ON(tp->timer_offset > HZ); | ||
6072 | tp->timer_counter = tp->timer_multiplier = | ||
6073 | (HZ / tp->timer_offset); | ||
6074 | tp->asf_counter = tp->asf_multiplier = | ||
6075 | ((HZ / tp->timer_offset) * 120); | ||
5986 | 6076 | ||
5987 | init_timer(&tp->timer); | 6077 | init_timer(&tp->timer); |
5988 | tp->timer.expires = jiffies + tp->timer_offset; | 6078 | tp->timer.expires = jiffies + tp->timer_offset; |
@@ -6005,6 +6095,7 @@ static int tg3_open(struct net_device *dev) | |||
6005 | 6095 | ||
6006 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { | 6096 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { |
6007 | err = tg3_test_msi(tp); | 6097 | err = tg3_test_msi(tp); |
6098 | |||
6008 | if (err) { | 6099 | if (err) { |
6009 | spin_lock_irq(&tp->lock); | 6100 | spin_lock_irq(&tp->lock); |
6010 | spin_lock(&tp->tx_lock); | 6101 | spin_lock(&tp->tx_lock); |
@@ -7203,6 +7294,14 @@ static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) | |||
7203 | } | 7294 | } |
7204 | #endif | 7295 | #endif |
7205 | 7296 | ||
7297 | static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) | ||
7298 | { | ||
7299 | struct tg3 *tp = netdev_priv(dev); | ||
7300 | |||
7301 | memcpy(ec, &tp->coal, sizeof(*ec)); | ||
7302 | return 0; | ||
7303 | } | ||
7304 | |||
7206 | static struct ethtool_ops tg3_ethtool_ops = { | 7305 | static struct ethtool_ops tg3_ethtool_ops = { |
7207 | .get_settings = tg3_get_settings, | 7306 | .get_settings = tg3_get_settings, |
7208 | .set_settings = tg3_set_settings, | 7307 | .set_settings = tg3_set_settings, |
@@ -7235,6 +7334,7 @@ static struct ethtool_ops tg3_ethtool_ops = { | |||
7235 | .get_strings = tg3_get_strings, | 7334 | .get_strings = tg3_get_strings, |
7236 | .get_stats_count = tg3_get_stats_count, | 7335 | .get_stats_count = tg3_get_stats_count, |
7237 | .get_ethtool_stats = tg3_get_ethtool_stats, | 7336 | .get_ethtool_stats = tg3_get_ethtool_stats, |
7337 | .get_coalesce = tg3_get_coalesce, | ||
7238 | }; | 7338 | }; |
7239 | 7339 | ||
7240 | static void __devinit tg3_get_eeprom_size(struct tg3 *tp) | 7340 | static void __devinit tg3_get_eeprom_size(struct tg3 *tp) |
@@ -8422,15 +8522,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) | |||
8422 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) | 8522 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) |
8423 | tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG; | 8523 | tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG; |
8424 | 8524 | ||
8425 | /* Only 5701 and later support tagged irq status mode. | ||
8426 | * Also, 5788 chips cannot use tagged irq status. | ||
8427 | * | ||
8428 | * However, since we are using NAPI avoid tagged irq status | ||
8429 | * because the interrupt condition is more difficult to | ||
8430 | * fully clear in that mode. | ||
8431 | */ | ||
8432 | tp->coalesce_mode = 0; | 8525 | tp->coalesce_mode = 0; |
8433 | |||
8434 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX && | 8526 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX && |
8435 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) | 8527 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) |
8436 | tp->coalesce_mode |= HOSTCC_MODE_32BYTE; | 8528 | tp->coalesce_mode |= HOSTCC_MODE_32BYTE; |
@@ -8494,6 +8586,18 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) | |||
8494 | grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M)) | 8586 | grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M)) |
8495 | tp->tg3_flags2 |= TG3_FLG2_IS_5788; | 8587 | tp->tg3_flags2 |= TG3_FLG2_IS_5788; |
8496 | 8588 | ||
8589 | if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) && | ||
8590 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)) | ||
8591 | tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS; | ||
8592 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) { | ||
8593 | tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | | ||
8594 | HOSTCC_MODE_CLRTICK_TXBD); | ||
8595 | |||
8596 | tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; | ||
8597 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | ||
8598 | tp->misc_host_ctrl); | ||
8599 | } | ||
8600 | |||
8497 | /* these are limited to 10/100 only */ | 8601 | /* these are limited to 10/100 only */ |
8498 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && | 8602 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && |
8499 | (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || | 8603 | (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || |
@@ -8671,6 +8775,146 @@ static int __devinit tg3_get_device_address(struct tg3 *tp) | |||
8671 | return 0; | 8775 | return 0; |
8672 | } | 8776 | } |
8673 | 8777 | ||
8778 | #define BOUNDARY_SINGLE_CACHELINE 1 | ||
8779 | #define BOUNDARY_MULTI_CACHELINE 2 | ||
8780 | |||
8781 | static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) | ||
8782 | { | ||
8783 | int cacheline_size; | ||
8784 | u8 byte; | ||
8785 | int goal; | ||
8786 | |||
8787 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); | ||
8788 | if (byte == 0) | ||
8789 | cacheline_size = 1024; | ||
8790 | else | ||
8791 | cacheline_size = (int) byte * 4; | ||
8792 | |||
8793 | /* On 5703 and later chips, the boundary bits have no | ||
8794 | * effect. | ||
8795 | */ | ||
8796 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | ||
8797 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | ||
8798 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | ||
8799 | goto out; | ||
8800 | |||
8801 | #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC) | ||
8802 | goal = BOUNDARY_MULTI_CACHELINE; | ||
8803 | #else | ||
8804 | #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA) | ||
8805 | goal = BOUNDARY_SINGLE_CACHELINE; | ||
8806 | #else | ||
8807 | goal = 0; | ||
8808 | #endif | ||
8809 | #endif | ||
8810 | |||
8811 | if (!goal) | ||
8812 | goto out; | ||
8813 | |||
8814 | /* PCI controllers on most RISC systems tend to disconnect | ||
8815 | * when a device tries to burst across a cache-line boundary. | ||
8816 | * Therefore, letting tg3 do so just wastes PCI bandwidth. | ||
8817 | * | ||
8818 | * Unfortunately, for PCI-E there are only limited | ||
8819 | * write-side controls for this, and thus for reads | ||
8820 | * we will still get the disconnects. We'll also waste | ||
8821 | * these PCI cycles for both read and write for chips | ||
8822 | * other than 5700 and 5701 which do not implement the | ||
8823 | * boundary bits. | ||
8824 | */ | ||
8825 | if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) && | ||
8826 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) { | ||
8827 | switch (cacheline_size) { | ||
8828 | case 16: | ||
8829 | case 32: | ||
8830 | case 64: | ||
8831 | case 128: | ||
8832 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | ||
8833 | val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX | | ||
8834 | DMA_RWCTRL_WRITE_BNDRY_128_PCIX); | ||
8835 | } else { | ||
8836 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | ||
8837 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | ||
8838 | } | ||
8839 | break; | ||
8840 | |||
8841 | case 256: | ||
8842 | val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX | | ||
8843 | DMA_RWCTRL_WRITE_BNDRY_256_PCIX); | ||
8844 | break; | ||
8845 | |||
8846 | default: | ||
8847 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | ||
8848 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | ||
8849 | break; | ||
8850 | }; | ||
8851 | } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | ||
8852 | switch (cacheline_size) { | ||
8853 | case 16: | ||
8854 | case 32: | ||
8855 | case 64: | ||
8856 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | ||
8857 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | ||
8858 | val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE; | ||
8859 | break; | ||
8860 | } | ||
8861 | /* fallthrough */ | ||
8862 | case 128: | ||
8863 | default: | ||
8864 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | ||
8865 | val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; | ||
8866 | break; | ||
8867 | }; | ||
8868 | } else { | ||
8869 | switch (cacheline_size) { | ||
8870 | case 16: | ||
8871 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | ||
8872 | val |= (DMA_RWCTRL_READ_BNDRY_16 | | ||
8873 | DMA_RWCTRL_WRITE_BNDRY_16); | ||
8874 | break; | ||
8875 | } | ||
8876 | /* fallthrough */ | ||
8877 | case 32: | ||
8878 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | ||
8879 | val |= (DMA_RWCTRL_READ_BNDRY_32 | | ||
8880 | DMA_RWCTRL_WRITE_BNDRY_32); | ||
8881 | break; | ||
8882 | } | ||
8883 | /* fallthrough */ | ||
8884 | case 64: | ||
8885 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | ||
8886 | val |= (DMA_RWCTRL_READ_BNDRY_64 | | ||
8887 | DMA_RWCTRL_WRITE_BNDRY_64); | ||
8888 | break; | ||
8889 | } | ||
8890 | /* fallthrough */ | ||
8891 | case 128: | ||
8892 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | ||
8893 | val |= (DMA_RWCTRL_READ_BNDRY_128 | | ||
8894 | DMA_RWCTRL_WRITE_BNDRY_128); | ||
8895 | break; | ||
8896 | } | ||
8897 | /* fallthrough */ | ||
8898 | case 256: | ||
8899 | val |= (DMA_RWCTRL_READ_BNDRY_256 | | ||
8900 | DMA_RWCTRL_WRITE_BNDRY_256); | ||
8901 | break; | ||
8902 | case 512: | ||
8903 | val |= (DMA_RWCTRL_READ_BNDRY_512 | | ||
8904 | DMA_RWCTRL_WRITE_BNDRY_512); | ||
8905 | break; | ||
8906 | case 1024: | ||
8907 | default: | ||
8908 | val |= (DMA_RWCTRL_READ_BNDRY_1024 | | ||
8909 | DMA_RWCTRL_WRITE_BNDRY_1024); | ||
8910 | break; | ||
8911 | }; | ||
8912 | } | ||
8913 | |||
8914 | out: | ||
8915 | return val; | ||
8916 | } | ||
8917 | |||
8674 | static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device) | 8918 | static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device) |
8675 | { | 8919 | { |
8676 | struct tg3_internal_buffer_desc test_desc; | 8920 | struct tg3_internal_buffer_desc test_desc; |
@@ -8752,12 +8996,12 @@ static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dm | |||
8752 | return ret; | 8996 | return ret; |
8753 | } | 8997 | } |
8754 | 8998 | ||
8755 | #define TEST_BUFFER_SIZE 0x400 | 8999 | #define TEST_BUFFER_SIZE 0x2000 |
8756 | 9000 | ||
8757 | static int __devinit tg3_test_dma(struct tg3 *tp) | 9001 | static int __devinit tg3_test_dma(struct tg3 *tp) |
8758 | { | 9002 | { |
8759 | dma_addr_t buf_dma; | 9003 | dma_addr_t buf_dma; |
8760 | u32 *buf; | 9004 | u32 *buf, saved_dma_rwctrl; |
8761 | int ret; | 9005 | int ret; |
8762 | 9006 | ||
8763 | buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma); | 9007 | buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma); |
@@ -8769,46 +9013,7 @@ static int __devinit tg3_test_dma(struct tg3 *tp) | |||
8769 | tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | | 9013 | tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | |
8770 | (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT)); | 9014 | (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT)); |
8771 | 9015 | ||
8772 | #ifndef CONFIG_X86 | 9016 | tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); |
8773 | { | ||
8774 | u8 byte; | ||
8775 | int cacheline_size; | ||
8776 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); | ||
8777 | |||
8778 | if (byte == 0) | ||
8779 | cacheline_size = 1024; | ||
8780 | else | ||
8781 | cacheline_size = (int) byte * 4; | ||
8782 | |||
8783 | switch (cacheline_size) { | ||
8784 | case 16: | ||
8785 | case 32: | ||
8786 | case 64: | ||
8787 | case 128: | ||
8788 | if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) && | ||
8789 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) { | ||
8790 | tp->dma_rwctrl |= | ||
8791 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX; | ||
8792 | break; | ||
8793 | } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | ||
8794 | tp->dma_rwctrl &= | ||
8795 | ~(DMA_RWCTRL_PCI_WRITE_CMD); | ||
8796 | tp->dma_rwctrl |= | ||
8797 | DMA_RWCTRL_WRITE_BNDRY_128_PCIE; | ||
8798 | break; | ||
8799 | } | ||
8800 | /* fallthrough */ | ||
8801 | case 256: | ||
8802 | if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE) && | ||
8803 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | ||
8804 | tp->dma_rwctrl |= | ||
8805 | DMA_RWCTRL_WRITE_BNDRY_256; | ||
8806 | else if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | ||
8807 | tp->dma_rwctrl |= | ||
8808 | DMA_RWCTRL_WRITE_BNDRY_256_PCIX; | ||
8809 | }; | ||
8810 | } | ||
8811 | #endif | ||
8812 | 9017 | ||
8813 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | 9018 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { |
8814 | /* DMA read watermark not used on PCIE */ | 9019 | /* DMA read watermark not used on PCIE */ |
@@ -8827,7 +9032,7 @@ static int __devinit tg3_test_dma(struct tg3 *tp) | |||
8827 | if (ccval == 0x6 || ccval == 0x7) | 9032 | if (ccval == 0x6 || ccval == 0x7) |
8828 | tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; | 9033 | tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; |
8829 | 9034 | ||
8830 | /* Set bit 23 to renable PCIX hw bug fix */ | 9035 | /* Set bit 23 to enable PCIX hw bug fix */ |
8831 | tp->dma_rwctrl |= 0x009f0000; | 9036 | tp->dma_rwctrl |= 0x009f0000; |
8832 | } else { | 9037 | } else { |
8833 | tp->dma_rwctrl |= 0x001b000f; | 9038 | tp->dma_rwctrl |= 0x001b000f; |
@@ -8868,6 +9073,13 @@ static int __devinit tg3_test_dma(struct tg3 *tp) | |||
8868 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) | 9073 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) |
8869 | goto out; | 9074 | goto out; |
8870 | 9075 | ||
9076 | /* It is best to perform DMA test with maximum write burst size | ||
9077 | * to expose the 5700/5701 write DMA bug. | ||
9078 | */ | ||
9079 | saved_dma_rwctrl = tp->dma_rwctrl; | ||
9080 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | ||
9081 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | ||
9082 | |||
8871 | while (1) { | 9083 | while (1) { |
8872 | u32 *p = buf, i; | 9084 | u32 *p = buf, i; |
8873 | 9085 | ||
@@ -8906,8 +9118,9 @@ static int __devinit tg3_test_dma(struct tg3 *tp) | |||
8906 | if (p[i] == i) | 9118 | if (p[i] == i) |
8907 | continue; | 9119 | continue; |
8908 | 9120 | ||
8909 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) == | 9121 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
8910 | DMA_RWCTRL_WRITE_BNDRY_DISAB) { | 9122 | DMA_RWCTRL_WRITE_BNDRY_16) { |
9123 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | ||
8911 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; | 9124 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; |
8912 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | 9125 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); |
8913 | break; | 9126 | break; |
@@ -8924,6 +9137,14 @@ static int __devinit tg3_test_dma(struct tg3 *tp) | |||
8924 | break; | 9137 | break; |
8925 | } | 9138 | } |
8926 | } | 9139 | } |
9140 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != | ||
9141 | DMA_RWCTRL_WRITE_BNDRY_16) { | ||
9142 | /* DMA test passed without adjusting DMA boundary, | ||
9143 | * just restore the calculated DMA boundary | ||
9144 | */ | ||
9145 | tp->dma_rwctrl = saved_dma_rwctrl; | ||
9146 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | ||
9147 | } | ||
8927 | 9148 | ||
8928 | out: | 9149 | out: |
8929 | pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma); | 9150 | pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma); |
@@ -9011,6 +9232,31 @@ static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp) | |||
9011 | return peer; | 9232 | return peer; |
9012 | } | 9233 | } |
9013 | 9234 | ||
9235 | static void __devinit tg3_init_coal(struct tg3 *tp) | ||
9236 | { | ||
9237 | struct ethtool_coalesce *ec = &tp->coal; | ||
9238 | |||
9239 | memset(ec, 0, sizeof(*ec)); | ||
9240 | ec->cmd = ETHTOOL_GCOALESCE; | ||
9241 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; | ||
9242 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; | ||
9243 | ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; | ||
9244 | ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; | ||
9245 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; | ||
9246 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; | ||
9247 | ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; | ||
9248 | ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; | ||
9249 | ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; | ||
9250 | |||
9251 | if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | | ||
9252 | HOSTCC_MODE_CLRTICK_TXBD)) { | ||
9253 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; | ||
9254 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; | ||
9255 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; | ||
9256 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; | ||
9257 | } | ||
9258 | } | ||
9259 | |||
9014 | static int __devinit tg3_init_one(struct pci_dev *pdev, | 9260 | static int __devinit tg3_init_one(struct pci_dev *pdev, |
9015 | const struct pci_device_id *ent) | 9261 | const struct pci_device_id *ent) |
9016 | { | 9262 | { |
@@ -9256,6 +9502,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev, | |||
9256 | /* flow control autonegotiation is default behavior */ | 9502 | /* flow control autonegotiation is default behavior */ |
9257 | tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; | 9503 | tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; |
9258 | 9504 | ||
9505 | tg3_init_coal(tp); | ||
9506 | |||
9259 | err = register_netdev(dev); | 9507 | err = register_netdev(dev); |
9260 | if (err) { | 9508 | if (err) { |
9261 | printk(KERN_ERR PFX "Cannot register net device, " | 9509 | printk(KERN_ERR PFX "Cannot register net device, " |
@@ -9298,6 +9546,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev, | |||
9298 | (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0, | 9546 | (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0, |
9299 | (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0, | 9547 | (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0, |
9300 | (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0); | 9548 | (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0); |
9549 | printk(KERN_INFO "%s: dma_rwctrl[%08x]\n", | ||
9550 | dev->name, tp->dma_rwctrl); | ||
9301 | 9551 | ||
9302 | return 0; | 9552 | return 0; |
9303 | 9553 | ||
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index 8de6f21037ba..993f84c93dc4 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h | |||
@@ -876,10 +876,12 @@ | |||
876 | #define HOSTCC_STATUS_ERROR_ATTN 0x00000004 | 876 | #define HOSTCC_STATUS_ERROR_ATTN 0x00000004 |
877 | #define HOSTCC_RXCOL_TICKS 0x00003c08 | 877 | #define HOSTCC_RXCOL_TICKS 0x00003c08 |
878 | #define LOW_RXCOL_TICKS 0x00000032 | 878 | #define LOW_RXCOL_TICKS 0x00000032 |
879 | #define LOW_RXCOL_TICKS_CLRTCKS 0x00000014 | ||
879 | #define DEFAULT_RXCOL_TICKS 0x00000048 | 880 | #define DEFAULT_RXCOL_TICKS 0x00000048 |
880 | #define HIGH_RXCOL_TICKS 0x00000096 | 881 | #define HIGH_RXCOL_TICKS 0x00000096 |
881 | #define HOSTCC_TXCOL_TICKS 0x00003c0c | 882 | #define HOSTCC_TXCOL_TICKS 0x00003c0c |
882 | #define LOW_TXCOL_TICKS 0x00000096 | 883 | #define LOW_TXCOL_TICKS 0x00000096 |
884 | #define LOW_TXCOL_TICKS_CLRTCKS 0x00000048 | ||
883 | #define DEFAULT_TXCOL_TICKS 0x0000012c | 885 | #define DEFAULT_TXCOL_TICKS 0x0000012c |
884 | #define HIGH_TXCOL_TICKS 0x00000145 | 886 | #define HIGH_TXCOL_TICKS 0x00000145 |
885 | #define HOSTCC_RXMAX_FRAMES 0x00003c10 | 887 | #define HOSTCC_RXMAX_FRAMES 0x00003c10 |
@@ -892,8 +894,10 @@ | |||
892 | #define HIGH_TXMAX_FRAMES 0x00000052 | 894 | #define HIGH_TXMAX_FRAMES 0x00000052 |
893 | #define HOSTCC_RXCOAL_TICK_INT 0x00003c18 | 895 | #define HOSTCC_RXCOAL_TICK_INT 0x00003c18 |
894 | #define DEFAULT_RXCOAL_TICK_INT 0x00000019 | 896 | #define DEFAULT_RXCOAL_TICK_INT 0x00000019 |
897 | #define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014 | ||
895 | #define HOSTCC_TXCOAL_TICK_INT 0x00003c1c | 898 | #define HOSTCC_TXCOAL_TICK_INT 0x00003c1c |
896 | #define DEFAULT_TXCOAL_TICK_INT 0x00000019 | 899 | #define DEFAULT_TXCOAL_TICK_INT 0x00000019 |
900 | #define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014 | ||
897 | #define HOSTCC_RXCOAL_MAXF_INT 0x00003c20 | 901 | #define HOSTCC_RXCOAL_MAXF_INT 0x00003c20 |
898 | #define DEFAULT_RXCOAL_MAXF_INT 0x00000005 | 902 | #define DEFAULT_RXCOAL_MAXF_INT 0x00000005 |
899 | #define HOSTCC_TXCOAL_MAXF_INT 0x00003c24 | 903 | #define HOSTCC_TXCOAL_MAXF_INT 0x00003c24 |
@@ -2023,6 +2027,7 @@ struct tg3 { | |||
2023 | 2027 | ||
2024 | struct tg3_hw_status *hw_status; | 2028 | struct tg3_hw_status *hw_status; |
2025 | dma_addr_t status_mapping; | 2029 | dma_addr_t status_mapping; |
2030 | u32 last_tag; | ||
2026 | 2031 | ||
2027 | u32 msg_enable; | 2032 | u32 msg_enable; |
2028 | 2033 | ||
@@ -2068,6 +2073,7 @@ struct tg3 { | |||
2068 | 2073 | ||
2069 | u32 rx_offset; | 2074 | u32 rx_offset; |
2070 | u32 tg3_flags; | 2075 | u32 tg3_flags; |
2076 | #define TG3_FLAG_TAGGED_STATUS 0x00000001 | ||
2071 | #define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002 | 2077 | #define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002 |
2072 | #define TG3_FLAG_RX_CHECKSUMS 0x00000004 | 2078 | #define TG3_FLAG_RX_CHECKSUMS 0x00000004 |
2073 | #define TG3_FLAG_USE_LINKCHG_REG 0x00000008 | 2079 | #define TG3_FLAG_USE_LINKCHG_REG 0x00000008 |
@@ -2225,7 +2231,7 @@ struct tg3 { | |||
2225 | 2231 | ||
2226 | #define SST_25VF0X0_PAGE_SIZE 4098 | 2232 | #define SST_25VF0X0_PAGE_SIZE 4098 |
2227 | 2233 | ||
2228 | 2234 | struct ethtool_coalesce coal; | |
2229 | }; | 2235 | }; |
2230 | 2236 | ||
2231 | #endif /* !(_T3_H) */ | 2237 | #endif /* !(_T3_H) */ |
diff --git a/drivers/net/tlan.c b/drivers/net/tlan.c index a7ffa64502dd..9680a308c62b 100644 --- a/drivers/net/tlan.c +++ b/drivers/net/tlan.c | |||
@@ -193,6 +193,12 @@ static int aui[MAX_TLAN_BOARDS]; | |||
193 | static int duplex[MAX_TLAN_BOARDS]; | 193 | static int duplex[MAX_TLAN_BOARDS]; |
194 | static int speed[MAX_TLAN_BOARDS]; | 194 | static int speed[MAX_TLAN_BOARDS]; |
195 | static int boards_found; | 195 | static int boards_found; |
196 | module_param_array(aui, int, NULL, 0); | ||
197 | module_param_array(duplex, int, NULL, 0); | ||
198 | module_param_array(speed, int, NULL, 0); | ||
199 | MODULE_PARM_DESC(aui, "ThunderLAN use AUI port(s) (0-1)"); | ||
200 | MODULE_PARM_DESC(duplex, "ThunderLAN duplex setting(s) (0-default, 1-half, 2-full)"); | ||
201 | MODULE_PARM_DESC(speed, "ThunderLAN port speen setting(s) (0,10,100)"); | ||
196 | 202 | ||
197 | MODULE_AUTHOR("Maintainer: Samuel Chessman <chessman@tux.org>"); | 203 | MODULE_AUTHOR("Maintainer: Samuel Chessman <chessman@tux.org>"); |
198 | MODULE_DESCRIPTION("Driver for TI ThunderLAN based ethernet PCI adapters"); | 204 | MODULE_DESCRIPTION("Driver for TI ThunderLAN based ethernet PCI adapters"); |
@@ -204,8 +210,13 @@ MODULE_LICENSE("GPL"); | |||
204 | 210 | ||
205 | /* Turn on debugging. See Documentation/networking/tlan.txt for details */ | 211 | /* Turn on debugging. See Documentation/networking/tlan.txt for details */ |
206 | static int debug; | 212 | static int debug; |
213 | module_param(debug, int, 0); | ||
214 | MODULE_PARM_DESC(debug, "ThunderLAN debug mask"); | ||
207 | 215 | ||
208 | static int bbuf; | 216 | static int bbuf; |
217 | module_param(bbuf, int, 0); | ||
218 | MODULE_PARM_DESC(bbuf, "ThunderLAN use big buffer (0-1)"); | ||
219 | |||
209 | static u8 *TLanPadBuffer; | 220 | static u8 *TLanPadBuffer; |
210 | static dma_addr_t TLanPadBufferDMA; | 221 | static dma_addr_t TLanPadBufferDMA; |
211 | static char TLanSignature[] = "TLAN"; | 222 | static char TLanSignature[] = "TLAN"; |
@@ -2381,6 +2392,7 @@ TLan_FinishReset( struct net_device *dev ) | |||
2381 | TLan_SetTimer( dev, (10*HZ), TLAN_TIMER_FINISH_RESET ); | 2392 | TLan_SetTimer( dev, (10*HZ), TLAN_TIMER_FINISH_RESET ); |
2382 | return; | 2393 | return; |
2383 | } | 2394 | } |
2395 | TLan_SetMulticastList(dev); | ||
2384 | 2396 | ||
2385 | } /* TLan_FinishReset */ | 2397 | } /* TLan_FinishReset */ |
2386 | 2398 | ||
diff --git a/drivers/net/tulip/media.c b/drivers/net/tulip/media.c index edae09a4b021..919c40cd635c 100644 --- a/drivers/net/tulip/media.c +++ b/drivers/net/tulip/media.c | |||
@@ -174,6 +174,7 @@ void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int val) | |||
174 | break; | 174 | break; |
175 | } | 175 | } |
176 | spin_unlock_irqrestore(&tp->mii_lock, flags); | 176 | spin_unlock_irqrestore(&tp->mii_lock, flags); |
177 | return; | ||
177 | } | 178 | } |
178 | 179 | ||
179 | /* Establish sync by sending 32 logic ones. */ | 180 | /* Establish sync by sending 32 logic ones. */ |
diff --git a/drivers/net/tulip/tulip_core.c b/drivers/net/tulip/tulip_core.c index d098b3ba3538..e0ae3ed6e578 100644 --- a/drivers/net/tulip/tulip_core.c +++ b/drivers/net/tulip/tulip_core.c | |||
@@ -1104,7 +1104,7 @@ static void set_rx_mode(struct net_device *dev) | |||
1104 | if (entry != 0) { | 1104 | if (entry != 0) { |
1105 | /* Avoid a chip errata by prefixing a dummy entry. Don't do | 1105 | /* Avoid a chip errata by prefixing a dummy entry. Don't do |
1106 | this on the ULI526X as it triggers a different problem */ | 1106 | this on the ULI526X as it triggers a different problem */ |
1107 | if (!(tp->chip_id == ULI526X && (tp->revision = 0x40 || tp->revision == 0x50))) { | 1107 | if (!(tp->chip_id == ULI526X && (tp->revision == 0x40 || tp->revision == 0x50))) { |
1108 | tp->tx_buffers[entry].skb = NULL; | 1108 | tp->tx_buffers[entry].skb = NULL; |
1109 | tp->tx_buffers[entry].mapping = 0; | 1109 | tp->tx_buffers[entry].mapping = 0; |
1110 | tp->tx_ring[entry].length = | 1110 | tp->tx_ring[entry].length = |
diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig index 0aaa12c0c098..1d3231cc471a 100644 --- a/drivers/net/wireless/Kconfig +++ b/drivers/net/wireless/Kconfig | |||
@@ -323,7 +323,7 @@ config PRISM54 | |||
323 | For a complete list of supported cards visit <http://prism54.org>. | 323 | For a complete list of supported cards visit <http://prism54.org>. |
324 | Here is the latest confirmed list of supported cards: | 324 | Here is the latest confirmed list of supported cards: |
325 | 325 | ||
326 | 3com OfficeConnect 11g Cardbus Card aka 3CRWE154G72 | 326 | 3com OfficeConnect 11g Cardbus Card aka 3CRWE154G72 (version 1) |
327 | Allnet ALL0271 PCI Card | 327 | Allnet ALL0271 PCI Card |
328 | Compex WL54G Cardbus Card | 328 | Compex WL54G Cardbus Card |
329 | Corega CG-WLCB54GT Cardbus Card | 329 | Corega CG-WLCB54GT Cardbus Card |
diff --git a/drivers/net/wireless/airo.c b/drivers/net/wireless/airo.c index 463c789cdc77..fb10a2db63ad 100644 --- a/drivers/net/wireless/airo.c +++ b/drivers/net/wireless/airo.c | |||
@@ -754,7 +754,7 @@ typedef struct { | |||
754 | u8 zero; | 754 | u8 zero; |
755 | u8 ssidLen; | 755 | u8 ssidLen; |
756 | u8 ssid[32]; | 756 | u8 ssid[32]; |
757 | u16 rssi; | 757 | u16 dBm; |
758 | #define CAP_ESS (1<<0) | 758 | #define CAP_ESS (1<<0) |
759 | #define CAP_IBSS (1<<1) | 759 | #define CAP_IBSS (1<<1) |
760 | #define CAP_PRIVACY (1<<4) | 760 | #define CAP_PRIVACY (1<<4) |
@@ -1125,6 +1125,9 @@ static int micsetup(struct airo_info *ai); | |||
1125 | static int encapsulate(struct airo_info *ai, etherHead *pPacket, MICBuffer *buffer, int len); | 1125 | static int encapsulate(struct airo_info *ai, etherHead *pPacket, MICBuffer *buffer, int len); |
1126 | static int decapsulate(struct airo_info *ai, MICBuffer *mic, etherHead *pPacket, u16 payLen); | 1126 | static int decapsulate(struct airo_info *ai, MICBuffer *mic, etherHead *pPacket, u16 payLen); |
1127 | 1127 | ||
1128 | static u8 airo_rssi_to_dbm (tdsRssiEntry *rssi_rid, u8 rssi); | ||
1129 | static u8 airo_dbm_to_pct (tdsRssiEntry *rssi_rid, u8 dbm); | ||
1130 | |||
1128 | #include <linux/crypto.h> | 1131 | #include <linux/crypto.h> |
1129 | #endif | 1132 | #endif |
1130 | 1133 | ||
@@ -1713,6 +1716,7 @@ static int readBSSListRid(struct airo_info *ai, int first, | |||
1713 | list->fh.dwell = le16_to_cpu(list->fh.dwell); | 1716 | list->fh.dwell = le16_to_cpu(list->fh.dwell); |
1714 | list->dsChannel = le16_to_cpu(list->dsChannel); | 1717 | list->dsChannel = le16_to_cpu(list->dsChannel); |
1715 | list->atimWindow = le16_to_cpu(list->atimWindow); | 1718 | list->atimWindow = le16_to_cpu(list->atimWindow); |
1719 | list->dBm = le16_to_cpu(list->dBm); | ||
1716 | return rc; | 1720 | return rc; |
1717 | } | 1721 | } |
1718 | 1722 | ||
@@ -3245,7 +3249,10 @@ badrx: | |||
3245 | wstats.level = 0x100 - apriv->rssi[hdr.rssi[1]].rssidBm; | 3249 | wstats.level = 0x100 - apriv->rssi[hdr.rssi[1]].rssidBm; |
3246 | else | 3250 | else |
3247 | wstats.level = (hdr.rssi[1] + 321) / 2; | 3251 | wstats.level = (hdr.rssi[1] + 321) / 2; |
3248 | wstats.updated = 3; | 3252 | wstats.noise = apriv->wstats.qual.noise; |
3253 | wstats.updated = IW_QUAL_LEVEL_UPDATED | ||
3254 | | IW_QUAL_QUAL_UPDATED | ||
3255 | | IW_QUAL_NOISE_UPDATED; | ||
3249 | /* Update spy records */ | 3256 | /* Update spy records */ |
3250 | wireless_spy_update(dev, sa, &wstats); | 3257 | wireless_spy_update(dev, sa, &wstats); |
3251 | } | 3258 | } |
@@ -3588,7 +3595,10 @@ void mpi_receive_802_11 (struct airo_info *ai) | |||
3588 | wstats.level = 0x100 - ai->rssi[hdr.rssi[1]].rssidBm; | 3595 | wstats.level = 0x100 - ai->rssi[hdr.rssi[1]].rssidBm; |
3589 | else | 3596 | else |
3590 | wstats.level = (hdr.rssi[1] + 321) / 2; | 3597 | wstats.level = (hdr.rssi[1] + 321) / 2; |
3591 | wstats.updated = 3; | 3598 | wstats.noise = ai->wstats.qual.noise; |
3599 | wstats.updated = IW_QUAL_QUAL_UPDATED | ||
3600 | | IW_QUAL_LEVEL_UPDATED | ||
3601 | | IW_QUAL_NOISE_UPDATED; | ||
3592 | /* Update spy records */ | 3602 | /* Update spy records */ |
3593 | wireless_spy_update(ai->dev, sa, &wstats); | 3603 | wireless_spy_update(ai->dev, sa, &wstats); |
3594 | } | 3604 | } |
@@ -3679,7 +3689,7 @@ static u16 setup_card(struct airo_info *ai, u8 *mac, int lock) | |||
3679 | status = PC4500_readrid(ai,RID_RSSI,&rssi_rid,sizeof(rssi_rid),lock); | 3689 | status = PC4500_readrid(ai,RID_RSSI,&rssi_rid,sizeof(rssi_rid),lock); |
3680 | if ( status == SUCCESS ) { | 3690 | if ( status == SUCCESS ) { |
3681 | if (ai->rssi || (ai->rssi = kmalloc(512, GFP_KERNEL)) != NULL) | 3691 | if (ai->rssi || (ai->rssi = kmalloc(512, GFP_KERNEL)) != NULL) |
3682 | memcpy(ai->rssi, (u8*)&rssi_rid + 2, 512); | 3692 | memcpy(ai->rssi, (u8*)&rssi_rid + 2, 512); /* Skip RID length member */ |
3683 | } | 3693 | } |
3684 | else { | 3694 | else { |
3685 | if (ai->rssi) { | 3695 | if (ai->rssi) { |
@@ -5348,7 +5358,7 @@ static int proc_BSSList_open( struct inode *inode, struct file *file ) { | |||
5348 | (int)BSSList_rid.bssid[5], | 5358 | (int)BSSList_rid.bssid[5], |
5349 | (int)BSSList_rid.ssidLen, | 5359 | (int)BSSList_rid.ssidLen, |
5350 | BSSList_rid.ssid, | 5360 | BSSList_rid.ssid, |
5351 | (int)BSSList_rid.rssi); | 5361 | (int)BSSList_rid.dBm); |
5352 | ptr += sprintf(ptr, " channel = %d %s %s %s %s\n", | 5362 | ptr += sprintf(ptr, " channel = %d %s %s %s %s\n", |
5353 | (int)BSSList_rid.dsChannel, | 5363 | (int)BSSList_rid.dsChannel, |
5354 | BSSList_rid.cap & CAP_ESS ? "ESS" : "", | 5364 | BSSList_rid.cap & CAP_ESS ? "ESS" : "", |
@@ -5593,6 +5603,29 @@ static void __exit airo_cleanup_module( void ) | |||
5593 | * would not work at all... - Jean II | 5603 | * would not work at all... - Jean II |
5594 | */ | 5604 | */ |
5595 | 5605 | ||
5606 | static u8 airo_rssi_to_dbm (tdsRssiEntry *rssi_rid, u8 rssi) | ||
5607 | { | ||
5608 | if( !rssi_rid ) | ||
5609 | return 0; | ||
5610 | |||
5611 | return (0x100 - rssi_rid[rssi].rssidBm); | ||
5612 | } | ||
5613 | |||
5614 | static u8 airo_dbm_to_pct (tdsRssiEntry *rssi_rid, u8 dbm) | ||
5615 | { | ||
5616 | int i; | ||
5617 | |||
5618 | if( !rssi_rid ) | ||
5619 | return 0; | ||
5620 | |||
5621 | for( i = 0; i < 256; i++ ) | ||
5622 | if (rssi_rid[i].rssidBm == dbm) | ||
5623 | return rssi_rid[i].rssipct; | ||
5624 | |||
5625 | return 0; | ||
5626 | } | ||
5627 | |||
5628 | |||
5596 | static int airo_get_quality (StatusRid *status_rid, CapabilityRid *cap_rid) | 5629 | static int airo_get_quality (StatusRid *status_rid, CapabilityRid *cap_rid) |
5597 | { | 5630 | { |
5598 | int quality = 0; | 5631 | int quality = 0; |
@@ -6443,11 +6476,29 @@ static int airo_get_range(struct net_device *dev, | |||
6443 | } | 6476 | } |
6444 | range->num_frequency = k; | 6477 | range->num_frequency = k; |
6445 | 6478 | ||
6479 | range->sensitivity = 65535; | ||
6480 | |||
6446 | /* Hum... Should put the right values there */ | 6481 | /* Hum... Should put the right values there */ |
6447 | range->max_qual.qual = airo_get_max_quality(&cap_rid); | 6482 | if (local->rssi) |
6448 | range->max_qual.level = 0x100 - 120; /* -120 dBm */ | 6483 | range->max_qual.qual = 100; /* % */ |
6484 | else | ||
6485 | range->max_qual.qual = airo_get_max_quality(&cap_rid); | ||
6486 | range->max_qual.level = 0; /* 0 means we use dBm */ | ||
6449 | range->max_qual.noise = 0; | 6487 | range->max_qual.noise = 0; |
6450 | range->sensitivity = 65535; | 6488 | range->max_qual.updated = 0; |
6489 | |||
6490 | /* Experimental measurements - boundary 11/5.5 Mb/s */ | ||
6491 | /* Note : with or without the (local->rssi), results | ||
6492 | * are somewhat different. - Jean II */ | ||
6493 | if (local->rssi) { | ||
6494 | range->avg_qual.qual = 50; /* % */ | ||
6495 | range->avg_qual.level = 186; /* -70 dBm */ | ||
6496 | } else { | ||
6497 | range->avg_qual.qual = airo_get_avg_quality(&cap_rid); | ||
6498 | range->avg_qual.level = 176; /* -80 dBm */ | ||
6499 | } | ||
6500 | range->avg_qual.noise = 0; | ||
6501 | range->avg_qual.updated = 0; | ||
6451 | 6502 | ||
6452 | for(i = 0 ; i < 8 ; i++) { | 6503 | for(i = 0 ; i < 8 ; i++) { |
6453 | range->bitrate[i] = cap_rid.supportedRates[i] * 500000; | 6504 | range->bitrate[i] = cap_rid.supportedRates[i] * 500000; |
@@ -6508,15 +6559,6 @@ static int airo_get_range(struct net_device *dev, | |||
6508 | range->max_retry = 65535; | 6559 | range->max_retry = 65535; |
6509 | range->min_r_time = 1024; | 6560 | range->min_r_time = 1024; |
6510 | range->max_r_time = 65535 * 1024; | 6561 | range->max_r_time = 65535 * 1024; |
6511 | /* Experimental measurements - boundary 11/5.5 Mb/s */ | ||
6512 | /* Note : with or without the (local->rssi), results | ||
6513 | * are somewhat different. - Jean II */ | ||
6514 | range->avg_qual.qual = airo_get_avg_quality(&cap_rid); | ||
6515 | if (local->rssi) | ||
6516 | range->avg_qual.level = 186; /* -70 dBm */ | ||
6517 | else | ||
6518 | range->avg_qual.level = 176; /* -80 dBm */ | ||
6519 | range->avg_qual.noise = 0; | ||
6520 | 6562 | ||
6521 | /* Event capability (kernel + driver) */ | 6563 | /* Event capability (kernel + driver) */ |
6522 | range->event_capa[0] = (IW_EVENT_CAPA_K_0 | | 6564 | range->event_capa[0] = (IW_EVENT_CAPA_K_0 | |
@@ -6676,12 +6718,18 @@ static int airo_get_aplist(struct net_device *dev, | |||
6676 | loseSync = 0; | 6718 | loseSync = 0; |
6677 | memcpy(address[i].sa_data, BSSList.bssid, ETH_ALEN); | 6719 | memcpy(address[i].sa_data, BSSList.bssid, ETH_ALEN); |
6678 | address[i].sa_family = ARPHRD_ETHER; | 6720 | address[i].sa_family = ARPHRD_ETHER; |
6679 | if (local->rssi) | 6721 | if (local->rssi) { |
6680 | qual[i].level = 0x100 - local->rssi[BSSList.rssi].rssidBm; | 6722 | qual[i].level = 0x100 - BSSList.dBm; |
6681 | else | 6723 | qual[i].qual = airo_dbm_to_pct( local->rssi, BSSList.dBm ); |
6682 | qual[i].level = (BSSList.rssi + 321) / 2; | 6724 | qual[i].updated = IW_QUAL_QUAL_UPDATED; |
6683 | qual[i].qual = qual[i].noise = 0; | 6725 | } else { |
6684 | qual[i].updated = 2; | 6726 | qual[i].level = (BSSList.dBm + 321) / 2; |
6727 | qual[i].qual = 0; | ||
6728 | qual[i].updated = IW_QUAL_QUAL_INVALID; | ||
6729 | } | ||
6730 | qual[i].noise = local->wstats.qual.noise; | ||
6731 | qual[i].updated = IW_QUAL_LEVEL_UPDATED | ||
6732 | | IW_QUAL_NOISE_UPDATED; | ||
6685 | if (BSSList.index == 0xffff) | 6733 | if (BSSList.index == 0xffff) |
6686 | break; | 6734 | break; |
6687 | } | 6735 | } |
@@ -6760,7 +6808,7 @@ static int airo_set_scan(struct net_device *dev, | |||
6760 | static inline char *airo_translate_scan(struct net_device *dev, | 6808 | static inline char *airo_translate_scan(struct net_device *dev, |
6761 | char *current_ev, | 6809 | char *current_ev, |
6762 | char *end_buf, | 6810 | char *end_buf, |
6763 | BSSListRid *list) | 6811 | BSSListRid *bss) |
6764 | { | 6812 | { |
6765 | struct airo_info *ai = dev->priv; | 6813 | struct airo_info *ai = dev->priv; |
6766 | struct iw_event iwe; /* Temporary buffer */ | 6814 | struct iw_event iwe; /* Temporary buffer */ |
@@ -6771,22 +6819,22 @@ static inline char *airo_translate_scan(struct net_device *dev, | |||
6771 | /* First entry *MUST* be the AP MAC address */ | 6819 | /* First entry *MUST* be the AP MAC address */ |
6772 | iwe.cmd = SIOCGIWAP; | 6820 | iwe.cmd = SIOCGIWAP; |
6773 | iwe.u.ap_addr.sa_family = ARPHRD_ETHER; | 6821 | iwe.u.ap_addr.sa_family = ARPHRD_ETHER; |
6774 | memcpy(iwe.u.ap_addr.sa_data, list->bssid, ETH_ALEN); | 6822 | memcpy(iwe.u.ap_addr.sa_data, bss->bssid, ETH_ALEN); |
6775 | current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, IW_EV_ADDR_LEN); | 6823 | current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, IW_EV_ADDR_LEN); |
6776 | 6824 | ||
6777 | /* Other entries will be displayed in the order we give them */ | 6825 | /* Other entries will be displayed in the order we give them */ |
6778 | 6826 | ||
6779 | /* Add the ESSID */ | 6827 | /* Add the ESSID */ |
6780 | iwe.u.data.length = list->ssidLen; | 6828 | iwe.u.data.length = bss->ssidLen; |
6781 | if(iwe.u.data.length > 32) | 6829 | if(iwe.u.data.length > 32) |
6782 | iwe.u.data.length = 32; | 6830 | iwe.u.data.length = 32; |
6783 | iwe.cmd = SIOCGIWESSID; | 6831 | iwe.cmd = SIOCGIWESSID; |
6784 | iwe.u.data.flags = 1; | 6832 | iwe.u.data.flags = 1; |
6785 | current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, list->ssid); | 6833 | current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, bss->ssid); |
6786 | 6834 | ||
6787 | /* Add mode */ | 6835 | /* Add mode */ |
6788 | iwe.cmd = SIOCGIWMODE; | 6836 | iwe.cmd = SIOCGIWMODE; |
6789 | capabilities = le16_to_cpu(list->cap); | 6837 | capabilities = le16_to_cpu(bss->cap); |
6790 | if(capabilities & (CAP_ESS | CAP_IBSS)) { | 6838 | if(capabilities & (CAP_ESS | CAP_IBSS)) { |
6791 | if(capabilities & CAP_ESS) | 6839 | if(capabilities & CAP_ESS) |
6792 | iwe.u.mode = IW_MODE_MASTER; | 6840 | iwe.u.mode = IW_MODE_MASTER; |
@@ -6797,19 +6845,25 @@ static inline char *airo_translate_scan(struct net_device *dev, | |||
6797 | 6845 | ||
6798 | /* Add frequency */ | 6846 | /* Add frequency */ |
6799 | iwe.cmd = SIOCGIWFREQ; | 6847 | iwe.cmd = SIOCGIWFREQ; |
6800 | iwe.u.freq.m = le16_to_cpu(list->dsChannel); | 6848 | iwe.u.freq.m = le16_to_cpu(bss->dsChannel); |
6801 | iwe.u.freq.m = frequency_list[iwe.u.freq.m] * 100000; | 6849 | iwe.u.freq.m = frequency_list[iwe.u.freq.m] * 100000; |
6802 | iwe.u.freq.e = 1; | 6850 | iwe.u.freq.e = 1; |
6803 | current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, IW_EV_FREQ_LEN); | 6851 | current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, IW_EV_FREQ_LEN); |
6804 | 6852 | ||
6805 | /* Add quality statistics */ | 6853 | /* Add quality statistics */ |
6806 | iwe.cmd = IWEVQUAL; | 6854 | iwe.cmd = IWEVQUAL; |
6807 | if (ai->rssi) | 6855 | if (ai->rssi) { |
6808 | iwe.u.qual.level = 0x100 - ai->rssi[list->rssi].rssidBm; | 6856 | iwe.u.qual.level = 0x100 - bss->dBm; |
6809 | else | 6857 | iwe.u.qual.qual = airo_dbm_to_pct( ai->rssi, bss->dBm ); |
6810 | iwe.u.qual.level = (list->rssi + 321) / 2; | 6858 | iwe.u.qual.updated = IW_QUAL_QUAL_UPDATED; |
6811 | iwe.u.qual.noise = 0; | 6859 | } else { |
6812 | iwe.u.qual.qual = 0; | 6860 | iwe.u.qual.level = (bss->dBm + 321) / 2; |
6861 | iwe.u.qual.qual = 0; | ||
6862 | iwe.u.qual.updated = IW_QUAL_QUAL_INVALID; | ||
6863 | } | ||
6864 | iwe.u.qual.noise = ai->wstats.qual.noise; | ||
6865 | iwe.u.qual.updated = IW_QUAL_LEVEL_UPDATED | ||
6866 | | IW_QUAL_NOISE_UPDATED; | ||
6813 | current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, IW_EV_QUAL_LEN); | 6867 | current_ev = iwe_stream_add_event(current_ev, end_buf, &iwe, IW_EV_QUAL_LEN); |
6814 | 6868 | ||
6815 | /* Add encryption capability */ | 6869 | /* Add encryption capability */ |
@@ -6819,7 +6873,7 @@ static inline char *airo_translate_scan(struct net_device *dev, | |||
6819 | else | 6873 | else |
6820 | iwe.u.data.flags = IW_ENCODE_DISABLED; | 6874 | iwe.u.data.flags = IW_ENCODE_DISABLED; |
6821 | iwe.u.data.length = 0; | 6875 | iwe.u.data.length = 0; |
6822 | current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, list->ssid); | 6876 | current_ev = iwe_stream_add_point(current_ev, end_buf, &iwe, bss->ssid); |
6823 | 6877 | ||
6824 | /* Rate : stuffing multiple values in a single event require a bit | 6878 | /* Rate : stuffing multiple values in a single event require a bit |
6825 | * more of magic - Jean II */ | 6879 | * more of magic - Jean II */ |
@@ -6831,10 +6885,10 @@ static inline char *airo_translate_scan(struct net_device *dev, | |||
6831 | /* Max 8 values */ | 6885 | /* Max 8 values */ |
6832 | for(i = 0 ; i < 8 ; i++) { | 6886 | for(i = 0 ; i < 8 ; i++) { |
6833 | /* NULL terminated */ | 6887 | /* NULL terminated */ |
6834 | if(list->rates[i] == 0) | 6888 | if(bss->rates[i] == 0) |
6835 | break; | 6889 | break; |
6836 | /* Bit rate given in 500 kb/s units (+ 0x80) */ | 6890 | /* Bit rate given in 500 kb/s units (+ 0x80) */ |
6837 | iwe.u.bitrate.value = ((list->rates[i] & 0x7f) * 500000); | 6891 | iwe.u.bitrate.value = ((bss->rates[i] & 0x7f) * 500000); |
6838 | /* Add new value to event */ | 6892 | /* Add new value to event */ |
6839 | current_val = iwe_stream_add_value(current_ev, current_val, end_buf, &iwe, IW_EV_PARAM_LEN); | 6893 | current_val = iwe_stream_add_value(current_ev, current_val, end_buf, &iwe, IW_EV_PARAM_LEN); |
6840 | } | 6894 | } |
@@ -7153,18 +7207,22 @@ static void airo_read_wireless_stats(struct airo_info *local) | |||
7153 | /* The status */ | 7207 | /* The status */ |
7154 | local->wstats.status = status_rid.mode; | 7208 | local->wstats.status = status_rid.mode; |
7155 | 7209 | ||
7156 | /* Signal quality and co. But where is the noise level ??? */ | 7210 | /* Signal quality and co */ |
7157 | local->wstats.qual.qual = airo_get_quality(&status_rid, &cap_rid); | 7211 | if (local->rssi) { |
7158 | if (local->rssi) | 7212 | local->wstats.qual.level = airo_rssi_to_dbm( local->rssi, status_rid.sigQuality ); |
7159 | local->wstats.qual.level = 0x100 - local->rssi[status_rid.sigQuality].rssidBm; | 7213 | /* normalizedSignalStrength appears to be a percentage */ |
7160 | else | 7214 | local->wstats.qual.qual = status_rid.normalizedSignalStrength; |
7215 | } else { | ||
7161 | local->wstats.qual.level = (status_rid.normalizedSignalStrength + 321) / 2; | 7216 | local->wstats.qual.level = (status_rid.normalizedSignalStrength + 321) / 2; |
7217 | local->wstats.qual.qual = airo_get_quality(&status_rid, &cap_rid); | ||
7218 | } | ||
7219 | local->wstats.qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_UPDATED; | ||
7162 | if (status_rid.len >= 124) { | 7220 | if (status_rid.len >= 124) { |
7163 | local->wstats.qual.noise = 256 - status_rid.noisedBm; | 7221 | local->wstats.qual.noise = 0x100 - status_rid.noisedBm; |
7164 | local->wstats.qual.updated = 7; | 7222 | local->wstats.qual.updated |= IW_QUAL_NOISE_UPDATED; |
7165 | } else { | 7223 | } else { |
7166 | local->wstats.qual.noise = 0; | 7224 | local->wstats.qual.noise = 0; |
7167 | local->wstats.qual.updated = 3; | 7225 | local->wstats.qual.updated |= IW_QUAL_NOISE_INVALID; |
7168 | } | 7226 | } |
7169 | 7227 | ||
7170 | /* Packets discarded in the wireless adapter due to wireless | 7228 | /* Packets discarded in the wireless adapter due to wireless |
diff --git a/drivers/net/wireless/atmel_cs.c b/drivers/net/wireless/atmel_cs.c index a91b507e0a7a..a4ed28d9c783 100644 --- a/drivers/net/wireless/atmel_cs.c +++ b/drivers/net/wireless/atmel_cs.c | |||
@@ -321,6 +321,7 @@ static struct { | |||
321 | { 0x01bf, 0x3302, NULL, ATMEL_FW_TYPE_502E, "Belkin F5D6020-V2" }, | 321 | { 0x01bf, 0x3302, NULL, ATMEL_FW_TYPE_502E, "Belkin F5D6020-V2" }, |
322 | { 0, 0, "BT/Voyager 1020 Laptop Adapter", ATMEL_FW_TYPE_502, "BT Voyager 1020" }, | 322 | { 0, 0, "BT/Voyager 1020 Laptop Adapter", ATMEL_FW_TYPE_502, "BT Voyager 1020" }, |
323 | { 0, 0, "IEEE 802.11b/Wireless LAN PC Card", ATMEL_FW_TYPE_502, "Siemens Gigaset PC Card II" }, | 323 | { 0, 0, "IEEE 802.11b/Wireless LAN PC Card", ATMEL_FW_TYPE_502, "Siemens Gigaset PC Card II" }, |
324 | { 0, 0, "IEEE 802.11b/Wireless LAN Card S", ATMEL_FW_TYPE_504_2958, "Siemens Gigaset PC Card II" }, | ||
324 | { 0, 0, "CNet/CNWLC 11Mbps Wireless PC Card V-5", ATMEL_FW_TYPE_502E, "CNet CNWLC-811ARL" }, | 325 | { 0, 0, "CNet/CNWLC 11Mbps Wireless PC Card V-5", ATMEL_FW_TYPE_502E, "CNet CNWLC-811ARL" }, |
325 | { 0, 0, "Wireless/PC_CARD", ATMEL_FW_TYPE_502D, "Planet WL-3552" }, | 326 | { 0, 0, "Wireless/PC_CARD", ATMEL_FW_TYPE_502D, "Planet WL-3552" }, |
326 | { 0, 0, "OEM/11Mbps Wireless LAN PC Card V-3", ATMEL_FW_TYPE_502, "OEM 11Mbps WLAN PCMCIA Card" }, | 327 | { 0, 0, "OEM/11Mbps Wireless LAN PC Card V-3", ATMEL_FW_TYPE_502, "OEM 11Mbps WLAN PCMCIA Card" }, |