Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6

* master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6:
  [TG3]: Update driver version and reldate.
  [TG3]: Add 5755 nvram support
  [TG3]: Add 5755 support
  [IPV6]: ip6_xmit: remove unnecessary NULL ptr check
  [NET_SCHED]: cls_u32: remove unnecessary NULL-ptr check
  [IPV4]: Add fib rule netlink notifications
  [BNX2]: Update version and reldate
  [BNX2]: Separate tx producer and consumer fields
  [BNX2]: Move .h files to bnx2.c
  [BNX2]: Combine small mem allocations
  [BNX2]: Fix link change handling
  [PKTGEN]: Add MPLS extension.

4 files changed, 173 insertions, 90 deletions

diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 7d213707008a..2671da20a496 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -9,13 +9,54 @@
  * Written by: Michael Chan  (mchan@broadcom.com)
  */
 
+#include <linux/config.h>
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+
+#include <linux/kernel.h>
+#include <linux/timer.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/dma-mapping.h>
+#include <asm/bitops.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <linux/delay.h>
+#include <asm/byteorder.h>
+#include <linux/time.h>
+#include <linux/ethtool.h>
+#include <linux/mii.h>
+#ifdef NETIF_F_HW_VLAN_TX
+#include <linux/if_vlan.h>
+#define BCM_VLAN 1
+#endif
+#ifdef NETIF_F_TSO
+#include <net/ip.h>
+#include <net/tcp.h>
+#include <net/checksum.h>
+#define BCM_TSO 1
+#endif
+#include <linux/workqueue.h>
+#include <linux/crc32.h>
+#include <linux/prefetch.h>
+#include <linux/cache.h>
+
 #include "bnx2.h"
 #include "bnx2_fw.h"
 
 #define DRV_MODULE_NAME         "bnx2"
 #define PFX DRV_MODULE_NAME     ": "
-#define DRV_MODULE_VERSION      "1.4.38"
-#define DRV_MODULE_RELDATE      "February 10, 2006"
+#define DRV_MODULE_VERSION      "1.4.39"
+#define DRV_MODULE_RELDATE      "March 22, 2006"
 
 #define RUN_AT(x) (jiffies + (x))
 
@@ -313,8 +354,6 @@ bnx2_disable_int(struct bnx2 *bp)
 static void
 bnx2_enable_int(struct bnx2 *bp)
 {
-        u32 val;
-
         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
                BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bp->last_status_idx);
@@ -322,8 +361,7 @@ bnx2_enable_int(struct bnx2 *bp)
         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
 
-        val = REG_RD(bp, BNX2_HC_COMMAND);
-        REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
+        REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
 }
 
 static void
@@ -362,15 +400,11 @@ bnx2_free_mem(struct bnx2 *bp)
 {
         int i;
 
-        if (bp->stats_blk) {
-                pci_free_consistent(bp->pdev, sizeof(struct statistics_block),
-                                    bp->stats_blk, bp->stats_blk_mapping);
-                bp->stats_blk = NULL;
-        }
         if (bp->status_blk) {
-                pci_free_consistent(bp->pdev, sizeof(struct status_block),
+                pci_free_consistent(bp->pdev, bp->status_stats_size,
                                     bp->status_blk, bp->status_blk_mapping);
                 bp->status_blk = NULL;
+                bp->stats_blk = NULL;
         }
         if (bp->tx_desc_ring) {
                 pci_free_consistent(bp->pdev,
@@ -395,14 +429,13 @@ bnx2_free_mem(struct bnx2 *bp)
 static int
 bnx2_alloc_mem(struct bnx2 *bp)
 {
-        int i;
+        int i, status_blk_size;
 
-        bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
-                                     GFP_KERNEL);
+        bp->tx_buf_ring = kzalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
+                                  GFP_KERNEL);
         if (bp->tx_buf_ring == NULL)
                 return -ENOMEM;
 
-        memset(bp->tx_buf_ring, 0, sizeof(struct sw_bd) * TX_DESC_CNT);
         bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
                                                 sizeof(struct tx_bd) *
                                                 TX_DESC_CNT,
@@ -428,21 +461,22 @@ bnx2_alloc_mem(struct bnx2 *bp)
 
         }
 
-        bp->status_blk = pci_alloc_consistent(bp->pdev,
-                                              sizeof(struct status_block),
+        /* Combine status and statistics blocks into one allocation. */
+        status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
+        bp->status_stats_size = status_blk_size +
+                                sizeof(struct statistics_block);
+
+        bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
                                               &bp->status_blk_mapping);
         if (bp->status_blk == NULL)
                 goto alloc_mem_err;
 
-        memset(bp->status_blk, 0, sizeof(struct status_block));
+        memset(bp->status_blk, 0, bp->status_stats_size);
 
-        bp->stats_blk = pci_alloc_consistent(bp->pdev,
-                                             sizeof(struct statistics_block),
-                                             &bp->stats_blk_mapping);
-        if (bp->stats_blk == NULL)
-                goto alloc_mem_err;
+        bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
+                                  status_blk_size);
 
-        memset(bp->stats_blk, 0, sizeof(struct statistics_block));
+        bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
 
         return 0;
 
@@ -1926,6 +1960,13 @@ bnx2_poll(struct net_device *dev, int *budget)
                 spin_lock(&bp->phy_lock);
                 bnx2_phy_int(bp);
                 spin_unlock(&bp->phy_lock);
+
+                /* This is needed to take care of transient status
+                 * during link changes.
+                 */
+                REG_WR(bp, BNX2_HC_COMMAND,
+                       bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
+                REG_RD(bp, BNX2_HC_COMMAND);
         }
 
         if (bp->status_blk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)
@@ -3307,6 +3348,8 @@ bnx2_init_chip(struct bnx2 *bp)
 
         udelay(20);
 
+        bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
+
         return rc;
 }
 
@@ -3746,7 +3789,6 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
         struct sk_buff *skb, *rx_skb;
         unsigned char *packet;
         u16 rx_start_idx, rx_idx;
-        u32 val;
         dma_addr_t map;
         struct tx_bd *txbd;
         struct sw_bd *rx_buf;
@@ -3777,8 +3819,9 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
         map = pci_map_single(bp->pdev, skb->data, pkt_size,
                 PCI_DMA_TODEVICE);
 
-        val = REG_RD(bp, BNX2_HC_COMMAND);
-        REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
+        REG_WR(bp, BNX2_HC_COMMAND,
+               bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
+
         REG_RD(bp, BNX2_HC_COMMAND);
 
         udelay(5);
@@ -3802,8 +3845,9 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
 
         udelay(100);
 
-        val = REG_RD(bp, BNX2_HC_COMMAND);
-        REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
+        REG_WR(bp, BNX2_HC_COMMAND,
+               bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
+
         REG_RD(bp, BNX2_HC_COMMAND);
 
         udelay(5);
@@ -3939,7 +3983,6 @@ static int
 bnx2_test_intr(struct bnx2 *bp)
 {
         int i;
-        u32 val;
         u16 status_idx;
 
         if (!netif_running(bp->dev))
@@ -3948,8 +3991,7 @@ bnx2_test_intr(struct bnx2 *bp)
         status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
 
         /* This register is not touched during run-time. */
-        val = REG_RD(bp, BNX2_HC_COMMAND);
-        REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
+        REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
         REG_RD(bp, BNX2_HC_COMMAND);
 
         for (i = 0; i < 10; i++) {
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index fd4b7f2eb477..b87925f6a228 100644
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -13,46 +13,6 @@
 #ifndef BNX2_H
 #define BNX2_H
 
-#include <linux/config.h>
-
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-
-#include <linux/kernel.h>
-#include <linux/timer.h>
-#include <linux/errno.h>
-#include <linux/ioport.h>
-#include <linux/slab.h>
-#include <linux/vmalloc.h>
-#include <linux/interrupt.h>
-#include <linux/pci.h>
-#include <linux/init.h>
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/skbuff.h>
-#include <linux/dma-mapping.h>
-#include <asm/bitops.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <linux/delay.h>
-#include <asm/byteorder.h>
-#include <linux/time.h>
-#include <linux/ethtool.h>
-#include <linux/mii.h>
-#ifdef NETIF_F_HW_VLAN_TX
-#include <linux/if_vlan.h>
-#define BCM_VLAN 1
-#endif
-#ifdef NETIF_F_TSO
-#include <net/ip.h>
-#include <net/tcp.h>
-#include <net/checksum.h>
-#define BCM_TSO 1
-#endif
-#include <linux/workqueue.h>
-#include <linux/crc32.h>
-#include <linux/prefetch.h>
-
 /* Hardware data structures and register definitions automatically
  * generated from RTL code. Do not modify.
  */
@@ -3917,15 +3877,17 @@ struct bnx2 {
 #define USING_MSI_FLAG                  0x20
 #define ASF_ENABLE_FLAG                 0x40
 
-        struct tx_bd            *tx_desc_ring;
-        struct sw_bd            *tx_buf_ring;
-        u32                     tx_prod_bseq;
-        u16                     tx_prod;
-        u16                     tx_cons;
-        int                     tx_ring_size;
+        /* Put tx producer and consumer fields in separate cache lines. */
 
-        u16                     hw_tx_cons;
-        u16                     hw_rx_cons;
+        u32             tx_prod_bseq __attribute__((aligned(L1_CACHE_BYTES)));
+        u16             tx_prod;
+
+        struct tx_bd    *tx_desc_ring;
+        struct sw_bd    *tx_buf_ring;
+        int             tx_ring_size;
+
+        u16             tx_cons __attribute__((aligned(L1_CACHE_BYTES)));
+        u16             hw_tx_cons;
 
 #ifdef BCM_VLAN 
         struct                  vlan_group *vlgrp;
@@ -3939,6 +3901,7 @@ struct bnx2 {
         u32                     rx_prod_bseq;
         u16                     rx_prod;
         u16                     rx_cons;
+        u16                     hw_rx_cons;
 
         u32                     rx_csum;
 
@@ -4038,6 +4001,7 @@ struct bnx2 {
         struct statistics_block *stats_blk;
         dma_addr_t              stats_blk_mapping;
 
+        u32                     hc_cmd;
         u32                     rx_mode;
 
         u16                     req_line_speed;
@@ -4082,6 +4046,8 @@ struct bnx2 {
 
         struct flash_spec       *flash_info;
         u32                     flash_size;
+
+        int                     status_stats_size;
 };
 
 static u32 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset);
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 88829eb9568e..b5473325bff4 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -69,8 +69,8 @@
 
 #define DRV_MODULE_NAME         "tg3"
 #define PFX DRV_MODULE_NAME     ": "
-#define DRV_MODULE_VERSION      "3.53"
-#define DRV_MODULE_RELDATE      "Mar 22, 2006"
+#define DRV_MODULE_VERSION      "3.54"
+#define DRV_MODULE_RELDATE      "Mar 23, 2006"
 
 #define TG3_DEF_MAC_MODE        0
 #define TG3_DEF_RX_MODE         0
@@ -225,6 +225,10 @@ static struct pci_device_id tg3_pci_tbl[] = {
           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M,
           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+        { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755,
+          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+        { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M,
+          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787,
           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M,
@@ -4557,6 +4561,7 @@ static int tg3_chip_reset(struct tg3 *tp)
         }
 
         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
+            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
                 tw32(GRC_FASTBOOT_PC, 0);
 
@@ -6152,6 +6157,9 @@ static int tg3_reset_hw(struct tg3 *tp)
                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
                                      GRC_LCLCTRL_GPIO_OUTPUT3;
 
+                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
+                        gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
+
                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
 
                 /* GPIO1 must be driven high for eeprom write protect */
@@ -6191,7 +6199,8 @@ static int tg3_reset_hw(struct tg3 *tp)
         }
 
         /* Enable host coalescing bug fix */
-        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
+        if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
+            (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
                 val |= (1 << 29);
 
         tw32_f(WDMAC_MODE, val);
@@ -6249,6 +6258,9 @@ static int tg3_reset_hw(struct tg3 *tp)
         udelay(100);
 
         tp->rx_mode = RX_MODE_ENABLE;
+        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
+                tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
+
         tw32_f(MAC_RX_MODE, tp->rx_mode);
         udelay(10);
 
@@ -7907,7 +7919,8 @@ static int tg3_set_tx_csum(struct net_device *dev, u32 data)
                 return 0;
         }
   
-        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
+        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
+            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
                 ethtool_op_set_tx_hw_csum(dev, data);
         else
                 ethtool_op_set_tx_csum(dev, data);
@@ -8332,7 +8345,8 @@ static int tg3_test_memory(struct tg3 *tp)
         int i;
 
         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
-                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
+                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
+                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
                         mem_tbl = mem_tbl_5755;
                 else
                         mem_tbl = mem_tbl_5705;
@@ -8924,6 +8938,47 @@ static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
         }
 }
 
+static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
+{
+        u32 nvcfg1;
+
+        nvcfg1 = tr32(NVRAM_CFG1);
+
+        /* NVRAM protection for TPM */
+        if (nvcfg1 & (1 << 27))
+                tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
+
+        switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
+                case FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ:
+                case FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ:
+                        tp->nvram_jedecnum = JEDEC_ATMEL;
+                        tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
+                        tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
+
+                        nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
+                        tw32(NVRAM_CFG1, nvcfg1);
+                        break;
+                case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
+                case FLASH_5755VENDOR_ATMEL_FLASH_1:
+                case FLASH_5755VENDOR_ATMEL_FLASH_2:
+                case FLASH_5755VENDOR_ATMEL_FLASH_3:
+                case FLASH_5755VENDOR_ATMEL_FLASH_4:
+                        tp->nvram_jedecnum = JEDEC_ATMEL;
+                        tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
+                        tp->tg3_flags2 |= TG3_FLG2_FLASH;
+                        tp->nvram_pagesize = 264;
+                        break;
+                case FLASH_5752VENDOR_ST_M45PE10:
+                case FLASH_5752VENDOR_ST_M45PE20:
+                case FLASH_5752VENDOR_ST_M45PE40:
+                        tp->nvram_jedecnum = JEDEC_ST;
+                        tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
+                        tp->tg3_flags2 |= TG3_FLG2_FLASH;
+                        tp->nvram_pagesize = 256;
+                        break;
+        }
+}
+
 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
 {
         u32 nvcfg1;
@@ -8997,6 +9052,8 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
 
                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
                         tg3_get_5752_nvram_info(tp);
+                else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
+                        tg3_get_5755_nvram_info(tp);
                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
                         tg3_get_5787_nvram_info(tp);
                 else
@@ -9310,6 +9367,7 @@ static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
                         nvram_cmd |= NVRAM_CMD_LAST;
 
                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
+                    (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
                     (tp->nvram_jedecnum == JEDEC_ST) &&
                     (nvram_cmd & NVRAM_CMD_FIRST)) {
@@ -10044,6 +10102,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
 
         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
+            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
@@ -10053,7 +10112,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
 
         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
-                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
+                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
+                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
                 } else
@@ -10063,6 +10123,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
+            GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787)
                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
 
@@ -10219,6 +10280,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
 
+        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
+                tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
+
         /* Force the chip into D0. */
         err = tg3_set_power_state(tp, PCI_D0);
         if (err) {
@@ -10274,6 +10338,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
 
         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
+            (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787))
                 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
 
@@ -10413,7 +10478,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
         /* All chips before 5787 can get confused if TX buffers
          * straddle the 4GB address boundary in some cases.
          */
-        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
+        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
+            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
                 tp->dev->hard_start_xmit = tg3_start_xmit;
         else
                 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
@@ -11002,6 +11068,7 @@ static char * __devinit tg3_phy_string(struct tg3 *tp)
         case PHY_ID_BCM5752:    return "5752";
         case PHY_ID_BCM5714:    return "5714";
         case PHY_ID_BCM5780:    return "5780";
+        case PHY_ID_BCM5755:    return "5755";
         case PHY_ID_BCM5787:    return "5787";
         case PHY_ID_BCM8002:    return "8002/serdes";
         case 0:                 return "serdes";
@@ -11350,7 +11417,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
          * checksumming.
          */
         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
-                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
+                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
+                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
                         dev->features |= NETIF_F_HW_CSUM;
                 else
                         dev->features |= NETIF_F_IP_CSUM;
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index baa34c4721db..c43cc3264202 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -138,6 +138,7 @@
 #define   ASIC_REV_5752                  0x06
 #define   ASIC_REV_5780                  0x08
 #define   ASIC_REV_5714                  0x09
+#define   ASIC_REV_5755                  0x0a
 #define   ASIC_REV_5787                  0x0b
 #define  GET_CHIP_REV(CHIP_REV_ID)      ((CHIP_REV_ID) >> 8)
 #define   CHIPREV_5700_AX                0x70
@@ -456,6 +457,7 @@
 #define  RX_MODE_PROMISC                 0x00000100
 #define  RX_MODE_NO_CRC_CHECK            0x00000200
 #define  RX_MODE_KEEP_VLAN_TAG           0x00000400
+#define  RX_MODE_IPV6_CSUM_ENABLE        0x01000000
 #define MAC_RX_STATUS                   0x0000046c
 #define  RX_STATUS_REMOTE_TX_XOFFED      0x00000001
 #define  RX_STATUS_XOFF_RCVD             0x00000002
@@ -1340,6 +1342,7 @@
 #define  GRC_LCLCTRL_CLEARINT           0x00000002
 #define  GRC_LCLCTRL_SETINT             0x00000004
 #define  GRC_LCLCTRL_INT_ON_ATTN        0x00000008
+#define  GRC_LCLCTRL_GPIO_UART_SEL      0x00000010      /* 5755 only */
 #define  GRC_LCLCTRL_USE_SIG_DETECT     0x00000010      /* 5714/5780 only */
 #define  GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020      /* 5714/5780 only */
 #define  GRC_LCLCTRL_GPIO_INPUT3        0x00000020
@@ -1441,6 +1444,9 @@
 #define  FLASH_5755VENDOR_ATMEL_FLASH_1  0x03400001
 #define  FLASH_5755VENDOR_ATMEL_FLASH_2  0x03400002
 #define  FLASH_5755VENDOR_ATMEL_FLASH_3  0x03400000
+#define  FLASH_5755VENDOR_ATMEL_FLASH_4  0x00000003
+#define  FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ     0x03c00003
+#define  FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ    0x03c00002
 #define  FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ     0x03000003
 #define  FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ    0x03000002
 #define  FLASH_5787VENDOR_MICRO_EEPROM_64KHZ     0x03000000
@@ -2259,6 +2265,7 @@ struct tg3 {
 #define PHY_ID_BCM5752                  0x60008100
 #define PHY_ID_BCM5714                  0x60008340
 #define PHY_ID_BCM5780                  0x60008350
+#define PHY_ID_BCM5755                  0xbc050cc0
 #define PHY_ID_BCM5787                  0xbc050ce0
 #define PHY_ID_BCM8002                  0x60010140
 #define PHY_ID_INVALID                  0xffffffff
@@ -2286,7 +2293,7 @@ struct tg3 {
          (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
          (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \
          (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
-         (X) == PHY_ID_BCM8002)
+         (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM8002)
 
         struct tg3_hw_stats             *hw_stats;
         dma_addr_t                      stats_mapping;