diff options
author | Matt Carlson <mcarlson@broadcom.com> | 2009-08-28 10:03:01 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-08-29 18:43:03 -0400 |
commit | 723344820aa405ac2663ab9e36fd27833d06129b (patch) | |
tree | dad1b2b19c269ff1ba9dcd3d5bbbc8d4ac38a9ba /drivers/net | |
parent | 898a56f8d8170c188e47ae3acb90d2ea9a585ebe (diff) |
tg3: Move per-int rx members to per-int struct
This patch moves the rx_rcb, rx_rcb_mapping, and rx_rcb_ptr return ring
device members to a per-interrupt structure. It also adds a new return
ring consumer mailbox register member (consmbox) and converts the code
to use it rather than a preprocessor constant.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r-- | drivers/net/tg3.c | 57 | ||||
-rw-r--r-- | drivers/net/tg3.h | 9 |
2 files changed, 37 insertions, 29 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 5b8d6e033183..939574c571f7 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -657,7 +657,7 @@ static inline unsigned int tg3_has_work(struct tg3_napi *tnapi) | |||
657 | } | 657 | } |
658 | /* check for RX/TX work to do */ | 658 | /* check for RX/TX work to do */ |
659 | if (sblk->idx[0].tx_consumer != tp->tx_cons || | 659 | if (sblk->idx[0].tx_consumer != tp->tx_cons || |
660 | sblk->idx[0].rx_producer != tp->rx_rcb_ptr) | 660 | sblk->idx[0].rx_producer != tnapi->rx_rcb_ptr) |
661 | work_exists = 1; | 661 | work_exists = 1; |
662 | 662 | ||
663 | return work_exists; | 663 | return work_exists; |
@@ -4480,7 +4480,7 @@ static int tg3_rx(struct tg3_napi *tnapi, int budget) | |||
4480 | { | 4480 | { |
4481 | struct tg3 *tp = tnapi->tp; | 4481 | struct tg3 *tp = tnapi->tp; |
4482 | u32 work_mask, rx_std_posted = 0; | 4482 | u32 work_mask, rx_std_posted = 0; |
4483 | u32 sw_idx = tp->rx_rcb_ptr; | 4483 | u32 sw_idx = tnapi->rx_rcb_ptr; |
4484 | u16 hw_idx; | 4484 | u16 hw_idx; |
4485 | int received; | 4485 | int received; |
4486 | struct tg3_rx_prodring_set *tpr = &tp->prodring[0]; | 4486 | struct tg3_rx_prodring_set *tpr = &tp->prodring[0]; |
@@ -4494,7 +4494,7 @@ static int tg3_rx(struct tg3_napi *tnapi, int budget) | |||
4494 | work_mask = 0; | 4494 | work_mask = 0; |
4495 | received = 0; | 4495 | received = 0; |
4496 | while (sw_idx != hw_idx && budget > 0) { | 4496 | while (sw_idx != hw_idx && budget > 0) { |
4497 | struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx]; | 4497 | struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; |
4498 | unsigned int len; | 4498 | unsigned int len; |
4499 | struct sk_buff *skb; | 4499 | struct sk_buff *skb; |
4500 | dma_addr_t dma_addr; | 4500 | dma_addr_t dma_addr; |
@@ -4622,8 +4622,8 @@ next_pkt_nopost: | |||
4622 | } | 4622 | } |
4623 | 4623 | ||
4624 | /* ACK the status ring. */ | 4624 | /* ACK the status ring. */ |
4625 | tp->rx_rcb_ptr = sw_idx; | 4625 | tnapi->rx_rcb_ptr = sw_idx; |
4626 | tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx); | 4626 | tw32_rx_mbox(tnapi->consmbox, sw_idx); |
4627 | 4627 | ||
4628 | /* Refill RX ring(s). */ | 4628 | /* Refill RX ring(s). */ |
4629 | if (work_mask & RXD_OPAQUE_RING_STD) { | 4629 | if (work_mask & RXD_OPAQUE_RING_STD) { |
@@ -4678,7 +4678,7 @@ static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget) | |||
4678 | * All RX "locking" is done by ensuring outside | 4678 | * All RX "locking" is done by ensuring outside |
4679 | * code synchronizes with tg3->napi.poll() | 4679 | * code synchronizes with tg3->napi.poll() |
4680 | */ | 4680 | */ |
4681 | if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) | 4681 | if (sblk->idx[0].rx_producer != tnapi->rx_rcb_ptr) |
4682 | work_done += tg3_rx(tnapi, budget - work_done); | 4682 | work_done += tg3_rx(tnapi, budget - work_done); |
4683 | 4683 | ||
4684 | return work_done; | 4684 | return work_done; |
@@ -4768,7 +4768,7 @@ static irqreturn_t tg3_msi_1shot(int irq, void *dev_id) | |||
4768 | struct tg3 *tp = tnapi->tp; | 4768 | struct tg3 *tp = tnapi->tp; |
4769 | 4769 | ||
4770 | prefetch(tnapi->hw_status); | 4770 | prefetch(tnapi->hw_status); |
4771 | prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]); | 4771 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
4772 | 4772 | ||
4773 | if (likely(!tg3_irq_sync(tp))) | 4773 | if (likely(!tg3_irq_sync(tp))) |
4774 | napi_schedule(&tnapi->napi); | 4774 | napi_schedule(&tnapi->napi); |
@@ -4786,7 +4786,7 @@ static irqreturn_t tg3_msi(int irq, void *dev_id) | |||
4786 | struct tg3 *tp = tnapi->tp; | 4786 | struct tg3 *tp = tnapi->tp; |
4787 | 4787 | ||
4788 | prefetch(tnapi->hw_status); | 4788 | prefetch(tnapi->hw_status); |
4789 | prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]); | 4789 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
4790 | /* | 4790 | /* |
4791 | * Writing any value to intr-mbox-0 clears PCI INTA# and | 4791 | * Writing any value to intr-mbox-0 clears PCI INTA# and |
4792 | * chip-internal interrupt pending events. | 4792 | * chip-internal interrupt pending events. |
@@ -4837,7 +4837,7 @@ static irqreturn_t tg3_interrupt(int irq, void *dev_id) | |||
4837 | goto out; | 4837 | goto out; |
4838 | sblk->status &= ~SD_STATUS_UPDATED; | 4838 | sblk->status &= ~SD_STATUS_UPDATED; |
4839 | if (likely(tg3_has_work(tnapi))) { | 4839 | if (likely(tg3_has_work(tnapi))) { |
4840 | prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]); | 4840 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
4841 | napi_schedule(&tnapi->napi); | 4841 | napi_schedule(&tnapi->napi); |
4842 | } else { | 4842 | } else { |
4843 | /* No work, shared interrupt perhaps? re-enable | 4843 | /* No work, shared interrupt perhaps? re-enable |
@@ -4894,7 +4894,7 @@ static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id) | |||
4894 | if (tg3_irq_sync(tp)) | 4894 | if (tg3_irq_sync(tp)) |
4895 | goto out; | 4895 | goto out; |
4896 | 4896 | ||
4897 | prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]); | 4897 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
4898 | 4898 | ||
4899 | napi_schedule(&tnapi->napi); | 4899 | napi_schedule(&tnapi->napi); |
4900 | 4900 | ||
@@ -5745,13 +5745,17 @@ static void tg3_free_rings(struct tg3 *tp) | |||
5745 | */ | 5745 | */ |
5746 | static int tg3_init_rings(struct tg3 *tp) | 5746 | static int tg3_init_rings(struct tg3 *tp) |
5747 | { | 5747 | { |
5748 | struct tg3_napi *tnapi = &tp->napi[0]; | ||
5749 | |||
5748 | /* Free up all the SKBs. */ | 5750 | /* Free up all the SKBs. */ |
5749 | tg3_free_rings(tp); | 5751 | tg3_free_rings(tp); |
5750 | 5752 | ||
5751 | /* Zero out all descriptors. */ | 5753 | /* Zero out all descriptors. */ |
5752 | memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); | ||
5753 | memset(tp->tx_ring, 0, TG3_TX_RING_BYTES); | 5754 | memset(tp->tx_ring, 0, TG3_TX_RING_BYTES); |
5754 | 5755 | ||
5756 | tnapi->rx_rcb_ptr = 0; | ||
5757 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); | ||
5758 | |||
5755 | return tg3_rx_prodring_alloc(tp, &tp->prodring[0]); | 5759 | return tg3_rx_prodring_alloc(tp, &tp->prodring[0]); |
5756 | } | 5760 | } |
5757 | 5761 | ||
@@ -5765,16 +5769,16 @@ static void tg3_free_consistent(struct tg3 *tp) | |||
5765 | 5769 | ||
5766 | kfree(tp->tx_buffers); | 5770 | kfree(tp->tx_buffers); |
5767 | tp->tx_buffers = NULL; | 5771 | tp->tx_buffers = NULL; |
5768 | if (tp->rx_rcb) { | ||
5769 | pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp), | ||
5770 | tp->rx_rcb, tp->rx_rcb_mapping); | ||
5771 | tp->rx_rcb = NULL; | ||
5772 | } | ||
5773 | if (tp->tx_ring) { | 5772 | if (tp->tx_ring) { |
5774 | pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES, | 5773 | pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES, |
5775 | tp->tx_ring, tp->tx_desc_mapping); | 5774 | tp->tx_ring, tp->tx_desc_mapping); |
5776 | tp->tx_ring = NULL; | 5775 | tp->tx_ring = NULL; |
5777 | } | 5776 | } |
5777 | if (tnapi->rx_rcb) { | ||
5778 | pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp), | ||
5779 | tnapi->rx_rcb, tnapi->rx_rcb_mapping); | ||
5780 | tnapi->rx_rcb = NULL; | ||
5781 | } | ||
5778 | if (tnapi->hw_status) { | 5782 | if (tnapi->hw_status) { |
5779 | pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE, | 5783 | pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE, |
5780 | tnapi->hw_status, | 5784 | tnapi->hw_status, |
@@ -5805,11 +5809,6 @@ static int tg3_alloc_consistent(struct tg3 *tp) | |||
5805 | if (!tp->tx_buffers) | 5809 | if (!tp->tx_buffers) |
5806 | goto err_out; | 5810 | goto err_out; |
5807 | 5811 | ||
5808 | tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp), | ||
5809 | &tp->rx_rcb_mapping); | ||
5810 | if (!tp->rx_rcb) | ||
5811 | goto err_out; | ||
5812 | |||
5813 | tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES, | 5812 | tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES, |
5814 | &tp->tx_desc_mapping); | 5813 | &tp->tx_desc_mapping); |
5815 | if (!tp->tx_ring) | 5814 | if (!tp->tx_ring) |
@@ -5823,6 +5822,14 @@ static int tg3_alloc_consistent(struct tg3 *tp) | |||
5823 | 5822 | ||
5824 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | 5823 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); |
5825 | 5824 | ||
5825 | tnapi->rx_rcb = pci_alloc_consistent(tp->pdev, | ||
5826 | TG3_RX_RCB_RING_BYTES(tp), | ||
5827 | &tnapi->rx_rcb_mapping); | ||
5828 | if (!tnapi->rx_rcb) | ||
5829 | goto err_out; | ||
5830 | |||
5831 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); | ||
5832 | |||
5826 | tp->hw_stats = pci_alloc_consistent(tp->pdev, | 5833 | tp->hw_stats = pci_alloc_consistent(tp->pdev, |
5827 | sizeof(struct tg3_hw_stats), | 5834 | sizeof(struct tg3_hw_stats), |
5828 | &tp->stats_mapping); | 5835 | &tp->stats_mapping); |
@@ -7109,11 +7116,10 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
7109 | } | 7116 | } |
7110 | } | 7117 | } |
7111 | 7118 | ||
7112 | tp->rx_rcb_ptr = 0; | 7119 | tw32_rx_mbox(tp->napi[0].consmbox, 0); |
7113 | tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0); | ||
7114 | 7120 | ||
7115 | tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB, | 7121 | tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB, |
7116 | tp->rx_rcb_mapping, | 7122 | tp->napi[0].rx_rcb_mapping, |
7117 | (TG3_RX_RCB_RING_SIZE(tp) << | 7123 | (TG3_RX_RCB_RING_SIZE(tp) << |
7118 | BDINFO_FLAGS_MAXLEN_SHIFT), | 7124 | BDINFO_FLAGS_MAXLEN_SHIFT), |
7119 | 0); | 7125 | 0); |
@@ -9956,7 +9962,7 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode) | |||
9956 | if (rx_idx != rx_start_idx + num_pkts) | 9962 | if (rx_idx != rx_start_idx + num_pkts) |
9957 | goto out; | 9963 | goto out; |
9958 | 9964 | ||
9959 | desc = &tp->rx_rcb[rx_start_idx]; | 9965 | desc = &rnapi->rx_rcb[rx_start_idx]; |
9960 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | 9966 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; |
9961 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | 9967 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; |
9962 | if (opaque_key != RXD_OPAQUE_RING_STD) | 9968 | if (opaque_key != RXD_OPAQUE_RING_STD) |
@@ -13413,6 +13419,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev, | |||
13413 | 13419 | ||
13414 | tp->napi[0].tp = tp; | 13420 | tp->napi[0].tp = tp; |
13415 | tp->napi[0].int_mbox = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW; | 13421 | tp->napi[0].int_mbox = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW; |
13422 | tp->napi[0].consmbox = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW; | ||
13416 | netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64); | 13423 | netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64); |
13417 | dev->ethtool_ops = &tg3_ethtool_ops; | 13424 | dev->ethtool_ops = &tg3_ethtool_ops; |
13418 | dev->watchdog_timeo = TG3_TX_TIMEOUT; | 13425 | dev->watchdog_timeo = TG3_TX_TIMEOUT; |
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index f46e6198a82b..b91ac29ae163 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h | |||
@@ -2497,8 +2497,13 @@ struct tg3_napi { | |||
2497 | u32 last_tag; | 2497 | u32 last_tag; |
2498 | u32 last_irq_tag; | 2498 | u32 last_irq_tag; |
2499 | u32 int_mbox; | 2499 | u32 int_mbox; |
2500 | u32 consmbox; | ||
2501 | u32 rx_rcb_ptr; | ||
2502 | |||
2503 | struct tg3_rx_buffer_desc *rx_rcb; | ||
2500 | 2504 | ||
2501 | dma_addr_t status_mapping; | 2505 | dma_addr_t status_mapping; |
2506 | dma_addr_t rx_rcb_mapping; | ||
2502 | }; | 2507 | }; |
2503 | 2508 | ||
2504 | struct tg3 { | 2509 | struct tg3 { |
@@ -2570,7 +2575,6 @@ struct tg3 { | |||
2570 | struct tg3_napi napi[TG3_IRQ_MAX_VECS]; | 2575 | struct tg3_napi napi[TG3_IRQ_MAX_VECS]; |
2571 | void (*write32_rx_mbox) (struct tg3 *, u32, | 2576 | void (*write32_rx_mbox) (struct tg3 *, u32, |
2572 | u32); | 2577 | u32); |
2573 | u32 rx_rcb_ptr; | ||
2574 | u32 rx_pending; | 2578 | u32 rx_pending; |
2575 | u32 rx_jumbo_pending; | 2579 | u32 rx_jumbo_pending; |
2576 | u32 rx_std_max_post; | 2580 | u32 rx_std_max_post; |
@@ -2579,9 +2583,6 @@ struct tg3 { | |||
2579 | struct vlan_group *vlgrp; | 2583 | struct vlan_group *vlgrp; |
2580 | #endif | 2584 | #endif |
2581 | 2585 | ||
2582 | struct tg3_rx_buffer_desc *rx_rcb; | ||
2583 | dma_addr_t rx_rcb_mapping; | ||
2584 | |||
2585 | struct tg3_rx_prodring_set prodring[1]; | 2586 | struct tg3_rx_prodring_set prodring[1]; |
2586 | 2587 | ||
2587 | 2588 | ||