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authorJesse Brandeburg <jesse.brandeburg@intel.com>2009-09-25 18:19:46 -0400
committerDavid S. Miller <davem@davemloft.net>2009-09-26 23:15:55 -0400
commit120a5d0d588c9a4d47574fcfdab8454817c8586c (patch)
tree7fd259149f9fbbf38f777995f568ec5aa32f7a04 /drivers/net
parent650b5a5cc34b9fbd38b68e9b8bb1455222fcdb87 (diff)
e1000: updated whitespace and comments
A large whitespace change to e1000_hw.[ch] in order to update it to kernel coding style (by running lindent). Updated function header comments into kdoc style. Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/e1000/e1000_hw.c9663
-rw-r--r--drivers/net/e1000/e1000_hw.h2891
-rw-r--r--drivers/net/e1000/e1000_main.c12
3 files changed, 6337 insertions, 6229 deletions
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index 076db19f69f4..6aba88304407 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -24,13 +24,12 @@
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 26
27*******************************************************************************/ 27 */
28 28
29/* e1000_hw.c 29/* e1000_hw.c
30 * Shared functions for accessing and configuring the MAC 30 * Shared functions for accessing and configuring the MAC
31 */ 31 */
32 32
33
34#include "e1000_hw.h" 33#include "e1000_hw.h"
35 34
36static s32 e1000_check_downshift(struct e1000_hw *hw); 35static s32 e1000_check_downshift(struct e1000_hw *hw);
@@ -69,12 +68,11 @@ static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
69static s32 e1000_config_mac_to_phy(struct e1000_hw *hw); 68static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);
70static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl); 69static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
71static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl); 70static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
72static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, 71static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);
73 u16 count);
74static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw); 72static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);
75static s32 e1000_phy_reset_dsp(struct e1000_hw *hw); 73static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
76static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, 74static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,
77 u16 words, u16 *data); 75 u16 words, u16 *data);
78static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, 76static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
79 u16 words, u16 *data); 77 u16 words, u16 *data);
80static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw); 78static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);
@@ -83,7 +81,7 @@ static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);
83static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count); 81static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);
84static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 82static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
85 u16 phy_data); 83 u16 phy_data);
86static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw,u32 reg_addr, 84static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
87 u16 *phy_data); 85 u16 *phy_data);
88static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count); 86static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
89static s32 e1000_acquire_eeprom(struct e1000_hw *hw); 87static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
@@ -92,159 +90,164 @@ static void e1000_standby_eeprom(struct e1000_hw *hw);
92static s32 e1000_set_vco_speed(struct e1000_hw *hw); 90static s32 e1000_set_vco_speed(struct e1000_hw *hw);
93static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw); 91static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
94static s32 e1000_set_phy_mode(struct e1000_hw *hw); 92static s32 e1000_set_phy_mode(struct e1000_hw *hw);
95static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); 93static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
96static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); 94 u16 *data);
95static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
96 u16 *data);
97 97
98/* IGP cable length table */ 98/* IGP cable length table */
99static const 99static const
100u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = 100u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {
101 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 101 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
102 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 102 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
103 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 103 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
104 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 104 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
105 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 105 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
106 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 106 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,
107 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 107 100,
108 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; 108 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
109 110, 110,
110 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,
111 120, 120
112};
109 113
110static DEFINE_SPINLOCK(e1000_eeprom_lock); 114static DEFINE_SPINLOCK(e1000_eeprom_lock);
111 115
112/****************************************************************************** 116/**
113 * Set the phy type member in the hw struct. 117 * e1000_set_phy_type - Set the phy type member in the hw struct.
114 * 118 * @hw: Struct containing variables accessed by shared code
115 * hw - Struct containing variables accessed by shared code 119 */
116 *****************************************************************************/
117static s32 e1000_set_phy_type(struct e1000_hw *hw) 120static s32 e1000_set_phy_type(struct e1000_hw *hw)
118{ 121{
119 DEBUGFUNC("e1000_set_phy_type"); 122 DEBUGFUNC("e1000_set_phy_type");
120
121 if (hw->mac_type == e1000_undefined)
122 return -E1000_ERR_PHY_TYPE;
123
124 switch (hw->phy_id) {
125 case M88E1000_E_PHY_ID:
126 case M88E1000_I_PHY_ID:
127 case M88E1011_I_PHY_ID:
128 case M88E1111_I_PHY_ID:
129 hw->phy_type = e1000_phy_m88;
130 break;
131 case IGP01E1000_I_PHY_ID:
132 if (hw->mac_type == e1000_82541 ||
133 hw->mac_type == e1000_82541_rev_2 ||
134 hw->mac_type == e1000_82547 ||
135 hw->mac_type == e1000_82547_rev_2) {
136 hw->phy_type = e1000_phy_igp;
137 break;
138 }
139 default:
140 /* Should never have loaded on this device */
141 hw->phy_type = e1000_phy_undefined;
142 return -E1000_ERR_PHY_TYPE;
143 }
144
145 return E1000_SUCCESS;
146}
147
148/******************************************************************************
149 * IGP phy init script - initializes the GbE PHY
150 *
151 * hw - Struct containing variables accessed by shared code
152 *****************************************************************************/
153static void e1000_phy_init_script(struct e1000_hw *hw)
154{
155 u32 ret_val;
156 u16 phy_saved_data;
157
158 DEBUGFUNC("e1000_phy_init_script");
159
160 if (hw->phy_init_script) {
161 msleep(20);
162
163 /* Save off the current value of register 0x2F5B to be restored at
164 * the end of this routine. */
165 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
166
167 /* Disabled the PHY transmitter */
168 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
169
170 msleep(20);
171
172 e1000_write_phy_reg(hw,0x0000,0x0140);
173
174 msleep(5);
175
176 switch (hw->mac_type) {
177 case e1000_82541:
178 case e1000_82547:
179 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
180
181 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
182
183 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
184 123
185 e1000_write_phy_reg(hw, 0x1F30, 0x1600); 124 if (hw->mac_type == e1000_undefined)
125 return -E1000_ERR_PHY_TYPE;
186 126
187 e1000_write_phy_reg(hw, 0x1F31, 0x0014); 127 switch (hw->phy_id) {
188 128 case M88E1000_E_PHY_ID:
189 e1000_write_phy_reg(hw, 0x1F32, 0x161C); 129 case M88E1000_I_PHY_ID:
190 130 case M88E1011_I_PHY_ID:
191 e1000_write_phy_reg(hw, 0x1F94, 0x0003); 131 case M88E1111_I_PHY_ID:
192 132 hw->phy_type = e1000_phy_m88;
193 e1000_write_phy_reg(hw, 0x1F96, 0x003F); 133 break;
194 134 case IGP01E1000_I_PHY_ID:
195 e1000_write_phy_reg(hw, 0x2010, 0x0008); 135 if (hw->mac_type == e1000_82541 ||
196 break; 136 hw->mac_type == e1000_82541_rev_2 ||
197 137 hw->mac_type == e1000_82547 ||
198 case e1000_82541_rev_2: 138 hw->mac_type == e1000_82547_rev_2) {
199 case e1000_82547_rev_2: 139 hw->phy_type = e1000_phy_igp;
200 e1000_write_phy_reg(hw, 0x1F73, 0x0099); 140 break;
201 break; 141 }
202 default: 142 default:
203 break; 143 /* Should never have loaded on this device */
204 } 144 hw->phy_type = e1000_phy_undefined;
205 145 return -E1000_ERR_PHY_TYPE;
206 e1000_write_phy_reg(hw, 0x0000, 0x3300); 146 }
207
208 msleep(20);
209
210 /* Now enable the transmitter */
211 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
212
213 if (hw->mac_type == e1000_82547) {
214 u16 fused, fine, coarse;
215
216 /* Move to analog registers page */
217 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
218
219 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
220 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
221 147
222 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 148 return E1000_SUCCESS;
223 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 149}
224 150
225 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 151/**
226 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; 152 * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY
227 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 153 * @hw: Struct containing variables accessed by shared code
228 } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 154 */
229 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 155static void e1000_phy_init_script(struct e1000_hw *hw)
156{
157 u32 ret_val;
158 u16 phy_saved_data;
159
160 DEBUGFUNC("e1000_phy_init_script");
161
162 if (hw->phy_init_script) {
163 msleep(20);
164
165 /* Save off the current value of register 0x2F5B to be restored at
166 * the end of this routine. */
167 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
168
169 /* Disabled the PHY transmitter */
170 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
171 msleep(20);
172
173 e1000_write_phy_reg(hw, 0x0000, 0x0140);
174 msleep(5);
175
176 switch (hw->mac_type) {
177 case e1000_82541:
178 case e1000_82547:
179 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
180 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
181 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
182 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
183 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
184 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
185 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
186 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
187 e1000_write_phy_reg(hw, 0x2010, 0x0008);
188 break;
230 189
231 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 190 case e1000_82541_rev_2:
232 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 191 case e1000_82547_rev_2:
233 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 192 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
193 break;
194 default:
195 break;
196 }
234 197
235 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused); 198 e1000_write_phy_reg(hw, 0x0000, 0x3300);
236 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS, 199 msleep(20);
237 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 200
238 } 201 /* Now enable the transmitter */
239 } 202 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
240 } 203
204 if (hw->mac_type == e1000_82547) {
205 u16 fused, fine, coarse;
206
207 /* Move to analog registers page */
208 e1000_read_phy_reg(hw,
209 IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
210 &fused);
211
212 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
213 e1000_read_phy_reg(hw,
214 IGP01E1000_ANALOG_FUSE_STATUS,
215 &fused);
216
217 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
218 coarse =
219 fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
220
221 if (coarse >
222 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
223 coarse -=
224 IGP01E1000_ANALOG_FUSE_COARSE_10;
225 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
226 } else if (coarse ==
227 IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
228 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
229
230 fused =
231 (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
232 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
233 (coarse &
234 IGP01E1000_ANALOG_FUSE_COARSE_MASK);
235
236 e1000_write_phy_reg(hw,
237 IGP01E1000_ANALOG_FUSE_CONTROL,
238 fused);
239 e1000_write_phy_reg(hw,
240 IGP01E1000_ANALOG_FUSE_BYPASS,
241 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
242 }
243 }
244 }
241} 245}
242 246
243/****************************************************************************** 247/**
244 * Set the mac type member in the hw struct. 248 * e1000_set_mac_type - Set the mac type member in the hw struct.
245 * 249 * @hw: Struct containing variables accessed by shared code
246 * hw - Struct containing variables accessed by shared code 250 */
247 *****************************************************************************/
248s32 e1000_set_mac_type(struct e1000_hw *hw) 251s32 e1000_set_mac_type(struct e1000_hw *hw)
249{ 252{
250 DEBUGFUNC("e1000_set_mac_type"); 253 DEBUGFUNC("e1000_set_mac_type");
@@ -348,1801 +351,1850 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
348 return E1000_SUCCESS; 351 return E1000_SUCCESS;
349} 352}
350 353
351/***************************************************************************** 354/**
352 * Set media type and TBI compatibility. 355 * e1000_set_media_type - Set media type and TBI compatibility.
353 * 356 * @hw: Struct containing variables accessed by shared code
354 * hw - Struct containing variables accessed by shared code 357 */
355 * **************************************************************************/
356void e1000_set_media_type(struct e1000_hw *hw) 358void e1000_set_media_type(struct e1000_hw *hw)
357{ 359{
358 u32 status; 360 u32 status;
359 361
360 DEBUGFUNC("e1000_set_media_type"); 362 DEBUGFUNC("e1000_set_media_type");
361 363
362 if (hw->mac_type != e1000_82543) { 364 if (hw->mac_type != e1000_82543) {
363 /* tbi_compatibility is only valid on 82543 */ 365 /* tbi_compatibility is only valid on 82543 */
364 hw->tbi_compatibility_en = false; 366 hw->tbi_compatibility_en = false;
365 } 367 }
366 368
367 switch (hw->device_id) { 369 switch (hw->device_id) {
368 case E1000_DEV_ID_82545GM_SERDES: 370 case E1000_DEV_ID_82545GM_SERDES:
369 case E1000_DEV_ID_82546GB_SERDES: 371 case E1000_DEV_ID_82546GB_SERDES:
370 hw->media_type = e1000_media_type_internal_serdes; 372 hw->media_type = e1000_media_type_internal_serdes;
371 break; 373 break;
372 default: 374 default:
373 switch (hw->mac_type) { 375 switch (hw->mac_type) {
374 case e1000_82542_rev2_0: 376 case e1000_82542_rev2_0:
375 case e1000_82542_rev2_1: 377 case e1000_82542_rev2_1:
376 hw->media_type = e1000_media_type_fiber; 378 hw->media_type = e1000_media_type_fiber;
377 break; 379 break;
378 default: 380 default:
379 status = er32(STATUS); 381 status = er32(STATUS);
380 if (status & E1000_STATUS_TBIMODE) { 382 if (status & E1000_STATUS_TBIMODE) {
381 hw->media_type = e1000_media_type_fiber; 383 hw->media_type = e1000_media_type_fiber;
382 /* tbi_compatibility not valid on fiber */ 384 /* tbi_compatibility not valid on fiber */
383 hw->tbi_compatibility_en = false; 385 hw->tbi_compatibility_en = false;
384 } else { 386 } else {
385 hw->media_type = e1000_media_type_copper; 387 hw->media_type = e1000_media_type_copper;
386 } 388 }
387 break; 389 break;
388 } 390 }
389 } 391 }
390} 392}
391 393
392/****************************************************************************** 394/**
393 * Reset the transmit and receive units; mask and clear all interrupts. 395 * e1000_reset_hw: reset the hardware completely
396 * @hw: Struct containing variables accessed by shared code
394 * 397 *
395 * hw - Struct containing variables accessed by shared code 398 * Reset the transmit and receive units; mask and clear all interrupts.
396 *****************************************************************************/ 399 */
397s32 e1000_reset_hw(struct e1000_hw *hw) 400s32 e1000_reset_hw(struct e1000_hw *hw)
398{ 401{
399 u32 ctrl; 402 u32 ctrl;
400 u32 ctrl_ext; 403 u32 ctrl_ext;
401 u32 icr; 404 u32 icr;
402 u32 manc; 405 u32 manc;
403 u32 led_ctrl; 406 u32 led_ctrl;
404 s32 ret_val; 407 s32 ret_val;
405 408
406 DEBUGFUNC("e1000_reset_hw"); 409 DEBUGFUNC("e1000_reset_hw");
407 410
408 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 411 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
409 if (hw->mac_type == e1000_82542_rev2_0) { 412 if (hw->mac_type == e1000_82542_rev2_0) {
410 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 413 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
411 e1000_pci_clear_mwi(hw); 414 e1000_pci_clear_mwi(hw);
412 } 415 }
413 416
414 /* Clear interrupt mask to stop board from generating interrupts */ 417 /* Clear interrupt mask to stop board from generating interrupts */
415 DEBUGOUT("Masking off all interrupts\n"); 418 DEBUGOUT("Masking off all interrupts\n");
416 ew32(IMC, 0xffffffff); 419 ew32(IMC, 0xffffffff);
417 420
418 /* Disable the Transmit and Receive units. Then delay to allow 421 /* Disable the Transmit and Receive units. Then delay to allow
419 * any pending transactions to complete before we hit the MAC with 422 * any pending transactions to complete before we hit the MAC with
420 * the global reset. 423 * the global reset.
421 */ 424 */
422 ew32(RCTL, 0); 425 ew32(RCTL, 0);
423 ew32(TCTL, E1000_TCTL_PSP); 426 ew32(TCTL, E1000_TCTL_PSP);
424 E1000_WRITE_FLUSH(); 427 E1000_WRITE_FLUSH();
425 428
426 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ 429 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
427 hw->tbi_compatibility_on = false; 430 hw->tbi_compatibility_on = false;
428 431
429 /* Delay to allow any outstanding PCI transactions to complete before 432 /* Delay to allow any outstanding PCI transactions to complete before
430 * resetting the device 433 * resetting the device
431 */ 434 */
432 msleep(10); 435 msleep(10);
433 436
434 ctrl = er32(CTRL); 437 ctrl = er32(CTRL);
435 438
436 /* Must reset the PHY before resetting the MAC */ 439 /* Must reset the PHY before resetting the MAC */
437 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 440 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
438 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST)); 441 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
439 msleep(5); 442 msleep(5);
440 } 443 }
441 444
442 /* Issue a global reset to the MAC. This will reset the chip's 445 /* Issue a global reset to the MAC. This will reset the chip's
443 * transmit, receive, DMA, and link units. It will not effect 446 * transmit, receive, DMA, and link units. It will not effect
444 * the current PCI configuration. The global reset bit is self- 447 * the current PCI configuration. The global reset bit is self-
445 * clearing, and should clear within a microsecond. 448 * clearing, and should clear within a microsecond.
446 */ 449 */
447 DEBUGOUT("Issuing a global reset to MAC\n"); 450 DEBUGOUT("Issuing a global reset to MAC\n");
448 451
449 switch (hw->mac_type) { 452 switch (hw->mac_type) {
450 case e1000_82544: 453 case e1000_82544:
451 case e1000_82540: 454 case e1000_82540:
452 case e1000_82545: 455 case e1000_82545:
453 case e1000_82546: 456 case e1000_82546:
454 case e1000_82541: 457 case e1000_82541:
455 case e1000_82541_rev_2: 458 case e1000_82541_rev_2:
456 /* These controllers can't ack the 64-bit write when issuing the 459 /* These controllers can't ack the 64-bit write when issuing the
457 * reset, so use IO-mapping as a workaround to issue the reset */ 460 * reset, so use IO-mapping as a workaround to issue the reset */
458 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); 461 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
459 break; 462 break;
460 case e1000_82545_rev_3: 463 case e1000_82545_rev_3:
461 case e1000_82546_rev_3: 464 case e1000_82546_rev_3:
462 /* Reset is performed on a shadow of the control register */ 465 /* Reset is performed on a shadow of the control register */
463 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST)); 466 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
464 break; 467 break;
465 default: 468 default:
466 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 469 ew32(CTRL, (ctrl | E1000_CTRL_RST));
467 break; 470 break;
468 } 471 }
469 472
470 /* After MAC reset, force reload of EEPROM to restore power-on settings to 473 /* After MAC reset, force reload of EEPROM to restore power-on settings to
471 * device. Later controllers reload the EEPROM automatically, so just wait 474 * device. Later controllers reload the EEPROM automatically, so just wait
472 * for reload to complete. 475 * for reload to complete.
473 */ 476 */
474 switch (hw->mac_type) { 477 switch (hw->mac_type) {
475 case e1000_82542_rev2_0: 478 case e1000_82542_rev2_0:
476 case e1000_82542_rev2_1: 479 case e1000_82542_rev2_1:
477 case e1000_82543: 480 case e1000_82543:
478 case e1000_82544: 481 case e1000_82544:
479 /* Wait for reset to complete */ 482 /* Wait for reset to complete */
480 udelay(10); 483 udelay(10);
481 ctrl_ext = er32(CTRL_EXT); 484 ctrl_ext = er32(CTRL_EXT);
482 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 485 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
483 ew32(CTRL_EXT, ctrl_ext); 486 ew32(CTRL_EXT, ctrl_ext);
484 E1000_WRITE_FLUSH(); 487 E1000_WRITE_FLUSH();
485 /* Wait for EEPROM reload */ 488 /* Wait for EEPROM reload */
486 msleep(2); 489 msleep(2);
487 break; 490 break;
488 case e1000_82541: 491 case e1000_82541:
489 case e1000_82541_rev_2: 492 case e1000_82541_rev_2:
490 case e1000_82547: 493 case e1000_82547:
491 case e1000_82547_rev_2: 494 case e1000_82547_rev_2:
492 /* Wait for EEPROM reload */ 495 /* Wait for EEPROM reload */
493 msleep(20); 496 msleep(20);
494 break; 497 break;
495 default: 498 default:
496 /* Auto read done will delay 5ms or poll based on mac type */ 499 /* Auto read done will delay 5ms or poll based on mac type */
497 ret_val = e1000_get_auto_rd_done(hw); 500 ret_val = e1000_get_auto_rd_done(hw);
498 if (ret_val) 501 if (ret_val)
499 return ret_val; 502 return ret_val;
500 break; 503 break;
501 } 504 }
502 505
503 /* Disable HW ARPs on ASF enabled adapters */ 506 /* Disable HW ARPs on ASF enabled adapters */
504 if (hw->mac_type >= e1000_82540) { 507 if (hw->mac_type >= e1000_82540) {
505 manc = er32(MANC); 508 manc = er32(MANC);
506 manc &= ~(E1000_MANC_ARP_EN); 509 manc &= ~(E1000_MANC_ARP_EN);
507 ew32(MANC, manc); 510 ew32(MANC, manc);
508 } 511 }
509 512
510 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 513 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
511 e1000_phy_init_script(hw); 514 e1000_phy_init_script(hw);
512 515
513 /* Configure activity LED after PHY reset */ 516 /* Configure activity LED after PHY reset */
514 led_ctrl = er32(LEDCTL); 517 led_ctrl = er32(LEDCTL);
515 led_ctrl &= IGP_ACTIVITY_LED_MASK; 518 led_ctrl &= IGP_ACTIVITY_LED_MASK;
516 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 519 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
517 ew32(LEDCTL, led_ctrl); 520 ew32(LEDCTL, led_ctrl);
518 } 521 }
519 522
520 /* Clear interrupt mask to stop board from generating interrupts */ 523 /* Clear interrupt mask to stop board from generating interrupts */
521 DEBUGOUT("Masking off all interrupts\n"); 524 DEBUGOUT("Masking off all interrupts\n");
522 ew32(IMC, 0xffffffff); 525 ew32(IMC, 0xffffffff);
523 526
524 /* Clear any pending interrupt events. */ 527 /* Clear any pending interrupt events. */
525 icr = er32(ICR); 528 icr = er32(ICR);
526 529
527 /* If MWI was previously enabled, reenable it. */ 530 /* If MWI was previously enabled, reenable it. */
528 if (hw->mac_type == e1000_82542_rev2_0) { 531 if (hw->mac_type == e1000_82542_rev2_0) {
529 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) 532 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
530 e1000_pci_set_mwi(hw); 533 e1000_pci_set_mwi(hw);
531 } 534 }
532 535
533 return E1000_SUCCESS; 536 return E1000_SUCCESS;
534} 537}
535 538
536/****************************************************************************** 539/**
537 * Performs basic configuration of the adapter. 540 * e1000_init_hw: Performs basic configuration of the adapter.
538 * 541 * @hw: Struct containing variables accessed by shared code
539 * hw - Struct containing variables accessed by shared code
540 * 542 *
541 * Assumes that the controller has previously been reset and is in a 543 * Assumes that the controller has previously been reset and is in a
542 * post-reset uninitialized state. Initializes the receive address registers, 544 * post-reset uninitialized state. Initializes the receive address registers,
543 * multicast table, and VLAN filter table. Calls routines to setup link 545 * multicast table, and VLAN filter table. Calls routines to setup link
544 * configuration and flow control settings. Clears all on-chip counters. Leaves 546 * configuration and flow control settings. Clears all on-chip counters. Leaves
545 * the transmit and receive units disabled and uninitialized. 547 * the transmit and receive units disabled and uninitialized.
546 *****************************************************************************/ 548 */
547s32 e1000_init_hw(struct e1000_hw *hw) 549s32 e1000_init_hw(struct e1000_hw *hw)
548{ 550{
549 u32 ctrl; 551 u32 ctrl;
550 u32 i; 552 u32 i;
551 s32 ret_val; 553 s32 ret_val;
552 u32 mta_size; 554 u32 mta_size;
553 u32 ctrl_ext; 555 u32 ctrl_ext;
554 556
555 DEBUGFUNC("e1000_init_hw"); 557 DEBUGFUNC("e1000_init_hw");
556 558
557 /* Initialize Identification LED */ 559 /* Initialize Identification LED */
558 ret_val = e1000_id_led_init(hw); 560 ret_val = e1000_id_led_init(hw);
559 if (ret_val) { 561 if (ret_val) {
560 DEBUGOUT("Error Initializing Identification LED\n"); 562 DEBUGOUT("Error Initializing Identification LED\n");
561 return ret_val; 563 return ret_val;
562 } 564 }
563 565
564 /* Set the media type and TBI compatibility */ 566 /* Set the media type and TBI compatibility */
565 e1000_set_media_type(hw); 567 e1000_set_media_type(hw);
566 568
567 /* Disabling VLAN filtering. */ 569 /* Disabling VLAN filtering. */
568 DEBUGOUT("Initializing the IEEE VLAN\n"); 570 DEBUGOUT("Initializing the IEEE VLAN\n");
569 if (hw->mac_type < e1000_82545_rev_3) 571 if (hw->mac_type < e1000_82545_rev_3)
570 ew32(VET, 0); 572 ew32(VET, 0);
571 e1000_clear_vfta(hw); 573 e1000_clear_vfta(hw);
572 574
573 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 575 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
574 if (hw->mac_type == e1000_82542_rev2_0) { 576 if (hw->mac_type == e1000_82542_rev2_0) {
575 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 577 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
576 e1000_pci_clear_mwi(hw); 578 e1000_pci_clear_mwi(hw);
577 ew32(RCTL, E1000_RCTL_RST); 579 ew32(RCTL, E1000_RCTL_RST);
578 E1000_WRITE_FLUSH(); 580 E1000_WRITE_FLUSH();
579 msleep(5); 581 msleep(5);
580 } 582 }
581 583
582 /* Setup the receive address. This involves initializing all of the Receive 584 /* Setup the receive address. This involves initializing all of the Receive
583 * Address Registers (RARs 0 - 15). 585 * Address Registers (RARs 0 - 15).
584 */ 586 */
585 e1000_init_rx_addrs(hw); 587 e1000_init_rx_addrs(hw);
586 588
587 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 589 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
588 if (hw->mac_type == e1000_82542_rev2_0) { 590 if (hw->mac_type == e1000_82542_rev2_0) {
589 ew32(RCTL, 0); 591 ew32(RCTL, 0);
590 E1000_WRITE_FLUSH(); 592 E1000_WRITE_FLUSH();
591 msleep(1); 593 msleep(1);
592 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) 594 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
593 e1000_pci_set_mwi(hw); 595 e1000_pci_set_mwi(hw);
594 } 596 }
595 597
596 /* Zero out the Multicast HASH table */ 598 /* Zero out the Multicast HASH table */
597 DEBUGOUT("Zeroing the MTA\n"); 599 DEBUGOUT("Zeroing the MTA\n");
598 mta_size = E1000_MC_TBL_SIZE; 600 mta_size = E1000_MC_TBL_SIZE;
599 for (i = 0; i < mta_size; i++) { 601 for (i = 0; i < mta_size; i++) {
600 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 602 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
601 /* use write flush to prevent Memory Write Block (MWB) from 603 /* use write flush to prevent Memory Write Block (MWB) from
602 * occuring when accessing our register space */ 604 * occurring when accessing our register space */
603 E1000_WRITE_FLUSH(); 605 E1000_WRITE_FLUSH();
604 } 606 }
605 607
606 /* Set the PCI priority bit correctly in the CTRL register. This 608 /* Set the PCI priority bit correctly in the CTRL register. This
607 * determines if the adapter gives priority to receives, or if it 609 * determines if the adapter gives priority to receives, or if it
608 * gives equal priority to transmits and receives. Valid only on 610 * gives equal priority to transmits and receives. Valid only on
609 * 82542 and 82543 silicon. 611 * 82542 and 82543 silicon.
610 */ 612 */
611 if (hw->dma_fairness && hw->mac_type <= e1000_82543) { 613 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
612 ctrl = er32(CTRL); 614 ctrl = er32(CTRL);
613 ew32(CTRL, ctrl | E1000_CTRL_PRIOR); 615 ew32(CTRL, ctrl | E1000_CTRL_PRIOR);
614 } 616 }
615 617
616 switch (hw->mac_type) { 618 switch (hw->mac_type) {
617 case e1000_82545_rev_3: 619 case e1000_82545_rev_3:
618 case e1000_82546_rev_3: 620 case e1000_82546_rev_3:
619 break; 621 break;
620 default: 622 default:
621 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ 623 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
622 if (hw->bus_type == e1000_bus_type_pcix && e1000_pcix_get_mmrbc(hw) > 2048) 624 if (hw->bus_type == e1000_bus_type_pcix
623 e1000_pcix_set_mmrbc(hw, 2048); 625 && e1000_pcix_get_mmrbc(hw) > 2048)
624 break; 626 e1000_pcix_set_mmrbc(hw, 2048);
625 } 627 break;
626 628 }
627 /* Call a subroutine to configure the link and setup flow control. */ 629
628 ret_val = e1000_setup_link(hw); 630 /* Call a subroutine to configure the link and setup flow control. */
629 631 ret_val = e1000_setup_link(hw);
630 /* Set the transmit descriptor write-back policy */ 632
631 if (hw->mac_type > e1000_82544) { 633 /* Set the transmit descriptor write-back policy */
632 ctrl = er32(TXDCTL); 634 if (hw->mac_type > e1000_82544) {
633 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; 635 ctrl = er32(TXDCTL);
634 ew32(TXDCTL, ctrl); 636 ctrl =
635 } 637 (ctrl & ~E1000_TXDCTL_WTHRESH) |
636 638 E1000_TXDCTL_FULL_TX_DESC_WB;
637 /* Clear all of the statistics registers (clear on read). It is 639 ew32(TXDCTL, ctrl);
638 * important that we do this after we have tried to establish link 640 }
639 * because the symbol error count will increment wildly if there 641
640 * is no link. 642 /* Clear all of the statistics registers (clear on read). It is
641 */ 643 * important that we do this after we have tried to establish link
642 e1000_clear_hw_cntrs(hw); 644 * because the symbol error count will increment wildly if there
643 645 * is no link.
644 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 646 */
645 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 647 e1000_clear_hw_cntrs(hw);
646 ctrl_ext = er32(CTRL_EXT); 648
647 /* Relaxed ordering must be disabled to avoid a parity 649 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
648 * error crash in a PCI slot. */ 650 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
649 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 651 ctrl_ext = er32(CTRL_EXT);
650 ew32(CTRL_EXT, ctrl_ext); 652 /* Relaxed ordering must be disabled to avoid a parity
651 } 653 * error crash in a PCI slot. */
652 654 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
653 return ret_val; 655 ew32(CTRL_EXT, ctrl_ext);
656 }
657
658 return ret_val;
654} 659}
655 660
656/****************************************************************************** 661/**
657 * Adjust SERDES output amplitude based on EEPROM setting. 662 * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting.
658 * 663 * @hw: Struct containing variables accessed by shared code.
659 * hw - Struct containing variables accessed by shared code. 664 */
660 *****************************************************************************/
661static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw) 665static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
662{ 666{
663 u16 eeprom_data; 667 u16 eeprom_data;
664 s32 ret_val; 668 s32 ret_val;
665 669
666 DEBUGFUNC("e1000_adjust_serdes_amplitude"); 670 DEBUGFUNC("e1000_adjust_serdes_amplitude");
667 671
668 if (hw->media_type != e1000_media_type_internal_serdes) 672 if (hw->media_type != e1000_media_type_internal_serdes)
669 return E1000_SUCCESS; 673 return E1000_SUCCESS;
670 674
671 switch (hw->mac_type) { 675 switch (hw->mac_type) {
672 case e1000_82545_rev_3: 676 case e1000_82545_rev_3:
673 case e1000_82546_rev_3: 677 case e1000_82546_rev_3:
674 break; 678 break;
675 default: 679 default:
676 return E1000_SUCCESS; 680 return E1000_SUCCESS;
677 } 681 }
678 682
679 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); 683 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
680 if (ret_val) { 684 &eeprom_data);
681 return ret_val; 685 if (ret_val) {
682 } 686 return ret_val;
683 687 }
684 if (eeprom_data != EEPROM_RESERVED_WORD) { 688
685 /* Adjust SERDES output amplitude only. */ 689 if (eeprom_data != EEPROM_RESERVED_WORD) {
686 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; 690 /* Adjust SERDES output amplitude only. */
687 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); 691 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
688 if (ret_val) 692 ret_val =
689 return ret_val; 693 e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
690 } 694 if (ret_val)
691 695 return ret_val;
692 return E1000_SUCCESS; 696 }
697
698 return E1000_SUCCESS;
693} 699}
694 700
695/****************************************************************************** 701/**
696 * Configures flow control and link settings. 702 * e1000_setup_link - Configures flow control and link settings.
697 * 703 * @hw: Struct containing variables accessed by shared code
698 * hw - Struct containing variables accessed by shared code
699 * 704 *
700 * Determines which flow control settings to use. Calls the apropriate media- 705 * Determines which flow control settings to use. Calls the appropriate media-
701 * specific link configuration function. Configures the flow control settings. 706 * specific link configuration function. Configures the flow control settings.
702 * Assuming the adapter has a valid link partner, a valid link should be 707 * Assuming the adapter has a valid link partner, a valid link should be
703 * established. Assumes the hardware has previously been reset and the 708 * established. Assumes the hardware has previously been reset and the
704 * transmitter and receiver are not enabled. 709 * transmitter and receiver are not enabled.
705 *****************************************************************************/ 710 */
706s32 e1000_setup_link(struct e1000_hw *hw) 711s32 e1000_setup_link(struct e1000_hw *hw)
707{ 712{
708 u32 ctrl_ext; 713 u32 ctrl_ext;
709 s32 ret_val; 714 s32 ret_val;
710 u16 eeprom_data; 715 u16 eeprom_data;
711 716
712 DEBUGFUNC("e1000_setup_link"); 717 DEBUGFUNC("e1000_setup_link");
713 718
714 /* Read and store word 0x0F of the EEPROM. This word contains bits 719 /* Read and store word 0x0F of the EEPROM. This word contains bits
715 * that determine the hardware's default PAUSE (flow control) mode, 720 * that determine the hardware's default PAUSE (flow control) mode,
716 * a bit that determines whether the HW defaults to enabling or 721 * a bit that determines whether the HW defaults to enabling or
717 * disabling auto-negotiation, and the direction of the 722 * disabling auto-negotiation, and the direction of the
718 * SW defined pins. If there is no SW over-ride of the flow 723 * SW defined pins. If there is no SW over-ride of the flow
719 * control setting, then the variable hw->fc will 724 * control setting, then the variable hw->fc will
720 * be initialized based on a value in the EEPROM. 725 * be initialized based on a value in the EEPROM.
721 */ 726 */
722 if (hw->fc == E1000_FC_DEFAULT) { 727 if (hw->fc == E1000_FC_DEFAULT) {
723 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 728 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
724 1, &eeprom_data); 729 1, &eeprom_data);
725 if (ret_val) { 730 if (ret_val) {
726 DEBUGOUT("EEPROM Read Error\n"); 731 DEBUGOUT("EEPROM Read Error\n");
727 return -E1000_ERR_EEPROM; 732 return -E1000_ERR_EEPROM;
728 } 733 }
729 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 734 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
730 hw->fc = E1000_FC_NONE; 735 hw->fc = E1000_FC_NONE;
731 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 736 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
732 EEPROM_WORD0F_ASM_DIR) 737 EEPROM_WORD0F_ASM_DIR)
733 hw->fc = E1000_FC_TX_PAUSE; 738 hw->fc = E1000_FC_TX_PAUSE;
734 else 739 else
735 hw->fc = E1000_FC_FULL; 740 hw->fc = E1000_FC_FULL;
736 } 741 }
737 742
738 /* We want to save off the original Flow Control configuration just 743 /* We want to save off the original Flow Control configuration just
739 * in case we get disconnected and then reconnected into a different 744 * in case we get disconnected and then reconnected into a different
740 * hub or switch with different Flow Control capabilities. 745 * hub or switch with different Flow Control capabilities.
741 */ 746 */
742 if (hw->mac_type == e1000_82542_rev2_0) 747 if (hw->mac_type == e1000_82542_rev2_0)
743 hw->fc &= (~E1000_FC_TX_PAUSE); 748 hw->fc &= (~E1000_FC_TX_PAUSE);
744 749
745 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) 750 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
746 hw->fc &= (~E1000_FC_RX_PAUSE); 751 hw->fc &= (~E1000_FC_RX_PAUSE);
747 752
748 hw->original_fc = hw->fc; 753 hw->original_fc = hw->fc;
749 754
750 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); 755 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
751 756
752 /* Take the 4 bits from EEPROM word 0x0F that determine the initial 757 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
753 * polarity value for the SW controlled pins, and setup the 758 * polarity value for the SW controlled pins, and setup the
754 * Extended Device Control reg with that info. 759 * Extended Device Control reg with that info.
755 * This is needed because one of the SW controlled pins is used for 760 * This is needed because one of the SW controlled pins is used for
756 * signal detection. So this should be done before e1000_setup_pcs_link() 761 * signal detection. So this should be done before e1000_setup_pcs_link()
757 * or e1000_phy_setup() is called. 762 * or e1000_phy_setup() is called.
758 */ 763 */
759 if (hw->mac_type == e1000_82543) { 764 if (hw->mac_type == e1000_82543) {
760 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 765 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
761 1, &eeprom_data); 766 1, &eeprom_data);
762 if (ret_val) { 767 if (ret_val) {
763 DEBUGOUT("EEPROM Read Error\n"); 768 DEBUGOUT("EEPROM Read Error\n");
764 return -E1000_ERR_EEPROM; 769 return -E1000_ERR_EEPROM;
765 } 770 }
766 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 771 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
767 SWDPIO__EXT_SHIFT); 772 SWDPIO__EXT_SHIFT);
768 ew32(CTRL_EXT, ctrl_ext); 773 ew32(CTRL_EXT, ctrl_ext);
769 } 774 }
770 775
771 /* Call the necessary subroutine to configure the link. */ 776 /* Call the necessary subroutine to configure the link. */
772 ret_val = (hw->media_type == e1000_media_type_copper) ? 777 ret_val = (hw->media_type == e1000_media_type_copper) ?
773 e1000_setup_copper_link(hw) : 778 e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw);
774 e1000_setup_fiber_serdes_link(hw); 779
775 780 /* Initialize the flow control address, type, and PAUSE timer
776 /* Initialize the flow control address, type, and PAUSE timer 781 * registers to their default values. This is done even if flow
777 * registers to their default values. This is done even if flow 782 * control is disabled, because it does not hurt anything to
778 * control is disabled, because it does not hurt anything to 783 * initialize these registers.
779 * initialize these registers. 784 */
780 */ 785 DEBUGOUT
781 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 786 ("Initializing the Flow Control address, type and timer regs\n");
782 787
783 ew32(FCT, FLOW_CONTROL_TYPE); 788 ew32(FCT, FLOW_CONTROL_TYPE);
784 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); 789 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
785 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); 790 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
786 791
787 ew32(FCTTV, hw->fc_pause_time); 792 ew32(FCTTV, hw->fc_pause_time);
788 793
789 /* Set the flow control receive threshold registers. Normally, 794 /* Set the flow control receive threshold registers. Normally,
790 * these registers will be set to a default threshold that may be 795 * these registers will be set to a default threshold that may be
791 * adjusted later by the driver's runtime code. However, if the 796 * adjusted later by the driver's runtime code. However, if the
792 * ability to transmit pause frames in not enabled, then these 797 * ability to transmit pause frames in not enabled, then these
793 * registers will be set to 0. 798 * registers will be set to 0.
794 */ 799 */
795 if (!(hw->fc & E1000_FC_TX_PAUSE)) { 800 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
796 ew32(FCRTL, 0); 801 ew32(FCRTL, 0);
797 ew32(FCRTH, 0); 802 ew32(FCRTH, 0);
798 } else { 803 } else {
799 /* We need to set up the Receive Threshold high and low water marks 804 /* We need to set up the Receive Threshold high and low water marks
800 * as well as (optionally) enabling the transmission of XON frames. 805 * as well as (optionally) enabling the transmission of XON frames.
801 */ 806 */
802 if (hw->fc_send_xon) { 807 if (hw->fc_send_xon) {
803 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); 808 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
804 ew32(FCRTH, hw->fc_high_water); 809 ew32(FCRTH, hw->fc_high_water);
805 } else { 810 } else {
806 ew32(FCRTL, hw->fc_low_water); 811 ew32(FCRTL, hw->fc_low_water);
807 ew32(FCRTH, hw->fc_high_water); 812 ew32(FCRTH, hw->fc_high_water);
808 } 813 }
809 } 814 }
810 return ret_val; 815 return ret_val;
811} 816}
812 817
813/****************************************************************************** 818/**
814 * Sets up link for a fiber based or serdes based adapter 819 * e1000_setup_fiber_serdes_link - prepare fiber or serdes link
815 * 820 * @hw: Struct containing variables accessed by shared code
816 * hw - Struct containing variables accessed by shared code
817 * 821 *
818 * Manipulates Physical Coding Sublayer functions in order to configure 822 * Manipulates Physical Coding Sublayer functions in order to configure
819 * link. Assumes the hardware has been previously reset and the transmitter 823 * link. Assumes the hardware has been previously reset and the transmitter
820 * and receiver are not enabled. 824 * and receiver are not enabled.
821 *****************************************************************************/ 825 */
822static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw) 826static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
823{ 827{
824 u32 ctrl; 828 u32 ctrl;
825 u32 status; 829 u32 status;
826 u32 txcw = 0; 830 u32 txcw = 0;
827 u32 i; 831 u32 i;
828 u32 signal = 0; 832 u32 signal = 0;
829 s32 ret_val; 833 s32 ret_val;
830 834
831 DEBUGFUNC("e1000_setup_fiber_serdes_link"); 835 DEBUGFUNC("e1000_setup_fiber_serdes_link");
832 836
833 /* On adapters with a MAC newer than 82544, SWDP 1 will be 837 /* On adapters with a MAC newer than 82544, SWDP 1 will be
834 * set when the optics detect a signal. On older adapters, it will be 838 * set when the optics detect a signal. On older adapters, it will be
835 * cleared when there is a signal. This applies to fiber media only. 839 * cleared when there is a signal. This applies to fiber media only.
836 * If we're on serdes media, adjust the output amplitude to value 840 * If we're on serdes media, adjust the output amplitude to value
837 * set in the EEPROM. 841 * set in the EEPROM.
838 */ 842 */
839 ctrl = er32(CTRL); 843 ctrl = er32(CTRL);
840 if (hw->media_type == e1000_media_type_fiber) 844 if (hw->media_type == e1000_media_type_fiber)
841 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 845 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
842 846
843 ret_val = e1000_adjust_serdes_amplitude(hw); 847 ret_val = e1000_adjust_serdes_amplitude(hw);
844 if (ret_val) 848 if (ret_val)
845 return ret_val; 849 return ret_val;
846 850
847 /* Take the link out of reset */ 851 /* Take the link out of reset */
848 ctrl &= ~(E1000_CTRL_LRST); 852 ctrl &= ~(E1000_CTRL_LRST);
849 853
850 /* Adjust VCO speed to improve BER performance */ 854 /* Adjust VCO speed to improve BER performance */
851 ret_val = e1000_set_vco_speed(hw); 855 ret_val = e1000_set_vco_speed(hw);
852 if (ret_val) 856 if (ret_val)
853 return ret_val; 857 return ret_val;
854 858
855 e1000_config_collision_dist(hw); 859 e1000_config_collision_dist(hw);
856 860
857 /* Check for a software override of the flow control settings, and setup 861 /* Check for a software override of the flow control settings, and setup
858 * the device accordingly. If auto-negotiation is enabled, then software 862 * the device accordingly. If auto-negotiation is enabled, then software
859 * will have to set the "PAUSE" bits to the correct value in the Tranmsit 863 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
860 * Config Word Register (TXCW) and re-start auto-negotiation. However, if 864 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
861 * auto-negotiation is disabled, then software will have to manually 865 * auto-negotiation is disabled, then software will have to manually
862 * configure the two flow control enable bits in the CTRL register. 866 * configure the two flow control enable bits in the CTRL register.
863 * 867 *
864 * The possible values of the "fc" parameter are: 868 * The possible values of the "fc" parameter are:
865 * 0: Flow control is completely disabled 869 * 0: Flow control is completely disabled
866 * 1: Rx flow control is enabled (we can receive pause frames, but 870 * 1: Rx flow control is enabled (we can receive pause frames, but
867 * not send pause frames). 871 * not send pause frames).
868 * 2: Tx flow control is enabled (we can send pause frames but we do 872 * 2: Tx flow control is enabled (we can send pause frames but we do
869 * not support receiving pause frames). 873 * not support receiving pause frames).
870 * 3: Both Rx and TX flow control (symmetric) are enabled. 874 * 3: Both Rx and TX flow control (symmetric) are enabled.
871 */ 875 */
872 switch (hw->fc) { 876 switch (hw->fc) {
873 case E1000_FC_NONE: 877 case E1000_FC_NONE:
874 /* Flow control is completely disabled by a software over-ride. */ 878 /* Flow control is completely disabled by a software over-ride. */
875 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 879 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
876 break; 880 break;
877 case E1000_FC_RX_PAUSE: 881 case E1000_FC_RX_PAUSE:
878 /* RX Flow control is enabled and TX Flow control is disabled by a 882 /* RX Flow control is enabled and TX Flow control is disabled by a
879 * software over-ride. Since there really isn't a way to advertise 883 * software over-ride. Since there really isn't a way to advertise
880 * that we are capable of RX Pause ONLY, we will advertise that we 884 * that we are capable of RX Pause ONLY, we will advertise that we
881 * support both symmetric and asymmetric RX PAUSE. Later, we will 885 * support both symmetric and asymmetric RX PAUSE. Later, we will
882 * disable the adapter's ability to send PAUSE frames. 886 * disable the adapter's ability to send PAUSE frames.
883 */ 887 */
884 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 888 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
885 break; 889 break;
886 case E1000_FC_TX_PAUSE: 890 case E1000_FC_TX_PAUSE:
887 /* TX Flow control is enabled, and RX Flow control is disabled, by a 891 /* TX Flow control is enabled, and RX Flow control is disabled, by a
888 * software over-ride. 892 * software over-ride.
889 */ 893 */
890 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 894 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
891 break; 895 break;
892 case E1000_FC_FULL: 896 case E1000_FC_FULL:
893 /* Flow control (both RX and TX) is enabled by a software over-ride. */ 897 /* Flow control (both RX and TX) is enabled by a software over-ride. */
894 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 898 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
895 break; 899 break;
896 default: 900 default:
897 DEBUGOUT("Flow control param set incorrectly\n"); 901 DEBUGOUT("Flow control param set incorrectly\n");
898 return -E1000_ERR_CONFIG; 902 return -E1000_ERR_CONFIG;
899 break; 903 break;
900 } 904 }
901 905
902 /* Since auto-negotiation is enabled, take the link out of reset (the link 906 /* Since auto-negotiation is enabled, take the link out of reset (the link
903 * will be in reset, because we previously reset the chip). This will 907 * will be in reset, because we previously reset the chip). This will
904 * restart auto-negotiation. If auto-neogtiation is successful then the 908 * restart auto-negotiation. If auto-negotiation is successful then the
905 * link-up status bit will be set and the flow control enable bits (RFCE 909 * link-up status bit will be set and the flow control enable bits (RFCE
906 * and TFCE) will be set according to their negotiated value. 910 * and TFCE) will be set according to their negotiated value.
907 */ 911 */
908 DEBUGOUT("Auto-negotiation enabled\n"); 912 DEBUGOUT("Auto-negotiation enabled\n");
909 913
910 ew32(TXCW, txcw); 914 ew32(TXCW, txcw);
911 ew32(CTRL, ctrl); 915 ew32(CTRL, ctrl);
912 E1000_WRITE_FLUSH(); 916 E1000_WRITE_FLUSH();
913 917
914 hw->txcw = txcw; 918 hw->txcw = txcw;
915 msleep(1); 919 msleep(1);
916 920
917 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" 921 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
918 * indication in the Device Status Register. Time-out if a link isn't 922 * indication in the Device Status Register. Time-out if a link isn't
919 * seen in 500 milliseconds seconds (Auto-negotiation should complete in 923 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
920 * less than 500 milliseconds even if the other end is doing it in SW). 924 * less than 500 milliseconds even if the other end is doing it in SW).
921 * For internal serdes, we just assume a signal is present, then poll. 925 * For internal serdes, we just assume a signal is present, then poll.
922 */ 926 */
923 if (hw->media_type == e1000_media_type_internal_serdes || 927 if (hw->media_type == e1000_media_type_internal_serdes ||
924 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) { 928 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {
925 DEBUGOUT("Looking for Link\n"); 929 DEBUGOUT("Looking for Link\n");
926 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 930 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
927 msleep(10); 931 msleep(10);
928 status = er32(STATUS); 932 status = er32(STATUS);
929 if (status & E1000_STATUS_LU) break; 933 if (status & E1000_STATUS_LU)
930 } 934 break;
931 if (i == (LINK_UP_TIMEOUT / 10)) { 935 }
932 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 936 if (i == (LINK_UP_TIMEOUT / 10)) {
933 hw->autoneg_failed = 1; 937 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
934 /* AutoNeg failed to achieve a link, so we'll call 938 hw->autoneg_failed = 1;
935 * e1000_check_for_link. This routine will force the link up if 939 /* AutoNeg failed to achieve a link, so we'll call
936 * we detect a signal. This will allow us to communicate with 940 * e1000_check_for_link. This routine will force the link up if
937 * non-autonegotiating link partners. 941 * we detect a signal. This will allow us to communicate with
938 */ 942 * non-autonegotiating link partners.
939 ret_val = e1000_check_for_link(hw); 943 */
940 if (ret_val) { 944 ret_val = e1000_check_for_link(hw);
941 DEBUGOUT("Error while checking for link\n"); 945 if (ret_val) {
942 return ret_val; 946 DEBUGOUT("Error while checking for link\n");
943 } 947 return ret_val;
944 hw->autoneg_failed = 0; 948 }
945 } else { 949 hw->autoneg_failed = 0;
946 hw->autoneg_failed = 0; 950 } else {
947 DEBUGOUT("Valid Link Found\n"); 951 hw->autoneg_failed = 0;
948 } 952 DEBUGOUT("Valid Link Found\n");
949 } else { 953 }
950 DEBUGOUT("No Signal Detected\n"); 954 } else {
951 } 955 DEBUGOUT("No Signal Detected\n");
952 return E1000_SUCCESS; 956 }
957 return E1000_SUCCESS;
953} 958}
954 959
955/****************************************************************************** 960/**
956* Make sure we have a valid PHY and change PHY mode before link setup. 961 * e1000_copper_link_preconfig - early configuration for copper
957* 962 * @hw: Struct containing variables accessed by shared code
958* hw - Struct containing variables accessed by shared code 963 *
959******************************************************************************/ 964 * Make sure we have a valid PHY and change PHY mode before link setup.
965 */
960static s32 e1000_copper_link_preconfig(struct e1000_hw *hw) 966static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
961{ 967{
962 u32 ctrl; 968 u32 ctrl;
963 s32 ret_val; 969 s32 ret_val;
964 u16 phy_data; 970 u16 phy_data;
965 971
966 DEBUGFUNC("e1000_copper_link_preconfig"); 972 DEBUGFUNC("e1000_copper_link_preconfig");
967 973
968 ctrl = er32(CTRL); 974 ctrl = er32(CTRL);
969 /* With 82543, we need to force speed and duplex on the MAC equal to what 975 /* With 82543, we need to force speed and duplex on the MAC equal to what
970 * the PHY speed and duplex configuration is. In addition, we need to 976 * the PHY speed and duplex configuration is. In addition, we need to
971 * perform a hardware reset on the PHY to take it out of reset. 977 * perform a hardware reset on the PHY to take it out of reset.
972 */ 978 */
973 if (hw->mac_type > e1000_82543) { 979 if (hw->mac_type > e1000_82543) {
974 ctrl |= E1000_CTRL_SLU; 980 ctrl |= E1000_CTRL_SLU;
975 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 981 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
976 ew32(CTRL, ctrl); 982 ew32(CTRL, ctrl);
977 } else { 983 } else {
978 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); 984 ctrl |=
979 ew32(CTRL, ctrl); 985 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
980 ret_val = e1000_phy_hw_reset(hw); 986 ew32(CTRL, ctrl);
981 if (ret_val) 987 ret_val = e1000_phy_hw_reset(hw);
982 return ret_val; 988 if (ret_val)
983 } 989 return ret_val;
984 990 }
985 /* Make sure we have a valid PHY */
986 ret_val = e1000_detect_gig_phy(hw);
987 if (ret_val) {
988 DEBUGOUT("Error, did not detect valid phy.\n");
989 return ret_val;
990 }
991 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
992
993 /* Set PHY to class A mode (if necessary) */
994 ret_val = e1000_set_phy_mode(hw);
995 if (ret_val)
996 return ret_val;
997
998 if ((hw->mac_type == e1000_82545_rev_3) ||
999 (hw->mac_type == e1000_82546_rev_3)) {
1000 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1001 phy_data |= 0x00000008;
1002 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1003 }
1004
1005 if (hw->mac_type <= e1000_82543 ||
1006 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1007 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1008 hw->phy_reset_disable = false;
1009
1010 return E1000_SUCCESS;
1011}
1012 991
992 /* Make sure we have a valid PHY */
993 ret_val = e1000_detect_gig_phy(hw);
994 if (ret_val) {
995 DEBUGOUT("Error, did not detect valid phy.\n");
996 return ret_val;
997 }
998 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
999
1000 /* Set PHY to class A mode (if necessary) */
1001 ret_val = e1000_set_phy_mode(hw);
1002 if (ret_val)
1003 return ret_val;
1004
1005 if ((hw->mac_type == e1000_82545_rev_3) ||
1006 (hw->mac_type == e1000_82546_rev_3)) {
1007 ret_val =
1008 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1009 phy_data |= 0x00000008;
1010 ret_val =
1011 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1012 }
1013
1014 if (hw->mac_type <= e1000_82543 ||
1015 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1016 hw->mac_type == e1000_82541_rev_2
1017 || hw->mac_type == e1000_82547_rev_2)
1018 hw->phy_reset_disable = false;
1019
1020 return E1000_SUCCESS;
1021}
1013 1022
1014/******************************************************************** 1023/**
1015* Copper link setup for e1000_phy_igp series. 1024 * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series.
1016* 1025 * @hw: Struct containing variables accessed by shared code
1017* hw - Struct containing variables accessed by shared code 1026 */
1018*********************************************************************/
1019static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw) 1027static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1020{ 1028{
1021 u32 led_ctrl; 1029 u32 led_ctrl;
1022 s32 ret_val; 1030 s32 ret_val;
1023 u16 phy_data; 1031 u16 phy_data;
1024 1032
1025 DEBUGFUNC("e1000_copper_link_igp_setup"); 1033 DEBUGFUNC("e1000_copper_link_igp_setup");
1026 1034
1027 if (hw->phy_reset_disable) 1035 if (hw->phy_reset_disable)
1028 return E1000_SUCCESS; 1036 return E1000_SUCCESS;
1029 1037
1030 ret_val = e1000_phy_reset(hw); 1038 ret_val = e1000_phy_reset(hw);
1031 if (ret_val) { 1039 if (ret_val) {
1032 DEBUGOUT("Error Resetting the PHY\n"); 1040 DEBUGOUT("Error Resetting the PHY\n");
1033 return ret_val; 1041 return ret_val;
1034 } 1042 }
1035 1043
1036 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 1044 /* Wait 15ms for MAC to configure PHY from eeprom settings */
1037 msleep(15); 1045 msleep(15);
1038 /* Configure activity LED after PHY reset */ 1046 /* Configure activity LED after PHY reset */
1039 led_ctrl = er32(LEDCTL); 1047 led_ctrl = er32(LEDCTL);
1040 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1048 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1041 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1049 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1042 ew32(LEDCTL, led_ctrl); 1050 ew32(LEDCTL, led_ctrl);
1043 1051
1044 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 1052 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1045 if (hw->phy_type == e1000_phy_igp) { 1053 if (hw->phy_type == e1000_phy_igp) {
1046 /* disable lplu d3 during driver init */ 1054 /* disable lplu d3 during driver init */
1047 ret_val = e1000_set_d3_lplu_state(hw, false); 1055 ret_val = e1000_set_d3_lplu_state(hw, false);
1048 if (ret_val) { 1056 if (ret_val) {
1049 DEBUGOUT("Error Disabling LPLU D3\n"); 1057 DEBUGOUT("Error Disabling LPLU D3\n");
1050 return ret_val; 1058 return ret_val;
1051 } 1059 }
1052 } 1060 }
1053 1061
1054 /* Configure mdi-mdix settings */ 1062 /* Configure mdi-mdix settings */
1055 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1063 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1056 if (ret_val) 1064 if (ret_val)
1057 return ret_val; 1065 return ret_val;
1058 1066
1059 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 1067 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1060 hw->dsp_config_state = e1000_dsp_config_disabled; 1068 hw->dsp_config_state = e1000_dsp_config_disabled;
1061 /* Force MDI for earlier revs of the IGP PHY */ 1069 /* Force MDI for earlier revs of the IGP PHY */
1062 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX); 1070 phy_data &=
1063 hw->mdix = 1; 1071 ~(IGP01E1000_PSCR_AUTO_MDIX |
1064 1072 IGP01E1000_PSCR_FORCE_MDI_MDIX);
1065 } else { 1073 hw->mdix = 1;
1066 hw->dsp_config_state = e1000_dsp_config_enabled; 1074
1067 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1075 } else {
1068 1076 hw->dsp_config_state = e1000_dsp_config_enabled;
1069 switch (hw->mdix) { 1077 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1070 case 1: 1078
1071 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1079 switch (hw->mdix) {
1072 break; 1080 case 1:
1073 case 2: 1081 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1074 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 1082 break;
1075 break; 1083 case 2:
1076 case 0: 1084 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1077 default: 1085 break;
1078 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 1086 case 0:
1079 break; 1087 default:
1080 } 1088 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1081 } 1089 break;
1082 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1090 }
1083 if (ret_val) 1091 }
1084 return ret_val; 1092 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1085 1093 if (ret_val)
1086 /* set auto-master slave resolution settings */ 1094 return ret_val;
1087 if (hw->autoneg) { 1095
1088 e1000_ms_type phy_ms_setting = hw->master_slave; 1096 /* set auto-master slave resolution settings */
1089 1097 if (hw->autoneg) {
1090 if (hw->ffe_config_state == e1000_ffe_config_active) 1098 e1000_ms_type phy_ms_setting = hw->master_slave;
1091 hw->ffe_config_state = e1000_ffe_config_enabled; 1099
1092 1100 if (hw->ffe_config_state == e1000_ffe_config_active)
1093 if (hw->dsp_config_state == e1000_dsp_config_activated) 1101 hw->ffe_config_state = e1000_ffe_config_enabled;
1094 hw->dsp_config_state = e1000_dsp_config_enabled; 1102
1095 1103 if (hw->dsp_config_state == e1000_dsp_config_activated)
1096 /* when autonegotiation advertisment is only 1000Mbps then we 1104 hw->dsp_config_state = e1000_dsp_config_enabled;
1097 * should disable SmartSpeed and enable Auto MasterSlave 1105
1098 * resolution as hardware default. */ 1106 /* when autonegotiation advertisement is only 1000Mbps then we
1099 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 1107 * should disable SmartSpeed and enable Auto MasterSlave
1100 /* Disable SmartSpeed */ 1108 * resolution as hardware default. */
1101 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1109 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1102 &phy_data); 1110 /* Disable SmartSpeed */
1103 if (ret_val) 1111 ret_val =
1104 return ret_val; 1112 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1105 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1113 &phy_data);
1106 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1114 if (ret_val)
1107 phy_data); 1115 return ret_val;
1108 if (ret_val) 1116 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1109 return ret_val; 1117 ret_val =
1110 /* Set auto Master/Slave resolution process */ 1118 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1111 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 1119 phy_data);
1112 if (ret_val) 1120 if (ret_val)
1113 return ret_val; 1121 return ret_val;
1114 phy_data &= ~CR_1000T_MS_ENABLE; 1122 /* Set auto Master/Slave resolution process */
1115 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 1123 ret_val =
1116 if (ret_val) 1124 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1117 return ret_val; 1125 if (ret_val)
1118 } 1126 return ret_val;
1119 1127 phy_data &= ~CR_1000T_MS_ENABLE;
1120 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 1128 ret_val =
1121 if (ret_val) 1129 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1122 return ret_val; 1130 if (ret_val)
1123 1131 return ret_val;
1124 /* load defaults for future use */ 1132 }
1125 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 1133
1126 ((phy_data & CR_1000T_MS_VALUE) ? 1134 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1127 e1000_ms_force_master : 1135 if (ret_val)
1128 e1000_ms_force_slave) : 1136 return ret_val;
1129 e1000_ms_auto; 1137
1130 1138 /* load defaults for future use */
1131 switch (phy_ms_setting) { 1139 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1132 case e1000_ms_force_master: 1140 ((phy_data & CR_1000T_MS_VALUE) ?
1133 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 1141 e1000_ms_force_master :
1134 break; 1142 e1000_ms_force_slave) : e1000_ms_auto;
1135 case e1000_ms_force_slave: 1143
1136 phy_data |= CR_1000T_MS_ENABLE; 1144 switch (phy_ms_setting) {
1137 phy_data &= ~(CR_1000T_MS_VALUE); 1145 case e1000_ms_force_master:
1138 break; 1146 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1139 case e1000_ms_auto: 1147 break;
1140 phy_data &= ~CR_1000T_MS_ENABLE; 1148 case e1000_ms_force_slave:
1141 default: 1149 phy_data |= CR_1000T_MS_ENABLE;
1142 break; 1150 phy_data &= ~(CR_1000T_MS_VALUE);
1143 } 1151 break;
1144 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 1152 case e1000_ms_auto:
1145 if (ret_val) 1153 phy_data &= ~CR_1000T_MS_ENABLE;
1146 return ret_val; 1154 default:
1147 } 1155 break;
1148 1156 }
1149 return E1000_SUCCESS; 1157 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1158 if (ret_val)
1159 return ret_val;
1160 }
1161
1162 return E1000_SUCCESS;
1150} 1163}
1151 1164
1152/******************************************************************** 1165/**
1153* Copper link setup for e1000_phy_m88 series. 1166 * e1000_copper_link_mgp_setup - Copper link setup for e1000_phy_m88 series.
1154* 1167 * @hw: Struct containing variables accessed by shared code
1155* hw - Struct containing variables accessed by shared code 1168 */
1156*********************************************************************/
1157static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw) 1169static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1158{ 1170{
1159 s32 ret_val; 1171 s32 ret_val;
1160 u16 phy_data; 1172 u16 phy_data;
1161 1173
1162 DEBUGFUNC("e1000_copper_link_mgp_setup"); 1174 DEBUGFUNC("e1000_copper_link_mgp_setup");
1163 1175
1164 if (hw->phy_reset_disable) 1176 if (hw->phy_reset_disable)
1165 return E1000_SUCCESS; 1177 return E1000_SUCCESS;
1166 1178
1167 /* Enable CRS on TX. This must be set for half-duplex operation. */ 1179 /* Enable CRS on TX. This must be set for half-duplex operation. */
1168 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1180 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1169 if (ret_val) 1181 if (ret_val)
1170 return ret_val; 1182 return ret_val;
1171 1183
1172 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1184 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1173 1185
1174 /* Options: 1186 /* Options:
1175 * MDI/MDI-X = 0 (default) 1187 * MDI/MDI-X = 0 (default)
1176 * 0 - Auto for all speeds 1188 * 0 - Auto for all speeds
1177 * 1 - MDI mode 1189 * 1 - MDI mode
1178 * 2 - MDI-X mode 1190 * 2 - MDI-X mode
1179 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1191 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1180 */ 1192 */
1181 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1193 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1182 1194
1183 switch (hw->mdix) { 1195 switch (hw->mdix) {
1184 case 1: 1196 case 1:
1185 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1197 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1186 break; 1198 break;
1187 case 2: 1199 case 2:
1188 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1200 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1189 break; 1201 break;
1190 case 3: 1202 case 3:
1191 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1203 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1192 break; 1204 break;
1193 case 0: 1205 case 0:
1194 default: 1206 default:
1195 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1207 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1196 break; 1208 break;
1197 } 1209 }
1198 1210
1199 /* Options: 1211 /* Options:
1200 * disable_polarity_correction = 0 (default) 1212 * disable_polarity_correction = 0 (default)
1201 * Automatic Correction for Reversed Cable Polarity 1213 * Automatic Correction for Reversed Cable Polarity
1202 * 0 - Disabled 1214 * 0 - Disabled
1203 * 1 - Enabled 1215 * 1 - Enabled
1204 */ 1216 */
1205 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1217 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1206 if (hw->disable_polarity_correction == 1) 1218 if (hw->disable_polarity_correction == 1)
1207 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1219 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1208 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1220 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1209 if (ret_val) 1221 if (ret_val)
1210 return ret_val; 1222 return ret_val;
1211 1223
1212 if (hw->phy_revision < M88E1011_I_REV_4) { 1224 if (hw->phy_revision < M88E1011_I_REV_4) {
1213 /* Force TX_CLK in the Extended PHY Specific Control Register 1225 /* Force TX_CLK in the Extended PHY Specific Control Register
1214 * to 25MHz clock. 1226 * to 25MHz clock.
1215 */ 1227 */
1216 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1228 ret_val =
1217 if (ret_val) 1229 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1218 return ret_val; 1230 &phy_data);
1219 1231 if (ret_val)
1220 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1232 return ret_val;
1221 1233
1222 if ((hw->phy_revision == E1000_REVISION_2) && 1234 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1223 (hw->phy_id == M88E1111_I_PHY_ID)) { 1235
1224 /* Vidalia Phy, set the downshift counter to 5x */ 1236 if ((hw->phy_revision == E1000_REVISION_2) &&
1225 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 1237 (hw->phy_id == M88E1111_I_PHY_ID)) {
1226 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 1238 /* Vidalia Phy, set the downshift counter to 5x */
1227 ret_val = e1000_write_phy_reg(hw, 1239 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1228 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1240 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1229 if (ret_val) 1241 ret_val = e1000_write_phy_reg(hw,
1230 return ret_val; 1242 M88E1000_EXT_PHY_SPEC_CTRL,
1231 } else { 1243 phy_data);
1232 /* Configure Master and Slave downshift values */ 1244 if (ret_val)
1233 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1245 return ret_val;
1234 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1246 } else {
1235 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1247 /* Configure Master and Slave downshift values */
1236 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1248 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1237 ret_val = e1000_write_phy_reg(hw, 1249 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1238 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1250 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1239 if (ret_val) 1251 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1240 return ret_val; 1252 ret_val = e1000_write_phy_reg(hw,
1241 } 1253 M88E1000_EXT_PHY_SPEC_CTRL,
1242 } 1254 phy_data);
1243 1255 if (ret_val)
1244 /* SW Reset the PHY so all changes take effect */ 1256 return ret_val;
1245 ret_val = e1000_phy_reset(hw); 1257 }
1246 if (ret_val) { 1258 }
1247 DEBUGOUT("Error Resetting the PHY\n"); 1259
1248 return ret_val; 1260 /* SW Reset the PHY so all changes take effect */
1249 } 1261 ret_val = e1000_phy_reset(hw);
1250 1262 if (ret_val) {
1251 return E1000_SUCCESS; 1263 DEBUGOUT("Error Resetting the PHY\n");
1264 return ret_val;
1265 }
1266
1267 return E1000_SUCCESS;
1252} 1268}
1253 1269
1254/******************************************************************** 1270/**
1255* Setup auto-negotiation and flow control advertisements, 1271 * e1000_copper_link_autoneg - setup auto-neg
1256* and then perform auto-negotiation. 1272 * @hw: Struct containing variables accessed by shared code
1257* 1273 *
1258* hw - Struct containing variables accessed by shared code 1274 * Setup auto-negotiation and flow control advertisements,
1259*********************************************************************/ 1275 * and then perform auto-negotiation.
1276 */
1260static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) 1277static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1261{ 1278{
1262 s32 ret_val; 1279 s32 ret_val;
1263 u16 phy_data; 1280 u16 phy_data;
1264 1281
1265 DEBUGFUNC("e1000_copper_link_autoneg"); 1282 DEBUGFUNC("e1000_copper_link_autoneg");
1266 1283
1267 /* Perform some bounds checking on the hw->autoneg_advertised 1284 /* Perform some bounds checking on the hw->autoneg_advertised
1268 * parameter. If this variable is zero, then set it to the default. 1285 * parameter. If this variable is zero, then set it to the default.
1269 */ 1286 */
1270 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 1287 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1271 1288
1272 /* If autoneg_advertised is zero, we assume it was not defaulted 1289 /* If autoneg_advertised is zero, we assume it was not defaulted
1273 * by the calling code so we set to advertise full capability. 1290 * by the calling code so we set to advertise full capability.
1274 */ 1291 */
1275 if (hw->autoneg_advertised == 0) 1292 if (hw->autoneg_advertised == 0)
1276 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 1293 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1277 1294
1278 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1295 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1279 ret_val = e1000_phy_setup_autoneg(hw); 1296 ret_val = e1000_phy_setup_autoneg(hw);
1280 if (ret_val) { 1297 if (ret_val) {
1281 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1298 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1282 return ret_val; 1299 return ret_val;
1283 } 1300 }
1284 DEBUGOUT("Restarting Auto-Neg\n"); 1301 DEBUGOUT("Restarting Auto-Neg\n");
1285 1302
1286 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1303 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1287 * the Auto Neg Restart bit in the PHY control register. 1304 * the Auto Neg Restart bit in the PHY control register.
1288 */ 1305 */
1289 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 1306 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1290 if (ret_val) 1307 if (ret_val)
1291 return ret_val; 1308 return ret_val;
1292 1309
1293 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1310 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1294 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 1311 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1295 if (ret_val) 1312 if (ret_val)
1296 return ret_val; 1313 return ret_val;
1297 1314
1298 /* Does the user want to wait for Auto-Neg to complete here, or 1315 /* Does the user want to wait for Auto-Neg to complete here, or
1299 * check at a later time (for example, callback routine). 1316 * check at a later time (for example, callback routine).
1300 */ 1317 */
1301 if (hw->wait_autoneg_complete) { 1318 if (hw->wait_autoneg_complete) {
1302 ret_val = e1000_wait_autoneg(hw); 1319 ret_val = e1000_wait_autoneg(hw);
1303 if (ret_val) { 1320 if (ret_val) {
1304 DEBUGOUT("Error while waiting for autoneg to complete\n"); 1321 DEBUGOUT
1305 return ret_val; 1322 ("Error while waiting for autoneg to complete\n");
1306 } 1323 return ret_val;
1307 } 1324 }
1308 1325 }
1309 hw->get_link_status = true; 1326
1310 1327 hw->get_link_status = true;
1311 return E1000_SUCCESS; 1328
1329 return E1000_SUCCESS;
1312} 1330}
1313 1331
1314/****************************************************************************** 1332/**
1315* Config the MAC and the PHY after link is up. 1333 * e1000_copper_link_postconfig - post link setup
1316* 1) Set up the MAC to the current PHY speed/duplex 1334 * @hw: Struct containing variables accessed by shared code
1317* if we are on 82543. If we 1335 *
1318* are on newer silicon, we only need to configure 1336 * Config the MAC and the PHY after link is up.
1319* collision distance in the Transmit Control Register. 1337 * 1) Set up the MAC to the current PHY speed/duplex
1320* 2) Set up flow control on the MAC to that established with 1338 * if we are on 82543. If we
1321* the link partner. 1339 * are on newer silicon, we only need to configure
1322* 3) Config DSP to improve Gigabit link quality for some PHY revisions. 1340 * collision distance in the Transmit Control Register.
1323* 1341 * 2) Set up flow control on the MAC to that established with
1324* hw - Struct containing variables accessed by shared code 1342 * the link partner.
1325******************************************************************************/ 1343 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1344 */
1326static s32 e1000_copper_link_postconfig(struct e1000_hw *hw) 1345static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
1327{ 1346{
1328 s32 ret_val; 1347 s32 ret_val;
1329 DEBUGFUNC("e1000_copper_link_postconfig"); 1348 DEBUGFUNC("e1000_copper_link_postconfig");
1330 1349
1331 if (hw->mac_type >= e1000_82544) { 1350 if (hw->mac_type >= e1000_82544) {
1332 e1000_config_collision_dist(hw); 1351 e1000_config_collision_dist(hw);
1333 } else { 1352 } else {
1334 ret_val = e1000_config_mac_to_phy(hw); 1353 ret_val = e1000_config_mac_to_phy(hw);
1335 if (ret_val) { 1354 if (ret_val) {
1336 DEBUGOUT("Error configuring MAC to PHY settings\n"); 1355 DEBUGOUT("Error configuring MAC to PHY settings\n");
1337 return ret_val; 1356 return ret_val;
1338 } 1357 }
1339 } 1358 }
1340 ret_val = e1000_config_fc_after_link_up(hw); 1359 ret_val = e1000_config_fc_after_link_up(hw);
1341 if (ret_val) { 1360 if (ret_val) {
1342 DEBUGOUT("Error Configuring Flow Control\n"); 1361 DEBUGOUT("Error Configuring Flow Control\n");
1343 return ret_val; 1362 return ret_val;
1344 } 1363 }
1345 1364
1346 /* Config DSP to improve Giga link quality */ 1365 /* Config DSP to improve Giga link quality */
1347 if (hw->phy_type == e1000_phy_igp) { 1366 if (hw->phy_type == e1000_phy_igp) {
1348 ret_val = e1000_config_dsp_after_link_change(hw, true); 1367 ret_val = e1000_config_dsp_after_link_change(hw, true);
1349 if (ret_val) { 1368 if (ret_val) {
1350 DEBUGOUT("Error Configuring DSP after link up\n"); 1369 DEBUGOUT("Error Configuring DSP after link up\n");
1351 return ret_val; 1370 return ret_val;
1352 } 1371 }
1353 } 1372 }
1354 1373
1355 return E1000_SUCCESS; 1374 return E1000_SUCCESS;
1356} 1375}
1357 1376
1358/****************************************************************************** 1377/**
1359* Detects which PHY is present and setup the speed and duplex 1378 * e1000_setup_copper_link - phy/speed/duplex setting
1360* 1379 * @hw: Struct containing variables accessed by shared code
1361* hw - Struct containing variables accessed by shared code 1380 *
1362******************************************************************************/ 1381 * Detects which PHY is present and sets up the speed and duplex
1382 */
1363static s32 e1000_setup_copper_link(struct e1000_hw *hw) 1383static s32 e1000_setup_copper_link(struct e1000_hw *hw)
1364{ 1384{
1365 s32 ret_val; 1385 s32 ret_val;
1366 u16 i; 1386 u16 i;
1367 u16 phy_data; 1387 u16 phy_data;
1368 1388
1369 DEBUGFUNC("e1000_setup_copper_link"); 1389 DEBUGFUNC("e1000_setup_copper_link");
1370 1390
1371 /* Check if it is a valid PHY and set PHY mode if necessary. */ 1391 /* Check if it is a valid PHY and set PHY mode if necessary. */
1372 ret_val = e1000_copper_link_preconfig(hw); 1392 ret_val = e1000_copper_link_preconfig(hw);
1373 if (ret_val) 1393 if (ret_val)
1374 return ret_val; 1394 return ret_val;
1375 1395
1376 if (hw->phy_type == e1000_phy_igp) { 1396 if (hw->phy_type == e1000_phy_igp) {
1377 ret_val = e1000_copper_link_igp_setup(hw); 1397 ret_val = e1000_copper_link_igp_setup(hw);
1378 if (ret_val) 1398 if (ret_val)
1379 return ret_val; 1399 return ret_val;
1380 } else if (hw->phy_type == e1000_phy_m88) { 1400 } else if (hw->phy_type == e1000_phy_m88) {
1381 ret_val = e1000_copper_link_mgp_setup(hw); 1401 ret_val = e1000_copper_link_mgp_setup(hw);
1382 if (ret_val) 1402 if (ret_val)
1383 return ret_val; 1403 return ret_val;
1384 } 1404 }
1385 1405
1386 if (hw->autoneg) { 1406 if (hw->autoneg) {
1387 /* Setup autoneg and flow control advertisement 1407 /* Setup autoneg and flow control advertisement
1388 * and perform autonegotiation */ 1408 * and perform autonegotiation */
1389 ret_val = e1000_copper_link_autoneg(hw); 1409 ret_val = e1000_copper_link_autoneg(hw);
1390 if (ret_val) 1410 if (ret_val)
1391 return ret_val; 1411 return ret_val;
1392 } else { 1412 } else {
1393 /* PHY will be set to 10H, 10F, 100H,or 100F 1413 /* PHY will be set to 10H, 10F, 100H,or 100F
1394 * depending on value from forced_speed_duplex. */ 1414 * depending on value from forced_speed_duplex. */
1395 DEBUGOUT("Forcing speed and duplex\n"); 1415 DEBUGOUT("Forcing speed and duplex\n");
1396 ret_val = e1000_phy_force_speed_duplex(hw); 1416 ret_val = e1000_phy_force_speed_duplex(hw);
1397 if (ret_val) { 1417 if (ret_val) {
1398 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1418 DEBUGOUT("Error Forcing Speed and Duplex\n");
1399 return ret_val; 1419 return ret_val;
1400 } 1420 }
1401 } 1421 }
1402 1422
1403 /* Check link status. Wait up to 100 microseconds for link to become 1423 /* Check link status. Wait up to 100 microseconds for link to become
1404 * valid. 1424 * valid.
1405 */ 1425 */
1406 for (i = 0; i < 10; i++) { 1426 for (i = 0; i < 10; i++) {
1407 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 1427 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1408 if (ret_val) 1428 if (ret_val)
1409 return ret_val; 1429 return ret_val;
1410 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 1430 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1411 if (ret_val) 1431 if (ret_val)
1412 return ret_val; 1432 return ret_val;
1413 1433
1414 if (phy_data & MII_SR_LINK_STATUS) { 1434 if (phy_data & MII_SR_LINK_STATUS) {
1415 /* Config the MAC and PHY after link is up */ 1435 /* Config the MAC and PHY after link is up */
1416 ret_val = e1000_copper_link_postconfig(hw); 1436 ret_val = e1000_copper_link_postconfig(hw);
1417 if (ret_val) 1437 if (ret_val)
1418 return ret_val; 1438 return ret_val;
1419 1439
1420 DEBUGOUT("Valid link established!!!\n"); 1440 DEBUGOUT("Valid link established!!!\n");
1421 return E1000_SUCCESS; 1441 return E1000_SUCCESS;
1422 } 1442 }
1423 udelay(10); 1443 udelay(10);
1424 } 1444 }
1425 1445
1426 DEBUGOUT("Unable to establish link!!!\n"); 1446 DEBUGOUT("Unable to establish link!!!\n");
1427 return E1000_SUCCESS; 1447 return E1000_SUCCESS;
1428} 1448}
1429 1449
1430/****************************************************************************** 1450/**
1431* Configures PHY autoneg and flow control advertisement settings 1451 * e1000_phy_setup_autoneg - phy settings
1432* 1452 * @hw: Struct containing variables accessed by shared code
1433* hw - Struct containing variables accessed by shared code 1453 *
1434******************************************************************************/ 1454 * Configures PHY autoneg and flow control advertisement settings
1455 */
1435s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) 1456s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1436{ 1457{
1437 s32 ret_val; 1458 s32 ret_val;
1438 u16 mii_autoneg_adv_reg; 1459 u16 mii_autoneg_adv_reg;
1439 u16 mii_1000t_ctrl_reg; 1460 u16 mii_1000t_ctrl_reg;
1440 1461
1441 DEBUGFUNC("e1000_phy_setup_autoneg"); 1462 DEBUGFUNC("e1000_phy_setup_autoneg");
1442 1463
1443 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1464 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1444 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 1465 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1445 if (ret_val) 1466 if (ret_val)
1446 return ret_val; 1467 return ret_val;
1447 1468
1448 /* Read the MII 1000Base-T Control Register (Address 9). */ 1469 /* Read the MII 1000Base-T Control Register (Address 9). */
1449 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); 1470 ret_val =
1450 if (ret_val) 1471 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1451 return ret_val; 1472 if (ret_val)
1452 1473 return ret_val;
1453 /* Need to parse both autoneg_advertised and fc and set up 1474
1454 * the appropriate PHY registers. First we will parse for 1475 /* Need to parse both autoneg_advertised and fc and set up
1455 * autoneg_advertised software override. Since we can advertise 1476 * the appropriate PHY registers. First we will parse for
1456 * a plethora of combinations, we need to check each bit 1477 * autoneg_advertised software override. Since we can advertise
1457 * individually. 1478 * a plethora of combinations, we need to check each bit
1458 */ 1479 * individually.
1459 1480 */
1460 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 1481
1461 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1482 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1462 * the 1000Base-T Control Register (Address 9). 1483 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1463 */ 1484 * the 1000Base-T Control Register (Address 9).
1464 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 1485 */
1465 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 1486 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1466 1487 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1467 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); 1488
1468 1489 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1469 /* Do we want to advertise 10 Mb Half Duplex? */ 1490
1470 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 1491 /* Do we want to advertise 10 Mb Half Duplex? */
1471 DEBUGOUT("Advertise 10mb Half duplex\n"); 1492 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
1472 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1493 DEBUGOUT("Advertise 10mb Half duplex\n");
1473 } 1494 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1474 1495 }
1475 /* Do we want to advertise 10 Mb Full Duplex? */ 1496
1476 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 1497 /* Do we want to advertise 10 Mb Full Duplex? */
1477 DEBUGOUT("Advertise 10mb Full duplex\n"); 1498 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
1478 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1499 DEBUGOUT("Advertise 10mb Full duplex\n");
1479 } 1500 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1480 1501 }
1481 /* Do we want to advertise 100 Mb Half Duplex? */ 1502
1482 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 1503 /* Do we want to advertise 100 Mb Half Duplex? */
1483 DEBUGOUT("Advertise 100mb Half duplex\n"); 1504 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
1484 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1505 DEBUGOUT("Advertise 100mb Half duplex\n");
1485 } 1506 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1486 1507 }
1487 /* Do we want to advertise 100 Mb Full Duplex? */ 1508
1488 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 1509 /* Do we want to advertise 100 Mb Full Duplex? */
1489 DEBUGOUT("Advertise 100mb Full duplex\n"); 1510 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
1490 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1511 DEBUGOUT("Advertise 100mb Full duplex\n");
1491 } 1512 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1492 1513 }
1493 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1514
1494 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 1515 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1495 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n"); 1516 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1496 } 1517 DEBUGOUT
1497 1518 ("Advertise 1000mb Half duplex requested, request denied!\n");
1498 /* Do we want to advertise 1000 Mb Full Duplex? */ 1519 }
1499 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 1520
1500 DEBUGOUT("Advertise 1000mb Full duplex\n"); 1521 /* Do we want to advertise 1000 Mb Full Duplex? */
1501 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1522 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1502 } 1523 DEBUGOUT("Advertise 1000mb Full duplex\n");
1503 1524 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1504 /* Check for a software override of the flow control settings, and 1525 }
1505 * setup the PHY advertisement registers accordingly. If 1526
1506 * auto-negotiation is enabled, then software will have to set the 1527 /* Check for a software override of the flow control settings, and
1507 * "PAUSE" bits to the correct value in the Auto-Negotiation 1528 * setup the PHY advertisement registers accordingly. If
1508 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. 1529 * auto-negotiation is enabled, then software will have to set the
1509 * 1530 * "PAUSE" bits to the correct value in the Auto-Negotiation
1510 * The possible values of the "fc" parameter are: 1531 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1511 * 0: Flow control is completely disabled 1532 *
1512 * 1: Rx flow control is enabled (we can receive pause frames 1533 * The possible values of the "fc" parameter are:
1513 * but not send pause frames). 1534 * 0: Flow control is completely disabled
1514 * 2: Tx flow control is enabled (we can send pause frames 1535 * 1: Rx flow control is enabled (we can receive pause frames
1515 * but we do not support receiving pause frames). 1536 * but not send pause frames).
1516 * 3: Both Rx and TX flow control (symmetric) are enabled. 1537 * 2: Tx flow control is enabled (we can send pause frames
1517 * other: No software override. The flow control configuration 1538 * but we do not support receiving pause frames).
1518 * in the EEPROM is used. 1539 * 3: Both Rx and TX flow control (symmetric) are enabled.
1519 */ 1540 * other: No software override. The flow control configuration
1520 switch (hw->fc) { 1541 * in the EEPROM is used.
1521 case E1000_FC_NONE: /* 0 */ 1542 */
1522 /* Flow control (RX & TX) is completely disabled by a 1543 switch (hw->fc) {
1523 * software over-ride. 1544 case E1000_FC_NONE: /* 0 */
1524 */ 1545 /* Flow control (RX & TX) is completely disabled by a
1525 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1546 * software over-ride.
1526 break; 1547 */
1527 case E1000_FC_RX_PAUSE: /* 1 */ 1548 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1528 /* RX Flow control is enabled, and TX Flow control is 1549 break;
1529 * disabled, by a software over-ride. 1550 case E1000_FC_RX_PAUSE: /* 1 */
1530 */ 1551 /* RX Flow control is enabled, and TX Flow control is
1531 /* Since there really isn't a way to advertise that we are 1552 * disabled, by a software over-ride.
1532 * capable of RX Pause ONLY, we will advertise that we 1553 */
1533 * support both symmetric and asymmetric RX PAUSE. Later 1554 /* Since there really isn't a way to advertise that we are
1534 * (in e1000_config_fc_after_link_up) we will disable the 1555 * capable of RX Pause ONLY, we will advertise that we
1535 *hw's ability to send PAUSE frames. 1556 * support both symmetric and asymmetric RX PAUSE. Later
1536 */ 1557 * (in e1000_config_fc_after_link_up) we will disable the
1537 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1558 *hw's ability to send PAUSE frames.
1538 break; 1559 */
1539 case E1000_FC_TX_PAUSE: /* 2 */ 1560 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1540 /* TX Flow control is enabled, and RX Flow control is 1561 break;
1541 * disabled, by a software over-ride. 1562 case E1000_FC_TX_PAUSE: /* 2 */
1542 */ 1563 /* TX Flow control is enabled, and RX Flow control is
1543 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1564 * disabled, by a software over-ride.
1544 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1565 */
1545 break; 1566 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1546 case E1000_FC_FULL: /* 3 */ 1567 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1547 /* Flow control (both RX and TX) is enabled by a software 1568 break;
1548 * over-ride. 1569 case E1000_FC_FULL: /* 3 */
1549 */ 1570 /* Flow control (both RX and TX) is enabled by a software
1550 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1571 * over-ride.
1551 break; 1572 */
1552 default: 1573 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1553 DEBUGOUT("Flow control param set incorrectly\n"); 1574 break;
1554 return -E1000_ERR_CONFIG; 1575 default:
1555 } 1576 DEBUGOUT("Flow control param set incorrectly\n");
1556 1577 return -E1000_ERR_CONFIG;
1557 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1578 }
1558 if (ret_val) 1579
1559 return ret_val; 1580 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1560 1581 if (ret_val)
1561 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1582 return ret_val;
1562 1583
1563 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); 1584 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1564 if (ret_val) 1585
1565 return ret_val; 1586 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1566 1587 if (ret_val)
1567 return E1000_SUCCESS; 1588 return ret_val;
1589
1590 return E1000_SUCCESS;
1568} 1591}
1569 1592
1570/****************************************************************************** 1593/**
1571* Force PHY speed and duplex settings to hw->forced_speed_duplex 1594 * e1000_phy_force_speed_duplex - force link settings
1572* 1595 * @hw: Struct containing variables accessed by shared code
1573* hw - Struct containing variables accessed by shared code 1596 *
1574******************************************************************************/ 1597 * Force PHY speed and duplex settings to hw->forced_speed_duplex
1598 */
1575static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) 1599static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1576{ 1600{
1577 u32 ctrl; 1601 u32 ctrl;
1578 s32 ret_val; 1602 s32 ret_val;
1579 u16 mii_ctrl_reg; 1603 u16 mii_ctrl_reg;
1580 u16 mii_status_reg; 1604 u16 mii_status_reg;
1581 u16 phy_data; 1605 u16 phy_data;
1582 u16 i; 1606 u16 i;
1583 1607
1584 DEBUGFUNC("e1000_phy_force_speed_duplex"); 1608 DEBUGFUNC("e1000_phy_force_speed_duplex");
1585 1609
1586 /* Turn off Flow control if we are forcing speed and duplex. */ 1610 /* Turn off Flow control if we are forcing speed and duplex. */
1587 hw->fc = E1000_FC_NONE; 1611 hw->fc = E1000_FC_NONE;
1588 1612
1589 DEBUGOUT1("hw->fc = %d\n", hw->fc); 1613 DEBUGOUT1("hw->fc = %d\n", hw->fc);
1590 1614
1591 /* Read the Device Control Register. */ 1615 /* Read the Device Control Register. */
1592 ctrl = er32(CTRL); 1616 ctrl = er32(CTRL);
1593 1617
1594 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ 1618 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1595 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1619 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1596 ctrl &= ~(DEVICE_SPEED_MASK); 1620 ctrl &= ~(DEVICE_SPEED_MASK);
1597 1621
1598 /* Clear the Auto Speed Detect Enable bit. */ 1622 /* Clear the Auto Speed Detect Enable bit. */
1599 ctrl &= ~E1000_CTRL_ASDE; 1623 ctrl &= ~E1000_CTRL_ASDE;
1600 1624
1601 /* Read the MII Control Register. */ 1625 /* Read the MII Control Register. */
1602 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); 1626 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
1603 if (ret_val) 1627 if (ret_val)
1604 return ret_val; 1628 return ret_val;
1605 1629
1606 /* We need to disable autoneg in order to force link and duplex. */ 1630 /* We need to disable autoneg in order to force link and duplex. */
1607 1631
1608 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; 1632 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1609 1633
1610 /* Are we forcing Full or Half Duplex? */ 1634 /* Are we forcing Full or Half Duplex? */
1611 if (hw->forced_speed_duplex == e1000_100_full || 1635 if (hw->forced_speed_duplex == e1000_100_full ||
1612 hw->forced_speed_duplex == e1000_10_full) { 1636 hw->forced_speed_duplex == e1000_10_full) {
1613 /* We want to force full duplex so we SET the full duplex bits in the 1637 /* We want to force full duplex so we SET the full duplex bits in the
1614 * Device and MII Control Registers. 1638 * Device and MII Control Registers.
1615 */ 1639 */
1616 ctrl |= E1000_CTRL_FD; 1640 ctrl |= E1000_CTRL_FD;
1617 mii_ctrl_reg |= MII_CR_FULL_DUPLEX; 1641 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
1618 DEBUGOUT("Full Duplex\n"); 1642 DEBUGOUT("Full Duplex\n");
1619 } else { 1643 } else {
1620 /* We want to force half duplex so we CLEAR the full duplex bits in 1644 /* We want to force half duplex so we CLEAR the full duplex bits in
1621 * the Device and MII Control Registers. 1645 * the Device and MII Control Registers.
1622 */ 1646 */
1623 ctrl &= ~E1000_CTRL_FD; 1647 ctrl &= ~E1000_CTRL_FD;
1624 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; 1648 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
1625 DEBUGOUT("Half Duplex\n"); 1649 DEBUGOUT("Half Duplex\n");
1626 } 1650 }
1627 1651
1628 /* Are we forcing 100Mbps??? */ 1652 /* Are we forcing 100Mbps??? */
1629 if (hw->forced_speed_duplex == e1000_100_full || 1653 if (hw->forced_speed_duplex == e1000_100_full ||
1630 hw->forced_speed_duplex == e1000_100_half) { 1654 hw->forced_speed_duplex == e1000_100_half) {
1631 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ 1655 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1632 ctrl |= E1000_CTRL_SPD_100; 1656 ctrl |= E1000_CTRL_SPD_100;
1633 mii_ctrl_reg |= MII_CR_SPEED_100; 1657 mii_ctrl_reg |= MII_CR_SPEED_100;
1634 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1658 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1635 DEBUGOUT("Forcing 100mb "); 1659 DEBUGOUT("Forcing 100mb ");
1636 } else { 1660 } else {
1637 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ 1661 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1638 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1662 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1639 mii_ctrl_reg |= MII_CR_SPEED_10; 1663 mii_ctrl_reg |= MII_CR_SPEED_10;
1640 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1664 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1641 DEBUGOUT("Forcing 10mb "); 1665 DEBUGOUT("Forcing 10mb ");
1642 } 1666 }
1643 1667
1644 e1000_config_collision_dist(hw); 1668 e1000_config_collision_dist(hw);
1645 1669
1646 /* Write the configured values back to the Device Control Reg. */ 1670 /* Write the configured values back to the Device Control Reg. */
1647 ew32(CTRL, ctrl); 1671 ew32(CTRL, ctrl);
1648 1672
1649 if (hw->phy_type == e1000_phy_m88) { 1673 if (hw->phy_type == e1000_phy_m88) {
1650 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1674 ret_val =
1651 if (ret_val) 1675 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1652 return ret_val; 1676 if (ret_val)
1653 1677 return ret_val;
1654 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 1678
1655 * forced whenever speed are duplex are forced. 1679 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1656 */ 1680 * forced whenever speed are duplex are forced.
1657 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1681 */
1658 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1682 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1659 if (ret_val) 1683 ret_val =
1660 return ret_val; 1684 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1661 1685 if (ret_val)
1662 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); 1686 return ret_val;
1663 1687
1664 /* Need to reset the PHY or these changes will be ignored */ 1688 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
1665 mii_ctrl_reg |= MII_CR_RESET; 1689
1666 1690 /* Need to reset the PHY or these changes will be ignored */
1667 } else { 1691 mii_ctrl_reg |= MII_CR_RESET;
1668 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 1692
1669 * forced whenever speed or duplex are forced. 1693 /* Disable MDI-X support for 10/100 */
1670 */ 1694 } else {
1671 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1695 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1672 if (ret_val) 1696 * forced whenever speed or duplex are forced.
1673 return ret_val; 1697 */
1674 1698 ret_val =
1675 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1699 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1676 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1700 if (ret_val)
1677 1701 return ret_val;
1678 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1702
1679 if (ret_val) 1703 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1680 return ret_val; 1704 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1681 } 1705
1682 1706 ret_val =
1683 /* Write back the modified PHY MII control register. */ 1707 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1684 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); 1708 if (ret_val)
1685 if (ret_val) 1709 return ret_val;
1686 return ret_val; 1710 }
1687 1711
1688 udelay(1); 1712 /* Write back the modified PHY MII control register. */
1689 1713 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
1690 /* The wait_autoneg_complete flag may be a little misleading here. 1714 if (ret_val)
1691 * Since we are forcing speed and duplex, Auto-Neg is not enabled. 1715 return ret_val;
1692 * But we do want to delay for a period while forcing only so we 1716
1693 * don't generate false No Link messages. So we will wait here 1717 udelay(1);
1694 * only if the user has set wait_autoneg_complete to 1, which is 1718
1695 * the default. 1719 /* The wait_autoneg_complete flag may be a little misleading here.
1696 */ 1720 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
1697 if (hw->wait_autoneg_complete) { 1721 * But we do want to delay for a period while forcing only so we
1698 /* We will wait for autoneg to complete. */ 1722 * don't generate false No Link messages. So we will wait here
1699 DEBUGOUT("Waiting for forced speed/duplex link.\n"); 1723 * only if the user has set wait_autoneg_complete to 1, which is
1700 mii_status_reg = 0; 1724 * the default.
1701 1725 */
1702 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 1726 if (hw->wait_autoneg_complete) {
1703 for (i = PHY_FORCE_TIME; i > 0; i--) { 1727 /* We will wait for autoneg to complete. */
1704 /* Read the MII Status Register and wait for Auto-Neg Complete bit 1728 DEBUGOUT("Waiting for forced speed/duplex link.\n");
1705 * to be set. 1729 mii_status_reg = 0;
1706 */ 1730
1707 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1731 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
1708 if (ret_val) 1732 for (i = PHY_FORCE_TIME; i > 0; i--) {
1709 return ret_val; 1733 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1710 1734 * to be set.
1711 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1735 */
1712 if (ret_val) 1736 ret_val =
1713 return ret_val; 1737 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1714 1738 if (ret_val)
1715 if (mii_status_reg & MII_SR_LINK_STATUS) break; 1739 return ret_val;
1716 msleep(100); 1740
1717 } 1741 ret_val =
1718 if ((i == 0) && 1742 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1719 (hw->phy_type == e1000_phy_m88)) { 1743 if (ret_val)
1720 /* We didn't get link. Reset the DSP and wait again for link. */ 1744 return ret_val;
1721 ret_val = e1000_phy_reset_dsp(hw); 1745
1722 if (ret_val) { 1746 if (mii_status_reg & MII_SR_LINK_STATUS)
1723 DEBUGOUT("Error Resetting PHY DSP\n"); 1747 break;
1724 return ret_val; 1748 msleep(100);
1725 } 1749 }
1726 } 1750 if ((i == 0) && (hw->phy_type == e1000_phy_m88)) {
1727 /* This loop will early-out if the link condition has been met. */ 1751 /* We didn't get link. Reset the DSP and wait again for link. */
1728 for (i = PHY_FORCE_TIME; i > 0; i--) { 1752 ret_val = e1000_phy_reset_dsp(hw);
1729 if (mii_status_reg & MII_SR_LINK_STATUS) break; 1753 if (ret_val) {
1730 msleep(100); 1754 DEBUGOUT("Error Resetting PHY DSP\n");
1731 /* Read the MII Status Register and wait for Auto-Neg Complete bit 1755 return ret_val;
1732 * to be set. 1756 }
1733 */ 1757 }
1734 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1758 /* This loop will early-out if the link condition has been met. */
1735 if (ret_val) 1759 for (i = PHY_FORCE_TIME; i > 0; i--) {
1736 return ret_val; 1760 if (mii_status_reg & MII_SR_LINK_STATUS)
1737 1761 break;
1738 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1762 msleep(100);
1739 if (ret_val) 1763 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1740 return ret_val; 1764 * to be set.
1741 } 1765 */
1742 } 1766 ret_val =
1743 1767 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1744 if (hw->phy_type == e1000_phy_m88) { 1768 if (ret_val)
1745 /* Because we reset the PHY above, we need to re-force TX_CLK in the 1769 return ret_val;
1746 * Extended PHY Specific Control Register to 25MHz clock. This value 1770
1747 * defaults back to a 2.5MHz clock when the PHY is reset. 1771 ret_val =
1748 */ 1772 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1749 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1773 if (ret_val)
1750 if (ret_val) 1774 return ret_val;
1751 return ret_val; 1775 }
1752 1776 }
1753 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1777
1754 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1778 if (hw->phy_type == e1000_phy_m88) {
1755 if (ret_val) 1779 /* Because we reset the PHY above, we need to re-force TX_CLK in the
1756 return ret_val; 1780 * Extended PHY Specific Control Register to 25MHz clock. This value
1757 1781 * defaults back to a 2.5MHz clock when the PHY is reset.
1758 /* In addition, because of the s/w reset above, we need to enable CRS on 1782 */
1759 * TX. This must be set for both full and half duplex operation. 1783 ret_val =
1760 */ 1784 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1761 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1785 &phy_data);
1762 if (ret_val) 1786 if (ret_val)
1763 return ret_val; 1787 return ret_val;
1764 1788
1765 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1789 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1766 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1790 ret_val =
1767 if (ret_val) 1791 e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1768 return ret_val; 1792 phy_data);
1769 1793 if (ret_val)
1770 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && 1794 return ret_val;
1771 (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full || 1795
1772 hw->forced_speed_duplex == e1000_10_half)) { 1796 /* In addition, because of the s/w reset above, we need to enable CRS on
1773 ret_val = e1000_polarity_reversal_workaround(hw); 1797 * TX. This must be set for both full and half duplex operation.
1774 if (ret_val) 1798 */
1775 return ret_val; 1799 ret_val =
1776 } 1800 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1777 } 1801 if (ret_val)
1778 return E1000_SUCCESS; 1802 return ret_val;
1803
1804 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1805 ret_val =
1806 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1807 if (ret_val)
1808 return ret_val;
1809
1810 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543)
1811 && (!hw->autoneg)
1812 && (hw->forced_speed_duplex == e1000_10_full
1813 || hw->forced_speed_duplex == e1000_10_half)) {
1814 ret_val = e1000_polarity_reversal_workaround(hw);
1815 if (ret_val)
1816 return ret_val;
1817 }
1818 }
1819 return E1000_SUCCESS;
1779} 1820}
1780 1821
1781/****************************************************************************** 1822/**
1782* Sets the collision distance in the Transmit Control register 1823 * e1000_config_collision_dist - set collision distance register
1783* 1824 * @hw: Struct containing variables accessed by shared code
1784* hw - Struct containing variables accessed by shared code 1825 *
1785* 1826 * Sets the collision distance in the Transmit Control register.
1786* Link should have been established previously. Reads the speed and duplex 1827 * Link should have been established previously. Reads the speed and duplex
1787* information from the Device Status register. 1828 * information from the Device Status register.
1788******************************************************************************/ 1829 */
1789void e1000_config_collision_dist(struct e1000_hw *hw) 1830void e1000_config_collision_dist(struct e1000_hw *hw)
1790{ 1831{
1791 u32 tctl, coll_dist; 1832 u32 tctl, coll_dist;
1792 1833
1793 DEBUGFUNC("e1000_config_collision_dist"); 1834 DEBUGFUNC("e1000_config_collision_dist");
1794 1835
1795 if (hw->mac_type < e1000_82543) 1836 if (hw->mac_type < e1000_82543)
1796 coll_dist = E1000_COLLISION_DISTANCE_82542; 1837 coll_dist = E1000_COLLISION_DISTANCE_82542;
1797 else 1838 else
1798 coll_dist = E1000_COLLISION_DISTANCE; 1839 coll_dist = E1000_COLLISION_DISTANCE;
1799 1840
1800 tctl = er32(TCTL); 1841 tctl = er32(TCTL);
1801 1842
1802 tctl &= ~E1000_TCTL_COLD; 1843 tctl &= ~E1000_TCTL_COLD;
1803 tctl |= coll_dist << E1000_COLD_SHIFT; 1844 tctl |= coll_dist << E1000_COLD_SHIFT;
1804 1845
1805 ew32(TCTL, tctl); 1846 ew32(TCTL, tctl);
1806 E1000_WRITE_FLUSH(); 1847 E1000_WRITE_FLUSH();
1807} 1848}
1808 1849
1809/****************************************************************************** 1850/**
1810* Sets MAC speed and duplex settings to reflect the those in the PHY 1851 * e1000_config_mac_to_phy - sync phy and mac settings
1811* 1852 * @hw: Struct containing variables accessed by shared code
1812* hw - Struct containing variables accessed by shared code 1853 * @mii_reg: data to write to the MII control register
1813* mii_reg - data to write to the MII control register 1854 *
1814* 1855 * Sets MAC speed and duplex settings to reflect the those in the PHY
1815* The contents of the PHY register containing the needed information need to 1856 * The contents of the PHY register containing the needed information need to
1816* be passed in. 1857 * be passed in.
1817******************************************************************************/ 1858 */
1818static s32 e1000_config_mac_to_phy(struct e1000_hw *hw) 1859static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
1819{ 1860{
1820 u32 ctrl; 1861 u32 ctrl;
1821 s32 ret_val; 1862 s32 ret_val;
1822 u16 phy_data; 1863 u16 phy_data;
1823 1864
1824 DEBUGFUNC("e1000_config_mac_to_phy"); 1865 DEBUGFUNC("e1000_config_mac_to_phy");
1825 1866
1826 /* 82544 or newer MAC, Auto Speed Detection takes care of 1867 /* 82544 or newer MAC, Auto Speed Detection takes care of
1827 * MAC speed/duplex configuration.*/ 1868 * MAC speed/duplex configuration.*/
1828 if (hw->mac_type >= e1000_82544) 1869 if (hw->mac_type >= e1000_82544)
1829 return E1000_SUCCESS; 1870 return E1000_SUCCESS;
1830 1871
1831 /* Read the Device Control Register and set the bits to Force Speed 1872 /* Read the Device Control Register and set the bits to Force Speed
1832 * and Duplex. 1873 * and Duplex.
1833 */ 1874 */
1834 ctrl = er32(CTRL); 1875 ctrl = er32(CTRL);
1835 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1876 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1836 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 1877 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1837 1878
1838 /* Set up duplex in the Device Control and Transmit Control 1879 /* Set up duplex in the Device Control and Transmit Control
1839 * registers depending on negotiated values. 1880 * registers depending on negotiated values.
1840 */ 1881 */
1841 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1882 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1842 if (ret_val) 1883 if (ret_val)
1843 return ret_val; 1884 return ret_val;
1844 1885
1845 if (phy_data & M88E1000_PSSR_DPLX) 1886 if (phy_data & M88E1000_PSSR_DPLX)
1846 ctrl |= E1000_CTRL_FD; 1887 ctrl |= E1000_CTRL_FD;
1847 else 1888 else
1848 ctrl &= ~E1000_CTRL_FD; 1889 ctrl &= ~E1000_CTRL_FD;
1849 1890
1850 e1000_config_collision_dist(hw); 1891 e1000_config_collision_dist(hw);
1851 1892
1852 /* Set up speed in the Device Control register depending on 1893 /* Set up speed in the Device Control register depending on
1853 * negotiated values. 1894 * negotiated values.
1854 */ 1895 */
1855 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 1896 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1856 ctrl |= E1000_CTRL_SPD_1000; 1897 ctrl |= E1000_CTRL_SPD_1000;
1857 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 1898 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1858 ctrl |= E1000_CTRL_SPD_100; 1899 ctrl |= E1000_CTRL_SPD_100;
1859 1900
1860 /* Write the configured values back to the Device Control Reg. */ 1901 /* Write the configured values back to the Device Control Reg. */
1861 ew32(CTRL, ctrl); 1902 ew32(CTRL, ctrl);
1862 return E1000_SUCCESS; 1903 return E1000_SUCCESS;
1863} 1904}
1864 1905
1865/****************************************************************************** 1906/**
1866 * Forces the MAC's flow control settings. 1907 * e1000_force_mac_fc - force flow control settings
1867 * 1908 * @hw: Struct containing variables accessed by shared code
1868 * hw - Struct containing variables accessed by shared code
1869 * 1909 *
1910 * Forces the MAC's flow control settings.
1870 * Sets the TFCE and RFCE bits in the device control register to reflect 1911 * Sets the TFCE and RFCE bits in the device control register to reflect
1871 * the adapter settings. TFCE and RFCE need to be explicitly set by 1912 * the adapter settings. TFCE and RFCE need to be explicitly set by
1872 * software when a Copper PHY is used because autonegotiation is managed 1913 * software when a Copper PHY is used because autonegotiation is managed
1873 * by the PHY rather than the MAC. Software must also configure these 1914 * by the PHY rather than the MAC. Software must also configure these
1874 * bits when link is forced on a fiber connection. 1915 * bits when link is forced on a fiber connection.
1875 *****************************************************************************/ 1916 */
1876s32 e1000_force_mac_fc(struct e1000_hw *hw) 1917s32 e1000_force_mac_fc(struct e1000_hw *hw)
1877{ 1918{
1878 u32 ctrl; 1919 u32 ctrl;
1879 1920
1880 DEBUGFUNC("e1000_force_mac_fc"); 1921 DEBUGFUNC("e1000_force_mac_fc");
1881 1922
1882 /* Get the current configuration of the Device Control Register */ 1923 /* Get the current configuration of the Device Control Register */
1883 ctrl = er32(CTRL); 1924 ctrl = er32(CTRL);
1884 1925
1885 /* Because we didn't get link via the internal auto-negotiation 1926 /* Because we didn't get link via the internal auto-negotiation
1886 * mechanism (we either forced link or we got link via PHY 1927 * mechanism (we either forced link or we got link via PHY
1887 * auto-neg), we have to manually enable/disable transmit an 1928 * auto-neg), we have to manually enable/disable transmit an
1888 * receive flow control. 1929 * receive flow control.
1889 * 1930 *
1890 * The "Case" statement below enables/disable flow control 1931 * The "Case" statement below enables/disable flow control
1891 * according to the "hw->fc" parameter. 1932 * according to the "hw->fc" parameter.
1892 * 1933 *
1893 * The possible values of the "fc" parameter are: 1934 * The possible values of the "fc" parameter are:
1894 * 0: Flow control is completely disabled 1935 * 0: Flow control is completely disabled
1895 * 1: Rx flow control is enabled (we can receive pause 1936 * 1: Rx flow control is enabled (we can receive pause
1896 * frames but not send pause frames). 1937 * frames but not send pause frames).
1897 * 2: Tx flow control is enabled (we can send pause frames 1938 * 2: Tx flow control is enabled (we can send pause frames
1898 * frames but we do not receive pause frames). 1939 * frames but we do not receive pause frames).
1899 * 3: Both Rx and TX flow control (symmetric) is enabled. 1940 * 3: Both Rx and TX flow control (symmetric) is enabled.
1900 * other: No other values should be possible at this point. 1941 * other: No other values should be possible at this point.
1901 */ 1942 */
1902 1943
1903 switch (hw->fc) { 1944 switch (hw->fc) {
1904 case E1000_FC_NONE: 1945 case E1000_FC_NONE:
1905 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1946 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1906 break; 1947 break;
1907 case E1000_FC_RX_PAUSE: 1948 case E1000_FC_RX_PAUSE:
1908 ctrl &= (~E1000_CTRL_TFCE); 1949 ctrl &= (~E1000_CTRL_TFCE);
1909 ctrl |= E1000_CTRL_RFCE; 1950 ctrl |= E1000_CTRL_RFCE;
1910 break; 1951 break;
1911 case E1000_FC_TX_PAUSE: 1952 case E1000_FC_TX_PAUSE:
1912 ctrl &= (~E1000_CTRL_RFCE); 1953 ctrl &= (~E1000_CTRL_RFCE);
1913 ctrl |= E1000_CTRL_TFCE; 1954 ctrl |= E1000_CTRL_TFCE;
1914 break; 1955 break;
1915 case E1000_FC_FULL: 1956 case E1000_FC_FULL:
1916 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1957 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1917 break; 1958 break;
1918 default: 1959 default:
1919 DEBUGOUT("Flow control param set incorrectly\n"); 1960 DEBUGOUT("Flow control param set incorrectly\n");
1920 return -E1000_ERR_CONFIG; 1961 return -E1000_ERR_CONFIG;
1921 } 1962 }
1922 1963
1923 /* Disable TX Flow Control for 82542 (rev 2.0) */ 1964 /* Disable TX Flow Control for 82542 (rev 2.0) */
1924 if (hw->mac_type == e1000_82542_rev2_0) 1965 if (hw->mac_type == e1000_82542_rev2_0)
1925 ctrl &= (~E1000_CTRL_TFCE); 1966 ctrl &= (~E1000_CTRL_TFCE);
1926 1967
1927 ew32(CTRL, ctrl); 1968 ew32(CTRL, ctrl);
1928 return E1000_SUCCESS; 1969 return E1000_SUCCESS;
1929} 1970}
1930 1971
1931/****************************************************************************** 1972/**
1932 * Configures flow control settings after link is established 1973 * e1000_config_fc_after_link_up - configure flow control after autoneg
1933 * 1974 * @hw: Struct containing variables accessed by shared code
1934 * hw - Struct containing variables accessed by shared code
1935 * 1975 *
1976 * Configures flow control settings after link is established
1936 * Should be called immediately after a valid link has been established. 1977 * Should be called immediately after a valid link has been established.
1937 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 1978 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
1938 * and autonegotiation is enabled, the MAC flow control settings will be set 1979 * and autonegotiation is enabled, the MAC flow control settings will be set
1939 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 1980 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
1940 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 1981 * and RFCE bits will be automatically set to the negotiated flow control mode.
1941 *****************************************************************************/ 1982 */
1942static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw) 1983static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
1943{ 1984{
1944 s32 ret_val; 1985 s32 ret_val;
1945 u16 mii_status_reg; 1986 u16 mii_status_reg;
1946 u16 mii_nway_adv_reg; 1987 u16 mii_nway_adv_reg;
1947 u16 mii_nway_lp_ability_reg; 1988 u16 mii_nway_lp_ability_reg;
1948 u16 speed; 1989 u16 speed;
1949 u16 duplex; 1990 u16 duplex;
1950 1991
1951 DEBUGFUNC("e1000_config_fc_after_link_up"); 1992 DEBUGFUNC("e1000_config_fc_after_link_up");
1952 1993
1953 /* Check for the case where we have fiber media and auto-neg failed 1994 /* Check for the case where we have fiber media and auto-neg failed
1954 * so we had to force link. In this case, we need to force the 1995 * so we had to force link. In this case, we need to force the
1955 * configuration of the MAC to match the "fc" parameter. 1996 * configuration of the MAC to match the "fc" parameter.
1956 */ 1997 */
1957 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) || 1998 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
1958 ((hw->media_type == e1000_media_type_internal_serdes) && 1999 || ((hw->media_type == e1000_media_type_internal_serdes)
1959 (hw->autoneg_failed)) || 2000 && (hw->autoneg_failed))
1960 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) { 2001 || ((hw->media_type == e1000_media_type_copper)
1961 ret_val = e1000_force_mac_fc(hw); 2002 && (!hw->autoneg))) {
1962 if (ret_val) { 2003 ret_val = e1000_force_mac_fc(hw);
1963 DEBUGOUT("Error forcing flow control settings\n"); 2004 if (ret_val) {
1964 return ret_val; 2005 DEBUGOUT("Error forcing flow control settings\n");
1965 } 2006 return ret_val;
1966 } 2007 }
1967 2008 }
1968 /* Check for the case where we have copper media and auto-neg is 2009
1969 * enabled. In this case, we need to check and see if Auto-Neg 2010 /* Check for the case where we have copper media and auto-neg is
1970 * has completed, and if so, how the PHY and link partner has 2011 * enabled. In this case, we need to check and see if Auto-Neg
1971 * flow control configured. 2012 * has completed, and if so, how the PHY and link partner has
1972 */ 2013 * flow control configured.
1973 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) { 2014 */
1974 /* Read the MII Status Register and check to see if AutoNeg 2015 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
1975 * has completed. We read this twice because this reg has 2016 /* Read the MII Status Register and check to see if AutoNeg
1976 * some "sticky" (latched) bits. 2017 * has completed. We read this twice because this reg has
1977 */ 2018 * some "sticky" (latched) bits.
1978 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2019 */
1979 if (ret_val) 2020 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1980 return ret_val; 2021 if (ret_val)
1981 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 2022 return ret_val;
1982 if (ret_val) 2023 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1983 return ret_val; 2024 if (ret_val)
1984 2025 return ret_val;
1985 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 2026
1986 /* The AutoNeg process has completed, so we now need to 2027 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
1987 * read both the Auto Negotiation Advertisement Register 2028 /* The AutoNeg process has completed, so we now need to
1988 * (Address 4) and the Auto_Negotiation Base Page Ability 2029 * read both the Auto Negotiation Advertisement Register
1989 * Register (Address 5) to determine how flow control was 2030 * (Address 4) and the Auto_Negotiation Base Page Ability
1990 * negotiated. 2031 * Register (Address 5) to determine how flow control was
1991 */ 2032 * negotiated.
1992 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 2033 */
1993 &mii_nway_adv_reg); 2034 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
1994 if (ret_val) 2035 &mii_nway_adv_reg);
1995 return ret_val; 2036 if (ret_val)
1996 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, 2037 return ret_val;
1997 &mii_nway_lp_ability_reg); 2038 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
1998 if (ret_val) 2039 &mii_nway_lp_ability_reg);
1999 return ret_val; 2040 if (ret_val)
2000 2041 return ret_val;
2001 /* Two bits in the Auto Negotiation Advertisement Register 2042
2002 * (Address 4) and two bits in the Auto Negotiation Base 2043 /* Two bits in the Auto Negotiation Advertisement Register
2003 * Page Ability Register (Address 5) determine flow control 2044 * (Address 4) and two bits in the Auto Negotiation Base
2004 * for both the PHY and the link partner. The following 2045 * Page Ability Register (Address 5) determine flow control
2005 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 2046 * for both the PHY and the link partner. The following
2006 * 1999, describes these PAUSE resolution bits and how flow 2047 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2007 * control is determined based upon these settings. 2048 * 1999, describes these PAUSE resolution bits and how flow
2008 * NOTE: DC = Don't Care 2049 * control is determined based upon these settings.
2009 * 2050 * NOTE: DC = Don't Care
2010 * LOCAL DEVICE | LINK PARTNER 2051 *
2011 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 2052 * LOCAL DEVICE | LINK PARTNER
2012 *-------|---------|-------|---------|-------------------- 2053 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2013 * 0 | 0 | DC | DC | E1000_FC_NONE 2054 *-------|---------|-------|---------|--------------------
2014 * 0 | 1 | 0 | DC | E1000_FC_NONE 2055 * 0 | 0 | DC | DC | E1000_FC_NONE
2015 * 0 | 1 | 1 | 0 | E1000_FC_NONE 2056 * 0 | 1 | 0 | DC | E1000_FC_NONE
2016 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE 2057 * 0 | 1 | 1 | 0 | E1000_FC_NONE
2017 * 1 | 0 | 0 | DC | E1000_FC_NONE 2058 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2018 * 1 | DC | 1 | DC | E1000_FC_FULL 2059 * 1 | 0 | 0 | DC | E1000_FC_NONE
2019 * 1 | 1 | 0 | 0 | E1000_FC_NONE 2060 * 1 | DC | 1 | DC | E1000_FC_FULL
2020 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE 2061 * 1 | 1 | 0 | 0 | E1000_FC_NONE
2021 * 2062 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2022 */ 2063 *
2023 /* Are both PAUSE bits set to 1? If so, this implies 2064 */
2024 * Symmetric Flow Control is enabled at both ends. The 2065 /* Are both PAUSE bits set to 1? If so, this implies
2025 * ASM_DIR bits are irrelevant per the spec. 2066 * Symmetric Flow Control is enabled at both ends. The
2026 * 2067 * ASM_DIR bits are irrelevant per the spec.
2027 * For Symmetric Flow Control: 2068 *
2028 * 2069 * For Symmetric Flow Control:
2029 * LOCAL DEVICE | LINK PARTNER 2070 *
2030 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2071 * LOCAL DEVICE | LINK PARTNER
2031 *-------|---------|-------|---------|-------------------- 2072 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2032 * 1 | DC | 1 | DC | E1000_FC_FULL 2073 *-------|---------|-------|---------|--------------------
2033 * 2074 * 1 | DC | 1 | DC | E1000_FC_FULL
2034 */ 2075 *
2035 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2076 */
2036 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 2077 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2037 /* Now we need to check if the user selected RX ONLY 2078 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2038 * of pause frames. In this case, we had to advertise 2079 /* Now we need to check if the user selected RX ONLY
2039 * FULL flow control because we could not advertise RX 2080 * of pause frames. In this case, we had to advertise
2040 * ONLY. Hence, we must now check to see if we need to 2081 * FULL flow control because we could not advertise RX
2041 * turn OFF the TRANSMISSION of PAUSE frames. 2082 * ONLY. Hence, we must now check to see if we need to
2042 */ 2083 * turn OFF the TRANSMISSION of PAUSE frames.
2043 if (hw->original_fc == E1000_FC_FULL) { 2084 */
2044 hw->fc = E1000_FC_FULL; 2085 if (hw->original_fc == E1000_FC_FULL) {
2045 DEBUGOUT("Flow Control = FULL.\n"); 2086 hw->fc = E1000_FC_FULL;
2046 } else { 2087 DEBUGOUT("Flow Control = FULL.\n");
2047 hw->fc = E1000_FC_RX_PAUSE; 2088 } else {
2048 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2089 hw->fc = E1000_FC_RX_PAUSE;
2049 } 2090 DEBUGOUT
2050 } 2091 ("Flow Control = RX PAUSE frames only.\n");
2051 /* For receiving PAUSE frames ONLY. 2092 }
2052 * 2093 }
2053 * LOCAL DEVICE | LINK PARTNER 2094 /* For receiving PAUSE frames ONLY.
2054 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2095 *
2055 *-------|---------|-------|---------|-------------------- 2096 * LOCAL DEVICE | LINK PARTNER
2056 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE 2097 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2057 * 2098 *-------|---------|-------|---------|--------------------
2058 */ 2099 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2059 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 2100 *
2060 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2101 */
2061 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2102 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2062 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 2103 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2063 hw->fc = E1000_FC_TX_PAUSE; 2104 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2064 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 2105 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
2065 } 2106 {
2066 /* For transmitting PAUSE frames ONLY. 2107 hw->fc = E1000_FC_TX_PAUSE;
2067 * 2108 DEBUGOUT
2068 * LOCAL DEVICE | LINK PARTNER 2109 ("Flow Control = TX PAUSE frames only.\n");
2069 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 2110 }
2070 *-------|---------|-------|---------|-------------------- 2111 /* For transmitting PAUSE frames ONLY.
2071 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE 2112 *
2072 * 2113 * LOCAL DEVICE | LINK PARTNER
2073 */ 2114 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2074 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 2115 *-------|---------|-------|---------|--------------------
2075 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 2116 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2076 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 2117 *
2077 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 2118 */
2078 hw->fc = E1000_FC_RX_PAUSE; 2119 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2079 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2120 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2080 } 2121 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2081 /* Per the IEEE spec, at this point flow control should be 2122 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
2082 * disabled. However, we want to consider that we could 2123 {
2083 * be connected to a legacy switch that doesn't advertise 2124 hw->fc = E1000_FC_RX_PAUSE;
2084 * desired flow control, but can be forced on the link 2125 DEBUGOUT
2085 * partner. So if we advertised no flow control, that is 2126 ("Flow Control = RX PAUSE frames only.\n");
2086 * what we will resolve to. If we advertised some kind of 2127 }
2087 * receive capability (Rx Pause Only or Full Flow Control) 2128 /* Per the IEEE spec, at this point flow control should be
2088 * and the link partner advertised none, we will configure 2129 * disabled. However, we want to consider that we could
2089 * ourselves to enable Rx Flow Control only. We can do 2130 * be connected to a legacy switch that doesn't advertise
2090 * this safely for two reasons: If the link partner really 2131 * desired flow control, but can be forced on the link
2091 * didn't want flow control enabled, and we enable Rx, no 2132 * partner. So if we advertised no flow control, that is
2092 * harm done since we won't be receiving any PAUSE frames 2133 * what we will resolve to. If we advertised some kind of
2093 * anyway. If the intent on the link partner was to have 2134 * receive capability (Rx Pause Only or Full Flow Control)
2094 * flow control enabled, then by us enabling RX only, we 2135 * and the link partner advertised none, we will configure
2095 * can at least receive pause frames and process them. 2136 * ourselves to enable Rx Flow Control only. We can do
2096 * This is a good idea because in most cases, since we are 2137 * this safely for two reasons: If the link partner really
2097 * predominantly a server NIC, more times than not we will 2138 * didn't want flow control enabled, and we enable Rx, no
2098 * be asked to delay transmission of packets than asking 2139 * harm done since we won't be receiving any PAUSE frames
2099 * our link partner to pause transmission of frames. 2140 * anyway. If the intent on the link partner was to have
2100 */ 2141 * flow control enabled, then by us enabling RX only, we
2101 else if ((hw->original_fc == E1000_FC_NONE || 2142 * can at least receive pause frames and process them.
2102 hw->original_fc == E1000_FC_TX_PAUSE) || 2143 * This is a good idea because in most cases, since we are
2103 hw->fc_strict_ieee) { 2144 * predominantly a server NIC, more times than not we will
2104 hw->fc = E1000_FC_NONE; 2145 * be asked to delay transmission of packets than asking
2105 DEBUGOUT("Flow Control = NONE.\n"); 2146 * our link partner to pause transmission of frames.
2106 } else { 2147 */
2107 hw->fc = E1000_FC_RX_PAUSE; 2148 else if ((hw->original_fc == E1000_FC_NONE ||
2108 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2149 hw->original_fc == E1000_FC_TX_PAUSE) ||
2109 } 2150 hw->fc_strict_ieee) {
2110 2151 hw->fc = E1000_FC_NONE;
2111 /* Now we need to do one last check... If we auto- 2152 DEBUGOUT("Flow Control = NONE.\n");
2112 * negotiated to HALF DUPLEX, flow control should not be 2153 } else {
2113 * enabled per IEEE 802.3 spec. 2154 hw->fc = E1000_FC_RX_PAUSE;
2114 */ 2155 DEBUGOUT
2115 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 2156 ("Flow Control = RX PAUSE frames only.\n");
2116 if (ret_val) { 2157 }
2117 DEBUGOUT("Error getting link speed and duplex\n"); 2158
2118 return ret_val; 2159 /* Now we need to do one last check... If we auto-
2119 } 2160 * negotiated to HALF DUPLEX, flow control should not be
2120 2161 * enabled per IEEE 802.3 spec.
2121 if (duplex == HALF_DUPLEX) 2162 */
2122 hw->fc = E1000_FC_NONE; 2163 ret_val =
2123 2164 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2124 /* Now we call a subroutine to actually force the MAC 2165 if (ret_val) {
2125 * controller to use the correct flow control settings. 2166 DEBUGOUT
2126 */ 2167 ("Error getting link speed and duplex\n");
2127 ret_val = e1000_force_mac_fc(hw); 2168 return ret_val;
2128 if (ret_val) { 2169 }
2129 DEBUGOUT("Error forcing flow control settings\n"); 2170
2130 return ret_val; 2171 if (duplex == HALF_DUPLEX)
2131 } 2172 hw->fc = E1000_FC_NONE;
2132 } else { 2173
2133 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); 2174 /* Now we call a subroutine to actually force the MAC
2134 } 2175 * controller to use the correct flow control settings.
2135 } 2176 */
2136 return E1000_SUCCESS; 2177 ret_val = e1000_force_mac_fc(hw);
2178 if (ret_val) {
2179 DEBUGOUT
2180 ("Error forcing flow control settings\n");
2181 return ret_val;
2182 }
2183 } else {
2184 DEBUGOUT
2185 ("Copper PHY and Auto Neg has not completed.\n");
2186 }
2187 }
2188 return E1000_SUCCESS;
2137} 2189}
2138 2190
2139/** 2191/**
2140 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 2192 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
2141 * @hw: pointer to the HW structure 2193 * @hw: pointer to the HW structure
2142 * 2194 *
2143 * Checks for link up on the hardware. If link is not up and we have 2195 * Checks for link up on the hardware. If link is not up and we have
2144 * a signal, then we need to force link up. 2196 * a signal, then we need to force link up.
2145 **/ 2197 */
2146s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 2198s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
2147{ 2199{
2148 u32 rxcw; 2200 u32 rxcw;
@@ -2227,11 +2279,11 @@ s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
2227 if (!(rxcw & E1000_RXCW_IV)) { 2279 if (!(rxcw & E1000_RXCW_IV)) {
2228 hw->serdes_has_link = true; 2280 hw->serdes_has_link = true;
2229 DEBUGOUT("SERDES: Link up - autoneg " 2281 DEBUGOUT("SERDES: Link up - autoneg "
2230 "completed sucessfully.\n"); 2282 "completed successfully.\n");
2231 } else { 2283 } else {
2232 hw->serdes_has_link = false; 2284 hw->serdes_has_link = false;
2233 DEBUGOUT("SERDES: Link down - invalid" 2285 DEBUGOUT("SERDES: Link down - invalid"
2234 "codewords detected in autoneg.\n"); 2286 "codewords detected in autoneg.\n");
2235 } 2287 }
2236 } else { 2288 } else {
2237 hw->serdes_has_link = false; 2289 hw->serdes_has_link = false;
@@ -2243,2631 +2295,2660 @@ s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
2243 } 2295 }
2244 } 2296 }
2245 2297
2246out: 2298 out:
2247 return ret_val; 2299 return ret_val;
2248} 2300}
2249/****************************************************************************** 2301
2250 * Checks to see if the link status of the hardware has changed. 2302/**
2251 * 2303 * e1000_check_for_link
2252 * hw - Struct containing variables accessed by shared code 2304 * @hw: Struct containing variables accessed by shared code
2253 * 2305 *
2306 * Checks to see if the link status of the hardware has changed.
2254 * Called by any function that needs to check the link status of the adapter. 2307 * Called by any function that needs to check the link status of the adapter.
2255 *****************************************************************************/ 2308 */
2256s32 e1000_check_for_link(struct e1000_hw *hw) 2309s32 e1000_check_for_link(struct e1000_hw *hw)
2257{ 2310{
2258 u32 rxcw = 0; 2311 u32 rxcw = 0;
2259 u32 ctrl; 2312 u32 ctrl;
2260 u32 status; 2313 u32 status;
2261 u32 rctl; 2314 u32 rctl;
2262 u32 icr; 2315 u32 icr;
2263 u32 signal = 0; 2316 u32 signal = 0;
2264 s32 ret_val; 2317 s32 ret_val;
2265 u16 phy_data; 2318 u16 phy_data;
2266 2319
2267 DEBUGFUNC("e1000_check_for_link"); 2320 DEBUGFUNC("e1000_check_for_link");
2268 2321
2269 ctrl = er32(CTRL); 2322 ctrl = er32(CTRL);
2270 status = er32(STATUS); 2323 status = er32(STATUS);
2271 2324
2272 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 2325 /* On adapters with a MAC newer than 82544, SW Definable pin 1 will be
2273 * set when the optics detect a signal. On older adapters, it will be 2326 * set when the optics detect a signal. On older adapters, it will be
2274 * cleared when there is a signal. This applies to fiber media only. 2327 * cleared when there is a signal. This applies to fiber media only.
2275 */ 2328 */
2276 if ((hw->media_type == e1000_media_type_fiber) || 2329 if ((hw->media_type == e1000_media_type_fiber) ||
2277 (hw->media_type == e1000_media_type_internal_serdes)) { 2330 (hw->media_type == e1000_media_type_internal_serdes)) {
2278 rxcw = er32(RXCW); 2331 rxcw = er32(RXCW);
2279 2332
2280 if (hw->media_type == e1000_media_type_fiber) { 2333 if (hw->media_type == e1000_media_type_fiber) {
2281 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; 2334 signal =
2282 if (status & E1000_STATUS_LU) 2335 (hw->mac_type >
2283 hw->get_link_status = false; 2336 e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2284 } 2337 if (status & E1000_STATUS_LU)
2285 } 2338 hw->get_link_status = false;
2286 2339 }
2287 /* If we have a copper PHY then we only want to go out to the PHY 2340 }
2288 * registers to see if Auto-Neg has completed and/or if our link 2341
2289 * status has changed. The get_link_status flag will be set if we 2342 /* If we have a copper PHY then we only want to go out to the PHY
2290 * receive a Link Status Change interrupt or we have Rx Sequence 2343 * registers to see if Auto-Neg has completed and/or if our link
2291 * Errors. 2344 * status has changed. The get_link_status flag will be set if we
2292 */ 2345 * receive a Link Status Change interrupt or we have Rx Sequence
2293 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { 2346 * Errors.
2294 /* First we want to see if the MII Status Register reports 2347 */
2295 * link. If so, then we want to get the current speed/duplex 2348 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2296 * of the PHY. 2349 /* First we want to see if the MII Status Register reports
2297 * Read the register twice since the link bit is sticky. 2350 * link. If so, then we want to get the current speed/duplex
2298 */ 2351 * of the PHY.
2299 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2352 * Read the register twice since the link bit is sticky.
2300 if (ret_val) 2353 */
2301 return ret_val; 2354 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2302 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2355 if (ret_val)
2303 if (ret_val) 2356 return ret_val;
2304 return ret_val; 2357 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2305 2358 if (ret_val)
2306 if (phy_data & MII_SR_LINK_STATUS) { 2359 return ret_val;
2307 hw->get_link_status = false; 2360
2308 /* Check if there was DownShift, must be checked immediately after 2361 if (phy_data & MII_SR_LINK_STATUS) {
2309 * link-up */ 2362 hw->get_link_status = false;
2310 e1000_check_downshift(hw); 2363 /* Check if there was DownShift, must be checked immediately after
2311 2364 * link-up */
2312 /* If we are on 82544 or 82543 silicon and speed/duplex 2365 e1000_check_downshift(hw);
2313 * are forced to 10H or 10F, then we will implement the polarity 2366
2314 * reversal workaround. We disable interrupts first, and upon 2367 /* If we are on 82544 or 82543 silicon and speed/duplex
2315 * returning, place the devices interrupt state to its previous 2368 * are forced to 10H or 10F, then we will implement the polarity
2316 * value except for the link status change interrupt which will 2369 * reversal workaround. We disable interrupts first, and upon
2317 * happen due to the execution of this workaround. 2370 * returning, place the devices interrupt state to its previous
2318 */ 2371 * value except for the link status change interrupt which will
2319 2372 * happen due to the execution of this workaround.
2320 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && 2373 */
2321 (!hw->autoneg) && 2374
2322 (hw->forced_speed_duplex == e1000_10_full || 2375 if ((hw->mac_type == e1000_82544
2323 hw->forced_speed_duplex == e1000_10_half)) { 2376 || hw->mac_type == e1000_82543) && (!hw->autoneg)
2324 ew32(IMC, 0xffffffff); 2377 && (hw->forced_speed_duplex == e1000_10_full
2325 ret_val = e1000_polarity_reversal_workaround(hw); 2378 || hw->forced_speed_duplex == e1000_10_half)) {
2326 icr = er32(ICR); 2379 ew32(IMC, 0xffffffff);
2327 ew32(ICS, (icr & ~E1000_ICS_LSC)); 2380 ret_val =
2328 ew32(IMS, IMS_ENABLE_MASK); 2381 e1000_polarity_reversal_workaround(hw);
2329 } 2382 icr = er32(ICR);
2330 2383 ew32(ICS, (icr & ~E1000_ICS_LSC));
2331 } else { 2384 ew32(IMS, IMS_ENABLE_MASK);
2332 /* No link detected */ 2385 }
2333 e1000_config_dsp_after_link_change(hw, false); 2386
2334 return 0; 2387 } else {
2335 } 2388 /* No link detected */
2336 2389 e1000_config_dsp_after_link_change(hw, false);
2337 /* If we are forcing speed/duplex, then we simply return since 2390 return 0;
2338 * we have already determined whether we have link or not. 2391 }
2339 */ 2392
2340 if (!hw->autoneg) return -E1000_ERR_CONFIG; 2393 /* If we are forcing speed/duplex, then we simply return since
2341 2394 * we have already determined whether we have link or not.
2342 /* optimize the dsp settings for the igp phy */ 2395 */
2343 e1000_config_dsp_after_link_change(hw, true); 2396 if (!hw->autoneg)
2344 2397 return -E1000_ERR_CONFIG;
2345 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we 2398
2346 * have Si on board that is 82544 or newer, Auto 2399 /* optimize the dsp settings for the igp phy */
2347 * Speed Detection takes care of MAC speed/duplex 2400 e1000_config_dsp_after_link_change(hw, true);
2348 * configuration. So we only need to configure Collision 2401
2349 * Distance in the MAC. Otherwise, we need to force 2402 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2350 * speed/duplex on the MAC to the current PHY speed/duplex 2403 * have Si on board that is 82544 or newer, Auto
2351 * settings. 2404 * Speed Detection takes care of MAC speed/duplex
2352 */ 2405 * configuration. So we only need to configure Collision
2353 if (hw->mac_type >= e1000_82544) 2406 * Distance in the MAC. Otherwise, we need to force
2354 e1000_config_collision_dist(hw); 2407 * speed/duplex on the MAC to the current PHY speed/duplex
2355 else { 2408 * settings.
2356 ret_val = e1000_config_mac_to_phy(hw); 2409 */
2357 if (ret_val) { 2410 if (hw->mac_type >= e1000_82544)
2358 DEBUGOUT("Error configuring MAC to PHY settings\n"); 2411 e1000_config_collision_dist(hw);
2359 return ret_val; 2412 else {
2360 } 2413 ret_val = e1000_config_mac_to_phy(hw);
2361 } 2414 if (ret_val) {
2362 2415 DEBUGOUT
2363 /* Configure Flow Control now that Auto-Neg has completed. First, we 2416 ("Error configuring MAC to PHY settings\n");
2364 * need to restore the desired flow control settings because we may 2417 return ret_val;
2365 * have had to re-autoneg with a different link partner. 2418 }
2366 */ 2419 }
2367 ret_val = e1000_config_fc_after_link_up(hw); 2420
2368 if (ret_val) { 2421 /* Configure Flow Control now that Auto-Neg has completed. First, we
2369 DEBUGOUT("Error configuring flow control\n"); 2422 * need to restore the desired flow control settings because we may
2370 return ret_val; 2423 * have had to re-autoneg with a different link partner.
2371 } 2424 */
2372 2425 ret_val = e1000_config_fc_after_link_up(hw);
2373 /* At this point we know that we are on copper and we have 2426 if (ret_val) {
2374 * auto-negotiated link. These are conditions for checking the link 2427 DEBUGOUT("Error configuring flow control\n");
2375 * partner capability register. We use the link speed to determine if 2428 return ret_val;
2376 * TBI compatibility needs to be turned on or off. If the link is not 2429 }
2377 * at gigabit speed, then TBI compatibility is not needed. If we are 2430
2378 * at gigabit speed, we turn on TBI compatibility. 2431 /* At this point we know that we are on copper and we have
2379 */ 2432 * auto-negotiated link. These are conditions for checking the link
2380 if (hw->tbi_compatibility_en) { 2433 * partner capability register. We use the link speed to determine if
2381 u16 speed, duplex; 2434 * TBI compatibility needs to be turned on or off. If the link is not
2382 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 2435 * at gigabit speed, then TBI compatibility is not needed. If we are
2383 if (ret_val) { 2436 * at gigabit speed, we turn on TBI compatibility.
2384 DEBUGOUT("Error getting link speed and duplex\n"); 2437 */
2385 return ret_val; 2438 if (hw->tbi_compatibility_en) {
2386 } 2439 u16 speed, duplex;
2387 if (speed != SPEED_1000) { 2440 ret_val =
2388 /* If link speed is not set to gigabit speed, we do not need 2441 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2389 * to enable TBI compatibility. 2442 if (ret_val) {
2390 */ 2443 DEBUGOUT
2391 if (hw->tbi_compatibility_on) { 2444 ("Error getting link speed and duplex\n");
2392 /* If we previously were in the mode, turn it off. */ 2445 return ret_val;
2393 rctl = er32(RCTL); 2446 }
2394 rctl &= ~E1000_RCTL_SBP; 2447 if (speed != SPEED_1000) {
2395 ew32(RCTL, rctl); 2448 /* If link speed is not set to gigabit speed, we do not need
2396 hw->tbi_compatibility_on = false; 2449 * to enable TBI compatibility.
2397 } 2450 */
2398 } else { 2451 if (hw->tbi_compatibility_on) {
2399 /* If TBI compatibility is was previously off, turn it on. For 2452 /* If we previously were in the mode, turn it off. */
2400 * compatibility with a TBI link partner, we will store bad 2453 rctl = er32(RCTL);
2401 * packets. Some frames have an additional byte on the end and 2454 rctl &= ~E1000_RCTL_SBP;
2402 * will look like CRC errors to the hardware. 2455 ew32(RCTL, rctl);
2403 */ 2456 hw->tbi_compatibility_on = false;
2404 if (!hw->tbi_compatibility_on) { 2457 }
2405 hw->tbi_compatibility_on = true; 2458 } else {
2406 rctl = er32(RCTL); 2459 /* If TBI compatibility is was previously off, turn it on. For
2407 rctl |= E1000_RCTL_SBP; 2460 * compatibility with a TBI link partner, we will store bad
2408 ew32(RCTL, rctl); 2461 * packets. Some frames have an additional byte on the end and
2409 } 2462 * will look like CRC errors to to the hardware.
2410 } 2463 */
2411 } 2464 if (!hw->tbi_compatibility_on) {
2412 } 2465 hw->tbi_compatibility_on = true;
2413 2466 rctl = er32(RCTL);
2414 if ((hw->media_type == e1000_media_type_fiber) || 2467 rctl |= E1000_RCTL_SBP;
2415 (hw->media_type == e1000_media_type_internal_serdes)) 2468 ew32(RCTL, rctl);
2416 e1000_check_for_serdes_link_generic(hw); 2469 }
2417 2470 }
2418 return E1000_SUCCESS; 2471 }
2472 }
2473
2474 if ((hw->media_type == e1000_media_type_fiber) ||
2475 (hw->media_type == e1000_media_type_internal_serdes))
2476 e1000_check_for_serdes_link_generic(hw);
2477
2478 return E1000_SUCCESS;
2419} 2479}
2420 2480
2421/****************************************************************************** 2481/**
2482 * e1000_get_speed_and_duplex
2483 * @hw: Struct containing variables accessed by shared code
2484 * @speed: Speed of the connection
2485 * @duplex: Duplex setting of the connection
2486
2422 * Detects the current speed and duplex settings of the hardware. 2487 * Detects the current speed and duplex settings of the hardware.
2423 * 2488 */
2424 * hw - Struct containing variables accessed by shared code
2425 * speed - Speed of the connection
2426 * duplex - Duplex setting of the connection
2427 *****************************************************************************/
2428s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex) 2489s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
2429{ 2490{
2430 u32 status; 2491 u32 status;
2431 s32 ret_val; 2492 s32 ret_val;
2432 u16 phy_data; 2493 u16 phy_data;
2433 2494
2434 DEBUGFUNC("e1000_get_speed_and_duplex"); 2495 DEBUGFUNC("e1000_get_speed_and_duplex");
2435 2496
2436 if (hw->mac_type >= e1000_82543) { 2497 if (hw->mac_type >= e1000_82543) {
2437 status = er32(STATUS); 2498 status = er32(STATUS);
2438 if (status & E1000_STATUS_SPEED_1000) { 2499 if (status & E1000_STATUS_SPEED_1000) {
2439 *speed = SPEED_1000; 2500 *speed = SPEED_1000;
2440 DEBUGOUT("1000 Mbs, "); 2501 DEBUGOUT("1000 Mbs, ");
2441 } else if (status & E1000_STATUS_SPEED_100) { 2502 } else if (status & E1000_STATUS_SPEED_100) {
2442 *speed = SPEED_100; 2503 *speed = SPEED_100;
2443 DEBUGOUT("100 Mbs, "); 2504 DEBUGOUT("100 Mbs, ");
2444 } else { 2505 } else {
2445 *speed = SPEED_10; 2506 *speed = SPEED_10;
2446 DEBUGOUT("10 Mbs, "); 2507 DEBUGOUT("10 Mbs, ");
2447 } 2508 }
2448 2509
2449 if (status & E1000_STATUS_FD) { 2510 if (status & E1000_STATUS_FD) {
2450 *duplex = FULL_DUPLEX; 2511 *duplex = FULL_DUPLEX;
2451 DEBUGOUT("Full Duplex\n"); 2512 DEBUGOUT("Full Duplex\n");
2452 } else { 2513 } else {
2453 *duplex = HALF_DUPLEX; 2514 *duplex = HALF_DUPLEX;
2454 DEBUGOUT(" Half Duplex\n"); 2515 DEBUGOUT(" Half Duplex\n");
2455 } 2516 }
2456 } else { 2517 } else {
2457 DEBUGOUT("1000 Mbs, Full Duplex\n"); 2518 DEBUGOUT("1000 Mbs, Full Duplex\n");
2458 *speed = SPEED_1000; 2519 *speed = SPEED_1000;
2459 *duplex = FULL_DUPLEX; 2520 *duplex = FULL_DUPLEX;
2460 } 2521 }
2461 2522
2462 /* IGP01 PHY may advertise full duplex operation after speed downgrade even 2523 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
2463 * if it is operating at half duplex. Here we set the duplex settings to 2524 * if it is operating at half duplex. Here we set the duplex settings to
2464 * match the duplex in the link partner's capabilities. 2525 * match the duplex in the link partner's capabilities.
2465 */ 2526 */
2466 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { 2527 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
2467 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 2528 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
2468 if (ret_val) 2529 if (ret_val)
2469 return ret_val; 2530 return ret_val;
2470 2531
2471 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 2532 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2472 *duplex = HALF_DUPLEX; 2533 *duplex = HALF_DUPLEX;
2473 else { 2534 else {
2474 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); 2535 ret_val =
2475 if (ret_val) 2536 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
2476 return ret_val; 2537 if (ret_val)
2477 if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || 2538 return ret_val;
2478 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 2539 if ((*speed == SPEED_100
2479 *duplex = HALF_DUPLEX; 2540 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
2480 } 2541 || (*speed == SPEED_10
2481 } 2542 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2482 2543 *duplex = HALF_DUPLEX;
2483 return E1000_SUCCESS; 2544 }
2545 }
2546
2547 return E1000_SUCCESS;
2484} 2548}
2485 2549
2486/****************************************************************************** 2550/**
2487* Blocks until autoneg completes or times out (~4.5 seconds) 2551 * e1000_wait_autoneg
2488* 2552 * @hw: Struct containing variables accessed by shared code
2489* hw - Struct containing variables accessed by shared code 2553 *
2490******************************************************************************/ 2554 * Blocks until autoneg completes or times out (~4.5 seconds)
2555 */
2491static s32 e1000_wait_autoneg(struct e1000_hw *hw) 2556static s32 e1000_wait_autoneg(struct e1000_hw *hw)
2492{ 2557{
2493 s32 ret_val; 2558 s32 ret_val;
2494 u16 i; 2559 u16 i;
2495 u16 phy_data; 2560 u16 phy_data;
2496 2561
2497 DEBUGFUNC("e1000_wait_autoneg"); 2562 DEBUGFUNC("e1000_wait_autoneg");
2498 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 2563 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2499 2564
2500 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 2565 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2501 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 2566 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2502 /* Read the MII Status Register and wait for Auto-Neg 2567 /* Read the MII Status Register and wait for Auto-Neg
2503 * Complete bit to be set. 2568 * Complete bit to be set.
2504 */ 2569 */
2505 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2570 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2506 if (ret_val) 2571 if (ret_val)
2507 return ret_val; 2572 return ret_val;
2508 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 2573 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2509 if (ret_val) 2574 if (ret_val)
2510 return ret_val; 2575 return ret_val;
2511 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 2576 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
2512 return E1000_SUCCESS; 2577 return E1000_SUCCESS;
2513 } 2578 }
2514 msleep(100); 2579 msleep(100);
2515 } 2580 }
2516 return E1000_SUCCESS; 2581 return E1000_SUCCESS;
2517} 2582}
2518 2583
2519/****************************************************************************** 2584/**
2520* Raises the Management Data Clock 2585 * e1000_raise_mdi_clk - Raises the Management Data Clock
2521* 2586 * @hw: Struct containing variables accessed by shared code
2522* hw - Struct containing variables accessed by shared code 2587 * @ctrl: Device control register's current value
2523* ctrl - Device control register's current value 2588 */
2524******************************************************************************/
2525static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl) 2589static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
2526{ 2590{
2527 /* Raise the clock input to the Management Data Clock (by setting the MDC 2591 /* Raise the clock input to the Management Data Clock (by setting the MDC
2528 * bit), and then delay 10 microseconds. 2592 * bit), and then delay 10 microseconds.
2529 */ 2593 */
2530 ew32(CTRL, (*ctrl | E1000_CTRL_MDC)); 2594 ew32(CTRL, (*ctrl | E1000_CTRL_MDC));
2531 E1000_WRITE_FLUSH(); 2595 E1000_WRITE_FLUSH();
2532 udelay(10); 2596 udelay(10);
2533} 2597}
2534 2598
2535/****************************************************************************** 2599/**
2536* Lowers the Management Data Clock 2600 * e1000_lower_mdi_clk - Lowers the Management Data Clock
2537* 2601 * @hw: Struct containing variables accessed by shared code
2538* hw - Struct containing variables accessed by shared code 2602 * @ctrl: Device control register's current value
2539* ctrl - Device control register's current value 2603 */
2540******************************************************************************/
2541static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl) 2604static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
2542{ 2605{
2543 /* Lower the clock input to the Management Data Clock (by clearing the MDC 2606 /* Lower the clock input to the Management Data Clock (by clearing the MDC
2544 * bit), and then delay 10 microseconds. 2607 * bit), and then delay 10 microseconds.
2545 */ 2608 */
2546 ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC)); 2609 ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC));
2547 E1000_WRITE_FLUSH(); 2610 E1000_WRITE_FLUSH();
2548 udelay(10); 2611 udelay(10);
2549} 2612}
2550 2613
2551/****************************************************************************** 2614/**
2552* Shifts data bits out to the PHY 2615 * e1000_shift_out_mdi_bits - Shifts data bits out to the PHY
2553* 2616 * @hw: Struct containing variables accessed by shared code
2554* hw - Struct containing variables accessed by shared code 2617 * @data: Data to send out to the PHY
2555* data - Data to send out to the PHY 2618 * @count: Number of bits to shift out
2556* count - Number of bits to shift out 2619 *
2557* 2620 * Bits are shifted out in MSB to LSB order.
2558* Bits are shifted out in MSB to LSB order. 2621 */
2559******************************************************************************/
2560static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count) 2622static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count)
2561{ 2623{
2562 u32 ctrl; 2624 u32 ctrl;
2563 u32 mask; 2625 u32 mask;
2564 2626
2565 /* We need to shift "count" number of bits out to the PHY. So, the value 2627 /* We need to shift "count" number of bits out to the PHY. So, the value
2566 * in the "data" parameter will be shifted out to the PHY one bit at a 2628 * in the "data" parameter will be shifted out to the PHY one bit at a
2567 * time. In order to do this, "data" must be broken down into bits. 2629 * time. In order to do this, "data" must be broken down into bits.
2568 */ 2630 */
2569 mask = 0x01; 2631 mask = 0x01;
2570 mask <<= (count - 1); 2632 mask <<= (count - 1);
2571 2633
2572 ctrl = er32(CTRL); 2634 ctrl = er32(CTRL);
2573 2635
2574 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 2636 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2575 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 2637 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2576 2638
2577 while (mask) { 2639 while (mask) {
2578 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and 2640 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2579 * then raising and lowering the Management Data Clock. A "0" is 2641 * then raising and lowering the Management Data Clock. A "0" is
2580 * shifted out to the PHY by setting the MDIO bit to "0" and then 2642 * shifted out to the PHY by setting the MDIO bit to "0" and then
2581 * raising and lowering the clock. 2643 * raising and lowering the clock.
2582 */ 2644 */
2583 if (data & mask) 2645 if (data & mask)
2584 ctrl |= E1000_CTRL_MDIO; 2646 ctrl |= E1000_CTRL_MDIO;
2585 else 2647 else
2586 ctrl &= ~E1000_CTRL_MDIO; 2648 ctrl &= ~E1000_CTRL_MDIO;
2587 2649
2588 ew32(CTRL, ctrl); 2650 ew32(CTRL, ctrl);
2589 E1000_WRITE_FLUSH(); 2651 E1000_WRITE_FLUSH();
2590 2652
2591 udelay(10); 2653 udelay(10);
2592 2654
2593 e1000_raise_mdi_clk(hw, &ctrl); 2655 e1000_raise_mdi_clk(hw, &ctrl);
2594 e1000_lower_mdi_clk(hw, &ctrl); 2656 e1000_lower_mdi_clk(hw, &ctrl);
2595 2657
2596 mask = mask >> 1; 2658 mask = mask >> 1;
2597 } 2659 }
2598} 2660}
2599 2661
2600/****************************************************************************** 2662/**
2601* Shifts data bits in from the PHY 2663 * e1000_shift_in_mdi_bits - Shifts data bits in from the PHY
2602* 2664 * @hw: Struct containing variables accessed by shared code
2603* hw - Struct containing variables accessed by shared code 2665 *
2604* 2666 * Bits are shifted in in MSB to LSB order.
2605* Bits are shifted in in MSB to LSB order. 2667 */
2606******************************************************************************/
2607static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw) 2668static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2608{ 2669{
2609 u32 ctrl; 2670 u32 ctrl;
2610 u16 data = 0; 2671 u16 data = 0;
2611 u8 i; 2672 u8 i;
2612 2673
2613 /* In order to read a register from the PHY, we need to shift in a total 2674 /* In order to read a register from the PHY, we need to shift in a total
2614 * of 18 bits from the PHY. The first two bit (turnaround) times are used 2675 * of 18 bits from the PHY. The first two bit (turnaround) times are used
2615 * to avoid contention on the MDIO pin when a read operation is performed. 2676 * to avoid contention on the MDIO pin when a read operation is performed.
2616 * These two bits are ignored by us and thrown away. Bits are "shifted in" 2677 * These two bits are ignored by us and thrown away. Bits are "shifted in"
2617 * by raising the input to the Management Data Clock (setting the MDC bit), 2678 * by raising the input to the Management Data Clock (setting the MDC bit),
2618 * and then reading the value of the MDIO bit. 2679 * and then reading the value of the MDIO bit.
2619 */ 2680 */
2620 ctrl = er32(CTRL); 2681 ctrl = er32(CTRL);
2621 2682
2622 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ 2683 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2623 ctrl &= ~E1000_CTRL_MDIO_DIR; 2684 ctrl &= ~E1000_CTRL_MDIO_DIR;
2624 ctrl &= ~E1000_CTRL_MDIO; 2685 ctrl &= ~E1000_CTRL_MDIO;
2625 2686
2626 ew32(CTRL, ctrl); 2687 ew32(CTRL, ctrl);
2627 E1000_WRITE_FLUSH(); 2688 E1000_WRITE_FLUSH();
2628 2689
2629 /* Raise and Lower the clock before reading in the data. This accounts for 2690 /* Raise and Lower the clock before reading in the data. This accounts for
2630 * the turnaround bits. The first clock occurred when we clocked out the 2691 * the turnaround bits. The first clock occurred when we clocked out the
2631 * last bit of the Register Address. 2692 * last bit of the Register Address.
2632 */ 2693 */
2633 e1000_raise_mdi_clk(hw, &ctrl); 2694 e1000_raise_mdi_clk(hw, &ctrl);
2634 e1000_lower_mdi_clk(hw, &ctrl); 2695 e1000_lower_mdi_clk(hw, &ctrl);
2635 2696
2636 for (data = 0, i = 0; i < 16; i++) { 2697 for (data = 0, i = 0; i < 16; i++) {
2637 data = data << 1; 2698 data = data << 1;
2638 e1000_raise_mdi_clk(hw, &ctrl); 2699 e1000_raise_mdi_clk(hw, &ctrl);
2639 ctrl = er32(CTRL); 2700 ctrl = er32(CTRL);
2640 /* Check to see if we shifted in a "1". */ 2701 /* Check to see if we shifted in a "1". */
2641 if (ctrl & E1000_CTRL_MDIO) 2702 if (ctrl & E1000_CTRL_MDIO)
2642 data |= 1; 2703 data |= 1;
2643 e1000_lower_mdi_clk(hw, &ctrl); 2704 e1000_lower_mdi_clk(hw, &ctrl);
2644 } 2705 }
2645 2706
2646 e1000_raise_mdi_clk(hw, &ctrl); 2707 e1000_raise_mdi_clk(hw, &ctrl);
2647 e1000_lower_mdi_clk(hw, &ctrl); 2708 e1000_lower_mdi_clk(hw, &ctrl);
2648 2709
2649 return data; 2710 return data;
2650} 2711}
2651 2712
2652/***************************************************************************** 2713
2653* Reads the value from a PHY register, if the value is on a specific non zero 2714/**
2654* page, sets the page first. 2715 * e1000_read_phy_reg - read a phy register
2655* hw - Struct containing variables accessed by shared code 2716 * @hw: Struct containing variables accessed by shared code
2656* reg_addr - address of the PHY register to read 2717 * @reg_addr: address of the PHY register to read
2657******************************************************************************/ 2718 *
2719 * Reads the value from a PHY register, if the value is on a specific non zero
2720 * page, sets the page first.
2721 */
2658s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data) 2722s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)
2659{ 2723{
2660 u32 ret_val; 2724 u32 ret_val;
2661 2725
2662 DEBUGFUNC("e1000_read_phy_reg"); 2726 DEBUGFUNC("e1000_read_phy_reg");
2663 2727
2664 if ((hw->phy_type == e1000_phy_igp) && 2728 if ((hw->phy_type == e1000_phy_igp) &&
2665 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 2729 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2666 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 2730 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2667 (u16)reg_addr); 2731 (u16) reg_addr);
2668 if (ret_val) 2732 if (ret_val)
2669 return ret_val; 2733 return ret_val;
2670 } 2734 }
2735
2736 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2737 phy_data);
2671 2738
2672 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 2739 return ret_val;
2673 phy_data);
2674 return ret_val;
2675} 2740}
2676 2741
2677static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 2742static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2678 u16 *phy_data) 2743 u16 *phy_data)
2679{ 2744{
2680 u32 i; 2745 u32 i;
2681 u32 mdic = 0; 2746 u32 mdic = 0;
2682 const u32 phy_addr = 1; 2747 const u32 phy_addr = 1;
2683 2748
2684 DEBUGFUNC("e1000_read_phy_reg_ex"); 2749 DEBUGFUNC("e1000_read_phy_reg_ex");
2685 2750
2686 if (reg_addr > MAX_PHY_REG_ADDRESS) { 2751 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2687 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 2752 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2688 return -E1000_ERR_PARAM; 2753 return -E1000_ERR_PARAM;
2689 } 2754 }
2690 2755
2691 if (hw->mac_type > e1000_82543) { 2756 if (hw->mac_type > e1000_82543) {
2692 /* Set up Op-code, Phy Address, and register address in the MDI 2757 /* Set up Op-code, Phy Address, and register address in the MDI
2693 * Control register. The MAC will take care of interfacing with the 2758 * Control register. The MAC will take care of interfacing with the
2694 * PHY to retrieve the desired data. 2759 * PHY to retrieve the desired data.
2695 */ 2760 */
2696 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 2761 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2697 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2762 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2698 (E1000_MDIC_OP_READ)); 2763 (E1000_MDIC_OP_READ));
2699 2764
2700 ew32(MDIC, mdic); 2765 ew32(MDIC, mdic);
2701 2766
2702 /* Poll the ready bit to see if the MDI read completed */ 2767 /* Poll the ready bit to see if the MDI read completed */
2703 for (i = 0; i < 64; i++) { 2768 for (i = 0; i < 64; i++) {
2704 udelay(50); 2769 udelay(50);
2705 mdic = er32(MDIC); 2770 mdic = er32(MDIC);
2706 if (mdic & E1000_MDIC_READY) break; 2771 if (mdic & E1000_MDIC_READY)
2707 } 2772 break;
2708 if (!(mdic & E1000_MDIC_READY)) { 2773 }
2709 DEBUGOUT("MDI Read did not complete\n"); 2774 if (!(mdic & E1000_MDIC_READY)) {
2710 return -E1000_ERR_PHY; 2775 DEBUGOUT("MDI Read did not complete\n");
2711 } 2776 return -E1000_ERR_PHY;
2712 if (mdic & E1000_MDIC_ERROR) { 2777 }
2713 DEBUGOUT("MDI Error\n"); 2778 if (mdic & E1000_MDIC_ERROR) {
2714 return -E1000_ERR_PHY; 2779 DEBUGOUT("MDI Error\n");
2715 } 2780 return -E1000_ERR_PHY;
2716 *phy_data = (u16)mdic; 2781 }
2717 } else { 2782 *phy_data = (u16) mdic;
2718 /* We must first send a preamble through the MDIO pin to signal the 2783 } else {
2719 * beginning of an MII instruction. This is done by sending 32 2784 /* We must first send a preamble through the MDIO pin to signal the
2720 * consecutive "1" bits. 2785 * beginning of an MII instruction. This is done by sending 32
2721 */ 2786 * consecutive "1" bits.
2722 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 2787 */
2723 2788 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2724 /* Now combine the next few fields that are required for a read 2789
2725 * operation. We use this method instead of calling the 2790 /* Now combine the next few fields that are required for a read
2726 * e1000_shift_out_mdi_bits routine five different times. The format of 2791 * operation. We use this method instead of calling the
2727 * a MII read instruction consists of a shift out of 14 bits and is 2792 * e1000_shift_out_mdi_bits routine five different times. The format of
2728 * defined as follows: 2793 * a MII read instruction consists of a shift out of 14 bits and is
2729 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> 2794 * defined as follows:
2730 * followed by a shift in of 18 bits. This first two bits shifted in 2795 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2731 * are TurnAround bits used to avoid contention on the MDIO pin when a 2796 * followed by a shift in of 18 bits. This first two bits shifted in
2732 * READ operation is performed. These two bits are thrown away 2797 * are TurnAround bits used to avoid contention on the MDIO pin when a
2733 * followed by a shift in of 16 bits which contains the desired data. 2798 * READ operation is performed. These two bits are thrown away
2734 */ 2799 * followed by a shift in of 16 bits which contains the desired data.
2735 mdic = ((reg_addr) | (phy_addr << 5) | 2800 */
2736 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 2801 mdic = ((reg_addr) | (phy_addr << 5) |
2737 2802 (PHY_OP_READ << 10) | (PHY_SOF << 12));
2738 e1000_shift_out_mdi_bits(hw, mdic, 14); 2803
2739 2804 e1000_shift_out_mdi_bits(hw, mdic, 14);
2740 /* Now that we've shifted out the read command to the MII, we need to 2805
2741 * "shift in" the 16-bit value (18 total bits) of the requested PHY 2806 /* Now that we've shifted out the read command to the MII, we need to
2742 * register address. 2807 * "shift in" the 16-bit value (18 total bits) of the requested PHY
2743 */ 2808 * register address.
2744 *phy_data = e1000_shift_in_mdi_bits(hw); 2809 */
2745 } 2810 *phy_data = e1000_shift_in_mdi_bits(hw);
2746 return E1000_SUCCESS; 2811 }
2812 return E1000_SUCCESS;
2747} 2813}
2748 2814
2749/****************************************************************************** 2815/**
2750* Writes a value to a PHY register 2816 * e1000_write_phy_reg - write a phy register
2751* 2817 *
2752* hw - Struct containing variables accessed by shared code 2818 * @hw: Struct containing variables accessed by shared code
2753* reg_addr - address of the PHY register to write 2819 * @reg_addr: address of the PHY register to write
2754* data - data to write to the PHY 2820 * @data: data to write to the PHY
2755******************************************************************************/ 2821
2822 * Writes a value to a PHY register
2823 */
2756s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data) 2824s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
2757{ 2825{
2758 u32 ret_val; 2826 u32 ret_val;
2759 2827
2760 DEBUGFUNC("e1000_write_phy_reg"); 2828 DEBUGFUNC("e1000_write_phy_reg");
2761 2829
2762 if ((hw->phy_type == e1000_phy_igp) && 2830 if ((hw->phy_type == e1000_phy_igp) &&
2763 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 2831 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2764 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 2832 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2765 (u16)reg_addr); 2833 (u16) reg_addr);
2766 if (ret_val) 2834 if (ret_val)
2767 return ret_val; 2835 return ret_val;
2768 } 2836 }
2769 2837
2770 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 2838 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2771 phy_data); 2839 phy_data);
2772 2840
2773 return ret_val; 2841 return ret_val;
2774} 2842}
2775 2843
2776static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr, 2844static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2777 u16 phy_data) 2845 u16 phy_data)
2778{ 2846{
2779 u32 i; 2847 u32 i;
2780 u32 mdic = 0; 2848 u32 mdic = 0;
2781 const u32 phy_addr = 1; 2849 const u32 phy_addr = 1;
2782 2850
2783 DEBUGFUNC("e1000_write_phy_reg_ex"); 2851 DEBUGFUNC("e1000_write_phy_reg_ex");
2784 2852
2785 if (reg_addr > MAX_PHY_REG_ADDRESS) { 2853 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2786 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 2854 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2787 return -E1000_ERR_PARAM; 2855 return -E1000_ERR_PARAM;
2788 } 2856 }
2789 2857
2790 if (hw->mac_type > e1000_82543) { 2858 if (hw->mac_type > e1000_82543) {
2791 /* Set up Op-code, Phy Address, register address, and data intended 2859 /* Set up Op-code, Phy Address, register address, and data intended
2792 * for the PHY register in the MDI Control register. The MAC will take 2860 * for the PHY register in the MDI Control register. The MAC will take
2793 * care of interfacing with the PHY to send the desired data. 2861 * care of interfacing with the PHY to send the desired data.
2794 */ 2862 */
2795 mdic = (((u32)phy_data) | 2863 mdic = (((u32) phy_data) |
2796 (reg_addr << E1000_MDIC_REG_SHIFT) | 2864 (reg_addr << E1000_MDIC_REG_SHIFT) |
2797 (phy_addr << E1000_MDIC_PHY_SHIFT) | 2865 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2798 (E1000_MDIC_OP_WRITE)); 2866 (E1000_MDIC_OP_WRITE));
2799 2867
2800 ew32(MDIC, mdic); 2868 ew32(MDIC, mdic);
2801 2869
2802 /* Poll the ready bit to see if the MDI read completed */ 2870 /* Poll the ready bit to see if the MDI read completed */
2803 for (i = 0; i < 641; i++) { 2871 for (i = 0; i < 641; i++) {
2804 udelay(5); 2872 udelay(5);
2805 mdic = er32(MDIC); 2873 mdic = er32(MDIC);
2806 if (mdic & E1000_MDIC_READY) break; 2874 if (mdic & E1000_MDIC_READY)
2807 } 2875 break;
2808 if (!(mdic & E1000_MDIC_READY)) { 2876 }
2809 DEBUGOUT("MDI Write did not complete\n"); 2877 if (!(mdic & E1000_MDIC_READY)) {
2810 return -E1000_ERR_PHY; 2878 DEBUGOUT("MDI Write did not complete\n");
2811 } 2879 return -E1000_ERR_PHY;
2812 } else { 2880 }
2813 /* We'll need to use the SW defined pins to shift the write command 2881 } else {
2814 * out to the PHY. We first send a preamble to the PHY to signal the 2882 /* We'll need to use the SW defined pins to shift the write command
2815 * beginning of the MII instruction. This is done by sending 32 2883 * out to the PHY. We first send a preamble to the PHY to signal the
2816 * consecutive "1" bits. 2884 * beginning of the MII instruction. This is done by sending 32
2817 */ 2885 * consecutive "1" bits.
2818 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 2886 */
2819 2887 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2820 /* Now combine the remaining required fields that will indicate a 2888
2821 * write operation. We use this method instead of calling the 2889 /* Now combine the remaining required fields that will indicate a
2822 * e1000_shift_out_mdi_bits routine for each field in the command. The 2890 * write operation. We use this method instead of calling the
2823 * format of a MII write instruction is as follows: 2891 * e1000_shift_out_mdi_bits routine for each field in the command. The
2824 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 2892 * format of a MII write instruction is as follows:
2825 */ 2893 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2826 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | 2894 */
2827 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 2895 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
2828 mdic <<= 16; 2896 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
2829 mdic |= (u32)phy_data; 2897 mdic <<= 16;
2830 2898 mdic |= (u32) phy_data;
2831 e1000_shift_out_mdi_bits(hw, mdic, 32); 2899
2832 } 2900 e1000_shift_out_mdi_bits(hw, mdic, 32);
2833 2901 }
2834 return E1000_SUCCESS; 2902
2903 return E1000_SUCCESS;
2835} 2904}
2836 2905
2837/****************************************************************************** 2906/**
2838* Returns the PHY to the power-on reset state 2907 * e1000_phy_hw_reset - reset the phy, hardware style
2839* 2908 * @hw: Struct containing variables accessed by shared code
2840* hw - Struct containing variables accessed by shared code 2909 *
2841******************************************************************************/ 2910 * Returns the PHY to the power-on reset state
2911 */
2842s32 e1000_phy_hw_reset(struct e1000_hw *hw) 2912s32 e1000_phy_hw_reset(struct e1000_hw *hw)
2843{ 2913{
2844 u32 ctrl, ctrl_ext; 2914 u32 ctrl, ctrl_ext;
2845 u32 led_ctrl; 2915 u32 led_ctrl;
2846 s32 ret_val; 2916 s32 ret_val;
2847 2917
2848 DEBUGFUNC("e1000_phy_hw_reset"); 2918 DEBUGFUNC("e1000_phy_hw_reset");
2849 2919
2850 DEBUGOUT("Resetting Phy...\n"); 2920 DEBUGOUT("Resetting Phy...\n");
2851 2921
2852 if (hw->mac_type > e1000_82543) { 2922 if (hw->mac_type > e1000_82543) {
2853 /* Read the device control register and assert the E1000_CTRL_PHY_RST 2923 /* Read the device control register and assert the E1000_CTRL_PHY_RST
2854 * bit. Then, take it out of reset. 2924 * bit. Then, take it out of reset.
2855 * For e1000 hardware, we delay for 10ms between the assert 2925 * For e1000 hardware, we delay for 10ms between the assert
2856 * and deassert. 2926 * and deassert.
2857 */ 2927 */
2858 ctrl = er32(CTRL); 2928 ctrl = er32(CTRL);
2859 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); 2929 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2860 E1000_WRITE_FLUSH(); 2930 E1000_WRITE_FLUSH();
2861 2931
2862 msleep(10); 2932 msleep(10);
2863 2933
2864 ew32(CTRL, ctrl); 2934 ew32(CTRL, ctrl);
2865 E1000_WRITE_FLUSH(); 2935 E1000_WRITE_FLUSH();
2866 } else { 2936
2867 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR 2937 } else {
2868 * bit to put the PHY into reset. Then, take it out of reset. 2938 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
2869 */ 2939 * bit to put the PHY into reset. Then, take it out of reset.
2870 ctrl_ext = er32(CTRL_EXT); 2940 */
2871 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 2941 ctrl_ext = er32(CTRL_EXT);
2872 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 2942 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
2873 ew32(CTRL_EXT, ctrl_ext); 2943 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
2874 E1000_WRITE_FLUSH(); 2944 ew32(CTRL_EXT, ctrl_ext);
2875 msleep(10); 2945 E1000_WRITE_FLUSH();
2876 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 2946 msleep(10);
2877 ew32(CTRL_EXT, ctrl_ext); 2947 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
2878 E1000_WRITE_FLUSH(); 2948 ew32(CTRL_EXT, ctrl_ext);
2879 } 2949 E1000_WRITE_FLUSH();
2880 udelay(150); 2950 }
2881 2951 udelay(150);
2882 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { 2952
2883 /* Configure activity LED after PHY reset */ 2953 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2884 led_ctrl = er32(LEDCTL); 2954 /* Configure activity LED after PHY reset */
2885 led_ctrl &= IGP_ACTIVITY_LED_MASK; 2955 led_ctrl = er32(LEDCTL);
2886 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 2956 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2887 ew32(LEDCTL, led_ctrl); 2957 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2888 } 2958 ew32(LEDCTL, led_ctrl);
2889 2959 }
2890 /* Wait for FW to finish PHY configuration. */ 2960
2891 ret_val = e1000_get_phy_cfg_done(hw); 2961 /* Wait for FW to finish PHY configuration. */
2892 if (ret_val != E1000_SUCCESS) 2962 ret_val = e1000_get_phy_cfg_done(hw);
2893 return ret_val; 2963 if (ret_val != E1000_SUCCESS)
2894 2964 return ret_val;
2895 return ret_val; 2965
2966 return ret_val;
2896} 2967}
2897 2968
2898/****************************************************************************** 2969/**
2899* Resets the PHY 2970 * e1000_phy_reset - reset the phy to commit settings
2900* 2971 * @hw: Struct containing variables accessed by shared code
2901* hw - Struct containing variables accessed by shared code 2972 *
2902* 2973 * Resets the PHY
2903* Sets bit 15 of the MII Control register 2974 * Sets bit 15 of the MII Control register
2904******************************************************************************/ 2975 */
2905s32 e1000_phy_reset(struct e1000_hw *hw) 2976s32 e1000_phy_reset(struct e1000_hw *hw)
2906{ 2977{
2907 s32 ret_val; 2978 s32 ret_val;
2908 u16 phy_data; 2979 u16 phy_data;
2909 2980
2910 DEBUGFUNC("e1000_phy_reset"); 2981 DEBUGFUNC("e1000_phy_reset");
2911 2982
2912 switch (hw->phy_type) { 2983 switch (hw->phy_type) {
2913 case e1000_phy_igp: 2984 case e1000_phy_igp:
2914 ret_val = e1000_phy_hw_reset(hw); 2985 ret_val = e1000_phy_hw_reset(hw);
2915 if (ret_val) 2986 if (ret_val)
2916 return ret_val; 2987 return ret_val;
2917 break; 2988 break;
2918 default: 2989 default:
2919 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); 2990 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2920 if (ret_val) 2991 if (ret_val)
2921 return ret_val; 2992 return ret_val;
2922 2993
2923 phy_data |= MII_CR_RESET; 2994 phy_data |= MII_CR_RESET;
2924 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); 2995 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2925 if (ret_val) 2996 if (ret_val)
2926 return ret_val; 2997 return ret_val;
2927 2998
2928 udelay(1); 2999 udelay(1);
2929 break; 3000 break;
2930 } 3001 }
2931 3002
2932 if (hw->phy_type == e1000_phy_igp) 3003 if (hw->phy_type == e1000_phy_igp)
2933 e1000_phy_init_script(hw); 3004 e1000_phy_init_script(hw);
2934 3005
2935 return E1000_SUCCESS; 3006 return E1000_SUCCESS;
2936} 3007}
2937 3008
2938/****************************************************************************** 3009/**
2939* Probes the expected PHY address for known PHY IDs 3010 * e1000_detect_gig_phy - check the phy type
2940* 3011 * @hw: Struct containing variables accessed by shared code
2941* hw - Struct containing variables accessed by shared code 3012 *
2942******************************************************************************/ 3013 * Probes the expected PHY address for known PHY IDs
3014 */
2943static s32 e1000_detect_gig_phy(struct e1000_hw *hw) 3015static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
2944{ 3016{
2945 s32 phy_init_status, ret_val; 3017 s32 phy_init_status, ret_val;
2946 u16 phy_id_high, phy_id_low; 3018 u16 phy_id_high, phy_id_low;
2947 bool match = false; 3019 bool match = false;
2948 3020
2949 DEBUGFUNC("e1000_detect_gig_phy"); 3021 DEBUGFUNC("e1000_detect_gig_phy");
2950 3022
2951 if (hw->phy_id != 0) 3023 if (hw->phy_id != 0)
2952 return E1000_SUCCESS; 3024 return E1000_SUCCESS;
2953 3025
2954 /* Read the PHY ID Registers to identify which PHY is onboard. */ 3026 /* Read the PHY ID Registers to identify which PHY is onboard. */
2955 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); 3027 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
2956 if (ret_val) 3028 if (ret_val)
2957 return ret_val; 3029 return ret_val;
2958 3030
2959 hw->phy_id = (u32)(phy_id_high << 16); 3031 hw->phy_id = (u32) (phy_id_high << 16);
2960 udelay(20); 3032 udelay(20);
2961 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); 3033 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
2962 if (ret_val) 3034 if (ret_val)
2963 return ret_val; 3035 return ret_val;
2964 3036
2965 hw->phy_id |= (u32)(phy_id_low & PHY_REVISION_MASK); 3037 hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK);
2966 hw->phy_revision = (u32)phy_id_low & ~PHY_REVISION_MASK; 3038 hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK;
2967 3039
2968 switch (hw->mac_type) { 3040 switch (hw->mac_type) {
2969 case e1000_82543: 3041 case e1000_82543:
2970 if (hw->phy_id == M88E1000_E_PHY_ID) match = true; 3042 if (hw->phy_id == M88E1000_E_PHY_ID)
2971 break; 3043 match = true;
2972 case e1000_82544: 3044 break;
2973 if (hw->phy_id == M88E1000_I_PHY_ID) match = true; 3045 case e1000_82544:
2974 break; 3046 if (hw->phy_id == M88E1000_I_PHY_ID)
2975 case e1000_82540: 3047 match = true;
2976 case e1000_82545: 3048 break;
2977 case e1000_82545_rev_3: 3049 case e1000_82540:
2978 case e1000_82546: 3050 case e1000_82545:
2979 case e1000_82546_rev_3: 3051 case e1000_82545_rev_3:
2980 if (hw->phy_id == M88E1011_I_PHY_ID) match = true; 3052 case e1000_82546:
2981 break; 3053 case e1000_82546_rev_3:
2982 case e1000_82541: 3054 if (hw->phy_id == M88E1011_I_PHY_ID)
2983 case e1000_82541_rev_2: 3055 match = true;
2984 case e1000_82547: 3056 break;
2985 case e1000_82547_rev_2: 3057 case e1000_82541:
2986 if (hw->phy_id == IGP01E1000_I_PHY_ID) match = true; 3058 case e1000_82541_rev_2:
2987 break; 3059 case e1000_82547:
2988 default: 3060 case e1000_82547_rev_2:
2989 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); 3061 if (hw->phy_id == IGP01E1000_I_PHY_ID)
2990 return -E1000_ERR_CONFIG; 3062 match = true;
2991 } 3063 break;
2992 phy_init_status = e1000_set_phy_type(hw); 3064 default:
2993 3065 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
2994 if ((match) && (phy_init_status == E1000_SUCCESS)) { 3066 return -E1000_ERR_CONFIG;
2995 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); 3067 }
2996 return E1000_SUCCESS; 3068 phy_init_status = e1000_set_phy_type(hw);
2997 } 3069
2998 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); 3070 if ((match) && (phy_init_status == E1000_SUCCESS)) {
2999 return -E1000_ERR_PHY; 3071 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
3072 return E1000_SUCCESS;
3073 }
3074 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
3075 return -E1000_ERR_PHY;
3000} 3076}
3001 3077
3002/****************************************************************************** 3078/**
3003* Resets the PHY's DSP 3079 * e1000_phy_reset_dsp - reset DSP
3004* 3080 * @hw: Struct containing variables accessed by shared code
3005* hw - Struct containing variables accessed by shared code 3081 *
3006******************************************************************************/ 3082 * Resets the PHY's DSP
3083 */
3007static s32 e1000_phy_reset_dsp(struct e1000_hw *hw) 3084static s32 e1000_phy_reset_dsp(struct e1000_hw *hw)
3008{ 3085{
3009 s32 ret_val; 3086 s32 ret_val;
3010 DEBUGFUNC("e1000_phy_reset_dsp"); 3087 DEBUGFUNC("e1000_phy_reset_dsp");
3011 3088
3012 do { 3089 do {
3013 ret_val = e1000_write_phy_reg(hw, 29, 0x001d); 3090 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
3014 if (ret_val) break; 3091 if (ret_val)
3015 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); 3092 break;
3016 if (ret_val) break; 3093 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
3017 ret_val = e1000_write_phy_reg(hw, 30, 0x0000); 3094 if (ret_val)
3018 if (ret_val) break; 3095 break;
3019 ret_val = E1000_SUCCESS; 3096 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
3020 } while (0); 3097 if (ret_val)
3021 3098 break;
3022 return ret_val; 3099 ret_val = E1000_SUCCESS;
3100 } while (0);
3101
3102 return ret_val;
3023} 3103}
3024 3104
3025/****************************************************************************** 3105/**
3026* Get PHY information from various PHY registers for igp PHY only. 3106 * e1000_phy_igp_get_info - get igp specific registers
3027* 3107 * @hw: Struct containing variables accessed by shared code
3028* hw - Struct containing variables accessed by shared code 3108 * @phy_info: PHY information structure
3029* phy_info - PHY information structure 3109 *
3030******************************************************************************/ 3110 * Get PHY information from various PHY registers for igp PHY only.
3111 */
3031static s32 e1000_phy_igp_get_info(struct e1000_hw *hw, 3112static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
3032 struct e1000_phy_info *phy_info) 3113 struct e1000_phy_info *phy_info)
3033{ 3114{
3034 s32 ret_val; 3115 s32 ret_val;
3035 u16 phy_data, min_length, max_length, average; 3116 u16 phy_data, min_length, max_length, average;
3036 e1000_rev_polarity polarity; 3117 e1000_rev_polarity polarity;
3037 3118
3038 DEBUGFUNC("e1000_phy_igp_get_info"); 3119 DEBUGFUNC("e1000_phy_igp_get_info");
3039 3120
3040 /* The downshift status is checked only once, after link is established, 3121 /* The downshift status is checked only once, after link is established,
3041 * and it stored in the hw->speed_downgraded parameter. */ 3122 * and it stored in the hw->speed_downgraded parameter. */
3042 phy_info->downshift = (e1000_downshift)hw->speed_downgraded; 3123 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3043 3124
3044 /* IGP01E1000 does not need to support it. */ 3125 /* IGP01E1000 does not need to support it. */
3045 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; 3126 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
3046 3127
3047 /* IGP01E1000 always correct polarity reversal */ 3128 /* IGP01E1000 always correct polarity reversal */
3048 phy_info->polarity_correction = e1000_polarity_reversal_enabled; 3129 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
3049 3130
3050 /* Check polarity status */ 3131 /* Check polarity status */
3051 ret_val = e1000_check_polarity(hw, &polarity); 3132 ret_val = e1000_check_polarity(hw, &polarity);
3052 if (ret_val) 3133 if (ret_val)
3053 return ret_val; 3134 return ret_val;
3054 3135
3055 phy_info->cable_polarity = polarity; 3136 phy_info->cable_polarity = polarity;
3056 3137
3057 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); 3138 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
3058 if (ret_val) 3139 if (ret_val)
3059 return ret_val; 3140 return ret_val;
3060 3141
3061 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >> 3142 phy_info->mdix_mode =
3062 IGP01E1000_PSSR_MDIX_SHIFT); 3143 (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >>
3063 3144 IGP01E1000_PSSR_MDIX_SHIFT);
3064 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 3145
3065 IGP01E1000_PSSR_SPEED_1000MBPS) { 3146 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
3066 /* Local/Remote Receiver Information are only valid at 1000 Mbps */ 3147 IGP01E1000_PSSR_SPEED_1000MBPS) {
3067 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 3148 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
3068 if (ret_val) 3149 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3069 return ret_val; 3150 if (ret_val)
3070 3151 return ret_val;
3071 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> 3152
3072 SR_1000T_LOCAL_RX_STATUS_SHIFT) ? 3153 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3073 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3154 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3074 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> 3155 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3075 SR_1000T_REMOTE_RX_STATUS_SHIFT) ? 3156 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3076 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3157 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3077 3158 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3078 /* Get cable length */ 3159
3079 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); 3160 /* Get cable length */
3080 if (ret_val) 3161 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
3081 return ret_val; 3162 if (ret_val)
3082 3163 return ret_val;
3083 /* Translate to old method */ 3164
3084 average = (max_length + min_length) / 2; 3165 /* Translate to old method */
3085 3166 average = (max_length + min_length) / 2;
3086 if (average <= e1000_igp_cable_length_50) 3167
3087 phy_info->cable_length = e1000_cable_length_50; 3168 if (average <= e1000_igp_cable_length_50)
3088 else if (average <= e1000_igp_cable_length_80) 3169 phy_info->cable_length = e1000_cable_length_50;
3089 phy_info->cable_length = e1000_cable_length_50_80; 3170 else if (average <= e1000_igp_cable_length_80)
3090 else if (average <= e1000_igp_cable_length_110) 3171 phy_info->cable_length = e1000_cable_length_50_80;
3091 phy_info->cable_length = e1000_cable_length_80_110; 3172 else if (average <= e1000_igp_cable_length_110)
3092 else if (average <= e1000_igp_cable_length_140) 3173 phy_info->cable_length = e1000_cable_length_80_110;
3093 phy_info->cable_length = e1000_cable_length_110_140; 3174 else if (average <= e1000_igp_cable_length_140)
3094 else 3175 phy_info->cable_length = e1000_cable_length_110_140;
3095 phy_info->cable_length = e1000_cable_length_140; 3176 else
3096 } 3177 phy_info->cable_length = e1000_cable_length_140;
3097 3178 }
3098 return E1000_SUCCESS;
3099}
3100 3179
3180 return E1000_SUCCESS;
3181}
3101 3182
3102/****************************************************************************** 3183/**
3103* Get PHY information from various PHY registers fot m88 PHY only. 3184 * e1000_phy_m88_get_info - get m88 specific registers
3104* 3185 * @hw: Struct containing variables accessed by shared code
3105* hw - Struct containing variables accessed by shared code 3186 * @phy_info: PHY information structure
3106* phy_info - PHY information structure 3187 *
3107******************************************************************************/ 3188 * Get PHY information from various PHY registers for m88 PHY only.
3189 */
3108static s32 e1000_phy_m88_get_info(struct e1000_hw *hw, 3190static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
3109 struct e1000_phy_info *phy_info) 3191 struct e1000_phy_info *phy_info)
3110{ 3192{
3111 s32 ret_val; 3193 s32 ret_val;
3112 u16 phy_data; 3194 u16 phy_data;
3113 e1000_rev_polarity polarity; 3195 e1000_rev_polarity polarity;
3114 3196
3115 DEBUGFUNC("e1000_phy_m88_get_info"); 3197 DEBUGFUNC("e1000_phy_m88_get_info");
3116 3198
3117 /* The downshift status is checked only once, after link is established, 3199 /* The downshift status is checked only once, after link is established,
3118 * and it stored in the hw->speed_downgraded parameter. */ 3200 * and it stored in the hw->speed_downgraded parameter. */
3119 phy_info->downshift = (e1000_downshift)hw->speed_downgraded; 3201 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3120 3202
3121 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 3203 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3122 if (ret_val) 3204 if (ret_val)
3123 return ret_val; 3205 return ret_val;
3124 3206
3125 phy_info->extended_10bt_distance = 3207 phy_info->extended_10bt_distance =
3126 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> 3208 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
3127 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ? 3209 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
3128 e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal; 3210 e1000_10bt_ext_dist_enable_lower :
3129 3211 e1000_10bt_ext_dist_enable_normal;
3130 phy_info->polarity_correction = 3212
3131 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> 3213 phy_info->polarity_correction =
3132 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ? 3214 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
3133 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; 3215 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
3134 3216 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
3135 /* Check polarity status */ 3217
3136 ret_val = e1000_check_polarity(hw, &polarity); 3218 /* Check polarity status */
3137 if (ret_val) 3219 ret_val = e1000_check_polarity(hw, &polarity);
3138 return ret_val; 3220 if (ret_val)
3139 phy_info->cable_polarity = polarity; 3221 return ret_val;
3140 3222 phy_info->cable_polarity = polarity;
3141 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 3223
3142 if (ret_val) 3224 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
3143 return ret_val; 3225 if (ret_val)
3144 3226 return ret_val;
3145 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >> 3227
3146 M88E1000_PSSR_MDIX_SHIFT); 3228 phy_info->mdix_mode =
3147 3229 (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >>
3148 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 3230 M88E1000_PSSR_MDIX_SHIFT);
3149 /* Cable Length Estimation and Local/Remote Receiver Information 3231
3150 * are only valid at 1000 Mbps. 3232 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
3151 */ 3233 /* Cable Length Estimation and Local/Remote Receiver Information
3152 phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 3234 * are only valid at 1000 Mbps.
3153 M88E1000_PSSR_CABLE_LENGTH_SHIFT); 3235 */
3154 3236 phy_info->cable_length =
3155 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); 3237 (e1000_cable_length) ((phy_data &
3156 if (ret_val) 3238 M88E1000_PSSR_CABLE_LENGTH) >>
3157 return ret_val; 3239 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
3158 3240
3159 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> 3241 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3160 SR_1000T_LOCAL_RX_STATUS_SHIFT) ? 3242 if (ret_val)
3161 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3243 return ret_val;
3162 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> 3244
3163 SR_1000T_REMOTE_RX_STATUS_SHIFT) ? 3245 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3164 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; 3246 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3165 3247 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3166 } 3248 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3167 3249 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3168 return E1000_SUCCESS; 3250 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3251
3252 }
3253
3254 return E1000_SUCCESS;
3169} 3255}
3170 3256
3171/****************************************************************************** 3257/**
3172* Get PHY information from various PHY registers 3258 * e1000_phy_get_info - request phy info
3173* 3259 * @hw: Struct containing variables accessed by shared code
3174* hw - Struct containing variables accessed by shared code 3260 * @phy_info: PHY information structure
3175* phy_info - PHY information structure 3261 *
3176******************************************************************************/ 3262 * Get PHY information from various PHY registers
3263 */
3177s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info) 3264s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
3178{ 3265{
3179 s32 ret_val; 3266 s32 ret_val;
3180 u16 phy_data; 3267 u16 phy_data;
3181 3268
3182 DEBUGFUNC("e1000_phy_get_info"); 3269 DEBUGFUNC("e1000_phy_get_info");
3183 3270
3184 phy_info->cable_length = e1000_cable_length_undefined; 3271 phy_info->cable_length = e1000_cable_length_undefined;
3185 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined; 3272 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
3186 phy_info->cable_polarity = e1000_rev_polarity_undefined; 3273 phy_info->cable_polarity = e1000_rev_polarity_undefined;
3187 phy_info->downshift = e1000_downshift_undefined; 3274 phy_info->downshift = e1000_downshift_undefined;
3188 phy_info->polarity_correction = e1000_polarity_reversal_undefined; 3275 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
3189 phy_info->mdix_mode = e1000_auto_x_mode_undefined; 3276 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
3190 phy_info->local_rx = e1000_1000t_rx_status_undefined; 3277 phy_info->local_rx = e1000_1000t_rx_status_undefined;
3191 phy_info->remote_rx = e1000_1000t_rx_status_undefined; 3278 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
3192 3279
3193 if (hw->media_type != e1000_media_type_copper) { 3280 if (hw->media_type != e1000_media_type_copper) {
3194 DEBUGOUT("PHY info is only valid for copper media\n"); 3281 DEBUGOUT("PHY info is only valid for copper media\n");
3195 return -E1000_ERR_CONFIG; 3282 return -E1000_ERR_CONFIG;
3196 } 3283 }
3197 3284
3198 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3285 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3199 if (ret_val) 3286 if (ret_val)
3200 return ret_val; 3287 return ret_val;
3201 3288
3202 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); 3289 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3203 if (ret_val) 3290 if (ret_val)
3204 return ret_val; 3291 return ret_val;
3205 3292
3206 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { 3293 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
3207 DEBUGOUT("PHY info is only valid if link is up\n"); 3294 DEBUGOUT("PHY info is only valid if link is up\n");
3208 return -E1000_ERR_CONFIG; 3295 return -E1000_ERR_CONFIG;
3209 } 3296 }
3210 3297
3211 if (hw->phy_type == e1000_phy_igp) 3298 if (hw->phy_type == e1000_phy_igp)
3212 return e1000_phy_igp_get_info(hw, phy_info); 3299 return e1000_phy_igp_get_info(hw, phy_info);
3213 else 3300 else
3214 return e1000_phy_m88_get_info(hw, phy_info); 3301 return e1000_phy_m88_get_info(hw, phy_info);
3215} 3302}
3216 3303
3217s32 e1000_validate_mdi_setting(struct e1000_hw *hw) 3304s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
3218{ 3305{
3219 DEBUGFUNC("e1000_validate_mdi_settings"); 3306 DEBUGFUNC("e1000_validate_mdi_settings");
3220
3221 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
3222 DEBUGOUT("Invalid MDI setting detected\n");
3223 hw->mdix = 1;
3224 return -E1000_ERR_CONFIG;
3225 }
3226 return E1000_SUCCESS;
3227}
3228 3307
3308 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
3309 DEBUGOUT("Invalid MDI setting detected\n");
3310 hw->mdix = 1;
3311 return -E1000_ERR_CONFIG;
3312 }
3313 return E1000_SUCCESS;
3314}
3229 3315
3230/****************************************************************************** 3316/**
3317 * e1000_init_eeprom_params - initialize sw eeprom vars
3318 * @hw: Struct containing variables accessed by shared code
3319 *
3231 * Sets up eeprom variables in the hw struct. Must be called after mac_type 3320 * Sets up eeprom variables in the hw struct. Must be called after mac_type
3232 * is configured. 3321 * is configured.
3233 * 3322 */
3234 * hw - Struct containing variables accessed by shared code
3235 *****************************************************************************/
3236s32 e1000_init_eeprom_params(struct e1000_hw *hw) 3323s32 e1000_init_eeprom_params(struct e1000_hw *hw)
3237{ 3324{
3238 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3325 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3239 u32 eecd = er32(EECD); 3326 u32 eecd = er32(EECD);
3240 s32 ret_val = E1000_SUCCESS; 3327 s32 ret_val = E1000_SUCCESS;
3241 u16 eeprom_size; 3328 u16 eeprom_size;
3242 3329
3243 DEBUGFUNC("e1000_init_eeprom_params"); 3330 DEBUGFUNC("e1000_init_eeprom_params");
3244 3331
3245 switch (hw->mac_type) { 3332 switch (hw->mac_type) {
3246 case e1000_82542_rev2_0: 3333 case e1000_82542_rev2_0:
3247 case e1000_82542_rev2_1: 3334 case e1000_82542_rev2_1:
3248 case e1000_82543: 3335 case e1000_82543:
3249 case e1000_82544: 3336 case e1000_82544:
3250 eeprom->type = e1000_eeprom_microwire; 3337 eeprom->type = e1000_eeprom_microwire;
3251 eeprom->word_size = 64; 3338 eeprom->word_size = 64;
3252 eeprom->opcode_bits = 3; 3339 eeprom->opcode_bits = 3;
3253 eeprom->address_bits = 6; 3340 eeprom->address_bits = 6;
3254 eeprom->delay_usec = 50; 3341 eeprom->delay_usec = 50;
3255 eeprom->use_eerd = false; 3342 eeprom->use_eerd = false;
3256 eeprom->use_eewr = false; 3343 eeprom->use_eewr = false;
3257 break; 3344 break;
3258 case e1000_82540: 3345 case e1000_82540:
3259 case e1000_82545: 3346 case e1000_82545:
3260 case e1000_82545_rev_3: 3347 case e1000_82545_rev_3:
3261 case e1000_82546: 3348 case e1000_82546:
3262 case e1000_82546_rev_3: 3349 case e1000_82546_rev_3:
3263 eeprom->type = e1000_eeprom_microwire; 3350 eeprom->type = e1000_eeprom_microwire;
3264 eeprom->opcode_bits = 3; 3351 eeprom->opcode_bits = 3;
3265 eeprom->delay_usec = 50; 3352 eeprom->delay_usec = 50;
3266 if (eecd & E1000_EECD_SIZE) { 3353 if (eecd & E1000_EECD_SIZE) {
3267 eeprom->word_size = 256; 3354 eeprom->word_size = 256;
3268 eeprom->address_bits = 8; 3355 eeprom->address_bits = 8;
3269 } else { 3356 } else {
3270 eeprom->word_size = 64; 3357 eeprom->word_size = 64;
3271 eeprom->address_bits = 6; 3358 eeprom->address_bits = 6;
3272 } 3359 }
3273 eeprom->use_eerd = false; 3360 eeprom->use_eerd = false;
3274 eeprom->use_eewr = false; 3361 eeprom->use_eewr = false;
3275 break; 3362 break;
3276 case e1000_82541: 3363 case e1000_82541:
3277 case e1000_82541_rev_2: 3364 case e1000_82541_rev_2:
3278 case e1000_82547: 3365 case e1000_82547:
3279 case e1000_82547_rev_2: 3366 case e1000_82547_rev_2:
3280 if (eecd & E1000_EECD_TYPE) { 3367 if (eecd & E1000_EECD_TYPE) {
3281 eeprom->type = e1000_eeprom_spi; 3368 eeprom->type = e1000_eeprom_spi;
3282 eeprom->opcode_bits = 8; 3369 eeprom->opcode_bits = 8;
3283 eeprom->delay_usec = 1; 3370 eeprom->delay_usec = 1;
3284 if (eecd & E1000_EECD_ADDR_BITS) { 3371 if (eecd & E1000_EECD_ADDR_BITS) {
3285 eeprom->page_size = 32; 3372 eeprom->page_size = 32;
3286 eeprom->address_bits = 16; 3373 eeprom->address_bits = 16;
3287 } else { 3374 } else {
3288 eeprom->page_size = 8; 3375 eeprom->page_size = 8;
3289 eeprom->address_bits = 8; 3376 eeprom->address_bits = 8;
3290 } 3377 }
3291 } else { 3378 } else {
3292 eeprom->type = e1000_eeprom_microwire; 3379 eeprom->type = e1000_eeprom_microwire;
3293 eeprom->opcode_bits = 3; 3380 eeprom->opcode_bits = 3;
3294 eeprom->delay_usec = 50; 3381 eeprom->delay_usec = 50;
3295 if (eecd & E1000_EECD_ADDR_BITS) { 3382 if (eecd & E1000_EECD_ADDR_BITS) {
3296 eeprom->word_size = 256; 3383 eeprom->word_size = 256;
3297 eeprom->address_bits = 8; 3384 eeprom->address_bits = 8;
3298 } else { 3385 } else {
3299 eeprom->word_size = 64; 3386 eeprom->word_size = 64;
3300 eeprom->address_bits = 6; 3387 eeprom->address_bits = 6;
3301 } 3388 }
3302 } 3389 }
3303 eeprom->use_eerd = false; 3390 eeprom->use_eerd = false;
3304 eeprom->use_eewr = false; 3391 eeprom->use_eewr = false;
3305 break; 3392 break;
3306 default: 3393 default:
3307 break; 3394 break;
3308 } 3395 }
3309 3396
3310 if (eeprom->type == e1000_eeprom_spi) { 3397 if (eeprom->type == e1000_eeprom_spi) {
3311 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to 3398 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
3312 * 32KB (incremented by powers of 2). 3399 * 32KB (incremented by powers of 2).
3313 */ 3400 */
3314 /* Set to default value for initial eeprom read. */ 3401 /* Set to default value for initial eeprom read. */
3315 eeprom->word_size = 64; 3402 eeprom->word_size = 64;
3316 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); 3403 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
3317 if (ret_val) 3404 if (ret_val)
3318 return ret_val; 3405 return ret_val;
3319 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; 3406 eeprom_size =
3320 /* 256B eeprom size was not supported in earlier hardware, so we 3407 (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
3321 * bump eeprom_size up one to ensure that "1" (which maps to 256B) 3408 /* 256B eeprom size was not supported in earlier hardware, so we
3322 * is never the result used in the shifting logic below. */ 3409 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
3323 if (eeprom_size) 3410 * is never the result used in the shifting logic below. */
3324 eeprom_size++; 3411 if (eeprom_size)
3325 3412 eeprom_size++;
3326 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 3413
3327 } 3414 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
3328 return ret_val; 3415 }
3416 return ret_val;
3329} 3417}
3330 3418
3331/****************************************************************************** 3419/**
3332 * Raises the EEPROM's clock input. 3420 * e1000_raise_ee_clk - Raises the EEPROM's clock input.
3333 * 3421 * @hw: Struct containing variables accessed by shared code
3334 * hw - Struct containing variables accessed by shared code 3422 * @eecd: EECD's current value
3335 * eecd - EECD's current value 3423 */
3336 *****************************************************************************/
3337static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd) 3424static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd)
3338{ 3425{
3339 /* Raise the clock input to the EEPROM (by setting the SK bit), and then 3426 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
3340 * wait <delay> microseconds. 3427 * wait <delay> microseconds.
3341 */ 3428 */
3342 *eecd = *eecd | E1000_EECD_SK; 3429 *eecd = *eecd | E1000_EECD_SK;
3343 ew32(EECD, *eecd); 3430 ew32(EECD, *eecd);
3344 E1000_WRITE_FLUSH(); 3431 E1000_WRITE_FLUSH();
3345 udelay(hw->eeprom.delay_usec); 3432 udelay(hw->eeprom.delay_usec);
3346} 3433}
3347 3434
3348/****************************************************************************** 3435/**
3349 * Lowers the EEPROM's clock input. 3436 * e1000_lower_ee_clk - Lowers the EEPROM's clock input.
3350 * 3437 * @hw: Struct containing variables accessed by shared code
3351 * hw - Struct containing variables accessed by shared code 3438 * @eecd: EECD's current value
3352 * eecd - EECD's current value 3439 */
3353 *****************************************************************************/
3354static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd) 3440static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd)
3355{ 3441{
3356 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 3442 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
3357 * wait 50 microseconds. 3443 * wait 50 microseconds.
3358 */ 3444 */
3359 *eecd = *eecd & ~E1000_EECD_SK; 3445 *eecd = *eecd & ~E1000_EECD_SK;
3360 ew32(EECD, *eecd); 3446 ew32(EECD, *eecd);
3361 E1000_WRITE_FLUSH(); 3447 E1000_WRITE_FLUSH();
3362 udelay(hw->eeprom.delay_usec); 3448 udelay(hw->eeprom.delay_usec);
3363} 3449}
3364 3450
3365/****************************************************************************** 3451/**
3366 * Shift data bits out to the EEPROM. 3452 * e1000_shift_out_ee_bits - Shift data bits out to the EEPROM.
3367 * 3453 * @hw: Struct containing variables accessed by shared code
3368 * hw - Struct containing variables accessed by shared code 3454 * @data: data to send to the EEPROM
3369 * data - data to send to the EEPROM 3455 * @count: number of bits to shift out
3370 * count - number of bits to shift out 3456 */
3371 *****************************************************************************/
3372static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count) 3457static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
3373{ 3458{
3374 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3459 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3375 u32 eecd; 3460 u32 eecd;
3376 u32 mask; 3461 u32 mask;
3377 3462
3378 /* We need to shift "count" bits out to the EEPROM. So, value in the 3463 /* We need to shift "count" bits out to the EEPROM. So, value in the
3379 * "data" parameter will be shifted out to the EEPROM one bit at a time. 3464 * "data" parameter will be shifted out to the EEPROM one bit at a time.
3380 * In order to do this, "data" must be broken down into bits. 3465 * In order to do this, "data" must be broken down into bits.
3381 */ 3466 */
3382 mask = 0x01 << (count - 1); 3467 mask = 0x01 << (count - 1);
3383 eecd = er32(EECD); 3468 eecd = er32(EECD);
3384 if (eeprom->type == e1000_eeprom_microwire) { 3469 if (eeprom->type == e1000_eeprom_microwire) {
3385 eecd &= ~E1000_EECD_DO; 3470 eecd &= ~E1000_EECD_DO;
3386 } else if (eeprom->type == e1000_eeprom_spi) { 3471 } else if (eeprom->type == e1000_eeprom_spi) {
3387 eecd |= E1000_EECD_DO; 3472 eecd |= E1000_EECD_DO;
3388 } 3473 }
3389 do { 3474 do {
3390 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", 3475 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
3391 * and then raising and then lowering the clock (the SK bit controls 3476 * and then raising and then lowering the clock (the SK bit controls
3392 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM 3477 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
3393 * by setting "DI" to "0" and then raising and then lowering the clock. 3478 * by setting "DI" to "0" and then raising and then lowering the clock.
3394 */ 3479 */
3395 eecd &= ~E1000_EECD_DI; 3480 eecd &= ~E1000_EECD_DI;
3396 3481
3397 if (data & mask) 3482 if (data & mask)
3398 eecd |= E1000_EECD_DI; 3483 eecd |= E1000_EECD_DI;
3399 3484
3400 ew32(EECD, eecd); 3485 ew32(EECD, eecd);
3401 E1000_WRITE_FLUSH(); 3486 E1000_WRITE_FLUSH();
3402 3487
3403 udelay(eeprom->delay_usec); 3488 udelay(eeprom->delay_usec);
3404 3489
3405 e1000_raise_ee_clk(hw, &eecd); 3490 e1000_raise_ee_clk(hw, &eecd);
3406 e1000_lower_ee_clk(hw, &eecd); 3491 e1000_lower_ee_clk(hw, &eecd);
3407 3492
3408 mask = mask >> 1; 3493 mask = mask >> 1;
3409 3494
3410 } while (mask); 3495 } while (mask);
3411 3496
3412 /* We leave the "DI" bit set to "0" when we leave this routine. */ 3497 /* We leave the "DI" bit set to "0" when we leave this routine. */
3413 eecd &= ~E1000_EECD_DI; 3498 eecd &= ~E1000_EECD_DI;
3414 ew32(EECD, eecd); 3499 ew32(EECD, eecd);
3415} 3500}
3416 3501
3417/****************************************************************************** 3502/**
3418 * Shift data bits in from the EEPROM 3503 * e1000_shift_in_ee_bits - Shift data bits in from the EEPROM
3419 * 3504 * @hw: Struct containing variables accessed by shared code
3420 * hw - Struct containing variables accessed by shared code 3505 * @count: number of bits to shift in
3421 *****************************************************************************/ 3506 */
3422static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count) 3507static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count)
3423{ 3508{
3424 u32 eecd; 3509 u32 eecd;
3425 u32 i; 3510 u32 i;
3426 u16 data; 3511 u16 data;
3427 3512
3428 /* In order to read a register from the EEPROM, we need to shift 'count' 3513 /* In order to read a register from the EEPROM, we need to shift 'count'
3429 * bits in from the EEPROM. Bits are "shifted in" by raising the clock 3514 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
3430 * input to the EEPROM (setting the SK bit), and then reading the value of 3515 * input to the EEPROM (setting the SK bit), and then reading the value of
3431 * the "DO" bit. During this "shifting in" process the "DI" bit should 3516 * the "DO" bit. During this "shifting in" process the "DI" bit should
3432 * always be clear. 3517 * always be clear.
3433 */ 3518 */
3434 3519
3435 eecd = er32(EECD); 3520 eecd = er32(EECD);
3436 3521
3437 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 3522 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
3438 data = 0; 3523 data = 0;
3439 3524
3440 for (i = 0; i < count; i++) { 3525 for (i = 0; i < count; i++) {
3441 data = data << 1; 3526 data = data << 1;
3442 e1000_raise_ee_clk(hw, &eecd); 3527 e1000_raise_ee_clk(hw, &eecd);
3443 3528
3444 eecd = er32(EECD); 3529 eecd = er32(EECD);
3445 3530
3446 eecd &= ~(E1000_EECD_DI); 3531 eecd &= ~(E1000_EECD_DI);
3447 if (eecd & E1000_EECD_DO) 3532 if (eecd & E1000_EECD_DO)
3448 data |= 1; 3533 data |= 1;
3449 3534
3450 e1000_lower_ee_clk(hw, &eecd); 3535 e1000_lower_ee_clk(hw, &eecd);
3451 } 3536 }
3452 3537
3453 return data; 3538 return data;
3454} 3539}
3455 3540
3456/****************************************************************************** 3541/**
3457 * Prepares EEPROM for access 3542 * e1000_acquire_eeprom - Prepares EEPROM for access
3458 * 3543 * @hw: Struct containing variables accessed by shared code
3459 * hw - Struct containing variables accessed by shared code
3460 * 3544 *
3461 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 3545 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3462 * function should be called before issuing a command to the EEPROM. 3546 * function should be called before issuing a command to the EEPROM.
3463 *****************************************************************************/ 3547 */
3464static s32 e1000_acquire_eeprom(struct e1000_hw *hw) 3548static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
3465{ 3549{
3466 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3550 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3467 u32 eecd, i=0; 3551 u32 eecd, i = 0;
3468 3552
3469 DEBUGFUNC("e1000_acquire_eeprom"); 3553 DEBUGFUNC("e1000_acquire_eeprom");
3470 3554
3471 eecd = er32(EECD); 3555 eecd = er32(EECD);
3472 3556
3473 /* Request EEPROM Access */ 3557 /* Request EEPROM Access */
3474 if (hw->mac_type > e1000_82544) { 3558 if (hw->mac_type > e1000_82544) {
3475 eecd |= E1000_EECD_REQ; 3559 eecd |= E1000_EECD_REQ;
3476 ew32(EECD, eecd); 3560 ew32(EECD, eecd);
3477 eecd = er32(EECD); 3561 eecd = er32(EECD);
3478 while ((!(eecd & E1000_EECD_GNT)) && 3562 while ((!(eecd & E1000_EECD_GNT)) &&
3479 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 3563 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3480 i++; 3564 i++;
3481 udelay(5); 3565 udelay(5);
3482 eecd = er32(EECD); 3566 eecd = er32(EECD);
3483 } 3567 }
3484 if (!(eecd & E1000_EECD_GNT)) { 3568 if (!(eecd & E1000_EECD_GNT)) {
3485 eecd &= ~E1000_EECD_REQ; 3569 eecd &= ~E1000_EECD_REQ;
3486 ew32(EECD, eecd); 3570 ew32(EECD, eecd);
3487 DEBUGOUT("Could not acquire EEPROM grant\n"); 3571 DEBUGOUT("Could not acquire EEPROM grant\n");
3488 return -E1000_ERR_EEPROM; 3572 return -E1000_ERR_EEPROM;
3489 } 3573 }
3490 } 3574 }
3491 3575
3492 /* Setup EEPROM for Read/Write */ 3576 /* Setup EEPROM for Read/Write */
3493 3577
3494 if (eeprom->type == e1000_eeprom_microwire) { 3578 if (eeprom->type == e1000_eeprom_microwire) {
3495 /* Clear SK and DI */ 3579 /* Clear SK and DI */
3496 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 3580 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
3497 ew32(EECD, eecd); 3581 ew32(EECD, eecd);
3498 3582
3499 /* Set CS */ 3583 /* Set CS */
3500 eecd |= E1000_EECD_CS; 3584 eecd |= E1000_EECD_CS;
3501 ew32(EECD, eecd); 3585 ew32(EECD, eecd);
3502 } else if (eeprom->type == e1000_eeprom_spi) { 3586 } else if (eeprom->type == e1000_eeprom_spi) {
3503 /* Clear SK and CS */ 3587 /* Clear SK and CS */
3504 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 3588 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3505 ew32(EECD, eecd); 3589 ew32(EECD, eecd);
3506 udelay(1); 3590 udelay(1);
3507 } 3591 }
3508 3592
3509 return E1000_SUCCESS; 3593 return E1000_SUCCESS;
3510} 3594}
3511 3595
3512/****************************************************************************** 3596/**
3513 * Returns EEPROM to a "standby" state 3597 * e1000_standby_eeprom - Returns EEPROM to a "standby" state
3514 * 3598 * @hw: Struct containing variables accessed by shared code
3515 * hw - Struct containing variables accessed by shared code 3599 */
3516 *****************************************************************************/
3517static void e1000_standby_eeprom(struct e1000_hw *hw) 3600static void e1000_standby_eeprom(struct e1000_hw *hw)
3518{ 3601{
3519 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3602 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3520 u32 eecd; 3603 u32 eecd;
3521 3604
3522 eecd = er32(EECD); 3605 eecd = er32(EECD);
3523 3606
3524 if (eeprom->type == e1000_eeprom_microwire) { 3607 if (eeprom->type == e1000_eeprom_microwire) {
3525 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 3608 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3526 ew32(EECD, eecd); 3609 ew32(EECD, eecd);
3527 E1000_WRITE_FLUSH(); 3610 E1000_WRITE_FLUSH();
3528 udelay(eeprom->delay_usec); 3611 udelay(eeprom->delay_usec);
3529 3612
3530 /* Clock high */ 3613 /* Clock high */
3531 eecd |= E1000_EECD_SK; 3614 eecd |= E1000_EECD_SK;
3532 ew32(EECD, eecd); 3615 ew32(EECD, eecd);
3533 E1000_WRITE_FLUSH(); 3616 E1000_WRITE_FLUSH();
3534 udelay(eeprom->delay_usec); 3617 udelay(eeprom->delay_usec);
3535 3618
3536 /* Select EEPROM */ 3619 /* Select EEPROM */
3537 eecd |= E1000_EECD_CS; 3620 eecd |= E1000_EECD_CS;
3538 ew32(EECD, eecd); 3621 ew32(EECD, eecd);
3539 E1000_WRITE_FLUSH(); 3622 E1000_WRITE_FLUSH();
3540 udelay(eeprom->delay_usec); 3623 udelay(eeprom->delay_usec);
3541 3624
3542 /* Clock low */ 3625 /* Clock low */
3543 eecd &= ~E1000_EECD_SK; 3626 eecd &= ~E1000_EECD_SK;
3544 ew32(EECD, eecd); 3627 ew32(EECD, eecd);
3545 E1000_WRITE_FLUSH(); 3628 E1000_WRITE_FLUSH();
3546 udelay(eeprom->delay_usec); 3629 udelay(eeprom->delay_usec);
3547 } else if (eeprom->type == e1000_eeprom_spi) { 3630 } else if (eeprom->type == e1000_eeprom_spi) {
3548 /* Toggle CS to flush commands */ 3631 /* Toggle CS to flush commands */
3549 eecd |= E1000_EECD_CS; 3632 eecd |= E1000_EECD_CS;
3550 ew32(EECD, eecd); 3633 ew32(EECD, eecd);
3551 E1000_WRITE_FLUSH(); 3634 E1000_WRITE_FLUSH();
3552 udelay(eeprom->delay_usec); 3635 udelay(eeprom->delay_usec);
3553 eecd &= ~E1000_EECD_CS; 3636 eecd &= ~E1000_EECD_CS;
3554 ew32(EECD, eecd); 3637 ew32(EECD, eecd);
3555 E1000_WRITE_FLUSH(); 3638 E1000_WRITE_FLUSH();
3556 udelay(eeprom->delay_usec); 3639 udelay(eeprom->delay_usec);
3557 } 3640 }
3558} 3641}
3559 3642
3560/****************************************************************************** 3643/**
3561 * Terminates a command by inverting the EEPROM's chip select pin 3644 * e1000_release_eeprom - drop chip select
3645 * @hw: Struct containing variables accessed by shared code
3562 * 3646 *
3563 * hw - Struct containing variables accessed by shared code 3647 * Terminates a command by inverting the EEPROM's chip select pin
3564 *****************************************************************************/ 3648 */
3565static void e1000_release_eeprom(struct e1000_hw *hw) 3649static void e1000_release_eeprom(struct e1000_hw *hw)
3566{ 3650{
3567 u32 eecd; 3651 u32 eecd;
3568 3652
3569 DEBUGFUNC("e1000_release_eeprom"); 3653 DEBUGFUNC("e1000_release_eeprom");
3570 3654
3571 eecd = er32(EECD); 3655 eecd = er32(EECD);
3572 3656
3573 if (hw->eeprom.type == e1000_eeprom_spi) { 3657 if (hw->eeprom.type == e1000_eeprom_spi) {
3574 eecd |= E1000_EECD_CS; /* Pull CS high */ 3658 eecd |= E1000_EECD_CS; /* Pull CS high */
3575 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 3659 eecd &= ~E1000_EECD_SK; /* Lower SCK */
3576 3660
3577 ew32(EECD, eecd); 3661 ew32(EECD, eecd);
3578 3662
3579 udelay(hw->eeprom.delay_usec); 3663 udelay(hw->eeprom.delay_usec);
3580 } else if (hw->eeprom.type == e1000_eeprom_microwire) { 3664 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
3581 /* cleanup eeprom */ 3665 /* cleanup eeprom */
3582 3666
3583 /* CS on Microwire is active-high */ 3667 /* CS on Microwire is active-high */
3584 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 3668 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
3585 3669
3586 ew32(EECD, eecd); 3670 ew32(EECD, eecd);
3587 3671
3588 /* Rising edge of clock */ 3672 /* Rising edge of clock */
3589 eecd |= E1000_EECD_SK; 3673 eecd |= E1000_EECD_SK;
3590 ew32(EECD, eecd); 3674 ew32(EECD, eecd);
3591 E1000_WRITE_FLUSH(); 3675 E1000_WRITE_FLUSH();
3592 udelay(hw->eeprom.delay_usec); 3676 udelay(hw->eeprom.delay_usec);
3593 3677
3594 /* Falling edge of clock */ 3678 /* Falling edge of clock */
3595 eecd &= ~E1000_EECD_SK; 3679 eecd &= ~E1000_EECD_SK;
3596 ew32(EECD, eecd); 3680 ew32(EECD, eecd);
3597 E1000_WRITE_FLUSH(); 3681 E1000_WRITE_FLUSH();
3598 udelay(hw->eeprom.delay_usec); 3682 udelay(hw->eeprom.delay_usec);
3599 } 3683 }
3600 3684
3601 /* Stop requesting EEPROM access */ 3685 /* Stop requesting EEPROM access */
3602 if (hw->mac_type > e1000_82544) { 3686 if (hw->mac_type > e1000_82544) {
3603 eecd &= ~E1000_EECD_REQ; 3687 eecd &= ~E1000_EECD_REQ;
3604 ew32(EECD, eecd); 3688 ew32(EECD, eecd);
3605 } 3689 }
3606} 3690}
3607 3691
3608/****************************************************************************** 3692/**
3609 * Reads a 16 bit word from the EEPROM. 3693 * e1000_spi_eeprom_ready - Reads a 16 bit word from the EEPROM.
3610 * 3694 * @hw: Struct containing variables accessed by shared code
3611 * hw - Struct containing variables accessed by shared code 3695 */
3612 *****************************************************************************/
3613static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw) 3696static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
3614{ 3697{
3615 u16 retry_count = 0; 3698 u16 retry_count = 0;
3616 u8 spi_stat_reg; 3699 u8 spi_stat_reg;
3617 3700
3618 DEBUGFUNC("e1000_spi_eeprom_ready"); 3701 DEBUGFUNC("e1000_spi_eeprom_ready");
3619 3702
3620 /* Read "Status Register" repeatedly until the LSB is cleared. The 3703 /* Read "Status Register" repeatedly until the LSB is cleared. The
3621 * EEPROM will signal that the command has been completed by clearing 3704 * EEPROM will signal that the command has been completed by clearing
3622 * bit 0 of the internal status register. If it's not cleared within 3705 * bit 0 of the internal status register. If it's not cleared within
3623 * 5 milliseconds, then error out. 3706 * 5 milliseconds, then error out.
3624 */ 3707 */
3625 retry_count = 0; 3708 retry_count = 0;
3626 do { 3709 do {
3627 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 3710 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3628 hw->eeprom.opcode_bits); 3711 hw->eeprom.opcode_bits);
3629 spi_stat_reg = (u8)e1000_shift_in_ee_bits(hw, 8); 3712 spi_stat_reg = (u8) e1000_shift_in_ee_bits(hw, 8);
3630 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 3713 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3631 break; 3714 break;
3632 3715
3633 udelay(5); 3716 udelay(5);
3634 retry_count += 5; 3717 retry_count += 5;
3635 3718
3636 e1000_standby_eeprom(hw); 3719 e1000_standby_eeprom(hw);
3637 } while (retry_count < EEPROM_MAX_RETRY_SPI); 3720 } while (retry_count < EEPROM_MAX_RETRY_SPI);
3638 3721
3639 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 3722 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3640 * only 0-5mSec on 5V devices) 3723 * only 0-5mSec on 5V devices)
3641 */ 3724 */
3642 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 3725 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
3643 DEBUGOUT("SPI EEPROM Status error\n"); 3726 DEBUGOUT("SPI EEPROM Status error\n");
3644 return -E1000_ERR_EEPROM; 3727 return -E1000_ERR_EEPROM;
3645 } 3728 }
3646 3729
3647 return E1000_SUCCESS; 3730 return E1000_SUCCESS;
3648} 3731}
3649 3732
3650/****************************************************************************** 3733/**
3651 * Reads a 16 bit word from the EEPROM. 3734 * e1000_read_eeprom - Reads a 16 bit word from the EEPROM.
3652 * 3735 * @hw: Struct containing variables accessed by shared code
3653 * hw - Struct containing variables accessed by shared code 3736 * @offset: offset of word in the EEPROM to read
3654 * offset - offset of word in the EEPROM to read 3737 * @data: word read from the EEPROM
3655 * data - word read from the EEPROM 3738 * @words: number of words to read
3656 * words - number of words to read 3739 */
3657 *****************************************************************************/
3658s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 3740s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
3659{ 3741{
3660 s32 ret; 3742 s32 ret;
3661 spin_lock(&e1000_eeprom_lock); 3743 spin_lock(&e1000_eeprom_lock);
3662 ret = e1000_do_read_eeprom(hw, offset, words, data); 3744 ret = e1000_do_read_eeprom(hw, offset, words, data);
3663 spin_unlock(&e1000_eeprom_lock); 3745 spin_unlock(&e1000_eeprom_lock);
3664 return ret; 3746 return ret;
3665} 3747}
3666 3748
3667static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 3749static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
3750 u16 *data)
3668{ 3751{
3669 struct e1000_eeprom_info *eeprom = &hw->eeprom; 3752 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3670 u32 i = 0; 3753 u32 i = 0;
3671 3754
3672 DEBUGFUNC("e1000_read_eeprom"); 3755 DEBUGFUNC("e1000_read_eeprom");
3673 3756
3674 /* If eeprom is not yet detected, do so now */ 3757 /* If eeprom is not yet detected, do so now */
3675 if (eeprom->word_size == 0) 3758 if (eeprom->word_size == 0)
3676 e1000_init_eeprom_params(hw); 3759 e1000_init_eeprom_params(hw);
3677 3760
3678 /* A check for invalid values: offset too large, too many words, and not 3761 /* A check for invalid values: offset too large, too many words, and not
3679 * enough words. 3762 * enough words.
3680 */ 3763 */
3681 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || 3764 if ((offset >= eeprom->word_size)
3682 (words == 0)) { 3765 || (words > eeprom->word_size - offset) || (words == 0)) {
3683 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size); 3766 DEBUGOUT2
3684 return -E1000_ERR_EEPROM; 3767 ("\"words\" parameter out of bounds. Words = %d, size = %d\n",
3685 } 3768 offset, eeprom->word_size);
3686 3769 return -E1000_ERR_EEPROM;
3687 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI 3770 }
3688 * directly. In this case, we need to acquire the EEPROM so that 3771
3689 * FW or other port software does not interrupt. 3772 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
3690 */ 3773 * directly. In this case, we need to acquire the EEPROM so that
3691 if (!hw->eeprom.use_eerd) { 3774 * FW or other port software does not interrupt.
3692 /* Prepare the EEPROM for bit-bang reading */ 3775 */
3693 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 3776 if (!hw->eeprom.use_eerd) {
3694 return -E1000_ERR_EEPROM; 3777 /* Prepare the EEPROM for bit-bang reading */
3695 } 3778 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3696 3779 return -E1000_ERR_EEPROM;
3697 /* Eerd register EEPROM access requires no eeprom aquire/release */ 3780 }
3698 if (eeprom->use_eerd) 3781
3699 return e1000_read_eeprom_eerd(hw, offset, words, data); 3782 /* Eerd register EEPROM access requires no eeprom aquire/release */
3700 3783 if (eeprom->use_eerd)
3701 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have 3784 return e1000_read_eeprom_eerd(hw, offset, words, data);
3702 * acquired the EEPROM at this point, so any returns should relase it */ 3785
3703 if (eeprom->type == e1000_eeprom_spi) { 3786 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
3704 u16 word_in; 3787 * acquired the EEPROM at this point, so any returns should release it */
3705 u8 read_opcode = EEPROM_READ_OPCODE_SPI; 3788 if (eeprom->type == e1000_eeprom_spi) {
3706 3789 u16 word_in;
3707 if (e1000_spi_eeprom_ready(hw)) { 3790 u8 read_opcode = EEPROM_READ_OPCODE_SPI;
3708 e1000_release_eeprom(hw); 3791
3709 return -E1000_ERR_EEPROM; 3792 if (e1000_spi_eeprom_ready(hw)) {
3710 } 3793 e1000_release_eeprom(hw);
3711 3794 return -E1000_ERR_EEPROM;
3712 e1000_standby_eeprom(hw); 3795 }
3713 3796
3714 /* Some SPI eeproms use the 8th address bit embedded in the opcode */ 3797 e1000_standby_eeprom(hw);
3715 if ((eeprom->address_bits == 8) && (offset >= 128)) 3798
3716 read_opcode |= EEPROM_A8_OPCODE_SPI; 3799 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3717 3800 if ((eeprom->address_bits == 8) && (offset >= 128))
3718 /* Send the READ command (opcode + addr) */ 3801 read_opcode |= EEPROM_A8_OPCODE_SPI;
3719 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 3802
3720 e1000_shift_out_ee_bits(hw, (u16)(offset*2), eeprom->address_bits); 3803 /* Send the READ command (opcode + addr) */
3721 3804 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3722 /* Read the data. The address of the eeprom internally increments with 3805 e1000_shift_out_ee_bits(hw, (u16) (offset * 2),
3723 * each byte (spi) being read, saving on the overhead of eeprom setup 3806 eeprom->address_bits);
3724 * and tear-down. The address counter will roll over if reading beyond 3807
3725 * the size of the eeprom, thus allowing the entire memory to be read 3808 /* Read the data. The address of the eeprom internally increments with
3726 * starting from any offset. */ 3809 * each byte (spi) being read, saving on the overhead of eeprom setup
3727 for (i = 0; i < words; i++) { 3810 * and tear-down. The address counter will roll over if reading beyond
3728 word_in = e1000_shift_in_ee_bits(hw, 16); 3811 * the size of the eeprom, thus allowing the entire memory to be read
3729 data[i] = (word_in >> 8) | (word_in << 8); 3812 * starting from any offset. */
3730 } 3813 for (i = 0; i < words; i++) {
3731 } else if (eeprom->type == e1000_eeprom_microwire) { 3814 word_in = e1000_shift_in_ee_bits(hw, 16);
3732 for (i = 0; i < words; i++) { 3815 data[i] = (word_in >> 8) | (word_in << 8);
3733 /* Send the READ command (opcode + addr) */ 3816 }
3734 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, 3817 } else if (eeprom->type == e1000_eeprom_microwire) {
3735 eeprom->opcode_bits); 3818 for (i = 0; i < words; i++) {
3736 e1000_shift_out_ee_bits(hw, (u16)(offset + i), 3819 /* Send the READ command (opcode + addr) */
3737 eeprom->address_bits); 3820 e1000_shift_out_ee_bits(hw,
3738 3821 EEPROM_READ_OPCODE_MICROWIRE,
3739 /* Read the data. For microwire, each word requires the overhead 3822 eeprom->opcode_bits);
3740 * of eeprom setup and tear-down. */ 3823 e1000_shift_out_ee_bits(hw, (u16) (offset + i),
3741 data[i] = e1000_shift_in_ee_bits(hw, 16); 3824 eeprom->address_bits);
3742 e1000_standby_eeprom(hw); 3825
3743 } 3826 /* Read the data. For microwire, each word requires the overhead
3744 } 3827 * of eeprom setup and tear-down. */
3745 3828 data[i] = e1000_shift_in_ee_bits(hw, 16);
3746 /* End this read operation */ 3829 e1000_standby_eeprom(hw);
3747 e1000_release_eeprom(hw); 3830 }
3748 3831 }
3749 return E1000_SUCCESS; 3832
3833 /* End this read operation */
3834 e1000_release_eeprom(hw);
3835
3836 return E1000_SUCCESS;
3750} 3837}
3751 3838
3752/****************************************************************************** 3839/**
3753 * Reads a 16 bit word from the EEPROM using the EERD register. 3840 * Reads a 16 bit word from the EEPROM using the EERD register.
3754 * 3841 *
3755 * hw - Struct containing variables accessed by shared code 3842 * @hw: Struct containing variables accessed by shared code
3756 * offset - offset of word in the EEPROM to read 3843 * offset - offset of word in the EEPROM to read
3757 * data - word read from the EEPROM 3844 * data - word read from the EEPROM
3758 * words - number of words to read 3845 * words - number of words to read
3759 *****************************************************************************/ 3846 */
3760static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words, 3847static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words,
3761 u16 *data) 3848 u16 *data)
3762{ 3849{
3763 u32 i, eerd = 0; 3850 u32 i, eerd = 0;
3764 s32 error = 0; 3851 s32 error = 0;
3765 3852
3766 for (i = 0; i < words; i++) { 3853 for (i = 0; i < words; i++) {
3767 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + 3854 eerd = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) +
3768 E1000_EEPROM_RW_REG_START; 3855 E1000_EEPROM_RW_REG_START;
3769 3856
3770 ew32(EERD, eerd); 3857 ew32(EERD, eerd);
3771 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 3858 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
3772 3859
3773 if (error) { 3860 if (error) {
3774 break; 3861 break;
3775 } 3862 }
3776 data[i] = (er32(EERD) >> E1000_EEPROM_RW_REG_DATA); 3863 data[i] = (er32(EERD) >> E1000_EEPROM_RW_REG_DATA);
3777 3864
3778 } 3865 }
3779 3866
3780 return error; 3867 return error;
3781} 3868}
3782 3869
3783/****************************************************************************** 3870/**
3784 * Writes a 16 bit word from the EEPROM using the EEWR register. 3871 * Writes a 16 bit word from the EEPROM using the EEWR register.
3785 * 3872 *
3786 * hw - Struct containing variables accessed by shared code 3873 * @hw: Struct containing variables accessed by shared code
3787 * offset - offset of word in the EEPROM to read 3874 * offset - offset of word in the EEPROM to read
3788 * data - word read from the EEPROM 3875 * data - word read from the EEPROM
3789 * words - number of words to read 3876 * words - number of words to read
3790 *****************************************************************************/ 3877 */
3791static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words, 3878static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words,
3792 u16 *data) 3879 u16 *data)
3793{ 3880{
3794 u32 register_value = 0; 3881 u32 register_value = 0;
3795 u32 i = 0; 3882 u32 i = 0;
3796 s32 error = 0; 3883 s32 error = 0;
3797 3884
3885 for (i = 0; i < words; i++) {
3886 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
3887 ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) |
3888 E1000_EEPROM_RW_REG_START;
3798 3889
3799 for (i = 0; i < words; i++) { 3890 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
3800 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | 3891 if (error) {
3801 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) | 3892 break;
3802 E1000_EEPROM_RW_REG_START; 3893 }
3803
3804 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
3805 if (error) {
3806 break;
3807 }
3808 3894
3809 ew32(EEWR, register_value); 3895 ew32(EEWR, register_value);
3810 3896
3811 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 3897 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
3812 3898
3813 if (error) { 3899 if (error) {
3814 break; 3900 break;
3815 } 3901 }
3816 } 3902 }
3817 3903
3818 return error; 3904 return error;
3819} 3905}
3820 3906
3821/****************************************************************************** 3907/**
3822 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 3908 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
3823 * 3909 *
3824 * hw - Struct containing variables accessed by shared code 3910 * @hw: Struct containing variables accessed by shared code
3825 *****************************************************************************/ 3911 */
3826static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) 3912static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
3827{ 3913{
3828 u32 attempts = 100000; 3914 u32 attempts = 100000;
3829 u32 i, reg = 0; 3915 u32 i, reg = 0;
3830 s32 done = E1000_ERR_EEPROM; 3916 s32 done = E1000_ERR_EEPROM;
3831 3917
3832 for (i = 0; i < attempts; i++) { 3918 for (i = 0; i < attempts; i++) {
3833 if (eerd == E1000_EEPROM_POLL_READ) 3919 if (eerd == E1000_EEPROM_POLL_READ)
3834 reg = er32(EERD); 3920 reg = er32(EERD);
3835 else 3921 else
3836 reg = er32(EEWR); 3922 reg = er32(EEWR);
3837 3923
3838 if (reg & E1000_EEPROM_RW_REG_DONE) { 3924 if (reg & E1000_EEPROM_RW_REG_DONE) {
3839 done = E1000_SUCCESS; 3925 done = E1000_SUCCESS;
3840 break; 3926 break;
3841 } 3927 }
3842 udelay(5); 3928 udelay(5);
3843 } 3929 }
3844 3930
3845 return done; 3931 return done;
3846} 3932}
3847 3933
3848/****************************************************************************** 3934/**
3849 * Verifies that the EEPROM has a valid checksum 3935 * e1000_validate_eeprom_checksum - Verifies that the EEPROM has a valid checksum
3850 * 3936 * @hw: Struct containing variables accessed by shared code
3851 * hw - Struct containing variables accessed by shared code
3852 * 3937 *
3853 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 3938 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
3854 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 3939 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
3855 * valid. 3940 * valid.
3856 *****************************************************************************/ 3941 */
3857s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw) 3942s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
3858{ 3943{
3859 u16 checksum = 0; 3944 u16 checksum = 0;
3860 u16 i, eeprom_data; 3945 u16 i, eeprom_data;
3861 3946
3862 DEBUGFUNC("e1000_validate_eeprom_checksum"); 3947 DEBUGFUNC("e1000_validate_eeprom_checksum");
3863 3948
3864 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { 3949 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3865 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 3950 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3866 DEBUGOUT("EEPROM Read Error\n"); 3951 DEBUGOUT("EEPROM Read Error\n");
3867 return -E1000_ERR_EEPROM; 3952 return -E1000_ERR_EEPROM;
3868 } 3953 }
3869 checksum += eeprom_data; 3954 checksum += eeprom_data;
3870 } 3955 }
3871 3956
3872 if (checksum == (u16)EEPROM_SUM) 3957 if (checksum == (u16) EEPROM_SUM)
3873 return E1000_SUCCESS; 3958 return E1000_SUCCESS;
3874 else { 3959 else {
3875 DEBUGOUT("EEPROM Checksum Invalid\n"); 3960 DEBUGOUT("EEPROM Checksum Invalid\n");
3876 return -E1000_ERR_EEPROM; 3961 return -E1000_ERR_EEPROM;
3877 } 3962 }
3878} 3963}
3879 3964
3880/****************************************************************************** 3965/**
3881 * Calculates the EEPROM checksum and writes it to the EEPROM 3966 * e1000_update_eeprom_checksum - Calculates/writes the EEPROM checksum
3882 * 3967 * @hw: Struct containing variables accessed by shared code
3883 * hw - Struct containing variables accessed by shared code
3884 * 3968 *
3885 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. 3969 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
3886 * Writes the difference to word offset 63 of the EEPROM. 3970 * Writes the difference to word offset 63 of the EEPROM.
3887 *****************************************************************************/ 3971 */
3888s32 e1000_update_eeprom_checksum(struct e1000_hw *hw) 3972s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
3889{ 3973{
3890 u16 checksum = 0; 3974 u16 checksum = 0;
3891 u16 i, eeprom_data; 3975 u16 i, eeprom_data;
3892 3976
3893 DEBUGFUNC("e1000_update_eeprom_checksum"); 3977 DEBUGFUNC("e1000_update_eeprom_checksum");
3894 3978
3895 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { 3979 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
3896 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 3980 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3897 DEBUGOUT("EEPROM Read Error\n"); 3981 DEBUGOUT("EEPROM Read Error\n");
3898 return -E1000_ERR_EEPROM; 3982 return -E1000_ERR_EEPROM;
3899 } 3983 }
3900 checksum += eeprom_data; 3984 checksum += eeprom_data;
3901 } 3985 }
3902 checksum = (u16)EEPROM_SUM - checksum; 3986 checksum = (u16) EEPROM_SUM - checksum;
3903 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 3987 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
3904 DEBUGOUT("EEPROM Write Error\n"); 3988 DEBUGOUT("EEPROM Write Error\n");
3905 return -E1000_ERR_EEPROM; 3989 return -E1000_ERR_EEPROM;
3906 } 3990 }
3907 return E1000_SUCCESS; 3991 return E1000_SUCCESS;
3908} 3992}
3909 3993
3910/****************************************************************************** 3994/**
3911 * Parent function for writing words to the different EEPROM types. 3995 * e1000_write_eeprom - write words to the different EEPROM types.
3912 * 3996 * @hw: Struct containing variables accessed by shared code
3913 * hw - Struct containing variables accessed by shared code 3997 * @offset: offset within the EEPROM to be written to
3914 * offset - offset within the EEPROM to be written to 3998 * @words: number of words to write
3915 * words - number of words to write 3999 * @data: 16 bit word to be written to the EEPROM
3916 * data - 16 bit word to be written to the EEPROM
3917 * 4000 *
3918 * If e1000_update_eeprom_checksum is not called after this function, the 4001 * If e1000_update_eeprom_checksum is not called after this function, the
3919 * EEPROM will most likely contain an invalid checksum. 4002 * EEPROM will most likely contain an invalid checksum.
3920 *****************************************************************************/ 4003 */
3921s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 4004s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
3922{ 4005{
3923 s32 ret; 4006 s32 ret;
3924 spin_lock(&e1000_eeprom_lock); 4007 spin_lock(&e1000_eeprom_lock);
3925 ret = e1000_do_write_eeprom(hw, offset, words, data); 4008 ret = e1000_do_write_eeprom(hw, offset, words, data);
3926 spin_unlock(&e1000_eeprom_lock); 4009 spin_unlock(&e1000_eeprom_lock);
3927 return ret; 4010 return ret;
3928} 4011}
3929 4012
3930 4013static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
3931static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 4014 u16 *data)
3932{ 4015{
3933 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4016 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3934 s32 status = 0; 4017 s32 status = 0;
3935 4018
3936 DEBUGFUNC("e1000_write_eeprom"); 4019 DEBUGFUNC("e1000_write_eeprom");
3937 4020
3938 /* If eeprom is not yet detected, do so now */ 4021 /* If eeprom is not yet detected, do so now */
3939 if (eeprom->word_size == 0) 4022 if (eeprom->word_size == 0)
3940 e1000_init_eeprom_params(hw); 4023 e1000_init_eeprom_params(hw);
3941 4024
3942 /* A check for invalid values: offset too large, too many words, and not 4025 /* A check for invalid values: offset too large, too many words, and not
3943 * enough words. 4026 * enough words.
3944 */ 4027 */
3945 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || 4028 if ((offset >= eeprom->word_size)
3946 (words == 0)) { 4029 || (words > eeprom->word_size - offset) || (words == 0)) {
3947 DEBUGOUT("\"words\" parameter out of bounds\n"); 4030 DEBUGOUT("\"words\" parameter out of bounds\n");
3948 return -E1000_ERR_EEPROM; 4031 return -E1000_ERR_EEPROM;
3949 } 4032 }
3950 4033
3951 if (eeprom->use_eewr) 4034 if (eeprom->use_eewr)
3952 return e1000_write_eeprom_eewr(hw, offset, words, data); 4035 return e1000_write_eeprom_eewr(hw, offset, words, data);
3953 4036
3954 /* Prepare the EEPROM for writing */ 4037 /* Prepare the EEPROM for writing */
3955 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) 4038 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3956 return -E1000_ERR_EEPROM; 4039 return -E1000_ERR_EEPROM;
3957 4040
3958 if (eeprom->type == e1000_eeprom_microwire) { 4041 if (eeprom->type == e1000_eeprom_microwire) {
3959 status = e1000_write_eeprom_microwire(hw, offset, words, data); 4042 status = e1000_write_eeprom_microwire(hw, offset, words, data);
3960 } else { 4043 } else {
3961 status = e1000_write_eeprom_spi(hw, offset, words, data); 4044 status = e1000_write_eeprom_spi(hw, offset, words, data);
3962 msleep(10); 4045 msleep(10);
3963 } 4046 }
3964 4047
3965 /* Done with writing */ 4048 /* Done with writing */
3966 e1000_release_eeprom(hw); 4049 e1000_release_eeprom(hw);
3967 4050
3968 return status; 4051 return status;
3969} 4052}
3970 4053
3971/****************************************************************************** 4054/**
3972 * Writes a 16 bit word to a given offset in an SPI EEPROM. 4055 * e1000_write_eeprom_spi - Writes a 16 bit word to a given offset in an SPI EEPROM.
3973 * 4056 * @hw: Struct containing variables accessed by shared code
3974 * hw - Struct containing variables accessed by shared code 4057 * @offset: offset within the EEPROM to be written to
3975 * offset - offset within the EEPROM to be written to 4058 * @words: number of words to write
3976 * words - number of words to write 4059 * @data: pointer to array of 8 bit words to be written to the EEPROM
3977 * data - pointer to array of 8 bit words to be written to the EEPROM 4060 */
3978 *
3979 *****************************************************************************/
3980static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words, 4061static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
3981 u16 *data) 4062 u16 *data)
3982{ 4063{
3983 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4064 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3984 u16 widx = 0; 4065 u16 widx = 0;
3985 4066
3986 DEBUGFUNC("e1000_write_eeprom_spi"); 4067 DEBUGFUNC("e1000_write_eeprom_spi");
3987 4068
3988 while (widx < words) { 4069 while (widx < words) {
3989 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI; 4070 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
3990 4071
3991 if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM; 4072 if (e1000_spi_eeprom_ready(hw))
4073 return -E1000_ERR_EEPROM;
3992 4074
3993 e1000_standby_eeprom(hw); 4075 e1000_standby_eeprom(hw);
3994 4076
3995 /* Send the WRITE ENABLE command (8 bit opcode ) */ 4077 /* Send the WRITE ENABLE command (8 bit opcode ) */
3996 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, 4078 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
3997 eeprom->opcode_bits); 4079 eeprom->opcode_bits);
3998 4080
3999 e1000_standby_eeprom(hw); 4081 e1000_standby_eeprom(hw);
4000 4082
4001 /* Some SPI eeproms use the 8th address bit embedded in the opcode */ 4083 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
4002 if ((eeprom->address_bits == 8) && (offset >= 128)) 4084 if ((eeprom->address_bits == 8) && (offset >= 128))
4003 write_opcode |= EEPROM_A8_OPCODE_SPI; 4085 write_opcode |= EEPROM_A8_OPCODE_SPI;
4004 4086
4005 /* Send the Write command (8-bit opcode + addr) */ 4087 /* Send the Write command (8-bit opcode + addr) */
4006 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); 4088 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
4007 4089
4008 e1000_shift_out_ee_bits(hw, (u16)((offset + widx)*2), 4090 e1000_shift_out_ee_bits(hw, (u16) ((offset + widx) * 2),
4009 eeprom->address_bits); 4091 eeprom->address_bits);
4010 4092
4011 /* Send the data */ 4093 /* Send the data */
4012 4094
4013 /* Loop to allow for up to whole page write (32 bytes) of eeprom */ 4095 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
4014 while (widx < words) { 4096 while (widx < words) {
4015 u16 word_out = data[widx]; 4097 u16 word_out = data[widx];
4016 word_out = (word_out >> 8) | (word_out << 8); 4098 word_out = (word_out >> 8) | (word_out << 8);
4017 e1000_shift_out_ee_bits(hw, word_out, 16); 4099 e1000_shift_out_ee_bits(hw, word_out, 16);
4018 widx++; 4100 widx++;
4019 4101
4020 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE 4102 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
4021 * operation, while the smaller eeproms are capable of an 8-byte 4103 * operation, while the smaller eeproms are capable of an 8-byte
4022 * PAGE WRITE operation. Break the inner loop to pass new address 4104 * PAGE WRITE operation. Break the inner loop to pass new address
4023 */ 4105 */
4024 if ((((offset + widx)*2) % eeprom->page_size) == 0) { 4106 if ((((offset + widx) * 2) % eeprom->page_size) == 0) {
4025 e1000_standby_eeprom(hw); 4107 e1000_standby_eeprom(hw);
4026 break; 4108 break;
4027 } 4109 }
4028 } 4110 }
4029 } 4111 }
4030 4112
4031 return E1000_SUCCESS; 4113 return E1000_SUCCESS;
4032} 4114}
4033 4115
4034/****************************************************************************** 4116/**
4035 * Writes a 16 bit word to a given offset in a Microwire EEPROM. 4117 * e1000_write_eeprom_microwire - Writes a 16 bit word to a given offset in a Microwire EEPROM.
4036 * 4118 * @hw: Struct containing variables accessed by shared code
4037 * hw - Struct containing variables accessed by shared code 4119 * @offset: offset within the EEPROM to be written to
4038 * offset - offset within the EEPROM to be written to 4120 * @words: number of words to write
4039 * words - number of words to write 4121 * @data: pointer to array of 8 bit words to be written to the EEPROM
4040 * data - pointer to array of 16 bit words to be written to the EEPROM 4122 */
4041 *
4042 *****************************************************************************/
4043static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset, 4123static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
4044 u16 words, u16 *data) 4124 u16 words, u16 *data)
4045{ 4125{
4046 struct e1000_eeprom_info *eeprom = &hw->eeprom; 4126 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4047 u32 eecd; 4127 u32 eecd;
4048 u16 words_written = 0; 4128 u16 words_written = 0;
4049 u16 i = 0; 4129 u16 i = 0;
4050 4130
4051 DEBUGFUNC("e1000_write_eeprom_microwire"); 4131 DEBUGFUNC("e1000_write_eeprom_microwire");
4052 4132
4053 /* Send the write enable command to the EEPROM (3-bit opcode plus 4133 /* Send the write enable command to the EEPROM (3-bit opcode plus
4054 * 6/8-bit dummy address beginning with 11). It's less work to include 4134 * 6/8-bit dummy address beginning with 11). It's less work to include
4055 * the 11 of the dummy address as part of the opcode than it is to shift 4135 * the 11 of the dummy address as part of the opcode than it is to shift
4056 * it over the correct number of bits for the address. This puts the 4136 * it over the correct number of bits for the address. This puts the
4057 * EEPROM into write/erase mode. 4137 * EEPROM into write/erase mode.
4058 */ 4138 */
4059 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, 4139 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
4060 (u16)(eeprom->opcode_bits + 2)); 4140 (u16) (eeprom->opcode_bits + 2));
4061 4141
4062 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2)); 4142 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));
4063 4143
4064 /* Prepare the EEPROM */ 4144 /* Prepare the EEPROM */
4065 e1000_standby_eeprom(hw); 4145 e1000_standby_eeprom(hw);
4066 4146
4067 while (words_written < words) { 4147 while (words_written < words) {
4068 /* Send the Write command (3-bit opcode + addr) */ 4148 /* Send the Write command (3-bit opcode + addr) */
4069 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, 4149 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
4070 eeprom->opcode_bits); 4150 eeprom->opcode_bits);
4071 4151
4072 e1000_shift_out_ee_bits(hw, (u16)(offset + words_written), 4152 e1000_shift_out_ee_bits(hw, (u16) (offset + words_written),
4073 eeprom->address_bits); 4153 eeprom->address_bits);
4074 4154
4075 /* Send the data */ 4155 /* Send the data */
4076 e1000_shift_out_ee_bits(hw, data[words_written], 16); 4156 e1000_shift_out_ee_bits(hw, data[words_written], 16);
4077 4157
4078 /* Toggle the CS line. This in effect tells the EEPROM to execute 4158 /* Toggle the CS line. This in effect tells the EEPROM to execute
4079 * the previous command. 4159 * the previous command.
4080 */ 4160 */
4081 e1000_standby_eeprom(hw); 4161 e1000_standby_eeprom(hw);
4082 4162
4083 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will 4163 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
4084 * signal that the command has been completed by raising the DO signal. 4164 * signal that the command has been completed by raising the DO signal.
4085 * If DO does not go high in 10 milliseconds, then error out. 4165 * If DO does not go high in 10 milliseconds, then error out.
4086 */ 4166 */
4087 for (i = 0; i < 200; i++) { 4167 for (i = 0; i < 200; i++) {
4088 eecd = er32(EECD); 4168 eecd = er32(EECD);
4089 if (eecd & E1000_EECD_DO) break; 4169 if (eecd & E1000_EECD_DO)
4090 udelay(50); 4170 break;
4091 } 4171 udelay(50);
4092 if (i == 200) { 4172 }
4093 DEBUGOUT("EEPROM Write did not complete\n"); 4173 if (i == 200) {
4094 return -E1000_ERR_EEPROM; 4174 DEBUGOUT("EEPROM Write did not complete\n");
4095 } 4175 return -E1000_ERR_EEPROM;
4096 4176 }
4097 /* Recover from write */ 4177
4098 e1000_standby_eeprom(hw); 4178 /* Recover from write */
4099 4179 e1000_standby_eeprom(hw);
4100 words_written++; 4180
4101 } 4181 words_written++;
4102 4182 }
4103 /* Send the write disable command to the EEPROM (3-bit opcode plus 4183
4104 * 6/8-bit dummy address beginning with 10). It's less work to include 4184 /* Send the write disable command to the EEPROM (3-bit opcode plus
4105 * the 10 of the dummy address as part of the opcode than it is to shift 4185 * 6/8-bit dummy address beginning with 10). It's less work to include
4106 * it over the correct number of bits for the address. This takes the 4186 * the 10 of the dummy address as part of the opcode than it is to shift
4107 * EEPROM out of write/erase mode. 4187 * it over the correct number of bits for the address. This takes the
4108 */ 4188 * EEPROM out of write/erase mode.
4109 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, 4189 */
4110 (u16)(eeprom->opcode_bits + 2)); 4190 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
4111 4191 (u16) (eeprom->opcode_bits + 2));
4112 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2)); 4192
4113 4193 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));
4114 return E1000_SUCCESS; 4194
4195 return E1000_SUCCESS;
4115} 4196}
4116 4197
4117/****************************************************************************** 4198/**
4199 * e1000_read_mac_addr - read the adapters MAC from eeprom
4200 * @hw: Struct containing variables accessed by shared code
4201 *
4118 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 4202 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
4119 * second function of dual function devices 4203 * second function of dual function devices
4120 * 4204 */
4121 * hw - Struct containing variables accessed by shared code
4122 *****************************************************************************/
4123s32 e1000_read_mac_addr(struct e1000_hw *hw) 4205s32 e1000_read_mac_addr(struct e1000_hw *hw)
4124{ 4206{
4125 u16 offset; 4207 u16 offset;
4126 u16 eeprom_data, i; 4208 u16 eeprom_data, i;
4127 4209
4128 DEBUGFUNC("e1000_read_mac_addr"); 4210 DEBUGFUNC("e1000_read_mac_addr");
4129 4211
4130 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 4212 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
4131 offset = i >> 1; 4213 offset = i >> 1;
4132 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 4214 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
4133 DEBUGOUT("EEPROM Read Error\n"); 4215 DEBUGOUT("EEPROM Read Error\n");
4134 return -E1000_ERR_EEPROM; 4216 return -E1000_ERR_EEPROM;
4135 } 4217 }
4136 hw->perm_mac_addr[i] = (u8)(eeprom_data & 0x00FF); 4218 hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF);
4137 hw->perm_mac_addr[i+1] = (u8)(eeprom_data >> 8); 4219 hw->perm_mac_addr[i + 1] = (u8) (eeprom_data >> 8);
4138 } 4220 }
4139 4221
4140 switch (hw->mac_type) { 4222 switch (hw->mac_type) {
4141 default: 4223 default:
4142 break; 4224 break;
4143 case e1000_82546: 4225 case e1000_82546:
4144 case e1000_82546_rev_3: 4226 case e1000_82546_rev_3:
4145 if (er32(STATUS) & E1000_STATUS_FUNC_1) 4227 if (er32(STATUS) & E1000_STATUS_FUNC_1)
4146 hw->perm_mac_addr[5] ^= 0x01; 4228 hw->perm_mac_addr[5] ^= 0x01;
4147 break; 4229 break;
4148 } 4230 }
4149 4231
4150 for (i = 0; i < NODE_ADDRESS_SIZE; i++) 4232 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
4151 hw->mac_addr[i] = hw->perm_mac_addr[i]; 4233 hw->mac_addr[i] = hw->perm_mac_addr[i];
4152 return E1000_SUCCESS; 4234 return E1000_SUCCESS;
4153} 4235}
4154 4236
4155/****************************************************************************** 4237/**
4156 * Initializes receive address filters. 4238 * e1000_init_rx_addrs - Initializes receive address filters.
4157 * 4239 * @hw: Struct containing variables accessed by shared code
4158 * hw - Struct containing variables accessed by shared code
4159 * 4240 *
4160 * Places the MAC address in receive address register 0 and clears the rest 4241 * Places the MAC address in receive address register 0 and clears the rest
4161 * of the receive addresss registers. Clears the multicast table. Assumes 4242 * of the receive address registers. Clears the multicast table. Assumes
4162 * the receiver is in reset when the routine is called. 4243 * the receiver is in reset when the routine is called.
4163 *****************************************************************************/ 4244 */
4164static void e1000_init_rx_addrs(struct e1000_hw *hw) 4245static void e1000_init_rx_addrs(struct e1000_hw *hw)
4165{ 4246{
4166 u32 i; 4247 u32 i;
4167 u32 rar_num; 4248 u32 rar_num;
4168 4249
4169 DEBUGFUNC("e1000_init_rx_addrs"); 4250 DEBUGFUNC("e1000_init_rx_addrs");
4170 4251
4171 /* Setup the receive address. */ 4252 /* Setup the receive address. */
4172 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 4253 DEBUGOUT("Programming MAC Address into RAR[0]\n");
4173 4254
4174 e1000_rar_set(hw, hw->mac_addr, 0); 4255 e1000_rar_set(hw, hw->mac_addr, 0);
4175 4256
4176 rar_num = E1000_RAR_ENTRIES; 4257 rar_num = E1000_RAR_ENTRIES;
4177 4258
4178 /* Zero out the other 15 receive addresses. */ 4259 /* Zero out the other 15 receive addresses. */
4179 DEBUGOUT("Clearing RAR[1-15]\n"); 4260 DEBUGOUT("Clearing RAR[1-15]\n");
4180 for (i = 1; i < rar_num; i++) { 4261 for (i = 1; i < rar_num; i++) {
4181 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 4262 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4182 E1000_WRITE_FLUSH(); 4263 E1000_WRITE_FLUSH();
4183 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 4264 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
4184 E1000_WRITE_FLUSH(); 4265 E1000_WRITE_FLUSH();
4185 } 4266 }
4186} 4267}
4187 4268
4188/****************************************************************************** 4269/**
4189 * Hashes an address to determine its location in the multicast table 4270 * e1000_hash_mc_addr - Hashes an address to determine its location in the multicast table
4190 * 4271 * @hw: Struct containing variables accessed by shared code
4191 * hw - Struct containing variables accessed by shared code 4272 * @mc_addr: the multicast address to hash
4192 * mc_addr - the multicast address to hash 4273 */
4193 *****************************************************************************/
4194u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) 4274u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
4195{ 4275{
4196 u32 hash_value = 0; 4276 u32 hash_value = 0;
4197 4277
4198 /* The portion of the address that is used for the hash table is 4278 /* The portion of the address that is used for the hash table is
4199 * determined by the mc_filter_type setting. 4279 * determined by the mc_filter_type setting.
4200 */ 4280 */
4201 switch (hw->mc_filter_type) { 4281 switch (hw->mc_filter_type) {
4202 /* [0] [1] [2] [3] [4] [5] 4282 /* [0] [1] [2] [3] [4] [5]
4203 * 01 AA 00 12 34 56 4283 * 01 AA 00 12 34 56
4204 * LSB MSB 4284 * LSB MSB
4205 */ 4285 */
4206 case 0: 4286 case 0:
4207 /* [47:36] i.e. 0x563 for above example address */ 4287 /* [47:36] i.e. 0x563 for above example address */
4208 hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 4288 hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
4209 break; 4289 break;
4210 case 1: 4290 case 1:
4211 /* [46:35] i.e. 0xAC6 for above example address */ 4291 /* [46:35] i.e. 0xAC6 for above example address */
4212 hash_value = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 4292 hash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));
4213 break; 4293 break;
4214 case 2: 4294 case 2:
4215 /* [45:34] i.e. 0x5D8 for above example address */ 4295 /* [45:34] i.e. 0x5D8 for above example address */
4216 hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 4296 hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
4217 break; 4297 break;
4218 case 3: 4298 case 3:
4219 /* [43:32] i.e. 0x634 for above example address */ 4299 /* [43:32] i.e. 0x634 for above example address */
4220 hash_value = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 4300 hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));
4221 break; 4301 break;
4222 } 4302 }
4223 4303
4224 hash_value &= 0xFFF; 4304 hash_value &= 0xFFF;
4225 return hash_value; 4305 return hash_value;
4226} 4306}
4227 4307
4228/****************************************************************************** 4308/**
4229 * Puts an ethernet address into a receive address register. 4309 * e1000_rar_set - Puts an ethernet address into a receive address register.
4230 * 4310 * @hw: Struct containing variables accessed by shared code
4231 * hw - Struct containing variables accessed by shared code 4311 * @addr: Address to put into receive address register
4232 * addr - Address to put into receive address register 4312 * @index: Receive address register to write
4233 * index - Receive address register to write 4313 */
4234 *****************************************************************************/
4235void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) 4314void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
4236{ 4315{
4237 u32 rar_low, rar_high; 4316 u32 rar_low, rar_high;
4238 4317
4239 /* HW expects these in little endian so we reverse the byte order 4318 /* HW expects these in little endian so we reverse the byte order
4240 * from network order (big endian) to little endian 4319 * from network order (big endian) to little endian
4241 */ 4320 */
4242 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | 4321 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
4243 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 4322 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
4244 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 4323 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
4245 4324
4246 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx 4325 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
4247 * unit hang. 4326 * unit hang.
4248 * 4327 *
4249 * Description: 4328 * Description:
4250 * If there are any Rx frames queued up or otherwise present in the HW 4329 * If there are any Rx frames queued up or otherwise present in the HW
4251 * before RSS is enabled, and then we enable RSS, the HW Rx unit will 4330 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
4252 * hang. To work around this issue, we have to disable receives and 4331 * hang. To work around this issue, we have to disable receives and
4253 * flush out all Rx frames before we enable RSS. To do so, we modify we 4332 * flush out all Rx frames before we enable RSS. To do so, we modify we
4254 * redirect all Rx traffic to manageability and then reset the HW. 4333 * redirect all Rx traffic to manageability and then reset the HW.
4255 * This flushes away Rx frames, and (since the redirections to 4334 * This flushes away Rx frames, and (since the redirections to
4256 * manageability persists across resets) keeps new ones from coming in 4335 * manageability persists across resets) keeps new ones from coming in
4257 * while we work. Then, we clear the Address Valid AV bit for all MAC 4336 * while we work. Then, we clear the Address Valid AV bit for all MAC
4258 * addresses and undo the re-direction to manageability. 4337 * addresses and undo the re-direction to manageability.
4259 * Now, frames are coming in again, but the MAC won't accept them, so 4338 * Now, frames are coming in again, but the MAC won't accept them, so
4260 * far so good. We now proceed to initialize RSS (if necessary) and 4339 * far so good. We now proceed to initialize RSS (if necessary) and
4261 * configure the Rx unit. Last, we re-enable the AV bits and continue 4340 * configure the Rx unit. Last, we re-enable the AV bits and continue
4262 * on our merry way. 4341 * on our merry way.
4263 */ 4342 */
4264 switch (hw->mac_type) { 4343 switch (hw->mac_type) {
4265 default: 4344 default:
4266 /* Indicate to hardware the Address is Valid. */ 4345 /* Indicate to hardware the Address is Valid. */
4267 rar_high |= E1000_RAH_AV; 4346 rar_high |= E1000_RAH_AV;
4268 break; 4347 break;
4269 } 4348 }
4270 4349
4271 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 4350 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
4272 E1000_WRITE_FLUSH(); 4351 E1000_WRITE_FLUSH();
4273 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 4352 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
4274 E1000_WRITE_FLUSH(); 4353 E1000_WRITE_FLUSH();
4275} 4354}
4276 4355
4277/****************************************************************************** 4356/**
4278 * Writes a value to the specified offset in the VLAN filter table. 4357 * e1000_write_vfta - Writes a value to the specified offset in the VLAN filter table.
4279 * 4358 * @hw: Struct containing variables accessed by shared code
4280 * hw - Struct containing variables accessed by shared code 4359 * @offset: Offset in VLAN filer table to write
4281 * offset - Offset in VLAN filer table to write 4360 * @value: Value to write into VLAN filter table
4282 * value - Value to write into VLAN filter table 4361 */
4283 *****************************************************************************/
4284void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value) 4362void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
4285{ 4363{
4286 u32 temp; 4364 u32 temp;
4287 4365
4288 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { 4366 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
4289 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); 4367 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
4290 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 4368 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4291 E1000_WRITE_FLUSH(); 4369 E1000_WRITE_FLUSH();
4292 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); 4370 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4293 E1000_WRITE_FLUSH(); 4371 E1000_WRITE_FLUSH();
4294 } else { 4372 } else {
4295 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); 4373 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4296 E1000_WRITE_FLUSH(); 4374 E1000_WRITE_FLUSH();
4297 } 4375 }
4298} 4376}
4299 4377
4300/****************************************************************************** 4378/**
4301 * Clears the VLAN filer table 4379 * e1000_clear_vfta - Clears the VLAN filer table
4302 * 4380 * @hw: Struct containing variables accessed by shared code
4303 * hw - Struct containing variables accessed by shared code 4381 */
4304 *****************************************************************************/
4305static void e1000_clear_vfta(struct e1000_hw *hw) 4382static void e1000_clear_vfta(struct e1000_hw *hw)
4306{ 4383{
4307 u32 offset; 4384 u32 offset;
4308 u32 vfta_value = 0; 4385 u32 vfta_value = 0;
4309 u32 vfta_offset = 0; 4386 u32 vfta_offset = 0;
4310 u32 vfta_bit_in_reg = 0; 4387 u32 vfta_bit_in_reg = 0;
4311 4388
4312 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 4389 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
4313 /* If the offset we want to clear is the same offset of the 4390 /* If the offset we want to clear is the same offset of the
4314 * manageability VLAN ID, then clear all bits except that of the 4391 * manageability VLAN ID, then clear all bits except that of the
4315 * manageability unit */ 4392 * manageability unit */
4316 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 4393 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
4317 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); 4394 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
4318 E1000_WRITE_FLUSH(); 4395 E1000_WRITE_FLUSH();
4319 } 4396 }
4320} 4397}
4321 4398
4322static s32 e1000_id_led_init(struct e1000_hw *hw) 4399static s32 e1000_id_led_init(struct e1000_hw *hw)
4323{ 4400{
4324 u32 ledctl; 4401 u32 ledctl;
4325 const u32 ledctl_mask = 0x000000FF; 4402 const u32 ledctl_mask = 0x000000FF;
4326 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 4403 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
4327 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 4404 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
4328 u16 eeprom_data, i, temp; 4405 u16 eeprom_data, i, temp;
4329 const u16 led_mask = 0x0F; 4406 const u16 led_mask = 0x0F;
4330 4407
4331 DEBUGFUNC("e1000_id_led_init"); 4408 DEBUGFUNC("e1000_id_led_init");
4332 4409
4333 if (hw->mac_type < e1000_82540) { 4410 if (hw->mac_type < e1000_82540) {
4334 /* Nothing to do */ 4411 /* Nothing to do */
4335 return E1000_SUCCESS; 4412 return E1000_SUCCESS;
4336 } 4413 }
4337 4414
4338 ledctl = er32(LEDCTL); 4415 ledctl = er32(LEDCTL);
4339 hw->ledctl_default = ledctl; 4416 hw->ledctl_default = ledctl;
4340 hw->ledctl_mode1 = hw->ledctl_default; 4417 hw->ledctl_mode1 = hw->ledctl_default;
4341 hw->ledctl_mode2 = hw->ledctl_default; 4418 hw->ledctl_mode2 = hw->ledctl_default;
4342 4419
4343 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { 4420 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
4344 DEBUGOUT("EEPROM Read Error\n"); 4421 DEBUGOUT("EEPROM Read Error\n");
4345 return -E1000_ERR_EEPROM; 4422 return -E1000_ERR_EEPROM;
4346 } 4423 }
4347 4424
4348 if ((eeprom_data == ID_LED_RESERVED_0000) || 4425 if ((eeprom_data == ID_LED_RESERVED_0000) ||
4349 (eeprom_data == ID_LED_RESERVED_FFFF)) { 4426 (eeprom_data == ID_LED_RESERVED_FFFF)) {
4350 eeprom_data = ID_LED_DEFAULT; 4427 eeprom_data = ID_LED_DEFAULT;
4351 } 4428 }
4352 4429
4353 for (i = 0; i < 4; i++) { 4430 for (i = 0; i < 4; i++) {
4354 temp = (eeprom_data >> (i << 2)) & led_mask; 4431 temp = (eeprom_data >> (i << 2)) & led_mask;
4355 switch (temp) { 4432 switch (temp) {
4356 case ID_LED_ON1_DEF2: 4433 case ID_LED_ON1_DEF2:
4357 case ID_LED_ON1_ON2: 4434 case ID_LED_ON1_ON2:
4358 case ID_LED_ON1_OFF2: 4435 case ID_LED_ON1_OFF2:
4359 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 4436 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4360 hw->ledctl_mode1 |= ledctl_on << (i << 3); 4437 hw->ledctl_mode1 |= ledctl_on << (i << 3);
4361 break; 4438 break;
4362 case ID_LED_OFF1_DEF2: 4439 case ID_LED_OFF1_DEF2:
4363 case ID_LED_OFF1_ON2: 4440 case ID_LED_OFF1_ON2:
4364 case ID_LED_OFF1_OFF2: 4441 case ID_LED_OFF1_OFF2:
4365 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 4442 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4366 hw->ledctl_mode1 |= ledctl_off << (i << 3); 4443 hw->ledctl_mode1 |= ledctl_off << (i << 3);
4367 break; 4444 break;
4368 default: 4445 default:
4369 /* Do nothing */ 4446 /* Do nothing */
4370 break; 4447 break;
4371 } 4448 }
4372 switch (temp) { 4449 switch (temp) {
4373 case ID_LED_DEF1_ON2: 4450 case ID_LED_DEF1_ON2:
4374 case ID_LED_ON1_ON2: 4451 case ID_LED_ON1_ON2:
4375 case ID_LED_OFF1_ON2: 4452 case ID_LED_OFF1_ON2:
4376 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 4453 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4377 hw->ledctl_mode2 |= ledctl_on << (i << 3); 4454 hw->ledctl_mode2 |= ledctl_on << (i << 3);
4378 break; 4455 break;
4379 case ID_LED_DEF1_OFF2: 4456 case ID_LED_DEF1_OFF2:
4380 case ID_LED_ON1_OFF2: 4457 case ID_LED_ON1_OFF2:
4381 case ID_LED_OFF1_OFF2: 4458 case ID_LED_OFF1_OFF2:
4382 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 4459 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4383 hw->ledctl_mode2 |= ledctl_off << (i << 3); 4460 hw->ledctl_mode2 |= ledctl_off << (i << 3);
4384 break; 4461 break;
4385 default: 4462 default:
4386 /* Do nothing */ 4463 /* Do nothing */
4387 break; 4464 break;
4388 } 4465 }
4389 } 4466 }
4390 return E1000_SUCCESS; 4467 return E1000_SUCCESS;
4391} 4468}
4392 4469
4393/****************************************************************************** 4470/**
4394 * Prepares SW controlable LED for use and saves the current state of the LED. 4471 * e1000_setup_led
4472 * @hw: Struct containing variables accessed by shared code
4395 * 4473 *
4396 * hw - Struct containing variables accessed by shared code 4474 * Prepares SW controlable LED for use and saves the current state of the LED.
4397 *****************************************************************************/ 4475 */
4398s32 e1000_setup_led(struct e1000_hw *hw) 4476s32 e1000_setup_led(struct e1000_hw *hw)
4399{ 4477{
4400 u32 ledctl; 4478 u32 ledctl;
4401 s32 ret_val = E1000_SUCCESS; 4479 s32 ret_val = E1000_SUCCESS;
4402 4480
4403 DEBUGFUNC("e1000_setup_led"); 4481 DEBUGFUNC("e1000_setup_led");
4404 4482
4405 switch (hw->mac_type) { 4483 switch (hw->mac_type) {
4406 case e1000_82542_rev2_0: 4484 case e1000_82542_rev2_0:
4407 case e1000_82542_rev2_1: 4485 case e1000_82542_rev2_1:
4408 case e1000_82543: 4486 case e1000_82543:
4409 case e1000_82544: 4487 case e1000_82544:
4410 /* No setup necessary */ 4488 /* No setup necessary */
4411 break; 4489 break;
4412 case e1000_82541: 4490 case e1000_82541:
4413 case e1000_82547: 4491 case e1000_82547:
4414 case e1000_82541_rev_2: 4492 case e1000_82541_rev_2:
4415 case e1000_82547_rev_2: 4493 case e1000_82547_rev_2:
4416 /* Turn off PHY Smart Power Down (if enabled) */ 4494 /* Turn off PHY Smart Power Down (if enabled) */
4417 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, 4495 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
4418 &hw->phy_spd_default); 4496 &hw->phy_spd_default);
4419 if (ret_val) 4497 if (ret_val)
4420 return ret_val; 4498 return ret_val;
4421 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 4499 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4422 (u16)(hw->phy_spd_default & 4500 (u16) (hw->phy_spd_default &
4423 ~IGP01E1000_GMII_SPD)); 4501 ~IGP01E1000_GMII_SPD));
4424 if (ret_val) 4502 if (ret_val)
4425 return ret_val; 4503 return ret_val;
4426 /* Fall Through */ 4504 /* Fall Through */
4427 default: 4505 default:
4428 if (hw->media_type == e1000_media_type_fiber) { 4506 if (hw->media_type == e1000_media_type_fiber) {
4429 ledctl = er32(LEDCTL); 4507 ledctl = er32(LEDCTL);
4430 /* Save current LEDCTL settings */ 4508 /* Save current LEDCTL settings */
4431 hw->ledctl_default = ledctl; 4509 hw->ledctl_default = ledctl;
4432 /* Turn off LED0 */ 4510 /* Turn off LED0 */
4433 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 4511 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
4434 E1000_LEDCTL_LED0_BLINK | 4512 E1000_LEDCTL_LED0_BLINK |
4435 E1000_LEDCTL_LED0_MODE_MASK); 4513 E1000_LEDCTL_LED0_MODE_MASK);
4436 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 4514 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
4437 E1000_LEDCTL_LED0_MODE_SHIFT); 4515 E1000_LEDCTL_LED0_MODE_SHIFT);
4438 ew32(LEDCTL, ledctl); 4516 ew32(LEDCTL, ledctl);
4439 } else if (hw->media_type == e1000_media_type_copper) 4517 } else if (hw->media_type == e1000_media_type_copper)
4440 ew32(LEDCTL, hw->ledctl_mode1); 4518 ew32(LEDCTL, hw->ledctl_mode1);
4441 break; 4519 break;
4442 } 4520 }
4443 4521
4444 return E1000_SUCCESS; 4522 return E1000_SUCCESS;
4445} 4523}
4446 4524
4447/****************************************************************************** 4525/**
4448 * Restores the saved state of the SW controlable LED. 4526 * e1000_cleanup_led - Restores the saved state of the SW controlable LED.
4449 * 4527 * @hw: Struct containing variables accessed by shared code
4450 * hw - Struct containing variables accessed by shared code 4528 */
4451 *****************************************************************************/
4452s32 e1000_cleanup_led(struct e1000_hw *hw) 4529s32 e1000_cleanup_led(struct e1000_hw *hw)
4453{ 4530{
4454 s32 ret_val = E1000_SUCCESS; 4531 s32 ret_val = E1000_SUCCESS;
4455 4532
4456 DEBUGFUNC("e1000_cleanup_led"); 4533 DEBUGFUNC("e1000_cleanup_led");
4457 4534
4458 switch (hw->mac_type) { 4535 switch (hw->mac_type) {
4459 case e1000_82542_rev2_0: 4536 case e1000_82542_rev2_0:
4460 case e1000_82542_rev2_1: 4537 case e1000_82542_rev2_1:
4461 case e1000_82543: 4538 case e1000_82543:
4462 case e1000_82544: 4539 case e1000_82544:
4463 /* No cleanup necessary */ 4540 /* No cleanup necessary */
4464 break; 4541 break;
4465 case e1000_82541: 4542 case e1000_82541:
4466 case e1000_82547: 4543 case e1000_82547:
4467 case e1000_82541_rev_2: 4544 case e1000_82541_rev_2:
4468 case e1000_82547_rev_2: 4545 case e1000_82547_rev_2:
4469 /* Turn on PHY Smart Power Down (if previously enabled) */ 4546 /* Turn on PHY Smart Power Down (if previously enabled) */
4470 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 4547 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4471 hw->phy_spd_default); 4548 hw->phy_spd_default);
4472 if (ret_val) 4549 if (ret_val)
4473 return ret_val; 4550 return ret_val;
4474 /* Fall Through */ 4551 /* Fall Through */
4475 default: 4552 default:
4476 /* Restore LEDCTL settings */ 4553 /* Restore LEDCTL settings */
4477 ew32(LEDCTL, hw->ledctl_default); 4554 ew32(LEDCTL, hw->ledctl_default);
4478 break; 4555 break;
4479 } 4556 }
4480 4557
4481 return E1000_SUCCESS; 4558 return E1000_SUCCESS;
4482} 4559}
4483 4560
4484/****************************************************************************** 4561/**
4485 * Turns on the software controllable LED 4562 * e1000_led_on - Turns on the software controllable LED
4486 * 4563 * @hw: Struct containing variables accessed by shared code
4487 * hw - Struct containing variables accessed by shared code 4564 */
4488 *****************************************************************************/
4489s32 e1000_led_on(struct e1000_hw *hw) 4565s32 e1000_led_on(struct e1000_hw *hw)
4490{ 4566{
4491 u32 ctrl = er32(CTRL); 4567 u32 ctrl = er32(CTRL);
4492 4568
4493 DEBUGFUNC("e1000_led_on"); 4569 DEBUGFUNC("e1000_led_on");
4494 4570
4495 switch (hw->mac_type) { 4571 switch (hw->mac_type) {
4496 case e1000_82542_rev2_0: 4572 case e1000_82542_rev2_0:
4497 case e1000_82542_rev2_1: 4573 case e1000_82542_rev2_1:
4498 case e1000_82543: 4574 case e1000_82543:
4499 /* Set SW Defineable Pin 0 to turn on the LED */ 4575 /* Set SW Defineable Pin 0 to turn on the LED */
4500 ctrl |= E1000_CTRL_SWDPIN0; 4576 ctrl |= E1000_CTRL_SWDPIN0;
4501 ctrl |= E1000_CTRL_SWDPIO0; 4577 ctrl |= E1000_CTRL_SWDPIO0;
4502 break; 4578 break;
4503 case e1000_82544: 4579 case e1000_82544:
4504 if (hw->media_type == e1000_media_type_fiber) { 4580 if (hw->media_type == e1000_media_type_fiber) {
4505 /* Set SW Defineable Pin 0 to turn on the LED */ 4581 /* Set SW Defineable Pin 0 to turn on the LED */
4506 ctrl |= E1000_CTRL_SWDPIN0; 4582 ctrl |= E1000_CTRL_SWDPIN0;
4507 ctrl |= E1000_CTRL_SWDPIO0; 4583 ctrl |= E1000_CTRL_SWDPIO0;
4508 } else { 4584 } else {
4509 /* Clear SW Defineable Pin 0 to turn on the LED */ 4585 /* Clear SW Defineable Pin 0 to turn on the LED */
4510 ctrl &= ~E1000_CTRL_SWDPIN0; 4586 ctrl &= ~E1000_CTRL_SWDPIN0;
4511 ctrl |= E1000_CTRL_SWDPIO0; 4587 ctrl |= E1000_CTRL_SWDPIO0;
4512 } 4588 }
4513 break; 4589 break;
4514 default: 4590 default:
4515 if (hw->media_type == e1000_media_type_fiber) { 4591 if (hw->media_type == e1000_media_type_fiber) {
4516 /* Clear SW Defineable Pin 0 to turn on the LED */ 4592 /* Clear SW Defineable Pin 0 to turn on the LED */
4517 ctrl &= ~E1000_CTRL_SWDPIN0; 4593 ctrl &= ~E1000_CTRL_SWDPIN0;
4518 ctrl |= E1000_CTRL_SWDPIO0; 4594 ctrl |= E1000_CTRL_SWDPIO0;
4519 } else if (hw->media_type == e1000_media_type_copper) { 4595 } else if (hw->media_type == e1000_media_type_copper) {
4520 ew32(LEDCTL, hw->ledctl_mode2); 4596 ew32(LEDCTL, hw->ledctl_mode2);
4521 return E1000_SUCCESS; 4597 return E1000_SUCCESS;
4522 } 4598 }
4523 break; 4599 break;
4524 } 4600 }
4525 4601
4526 ew32(CTRL, ctrl); 4602 ew32(CTRL, ctrl);
4527 4603
4528 return E1000_SUCCESS; 4604 return E1000_SUCCESS;
4529} 4605}
4530 4606
4531/****************************************************************************** 4607/**
4532 * Turns off the software controllable LED 4608 * e1000_led_off - Turns off the software controllable LED
4533 * 4609 * @hw: Struct containing variables accessed by shared code
4534 * hw - Struct containing variables accessed by shared code 4610 */
4535 *****************************************************************************/
4536s32 e1000_led_off(struct e1000_hw *hw) 4611s32 e1000_led_off(struct e1000_hw *hw)
4537{ 4612{
4538 u32 ctrl = er32(CTRL); 4613 u32 ctrl = er32(CTRL);
4539 4614
4540 DEBUGFUNC("e1000_led_off"); 4615 DEBUGFUNC("e1000_led_off");
4541 4616
4542 switch (hw->mac_type) { 4617 switch (hw->mac_type) {
4543 case e1000_82542_rev2_0: 4618 case e1000_82542_rev2_0:
4544 case e1000_82542_rev2_1: 4619 case e1000_82542_rev2_1:
4545 case e1000_82543: 4620 case e1000_82543:
4546 /* Clear SW Defineable Pin 0 to turn off the LED */ 4621 /* Clear SW Defineable Pin 0 to turn off the LED */
4547 ctrl &= ~E1000_CTRL_SWDPIN0; 4622 ctrl &= ~E1000_CTRL_SWDPIN0;
4548 ctrl |= E1000_CTRL_SWDPIO0; 4623 ctrl |= E1000_CTRL_SWDPIO0;
4549 break; 4624 break;
4550 case e1000_82544: 4625 case e1000_82544:
4551 if (hw->media_type == e1000_media_type_fiber) { 4626 if (hw->media_type == e1000_media_type_fiber) {
4552 /* Clear SW Defineable Pin 0 to turn off the LED */ 4627 /* Clear SW Defineable Pin 0 to turn off the LED */
4553 ctrl &= ~E1000_CTRL_SWDPIN0; 4628 ctrl &= ~E1000_CTRL_SWDPIN0;
4554 ctrl |= E1000_CTRL_SWDPIO0; 4629 ctrl |= E1000_CTRL_SWDPIO0;
4555 } else { 4630 } else {
4556 /* Set SW Defineable Pin 0 to turn off the LED */ 4631 /* Set SW Defineable Pin 0 to turn off the LED */
4557 ctrl |= E1000_CTRL_SWDPIN0; 4632 ctrl |= E1000_CTRL_SWDPIN0;
4558 ctrl |= E1000_CTRL_SWDPIO0; 4633 ctrl |= E1000_CTRL_SWDPIO0;
4559 } 4634 }
4560 break; 4635 break;
4561 default: 4636 default:
4562 if (hw->media_type == e1000_media_type_fiber) { 4637 if (hw->media_type == e1000_media_type_fiber) {
4563 /* Set SW Defineable Pin 0 to turn off the LED */ 4638 /* Set SW Defineable Pin 0 to turn off the LED */
4564 ctrl |= E1000_CTRL_SWDPIN0; 4639 ctrl |= E1000_CTRL_SWDPIN0;
4565 ctrl |= E1000_CTRL_SWDPIO0; 4640 ctrl |= E1000_CTRL_SWDPIO0;
4566 } else if (hw->media_type == e1000_media_type_copper) { 4641 } else if (hw->media_type == e1000_media_type_copper) {
4567 ew32(LEDCTL, hw->ledctl_mode1); 4642 ew32(LEDCTL, hw->ledctl_mode1);
4568 return E1000_SUCCESS; 4643 return E1000_SUCCESS;
4569 } 4644 }
4570 break; 4645 break;
4571 } 4646 }
4572 4647
4573 ew32(CTRL, ctrl); 4648 ew32(CTRL, ctrl);
4574 4649
4575 return E1000_SUCCESS; 4650 return E1000_SUCCESS;
4576} 4651}
4577 4652
4578/****************************************************************************** 4653/**
4579 * Clears all hardware statistics counters. 4654 * e1000_clear_hw_cntrs - Clears all hardware statistics counters.
4580 * 4655 * @hw: Struct containing variables accessed by shared code
4581 * hw - Struct containing variables accessed by shared code 4656 */
4582 *****************************************************************************/
4583static void e1000_clear_hw_cntrs(struct e1000_hw *hw) 4657static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
4584{ 4658{
4585 volatile u32 temp; 4659 volatile u32 temp;
4586 4660
4587 temp = er32(CRCERRS); 4661 temp = er32(CRCERRS);
4588 temp = er32(SYMERRS); 4662 temp = er32(SYMERRS);
4589 temp = er32(MPC); 4663 temp = er32(MPC);
4590 temp = er32(SCC); 4664 temp = er32(SCC);
4591 temp = er32(ECOL); 4665 temp = er32(ECOL);
4592 temp = er32(MCC); 4666 temp = er32(MCC);
4593 temp = er32(LATECOL); 4667 temp = er32(LATECOL);
4594 temp = er32(COLC); 4668 temp = er32(COLC);
4595 temp = er32(DC); 4669 temp = er32(DC);
4596 temp = er32(SEC); 4670 temp = er32(SEC);
4597 temp = er32(RLEC); 4671 temp = er32(RLEC);
4598 temp = er32(XONRXC); 4672 temp = er32(XONRXC);
4599 temp = er32(XONTXC); 4673 temp = er32(XONTXC);
4600 temp = er32(XOFFRXC); 4674 temp = er32(XOFFRXC);
4601 temp = er32(XOFFTXC); 4675 temp = er32(XOFFTXC);
4602 temp = er32(FCRUC); 4676 temp = er32(FCRUC);
4603 4677
4604 temp = er32(PRC64); 4678 temp = er32(PRC64);
4605 temp = er32(PRC127); 4679 temp = er32(PRC127);
4606 temp = er32(PRC255); 4680 temp = er32(PRC255);
4607 temp = er32(PRC511); 4681 temp = er32(PRC511);
4608 temp = er32(PRC1023); 4682 temp = er32(PRC1023);
4609 temp = er32(PRC1522); 4683 temp = er32(PRC1522);
4610 4684
4611 temp = er32(GPRC); 4685 temp = er32(GPRC);
4612 temp = er32(BPRC); 4686 temp = er32(BPRC);
4613 temp = er32(MPRC); 4687 temp = er32(MPRC);
4614 temp = er32(GPTC); 4688 temp = er32(GPTC);
4615 temp = er32(GORCL); 4689 temp = er32(GORCL);
4616 temp = er32(GORCH); 4690 temp = er32(GORCH);
4617 temp = er32(GOTCL); 4691 temp = er32(GOTCL);
4618 temp = er32(GOTCH); 4692 temp = er32(GOTCH);
4619 temp = er32(RNBC); 4693 temp = er32(RNBC);
4620 temp = er32(RUC); 4694 temp = er32(RUC);
4621 temp = er32(RFC); 4695 temp = er32(RFC);
4622 temp = er32(ROC); 4696 temp = er32(ROC);
4623 temp = er32(RJC); 4697 temp = er32(RJC);
4624 temp = er32(TORL); 4698 temp = er32(TORL);
4625 temp = er32(TORH); 4699 temp = er32(TORH);
4626 temp = er32(TOTL); 4700 temp = er32(TOTL);
4627 temp = er32(TOTH); 4701 temp = er32(TOTH);
4628 temp = er32(TPR); 4702 temp = er32(TPR);
4629 temp = er32(TPT); 4703 temp = er32(TPT);
4630 4704
4631 temp = er32(PTC64); 4705 temp = er32(PTC64);
4632 temp = er32(PTC127); 4706 temp = er32(PTC127);
4633 temp = er32(PTC255); 4707 temp = er32(PTC255);
4634 temp = er32(PTC511); 4708 temp = er32(PTC511);
4635 temp = er32(PTC1023); 4709 temp = er32(PTC1023);
4636 temp = er32(PTC1522); 4710 temp = er32(PTC1522);
4637 4711
4638 temp = er32(MPTC); 4712 temp = er32(MPTC);
4639 temp = er32(BPTC); 4713 temp = er32(BPTC);
4640 4714
4641 if (hw->mac_type < e1000_82543) return; 4715 if (hw->mac_type < e1000_82543)
4642 4716 return;
4643 temp = er32(ALGNERRC); 4717
4644 temp = er32(RXERRC); 4718 temp = er32(ALGNERRC);
4645 temp = er32(TNCRS); 4719 temp = er32(RXERRC);
4646 temp = er32(CEXTERR); 4720 temp = er32(TNCRS);
4647 temp = er32(TSCTC); 4721 temp = er32(CEXTERR);
4648 temp = er32(TSCTFC); 4722 temp = er32(TSCTC);
4649 4723 temp = er32(TSCTFC);
4650 if (hw->mac_type <= e1000_82544) return; 4724
4651 4725 if (hw->mac_type <= e1000_82544)
4652 temp = er32(MGTPRC); 4726 return;
4653 temp = er32(MGTPDC); 4727
4654 temp = er32(MGTPTC); 4728 temp = er32(MGTPRC);
4729 temp = er32(MGTPDC);
4730 temp = er32(MGTPTC);
4655} 4731}
4656 4732
4657/****************************************************************************** 4733/**
4658 * Resets Adaptive IFS to its default state. 4734 * e1000_reset_adaptive - Resets Adaptive IFS to its default state.
4659 * 4735 * @hw: Struct containing variables accessed by shared code
4660 * hw - Struct containing variables accessed by shared code
4661 * 4736 *
4662 * Call this after e1000_init_hw. You may override the IFS defaults by setting 4737 * Call this after e1000_init_hw. You may override the IFS defaults by setting
4663 * hw->ifs_params_forced to true. However, you must initialize hw-> 4738 * hw->ifs_params_forced to true. However, you must initialize hw->
4664 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio 4739 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
4665 * before calling this function. 4740 * before calling this function.
4666 *****************************************************************************/ 4741 */
4667void e1000_reset_adaptive(struct e1000_hw *hw) 4742void e1000_reset_adaptive(struct e1000_hw *hw)
4668{ 4743{
4669 DEBUGFUNC("e1000_reset_adaptive"); 4744 DEBUGFUNC("e1000_reset_adaptive");
4670 4745
4671 if (hw->adaptive_ifs) { 4746 if (hw->adaptive_ifs) {
4672 if (!hw->ifs_params_forced) { 4747 if (!hw->ifs_params_forced) {
4673 hw->current_ifs_val = 0; 4748 hw->current_ifs_val = 0;
4674 hw->ifs_min_val = IFS_MIN; 4749 hw->ifs_min_val = IFS_MIN;
4675 hw->ifs_max_val = IFS_MAX; 4750 hw->ifs_max_val = IFS_MAX;
4676 hw->ifs_step_size = IFS_STEP; 4751 hw->ifs_step_size = IFS_STEP;
4677 hw->ifs_ratio = IFS_RATIO; 4752 hw->ifs_ratio = IFS_RATIO;
4678 } 4753 }
4679 hw->in_ifs_mode = false; 4754 hw->in_ifs_mode = false;
4680 ew32(AIT, 0); 4755 ew32(AIT, 0);
4681 } else { 4756 } else {
4682 DEBUGOUT("Not in Adaptive IFS mode!\n"); 4757 DEBUGOUT("Not in Adaptive IFS mode!\n");
4683 } 4758 }
4684} 4759}
4685 4760
4686/****************************************************************************** 4761/**
4762 * e1000_update_adaptive - update adaptive IFS
4763 * @hw: Struct containing variables accessed by shared code
4764 * @tx_packets: Number of transmits since last callback
4765 * @total_collisions: Number of collisions since last callback
4766 *
4687 * Called during the callback/watchdog routine to update IFS value based on 4767 * Called during the callback/watchdog routine to update IFS value based on
4688 * the ratio of transmits to collisions. 4768 * the ratio of transmits to collisions.
4689 * 4769 */
4690 * hw - Struct containing variables accessed by shared code
4691 * tx_packets - Number of transmits since last callback
4692 * total_collisions - Number of collisions since last callback
4693 *****************************************************************************/
4694void e1000_update_adaptive(struct e1000_hw *hw) 4770void e1000_update_adaptive(struct e1000_hw *hw)
4695{ 4771{
4696 DEBUGFUNC("e1000_update_adaptive"); 4772 DEBUGFUNC("e1000_update_adaptive");
4697 4773
4698 if (hw->adaptive_ifs) { 4774 if (hw->adaptive_ifs) {
4699 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) { 4775 if ((hw->collision_delta *hw->ifs_ratio) > hw->tx_packet_delta) {
4700 if (hw->tx_packet_delta > MIN_NUM_XMITS) { 4776 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
4701 hw->in_ifs_mode = true; 4777 hw->in_ifs_mode = true;
4702 if (hw->current_ifs_val < hw->ifs_max_val) { 4778 if (hw->current_ifs_val < hw->ifs_max_val) {
4703 if (hw->current_ifs_val == 0) 4779 if (hw->current_ifs_val == 0)
4704 hw->current_ifs_val = hw->ifs_min_val; 4780 hw->current_ifs_val =
4705 else 4781 hw->ifs_min_val;
4706 hw->current_ifs_val += hw->ifs_step_size; 4782 else
4707 ew32(AIT, hw->current_ifs_val); 4783 hw->current_ifs_val +=
4708 } 4784 hw->ifs_step_size;
4709 } 4785 ew32(AIT, hw->current_ifs_val);
4710 } else { 4786 }
4711 if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { 4787 }
4712 hw->current_ifs_val = 0; 4788 } else {
4713 hw->in_ifs_mode = false; 4789 if (hw->in_ifs_mode
4714 ew32(AIT, 0); 4790 && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
4715 } 4791 hw->current_ifs_val = 0;
4716 } 4792 hw->in_ifs_mode = false;
4717 } else { 4793 ew32(AIT, 0);
4718 DEBUGOUT("Not in Adaptive IFS mode!\n"); 4794 }
4719 } 4795 }
4796 } else {
4797 DEBUGOUT("Not in Adaptive IFS mode!\n");
4798 }
4720} 4799}
4721 4800
4722/****************************************************************************** 4801/**
4723 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 4802 * e1000_tbi_adjust_stats
4803 * @hw: Struct containing variables accessed by shared code
4804 * @frame_len: The length of the frame in question
4805 * @mac_addr: The Ethernet destination address of the frame in question
4724 * 4806 *
4725 * hw - Struct containing variables accessed by shared code 4807 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
4726 * frame_len - The length of the frame in question 4808 */
4727 * mac_addr - The Ethernet destination address of the frame in question
4728 *****************************************************************************/
4729void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, 4809void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats,
4730 u32 frame_len, u8 *mac_addr) 4810 u32 frame_len, u8 *mac_addr)
4731{ 4811{
4732 u64 carry_bit; 4812 u64 carry_bit;
4733 4813
4734 /* First adjust the frame length. */ 4814 /* First adjust the frame length. */
4735 frame_len--; 4815 frame_len--;
4736 /* We need to adjust the statistics counters, since the hardware 4816 /* We need to adjust the statistics counters, since the hardware
4737 * counters overcount this packet as a CRC error and undercount 4817 * counters overcount this packet as a CRC error and undercount
4738 * the packet as a good packet 4818 * the packet as a good packet
4739 */ 4819 */
4740 /* This packet should not be counted as a CRC error. */ 4820 /* This packet should not be counted as a CRC error. */
4741 stats->crcerrs--; 4821 stats->crcerrs--;
4742 /* This packet does count as a Good Packet Received. */ 4822 /* This packet does count as a Good Packet Received. */
4743 stats->gprc++; 4823 stats->gprc++;
4744 4824
4745 /* Adjust the Good Octets received counters */ 4825 /* Adjust the Good Octets received counters */
4746 carry_bit = 0x80000000 & stats->gorcl; 4826 carry_bit = 0x80000000 & stats->gorcl;
4747 stats->gorcl += frame_len; 4827 stats->gorcl += frame_len;
4748 /* If the high bit of Gorcl (the low 32 bits of the Good Octets 4828 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
4749 * Received Count) was one before the addition, 4829 * Received Count) was one before the addition,
4750 * AND it is zero after, then we lost the carry out, 4830 * AND it is zero after, then we lost the carry out,
4751 * need to add one to Gorch (Good Octets Received Count High). 4831 * need to add one to Gorch (Good Octets Received Count High).
4752 * This could be simplified if all environments supported 4832 * This could be simplified if all environments supported
4753 * 64-bit integers. 4833 * 64-bit integers.
4754 */ 4834 */
4755 if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) 4835 if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
4756 stats->gorch++; 4836 stats->gorch++;
4757 /* Is this a broadcast or multicast? Check broadcast first, 4837 /* Is this a broadcast or multicast? Check broadcast first,
4758 * since the test for a multicast frame will test positive on 4838 * since the test for a multicast frame will test positive on
4759 * a broadcast frame. 4839 * a broadcast frame.
4760 */ 4840 */
4761 if ((mac_addr[0] == (u8)0xff) && (mac_addr[1] == (u8)0xff)) 4841 if ((mac_addr[0] == (u8) 0xff) && (mac_addr[1] == (u8) 0xff))
4762 /* Broadcast packet */ 4842 /* Broadcast packet */
4763 stats->bprc++; 4843 stats->bprc++;
4764 else if (*mac_addr & 0x01) 4844 else if (*mac_addr & 0x01)
4765 /* Multicast packet */ 4845 /* Multicast packet */
4766 stats->mprc++; 4846 stats->mprc++;
4767 4847
4768 if (frame_len == hw->max_frame_size) { 4848 if (frame_len == hw->max_frame_size) {
4769 /* In this case, the hardware has overcounted the number of 4849 /* In this case, the hardware has overcounted the number of
4770 * oversize frames. 4850 * oversize frames.
4771 */ 4851 */
4772 if (stats->roc > 0) 4852 if (stats->roc > 0)
4773 stats->roc--; 4853 stats->roc--;
4774 } 4854 }
4775 4855
4776 /* Adjust the bin counters when the extra byte put the frame in the 4856 /* Adjust the bin counters when the extra byte put the frame in the
4777 * wrong bin. Remember that the frame_len was adjusted above. 4857 * wrong bin. Remember that the frame_len was adjusted above.
4778 */ 4858 */
4779 if (frame_len == 64) { 4859 if (frame_len == 64) {
4780 stats->prc64++; 4860 stats->prc64++;
4781 stats->prc127--; 4861 stats->prc127--;
4782 } else if (frame_len == 127) { 4862 } else if (frame_len == 127) {
4783 stats->prc127++; 4863 stats->prc127++;
4784 stats->prc255--; 4864 stats->prc255--;
4785 } else if (frame_len == 255) { 4865 } else if (frame_len == 255) {
4786 stats->prc255++; 4866 stats->prc255++;
4787 stats->prc511--; 4867 stats->prc511--;
4788 } else if (frame_len == 511) { 4868 } else if (frame_len == 511) {
4789 stats->prc511++; 4869 stats->prc511++;
4790 stats->prc1023--; 4870 stats->prc1023--;
4791 } else if (frame_len == 1023) { 4871 } else if (frame_len == 1023) {
4792 stats->prc1023++; 4872 stats->prc1023++;
4793 stats->prc1522--; 4873 stats->prc1522--;
4794 } else if (frame_len == 1522) { 4874 } else if (frame_len == 1522) {
4795 stats->prc1522++; 4875 stats->prc1522++;
4796 } 4876 }
4797} 4877}
4798 4878
4799/****************************************************************************** 4879/**
4800 * Gets the current PCI bus type, speed, and width of the hardware 4880 * e1000_get_bus_info
4881 * @hw: Struct containing variables accessed by shared code
4801 * 4882 *
4802 * hw - Struct containing variables accessed by shared code 4883 * Gets the current PCI bus type, speed, and width of the hardware
4803 *****************************************************************************/ 4884 */
4804void e1000_get_bus_info(struct e1000_hw *hw) 4885void e1000_get_bus_info(struct e1000_hw *hw)
4805{ 4886{
4806 u32 status; 4887 u32 status;
4807 4888
4808 switch (hw->mac_type) { 4889 switch (hw->mac_type) {
4809 case e1000_82542_rev2_0: 4890 case e1000_82542_rev2_0:
4810 case e1000_82542_rev2_1: 4891 case e1000_82542_rev2_1:
4811 hw->bus_type = e1000_bus_type_pci; 4892 hw->bus_type = e1000_bus_type_pci;
4812 hw->bus_speed = e1000_bus_speed_unknown; 4893 hw->bus_speed = e1000_bus_speed_unknown;
4813 hw->bus_width = e1000_bus_width_unknown; 4894 hw->bus_width = e1000_bus_width_unknown;
4814 break; 4895 break;
4815 default: 4896 default:
4816 status = er32(STATUS); 4897 status = er32(STATUS);
4817 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 4898 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
4818 e1000_bus_type_pcix : e1000_bus_type_pci; 4899 e1000_bus_type_pcix : e1000_bus_type_pci;
4819 4900
4820 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { 4901 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
4821 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? 4902 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
4822 e1000_bus_speed_66 : e1000_bus_speed_120; 4903 e1000_bus_speed_66 : e1000_bus_speed_120;
4823 } else if (hw->bus_type == e1000_bus_type_pci) { 4904 } else if (hw->bus_type == e1000_bus_type_pci) {
4824 hw->bus_speed = (status & E1000_STATUS_PCI66) ? 4905 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
4825 e1000_bus_speed_66 : e1000_bus_speed_33; 4906 e1000_bus_speed_66 : e1000_bus_speed_33;
4826 } else { 4907 } else {
4827 switch (status & E1000_STATUS_PCIX_SPEED) { 4908 switch (status & E1000_STATUS_PCIX_SPEED) {
4828 case E1000_STATUS_PCIX_SPEED_66: 4909 case E1000_STATUS_PCIX_SPEED_66:
4829 hw->bus_speed = e1000_bus_speed_66; 4910 hw->bus_speed = e1000_bus_speed_66;
4830 break; 4911 break;
4831 case E1000_STATUS_PCIX_SPEED_100: 4912 case E1000_STATUS_PCIX_SPEED_100:
4832 hw->bus_speed = e1000_bus_speed_100; 4913 hw->bus_speed = e1000_bus_speed_100;
4833 break; 4914 break;
4834 case E1000_STATUS_PCIX_SPEED_133: 4915 case E1000_STATUS_PCIX_SPEED_133:
4835 hw->bus_speed = e1000_bus_speed_133; 4916 hw->bus_speed = e1000_bus_speed_133;
4836 break; 4917 break;
4837 default: 4918 default:
4838 hw->bus_speed = e1000_bus_speed_reserved; 4919 hw->bus_speed = e1000_bus_speed_reserved;
4839 break; 4920 break;
4840 } 4921 }
4841 } 4922 }
4842 hw->bus_width = (status & E1000_STATUS_BUS64) ? 4923 hw->bus_width = (status & E1000_STATUS_BUS64) ?
4843 e1000_bus_width_64 : e1000_bus_width_32; 4924 e1000_bus_width_64 : e1000_bus_width_32;
4844 break; 4925 break;
4845 } 4926 }
4846} 4927}
4847 4928
4848/****************************************************************************** 4929/**
4930 * e1000_write_reg_io
4931 * @hw: Struct containing variables accessed by shared code
4932 * @offset: offset to write to
4933 * @value: value to write
4934 *
4849 * Writes a value to one of the devices registers using port I/O (as opposed to 4935 * Writes a value to one of the devices registers using port I/O (as opposed to
4850 * memory mapped I/O). Only 82544 and newer devices support port I/O. 4936 * memory mapped I/O). Only 82544 and newer devices support port I/O.
4851 * 4937 */
4852 * hw - Struct containing variables accessed by shared code
4853 * offset - offset to write to
4854 * value - value to write
4855 *****************************************************************************/
4856static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value) 4938static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)
4857{ 4939{
4858 unsigned long io_addr = hw->io_base; 4940 unsigned long io_addr = hw->io_base;
4859 unsigned long io_data = hw->io_base + 4; 4941 unsigned long io_data = hw->io_base + 4;
4860 4942
4861 e1000_io_write(hw, io_addr, offset); 4943 e1000_io_write(hw, io_addr, offset);
4862 e1000_io_write(hw, io_data, value); 4944 e1000_io_write(hw, io_data, value);
4863} 4945}
4864 4946
4865/****************************************************************************** 4947/**
4866 * Estimates the cable length. 4948 * e1000_get_cable_length - Estimates the cable length.
4867 * 4949 * @hw: Struct containing variables accessed by shared code
4868 * hw - Struct containing variables accessed by shared code 4950 * @min_length: The estimated minimum length
4869 * min_length - The estimated minimum length 4951 * @max_length: The estimated maximum length
4870 * max_length - The estimated maximum length
4871 * 4952 *
4872 * returns: - E1000_ERR_XXX 4953 * returns: - E1000_ERR_XXX
4873 * E1000_SUCCESS 4954 * E1000_SUCCESS
@@ -4876,112 +4957,115 @@ static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)
4876 * So for M88 phy's, this function interprets the one value returned from the 4957 * So for M88 phy's, this function interprets the one value returned from the
4877 * register to the minimum and maximum range. 4958 * register to the minimum and maximum range.
4878 * For IGP phy's, the function calculates the range by the AGC registers. 4959 * For IGP phy's, the function calculates the range by the AGC registers.
4879 *****************************************************************************/ 4960 */
4880static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length, 4961static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
4881 u16 *max_length) 4962 u16 *max_length)
4882{ 4963{
4883 s32 ret_val; 4964 s32 ret_val;
4884 u16 agc_value = 0; 4965 u16 agc_value = 0;
4885 u16 i, phy_data; 4966 u16 i, phy_data;
4886 u16 cable_length; 4967 u16 cable_length;
4887 4968
4888 DEBUGFUNC("e1000_get_cable_length"); 4969 DEBUGFUNC("e1000_get_cable_length");
4889 4970
4890 *min_length = *max_length = 0; 4971 *min_length = *max_length = 0;
4891 4972
4892 /* Use old method for Phy older than IGP */ 4973 /* Use old method for Phy older than IGP */
4893 if (hw->phy_type == e1000_phy_m88) { 4974 if (hw->phy_type == e1000_phy_m88) {
4894 4975
4895 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 4976 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4896 &phy_data); 4977 &phy_data);
4897 if (ret_val) 4978 if (ret_val)
4898 return ret_val; 4979 return ret_val;
4899 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 4980 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4900 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 4981 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
4901 4982
4902 /* Convert the enum value to ranged values */ 4983 /* Convert the enum value to ranged values */
4903 switch (cable_length) { 4984 switch (cable_length) {
4904 case e1000_cable_length_50: 4985 case e1000_cable_length_50:
4905 *min_length = 0; 4986 *min_length = 0;
4906 *max_length = e1000_igp_cable_length_50; 4987 *max_length = e1000_igp_cable_length_50;
4907 break; 4988 break;
4908 case e1000_cable_length_50_80: 4989 case e1000_cable_length_50_80:
4909 *min_length = e1000_igp_cable_length_50; 4990 *min_length = e1000_igp_cable_length_50;
4910 *max_length = e1000_igp_cable_length_80; 4991 *max_length = e1000_igp_cable_length_80;
4911 break; 4992 break;
4912 case e1000_cable_length_80_110: 4993 case e1000_cable_length_80_110:
4913 *min_length = e1000_igp_cable_length_80; 4994 *min_length = e1000_igp_cable_length_80;
4914 *max_length = e1000_igp_cable_length_110; 4995 *max_length = e1000_igp_cable_length_110;
4915 break; 4996 break;
4916 case e1000_cable_length_110_140: 4997 case e1000_cable_length_110_140:
4917 *min_length = e1000_igp_cable_length_110; 4998 *min_length = e1000_igp_cable_length_110;
4918 *max_length = e1000_igp_cable_length_140; 4999 *max_length = e1000_igp_cable_length_140;
4919 break; 5000 break;
4920 case e1000_cable_length_140: 5001 case e1000_cable_length_140:
4921 *min_length = e1000_igp_cable_length_140; 5002 *min_length = e1000_igp_cable_length_140;
4922 *max_length = e1000_igp_cable_length_170; 5003 *max_length = e1000_igp_cable_length_170;
4923 break; 5004 break;
4924 default: 5005 default:
4925 return -E1000_ERR_PHY; 5006 return -E1000_ERR_PHY;
4926 break; 5007 break;
4927 } 5008 }
4928 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ 5009 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
4929 u16 cur_agc_value; 5010 u16 cur_agc_value;
4930 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 5011 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
4931 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 5012 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
4932 {IGP01E1000_PHY_AGC_A, 5013 { IGP01E1000_PHY_AGC_A,
4933 IGP01E1000_PHY_AGC_B, 5014 IGP01E1000_PHY_AGC_B,
4934 IGP01E1000_PHY_AGC_C, 5015 IGP01E1000_PHY_AGC_C,
4935 IGP01E1000_PHY_AGC_D}; 5016 IGP01E1000_PHY_AGC_D
4936 /* Read the AGC registers for all channels */ 5017 };
4937 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 5018 /* Read the AGC registers for all channels */
4938 5019 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4939 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); 5020
4940 if (ret_val) 5021 ret_val =
4941 return ret_val; 5022 e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
4942 5023 if (ret_val)
4943 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; 5024 return ret_val;
4944 5025
4945 /* Value bound check. */ 5026 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
4946 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 5027
4947 (cur_agc_value == 0)) 5028 /* Value bound check. */
4948 return -E1000_ERR_PHY; 5029 if ((cur_agc_value >=
4949 5030 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1)
4950 agc_value += cur_agc_value; 5031 || (cur_agc_value == 0))
4951 5032 return -E1000_ERR_PHY;
4952 /* Update minimal AGC value. */ 5033
4953 if (min_agc_value > cur_agc_value) 5034 agc_value += cur_agc_value;
4954 min_agc_value = cur_agc_value; 5035
4955 } 5036 /* Update minimal AGC value. */
4956 5037 if (min_agc_value > cur_agc_value)
4957 /* Remove the minimal AGC result for length < 50m */ 5038 min_agc_value = cur_agc_value;
4958 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { 5039 }
4959 agc_value -= min_agc_value; 5040
4960 5041 /* Remove the minimal AGC result for length < 50m */
4961 /* Get the average length of the remaining 3 channels */ 5042 if (agc_value <
4962 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 5043 IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
4963 } else { 5044 agc_value -= min_agc_value;
4964 /* Get the average length of all the 4 channels. */ 5045
4965 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 5046 /* Get the average length of the remaining 3 channels */
4966 } 5047 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
4967 5048 } else {
4968 /* Set the range of the calculated length. */ 5049 /* Get the average length of all the 4 channels. */
4969 *min_length = ((e1000_igp_cable_length_table[agc_value] - 5050 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
4970 IGP01E1000_AGC_RANGE) > 0) ? 5051 }
4971 (e1000_igp_cable_length_table[agc_value] - 5052
4972 IGP01E1000_AGC_RANGE) : 0; 5053 /* Set the range of the calculated length. */
4973 *max_length = e1000_igp_cable_length_table[agc_value] + 5054 *min_length = ((e1000_igp_cable_length_table[agc_value] -
4974 IGP01E1000_AGC_RANGE; 5055 IGP01E1000_AGC_RANGE) > 0) ?
4975 } 5056 (e1000_igp_cable_length_table[agc_value] -
4976 5057 IGP01E1000_AGC_RANGE) : 0;
4977 return E1000_SUCCESS; 5058 *max_length = e1000_igp_cable_length_table[agc_value] +
5059 IGP01E1000_AGC_RANGE;
5060 }
5061
5062 return E1000_SUCCESS;
4978} 5063}
4979 5064
4980/****************************************************************************** 5065/**
4981 * Check the cable polarity 5066 * e1000_check_polarity - Check the cable polarity
4982 * 5067 * @hw: Struct containing variables accessed by shared code
4983 * hw - Struct containing variables accessed by shared code 5068 * @polarity: output parameter : 0 - Polarity is not reversed
4984 * polarity - output parameter : 0 - Polarity is not reversed
4985 * 1 - Polarity is reversed. 5069 * 1 - Polarity is reversed.
4986 * 5070 *
4987 * returns: - E1000_ERR_XXX 5071 * returns: - E1000_ERR_XXX
@@ -4992,62 +5076,65 @@ static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
4992 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will 5076 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
4993 * return 0. If the link speed is 1000 Mbps the polarity status is in the 5077 * return 0. If the link speed is 1000 Mbps the polarity status is in the
4994 * IGP01E1000_PHY_PCS_INIT_REG. 5078 * IGP01E1000_PHY_PCS_INIT_REG.
4995 *****************************************************************************/ 5079 */
4996static s32 e1000_check_polarity(struct e1000_hw *hw, 5080static s32 e1000_check_polarity(struct e1000_hw *hw,
4997 e1000_rev_polarity *polarity) 5081 e1000_rev_polarity *polarity)
4998{ 5082{
4999 s32 ret_val; 5083 s32 ret_val;
5000 u16 phy_data; 5084 u16 phy_data;
5001 5085
5002 DEBUGFUNC("e1000_check_polarity"); 5086 DEBUGFUNC("e1000_check_polarity");
5003 5087
5004 if (hw->phy_type == e1000_phy_m88) { 5088 if (hw->phy_type == e1000_phy_m88) {
5005 /* return the Polarity bit in the Status register. */ 5089 /* return the Polarity bit in the Status register. */
5006 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 5090 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5007 &phy_data); 5091 &phy_data);
5008 if (ret_val) 5092 if (ret_val)
5009 return ret_val; 5093 return ret_val;
5010 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >> 5094 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
5011 M88E1000_PSSR_REV_POLARITY_SHIFT) ? 5095 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
5012 e1000_rev_polarity_reversed : e1000_rev_polarity_normal; 5096 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
5013 5097
5014 } else if (hw->phy_type == e1000_phy_igp) { 5098 } else if (hw->phy_type == e1000_phy_igp) {
5015 /* Read the Status register to check the speed */ 5099 /* Read the Status register to check the speed */
5016 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, 5100 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
5017 &phy_data); 5101 &phy_data);
5018 if (ret_val) 5102 if (ret_val)
5019 return ret_val; 5103 return ret_val;
5020 5104
5021 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to 5105 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
5022 * find the polarity status */ 5106 * find the polarity status */
5023 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == 5107 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
5024 IGP01E1000_PSSR_SPEED_1000MBPS) { 5108 IGP01E1000_PSSR_SPEED_1000MBPS) {
5025 5109
5026 /* Read the GIG initialization PCS register (0x00B4) */ 5110 /* Read the GIG initialization PCS register (0x00B4) */
5027 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, 5111 ret_val =
5028 &phy_data); 5112 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
5029 if (ret_val) 5113 &phy_data);
5030 return ret_val; 5114 if (ret_val)
5031 5115 return ret_val;
5032 /* Check the polarity bits */ 5116
5033 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 5117 /* Check the polarity bits */
5034 e1000_rev_polarity_reversed : e1000_rev_polarity_normal; 5118 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
5035 } else { 5119 e1000_rev_polarity_reversed :
5036 /* For 10 Mbps, read the polarity bit in the status register. (for 5120 e1000_rev_polarity_normal;
5037 * 100 Mbps this bit is always 0) */ 5121 } else {
5038 *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ? 5122 /* For 10 Mbps, read the polarity bit in the status register. (for
5039 e1000_rev_polarity_reversed : e1000_rev_polarity_normal; 5123 * 100 Mbps this bit is always 0) */
5040 } 5124 *polarity =
5041 } 5125 (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
5042 return E1000_SUCCESS; 5126 e1000_rev_polarity_reversed :
5127 e1000_rev_polarity_normal;
5128 }
5129 }
5130 return E1000_SUCCESS;
5043} 5131}
5044 5132
5045/****************************************************************************** 5133/**
5046 * Check if Downshift occured 5134 * e1000_check_downshift - Check if Downshift occurred
5047 * 5135 * @hw: Struct containing variables accessed by shared code
5048 * hw - Struct containing variables accessed by shared code 5136 * @downshift: output parameter : 0 - No Downshift occurred.
5049 * downshift - output parameter : 0 - No Downshift ocured. 5137 * 1 - Downshift occurred.
5050 * 1 - Downshift ocured.
5051 * 5138 *
5052 * returns: - E1000_ERR_XXX 5139 * returns: - E1000_ERR_XXX
5053 * E1000_SUCCESS 5140 * E1000_SUCCESS
@@ -5056,573 +5143,607 @@ static s32 e1000_check_polarity(struct e1000_hw *hw,
5056 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the 5143 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
5057 * Link Health register. In IGP this bit is latched high, so the driver must 5144 * Link Health register. In IGP this bit is latched high, so the driver must
5058 * read it immediately after link is established. 5145 * read it immediately after link is established.
5059 *****************************************************************************/ 5146 */
5060static s32 e1000_check_downshift(struct e1000_hw *hw) 5147static s32 e1000_check_downshift(struct e1000_hw *hw)
5061{ 5148{
5062 s32 ret_val; 5149 s32 ret_val;
5063 u16 phy_data; 5150 u16 phy_data;
5064 5151
5065 DEBUGFUNC("e1000_check_downshift"); 5152 DEBUGFUNC("e1000_check_downshift");
5066 5153
5067 if (hw->phy_type == e1000_phy_igp) { 5154 if (hw->phy_type == e1000_phy_igp) {
5068 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 5155 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
5069 &phy_data); 5156 &phy_data);
5070 if (ret_val) 5157 if (ret_val)
5071 return ret_val; 5158 return ret_val;
5072 5159
5073 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; 5160 hw->speed_downgraded =
5074 } else if (hw->phy_type == e1000_phy_m88) { 5161 (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
5075 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 5162 } else if (hw->phy_type == e1000_phy_m88) {
5076 &phy_data); 5163 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5077 if (ret_val) 5164 &phy_data);
5078 return ret_val; 5165 if (ret_val)
5079 5166 return ret_val;
5080 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 5167
5081 M88E1000_PSSR_DOWNSHIFT_SHIFT; 5168 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
5082 } 5169 M88E1000_PSSR_DOWNSHIFT_SHIFT;
5170 }
5083 5171
5084 return E1000_SUCCESS; 5172 return E1000_SUCCESS;
5085} 5173}
5086 5174
5087/***************************************************************************** 5175/**
5088 * 5176 * e1000_config_dsp_after_link_change
5089 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 5177 * @hw: Struct containing variables accessed by shared code
5090 * gigabit link is achieved to improve link quality. 5178 * @link_up: was link up at the time this was called
5091 *
5092 * hw: Struct containing variables accessed by shared code
5093 * 5179 *
5094 * returns: - E1000_ERR_PHY if fail to read/write the PHY 5180 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5095 * E1000_SUCCESS at any other case. 5181 * E1000_SUCCESS at any other case.
5096 * 5182 *
5097 ****************************************************************************/ 5183 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
5184 * gigabit link is achieved to improve link quality.
5185 */
5098 5186
5099static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up) 5187static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
5100{ 5188{
5101 s32 ret_val; 5189 s32 ret_val;
5102 u16 phy_data, phy_saved_data, speed, duplex, i; 5190 u16 phy_data, phy_saved_data, speed, duplex, i;
5103 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 5191 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
5104 {IGP01E1000_PHY_AGC_PARAM_A, 5192 { IGP01E1000_PHY_AGC_PARAM_A,
5105 IGP01E1000_PHY_AGC_PARAM_B, 5193 IGP01E1000_PHY_AGC_PARAM_B,
5106 IGP01E1000_PHY_AGC_PARAM_C, 5194 IGP01E1000_PHY_AGC_PARAM_C,
5107 IGP01E1000_PHY_AGC_PARAM_D}; 5195 IGP01E1000_PHY_AGC_PARAM_D
5108 u16 min_length, max_length; 5196 };
5109 5197 u16 min_length, max_length;
5110 DEBUGFUNC("e1000_config_dsp_after_link_change"); 5198
5111 5199 DEBUGFUNC("e1000_config_dsp_after_link_change");
5112 if (hw->phy_type != e1000_phy_igp) 5200
5113 return E1000_SUCCESS; 5201 if (hw->phy_type != e1000_phy_igp)
5114 5202 return E1000_SUCCESS;
5115 if (link_up) { 5203
5116 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 5204 if (link_up) {
5117 if (ret_val) { 5205 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
5118 DEBUGOUT("Error getting link speed and duplex\n"); 5206 if (ret_val) {
5119 return ret_val; 5207 DEBUGOUT("Error getting link speed and duplex\n");
5120 } 5208 return ret_val;
5121 5209 }
5122 if (speed == SPEED_1000) { 5210
5123 5211 if (speed == SPEED_1000) {
5124 ret_val = e1000_get_cable_length(hw, &min_length, &max_length); 5212
5125 if (ret_val) 5213 ret_val =
5126 return ret_val; 5214 e1000_get_cable_length(hw, &min_length,
5127 5215 &max_length);
5128 if ((hw->dsp_config_state == e1000_dsp_config_enabled) && 5216 if (ret_val)
5129 min_length >= e1000_igp_cable_length_50) { 5217 return ret_val;
5130 5218
5131 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 5219 if ((hw->dsp_config_state == e1000_dsp_config_enabled)
5132 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], 5220 && min_length >= e1000_igp_cable_length_50) {
5133 &phy_data); 5221
5134 if (ret_val) 5222 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5135 return ret_val; 5223 ret_val =
5136 5224 e1000_read_phy_reg(hw,
5137 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 5225 dsp_reg_array[i],
5138 5226 &phy_data);
5139 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i], 5227 if (ret_val)
5140 phy_data); 5228 return ret_val;
5141 if (ret_val) 5229
5142 return ret_val; 5230 phy_data &=
5143 } 5231 ~IGP01E1000_PHY_EDAC_MU_INDEX;
5144 hw->dsp_config_state = e1000_dsp_config_activated; 5232
5145 } 5233 ret_val =
5146 5234 e1000_write_phy_reg(hw,
5147 if ((hw->ffe_config_state == e1000_ffe_config_enabled) && 5235 dsp_reg_array
5148 (min_length < e1000_igp_cable_length_50)) { 5236 [i], phy_data);
5149 5237 if (ret_val)
5150 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; 5238 return ret_val;
5151 u32 idle_errs = 0; 5239 }
5152 5240 hw->dsp_config_state =
5153 /* clear previous idle error counts */ 5241 e1000_dsp_config_activated;
5154 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, 5242 }
5155 &phy_data); 5243
5156 if (ret_val) 5244 if ((hw->ffe_config_state == e1000_ffe_config_enabled)
5157 return ret_val; 5245 && (min_length < e1000_igp_cable_length_50)) {
5158 5246
5159 for (i = 0; i < ffe_idle_err_timeout; i++) { 5247 u16 ffe_idle_err_timeout =
5160 udelay(1000); 5248 FFE_IDLE_ERR_COUNT_TIMEOUT_20;
5161 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, 5249 u32 idle_errs = 0;
5162 &phy_data); 5250
5163 if (ret_val) 5251 /* clear previous idle error counts */
5164 return ret_val; 5252 ret_val =
5165 5253 e1000_read_phy_reg(hw, PHY_1000T_STATUS,
5166 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); 5254 &phy_data);
5167 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 5255 if (ret_val)
5168 hw->ffe_config_state = e1000_ffe_config_active; 5256 return ret_val;
5169 5257
5170 ret_val = e1000_write_phy_reg(hw, 5258 for (i = 0; i < ffe_idle_err_timeout; i++) {
5171 IGP01E1000_PHY_DSP_FFE, 5259 udelay(1000);
5172 IGP01E1000_PHY_DSP_FFE_CM_CP); 5260 ret_val =
5173 if (ret_val) 5261 e1000_read_phy_reg(hw,
5174 return ret_val; 5262 PHY_1000T_STATUS,
5175 break; 5263 &phy_data);
5176 } 5264 if (ret_val)
5177 5265 return ret_val;
5178 if (idle_errs) 5266
5179 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100; 5267 idle_errs +=
5180 } 5268 (phy_data &
5181 } 5269 SR_1000T_IDLE_ERROR_CNT);
5182 } 5270 if (idle_errs >
5183 } else { 5271 SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT)
5184 if (hw->dsp_config_state == e1000_dsp_config_activated) { 5272 {
5185 /* Save off the current value of register 0x2F5B to be restored at 5273 hw->ffe_config_state =
5186 * the end of the routines. */ 5274 e1000_ffe_config_active;
5187 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 5275
5188 5276 ret_val =
5189 if (ret_val) 5277 e1000_write_phy_reg(hw,
5190 return ret_val; 5278 IGP01E1000_PHY_DSP_FFE,
5191 5279 IGP01E1000_PHY_DSP_FFE_CM_CP);
5192 /* Disable the PHY transmitter */ 5280 if (ret_val)
5193 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 5281 return ret_val;
5194 5282 break;
5195 if (ret_val) 5283 }
5196 return ret_val; 5284
5197 5285 if (idle_errs)
5198 mdelay(20); 5286 ffe_idle_err_timeout =
5199 5287 FFE_IDLE_ERR_COUNT_TIMEOUT_100;
5200 ret_val = e1000_write_phy_reg(hw, 0x0000, 5288 }
5201 IGP01E1000_IEEE_FORCE_GIGA); 5289 }
5202 if (ret_val) 5290 }
5203 return ret_val; 5291 } else {
5204 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 5292 if (hw->dsp_config_state == e1000_dsp_config_activated) {
5205 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data); 5293 /* Save off the current value of register 0x2F5B to be restored at
5206 if (ret_val) 5294 * the end of the routines. */
5207 return ret_val; 5295 ret_val =
5208 5296 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5209 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 5297
5210 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 5298 if (ret_val)
5211 5299 return ret_val;
5212 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data); 5300
5213 if (ret_val) 5301 /* Disable the PHY transmitter */
5214 return ret_val; 5302 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5215 } 5303
5216 5304 if (ret_val)
5217 ret_val = e1000_write_phy_reg(hw, 0x0000, 5305 return ret_val;
5218 IGP01E1000_IEEE_RESTART_AUTONEG); 5306
5219 if (ret_val) 5307 mdelay(20);
5220 return ret_val; 5308
5221 5309 ret_val = e1000_write_phy_reg(hw, 0x0000,
5222 mdelay(20); 5310 IGP01E1000_IEEE_FORCE_GIGA);
5223 5311 if (ret_val)
5224 /* Now enable the transmitter */ 5312 return ret_val;
5225 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 5313 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5226 5314 ret_val =
5227 if (ret_val) 5315 e1000_read_phy_reg(hw, dsp_reg_array[i],
5228 return ret_val; 5316 &phy_data);
5229 5317 if (ret_val)
5230 hw->dsp_config_state = e1000_dsp_config_enabled; 5318 return ret_val;
5231 } 5319
5232 5320 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5233 if (hw->ffe_config_state == e1000_ffe_config_active) { 5321 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
5234 /* Save off the current value of register 0x2F5B to be restored at 5322
5235 * the end of the routines. */ 5323 ret_val =
5236 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 5324 e1000_write_phy_reg(hw, dsp_reg_array[i],
5237 5325 phy_data);
5238 if (ret_val) 5326 if (ret_val)
5239 return ret_val; 5327 return ret_val;
5240 5328 }
5241 /* Disable the PHY transmitter */ 5329
5242 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); 5330 ret_val = e1000_write_phy_reg(hw, 0x0000,
5243 5331 IGP01E1000_IEEE_RESTART_AUTONEG);
5244 if (ret_val) 5332 if (ret_val)
5245 return ret_val; 5333 return ret_val;
5246 5334
5247 mdelay(20); 5335 mdelay(20);
5248 5336
5249 ret_val = e1000_write_phy_reg(hw, 0x0000, 5337 /* Now enable the transmitter */
5250 IGP01E1000_IEEE_FORCE_GIGA); 5338 ret_val =
5251 if (ret_val) 5339 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5252 return ret_val; 5340
5253 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, 5341 if (ret_val)
5254 IGP01E1000_PHY_DSP_FFE_DEFAULT); 5342 return ret_val;
5255 if (ret_val) 5343
5256 return ret_val; 5344 hw->dsp_config_state = e1000_dsp_config_enabled;
5257 5345 }
5258 ret_val = e1000_write_phy_reg(hw, 0x0000, 5346
5259 IGP01E1000_IEEE_RESTART_AUTONEG); 5347 if (hw->ffe_config_state == e1000_ffe_config_active) {
5260 if (ret_val) 5348 /* Save off the current value of register 0x2F5B to be restored at
5261 return ret_val; 5349 * the end of the routines. */
5262 5350 ret_val =
5263 mdelay(20); 5351 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5264 5352
5265 /* Now enable the transmitter */ 5353 if (ret_val)
5266 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); 5354 return ret_val;
5267 5355
5268 if (ret_val) 5356 /* Disable the PHY transmitter */
5269 return ret_val; 5357 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5270 5358
5271 hw->ffe_config_state = e1000_ffe_config_enabled; 5359 if (ret_val)
5272 } 5360 return ret_val;
5273 } 5361
5274 return E1000_SUCCESS; 5362 mdelay(20);
5363
5364 ret_val = e1000_write_phy_reg(hw, 0x0000,
5365 IGP01E1000_IEEE_FORCE_GIGA);
5366 if (ret_val)
5367 return ret_val;
5368 ret_val =
5369 e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
5370 IGP01E1000_PHY_DSP_FFE_DEFAULT);
5371 if (ret_val)
5372 return ret_val;
5373
5374 ret_val = e1000_write_phy_reg(hw, 0x0000,
5375 IGP01E1000_IEEE_RESTART_AUTONEG);
5376 if (ret_val)
5377 return ret_val;
5378
5379 mdelay(20);
5380
5381 /* Now enable the transmitter */
5382 ret_val =
5383 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5384
5385 if (ret_val)
5386 return ret_val;
5387
5388 hw->ffe_config_state = e1000_ffe_config_enabled;
5389 }
5390 }
5391 return E1000_SUCCESS;
5275} 5392}
5276 5393
5277/***************************************************************************** 5394/**
5278 * Set PHY to class A mode 5395 * e1000_set_phy_mode - Set PHY to class A mode
5396 * @hw: Struct containing variables accessed by shared code
5397 *
5279 * Assumes the following operations will follow to enable the new class mode. 5398 * Assumes the following operations will follow to enable the new class mode.
5280 * 1. Do a PHY soft reset 5399 * 1. Do a PHY soft reset
5281 * 2. Restart auto-negotiation or force link. 5400 * 2. Restart auto-negotiation or force link.
5282 * 5401 */
5283 * hw - Struct containing variables accessed by shared code
5284 ****************************************************************************/
5285static s32 e1000_set_phy_mode(struct e1000_hw *hw) 5402static s32 e1000_set_phy_mode(struct e1000_hw *hw)
5286{ 5403{
5287 s32 ret_val; 5404 s32 ret_val;
5288 u16 eeprom_data; 5405 u16 eeprom_data;
5289 5406
5290 DEBUGFUNC("e1000_set_phy_mode"); 5407 DEBUGFUNC("e1000_set_phy_mode");
5291 5408
5292 if ((hw->mac_type == e1000_82545_rev_3) && 5409 if ((hw->mac_type == e1000_82545_rev_3) &&
5293 (hw->media_type == e1000_media_type_copper)) { 5410 (hw->media_type == e1000_media_type_copper)) {
5294 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data); 5411 ret_val =
5295 if (ret_val) { 5412 e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1,
5296 return ret_val; 5413 &eeprom_data);
5297 } 5414 if (ret_val) {
5298 5415 return ret_val;
5299 if ((eeprom_data != EEPROM_RESERVED_WORD) && 5416 }
5300 (eeprom_data & EEPROM_PHY_CLASS_A)) { 5417
5301 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B); 5418 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
5302 if (ret_val) 5419 (eeprom_data & EEPROM_PHY_CLASS_A)) {
5303 return ret_val; 5420 ret_val =
5304 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104); 5421 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
5305 if (ret_val) 5422 0x000B);
5306 return ret_val; 5423 if (ret_val)
5307 5424 return ret_val;
5308 hw->phy_reset_disable = false; 5425 ret_val =
5309 } 5426 e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
5310 } 5427 0x8104);
5311 5428 if (ret_val)
5312 return E1000_SUCCESS; 5429 return ret_val;
5430
5431 hw->phy_reset_disable = false;
5432 }
5433 }
5434
5435 return E1000_SUCCESS;
5313} 5436}
5314 5437
5315/***************************************************************************** 5438/**
5439 * e1000_set_d3_lplu_state - set d3 link power state
5440 * @hw: Struct containing variables accessed by shared code
5441 * @active: true to enable lplu false to disable lplu.
5316 * 5442 *
5317 * This function sets the lplu state according to the active flag. When 5443 * This function sets the lplu state according to the active flag. When
5318 * activating lplu this function also disables smart speed and vise versa. 5444 * activating lplu this function also disables smart speed and vise versa.
5319 * lplu will not be activated unless the device autonegotiation advertisment 5445 * lplu will not be activated unless the device autonegotiation advertisement
5320 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 5446 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5321 * hw: Struct containing variables accessed by shared code
5322 * active - true to enable lplu false to disable lplu.
5323 * 5447 *
5324 * returns: - E1000_ERR_PHY if fail to read/write the PHY 5448 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5325 * E1000_SUCCESS at any other case. 5449 * E1000_SUCCESS at any other case.
5326 * 5450 */
5327 ****************************************************************************/
5328
5329static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) 5451static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
5330{ 5452{
5331 s32 ret_val; 5453 s32 ret_val;
5332 u16 phy_data; 5454 u16 phy_data;
5333 DEBUGFUNC("e1000_set_d3_lplu_state"); 5455 DEBUGFUNC("e1000_set_d3_lplu_state");
5334 5456
5335 if (hw->phy_type != e1000_phy_igp) 5457 if (hw->phy_type != e1000_phy_igp)
5336 return E1000_SUCCESS; 5458 return E1000_SUCCESS;
5337 5459
5338 /* During driver activity LPLU should not be used or it will attain link 5460 /* During driver activity LPLU should not be used or it will attain link
5339 * from the lowest speeds starting from 10Mbps. The capability is used for 5461 * from the lowest speeds starting from 10Mbps. The capability is used for
5340 * Dx transitions and states */ 5462 * Dx transitions and states */
5341 if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) { 5463 if (hw->mac_type == e1000_82541_rev_2
5342 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 5464 || hw->mac_type == e1000_82547_rev_2) {
5343 if (ret_val) 5465 ret_val =
5344 return ret_val; 5466 e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
5345 } else { 5467 if (ret_val)
5346 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 5468 return ret_val;
5347 if (ret_val) 5469 }
5348 return ret_val; 5470
5349 } 5471 if (!active) {
5350 5472 if (hw->mac_type == e1000_82541_rev_2 ||
5351 if (!active) { 5473 hw->mac_type == e1000_82547_rev_2) {
5352 if (hw->mac_type == e1000_82541_rev_2 || 5474 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5353 hw->mac_type == e1000_82547_rev_2) { 5475 ret_val =
5354 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 5476 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5355 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); 5477 phy_data);
5356 if (ret_val) 5478 if (ret_val)
5357 return ret_val; 5479 return ret_val;
5358 } else { 5480 }
5359 phy_data &= ~IGP02E1000_PM_D3_LPLU; 5481
5360 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 5482 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5361 phy_data); 5483 * Dx states where the power conservation is most important. During
5362 if (ret_val) 5484 * driver activity we should enable SmartSpeed, so performance is
5363 return ret_val; 5485 * maintained. */
5364 } 5486 if (hw->smart_speed == e1000_smart_speed_on) {
5365 5487 ret_val =
5366 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during 5488 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5367 * Dx states where the power conservation is most important. During 5489 &phy_data);
5368 * driver activity we should enable SmartSpeed, so performance is 5490 if (ret_val)
5369 * maintained. */ 5491 return ret_val;
5370 if (hw->smart_speed == e1000_smart_speed_on) { 5492
5371 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5493 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5372 &phy_data); 5494 ret_val =
5373 if (ret_val) 5495 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5374 return ret_val; 5496 phy_data);
5375 5497 if (ret_val)
5376 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 5498 return ret_val;
5377 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5499 } else if (hw->smart_speed == e1000_smart_speed_off) {
5378 phy_data); 5500 ret_val =
5379 if (ret_val) 5501 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5380 return ret_val; 5502 &phy_data);
5381 } else if (hw->smart_speed == e1000_smart_speed_off) { 5503 if (ret_val)
5382 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5504 return ret_val;
5383 &phy_data); 5505
5384 if (ret_val) 5506 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5385 return ret_val; 5507 ret_val =
5386 5508 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5387 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 5509 phy_data);
5388 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 5510 if (ret_val)
5389 phy_data); 5511 return ret_val;
5390 if (ret_val) 5512 }
5391 return ret_val; 5513 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
5392 } 5514 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL)
5393 5515 || (hw->autoneg_advertised ==
5394 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) || 5516 AUTONEG_ADVERTISE_10_100_ALL)) {
5395 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) || 5517
5396 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 5518 if (hw->mac_type == e1000_82541_rev_2 ||
5397 5519 hw->mac_type == e1000_82547_rev_2) {
5398 if (hw->mac_type == e1000_82541_rev_2 || 5520 phy_data |= IGP01E1000_GMII_FLEX_SPD;
5399 hw->mac_type == e1000_82547_rev_2) { 5521 ret_val =
5400 phy_data |= IGP01E1000_GMII_FLEX_SPD; 5522 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5401 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); 5523 phy_data);
5402 if (ret_val) 5524 if (ret_val)
5403 return ret_val; 5525 return ret_val;
5404 } else { 5526 }
5405 phy_data |= IGP02E1000_PM_D3_LPLU; 5527
5406 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 5528 /* When LPLU is enabled we should disable SmartSpeed */
5407 phy_data); 5529 ret_val =
5408 if (ret_val) 5530 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5409 return ret_val; 5531 &phy_data);
5410 } 5532 if (ret_val)
5411 5533 return ret_val;
5412 /* When LPLU is enabled we should disable SmartSpeed */ 5534
5413 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); 5535 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5414 if (ret_val) 5536 ret_val =
5415 return ret_val; 5537 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5416 5538 phy_data);
5417 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 5539 if (ret_val)
5418 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); 5540 return ret_val;
5419 if (ret_val) 5541
5420 return ret_val; 5542 }
5421 5543 return E1000_SUCCESS;
5422 }
5423 return E1000_SUCCESS;
5424} 5544}
5425 5545
5426/****************************************************************************** 5546/**
5427 * Change VCO speed register to improve Bit Error Rate performance of SERDES. 5547 * e1000_set_vco_speed
5548 * @hw: Struct containing variables accessed by shared code
5428 * 5549 *
5429 * hw - Struct containing variables accessed by shared code 5550 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
5430 *****************************************************************************/ 5551 */
5431static s32 e1000_set_vco_speed(struct e1000_hw *hw) 5552static s32 e1000_set_vco_speed(struct e1000_hw *hw)
5432{ 5553{
5433 s32 ret_val; 5554 s32 ret_val;
5434 u16 default_page = 0; 5555 u16 default_page = 0;
5435 u16 phy_data; 5556 u16 phy_data;
5436 5557
5437 DEBUGFUNC("e1000_set_vco_speed"); 5558 DEBUGFUNC("e1000_set_vco_speed");
5438 5559
5439 switch (hw->mac_type) { 5560 switch (hw->mac_type) {
5440 case e1000_82545_rev_3: 5561 case e1000_82545_rev_3:
5441 case e1000_82546_rev_3: 5562 case e1000_82546_rev_3:
5442 break; 5563 break;
5443 default: 5564 default:
5444 return E1000_SUCCESS; 5565 return E1000_SUCCESS;
5445 } 5566 }
5446 5567
5447 /* Set PHY register 30, page 5, bit 8 to 0 */ 5568 /* Set PHY register 30, page 5, bit 8 to 0 */
5448 5569
5449 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); 5570 ret_val =
5450 if (ret_val) 5571 e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
5451 return ret_val; 5572 if (ret_val)
5573 return ret_val;
5452 5574
5453 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); 5575 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
5454 if (ret_val) 5576 if (ret_val)
5455 return ret_val; 5577 return ret_val;
5456 5578
5457 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 5579 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5458 if (ret_val) 5580 if (ret_val)
5459 return ret_val; 5581 return ret_val;
5460 5582
5461 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; 5583 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
5462 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 5584 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5463 if (ret_val) 5585 if (ret_val)
5464 return ret_val; 5586 return ret_val;
5465 5587
5466 /* Set PHY register 30, page 4, bit 11 to 1 */ 5588 /* Set PHY register 30, page 4, bit 11 to 1 */
5467 5589
5468 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); 5590 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
5469 if (ret_val) 5591 if (ret_val)
5470 return ret_val; 5592 return ret_val;
5471 5593
5472 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 5594 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5473 if (ret_val) 5595 if (ret_val)
5474 return ret_val; 5596 return ret_val;
5475 5597
5476 phy_data |= M88E1000_PHY_VCO_REG_BIT11; 5598 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
5477 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 5599 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5478 if (ret_val) 5600 if (ret_val)
5479 return ret_val; 5601 return ret_val;
5480 5602
5481 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); 5603 ret_val =
5482 if (ret_val) 5604 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
5483 return ret_val; 5605 if (ret_val)
5606 return ret_val;
5484 5607
5485 return E1000_SUCCESS; 5608 return E1000_SUCCESS;
5486} 5609}
5487 5610
5488 5611
5489/****************************************************************************** 5612/**
5490 * Verifies the hardware needs to allow ARPs to be processed by the host 5613 * e1000_enable_mng_pass_thru - check for bmc pass through
5491 * 5614 * @hw: Struct containing variables accessed by shared code
5492 * hw - Struct containing variables accessed by shared code
5493 * 5615 *
5616 * Verifies the hardware needs to allow ARPs to be processed by the host
5494 * returns: - true/false 5617 * returns: - true/false
5495 * 5618 */
5496 *****************************************************************************/
5497u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw) 5619u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
5498{ 5620{
5499 u32 manc; 5621 u32 manc;
5500 5622
5501 if (hw->asf_firmware_present) { 5623 if (hw->asf_firmware_present) {
5502 manc = er32(MANC); 5624 manc = er32(MANC);
5503 5625
5504 if (!(manc & E1000_MANC_RCV_TCO_EN) || 5626 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
5505 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) 5627 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
5506 return false; 5628 return false;
5507 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) 5629 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
5508 return true; 5630 return true;
5509 } 5631 }
5510 return false; 5632 return false;
5511} 5633}
5512 5634
5513static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw) 5635static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
5514{ 5636{
5515 s32 ret_val; 5637 s32 ret_val;
5516 u16 mii_status_reg; 5638 u16 mii_status_reg;
5517 u16 i; 5639 u16 i;
5518 5640
5519 /* Polarity reversal workaround for forced 10F/10H links. */ 5641 /* Polarity reversal workaround for forced 10F/10H links. */
5520 5642
5521 /* Disable the transmitter on the PHY */ 5643 /* Disable the transmitter on the PHY */
5522 5644
5523 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 5645 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5524 if (ret_val) 5646 if (ret_val)
5525 return ret_val; 5647 return ret_val;
5526 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 5648 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
5527 if (ret_val) 5649 if (ret_val)
5528 return ret_val; 5650 return ret_val;
5529 5651
5530 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 5652 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5531 if (ret_val) 5653 if (ret_val)
5532 return ret_val; 5654 return ret_val;
5533 5655
5534 /* This loop will early-out if the NO link condition has been met. */ 5656 /* This loop will early-out if the NO link condition has been met. */
5535 for (i = PHY_FORCE_TIME; i > 0; i--) { 5657 for (i = PHY_FORCE_TIME; i > 0; i--) {
5536 /* Read the MII Status Register and wait for Link Status bit 5658 /* Read the MII Status Register and wait for Link Status bit
5537 * to be clear. 5659 * to be clear.
5538 */ 5660 */
5539 5661
5540 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 5662 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5541 if (ret_val) 5663 if (ret_val)
5542 return ret_val; 5664 return ret_val;
5543 5665
5544 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 5666 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5545 if (ret_val) 5667 if (ret_val)
5546 return ret_val; 5668 return ret_val;
5547 5669
5548 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break; 5670 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
5549 mdelay(100); 5671 break;
5550 } 5672 mdelay(100);
5551 5673 }
5552 /* Recommended delay time after link has been lost */ 5674
5553 mdelay(1000); 5675 /* Recommended delay time after link has been lost */
5554 5676 mdelay(1000);
5555 /* Now we will re-enable th transmitter on the PHY */ 5677
5556 5678 /* Now we will re-enable th transmitter on the PHY */
5557 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 5679
5558 if (ret_val) 5680 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5559 return ret_val; 5681 if (ret_val)
5560 mdelay(50); 5682 return ret_val;
5561 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 5683 mdelay(50);
5562 if (ret_val) 5684 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
5563 return ret_val; 5685 if (ret_val)
5564 mdelay(50); 5686 return ret_val;
5565 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 5687 mdelay(50);
5566 if (ret_val) 5688 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
5567 return ret_val; 5689 if (ret_val)
5568 mdelay(50); 5690 return ret_val;
5569 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 5691 mdelay(50);
5570 if (ret_val) 5692 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
5571 return ret_val; 5693 if (ret_val)
5572 5694 return ret_val;
5573 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 5695
5574 if (ret_val) 5696 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5575 return ret_val; 5697 if (ret_val)
5576 5698 return ret_val;
5577 /* This loop will early-out if the link condition has been met. */ 5699
5578 for (i = PHY_FORCE_TIME; i > 0; i--) { 5700 /* This loop will early-out if the link condition has been met. */
5579 /* Read the MII Status Register and wait for Link Status bit 5701 for (i = PHY_FORCE_TIME; i > 0; i--) {
5580 * to be set. 5702 /* Read the MII Status Register and wait for Link Status bit
5581 */ 5703 * to be set.
5582 5704 */
5583 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 5705
5584 if (ret_val) 5706 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5585 return ret_val; 5707 if (ret_val)
5586 5708 return ret_val;
5587 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 5709
5588 if (ret_val) 5710 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5589 return ret_val; 5711 if (ret_val)
5590 5712 return ret_val;
5591 if (mii_status_reg & MII_SR_LINK_STATUS) break; 5713
5592 mdelay(100); 5714 if (mii_status_reg & MII_SR_LINK_STATUS)
5593 } 5715 break;
5594 return E1000_SUCCESS; 5716 mdelay(100);
5717 }
5718 return E1000_SUCCESS;
5595} 5719}
5596 5720
5597/******************************************************************************* 5721/**
5722 * e1000_get_auto_rd_done
5723 * @hw: Struct containing variables accessed by shared code
5598 * 5724 *
5599 * Check for EEPROM Auto Read bit done. 5725 * Check for EEPROM Auto Read bit done.
5600 *
5601 * hw: Struct containing variables accessed by shared code
5602 *
5603 * returns: - E1000_ERR_RESET if fail to reset MAC 5726 * returns: - E1000_ERR_RESET if fail to reset MAC
5604 * E1000_SUCCESS at any other case. 5727 * E1000_SUCCESS at any other case.
5605 * 5728 */
5606 ******************************************************************************/
5607static s32 e1000_get_auto_rd_done(struct e1000_hw *hw) 5729static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
5608{ 5730{
5609 DEBUGFUNC("e1000_get_auto_rd_done"); 5731 DEBUGFUNC("e1000_get_auto_rd_done");
5610 msleep(5); 5732 msleep(5);
5611 return E1000_SUCCESS; 5733 return E1000_SUCCESS;
5612} 5734}
5613 5735
5614/*************************************************************************** 5736/**
5615 * Checks if the PHY configuration is done 5737 * e1000_get_phy_cfg_done
5616 * 5738 * @hw: Struct containing variables accessed by shared code
5617 * hw: Struct containing variables accessed by shared code
5618 * 5739 *
5740 * Checks if the PHY configuration is done
5619 * returns: - E1000_ERR_RESET if fail to reset MAC 5741 * returns: - E1000_ERR_RESET if fail to reset MAC
5620 * E1000_SUCCESS at any other case. 5742 * E1000_SUCCESS at any other case.
5621 * 5743 */
5622 ***************************************************************************/
5623static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) 5744static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
5624{ 5745{
5625 DEBUGFUNC("e1000_get_phy_cfg_done"); 5746 DEBUGFUNC("e1000_get_phy_cfg_done");
5626 mdelay(10); 5747 mdelay(10);
5627 return E1000_SUCCESS; 5748 return E1000_SUCCESS;
5628} 5749}
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h
index 1c782d2ff04e..4bfdf323b589 100644
--- a/drivers/net/e1000/e1000_hw.h
+++ b/drivers/net/e1000/e1000_hw.h
@@ -35,7 +35,6 @@
35 35
36#include "e1000_osdep.h" 36#include "e1000_osdep.h"
37 37
38
39/* Forward declarations of structures used by the shared code */ 38/* Forward declarations of structures used by the shared code */
40struct e1000_hw; 39struct e1000_hw;
41struct e1000_hw_stats; 40struct e1000_hw_stats;
@@ -43,169 +42,169 @@ struct e1000_hw_stats;
43/* Enumerated types specific to the e1000 hardware */ 42/* Enumerated types specific to the e1000 hardware */
44/* Media Access Controlers */ 43/* Media Access Controlers */
45typedef enum { 44typedef enum {
46 e1000_undefined = 0, 45 e1000_undefined = 0,
47 e1000_82542_rev2_0, 46 e1000_82542_rev2_0,
48 e1000_82542_rev2_1, 47 e1000_82542_rev2_1,
49 e1000_82543, 48 e1000_82543,
50 e1000_82544, 49 e1000_82544,
51 e1000_82540, 50 e1000_82540,
52 e1000_82545, 51 e1000_82545,
53 e1000_82545_rev_3, 52 e1000_82545_rev_3,
54 e1000_82546, 53 e1000_82546,
55 e1000_82546_rev_3, 54 e1000_82546_rev_3,
56 e1000_82541, 55 e1000_82541,
57 e1000_82541_rev_2, 56 e1000_82541_rev_2,
58 e1000_82547, 57 e1000_82547,
59 e1000_82547_rev_2, 58 e1000_82547_rev_2,
60 e1000_num_macs 59 e1000_num_macs
61} e1000_mac_type; 60} e1000_mac_type;
62 61
63typedef enum { 62typedef enum {
64 e1000_eeprom_uninitialized = 0, 63 e1000_eeprom_uninitialized = 0,
65 e1000_eeprom_spi, 64 e1000_eeprom_spi,
66 e1000_eeprom_microwire, 65 e1000_eeprom_microwire,
67 e1000_eeprom_flash, 66 e1000_eeprom_flash,
68 e1000_eeprom_none, /* No NVM support */ 67 e1000_eeprom_none, /* No NVM support */
69 e1000_num_eeprom_types 68 e1000_num_eeprom_types
70} e1000_eeprom_type; 69} e1000_eeprom_type;
71 70
72/* Media Types */ 71/* Media Types */
73typedef enum { 72typedef enum {
74 e1000_media_type_copper = 0, 73 e1000_media_type_copper = 0,
75 e1000_media_type_fiber = 1, 74 e1000_media_type_fiber = 1,
76 e1000_media_type_internal_serdes = 2, 75 e1000_media_type_internal_serdes = 2,
77 e1000_num_media_types 76 e1000_num_media_types
78} e1000_media_type; 77} e1000_media_type;
79 78
80typedef enum { 79typedef enum {
81 e1000_10_half = 0, 80 e1000_10_half = 0,
82 e1000_10_full = 1, 81 e1000_10_full = 1,
83 e1000_100_half = 2, 82 e1000_100_half = 2,
84 e1000_100_full = 3 83 e1000_100_full = 3
85} e1000_speed_duplex_type; 84} e1000_speed_duplex_type;
86 85
87/* Flow Control Settings */ 86/* Flow Control Settings */
88typedef enum { 87typedef enum {
89 E1000_FC_NONE = 0, 88 E1000_FC_NONE = 0,
90 E1000_FC_RX_PAUSE = 1, 89 E1000_FC_RX_PAUSE = 1,
91 E1000_FC_TX_PAUSE = 2, 90 E1000_FC_TX_PAUSE = 2,
92 E1000_FC_FULL = 3, 91 E1000_FC_FULL = 3,
93 E1000_FC_DEFAULT = 0xFF 92 E1000_FC_DEFAULT = 0xFF
94} e1000_fc_type; 93} e1000_fc_type;
95 94
96struct e1000_shadow_ram { 95struct e1000_shadow_ram {
97 u16 eeprom_word; 96 u16 eeprom_word;
98 bool modified; 97 bool modified;
99}; 98};
100 99
101/* PCI bus types */ 100/* PCI bus types */
102typedef enum { 101typedef enum {
103 e1000_bus_type_unknown = 0, 102 e1000_bus_type_unknown = 0,
104 e1000_bus_type_pci, 103 e1000_bus_type_pci,
105 e1000_bus_type_pcix, 104 e1000_bus_type_pcix,
106 e1000_bus_type_reserved 105 e1000_bus_type_reserved
107} e1000_bus_type; 106} e1000_bus_type;
108 107
109/* PCI bus speeds */ 108/* PCI bus speeds */
110typedef enum { 109typedef enum {
111 e1000_bus_speed_unknown = 0, 110 e1000_bus_speed_unknown = 0,
112 e1000_bus_speed_33, 111 e1000_bus_speed_33,
113 e1000_bus_speed_66, 112 e1000_bus_speed_66,
114 e1000_bus_speed_100, 113 e1000_bus_speed_100,
115 e1000_bus_speed_120, 114 e1000_bus_speed_120,
116 e1000_bus_speed_133, 115 e1000_bus_speed_133,
117 e1000_bus_speed_reserved 116 e1000_bus_speed_reserved
118} e1000_bus_speed; 117} e1000_bus_speed;
119 118
120/* PCI bus widths */ 119/* PCI bus widths */
121typedef enum { 120typedef enum {
122 e1000_bus_width_unknown = 0, 121 e1000_bus_width_unknown = 0,
123 e1000_bus_width_32, 122 e1000_bus_width_32,
124 e1000_bus_width_64, 123 e1000_bus_width_64,
125 e1000_bus_width_reserved 124 e1000_bus_width_reserved
126} e1000_bus_width; 125} e1000_bus_width;
127 126
128/* PHY status info structure and supporting enums */ 127/* PHY status info structure and supporting enums */
129typedef enum { 128typedef enum {
130 e1000_cable_length_50 = 0, 129 e1000_cable_length_50 = 0,
131 e1000_cable_length_50_80, 130 e1000_cable_length_50_80,
132 e1000_cable_length_80_110, 131 e1000_cable_length_80_110,
133 e1000_cable_length_110_140, 132 e1000_cable_length_110_140,
134 e1000_cable_length_140, 133 e1000_cable_length_140,
135 e1000_cable_length_undefined = 0xFF 134 e1000_cable_length_undefined = 0xFF
136} e1000_cable_length; 135} e1000_cable_length;
137 136
138typedef enum { 137typedef enum {
139 e1000_gg_cable_length_60 = 0, 138 e1000_gg_cable_length_60 = 0,
140 e1000_gg_cable_length_60_115 = 1, 139 e1000_gg_cable_length_60_115 = 1,
141 e1000_gg_cable_length_115_150 = 2, 140 e1000_gg_cable_length_115_150 = 2,
142 e1000_gg_cable_length_150 = 4 141 e1000_gg_cable_length_150 = 4
143} e1000_gg_cable_length; 142} e1000_gg_cable_length;
144 143
145typedef enum { 144typedef enum {
146 e1000_igp_cable_length_10 = 10, 145 e1000_igp_cable_length_10 = 10,
147 e1000_igp_cable_length_20 = 20, 146 e1000_igp_cable_length_20 = 20,
148 e1000_igp_cable_length_30 = 30, 147 e1000_igp_cable_length_30 = 30,
149 e1000_igp_cable_length_40 = 40, 148 e1000_igp_cable_length_40 = 40,
150 e1000_igp_cable_length_50 = 50, 149 e1000_igp_cable_length_50 = 50,
151 e1000_igp_cable_length_60 = 60, 150 e1000_igp_cable_length_60 = 60,
152 e1000_igp_cable_length_70 = 70, 151 e1000_igp_cable_length_70 = 70,
153 e1000_igp_cable_length_80 = 80, 152 e1000_igp_cable_length_80 = 80,
154 e1000_igp_cable_length_90 = 90, 153 e1000_igp_cable_length_90 = 90,
155 e1000_igp_cable_length_100 = 100, 154 e1000_igp_cable_length_100 = 100,
156 e1000_igp_cable_length_110 = 110, 155 e1000_igp_cable_length_110 = 110,
157 e1000_igp_cable_length_115 = 115, 156 e1000_igp_cable_length_115 = 115,
158 e1000_igp_cable_length_120 = 120, 157 e1000_igp_cable_length_120 = 120,
159 e1000_igp_cable_length_130 = 130, 158 e1000_igp_cable_length_130 = 130,
160 e1000_igp_cable_length_140 = 140, 159 e1000_igp_cable_length_140 = 140,
161 e1000_igp_cable_length_150 = 150, 160 e1000_igp_cable_length_150 = 150,
162 e1000_igp_cable_length_160 = 160, 161 e1000_igp_cable_length_160 = 160,
163 e1000_igp_cable_length_170 = 170, 162 e1000_igp_cable_length_170 = 170,
164 e1000_igp_cable_length_180 = 180 163 e1000_igp_cable_length_180 = 180
165} e1000_igp_cable_length; 164} e1000_igp_cable_length;
166 165
167typedef enum { 166typedef enum {
168 e1000_10bt_ext_dist_enable_normal = 0, 167 e1000_10bt_ext_dist_enable_normal = 0,
169 e1000_10bt_ext_dist_enable_lower, 168 e1000_10bt_ext_dist_enable_lower,
170 e1000_10bt_ext_dist_enable_undefined = 0xFF 169 e1000_10bt_ext_dist_enable_undefined = 0xFF
171} e1000_10bt_ext_dist_enable; 170} e1000_10bt_ext_dist_enable;
172 171
173typedef enum { 172typedef enum {
174 e1000_rev_polarity_normal = 0, 173 e1000_rev_polarity_normal = 0,
175 e1000_rev_polarity_reversed, 174 e1000_rev_polarity_reversed,
176 e1000_rev_polarity_undefined = 0xFF 175 e1000_rev_polarity_undefined = 0xFF
177} e1000_rev_polarity; 176} e1000_rev_polarity;
178 177
179typedef enum { 178typedef enum {
180 e1000_downshift_normal = 0, 179 e1000_downshift_normal = 0,
181 e1000_downshift_activated, 180 e1000_downshift_activated,
182 e1000_downshift_undefined = 0xFF 181 e1000_downshift_undefined = 0xFF
183} e1000_downshift; 182} e1000_downshift;
184 183
185typedef enum { 184typedef enum {
186 e1000_smart_speed_default = 0, 185 e1000_smart_speed_default = 0,
187 e1000_smart_speed_on, 186 e1000_smart_speed_on,
188 e1000_smart_speed_off 187 e1000_smart_speed_off
189} e1000_smart_speed; 188} e1000_smart_speed;
190 189
191typedef enum { 190typedef enum {
192 e1000_polarity_reversal_enabled = 0, 191 e1000_polarity_reversal_enabled = 0,
193 e1000_polarity_reversal_disabled, 192 e1000_polarity_reversal_disabled,
194 e1000_polarity_reversal_undefined = 0xFF 193 e1000_polarity_reversal_undefined = 0xFF
195} e1000_polarity_reversal; 194} e1000_polarity_reversal;
196 195
197typedef enum { 196typedef enum {
198 e1000_auto_x_mode_manual_mdi = 0, 197 e1000_auto_x_mode_manual_mdi = 0,
199 e1000_auto_x_mode_manual_mdix, 198 e1000_auto_x_mode_manual_mdix,
200 e1000_auto_x_mode_auto1, 199 e1000_auto_x_mode_auto1,
201 e1000_auto_x_mode_auto2, 200 e1000_auto_x_mode_auto2,
202 e1000_auto_x_mode_undefined = 0xFF 201 e1000_auto_x_mode_undefined = 0xFF
203} e1000_auto_x_mode; 202} e1000_auto_x_mode;
204 203
205typedef enum { 204typedef enum {
206 e1000_1000t_rx_status_not_ok = 0, 205 e1000_1000t_rx_status_not_ok = 0,
207 e1000_1000t_rx_status_ok, 206 e1000_1000t_rx_status_ok,
208 e1000_1000t_rx_status_undefined = 0xFF 207 e1000_1000t_rx_status_undefined = 0xFF
209} e1000_1000t_rx_status; 208} e1000_1000t_rx_status;
210 209
211typedef enum { 210typedef enum {
@@ -215,63 +214,61 @@ typedef enum {
215} e1000_phy_type; 214} e1000_phy_type;
216 215
217typedef enum { 216typedef enum {
218 e1000_ms_hw_default = 0, 217 e1000_ms_hw_default = 0,
219 e1000_ms_force_master, 218 e1000_ms_force_master,
220 e1000_ms_force_slave, 219 e1000_ms_force_slave,
221 e1000_ms_auto 220 e1000_ms_auto
222} e1000_ms_type; 221} e1000_ms_type;
223 222
224typedef enum { 223typedef enum {
225 e1000_ffe_config_enabled = 0, 224 e1000_ffe_config_enabled = 0,
226 e1000_ffe_config_active, 225 e1000_ffe_config_active,
227 e1000_ffe_config_blocked 226 e1000_ffe_config_blocked
228} e1000_ffe_config; 227} e1000_ffe_config;
229 228
230typedef enum { 229typedef enum {
231 e1000_dsp_config_disabled = 0, 230 e1000_dsp_config_disabled = 0,
232 e1000_dsp_config_enabled, 231 e1000_dsp_config_enabled,
233 e1000_dsp_config_activated, 232 e1000_dsp_config_activated,
234 e1000_dsp_config_undefined = 0xFF 233 e1000_dsp_config_undefined = 0xFF
235} e1000_dsp_config; 234} e1000_dsp_config;
236 235
237struct e1000_phy_info { 236struct e1000_phy_info {
238 e1000_cable_length cable_length; 237 e1000_cable_length cable_length;
239 e1000_10bt_ext_dist_enable extended_10bt_distance; 238 e1000_10bt_ext_dist_enable extended_10bt_distance;
240 e1000_rev_polarity cable_polarity; 239 e1000_rev_polarity cable_polarity;
241 e1000_downshift downshift; 240 e1000_downshift downshift;
242 e1000_polarity_reversal polarity_correction; 241 e1000_polarity_reversal polarity_correction;
243 e1000_auto_x_mode mdix_mode; 242 e1000_auto_x_mode mdix_mode;
244 e1000_1000t_rx_status local_rx; 243 e1000_1000t_rx_status local_rx;
245 e1000_1000t_rx_status remote_rx; 244 e1000_1000t_rx_status remote_rx;
246}; 245};
247 246
248struct e1000_phy_stats { 247struct e1000_phy_stats {
249 u32 idle_errors; 248 u32 idle_errors;
250 u32 receive_errors; 249 u32 receive_errors;
251}; 250};
252 251
253struct e1000_eeprom_info { 252struct e1000_eeprom_info {
254 e1000_eeprom_type type; 253 e1000_eeprom_type type;
255 u16 word_size; 254 u16 word_size;
256 u16 opcode_bits; 255 u16 opcode_bits;
257 u16 address_bits; 256 u16 address_bits;
258 u16 delay_usec; 257 u16 delay_usec;
259 u16 page_size; 258 u16 page_size;
260 bool use_eerd; 259 bool use_eerd;
261 bool use_eewr; 260 bool use_eewr;
262}; 261};
263 262
264/* Flex ASF Information */ 263/* Flex ASF Information */
265#define E1000_HOST_IF_MAX_SIZE 2048 264#define E1000_HOST_IF_MAX_SIZE 2048
266 265
267typedef enum { 266typedef enum {
268 e1000_byte_align = 0, 267 e1000_byte_align = 0,
269 e1000_word_align = 1, 268 e1000_word_align = 1,
270 e1000_dword_align = 2 269 e1000_dword_align = 2
271} e1000_align_type; 270} e1000_align_type;
272 271
273
274
275/* Error Codes */ 272/* Error Codes */
276#define E1000_SUCCESS 0 273#define E1000_SUCCESS 0
277#define E1000_ERR_EEPROM 1 274#define E1000_ERR_EEPROM 1
@@ -300,11 +297,11 @@ s32 e1000_setup_link(struct e1000_hw *hw);
300s32 e1000_phy_setup_autoneg(struct e1000_hw *hw); 297s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);
301void e1000_config_collision_dist(struct e1000_hw *hw); 298void e1000_config_collision_dist(struct e1000_hw *hw);
302s32 e1000_check_for_link(struct e1000_hw *hw); 299s32 e1000_check_for_link(struct e1000_hw *hw);
303s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex); 300s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 * speed, u16 * duplex);
304s32 e1000_force_mac_fc(struct e1000_hw *hw); 301s32 e1000_force_mac_fc(struct e1000_hw *hw);
305 302
306/* PHY */ 303/* PHY */
307s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data); 304s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 * phy_data);
308s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 data); 305s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 data);
309s32 e1000_phy_hw_reset(struct e1000_hw *hw); 306s32 e1000_phy_hw_reset(struct e1000_hw *hw);
310s32 e1000_phy_reset(struct e1000_hw *hw); 307s32 e1000_phy_reset(struct e1000_hw *hw);
@@ -318,64 +315,64 @@ s32 e1000_init_eeprom_params(struct e1000_hw *hw);
318u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw); 315u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw);
319 316
320#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 317#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
321#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */ 318#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */
322 319
323#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */ 320#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */
324#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */ 321#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */
325#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */ 322#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */
326#define E1000_MNG_IAMT_MODE 0x3 323#define E1000_MNG_IAMT_MODE 0x3
327#define E1000_MNG_ICH_IAMT_MODE 0x2 324#define E1000_MNG_ICH_IAMT_MODE 0x2
328#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */ 325#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */
329 326
330#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */ 327#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */
331#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2 /* DHCP parsing enabled */ 328#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2 /* DHCP parsing enabled */
332#define E1000_VFTA_ENTRY_SHIFT 0x5 329#define E1000_VFTA_ENTRY_SHIFT 0x5
333#define E1000_VFTA_ENTRY_MASK 0x7F 330#define E1000_VFTA_ENTRY_MASK 0x7F
334#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 331#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
335 332
336struct e1000_host_mng_command_header { 333struct e1000_host_mng_command_header {
337 u8 command_id; 334 u8 command_id;
338 u8 checksum; 335 u8 checksum;
339 u16 reserved1; 336 u16 reserved1;
340 u16 reserved2; 337 u16 reserved2;
341 u16 command_length; 338 u16 command_length;
342}; 339};
343 340
344struct e1000_host_mng_command_info { 341struct e1000_host_mng_command_info {
345 struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ 342 struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
346 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658*/ 343 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658 */
347}; 344};
348#ifdef __BIG_ENDIAN 345#ifdef __BIG_ENDIAN
349struct e1000_host_mng_dhcp_cookie{ 346struct e1000_host_mng_dhcp_cookie {
350 u32 signature; 347 u32 signature;
351 u16 vlan_id; 348 u16 vlan_id;
352 u8 reserved0; 349 u8 reserved0;
353 u8 status; 350 u8 status;
354 u32 reserved1; 351 u32 reserved1;
355 u8 checksum; 352 u8 checksum;
356 u8 reserved3; 353 u8 reserved3;
357 u16 reserved2; 354 u16 reserved2;
358}; 355};
359#else 356#else
360struct e1000_host_mng_dhcp_cookie{ 357struct e1000_host_mng_dhcp_cookie {
361 u32 signature; 358 u32 signature;
362 u8 status; 359 u8 status;
363 u8 reserved0; 360 u8 reserved0;
364 u16 vlan_id; 361 u16 vlan_id;
365 u32 reserved1; 362 u32 reserved1;
366 u16 reserved2; 363 u16 reserved2;
367 u8 reserved3; 364 u8 reserved3;
368 u8 checksum; 365 u8 checksum;
369}; 366};
370#endif 367#endif
371 368
372bool e1000_check_mng_mode(struct e1000_hw *hw); 369bool e1000_check_mng_mode(struct e1000_hw *hw);
373bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw); 370bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw);
374s32 e1000_read_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 *data); 371s32 e1000_read_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data);
375s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw); 372s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw);
376s32 e1000_update_eeprom_checksum(struct e1000_hw *hw); 373s32 e1000_update_eeprom_checksum(struct e1000_hw *hw);
377s32 e1000_write_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 *data); 374s32 e1000_write_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data);
378s32 e1000_read_mac_addr(struct e1000_hw * hw); 375s32 e1000_read_mac_addr(struct e1000_hw *hw);
379 376
380/* Filters (multicast, vlan, receive) */ 377/* Filters (multicast, vlan, receive) */
381u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 * mc_addr); 378u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 * mc_addr);
@@ -395,7 +392,8 @@ s32 e1000_blink_led_start(struct e1000_hw *hw);
395/* Everything else */ 392/* Everything else */
396void e1000_reset_adaptive(struct e1000_hw *hw); 393void e1000_reset_adaptive(struct e1000_hw *hw);
397void e1000_update_adaptive(struct e1000_hw *hw); 394void e1000_update_adaptive(struct e1000_hw *hw);
398void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, u32 frame_len, u8 * mac_addr); 395void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats,
396 u32 frame_len, u8 * mac_addr);
399void e1000_get_bus_info(struct e1000_hw *hw); 397void e1000_get_bus_info(struct e1000_hw *hw);
400void e1000_pci_set_mwi(struct e1000_hw *hw); 398void e1000_pci_set_mwi(struct e1000_hw *hw);
401void e1000_pci_clear_mwi(struct e1000_hw *hw); 399void e1000_pci_clear_mwi(struct e1000_hw *hw);
@@ -404,7 +402,6 @@ int e1000_pcix_get_mmrbc(struct e1000_hw *hw);
404/* Port I/O is only supported on 82544 and newer */ 402/* Port I/O is only supported on 82544 and newer */
405void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value); 403void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value);
406 404
407
408#define E1000_READ_REG_IO(a, reg) \ 405#define E1000_READ_REG_IO(a, reg) \
409 e1000_read_reg_io((a), E1000_##reg) 406 e1000_read_reg_io((a), E1000_##reg)
410#define E1000_WRITE_REG_IO(a, reg, val) \ 407#define E1000_WRITE_REG_IO(a, reg, val) \
@@ -469,21 +466,20 @@ void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value);
469 466
470/* The sizes (in bytes) of a ethernet packet */ 467/* The sizes (in bytes) of a ethernet packet */
471#define ENET_HEADER_SIZE 14 468#define ENET_HEADER_SIZE 14
472#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ 469#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
473#define ETHERNET_FCS_SIZE 4 470#define ETHERNET_FCS_SIZE 4
474#define MINIMUM_ETHERNET_PACKET_SIZE \ 471#define MINIMUM_ETHERNET_PACKET_SIZE \
475 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) 472 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
476#define CRC_LENGTH ETHERNET_FCS_SIZE 473#define CRC_LENGTH ETHERNET_FCS_SIZE
477#define MAX_JUMBO_FRAME_SIZE 0x3F00 474#define MAX_JUMBO_FRAME_SIZE 0x3F00
478 475
479
480/* 802.1q VLAN Packet Sizes */ 476/* 802.1q VLAN Packet Sizes */
481#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */ 477#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
482 478
483/* Ethertype field values */ 479/* Ethertype field values */
484#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 480#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
485#define ETHERNET_IP_TYPE 0x0800 /* IP packets */ 481#define ETHERNET_IP_TYPE 0x0800 /* IP packets */
486#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */ 482#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */
487 483
488/* Packet Header defines */ 484/* Packet Header defines */
489#define IP_PROTOCOL_TCP 6 485#define IP_PROTOCOL_TCP 6
@@ -525,93 +521,93 @@ void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value);
525 521
526/* Receive Descriptor */ 522/* Receive Descriptor */
527struct e1000_rx_desc { 523struct e1000_rx_desc {
528 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 524 __le64 buffer_addr; /* Address of the descriptor's data buffer */
529 __le16 length; /* Length of data DMAed into data buffer */ 525 __le16 length; /* Length of data DMAed into data buffer */
530 __le16 csum; /* Packet checksum */ 526 __le16 csum; /* Packet checksum */
531 u8 status; /* Descriptor status */ 527 u8 status; /* Descriptor status */
532 u8 errors; /* Descriptor Errors */ 528 u8 errors; /* Descriptor Errors */
533 __le16 special; 529 __le16 special;
534}; 530};
535 531
536/* Receive Descriptor - Extended */ 532/* Receive Descriptor - Extended */
537union e1000_rx_desc_extended { 533union e1000_rx_desc_extended {
538 struct { 534 struct {
539 __le64 buffer_addr; 535 __le64 buffer_addr;
540 __le64 reserved; 536 __le64 reserved;
541 } read; 537 } read;
542 struct { 538 struct {
543 struct { 539 struct {
544 __le32 mrq; /* Multiple Rx Queues */ 540 __le32 mrq; /* Multiple Rx Queues */
545 union { 541 union {
546 __le32 rss; /* RSS Hash */ 542 __le32 rss; /* RSS Hash */
547 struct { 543 struct {
548 __le16 ip_id; /* IP id */ 544 __le16 ip_id; /* IP id */
549 __le16 csum; /* Packet Checksum */ 545 __le16 csum; /* Packet Checksum */
550 } csum_ip; 546 } csum_ip;
551 } hi_dword; 547 } hi_dword;
552 } lower; 548 } lower;
553 struct { 549 struct {
554 __le32 status_error; /* ext status/error */ 550 __le32 status_error; /* ext status/error */
555 __le16 length; 551 __le16 length;
556 __le16 vlan; /* VLAN tag */ 552 __le16 vlan; /* VLAN tag */
557 } upper; 553 } upper;
558 } wb; /* writeback */ 554 } wb; /* writeback */
559}; 555};
560 556
561#define MAX_PS_BUFFERS 4 557#define MAX_PS_BUFFERS 4
562/* Receive Descriptor - Packet Split */ 558/* Receive Descriptor - Packet Split */
563union e1000_rx_desc_packet_split { 559union e1000_rx_desc_packet_split {
564 struct { 560 struct {
565 /* one buffer for protocol header(s), three data buffers */ 561 /* one buffer for protocol header(s), three data buffers */
566 __le64 buffer_addr[MAX_PS_BUFFERS]; 562 __le64 buffer_addr[MAX_PS_BUFFERS];
567 } read; 563 } read;
568 struct { 564 struct {
569 struct { 565 struct {
570 __le32 mrq; /* Multiple Rx Queues */ 566 __le32 mrq; /* Multiple Rx Queues */
571 union { 567 union {
572 __le32 rss; /* RSS Hash */ 568 __le32 rss; /* RSS Hash */
573 struct { 569 struct {
574 __le16 ip_id; /* IP id */ 570 __le16 ip_id; /* IP id */
575 __le16 csum; /* Packet Checksum */ 571 __le16 csum; /* Packet Checksum */
576 } csum_ip; 572 } csum_ip;
577 } hi_dword; 573 } hi_dword;
578 } lower; 574 } lower;
579 struct { 575 struct {
580 __le32 status_error; /* ext status/error */ 576 __le32 status_error; /* ext status/error */
581 __le16 length0; /* length of buffer 0 */ 577 __le16 length0; /* length of buffer 0 */
582 __le16 vlan; /* VLAN tag */ 578 __le16 vlan; /* VLAN tag */
583 } middle; 579 } middle;
584 struct { 580 struct {
585 __le16 header_status; 581 __le16 header_status;
586 __le16 length[3]; /* length of buffers 1-3 */ 582 __le16 length[3]; /* length of buffers 1-3 */
587 } upper; 583 } upper;
588 __le64 reserved; 584 __le64 reserved;
589 } wb; /* writeback */ 585 } wb; /* writeback */
590}; 586};
591 587
592/* Receive Decriptor bit definitions */ 588/* Receive Descriptor bit definitions */
593#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 589#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
594#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 590#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
595#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 591#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
596#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 592#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
597#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */ 593#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
598#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 594#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
599#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 595#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
600#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 596#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
601#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ 597#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
602#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 598#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
603#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 599#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
604#define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 600#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
605#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 601#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
606#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 602#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
607#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 603#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
608#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 604#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
609#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 605#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
610#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 606#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
611#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 607#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
612#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 608#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
613#define E1000_RXD_SPC_PRI_SHIFT 13 609#define E1000_RXD_SPC_PRI_SHIFT 13
614#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ 610#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
615#define E1000_RXD_SPC_CFI_SHIFT 12 611#define E1000_RXD_SPC_CFI_SHIFT 12
616 612
617#define E1000_RXDEXT_STATERR_CE 0x01000000 613#define E1000_RXDEXT_STATERR_CE 0x01000000
@@ -633,7 +629,6 @@ union e1000_rx_desc_packet_split {
633 E1000_RXD_ERR_CXE | \ 629 E1000_RXD_ERR_CXE | \
634 E1000_RXD_ERR_RXE) 630 E1000_RXD_ERR_RXE)
635 631
636
637/* Same mask, but for extended and packet split descriptors */ 632/* Same mask, but for extended and packet split descriptors */
638#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 633#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
639 E1000_RXDEXT_STATERR_CE | \ 634 E1000_RXDEXT_STATERR_CE | \
@@ -642,109 +637,108 @@ union e1000_rx_desc_packet_split {
642 E1000_RXDEXT_STATERR_CXE | \ 637 E1000_RXDEXT_STATERR_CXE | \
643 E1000_RXDEXT_STATERR_RXE) 638 E1000_RXDEXT_STATERR_RXE)
644 639
645
646/* Transmit Descriptor */ 640/* Transmit Descriptor */
647struct e1000_tx_desc { 641struct e1000_tx_desc {
648 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 642 __le64 buffer_addr; /* Address of the descriptor's data buffer */
649 union { 643 union {
650 __le32 data; 644 __le32 data;
651 struct { 645 struct {
652 __le16 length; /* Data buffer length */ 646 __le16 length; /* Data buffer length */
653 u8 cso; /* Checksum offset */ 647 u8 cso; /* Checksum offset */
654 u8 cmd; /* Descriptor control */ 648 u8 cmd; /* Descriptor control */
655 } flags; 649 } flags;
656 } lower; 650 } lower;
657 union { 651 union {
658 __le32 data; 652 __le32 data;
659 struct { 653 struct {
660 u8 status; /* Descriptor status */ 654 u8 status; /* Descriptor status */
661 u8 css; /* Checksum start */ 655 u8 css; /* Checksum start */
662 __le16 special; 656 __le16 special;
663 } fields; 657 } fields;
664 } upper; 658 } upper;
665}; 659};
666 660
667/* Transmit Descriptor bit definitions */ 661/* Transmit Descriptor bit definitions */
668#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 662#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
669#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ 663#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
670#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 664#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
671#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 665#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
672#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 666#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
673#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 667#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
674#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 668#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
675#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 669#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
676#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 670#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
677#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 671#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
678#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 672#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
679#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 673#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
680#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 674#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
681#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 675#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
682#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 676#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
683#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 677#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
684#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 678#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
685#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 679#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
686#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 680#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
687#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 681#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
688 682
689/* Offload Context Descriptor */ 683/* Offload Context Descriptor */
690struct e1000_context_desc { 684struct e1000_context_desc {
691 union { 685 union {
692 __le32 ip_config; 686 __le32 ip_config;
693 struct { 687 struct {
694 u8 ipcss; /* IP checksum start */ 688 u8 ipcss; /* IP checksum start */
695 u8 ipcso; /* IP checksum offset */ 689 u8 ipcso; /* IP checksum offset */
696 __le16 ipcse; /* IP checksum end */ 690 __le16 ipcse; /* IP checksum end */
697 } ip_fields; 691 } ip_fields;
698 } lower_setup; 692 } lower_setup;
699 union { 693 union {
700 __le32 tcp_config; 694 __le32 tcp_config;
701 struct { 695 struct {
702 u8 tucss; /* TCP checksum start */ 696 u8 tucss; /* TCP checksum start */
703 u8 tucso; /* TCP checksum offset */ 697 u8 tucso; /* TCP checksum offset */
704 __le16 tucse; /* TCP checksum end */ 698 __le16 tucse; /* TCP checksum end */
705 } tcp_fields; 699 } tcp_fields;
706 } upper_setup; 700 } upper_setup;
707 __le32 cmd_and_length; /* */ 701 __le32 cmd_and_length; /* */
708 union { 702 union {
709 __le32 data; 703 __le32 data;
710 struct { 704 struct {
711 u8 status; /* Descriptor status */ 705 u8 status; /* Descriptor status */
712 u8 hdr_len; /* Header length */ 706 u8 hdr_len; /* Header length */
713 __le16 mss; /* Maximum segment size */ 707 __le16 mss; /* Maximum segment size */
714 } fields; 708 } fields;
715 } tcp_seg_setup; 709 } tcp_seg_setup;
716}; 710};
717 711
718/* Offload data descriptor */ 712/* Offload data descriptor */
719struct e1000_data_desc { 713struct e1000_data_desc {
720 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 714 __le64 buffer_addr; /* Address of the descriptor's buffer address */
721 union { 715 union {
722 __le32 data; 716 __le32 data;
723 struct { 717 struct {
724 __le16 length; /* Data buffer length */ 718 __le16 length; /* Data buffer length */
725 u8 typ_len_ext; /* */ 719 u8 typ_len_ext; /* */
726 u8 cmd; /* */ 720 u8 cmd; /* */
727 } flags; 721 } flags;
728 } lower; 722 } lower;
729 union { 723 union {
730 __le32 data; 724 __le32 data;
731 struct { 725 struct {
732 u8 status; /* Descriptor status */ 726 u8 status; /* Descriptor status */
733 u8 popts; /* Packet Options */ 727 u8 popts; /* Packet Options */
734 __le16 special; /* */ 728 __le16 special; /* */
735 } fields; 729 } fields;
736 } upper; 730 } upper;
737}; 731};
738 732
739/* Filters */ 733/* Filters */
740#define E1000_NUM_UNICAST 16 /* Unicast filter entries */ 734#define E1000_NUM_UNICAST 16 /* Unicast filter entries */
741#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ 735#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
742#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 736#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
743 737
744/* Receive Address Register */ 738/* Receive Address Register */
745struct e1000_rar { 739struct e1000_rar {
746 volatile __le32 low; /* receive address low */ 740 volatile __le32 low; /* receive address low */
747 volatile __le32 high; /* receive address high */ 741 volatile __le32 high; /* receive address high */
748}; 742};
749 743
750/* Number of entries in the Multicast Table Array (MTA). */ 744/* Number of entries in the Multicast Table Array (MTA). */
@@ -752,8 +746,8 @@ struct e1000_rar {
752 746
753/* IPv4 Address Table Entry */ 747/* IPv4 Address Table Entry */
754struct e1000_ipv4_at_entry { 748struct e1000_ipv4_at_entry {
755 volatile u32 ipv4_addr; /* IP Address (RW) */ 749 volatile u32 ipv4_addr; /* IP Address (RW) */
756 volatile u32 reserved; 750 volatile u32 reserved;
757}; 751};
758 752
759/* Four wakeup IP addresses are supported */ 753/* Four wakeup IP addresses are supported */
@@ -763,25 +757,25 @@ struct e1000_ipv4_at_entry {
763 757
764/* IPv6 Address Table Entry */ 758/* IPv6 Address Table Entry */
765struct e1000_ipv6_at_entry { 759struct e1000_ipv6_at_entry {
766 volatile u8 ipv6_addr[16]; 760 volatile u8 ipv6_addr[16];
767}; 761};
768 762
769/* Flexible Filter Length Table Entry */ 763/* Flexible Filter Length Table Entry */
770struct e1000_fflt_entry { 764struct e1000_fflt_entry {
771 volatile u32 length; /* Flexible Filter Length (RW) */ 765 volatile u32 length; /* Flexible Filter Length (RW) */
772 volatile u32 reserved; 766 volatile u32 reserved;
773}; 767};
774 768
775/* Flexible Filter Mask Table Entry */ 769/* Flexible Filter Mask Table Entry */
776struct e1000_ffmt_entry { 770struct e1000_ffmt_entry {
777 volatile u32 mask; /* Flexible Filter Mask (RW) */ 771 volatile u32 mask; /* Flexible Filter Mask (RW) */
778 volatile u32 reserved; 772 volatile u32 reserved;
779}; 773};
780 774
781/* Flexible Filter Value Table Entry */ 775/* Flexible Filter Value Table Entry */
782struct e1000_ffvt_entry { 776struct e1000_ffvt_entry {
783 volatile u32 value; /* Flexible Filter Value (RW) */ 777 volatile u32 value; /* Flexible Filter Value (RW) */
784 volatile u32 reserved; 778 volatile u32 reserved;
785}; 779};
786 780
787/* Four Flexible Filters are supported */ 781/* Four Flexible Filters are supported */
@@ -808,210 +802,211 @@ struct e1000_ffvt_entry {
808 * R/clr - register is read only and is cleared when read 802 * R/clr - register is read only and is cleared when read
809 * A - register array 803 * A - register array
810 */ 804 */
811#define E1000_CTRL 0x00000 /* Device Control - RW */ 805#define E1000_CTRL 0x00000 /* Device Control - RW */
812#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ 806#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
813#define E1000_STATUS 0x00008 /* Device Status - RO */ 807#define E1000_STATUS 0x00008 /* Device Status - RO */
814#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ 808#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
815#define E1000_EERD 0x00014 /* EEPROM Read - RW */ 809#define E1000_EERD 0x00014 /* EEPROM Read - RW */
816#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ 810#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
817#define E1000_FLA 0x0001C /* Flash Access - RW */ 811#define E1000_FLA 0x0001C /* Flash Access - RW */
818#define E1000_MDIC 0x00020 /* MDI Control - RW */ 812#define E1000_MDIC 0x00020 /* MDI Control - RW */
819#define E1000_SCTL 0x00024 /* SerDes Control - RW */ 813#define E1000_SCTL 0x00024 /* SerDes Control - RW */
820#define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */ 814#define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */
821#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ 815#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
822#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ 816#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
823#define E1000_FCT 0x00030 /* Flow Control Type - RW */ 817#define E1000_FCT 0x00030 /* Flow Control Type - RW */
824#define E1000_VET 0x00038 /* VLAN Ether Type - RW */ 818#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
825#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ 819#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
826#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ 820#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
827#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ 821#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
828#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ 822#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
829#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ 823#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
830#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ 824#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
831#define E1000_RCTL 0x00100 /* RX Control - RW */ 825#define E1000_RCTL 0x00100 /* RX Control - RW */
832#define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */ 826#define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */
833#define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */ 827#define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */
834#define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */ 828#define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */
835#define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */ 829#define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */
836#define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */ 830#define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */
837#define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */ 831#define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */
838#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ 832#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
839#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ 833#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
840#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */ 834#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
841#define E1000_TCTL 0x00400 /* TX Control - RW */ 835#define E1000_TCTL 0x00400 /* TX Control - RW */
842#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ 836#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
843#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ 837#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
844#define E1000_TBT 0x00448 /* TX Burst Timer - RW */ 838#define E1000_TBT 0x00448 /* TX Burst Timer - RW */
845#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ 839#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
846#define E1000_LEDCTL 0x00E00 /* LED Control - RW */ 840#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
847#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ 841#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
848#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ 842#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
849#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ 843#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
850#define FEXTNVM_SW_CONFIG 0x0001 844#define FEXTNVM_SW_CONFIG 0x0001
851#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ 845#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
852#define E1000_PBS 0x01008 /* Packet Buffer Size */ 846#define E1000_PBS 0x01008 /* Packet Buffer Size */
853#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ 847#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
854#define E1000_FLASH_UPDATES 1000 848#define E1000_FLASH_UPDATES 1000
855#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ 849#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
856#define E1000_FLASHT 0x01028 /* FLASH Timer Register */ 850#define E1000_FLASHT 0x01028 /* FLASH Timer Register */
857#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ 851#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
858#define E1000_FLSWCTL 0x01030 /* FLASH control register */ 852#define E1000_FLSWCTL 0x01030 /* FLASH control register */
859#define E1000_FLSWDATA 0x01034 /* FLASH data register */ 853#define E1000_FLSWDATA 0x01034 /* FLASH data register */
860#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ 854#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
861#define E1000_FLOP 0x0103C /* FLASH Opcode Register */ 855#define E1000_FLOP 0x0103C /* FLASH Opcode Register */
862#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ 856#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
863#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ 857#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
864#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ 858#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
865#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ 859#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
866#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */ 860#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
867#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */ 861#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
868#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */ 862#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
869#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */ 863#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
870#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */ 864#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
871#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */ 865#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
872#define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */ 866#define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */
873#define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */ 867#define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */
874#define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */ 868#define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */
875#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */ 869#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */
876#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */ 870#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */
877#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */ 871#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */
878#define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */ 872#define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */
879#define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */ 873#define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */
880#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ 874#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
881#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ 875#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
882#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ 876#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
883#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ 877#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
884#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ 878#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
885#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ 879#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
886#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ 880#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
887#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ 881#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
888#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */ 882#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
889#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */ 883#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
890#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */ 884#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
891#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */ 885#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
892#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */ 886#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
893#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */ 887#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
894#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */ 888#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
895#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */ 889#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
896#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */ 890#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
897#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ 891#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
898#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ 892#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
899#define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */ 893#define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */
900#define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */ 894#define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */
901#define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */ 895#define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */
902#define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */ 896#define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */
903#define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */ 897#define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */
904#define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */ 898#define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */
905#define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */ 899#define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */
906#define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */ 900#define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */
907#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ 901#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
908#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ 902#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
909#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ 903#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
910#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ 904#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
911#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ 905#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
912#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ 906#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
913#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ 907#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
914#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ 908#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
915#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ 909#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
916#define E1000_COLC 0x04028 /* Collision Count - R/clr */ 910#define E1000_COLC 0x04028 /* Collision Count - R/clr */
917#define E1000_DC 0x04030 /* Defer Count - R/clr */ 911#define E1000_DC 0x04030 /* Defer Count - R/clr */
918#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ 912#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
919#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ 913#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
920#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ 914#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
921#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ 915#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
922#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ 916#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
923#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ 917#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
924#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ 918#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
925#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ 919#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
926#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ 920#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
927#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ 921#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
928#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ 922#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
929#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ 923#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
930#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ 924#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
931#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ 925#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
932#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ 926#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
933#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ 927#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
934#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ 928#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
935#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ 929#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
936#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ 930#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
937#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ 931#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
938#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ 932#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
939#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ 933#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
940#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ 934#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
941#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ 935#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
942#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ 936#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
943#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ 937#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
944#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ 938#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
945#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ 939#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
946#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ 940#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
947#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ 941#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
948#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ 942#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
949#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ 943#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
950#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ 944#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
951#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ 945#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
952#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ 946#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
953#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ 947#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
954#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ 948#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
955#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ 949#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
956#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ 950#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
957#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ 951#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
958#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ 952#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
959#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ 953#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
960#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ 954#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
961#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ 955#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
962#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ 956#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
963#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ 957#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
964#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ 958#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
965#define E1000_IAC 0x04100 /* Interrupt Assertion Count */ 959#define E1000_IAC 0x04100 /* Interrupt Assertion Count */
966#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */ 960#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */
967#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */ 961#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */
968#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */ 962#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */
969#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */ 963#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */
970#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ 964#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */
971#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */ 965#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */
972#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */ 966#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */
973#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ 967#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */
974#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ 968#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
975#define E1000_RFCTL 0x05008 /* Receive Filter Control*/ 969#define E1000_RFCTL 0x05008 /* Receive Filter Control */
976#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ 970#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
977#define E1000_RA 0x05400 /* Receive Address - RW Array */ 971#define E1000_RA 0x05400 /* Receive Address - RW Array */
978#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ 972#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
979#define E1000_WUC 0x05800 /* Wakeup Control - RW */ 973#define E1000_WUC 0x05800 /* Wakeup Control - RW */
980#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ 974#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
981#define E1000_WUS 0x05810 /* Wakeup Status - RO */ 975#define E1000_WUS 0x05810 /* Wakeup Status - RO */
982#define E1000_MANC 0x05820 /* Management Control - RW */ 976#define E1000_MANC 0x05820 /* Management Control - RW */
983#define E1000_IPAV 0x05838 /* IP Address Valid - RW */ 977#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
984#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ 978#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
985#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ 979#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
986#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ 980#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
987#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ 981#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
988#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ 982#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
989#define E1000_HOST_IF 0x08800 /* Host Interface */ 983#define E1000_HOST_IF 0x08800 /* Host Interface */
990#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ 984#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
991#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ 985#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
992 986
993#define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */ 987#define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */
994#define E1000_MDPHYA 0x0003C /* PHY address - RW */ 988#define E1000_MDPHYA 0x0003C /* PHY address - RW */
995#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ 989#define E1000_MANC2H 0x05860 /* Managment Control To Host - RW */
996 990#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
997#define E1000_GCR 0x05B00 /* PCI-Ex Control */ 991
998#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ 992#define E1000_GCR 0x05B00 /* PCI-Ex Control */
999#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ 993#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
1000#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ 994#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
1001#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ 995#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
1002#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ 996#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
1003#define E1000_SWSM 0x05B50 /* SW Semaphore */ 997#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
1004#define E1000_FWSM 0x05B54 /* FW Semaphore */ 998#define E1000_SWSM 0x05B50 /* SW Semaphore */
1005#define E1000_FFLT_DBG 0x05F04 /* Debug Register */ 999#define E1000_FWSM 0x05B54 /* FW Semaphore */
1006#define E1000_HICR 0x08F00 /* Host Inteface Control */ 1000#define E1000_FFLT_DBG 0x05F04 /* Debug Register */
1001#define E1000_HICR 0x08F00 /* Host Interface Control */
1007 1002
1008/* RSS registers */ 1003/* RSS registers */
1009#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ 1004#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */
1010#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ 1005#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
1011#define E1000_RETA 0x05C00 /* Redirection Table - RW Array */ 1006#define E1000_RETA 0x05C00 /* Redirection Table - RW Array */
1012#define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */ 1007#define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */
1013#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */ 1008#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */
1014#define E1000_RSSIR 0x05868 /* RSS Interrupt Request */ 1009#define E1000_RSSIR 0x05868 /* RSS Interrupt Request */
1015/* Register Set (82542) 1010/* Register Set (82542)
1016 * 1011 *
1017 * Some of the 82542 registers are located at different offsets than they are 1012 * Some of the 82542 registers are located at different offsets than they are
@@ -1051,19 +1046,19 @@ struct e1000_ffvt_entry {
1051#define E1000_82542_RDLEN0 E1000_82542_RDLEN 1046#define E1000_82542_RDLEN0 E1000_82542_RDLEN
1052#define E1000_82542_RDH0 E1000_82542_RDH 1047#define E1000_82542_RDH0 E1000_82542_RDH
1053#define E1000_82542_RDT0 E1000_82542_RDT 1048#define E1000_82542_RDT0 E1000_82542_RDT
1054#define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8)) /* Split and Replication 1049#define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8)) /* Split and Replication
1055 * RX Control - RW */ 1050 * RX Control - RW */
1056#define E1000_82542_DCA_RXCTRL(_n) (0x02814 + ((_n) << 8)) 1051#define E1000_82542_DCA_RXCTRL(_n) (0x02814 + ((_n) << 8))
1057#define E1000_82542_RDBAH3 0x02B04 /* RX Desc Base High Queue 3 - RW */ 1052#define E1000_82542_RDBAH3 0x02B04 /* RX Desc Base High Queue 3 - RW */
1058#define E1000_82542_RDBAL3 0x02B00 /* RX Desc Low Queue 3 - RW */ 1053#define E1000_82542_RDBAL3 0x02B00 /* RX Desc Low Queue 3 - RW */
1059#define E1000_82542_RDLEN3 0x02B08 /* RX Desc Length Queue 3 - RW */ 1054#define E1000_82542_RDLEN3 0x02B08 /* RX Desc Length Queue 3 - RW */
1060#define E1000_82542_RDH3 0x02B10 /* RX Desc Head Queue 3 - RW */ 1055#define E1000_82542_RDH3 0x02B10 /* RX Desc Head Queue 3 - RW */
1061#define E1000_82542_RDT3 0x02B18 /* RX Desc Tail Queue 3 - RW */ 1056#define E1000_82542_RDT3 0x02B18 /* RX Desc Tail Queue 3 - RW */
1062#define E1000_82542_RDBAL2 0x02A00 /* RX Desc Base Low Queue 2 - RW */ 1057#define E1000_82542_RDBAL2 0x02A00 /* RX Desc Base Low Queue 2 - RW */
1063#define E1000_82542_RDBAH2 0x02A04 /* RX Desc Base High Queue 2 - RW */ 1058#define E1000_82542_RDBAH2 0x02A04 /* RX Desc Base High Queue 2 - RW */
1064#define E1000_82542_RDLEN2 0x02A08 /* RX Desc Length Queue 2 - RW */ 1059#define E1000_82542_RDLEN2 0x02A08 /* RX Desc Length Queue 2 - RW */
1065#define E1000_82542_RDH2 0x02A10 /* RX Desc Head Queue 2 - RW */ 1060#define E1000_82542_RDH2 0x02A10 /* RX Desc Head Queue 2 - RW */
1066#define E1000_82542_RDT2 0x02A18 /* RX Desc Tail Queue 2 - RW */ 1061#define E1000_82542_RDT2 0x02A18 /* RX Desc Tail Queue 2 - RW */
1067#define E1000_82542_RDTR1 0x00130 1062#define E1000_82542_RDTR1 0x00130
1068#define E1000_82542_RDBAL1 0x00138 1063#define E1000_82542_RDBAL1 0x00138
1069#define E1000_82542_RDBAH1 0x0013C 1064#define E1000_82542_RDBAH1 0x0013C
@@ -1233,279 +1228,278 @@ struct e1000_ffvt_entry {
1233 1228
1234/* Statistics counters collected by the MAC */ 1229/* Statistics counters collected by the MAC */
1235struct e1000_hw_stats { 1230struct e1000_hw_stats {
1236 u64 crcerrs; 1231 u64 crcerrs;
1237 u64 algnerrc; 1232 u64 algnerrc;
1238 u64 symerrs; 1233 u64 symerrs;
1239 u64 rxerrc; 1234 u64 rxerrc;
1240 u64 txerrc; 1235 u64 txerrc;
1241 u64 mpc; 1236 u64 mpc;
1242 u64 scc; 1237 u64 scc;
1243 u64 ecol; 1238 u64 ecol;
1244 u64 mcc; 1239 u64 mcc;
1245 u64 latecol; 1240 u64 latecol;
1246 u64 colc; 1241 u64 colc;
1247 u64 dc; 1242 u64 dc;
1248 u64 tncrs; 1243 u64 tncrs;
1249 u64 sec; 1244 u64 sec;
1250 u64 cexterr; 1245 u64 cexterr;
1251 u64 rlec; 1246 u64 rlec;
1252 u64 xonrxc; 1247 u64 xonrxc;
1253 u64 xontxc; 1248 u64 xontxc;
1254 u64 xoffrxc; 1249 u64 xoffrxc;
1255 u64 xofftxc; 1250 u64 xofftxc;
1256 u64 fcruc; 1251 u64 fcruc;
1257 u64 prc64; 1252 u64 prc64;
1258 u64 prc127; 1253 u64 prc127;
1259 u64 prc255; 1254 u64 prc255;
1260 u64 prc511; 1255 u64 prc511;
1261 u64 prc1023; 1256 u64 prc1023;
1262 u64 prc1522; 1257 u64 prc1522;
1263 u64 gprc; 1258 u64 gprc;
1264 u64 bprc; 1259 u64 bprc;
1265 u64 mprc; 1260 u64 mprc;
1266 u64 gptc; 1261 u64 gptc;
1267 u64 gorcl; 1262 u64 gorcl;
1268 u64 gorch; 1263 u64 gorch;
1269 u64 gotcl; 1264 u64 gotcl;
1270 u64 gotch; 1265 u64 gotch;
1271 u64 rnbc; 1266 u64 rnbc;
1272 u64 ruc; 1267 u64 ruc;
1273 u64 rfc; 1268 u64 rfc;
1274 u64 roc; 1269 u64 roc;
1275 u64 rlerrc; 1270 u64 rlerrc;
1276 u64 rjc; 1271 u64 rjc;
1277 u64 mgprc; 1272 u64 mgprc;
1278 u64 mgpdc; 1273 u64 mgpdc;
1279 u64 mgptc; 1274 u64 mgptc;
1280 u64 torl; 1275 u64 torl;
1281 u64 torh; 1276 u64 torh;
1282 u64 totl; 1277 u64 totl;
1283 u64 toth; 1278 u64 toth;
1284 u64 tpr; 1279 u64 tpr;
1285 u64 tpt; 1280 u64 tpt;
1286 u64 ptc64; 1281 u64 ptc64;
1287 u64 ptc127; 1282 u64 ptc127;
1288 u64 ptc255; 1283 u64 ptc255;
1289 u64 ptc511; 1284 u64 ptc511;
1290 u64 ptc1023; 1285 u64 ptc1023;
1291 u64 ptc1522; 1286 u64 ptc1522;
1292 u64 mptc; 1287 u64 mptc;
1293 u64 bptc; 1288 u64 bptc;
1294 u64 tsctc; 1289 u64 tsctc;
1295 u64 tsctfc; 1290 u64 tsctfc;
1296 u64 iac; 1291 u64 iac;
1297 u64 icrxptc; 1292 u64 icrxptc;
1298 u64 icrxatc; 1293 u64 icrxatc;
1299 u64 ictxptc; 1294 u64 ictxptc;
1300 u64 ictxatc; 1295 u64 ictxatc;
1301 u64 ictxqec; 1296 u64 ictxqec;
1302 u64 ictxqmtc; 1297 u64 ictxqmtc;
1303 u64 icrxdmtc; 1298 u64 icrxdmtc;
1304 u64 icrxoc; 1299 u64 icrxoc;
1305}; 1300};
1306 1301
1307/* Structure containing variables used by the shared code (e1000_hw.c) */ 1302/* Structure containing variables used by the shared code (e1000_hw.c) */
1308struct e1000_hw { 1303struct e1000_hw {
1309 u8 __iomem *hw_addr; 1304 u8 __iomem *hw_addr;
1310 u8 __iomem *flash_address; 1305 u8 __iomem *flash_address;
1311 e1000_mac_type mac_type; 1306 e1000_mac_type mac_type;
1312 e1000_phy_type phy_type; 1307 e1000_phy_type phy_type;
1313 u32 phy_init_script; 1308 u32 phy_init_script;
1314 e1000_media_type media_type; 1309 e1000_media_type media_type;
1315 void *back; 1310 void *back;
1316 struct e1000_shadow_ram *eeprom_shadow_ram; 1311 struct e1000_shadow_ram *eeprom_shadow_ram;
1317 u32 flash_bank_size; 1312 u32 flash_bank_size;
1318 u32 flash_base_addr; 1313 u32 flash_base_addr;
1319 e1000_fc_type fc; 1314 e1000_fc_type fc;
1320 e1000_bus_speed bus_speed; 1315 e1000_bus_speed bus_speed;
1321 e1000_bus_width bus_width; 1316 e1000_bus_width bus_width;
1322 e1000_bus_type bus_type; 1317 e1000_bus_type bus_type;
1323 struct e1000_eeprom_info eeprom; 1318 struct e1000_eeprom_info eeprom;
1324 e1000_ms_type master_slave; 1319 e1000_ms_type master_slave;
1325 e1000_ms_type original_master_slave; 1320 e1000_ms_type original_master_slave;
1326 e1000_ffe_config ffe_config_state; 1321 e1000_ffe_config ffe_config_state;
1327 u32 asf_firmware_present; 1322 u32 asf_firmware_present;
1328 u32 eeprom_semaphore_present; 1323 u32 eeprom_semaphore_present;
1329 unsigned long io_base; 1324 unsigned long io_base;
1330 u32 phy_id; 1325 u32 phy_id;
1331 u32 phy_revision; 1326 u32 phy_revision;
1332 u32 phy_addr; 1327 u32 phy_addr;
1333 u32 original_fc; 1328 u32 original_fc;
1334 u32 txcw; 1329 u32 txcw;
1335 u32 autoneg_failed; 1330 u32 autoneg_failed;
1336 u32 max_frame_size; 1331 u32 max_frame_size;
1337 u32 min_frame_size; 1332 u32 min_frame_size;
1338 u32 mc_filter_type; 1333 u32 mc_filter_type;
1339 u32 num_mc_addrs; 1334 u32 num_mc_addrs;
1340 u32 collision_delta; 1335 u32 collision_delta;
1341 u32 tx_packet_delta; 1336 u32 tx_packet_delta;
1342 u32 ledctl_default; 1337 u32 ledctl_default;
1343 u32 ledctl_mode1; 1338 u32 ledctl_mode1;
1344 u32 ledctl_mode2; 1339 u32 ledctl_mode2;
1345 bool tx_pkt_filtering; 1340 bool tx_pkt_filtering;
1346 struct e1000_host_mng_dhcp_cookie mng_cookie; 1341 struct e1000_host_mng_dhcp_cookie mng_cookie;
1347 u16 phy_spd_default; 1342 u16 phy_spd_default;
1348 u16 autoneg_advertised; 1343 u16 autoneg_advertised;
1349 u16 pci_cmd_word; 1344 u16 pci_cmd_word;
1350 u16 fc_high_water; 1345 u16 fc_high_water;
1351 u16 fc_low_water; 1346 u16 fc_low_water;
1352 u16 fc_pause_time; 1347 u16 fc_pause_time;
1353 u16 current_ifs_val; 1348 u16 current_ifs_val;
1354 u16 ifs_min_val; 1349 u16 ifs_min_val;
1355 u16 ifs_max_val; 1350 u16 ifs_max_val;
1356 u16 ifs_step_size; 1351 u16 ifs_step_size;
1357 u16 ifs_ratio; 1352 u16 ifs_ratio;
1358 u16 device_id; 1353 u16 device_id;
1359 u16 vendor_id; 1354 u16 vendor_id;
1360 u16 subsystem_id; 1355 u16 subsystem_id;
1361 u16 subsystem_vendor_id; 1356 u16 subsystem_vendor_id;
1362 u8 revision_id; 1357 u8 revision_id;
1363 u8 autoneg; 1358 u8 autoneg;
1364 u8 mdix; 1359 u8 mdix;
1365 u8 forced_speed_duplex; 1360 u8 forced_speed_duplex;
1366 u8 wait_autoneg_complete; 1361 u8 wait_autoneg_complete;
1367 u8 dma_fairness; 1362 u8 dma_fairness;
1368 u8 mac_addr[NODE_ADDRESS_SIZE]; 1363 u8 mac_addr[NODE_ADDRESS_SIZE];
1369 u8 perm_mac_addr[NODE_ADDRESS_SIZE]; 1364 u8 perm_mac_addr[NODE_ADDRESS_SIZE];
1370 bool disable_polarity_correction; 1365 bool disable_polarity_correction;
1371 bool speed_downgraded; 1366 bool speed_downgraded;
1372 e1000_smart_speed smart_speed; 1367 e1000_smart_speed smart_speed;
1373 e1000_dsp_config dsp_config_state; 1368 e1000_dsp_config dsp_config_state;
1374 bool get_link_status; 1369 bool get_link_status;
1375 bool serdes_has_link; 1370 bool serdes_has_link;
1376 bool tbi_compatibility_en; 1371 bool tbi_compatibility_en;
1377 bool tbi_compatibility_on; 1372 bool tbi_compatibility_on;
1378 bool laa_is_present; 1373 bool laa_is_present;
1379 bool phy_reset_disable; 1374 bool phy_reset_disable;
1380 bool initialize_hw_bits_disable; 1375 bool initialize_hw_bits_disable;
1381 bool fc_send_xon; 1376 bool fc_send_xon;
1382 bool fc_strict_ieee; 1377 bool fc_strict_ieee;
1383 bool report_tx_early; 1378 bool report_tx_early;
1384 bool adaptive_ifs; 1379 bool adaptive_ifs;
1385 bool ifs_params_forced; 1380 bool ifs_params_forced;
1386 bool in_ifs_mode; 1381 bool in_ifs_mode;
1387 bool mng_reg_access_disabled; 1382 bool mng_reg_access_disabled;
1388 bool leave_av_bit_off; 1383 bool leave_av_bit_off;
1389 bool bad_tx_carr_stats_fd; 1384 bool bad_tx_carr_stats_fd;
1390 bool has_smbus; 1385 bool has_smbus;
1391}; 1386};
1392 1387
1393 1388#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
1394#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ 1389#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
1395#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ 1390#define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */
1396#define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */ 1391#define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1397#define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 1392#define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */
1398#define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */ 1393#define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1399#define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 1394#define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */
1400#define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */ 1395#define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */
1401#define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */
1402/* Register Bit Masks */ 1396/* Register Bit Masks */
1403/* Device Control */ 1397/* Device Control */
1404#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 1398#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
1405#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ 1399#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
1406#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ 1400#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
1407#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ 1401#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
1408#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 1402#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
1409#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ 1403#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
1410#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ 1404#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
1411#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 1405#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
1412#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 1406#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
1413#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 1407#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
1414#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 1408#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
1415#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 1409#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
1416#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 1410#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
1417#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 1411#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
1418#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ 1412#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
1419#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 1413#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
1420#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 1414#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
1421#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */ 1415#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */
1422#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */ 1416#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */
1423#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */ 1417#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */
1424#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */ 1418#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */
1425#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 1419#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
1426#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 1420#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
1427#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ 1421#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
1428#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ 1422#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
1429#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 1423#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
1430#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ 1424#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
1431#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ 1425#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
1432#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ 1426#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
1433#define E1000_CTRL_RST 0x04000000 /* Global reset */ 1427#define E1000_CTRL_RST 0x04000000 /* Global reset */
1434#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 1428#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
1435#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 1429#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
1436#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ 1430#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
1437#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 1431#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
1438#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 1432#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
1439#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */ 1433#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */
1440 1434
1441/* Device Status */ 1435/* Device Status */
1442#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 1436#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
1443#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 1437#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
1444#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 1438#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
1445#define E1000_STATUS_FUNC_SHIFT 2 1439#define E1000_STATUS_FUNC_SHIFT 2
1446#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ 1440#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
1447#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 1441#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
1448#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 1442#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
1449#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ 1443#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
1450#define E1000_STATUS_SPEED_MASK 0x000000C0 1444#define E1000_STATUS_SPEED_MASK 0x000000C0
1451#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 1445#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
1452#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 1446#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
1453#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 1447#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
1454#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion 1448#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion
1455 by EEPROM/Flash */ 1449 by EEPROM/Flash */
1456#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ 1450#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
1457#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */ 1451#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */
1458#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ 1452#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
1459#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ 1453#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
1460#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ 1454#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
1461#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ 1455#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
1462#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ 1456#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
1463#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ 1457#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
1464#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */ 1458#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */
1465#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */ 1459#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */
1466#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */ 1460#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */
1467#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */ 1461#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
1468#define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */ 1462#define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */
1469#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */ 1463#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
1470#define E1000_STATUS_FUSE_8 0x04000000 1464#define E1000_STATUS_FUSE_8 0x04000000
1471#define E1000_STATUS_FUSE_9 0x08000000 1465#define E1000_STATUS_FUSE_9 0x08000000
1472#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */ 1466#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */
1473#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */ 1467#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */
1474 1468
1475/* Constants used to intrepret the masked PCI-X bus speed. */ 1469/* Constants used to interpret the masked PCI-X bus speed. */
1476#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ 1470#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
1477#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ 1471#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
1478#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */ 1472#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
1479 1473
1480/* EEPROM/Flash Control */ 1474/* EEPROM/Flash Control */
1481#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */ 1475#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */
1482#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */ 1476#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */
1483#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */ 1477#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */
1484#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */ 1478#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */
1485#define E1000_EECD_FWE_MASK 0x00000030 1479#define E1000_EECD_FWE_MASK 0x00000030
1486#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ 1480#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1487#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ 1481#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1488#define E1000_EECD_FWE_SHIFT 4 1482#define E1000_EECD_FWE_SHIFT 4
1489#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */ 1483#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */
1490#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */ 1484#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */
1491#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */ 1485#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
1492#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */ 1486#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
1493#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type 1487#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
1494 * (0-small, 1-large) */ 1488 * (0-small, 1-large) */
1495#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */ 1489#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
1496#ifndef E1000_EEPROM_GRANT_ATTEMPTS 1490#ifndef E1000_EEPROM_GRANT_ATTEMPTS
1497#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ 1491#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1498#endif 1492#endif
1499#define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */ 1493#define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */
1500#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */ 1494#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */
1501#define E1000_EECD_SIZE_EX_SHIFT 11 1495#define E1000_EECD_SIZE_EX_SHIFT 11
1502#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ 1496#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
1503#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ 1497#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
1504#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ 1498#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
1505#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 1499#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1506#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ 1500#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
1507#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ 1501#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
1508#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 1502#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
1509#define E1000_EECD_SECVAL_SHIFT 22 1503#define E1000_EECD_SECVAL_SHIFT 22
1510#define E1000_STM_OPCODE 0xDB00 1504#define E1000_STM_OPCODE 0xDB00
1511#define E1000_HICR_FW_RESET 0xC0 1505#define E1000_HICR_FW_RESET 0xC0
@@ -1515,12 +1509,12 @@ struct e1000_hw {
1515#define E1000_ICH_NVM_SIG_MASK 0xC0 1509#define E1000_ICH_NVM_SIG_MASK 0xC0
1516 1510
1517/* EEPROM Read */ 1511/* EEPROM Read */
1518#define E1000_EERD_START 0x00000001 /* Start Read */ 1512#define E1000_EERD_START 0x00000001 /* Start Read */
1519#define E1000_EERD_DONE 0x00000010 /* Read Done */ 1513#define E1000_EERD_DONE 0x00000010 /* Read Done */
1520#define E1000_EERD_ADDR_SHIFT 8 1514#define E1000_EERD_ADDR_SHIFT 8
1521#define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */ 1515#define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */
1522#define E1000_EERD_DATA_SHIFT 16 1516#define E1000_EERD_DATA_SHIFT 16
1523#define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */ 1517#define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */
1524 1518
1525/* SPI EEPROM Status Register */ 1519/* SPI EEPROM Status Register */
1526#define EEPROM_STATUS_RDY_SPI 0x01 1520#define EEPROM_STATUS_RDY_SPI 0x01
@@ -1530,25 +1524,25 @@ struct e1000_hw {
1530#define EEPROM_STATUS_WPEN_SPI 0x80 1524#define EEPROM_STATUS_WPEN_SPI 0x80
1531 1525
1532/* Extended Device Control */ 1526/* Extended Device Control */
1533#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ 1527#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
1534#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ 1528#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
1535#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN 1529#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
1536#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ 1530#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
1537#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ 1531#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
1538#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */ 1532#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
1539#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */ 1533#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
1540#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA 1534#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
1541#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */ 1535#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
1542#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */ 1536#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
1543#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ 1537#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
1544#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ 1538#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
1545#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ 1539#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
1546#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */ 1540#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
1547#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ 1541#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
1548#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 1542#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
1549#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ 1543#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
1550#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 1544#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
1551#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 1545#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
1552#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 1546#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
1553#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 1547#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
1554#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 1548#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
@@ -1560,11 +1554,11 @@ struct e1000_hw {
1560#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 1554#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
1561#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 1555#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
1562#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 1556#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
1563#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 1557#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
1564#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ 1558#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
1565#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ 1559#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
1566#define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */ 1560#define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */
1567#define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */ 1561#define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */
1568#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000 1562#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000
1569 1563
1570/* MDI Control */ 1564/* MDI Control */
@@ -1664,167 +1658,167 @@ struct e1000_hw {
1664#define E1000_LEDCTL_MODE_LED_OFF 0xF 1658#define E1000_LEDCTL_MODE_LED_OFF 0xF
1665 1659
1666/* Receive Address */ 1660/* Receive Address */
1667#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 1661#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
1668 1662
1669/* Interrupt Cause Read */ 1663/* Interrupt Cause Read */
1670#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 1664#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
1671#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ 1665#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
1672#define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 1666#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
1673#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ 1667#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
1674#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ 1668#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
1675#define E1000_ICR_RXO 0x00000040 /* rx overrun */ 1669#define E1000_ICR_RXO 0x00000040 /* rx overrun */
1676#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ 1670#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
1677#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ 1671#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
1678#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ 1672#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
1679#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ 1673#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
1680#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 1674#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
1681#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 1675#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
1682#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 1676#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
1683#define E1000_ICR_TXD_LOW 0x00008000 1677#define E1000_ICR_TXD_LOW 0x00008000
1684#define E1000_ICR_SRPD 0x00010000 1678#define E1000_ICR_SRPD 0x00010000
1685#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ 1679#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
1686#define E1000_ICR_MNG 0x00040000 /* Manageability event */ 1680#define E1000_ICR_MNG 0x00040000 /* Manageability event */
1687#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ 1681#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */
1688#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ 1682#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */
1689#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */ 1683#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */
1690#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */ 1684#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */
1691#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */ 1685#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */
1692#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */ 1686#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */
1693#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */ 1687#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */
1694#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */ 1688#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */
1695#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ 1689#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */
1696#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */ 1690#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */
1697#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */ 1691#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */
1698#define E1000_ICR_EPRST 0x00100000 /* ME handware reset occurs */ 1692#define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */
1699 1693
1700/* Interrupt Cause Set */ 1694/* Interrupt Cause Set */
1701#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1695#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1702#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 1696#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1703#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 1697#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
1704#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 1698#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1705#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 1699#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1706#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ 1700#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
1707#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 1701#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1708#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 1702#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1709#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 1703#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1710#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1704#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1711#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1705#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1712#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1706#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1713#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1707#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1714#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW 1708#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
1715#define E1000_ICS_SRPD E1000_ICR_SRPD 1709#define E1000_ICS_SRPD E1000_ICR_SRPD
1716#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ 1710#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */
1717#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ 1711#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */
1718#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ 1712#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */
1719#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ 1713#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1720#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ 1714#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1721#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ 1715#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1722#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1716#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1723#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1717#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1724#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1718#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1725#define E1000_ICS_DSW E1000_ICR_DSW 1719#define E1000_ICS_DSW E1000_ICR_DSW
1726#define E1000_ICS_PHYINT E1000_ICR_PHYINT 1720#define E1000_ICS_PHYINT E1000_ICR_PHYINT
1727#define E1000_ICS_EPRST E1000_ICR_EPRST 1721#define E1000_ICS_EPRST E1000_ICR_EPRST
1728 1722
1729/* Interrupt Mask Set */ 1723/* Interrupt Mask Set */
1730#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1724#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1731#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 1725#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1732#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 1726#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
1733#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 1727#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1734#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 1728#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1735#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ 1729#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
1736#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 1730#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1737#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 1731#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1738#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 1732#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1739#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1733#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1740#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1734#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1741#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1735#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1742#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1736#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1743#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW 1737#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
1744#define E1000_IMS_SRPD E1000_ICR_SRPD 1738#define E1000_IMS_SRPD E1000_ICR_SRPD
1745#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ 1739#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */
1746#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ 1740#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */
1747#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ 1741#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */
1748#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ 1742#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1749#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ 1743#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1750#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ 1744#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1751#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1745#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1752#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1746#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1753#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1747#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1754#define E1000_IMS_DSW E1000_ICR_DSW 1748#define E1000_IMS_DSW E1000_ICR_DSW
1755#define E1000_IMS_PHYINT E1000_ICR_PHYINT 1749#define E1000_IMS_PHYINT E1000_ICR_PHYINT
1756#define E1000_IMS_EPRST E1000_ICR_EPRST 1750#define E1000_IMS_EPRST E1000_ICR_EPRST
1757 1751
1758/* Interrupt Mask Clear */ 1752/* Interrupt Mask Clear */
1759#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1753#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1760#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 1754#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1761#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */ 1755#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
1762#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 1756#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1763#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 1757#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1764#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ 1758#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
1765#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 1759#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1766#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ 1760#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
1767#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 1761#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1768#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1762#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1769#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1763#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1770#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1764#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1771#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1765#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1772#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW 1766#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
1773#define E1000_IMC_SRPD E1000_ICR_SRPD 1767#define E1000_IMC_SRPD E1000_ICR_SRPD
1774#define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */ 1768#define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */
1775#define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */ 1769#define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */
1776#define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */ 1770#define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */
1777#define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ 1771#define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1778#define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ 1772#define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1779#define E1000_IMC_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ 1773#define E1000_IMC_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1780#define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1774#define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1781#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1775#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1782#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1776#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1783#define E1000_IMC_DSW E1000_ICR_DSW 1777#define E1000_IMC_DSW E1000_ICR_DSW
1784#define E1000_IMC_PHYINT E1000_ICR_PHYINT 1778#define E1000_IMC_PHYINT E1000_ICR_PHYINT
1785#define E1000_IMC_EPRST E1000_ICR_EPRST 1779#define E1000_IMC_EPRST E1000_ICR_EPRST
1786 1780
1787/* Receive Control */ 1781/* Receive Control */
1788#define E1000_RCTL_RST 0x00000001 /* Software reset */ 1782#define E1000_RCTL_RST 0x00000001 /* Software reset */
1789#define E1000_RCTL_EN 0x00000002 /* enable */ 1783#define E1000_RCTL_EN 0x00000002 /* enable */
1790#define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 1784#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
1791#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 1785#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
1792#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 1786#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
1793#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 1787#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
1794#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 1788#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
1795#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 1789#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
1796#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ 1790#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
1797#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 1791#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
1798#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ 1792#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
1799#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 1793#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
1800#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ 1794#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
1801#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ 1795#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
1802#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ 1796#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
1803#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 1797#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
1804#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ 1798#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
1805#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ 1799#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
1806#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ 1800#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
1807#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 1801#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
1808#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ 1802#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
1809#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 1803#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
1810/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 1804/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
1811#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ 1805#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
1812#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ 1806#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
1813#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ 1807#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
1814#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ 1808#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
1815/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 1809/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
1816#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ 1810#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
1817#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ 1811#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
1818#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ 1812#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
1819#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 1813#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
1820#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 1814#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
1821#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 1815#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
1822#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ 1816#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
1823#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 1817#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
1824#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 1818#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
1825#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 1819#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
1826#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */ 1820#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
1827#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */ 1821#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
1828 1822
1829/* Use byte values for the following shift parameters 1823/* Use byte values for the following shift parameters
1830 * Usage: 1824 * Usage:
@@ -1847,10 +1841,10 @@ struct e1000_hw {
1847#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 1841#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
1848#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 1842#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
1849 1843
1850#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 1844#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
1851#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 1845#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
1852#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 1846#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
1853#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 1847#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
1854 1848
1855/* SW_W_SYNC definitions */ 1849/* SW_W_SYNC definitions */
1856#define E1000_SWFW_EEP_SM 0x0001 1850#define E1000_SWFW_EEP_SM 0x0001
@@ -1859,17 +1853,17 @@ struct e1000_hw {
1859#define E1000_SWFW_MAC_CSR_SM 0x0008 1853#define E1000_SWFW_MAC_CSR_SM 0x0008
1860 1854
1861/* Receive Descriptor */ 1855/* Receive Descriptor */
1862#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */ 1856#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
1863#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */ 1857#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */
1864#define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */ 1858#define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */
1865#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */ 1859#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */
1866#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */ 1860#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */
1867 1861
1868/* Flow Control */ 1862/* Flow Control */
1869#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 1863#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
1870#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ 1864#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
1871#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 1865#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
1872#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 1866#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
1873 1867
1874/* Header split receive */ 1868/* Header split receive */
1875#define E1000_RFCTL_ISCSI_DIS 0x00000001 1869#define E1000_RFCTL_ISCSI_DIS 0x00000001
@@ -1889,64 +1883,64 @@ struct e1000_hw {
1889#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 1883#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
1890 1884
1891/* Receive Descriptor Control */ 1885/* Receive Descriptor Control */
1892#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */ 1886#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
1893#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */ 1887#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
1894#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */ 1888#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
1895#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */ 1889#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
1896 1890
1897/* Transmit Descriptor Control */ 1891/* Transmit Descriptor Control */
1898#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ 1892#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
1899#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ 1893#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
1900#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ 1894#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
1901#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 1895#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
1902#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ 1896#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
1903#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 1897#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
1904#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc. 1898#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
1905 still to be processed. */ 1899 still to be processed. */
1906/* Transmit Configuration Word */ 1900/* Transmit Configuration Word */
1907#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 1901#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
1908#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ 1902#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
1909#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 1903#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
1910#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 1904#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
1911#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 1905#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
1912#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ 1906#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
1913#define E1000_TXCW_NP 0x00008000 /* TXCW next page */ 1907#define E1000_TXCW_NP 0x00008000 /* TXCW next page */
1914#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ 1908#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
1915#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ 1909#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
1916#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 1910#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
1917 1911
1918/* Receive Configuration Word */ 1912/* Receive Configuration Word */
1919#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 1913#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
1920#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ 1914#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
1921#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 1915#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
1922#define E1000_RXCW_CC 0x10000000 /* Receive config change */ 1916#define E1000_RXCW_CC 0x10000000 /* Receive config change */
1923#define E1000_RXCW_C 0x20000000 /* Receive config */ 1917#define E1000_RXCW_C 0x20000000 /* Receive config */
1924#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 1918#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
1925#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ 1919#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
1926 1920
1927/* Transmit Control */ 1921/* Transmit Control */
1928#define E1000_TCTL_RST 0x00000001 /* software reset */ 1922#define E1000_TCTL_RST 0x00000001 /* software reset */
1929#define E1000_TCTL_EN 0x00000002 /* enable tx */ 1923#define E1000_TCTL_EN 0x00000002 /* enable tx */
1930#define E1000_TCTL_BCE 0x00000004 /* busy check enable */ 1924#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
1931#define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 1925#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
1932#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 1926#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
1933#define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 1927#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
1934#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ 1928#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
1935#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ 1929#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
1936#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 1930#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
1937#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ 1931#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
1938#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ 1932#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
1939/* Extended Transmit Control */ 1933/* Extended Transmit Control */
1940#define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */ 1934#define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */
1941#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ 1935#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
1942 1936
1943/* Receive Checksum Control */ 1937/* Receive Checksum Control */
1944#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ 1938#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
1945#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 1939#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
1946#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 1940#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
1947#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ 1941#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
1948#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 1942#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
1949#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 1943#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
1950 1944
1951/* Multiple Receive Queue Control */ 1945/* Multiple Receive Queue Control */
1952#define E1000_MRQC_ENABLE_MASK 0x00000003 1946#define E1000_MRQC_ENABLE_MASK 0x00000003
@@ -1962,141 +1956,141 @@ struct e1000_hw {
1962 1956
1963/* Definitions for power management and wakeup registers */ 1957/* Definitions for power management and wakeup registers */
1964/* Wake Up Control */ 1958/* Wake Up Control */
1965#define E1000_WUC_APME 0x00000001 /* APM Enable */ 1959#define E1000_WUC_APME 0x00000001 /* APM Enable */
1966#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 1960#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
1967#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ 1961#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
1968#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ 1962#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
1969#define E1000_WUC_SPM 0x80000000 /* Enable SPM */ 1963#define E1000_WUC_SPM 0x80000000 /* Enable SPM */
1970 1964
1971/* Wake Up Filter Control */ 1965/* Wake Up Filter Control */
1972#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 1966#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
1973#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 1967#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
1974#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 1968#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
1975#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 1969#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
1976#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 1970#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
1977#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 1971#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
1978#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 1972#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
1979#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ 1973#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
1980#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ 1974#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
1981#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 1975#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
1982#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ 1976#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
1983#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ 1977#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
1984#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ 1978#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
1985#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */ 1979#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
1986#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ 1980#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
1987#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ 1981#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1988 1982
1989/* Wake Up Status */ 1983/* Wake Up Status */
1990#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */ 1984#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
1991#define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */ 1985#define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */
1992#define E1000_WUS_EX 0x00000004 /* Directed Exact Received */ 1986#define E1000_WUS_EX 0x00000004 /* Directed Exact Received */
1993#define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */ 1987#define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */
1994#define E1000_WUS_BC 0x00000010 /* Broadcast Received */ 1988#define E1000_WUS_BC 0x00000010 /* Broadcast Received */
1995#define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */ 1989#define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */
1996#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */ 1990#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
1997#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */ 1991#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
1998#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */ 1992#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
1999#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */ 1993#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
2000#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */ 1994#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
2001#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */ 1995#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
2002#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ 1996#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
2003 1997
2004/* Management Control */ 1998/* Management Control */
2005#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 1999#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
2006#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 2000#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
2007#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ 2001#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
2008#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ 2002#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
2009#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ 2003#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
2010#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ 2004#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
2011#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ 2005#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
2012#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ 2006#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
2013#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 2007#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
2014#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery 2008#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
2015 * Filtering */ 2009 * Filtering */
2016#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */ 2010#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
2017#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ 2011#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
2018#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 2012#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
2019#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ 2013#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
2020#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */ 2014#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */
2021#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 2015#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
2022#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address 2016#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address
2023 * filtering */ 2017 * filtering */
2024#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host 2018#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host
2025 * memory */ 2019 * memory */
2026#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address 2020#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address
2027 * filtering */ 2021 * filtering */
2028#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ 2022#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */
2029#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ 2023#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
2030#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ 2024#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
2031#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ 2025#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
2032#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ 2026#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
2033#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ 2027#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
2034#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ 2028#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
2035#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ 2029#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
2036 2030
2037#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ 2031#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
2038#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ 2032#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
2039 2033
2040/* SW Semaphore Register */ 2034/* SW Semaphore Register */
2041#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 2035#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
2042#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 2036#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
2043#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 2037#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
2044#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 2038#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
2045 2039
2046/* FW Semaphore Register */ 2040/* FW Semaphore Register */
2047#define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */ 2041#define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */
2048#define E1000_FWSM_MODE_SHIFT 1 2042#define E1000_FWSM_MODE_SHIFT 1
2049#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */ 2043#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */
2050 2044
2051#define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */ 2045#define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */
2052#define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */ 2046#define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */
2053#define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */ 2047#define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */
2054#define E1000_FWSM_SKUEL_SHIFT 29 2048#define E1000_FWSM_SKUEL_SHIFT 29
2055#define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */ 2049#define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */
2056#define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */ 2050#define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */
2057#define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */ 2051#define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */
2058#define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */ 2052#define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */
2059 2053
2060/* FFLT Debug Register */ 2054/* FFLT Debug Register */
2061#define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */ 2055#define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */
2062 2056
2063typedef enum { 2057typedef enum {
2064 e1000_mng_mode_none = 0, 2058 e1000_mng_mode_none = 0,
2065 e1000_mng_mode_asf, 2059 e1000_mng_mode_asf,
2066 e1000_mng_mode_pt, 2060 e1000_mng_mode_pt,
2067 e1000_mng_mode_ipmi, 2061 e1000_mng_mode_ipmi,
2068 e1000_mng_mode_host_interface_only 2062 e1000_mng_mode_host_interface_only
2069} e1000_mng_mode; 2063} e1000_mng_mode;
2070 2064
2071/* Host Inteface Control Register */ 2065/* Host Interface Control Register */
2072#define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */ 2066#define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */
2073#define E1000_HICR_C 0x00000002 /* Driver sets this bit when done 2067#define E1000_HICR_C 0x00000002 /* Driver sets this bit when done
2074 * to put command in RAM */ 2068 * to put command in RAM */
2075#define E1000_HICR_SV 0x00000004 /* Status Validity */ 2069#define E1000_HICR_SV 0x00000004 /* Status Validity */
2076#define E1000_HICR_FWR 0x00000080 /* FW reset. Set by the Host */ 2070#define E1000_HICR_FWR 0x00000080 /* FW reset. Set by the Host */
2077 2071
2078/* Host Interface Command Interface - Address range 0x8800-0x8EFF */ 2072/* Host Interface Command Interface - Address range 0x8800-0x8EFF */
2079#define E1000_HI_MAX_DATA_LENGTH 252 /* Host Interface data length */ 2073#define E1000_HI_MAX_DATA_LENGTH 252 /* Host Interface data length */
2080#define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */ 2074#define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */
2081#define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */ 2075#define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */
2082#define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */ 2076#define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */
2083 2077
2084struct e1000_host_command_header { 2078struct e1000_host_command_header {
2085 u8 command_id; 2079 u8 command_id;
2086 u8 command_length; 2080 u8 command_length;
2087 u8 command_options; /* I/F bits for command, status for return */ 2081 u8 command_options; /* I/F bits for command, status for return */
2088 u8 checksum; 2082 u8 checksum;
2089}; 2083};
2090struct e1000_host_command_info { 2084struct e1000_host_command_info {
2091 struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ 2085 struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
2092 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */ 2086 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */
2093}; 2087};
2094 2088
2095/* Host SMB register #0 */ 2089/* Host SMB register #0 */
2096#define E1000_HSMC0R_CLKIN 0x00000001 /* SMB Clock in */ 2090#define E1000_HSMC0R_CLKIN 0x00000001 /* SMB Clock in */
2097#define E1000_HSMC0R_DATAIN 0x00000002 /* SMB Data in */ 2091#define E1000_HSMC0R_DATAIN 0x00000002 /* SMB Data in */
2098#define E1000_HSMC0R_DATAOUT 0x00000004 /* SMB Data out */ 2092#define E1000_HSMC0R_DATAOUT 0x00000004 /* SMB Data out */
2099#define E1000_HSMC0R_CLKOUT 0x00000008 /* SMB Clock out */ 2093#define E1000_HSMC0R_CLKOUT 0x00000008 /* SMB Clock out */
2100 2094
2101/* Host SMB register #1 */ 2095/* Host SMB register #1 */
2102#define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN 2096#define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN
@@ -2105,10 +2099,10 @@ struct e1000_host_command_info {
2105#define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT 2099#define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT
2106 2100
2107/* FW Status Register */ 2101/* FW Status Register */
2108#define E1000_FWSTS_FWS_MASK 0x000000FF /* FW Status */ 2102#define E1000_FWSTS_FWS_MASK 0x000000FF /* FW Status */
2109 2103
2110/* Wake Up Packet Length */ 2104/* Wake Up Packet Length */
2111#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ 2105#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
2112 2106
2113#define E1000_MDALIGN 4096 2107#define E1000_MDALIGN 4096
2114 2108
@@ -2162,24 +2156,24 @@ struct e1000_host_command_info {
2162#define PCI_EX_LINK_WIDTH_SHIFT 4 2156#define PCI_EX_LINK_WIDTH_SHIFT 4
2163 2157
2164/* EEPROM Commands - Microwire */ 2158/* EEPROM Commands - Microwire */
2165#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */ 2159#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
2166#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */ 2160#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
2167#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */ 2161#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */
2168#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */ 2162#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */
2169#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */ 2163#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erase/write disable */
2170 2164
2171/* EEPROM Commands - SPI */ 2165/* EEPROM Commands - SPI */
2172#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 2166#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
2173#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ 2167#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
2174#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ 2168#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
2175#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 2169#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
2176#define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */ 2170#define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */
2177#define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */ 2171#define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */
2178#define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */ 2172#define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */
2179#define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */ 2173#define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */
2180#define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ 2174#define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
2181#define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ 2175#define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
2182#define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ 2176#define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
2183 2177
2184/* EEPROM Size definitions */ 2178/* EEPROM Size definitions */
2185#define EEPROM_WORD_SIZE_SHIFT 6 2179#define EEPROM_WORD_SIZE_SHIFT 6
@@ -2190,7 +2184,7 @@ struct e1000_host_command_info {
2190#define EEPROM_COMPAT 0x0003 2184#define EEPROM_COMPAT 0x0003
2191#define EEPROM_ID_LED_SETTINGS 0x0004 2185#define EEPROM_ID_LED_SETTINGS 0x0004
2192#define EEPROM_VERSION 0x0005 2186#define EEPROM_VERSION 0x0005
2193#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */ 2187#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */
2194#define EEPROM_PHY_CLASS_WORD 0x0007 2188#define EEPROM_PHY_CLASS_WORD 0x0007
2195#define EEPROM_INIT_CONTROL1_REG 0x000A 2189#define EEPROM_INIT_CONTROL1_REG 0x000A
2196#define EEPROM_INIT_CONTROL2_REG 0x000F 2190#define EEPROM_INIT_CONTROL2_REG 0x000F
@@ -2203,8 +2197,8 @@ struct e1000_host_command_info {
2203#define EEPROM_FLASH_VERSION 0x0032 2197#define EEPROM_FLASH_VERSION 0x0032
2204#define EEPROM_CHECKSUM_REG 0x003F 2198#define EEPROM_CHECKSUM_REG 0x003F
2205 2199
2206#define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */ 2200#define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */
2207#define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */ 2201#define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */
2208 2202
2209/* Word definitions for ID LED Settings */ 2203/* Word definitions for ID LED Settings */
2210#define ID_LED_RESERVED_0000 0x0000 2204#define ID_LED_RESERVED_0000 0x0000
@@ -2227,7 +2221,6 @@ struct e1000_host_command_info {
2227#define IGP_ACTIVITY_LED_ENABLE 0x0300 2221#define IGP_ACTIVITY_LED_ENABLE 0x0300
2228#define IGP_LED3_MODE 0x07000000 2222#define IGP_LED3_MODE 0x07000000
2229 2223
2230
2231/* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */ 2224/* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */
2232#define EEPROM_SERDES_AMPLITUDE_MASK 0x000F 2225#define EEPROM_SERDES_AMPLITUDE_MASK 0x000F
2233 2226
@@ -2332,9 +2325,9 @@ struct e1000_host_command_info {
2332#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 2325#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
2333 2326
2334/* PBA constants */ 2327/* PBA constants */
2335#define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */ 2328#define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */
2336#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */ 2329#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */
2337#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ 2330#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
2338#define E1000_PBA_20K 0x0014 2331#define E1000_PBA_20K 0x0014
2339#define E1000_PBA_22K 0x0016 2332#define E1000_PBA_22K 0x0016
2340#define E1000_PBA_24K 0x0018 2333#define E1000_PBA_24K 0x0018
@@ -2343,7 +2336,7 @@ struct e1000_host_command_info {
2343#define E1000_PBA_34K 0x0022 2336#define E1000_PBA_34K 0x0022
2344#define E1000_PBA_38K 0x0026 2337#define E1000_PBA_38K 0x0026
2345#define E1000_PBA_40K 0x0028 2338#define E1000_PBA_40K 0x0028
2346#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */ 2339#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
2347 2340
2348#define E1000_PBS_16K E1000_PBA_16K 2341#define E1000_PBS_16K E1000_PBA_16K
2349 2342
@@ -2353,9 +2346,9 @@ struct e1000_host_command_info {
2353#define FLOW_CONTROL_TYPE 0x8808 2346#define FLOW_CONTROL_TYPE 0x8808
2354 2347
2355/* The historical defaults for the flow control values are given below. */ 2348/* The historical defaults for the flow control values are given below. */
2356#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */ 2349#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
2357#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */ 2350#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
2358#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */ 2351#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
2359 2352
2360/* PCIX Config space */ 2353/* PCIX Config space */
2361#define PCIX_COMMAND_REGISTER 0xE6 2354#define PCIX_COMMAND_REGISTER 0xE6
@@ -2369,7 +2362,6 @@ struct e1000_host_command_info {
2369#define PCIX_STATUS_HI_MMRBC_4K 0x3 2362#define PCIX_STATUS_HI_MMRBC_4K 0x3
2370#define PCIX_STATUS_HI_MMRBC_2K 0x2 2363#define PCIX_STATUS_HI_MMRBC_2K 0x2
2371 2364
2372
2373/* Number of bits required to shift right the "pause" bits from the 2365/* Number of bits required to shift right the "pause" bits from the
2374 * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register. 2366 * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register.
2375 */ 2367 */
@@ -2390,7 +2382,6 @@ struct e1000_host_command_info {
2390 */ 2382 */
2391#define ILOS_SHIFT 3 2383#define ILOS_SHIFT 3
2392 2384
2393
2394#define RECEIVE_BUFFER_ALIGN_SIZE (256) 2385#define RECEIVE_BUFFER_ALIGN_SIZE (256)
2395 2386
2396/* Number of milliseconds we wait for auto-negotiation to complete */ 2387/* Number of milliseconds we wait for auto-negotiation to complete */
@@ -2443,7 +2434,6 @@ struct e1000_host_command_info {
2443 (((length) > (adapter)->min_frame_size) && \ 2434 (((length) > (adapter)->min_frame_size) && \
2444 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1))))) 2435 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
2445 2436
2446
2447/* Structures, enums, and macros for the PHY */ 2437/* Structures, enums, and macros for the PHY */
2448 2438
2449/* Bit definitions for the Management Data IO (MDIO) and Management Data 2439/* Bit definitions for the Management Data IO (MDIO) and Management Data
@@ -2460,49 +2450,49 @@ struct e1000_host_command_info {
2460 2450
2461/* PHY 1000 MII Register/Bit Definitions */ 2451/* PHY 1000 MII Register/Bit Definitions */
2462/* PHY Registers defined by IEEE */ 2452/* PHY Registers defined by IEEE */
2463#define PHY_CTRL 0x00 /* Control Register */ 2453#define PHY_CTRL 0x00 /* Control Register */
2464#define PHY_STATUS 0x01 /* Status Regiser */ 2454#define PHY_STATUS 0x01 /* Status Register */
2465#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 2455#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
2466#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 2456#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
2467#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 2457#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
2468#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 2458#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
2469#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 2459#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
2470#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ 2460#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
2471#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ 2461#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
2472#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 2462#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
2473#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 2463#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
2474#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 2464#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
2475 2465
2476#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 2466#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
2477#define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */ 2467#define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */
2478 2468
2479/* M88E1000 Specific Registers */ 2469/* M88E1000 Specific Registers */
2480#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 2470#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
2481#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 2471#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
2482#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ 2472#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
2483#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ 2473#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
2484#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 2474#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
2485#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ 2475#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
2486 2476
2487#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ 2477#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
2488#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ 2478#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
2489#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 2479#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
2490#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ 2480#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
2491#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ 2481#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
2492 2482
2493#define IGP01E1000_IEEE_REGS_PAGE 0x0000 2483#define IGP01E1000_IEEE_REGS_PAGE 0x0000
2494#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300 2484#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
2495#define IGP01E1000_IEEE_FORCE_GIGA 0x0140 2485#define IGP01E1000_IEEE_FORCE_GIGA 0x0140
2496 2486
2497/* IGP01E1000 Specific Registers */ 2487/* IGP01E1000 Specific Registers */
2498#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */ 2488#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
2499#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */ 2489#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
2500#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */ 2490#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
2501#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */ 2491#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
2502#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */ 2492#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
2503#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */ 2493#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
2504#define IGP02E1000_PHY_POWER_MGMT 0x19 2494#define IGP02E1000_PHY_POWER_MGMT 0x19
2505#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */ 2495#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
2506 2496
2507/* IGP01E1000 AGC Registers - stores the cable length values*/ 2497/* IGP01E1000 AGC Registers - stores the cable length values*/
2508#define IGP01E1000_PHY_AGC_A 0x1172 2498#define IGP01E1000_PHY_AGC_A 0x1172
@@ -2546,118 +2536,118 @@ struct e1000_host_command_info {
2546#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0 2536#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
2547 2537
2548/* PHY Control Register */ 2538/* PHY Control Register */
2549#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ 2539#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
2550#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ 2540#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
2551#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 2541#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
2552#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 2542#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
2553#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ 2543#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
2554#define MII_CR_POWER_DOWN 0x0800 /* Power down */ 2544#define MII_CR_POWER_DOWN 0x0800 /* Power down */
2555#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 2545#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
2556#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ 2546#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
2557#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 2547#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
2558#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 2548#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
2559 2549
2560/* PHY Status Register */ 2550/* PHY Status Register */
2561#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ 2551#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
2562#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ 2552#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
2563#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 2553#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
2564#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ 2554#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
2565#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ 2555#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
2566#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 2556#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
2567#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ 2557#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
2568#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ 2558#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
2569#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ 2559#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
2570#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ 2560#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
2571#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ 2561#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
2572#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ 2562#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
2573#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ 2563#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
2574#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ 2564#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
2575#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ 2565#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
2576 2566
2577/* Autoneg Advertisement Register */ 2567/* Autoneg Advertisement Register */
2578#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ 2568#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
2579#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 2569#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
2580#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 2570#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
2581#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 2571#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
2582#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 2572#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
2583#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ 2573#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
2584#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 2574#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
2585#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 2575#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
2586#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ 2576#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
2587#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 2577#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
2588 2578
2589/* Link Partner Ability Register (Base Page) */ 2579/* Link Partner Ability Register (Base Page) */
2590#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ 2580#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
2591#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ 2581#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
2592#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ 2582#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
2593#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ 2583#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
2594#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ 2584#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
2595#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ 2585#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
2596#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 2586#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
2597#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 2587#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
2598#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ 2588#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
2599#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ 2589#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
2600#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 2590#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
2601 2591
2602/* Autoneg Expansion Register */ 2592/* Autoneg Expansion Register */
2603#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ 2593#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
2604#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ 2594#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
2605#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ 2595#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
2606#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ 2596#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
2607#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */ 2597#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */
2608 2598
2609/* Next Page TX Register */ 2599/* Next Page TX Register */
2610#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ 2600#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2611#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges 2601#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
2612 * of different NP 2602 * of different NP
2613 */ 2603 */
2614#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg 2604#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2615 * 0 = cannot comply with msg 2605 * 0 = cannot comply with msg
2616 */ 2606 */
2617#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ 2607#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2618#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow 2608#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2619 * 0 = sending last NP 2609 * 0 = sending last NP
2620 */ 2610 */
2621 2611
2622/* Link Partner Next Page Register */ 2612/* Link Partner Next Page Register */
2623#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ 2613#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2624#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges 2614#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
2625 * of different NP 2615 * of different NP
2626 */ 2616 */
2627#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg 2617#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2628 * 0 = cannot comply with msg 2618 * 0 = cannot comply with msg
2629 */ 2619 */
2630#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ 2620#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2631#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */ 2621#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
2632#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow 2622#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2633 * 0 = sending last NP 2623 * 0 = sending last NP
2634 */ 2624 */
2635 2625
2636/* 1000BASE-T Control Register */ 2626/* 1000BASE-T Control Register */
2637#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ 2627#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
2638#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 2628#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
2639#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 2629#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
2640#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ 2630#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
2641 /* 0=DTE device */ 2631 /* 0=DTE device */
2642#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ 2632#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
2643 /* 0=Configure PHY as Slave */ 2633 /* 0=Configure PHY as Slave */
2644#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ 2634#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
2645 /* 0=Automatic Master/Slave config */ 2635 /* 0=Automatic Master/Slave config */
2646#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ 2636#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
2647#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ 2637#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
2648#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ 2638#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
2649#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ 2639#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
2650#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ 2640#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
2651 2641
2652/* 1000BASE-T Status Register */ 2642/* 1000BASE-T Status Register */
2653#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ 2643#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
2654#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ 2644#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
2655#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ 2645#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
2656#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ 2646#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
2657#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 2647#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
2658#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 2648#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
2659#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ 2649#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
2660#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ 2650#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
2661#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12 2651#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
2662#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13 2652#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
2663#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 2653#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
@@ -2665,64 +2655,64 @@ struct e1000_host_command_info {
2665#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100 2655#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
2666 2656
2667/* Extended Status Register */ 2657/* Extended Status Register */
2668#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ 2658#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
2669#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ 2659#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
2670#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ 2660#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
2671#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ 2661#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
2672 2662
2673#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */ 2663#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
2674#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */ 2664#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
2675 2665
2676#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */ 2666#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
2677 /* (0=enable, 1=disable) */ 2667 /* (0=enable, 1=disable) */
2678 2668
2679/* M88E1000 PHY Specific Control Register */ 2669/* M88E1000 PHY Specific Control Register */
2680#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ 2670#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
2681#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ 2671#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
2682#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ 2672#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
2683#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, 2673#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
2684 * 0=CLK125 toggling 2674 * 0=CLK125 toggling
2685 */ 2675 */
2686#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 2676#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
2687 /* Manual MDI configuration */ 2677 /* Manual MDI configuration */
2688#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 2678#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
2689#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, 2679#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
2690 * 100BASE-TX/10BASE-T: 2680 * 100BASE-TX/10BASE-T:
2691 * MDI Mode 2681 * MDI Mode
2692 */ 2682 */
2693#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled 2683#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
2694 * all speeds. 2684 * all speeds.
2695 */ 2685 */
2696#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080 2686#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
2697 /* 1=Enable Extended 10BASE-T distance 2687 /* 1=Enable Extended 10BASE-T distance
2698 * (Lower 10BASE-T RX Threshold) 2688 * (Lower 10BASE-T RX Threshold)
2699 * 0=Normal 10BASE-T RX Threshold */ 2689 * 0=Normal 10BASE-T RX Threshold */
2700#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 2690#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
2701 /* 1=5-Bit interface in 100BASE-TX 2691 /* 1=5-Bit interface in 100BASE-TX
2702 * 0=MII interface in 100BASE-TX */ 2692 * 0=MII interface in 100BASE-TX */
2703#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ 2693#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
2704#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ 2694#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
2705#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 2695#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
2706 2696
2707#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1 2697#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
2708#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5 2698#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
2709#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7 2699#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
2710 2700
2711/* M88E1000 PHY Specific Status Register */ 2701/* M88E1000 PHY Specific Status Register */
2712#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ 2702#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
2713#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 2703#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
2714#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 2704#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
2715#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 2705#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
2716#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M; 2706#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
2717 * 3=110-140M;4=>140M */ 2707 * 3=110-140M;4=>140M */
2718#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ 2708#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
2719#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ 2709#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
2720#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ 2710#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
2721#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ 2711#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
2722#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 2712#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
2723#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ 2713#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
2724#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ 2714#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
2725#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 2715#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
2726 2716
2727#define M88E1000_PSSR_REV_POLARITY_SHIFT 1 2717#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
2728#define M88E1000_PSSR_DOWNSHIFT_SHIFT 5 2718#define M88E1000_PSSR_DOWNSHIFT_SHIFT 5
@@ -2730,12 +2720,12 @@ struct e1000_host_command_info {
2730#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 2720#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
2731 2721
2732/* M88E1000 Extended PHY Specific Control Register */ 2722/* M88E1000 Extended PHY Specific Control Register */
2733#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ 2723#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
2734#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled. 2724#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
2735 * Will assert lost lock and bring 2725 * Will assert lost lock and bring
2736 * link down if idle not seen 2726 * link down if idle not seen
2737 * within 1ms in 1000BASE-T 2727 * within 1ms in 1000BASE-T
2738 */ 2728 */
2739/* Number of times we will attempt to autonegotiate before downshifting if we 2729/* Number of times we will attempt to autonegotiate before downshifting if we
2740 * are the master */ 2730 * are the master */
2741#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 2731#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
@@ -2750,9 +2740,9 @@ struct e1000_host_command_info {
2750#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 2740#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
2751#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 2741#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
2752#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 2742#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
2753#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ 2743#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
2754#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 2744#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
2755#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ 2745#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
2756 2746
2757/* M88EC018 Rev 2 specific DownShift settings */ 2747/* M88EC018 Rev 2 specific DownShift settings */
2758#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 2748#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
@@ -2774,18 +2764,18 @@ struct e1000_host_command_info {
2774#define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000 2764#define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000
2775 2765
2776/* IGP01E1000 Specific Port Status Register - R/O */ 2766/* IGP01E1000 Specific Port Status Register - R/O */
2777#define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */ 2767#define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */
2778#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 2768#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
2779#define IGP01E1000_PSSR_CABLE_LENGTH 0x007C 2769#define IGP01E1000_PSSR_CABLE_LENGTH 0x007C
2780#define IGP01E1000_PSSR_FULL_DUPLEX 0x0200 2770#define IGP01E1000_PSSR_FULL_DUPLEX 0x0200
2781#define IGP01E1000_PSSR_LINK_UP 0x0400 2771#define IGP01E1000_PSSR_LINK_UP 0x0400
2782#define IGP01E1000_PSSR_MDIX 0x0800 2772#define IGP01E1000_PSSR_MDIX 0x0800
2783#define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */ 2773#define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */
2784#define IGP01E1000_PSSR_SPEED_10MBPS 0x4000 2774#define IGP01E1000_PSSR_SPEED_10MBPS 0x4000
2785#define IGP01E1000_PSSR_SPEED_100MBPS 0x8000 2775#define IGP01E1000_PSSR_SPEED_100MBPS 0x8000
2786#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 2776#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
2787#define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */ 2777#define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */
2788#define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */ 2778#define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */
2789 2779
2790/* IGP01E1000 Specific Port Control Register - R/W */ 2780/* IGP01E1000 Specific Port Control Register - R/W */
2791#define IGP01E1000_PSCR_TP_LOOPBACK 0x0010 2781#define IGP01E1000_PSCR_TP_LOOPBACK 0x0010
@@ -2793,16 +2783,16 @@ struct e1000_host_command_info {
2793#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400 2783#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
2794#define IGP01E1000_PSCR_FLIP_CHIP 0x0800 2784#define IGP01E1000_PSCR_FLIP_CHIP 0x0800
2795#define IGP01E1000_PSCR_AUTO_MDIX 0x1000 2785#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
2796#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */ 2786#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
2797 2787
2798/* IGP01E1000 Specific Port Link Health Register */ 2788/* IGP01E1000 Specific Port Link Health Register */
2799#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 2789#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
2800#define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000 2790#define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000
2801#define IGP01E1000_PLHR_MASTER_FAULT 0x2000 2791#define IGP01E1000_PLHR_MASTER_FAULT 0x2000
2802#define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000 2792#define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000
2803#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */ 2793#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */
2804#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */ 2794#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */
2805#define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */ 2795#define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */
2806#define IGP01E1000_PLHR_DATA_ERR_0 0x0100 2796#define IGP01E1000_PLHR_DATA_ERR_0 0x0100
2807#define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040 2797#define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040
2808#define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010 2798#define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010
@@ -2817,9 +2807,9 @@ struct e1000_host_command_info {
2817#define IGP01E1000_MSE_CHANNEL_B 0x0F00 2807#define IGP01E1000_MSE_CHANNEL_B 0x0F00
2818#define IGP01E1000_MSE_CHANNEL_A 0xF000 2808#define IGP01E1000_MSE_CHANNEL_A 0xF000
2819 2809
2820#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ 2810#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
2821#define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */ 2811#define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */
2822#define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in D0a mode */ 2812#define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in D0a mode */
2823 2813
2824/* IGP01E1000 DSP reset macros */ 2814/* IGP01E1000 DSP reset macros */
2825#define DSP_RESET_ENABLE 0x0 2815#define DSP_RESET_ENABLE 0x0
@@ -2828,8 +2818,8 @@ struct e1000_host_command_info {
2828 2818
2829/* IGP01E1000 & IGP02E1000 AGC Registers */ 2819/* IGP01E1000 & IGP02E1000 AGC Registers */
2830 2820
2831#define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */ 2821#define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */
2832#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */ 2822#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */
2833 2823
2834/* IGP02E1000 AGC Register Length 9-bit mask */ 2824/* IGP02E1000 AGC Register Length 9-bit mask */
2835#define IGP02E1000_AGC_LENGTH_MASK 0x7F 2825#define IGP02E1000_AGC_LENGTH_MASK 0x7F
@@ -2847,9 +2837,9 @@ struct e1000_host_command_info {
2847#define IGP01E1000_PHY_POLARITY_MASK 0x0078 2837#define IGP01E1000_PHY_POLARITY_MASK 0x0078
2848 2838
2849/* IGP01E1000 GMII FIFO Register */ 2839/* IGP01E1000 GMII FIFO Register */
2850#define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed 2840#define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed
2851 * on Link-Up */ 2841 * on Link-Up */
2852#define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */ 2842#define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */
2853 2843
2854/* IGP01E1000 Analog Register */ 2844/* IGP01E1000 Analog Register */
2855#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1 2845#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
@@ -2883,7 +2873,6 @@ struct e1000_host_command_info {
2883#define M88E1111_I_PHY_ID 0x01410CC0 2873#define M88E1111_I_PHY_ID 0x01410CC0
2884#define L1LXT971A_PHY_ID 0x001378E0 2874#define L1LXT971A_PHY_ID 0x001378E0
2885 2875
2886
2887/* Bits... 2876/* Bits...
2888 * 15-5: page 2877 * 15-5: page
2889 * 4-0: register offset 2878 * 4-0: register offset
@@ -2893,41 +2882,41 @@ struct e1000_host_command_info {
2893 (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 2882 (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
2894 2883
2895#define IGP3_PHY_PORT_CTRL \ 2884#define IGP3_PHY_PORT_CTRL \
2896 PHY_REG(769, 17) /* Port General Configuration */ 2885 PHY_REG(769, 17) /* Port General Configuration */
2897#define IGP3_PHY_RATE_ADAPT_CTRL \ 2886#define IGP3_PHY_RATE_ADAPT_CTRL \
2898 PHY_REG(769, 25) /* Rate Adapter Control Register */ 2887 PHY_REG(769, 25) /* Rate Adapter Control Register */
2899 2888
2900#define IGP3_KMRN_FIFO_CTRL_STATS \ 2889#define IGP3_KMRN_FIFO_CTRL_STATS \
2901 PHY_REG(770, 16) /* KMRN FIFO's control/status register */ 2890 PHY_REG(770, 16) /* KMRN FIFO's control/status register */
2902#define IGP3_KMRN_POWER_MNG_CTRL \ 2891#define IGP3_KMRN_POWER_MNG_CTRL \
2903 PHY_REG(770, 17) /* KMRN Power Management Control Register */ 2892 PHY_REG(770, 17) /* KMRN Power Management Control Register */
2904#define IGP3_KMRN_INBAND_CTRL \ 2893#define IGP3_KMRN_INBAND_CTRL \
2905 PHY_REG(770, 18) /* KMRN Inband Control Register */ 2894 PHY_REG(770, 18) /* KMRN Inband Control Register */
2906#define IGP3_KMRN_DIAG \ 2895#define IGP3_KMRN_DIAG \
2907 PHY_REG(770, 19) /* KMRN Diagnostic register */ 2896 PHY_REG(770, 19) /* KMRN Diagnostic register */
2908#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 /* RX PCS is not synced */ 2897#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 /* RX PCS is not synced */
2909#define IGP3_KMRN_ACK_TIMEOUT \ 2898#define IGP3_KMRN_ACK_TIMEOUT \
2910 PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */ 2899 PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */
2911 2900
2912#define IGP3_VR_CTRL \ 2901#define IGP3_VR_CTRL \
2913 PHY_REG(776, 18) /* Voltage regulator control register */ 2902 PHY_REG(776, 18) /* Voltage regulator control register */
2914#define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */ 2903#define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */
2915#define IGP3_VR_CTRL_MODE_MASK 0x0300 /* Shutdown VR Mask */ 2904#define IGP3_VR_CTRL_MODE_MASK 0x0300 /* Shutdown VR Mask */
2916 2905
2917#define IGP3_CAPABILITY \ 2906#define IGP3_CAPABILITY \
2918 PHY_REG(776, 19) /* IGP3 Capability Register */ 2907 PHY_REG(776, 19) /* IGP3 Capability Register */
2919 2908
2920/* Capabilities for SKU Control */ 2909/* Capabilities for SKU Control */
2921#define IGP3_CAP_INITIATE_TEAM 0x0001 /* Able to initiate a team */ 2910#define IGP3_CAP_INITIATE_TEAM 0x0001 /* Able to initiate a team */
2922#define IGP3_CAP_WFM 0x0002 /* Support WoL and PXE */ 2911#define IGP3_CAP_WFM 0x0002 /* Support WoL and PXE */
2923#define IGP3_CAP_ASF 0x0004 /* Support ASF */ 2912#define IGP3_CAP_ASF 0x0004 /* Support ASF */
2924#define IGP3_CAP_LPLU 0x0008 /* Support Low Power Link Up */ 2913#define IGP3_CAP_LPLU 0x0008 /* Support Low Power Link Up */
2925#define IGP3_CAP_DC_AUTO_SPEED 0x0010 /* Support AC/DC Auto Link Speed */ 2914#define IGP3_CAP_DC_AUTO_SPEED 0x0010 /* Support AC/DC Auto Link Speed */
2926#define IGP3_CAP_SPD 0x0020 /* Support Smart Power Down */ 2915#define IGP3_CAP_SPD 0x0020 /* Support Smart Power Down */
2927#define IGP3_CAP_MULT_QUEUE 0x0040 /* Support 2 tx & 2 rx queues */ 2916#define IGP3_CAP_MULT_QUEUE 0x0040 /* Support 2 tx & 2 rx queues */
2928#define IGP3_CAP_RSS 0x0080 /* Support RSS */ 2917#define IGP3_CAP_RSS 0x0080 /* Support RSS */
2929#define IGP3_CAP_8021PQ 0x0100 /* Support 802.1Q & 802.1p */ 2918#define IGP3_CAP_8021PQ 0x0100 /* Support 802.1Q & 802.1p */
2930#define IGP3_CAP_AMT_CB 0x0200 /* Support active manageability and circuit breaker */ 2919#define IGP3_CAP_AMT_CB 0x0200 /* Support active manageability and circuit breaker */
2931 2920
2932#define IGP3_PPC_JORDAN_EN 0x0001 2921#define IGP3_PPC_JORDAN_EN 0x0001
2933#define IGP3_PPC_JORDAN_GIGA_SPEED 0x0002 2922#define IGP3_PPC_JORDAN_GIGA_SPEED 0x0002
@@ -2937,69 +2926,69 @@ struct e1000_host_command_info {
2937#define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA 0x0020 2926#define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA 0x0020
2938#define IGP3_KMRN_PMC_K0S_MODE1_EN_100 0x0040 2927#define IGP3_KMRN_PMC_K0S_MODE1_EN_100 0x0040
2939 2928
2940#define IGP3E1000_PHY_MISC_CTRL 0x1B /* Misc. Ctrl register */ 2929#define IGP3E1000_PHY_MISC_CTRL 0x1B /* Misc. Ctrl register */
2941#define IGP3_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Duplex Manual Set */ 2930#define IGP3_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Duplex Manual Set */
2942 2931
2943#define IGP3_KMRN_EXT_CTRL PHY_REG(770, 18) 2932#define IGP3_KMRN_EXT_CTRL PHY_REG(770, 18)
2944#define IGP3_KMRN_EC_DIS_INBAND 0x0080 2933#define IGP3_KMRN_EC_DIS_INBAND 0x0080
2945 2934
2946#define IGP03E1000_E_PHY_ID 0x02A80390 2935#define IGP03E1000_E_PHY_ID 0x02A80390
2947#define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */ 2936#define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */
2948#define IFE_PLUS_E_PHY_ID 0x02A80320 2937#define IFE_PLUS_E_PHY_ID 0x02A80320
2949#define IFE_C_E_PHY_ID 0x02A80310 2938#define IFE_C_E_PHY_ID 0x02A80310
2950 2939
2951#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, Control and Address */ 2940#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, Control and Address */
2952#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */ 2941#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */
2953#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False Carrier Counter */ 2942#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False Carrier Counter */
2954#define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet Counter */ 2943#define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnect Counter */
2955#define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error Frame Counter */ 2944#define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error Frame Counter */
2956#define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error Counter */ 2945#define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error Counter */
2957#define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive Premature End Of Frame Error Counter */ 2946#define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive Premature End Of Frame Error Counter */
2958#define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of Frame Error Counter */ 2947#define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of Frame Error Counter */
2959#define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber Detect Counter */ 2948#define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber Detect Counter */
2960#define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and Status */ 2949#define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and Status */
2961#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and LED configuration */ 2950#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and LED configuration */
2962#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */ 2951#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */
2963#define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control (HWI) */ 2952#define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control (HWI) */
2964 2953
2965#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Defaut 1 = Disable auto reduced power down */ 2954#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Default 1 = Disable auto reduced power down */
2966#define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */ 2955#define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */
2967#define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */ 2956#define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */
2968#define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */ 2957#define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */
2969#define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY address */ 2958#define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY address */
2970#define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */ 2959#define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */
2971#define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation duplex result 1=Full, 0=Half */ 2960#define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation duplex result 1=Full, 0=Half */
2972#define IFE_PESC_POLARITY_REVERSED_SHIFT 8 2961#define IFE_PESC_POLARITY_REVERSED_SHIFT 8
2973 2962
2974#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dyanmic Power Down disabled */ 2963#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dynamic Power Down disabled */
2975#define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, 0=Normal */ 2964#define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, 0=Normal */
2976#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity Disabled, 0=Enabled */ 2965#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity Disabled, 0=Enabled */
2977#define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, 0=Normal Jabber Operation */ 2966#define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, 0=Normal Jabber Operation */
2978#define IFE_PSC_FORCE_POLARITY_SHIFT 5 2967#define IFE_PSC_FORCE_POLARITY_SHIFT 5
2979#define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4 2968#define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4
2980 2969
2981#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X feature, default 0=disabled */ 2970#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X feature, default 0=disabled */
2982#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, 0=force MDI */ 2971#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, 0=force MDI */
2983#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ 2972#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
2984#define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorithm is completed */ 2973#define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorithm is completed */
2985#define IFE_PMC_MDIX_MODE_SHIFT 6 2974#define IFE_PMC_MDIX_MODE_SHIFT 6
2986#define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */ 2975#define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */
2987 2976
2988#define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI feature */ 2977#define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI feature */
2989#define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed, 0=failed */ 2978#define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed, 0=failed */
2990#define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses on the wire */ 2979#define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses on the wire */
2991#define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */ 2980#define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */
2992#define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */ 2981#define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */
2993#define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication type of problem on the line */ 2982#define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication type of problem on the line */
2994#define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to the cable problem, in 80cm granularity */ 2983#define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to the cable problem, in 80cm granularity */
2995#define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */ 2984#define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */
2996#define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */ 2985#define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */
2997#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ 2986#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
2998#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ 2987#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
2999 2988
3000#define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */ 2989#define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */
3001#define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */ 2990#define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */
3002#define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */ 2991#define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */
3003#define ICH_FLASH_SEG_SIZE_256 256 2992#define ICH_FLASH_SEG_SIZE_256 256
3004#define ICH_FLASH_SEG_SIZE_4K 4096 2993#define ICH_FLASH_SEG_SIZE_4K 4096
3005#define ICH_FLASH_SEG_SIZE_64K 65536 2994#define ICH_FLASH_SEG_SIZE_64K 65536
@@ -3043,10 +3032,10 @@ struct e1000_host_command_info {
3043#define MII_CR_SPEED_100 0x2000 3032#define MII_CR_SPEED_100 0x2000
3044#define MII_CR_SPEED_10 0x0000 3033#define MII_CR_SPEED_10 0x0000
3045#define E1000_PHY_ADDRESS 0x01 3034#define E1000_PHY_ADDRESS 0x01
3046#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 3035#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
3047#define PHY_FORCE_TIME 20 /* 2.0 Seconds */ 3036#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
3048#define PHY_REVISION_MASK 0xFFFFFFF0 3037#define PHY_REVISION_MASK 0xFFFFFFF0
3049#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */ 3038#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
3050#define REG4_SPEED_MASK 0x01E0 3039#define REG4_SPEED_MASK 0x01E0
3051#define REG9_SPEED_MASK 0x0300 3040#define REG9_SPEED_MASK 0x0300
3052#define ADVERTISE_10_HALF 0x0001 3041#define ADVERTISE_10_HALF 0x0001
@@ -3055,8 +3044,8 @@ struct e1000_host_command_info {
3055#define ADVERTISE_100_FULL 0x0008 3044#define ADVERTISE_100_FULL 0x0008
3056#define ADVERTISE_1000_HALF 0x0010 3045#define ADVERTISE_1000_HALF 0x0010
3057#define ADVERTISE_1000_FULL 0x0020 3046#define ADVERTISE_1000_FULL 0x0020
3058#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */ 3047#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
3059#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/ 3048#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds */
3060#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/ 3049#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds */
3061 3050
3062#endif /* _E1000_HW_H_ */ 3051#endif /* _E1000_HW_H_ */
diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c
index d7dea6946e85..8302e1881b83 100644
--- a/drivers/net/e1000/e1000_main.c
+++ b/drivers/net/e1000/e1000_main.c
@@ -2255,7 +2255,6 @@ static bool e1000_has_link(struct e1000_adapter *adapter)
2255{ 2255{
2256 struct e1000_hw *hw = &adapter->hw; 2256 struct e1000_hw *hw = &adapter->hw;
2257 bool link_active = false; 2257 bool link_active = false;
2258 s32 ret_val = 0;
2259 2258
2260 /* get_link_status is set on LSC (link status) interrupt or 2259 /* get_link_status is set on LSC (link status) interrupt or
2261 * rx sequence error interrupt. get_link_status will stay 2260 * rx sequence error interrupt. get_link_status will stay
@@ -2265,18 +2264,18 @@ static bool e1000_has_link(struct e1000_adapter *adapter)
2265 switch (hw->media_type) { 2264 switch (hw->media_type) {
2266 case e1000_media_type_copper: 2265 case e1000_media_type_copper:
2267 if (hw->get_link_status) { 2266 if (hw->get_link_status) {
2268 ret_val = e1000_check_for_link(hw); 2267 e1000_check_for_link(hw);
2269 link_active = !hw->get_link_status; 2268 link_active = !hw->get_link_status;
2270 } else { 2269 } else {
2271 link_active = true; 2270 link_active = true;
2272 } 2271 }
2273 break; 2272 break;
2274 case e1000_media_type_fiber: 2273 case e1000_media_type_fiber:
2275 ret_val = e1000_check_for_link(hw); 2274 e1000_check_for_link(hw);
2276 link_active = !!(er32(STATUS) & E1000_STATUS_LU); 2275 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
2277 break; 2276 break;
2278 case e1000_media_type_internal_serdes: 2277 case e1000_media_type_internal_serdes:
2279 ret_val = e1000_check_for_link(hw); 2278 e1000_check_for_link(hw);
2280 link_active = hw->serdes_has_link; 2279 link_active = hw->serdes_has_link;
2281 break; 2280 break;
2282 default: 2281 default:
@@ -4405,8 +4404,7 @@ static void e1000_vlan_rx_register(struct net_device *netdev,
4405 ew32(RCTL, rctl); 4404 ew32(RCTL, rctl);
4406 4405
4407 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) { 4406 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
4408 e1000_vlan_rx_kill_vid(netdev, 4407 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4409 adapter->mng_vlan_id);
4410 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; 4408 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4411 } 4409 }
4412 } 4410 }
@@ -4679,7 +4677,7 @@ static void e1000_netpoll(struct net_device *netdev)
4679/** 4677/**
4680 * e1000_io_error_detected - called when PCI error is detected 4678 * e1000_io_error_detected - called when PCI error is detected
4681 * @pdev: Pointer to PCI device 4679 * @pdev: Pointer to PCI device
4682 * @state: The current pci conneection state 4680 * @state: The current pci connection state
4683 * 4681 *
4684 * This function is called after a PCI bus error affecting 4682 * This function is called after a PCI bus error affecting
4685 * this device has been detected. 4683 * this device has been detected.
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 04:24:30 -0500