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authorYaniv Rosner <yanivr@broadcom.com>2008-06-23 23:27:52 -0400
committerDavid S. Miller <davem@davemloft.net>2008-06-23 23:27:52 -0400
commitc18487ee24381b40df3b8b4f54dd13ee9367a1ce (patch)
tree0c52df7c30f0789fd7509426c38b2d1551c444b9 /drivers/net
parentea4e040abc72f2dbbfdd8d04e271a18593ba72c7 (diff)
bnx2x: New link code
New Link code: Moving all the link related code (including the calculations, the initialization of the MAC and PHY and the external PHY's code) into a separated file. The changes from the code that used to be part of bnx2x.c (now called bnx2x_main.c) are: - Using separate structures for link inputs and link outputs to clearly identify what was configured and what is the outcome - Adding code to read external PHY FW version and print it as part of ethtool -i - Adding code to upgrade external PHY FW from ethtool -E with special magic number - Changing the link down indication to ERR level - Adding a lock on all PHY access to prevent an interrupt and setting changes to overlap - Adding support for emulation and FPGA (small chunk of code that really helps in the lab) - Adding support for 1G on BCM8706 PHY - Adding clear debug print incase of fan failure (the PHY type is now "failure") Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/Makefile2
-rw-r--r--drivers/net/bnx2x.h180
-rw-r--r--drivers/net/bnx2x_init.h7
-rw-r--r--drivers/net/bnx2x_main.c3097
-rw-r--r--drivers/net/bnx2x_reg.h1939
5 files changed, 1826 insertions, 3399 deletions
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 59842a109e9d..87703ffd4c1e 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -66,7 +66,7 @@ obj-$(CONFIG_FEALNX) += fealnx.o
66obj-$(CONFIG_TIGON3) += tg3.o 66obj-$(CONFIG_TIGON3) += tg3.o
67obj-$(CONFIG_BNX2) += bnx2.o 67obj-$(CONFIG_BNX2) += bnx2.o
68obj-$(CONFIG_BNX2X) += bnx2x.o 68obj-$(CONFIG_BNX2X) += bnx2x.o
69bnx2x-objs := bnx2x_main.o 69bnx2x-objs := bnx2x_main.o bnx2x_link.o
70spidernet-y += spider_net.o spider_net_ethtool.o 70spidernet-y += spider_net.o spider_net_ethtool.o
71obj-$(CONFIG_SPIDER_NET) += spidernet.o sungem_phy.o 71obj-$(CONFIG_SPIDER_NET) += spidernet.o sungem_phy.o
72obj-$(CONFIG_GELIC_NET) += ps3_gelic.o 72obj-$(CONFIG_GELIC_NET) += ps3_gelic.o
diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h
index 8e68d06510a6..2a13defda8ab 100644
--- a/drivers/net/bnx2x.h
+++ b/drivers/net/bnx2x.h
@@ -90,6 +90,12 @@
90#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) 90#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
91#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) 91#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
92 92
93#define REG_RD_DMAE(bp, offset, valp, len32) \
94 do { \
95 bnx2x_read_dmae(bp, offset, len32);\
96 memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \
97 } while (0)
98
93#define REG_WR_DMAE(bp, offset, val, len32) \ 99#define REG_WR_DMAE(bp, offset, val, len32) \
94 do { \ 100 do { \
95 memcpy(bnx2x_sp(bp, wb_data[0]), val, len32 * 4); \ 101 memcpy(bnx2x_sp(bp, wb_data[0]), val, len32 * 4); \
@@ -542,11 +548,8 @@ struct bnx2x {
542 int pm_cap; 548 int pm_cap;
543 int pcie_cap; 549 int pcie_cap;
544 550
545 /* Used to synchronize phy accesses */ 551 struct work_struct sp_task;
546 spinlock_t phy_lock; 552 struct work_struct reset_task;
547
548 struct work_struct reset_task;
549 struct work_struct sp_task;
550 553
551 struct timer_list timer; 554 struct timer_list timer;
552 int timer_interval; 555 int timer_interval;
@@ -568,6 +571,8 @@ struct bnx2x {
568#define CHIP_REV_FPGA 0x0000f000 571#define CHIP_REV_FPGA 0x0000f000
569#define CHIP_REV_IS_SLOW(bp) ((CHIP_REV(bp) == CHIP_REV_EMUL) || \ 572#define CHIP_REV_IS_SLOW(bp) ((CHIP_REV(bp) == CHIP_REV_EMUL) || \
570 (CHIP_REV(bp) == CHIP_REV_FPGA)) 573 (CHIP_REV(bp) == CHIP_REV_FPGA))
574#define CHIP_REV_IS_EMUL(bp) (CHIP_REV(bp) == CHIP_REV_EMUL)
575#define CHIP_REV_IS_FPGA(bp) (CHIP_REV(bp) == CHIP_REV_FPGA)
571 576
572#define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0) 577#define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0)
573#define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0x0000000f) 578#define CHIP_BOND_ID(bp) (((bp)->chip_id) & 0x0000000f)
@@ -578,84 +583,29 @@ struct bnx2x {
578 583
579 u32 hw_config; 584 u32 hw_config;
580 u32 board; 585 u32 board;
581 u32 serdes_config; 586
582 u32 lane_config; 587 struct link_params link_params;
583 u32 ext_phy_config; 588
584#define XGXS_EXT_PHY_TYPE(bp) (bp->ext_phy_config & \ 589 struct link_vars link_vars;
585 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) 590
586#define SERDES_EXT_PHY_TYPE(bp) (bp->ext_phy_config & \ 591 u32 link_config;
587 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
588
589 u32 speed_cap_mask;
590 u32 link_config;
591#define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
592#define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
593#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
594#define SWITCH_CFG_ONE_TIME_DETECT \
595 PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT
596
597 u8 ser_lane;
598 u8 rx_lane_swap;
599 u8 tx_lane_swap;
600
601 u8 link_up;
602 u8 phy_link_up;
603 592
604 u32 supported; 593 u32 supported;
605/* link settings - missing defines */ 594/* link settings - missing defines */
606#define SUPPORTED_2500baseT_Full (1 << 15) 595#define SUPPORTED_2500baseT_Full (1 << 15)
607 596
608 u32 phy_flags;
609/*#define PHY_SERDES_FLAG 0x1*/
610#define PHY_BMAC_FLAG 0x2
611#define PHY_EMAC_FLAG 0x4
612#define PHY_XGXS_FLAG 0x8
613#define PHY_SGMII_FLAG 0x10
614#define PHY_INT_MODE_MASK_FLAG 0x300
615#define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100
616#define PHY_INT_MODE_LINK_READY_FLAG 0x200
617
618 u32 phy_addr; 597 u32 phy_addr;
598
599 /* used to synchronize phy accesses */
600 struct mutex phy_mutex;
601
619 u32 phy_id; 602 u32 phy_id;
620 603
621 u32 autoneg;
622#define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
623#define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
624#define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
625#define AUTONEG_PARALLEL \
626 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
627#define AUTONEG_SGMII_FIBER_AUTODET \
628 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
629#define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
630
631 u32 req_autoneg;
632#define AUTONEG_SPEED 0x1
633#define AUTONEG_FLOW_CTRL 0x2
634
635 u32 req_line_speed;
636/* link settings - missing defines */
637#define SPEED_12000 12000
638#define SPEED_12500 12500
639#define SPEED_13000 13000
640#define SPEED_15000 15000
641#define SPEED_16000 16000
642
643 u32 req_duplex;
644 u32 req_flow_ctrl;
645#define FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
646#define FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
647#define FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
648#define FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
649#define FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
650 604
651 u32 advertising; 605 u32 advertising;
652/* link settings - missing defines */ 606/* link settings - missing defines */
653#define ADVERTISED_2500baseT_Full (1 << 15) 607#define ADVERTISED_2500baseT_Full (1 << 15)
654 608
655 u32 link_status;
656 u32 line_speed;
657 u32 duplex;
658 u32 flow_ctrl;
659 609
660 u32 bc_ver; 610 u32 bc_ver;
661 611
@@ -765,6 +715,11 @@ struct bnx2x {
765 715
766#define DMAE_LEN32_MAX 0x400 716#define DMAE_LEN32_MAX 0x400
767 717
718void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
719void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
720 u32 len32);
721int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);
722
768 723
769/* MC hsi */ 724/* MC hsi */
770#define RX_COPY_THRESH 92 725#define RX_COPY_THRESH 92
@@ -890,91 +845,6 @@ struct bnx2x {
890 (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT)) 845 (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
891 846
892 847
893#define MDIO_AN_CL73_OR_37_COMPLETE \
894 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
895 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
896
897#define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
898 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
899#define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
900 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
901#define GP_STATUS_SPEED_MASK \
902 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
903#define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
904#define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
905#define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
906#define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
907#define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
908#define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
909#define GP_STATUS_10G_HIG \
910 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
911#define GP_STATUS_10G_CX4 \
912 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
913#define GP_STATUS_12G_HIG \
914 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
915#define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
916#define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
917#define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
918#define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
919#define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
920#define GP_STATUS_10G_KX4 \
921 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
922
923#define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
924#define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
925#define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
926#define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
927#define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
928#define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
929#define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
930#define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
931#define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
932#define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
933#define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
934#define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
935#define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
936#define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
937#define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
938#define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
939#define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
940#define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
941#define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
942#define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
943#define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
944#define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
945#define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
946
947#define NIG_STATUS_XGXS0_LINK10G \
948 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
949#define NIG_STATUS_XGXS0_LINK_STATUS \
950 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
951#define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
952 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
953#define NIG_STATUS_SERDES0_LINK_STATUS \
954 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
955#define NIG_MASK_MI_INT \
956 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
957#define NIG_MASK_XGXS0_LINK10G \
958 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
959#define NIG_MASK_XGXS0_LINK_STATUS \
960 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
961#define NIG_MASK_SERDES0_LINK_STATUS \
962 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
963
964#define XGXS_RESET_BITS \
965 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
966 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
967 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
968 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
969 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
970
971#define SERDES_RESET_BITS \
972 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
973 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
974 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
975 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
976
977
978#define BNX2X_MC_ASSERT_BITS \ 848#define BNX2X_MC_ASSERT_BITS \
979 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 849 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
980 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 850 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h
index 370686eef97c..bb0ee2dd2d80 100644
--- a/drivers/net/bnx2x_init.h
+++ b/drivers/net/bnx2x_init.h
@@ -87,10 +87,6 @@ union init_op {
87#include "bnx2x_init_values.h" 87#include "bnx2x_init_values.h"
88 88
89static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val); 89static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
90
91static void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr,
92 u32 dst_addr, u32 len32);
93
94static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len); 90static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len);
95 91
96static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, const u32 *data, 92static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, const u32 *data,
@@ -107,9 +103,6 @@ static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, const u32 *data,
107 } 103 }
108} 104}
109 105
110#define INIT_MEM_WR(reg, data, reg_off, len) \
111 bnx2x_init_str_wr(bp, reg + reg_off*4, data, len)
112
113static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data, 106static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data,
114 u16 len) 107 u16 len)
115{ 108{
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c
index 70cba64732ca..7b547f03b565 100644
--- a/drivers/net/bnx2x_main.c
+++ b/drivers/net/bnx2x_main.c
@@ -61,6 +61,7 @@
61#include "bnx2x_reg.h" 61#include "bnx2x_reg.h"
62#include "bnx2x_fw_defs.h" 62#include "bnx2x_fw_defs.h"
63#include "bnx2x_hsi.h" 63#include "bnx2x_hsi.h"
64#include "bnx2x_link.h"
64#include "bnx2x.h" 65#include "bnx2x.h"
65#include "bnx2x_init.h" 66#include "bnx2x_init.h"
66 67
@@ -174,7 +175,7 @@ static void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae,
174 REG_WR(bp, dmae_reg_go_c[idx], 1); 175 REG_WR(bp, dmae_reg_go_c[idx], 1);
175} 176}
176 177
177static void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, 178void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr,
178 u32 dst_addr, u32 len32) 179 u32 dst_addr, u32 len32)
179{ 180{
180 struct dmae_command *dmae = &bp->dmae; 181 struct dmae_command *dmae = &bp->dmae;
@@ -236,8 +237,7 @@ static void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr,
236 } 237 }
237} 238}
238 239
239#ifdef BNX2X_DMAE_RD 240void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
240static void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
241{ 241{
242 struct dmae_command *dmae = &bp->dmae; 242 struct dmae_command *dmae = &bp->dmae;
243 int port = bp->port; 243 int port = bp->port;
@@ -294,7 +294,6 @@ static void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
294 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]); 294 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
295*/ 295*/
296} 296}
297#endif
298 297
299static int bnx2x_mc_assert(struct bnx2x *bp) 298static int bnx2x_mc_assert(struct bnx2x *bp)
300{ 299{
@@ -1135,67 +1134,19 @@ static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1135 1134
1136/* end of fast path */ 1135/* end of fast path */
1137 1136
1138/* PHY/MAC */ 1137
1138/* Link */
1139 1139
1140/* 1140/*
1141 * General service functions 1141 * General service functions
1142 */ 1142 */
1143 1143
1144static void bnx2x_leds_set(struct bnx2x *bp, unsigned int speed)
1145{
1146 int port = bp->port;
1147
1148 NIG_WR(NIG_REG_LED_MODE_P0 + port*4,
1149 ((bp->hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
1150 SHARED_HW_CFG_LED_MODE_SHIFT));
1151 NIG_WR(NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
1152
1153 /* Set blinking rate to ~15.9Hz */
1154 NIG_WR(NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
1155 LED_BLINK_RATE_VAL);
1156 NIG_WR(NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + port*4, 1);
1157
1158 /* On Ax chip versions for speeds less than 10G
1159 LED scheme is different */
1160 if ((CHIP_REV(bp) == CHIP_REV_Ax) && (speed < SPEED_10000)) {
1161 NIG_WR(NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 1);
1162 NIG_WR(NIG_REG_LED_CONTROL_TRAFFIC_P0 + port*4, 0);
1163 NIG_WR(NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + port*4, 1);
1164 }
1165}
1166
1167static void bnx2x_leds_unset(struct bnx2x *bp)
1168{
1169 int port = bp->port;
1170
1171 NIG_WR(NIG_REG_LED_10G_P0 + port*4, 0);
1172 NIG_WR(NIG_REG_LED_MODE_P0 + port*4, SHARED_HW_CFG_LED_MAC1);
1173}
1174
1175static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
1176{
1177 u32 val = REG_RD(bp, reg);
1178
1179 val |= bits;
1180 REG_WR(bp, reg, val);
1181 return val;
1182}
1183
1184static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
1185{
1186 u32 val = REG_RD(bp, reg);
1187
1188 val &= ~bits;
1189 REG_WR(bp, reg, val);
1190 return val;
1191}
1192
1193static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource) 1144static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource)
1194{ 1145{
1195 u32 cnt;
1196 u32 lock_status; 1146 u32 lock_status;
1197 u32 resource_bit = (1 << resource); 1147 u32 resource_bit = (1 << resource);
1198 u8 func = bp->port; 1148 u8 port = bp->port;
1149 int cnt;
1199 1150
1200 /* Validating that the resource is within range */ 1151 /* Validating that the resource is within range */
1201 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1152 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
@@ -1206,7 +1157,7 @@ static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource)
1206 } 1157 }
1207 1158
1208 /* Validating that the resource is not already taken */ 1159 /* Validating that the resource is not already taken */
1209 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + func*8); 1160 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + port*8);
1210 if (lock_status & resource_bit) { 1161 if (lock_status & resource_bit) {
1211 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1162 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1212 lock_status, resource_bit); 1163 lock_status, resource_bit);
@@ -1216,9 +1167,9 @@ static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource)
1216 /* Try for 1 second every 5ms */ 1167 /* Try for 1 second every 5ms */
1217 for (cnt = 0; cnt < 200; cnt++) { 1168 for (cnt = 0; cnt < 200; cnt++) {
1218 /* Try to acquire the lock */ 1169 /* Try to acquire the lock */
1219 REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + func*8 + 4, 1170 REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + port*8 + 4,
1220 resource_bit); 1171 resource_bit);
1221 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + func*8); 1172 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + port*8);
1222 if (lock_status & resource_bit) 1173 if (lock_status & resource_bit)
1223 return 0; 1174 return 0;
1224 1175
@@ -1232,7 +1183,7 @@ static int bnx2x_hw_unlock(struct bnx2x *bp, u32 resource)
1232{ 1183{
1233 u32 lock_status; 1184 u32 lock_status;
1234 u32 resource_bit = (1 << resource); 1185 u32 resource_bit = (1 << resource);
1235 u8 func = bp->port; 1186 u8 port = bp->port;
1236 1187
1237 /* Validating that the resource is within range */ 1188 /* Validating that the resource is within range */
1238 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1189 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
@@ -1243,18 +1194,41 @@ static int bnx2x_hw_unlock(struct bnx2x *bp, u32 resource)
1243 } 1194 }
1244 1195
1245 /* Validating that the resource is currently taken */ 1196 /* Validating that the resource is currently taken */
1246 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + func*8); 1197 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + port*8);
1247 if (!(lock_status & resource_bit)) { 1198 if (!(lock_status & resource_bit)) {
1248 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1199 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1249 lock_status, resource_bit); 1200 lock_status, resource_bit);
1250 return -EFAULT; 1201 return -EFAULT;
1251 } 1202 }
1252 1203
1253 REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + func*8, resource_bit); 1204 REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + port*8, resource_bit);
1254 return 0; 1205 return 0;
1255} 1206}
1256 1207
1257static int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode) 1208/* HW Lock for shared dual port PHYs */
1209static void bnx2x_phy_hw_lock(struct bnx2x *bp)
1210{
1211 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
1212
1213 mutex_lock(&bp->phy_mutex);
1214
1215 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
1216 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
1217 bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
1218}
1219
1220static void bnx2x_phy_hw_unlock(struct bnx2x *bp)
1221{
1222 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
1223
1224 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
1225 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
1226 bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_8072_MDIO);
1227
1228 mutex_unlock(&bp->phy_mutex);
1229}
1230
1231int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode)
1258{ 1232{
1259 /* The GPIO should be swapped if swap register is set and active */ 1233 /* The GPIO should be swapped if swap register is set and active */
1260 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && 1234 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
@@ -1353,1281 +1327,45 @@ static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
1353 return 0; 1327 return 0;
1354} 1328}
1355 1329
1356static int bnx2x_mdio22_write(struct bnx2x *bp, u32 reg, u32 val) 1330static void bnx2x_calc_fc_adv(struct bnx2x *bp)
1357{
1358 int port = bp->port;
1359 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1360 u32 tmp;
1361 int i, rc;
1362
1363/* DP(NETIF_MSG_HW, "phy_addr 0x%x reg 0x%x val 0x%08x\n",
1364 bp->phy_addr, reg, val); */
1365
1366 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
1367
1368 tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1369 tmp &= ~EMAC_MDIO_MODE_AUTO_POLL;
1370 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, tmp);
1371 REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1372 udelay(40);
1373 }
1374
1375 tmp = ((bp->phy_addr << 21) | (reg << 16) |
1376 (val & EMAC_MDIO_COMM_DATA) |
1377 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
1378 EMAC_MDIO_COMM_START_BUSY);
1379 EMAC_WR(EMAC_REG_EMAC_MDIO_COMM, tmp);
1380
1381 for (i = 0; i < 50; i++) {
1382 udelay(10);
1383
1384 tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM);
1385 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1386 udelay(5);
1387 break;
1388 }
1389 }
1390
1391 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1392 BNX2X_ERR("write phy register failed\n");
1393
1394 rc = -EBUSY;
1395 } else {
1396 rc = 0;
1397 }
1398
1399 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
1400
1401 tmp = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1402 tmp |= EMAC_MDIO_MODE_AUTO_POLL;
1403 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, tmp);
1404 }
1405
1406 return rc;
1407}
1408
1409static int bnx2x_mdio22_read(struct bnx2x *bp, u32 reg, u32 *ret_val)
1410{
1411 int port = bp->port;
1412 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1413 u32 val;
1414 int i, rc;
1415
1416 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
1417
1418 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1419 val &= ~EMAC_MDIO_MODE_AUTO_POLL;
1420 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, val);
1421 REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1422 udelay(40);
1423 }
1424
1425 val = ((bp->phy_addr << 21) | (reg << 16) |
1426 EMAC_MDIO_COMM_COMMAND_READ_22 |
1427 EMAC_MDIO_COMM_START_BUSY);
1428 EMAC_WR(EMAC_REG_EMAC_MDIO_COMM, val);
1429
1430 for (i = 0; i < 50; i++) {
1431 udelay(10);
1432
1433 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM);
1434 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1435 val &= EMAC_MDIO_COMM_DATA;
1436 break;
1437 }
1438 }
1439
1440 if (val & EMAC_MDIO_COMM_START_BUSY) {
1441 BNX2X_ERR("read phy register failed\n");
1442
1443 *ret_val = 0x0;
1444 rc = -EBUSY;
1445 } else {
1446 *ret_val = val;
1447 rc = 0;
1448 }
1449
1450 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
1451
1452 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1453 val |= EMAC_MDIO_MODE_AUTO_POLL;
1454 EMAC_WR(EMAC_REG_EMAC_MDIO_MODE, val);
1455 }
1456
1457/* DP(NETIF_MSG_HW, "phy_addr 0x%x reg 0x%x ret_val 0x%08x\n",
1458 bp->phy_addr, reg, *ret_val); */
1459
1460 return rc;
1461}
1462
1463static int bnx2x_mdio45_ctrl_write(struct bnx2x *bp, u32 mdio_ctrl,
1464 u32 phy_addr, u32 reg, u32 addr, u32 val)
1465{
1466 u32 tmp;
1467 int i, rc = 0;
1468
1469 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
1470 * (a value of 49==0x31) and make sure that the AUTO poll is off
1471 */
1472 tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1473 tmp &= ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1474 tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
1475 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
1476 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
1477 REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1478 udelay(40);
1479
1480 /* address */
1481 tmp = ((phy_addr << 21) | (reg << 16) | addr |
1482 EMAC_MDIO_COMM_COMMAND_ADDRESS |
1483 EMAC_MDIO_COMM_START_BUSY);
1484 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
1485
1486 for (i = 0; i < 50; i++) {
1487 udelay(10);
1488
1489 tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1490 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1491 udelay(5);
1492 break;
1493 }
1494 }
1495 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1496 BNX2X_ERR("write phy register failed\n");
1497
1498 rc = -EBUSY;
1499
1500 } else {
1501 /* data */
1502 tmp = ((phy_addr << 21) | (reg << 16) | val |
1503 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
1504 EMAC_MDIO_COMM_START_BUSY);
1505 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
1506
1507 for (i = 0; i < 50; i++) {
1508 udelay(10);
1509
1510 tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1511 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1512 udelay(5);
1513 break;
1514 }
1515 }
1516
1517 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1518 BNX2X_ERR("write phy register failed\n");
1519
1520 rc = -EBUSY;
1521 }
1522 }
1523
1524 /* unset clause 45 mode, set the MDIO clock to a faster value
1525 * (0x13 => 6.25Mhz) and restore the AUTO poll if needed
1526 */
1527 tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1528 tmp &= ~(EMAC_MDIO_MODE_CLAUSE_45 | EMAC_MDIO_MODE_CLOCK_CNT);
1529 tmp |= (0x13 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1530 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG)
1531 tmp |= EMAC_MDIO_MODE_AUTO_POLL;
1532 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
1533
1534 return rc;
1535}
1536
1537static int bnx2x_mdio45_write(struct bnx2x *bp, u32 phy_addr, u32 reg,
1538 u32 addr, u32 val)
1539{
1540 u32 emac_base = bp->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1541
1542 return bnx2x_mdio45_ctrl_write(bp, emac_base, phy_addr,
1543 reg, addr, val);
1544}
1545
1546static int bnx2x_mdio45_ctrl_read(struct bnx2x *bp, u32 mdio_ctrl,
1547 u32 phy_addr, u32 reg, u32 addr,
1548 u32 *ret_val)
1549{
1550 u32 val;
1551 int i, rc = 0;
1552
1553 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
1554 * (a value of 49==0x31) and make sure that the AUTO poll is off
1555 */
1556 val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1557 val &= ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1558 val |= (EMAC_MDIO_MODE_CLAUSE_45 |
1559 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
1560 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
1561 REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1562 udelay(40);
1563
1564 /* address */
1565 val = ((phy_addr << 21) | (reg << 16) | addr |
1566 EMAC_MDIO_COMM_COMMAND_ADDRESS |
1567 EMAC_MDIO_COMM_START_BUSY);
1568 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
1569
1570 for (i = 0; i < 50; i++) {
1571 udelay(10);
1572
1573 val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1574 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1575 udelay(5);
1576 break;
1577 }
1578 }
1579 if (val & EMAC_MDIO_COMM_START_BUSY) {
1580 BNX2X_ERR("read phy register failed\n");
1581
1582 *ret_val = 0;
1583 rc = -EBUSY;
1584
1585 } else {
1586 /* data */
1587 val = ((phy_addr << 21) | (reg << 16) |
1588 EMAC_MDIO_COMM_COMMAND_READ_45 |
1589 EMAC_MDIO_COMM_START_BUSY);
1590 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
1591
1592 for (i = 0; i < 50; i++) {
1593 udelay(10);
1594
1595 val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1596 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1597 val &= EMAC_MDIO_COMM_DATA;
1598 break;
1599 }
1600 }
1601
1602 if (val & EMAC_MDIO_COMM_START_BUSY) {
1603 BNX2X_ERR("read phy register failed\n");
1604
1605 val = 0;
1606 rc = -EBUSY;
1607 }
1608
1609 *ret_val = val;
1610 }
1611
1612 /* unset clause 45 mode, set the MDIO clock to a faster value
1613 * (0x13 => 6.25Mhz) and restore the AUTO poll if needed
1614 */
1615 val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1616 val &= ~(EMAC_MDIO_MODE_CLAUSE_45 | EMAC_MDIO_MODE_CLOCK_CNT);
1617 val |= (0x13 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1618 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG)
1619 val |= EMAC_MDIO_MODE_AUTO_POLL;
1620 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
1621
1622 return rc;
1623}
1624
1625static int bnx2x_mdio45_read(struct bnx2x *bp, u32 phy_addr, u32 reg,
1626 u32 addr, u32 *ret_val)
1627{
1628 u32 emac_base = bp->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1629
1630 return bnx2x_mdio45_ctrl_read(bp, emac_base, phy_addr,
1631 reg, addr, ret_val);
1632}
1633
1634static int bnx2x_mdio45_vwrite(struct bnx2x *bp, u32 phy_addr, u32 reg,
1635 u32 addr, u32 val)
1636{
1637 int i;
1638 u32 rd_val;
1639
1640 might_sleep();
1641 for (i = 0; i < 10; i++) {
1642 bnx2x_mdio45_write(bp, phy_addr, reg, addr, val);
1643 msleep(5);
1644 bnx2x_mdio45_read(bp, phy_addr, reg, addr, &rd_val);
1645 /* if the read value is not the same as the value we wrote,
1646 we should write it again */
1647 if (rd_val == val)
1648 return 0;
1649 }
1650 BNX2X_ERR("MDIO write in CL45 failed\n");
1651 return -EBUSY;
1652}
1653
1654/*
1655 * link management
1656 */
1657
1658static void bnx2x_pause_resolve(struct bnx2x *bp, u32 pause_result)
1659{
1660 switch (pause_result) { /* ASYM P ASYM P */
1661 case 0xb: /* 1 0 1 1 */
1662 bp->flow_ctrl = FLOW_CTRL_TX;
1663 break;
1664
1665 case 0xe: /* 1 1 1 0 */
1666 bp->flow_ctrl = FLOW_CTRL_RX;
1667 break;
1668
1669 case 0x5: /* 0 1 0 1 */
1670 case 0x7: /* 0 1 1 1 */
1671 case 0xd: /* 1 1 0 1 */
1672 case 0xf: /* 1 1 1 1 */
1673 bp->flow_ctrl = FLOW_CTRL_BOTH;
1674 break;
1675
1676 default:
1677 break;
1678 }
1679}
1680
1681static u8 bnx2x_ext_phy_resove_fc(struct bnx2x *bp)
1682{
1683 u32 ext_phy_addr;
1684 u32 ld_pause; /* local */
1685 u32 lp_pause; /* link partner */
1686 u32 an_complete; /* AN complete */
1687 u32 pause_result;
1688 u8 ret = 0;
1689
1690 ext_phy_addr = ((bp->ext_phy_config &
1691 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
1692 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
1693
1694 /* read twice */
1695 bnx2x_mdio45_read(bp, ext_phy_addr,
1696 EXT_PHY_KR_AUTO_NEG_DEVAD,
1697 EXT_PHY_KR_STATUS, &an_complete);
1698 bnx2x_mdio45_read(bp, ext_phy_addr,
1699 EXT_PHY_KR_AUTO_NEG_DEVAD,
1700 EXT_PHY_KR_STATUS, &an_complete);
1701
1702 if (an_complete & EXT_PHY_KR_AUTO_NEG_COMPLETE) {
1703 ret = 1;
1704 bnx2x_mdio45_read(bp, ext_phy_addr,
1705 EXT_PHY_KR_AUTO_NEG_DEVAD,
1706 EXT_PHY_KR_AUTO_NEG_ADVERT, &ld_pause);
1707 bnx2x_mdio45_read(bp, ext_phy_addr,
1708 EXT_PHY_KR_AUTO_NEG_DEVAD,
1709 EXT_PHY_KR_LP_AUTO_NEG, &lp_pause);
1710 pause_result = (ld_pause &
1711 EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_MASK) >> 8;
1712 pause_result |= (lp_pause &
1713 EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_MASK) >> 10;
1714 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x \n",
1715 pause_result);
1716 bnx2x_pause_resolve(bp, pause_result);
1717 }
1718 return ret;
1719}
1720
1721static void bnx2x_flow_ctrl_resolve(struct bnx2x *bp, u32 gp_status)
1722{
1723 u32 ld_pause; /* local driver */
1724 u32 lp_pause; /* link partner */
1725 u32 pause_result;
1726
1727 bp->flow_ctrl = 0;
1728
1729 /* resolve from gp_status in case of AN complete and not sgmii */
1730 if ((bp->req_autoneg & AUTONEG_FLOW_CTRL) &&
1731 (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
1732 (!(bp->phy_flags & PHY_SGMII_FLAG)) &&
1733 (XGXS_EXT_PHY_TYPE(bp) == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)) {
1734
1735 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
1736 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
1737 &ld_pause);
1738 bnx2x_mdio22_read(bp,
1739 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
1740 &lp_pause);
1741 pause_result = (ld_pause &
1742 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
1743 pause_result |= (lp_pause &
1744 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
1745 DP(NETIF_MSG_LINK, "pause_result 0x%x\n", pause_result);
1746 bnx2x_pause_resolve(bp, pause_result);
1747 } else if (!(bp->req_autoneg & AUTONEG_FLOW_CTRL) ||
1748 !(bnx2x_ext_phy_resove_fc(bp))) {
1749 /* forced speed */
1750 if (bp->req_autoneg & AUTONEG_FLOW_CTRL) {
1751 switch (bp->req_flow_ctrl) {
1752 case FLOW_CTRL_AUTO:
1753 if (bp->dev->mtu <= 4500)
1754 bp->flow_ctrl = FLOW_CTRL_BOTH;
1755 else
1756 bp->flow_ctrl = FLOW_CTRL_TX;
1757 break;
1758
1759 case FLOW_CTRL_TX:
1760 bp->flow_ctrl = FLOW_CTRL_TX;
1761 break;
1762
1763 case FLOW_CTRL_RX:
1764 if (bp->dev->mtu <= 4500)
1765 bp->flow_ctrl = FLOW_CTRL_RX;
1766 break;
1767
1768 case FLOW_CTRL_BOTH:
1769 if (bp->dev->mtu <= 4500)
1770 bp->flow_ctrl = FLOW_CTRL_BOTH;
1771 else
1772 bp->flow_ctrl = FLOW_CTRL_TX;
1773 break;
1774
1775 case FLOW_CTRL_NONE:
1776 default:
1777 break;
1778 }
1779 } else { /* forced mode */
1780 switch (bp->req_flow_ctrl) {
1781 case FLOW_CTRL_AUTO:
1782 DP(NETIF_MSG_LINK, "req_flow_ctrl 0x%x while"
1783 " req_autoneg 0x%x\n",
1784 bp->req_flow_ctrl, bp->req_autoneg);
1785 break;
1786
1787 case FLOW_CTRL_TX:
1788 case FLOW_CTRL_RX:
1789 case FLOW_CTRL_BOTH:
1790 bp->flow_ctrl = bp->req_flow_ctrl;
1791 break;
1792
1793 case FLOW_CTRL_NONE:
1794 default:
1795 break;
1796 }
1797 }
1798 }
1799 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", bp->flow_ctrl);
1800}
1801
1802static void bnx2x_link_settings_status(struct bnx2x *bp, u32 gp_status)
1803{
1804 bp->link_status = 0;
1805
1806 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
1807 DP(NETIF_MSG_LINK, "phy link up\n");
1808
1809 bp->phy_link_up = 1;
1810 bp->link_status |= LINK_STATUS_LINK_UP;
1811
1812 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
1813 bp->duplex = DUPLEX_FULL;
1814 else
1815 bp->duplex = DUPLEX_HALF;
1816
1817 bnx2x_flow_ctrl_resolve(bp, gp_status);
1818
1819 switch (gp_status & GP_STATUS_SPEED_MASK) {
1820 case GP_STATUS_10M:
1821 bp->line_speed = SPEED_10;
1822 if (bp->duplex == DUPLEX_FULL)
1823 bp->link_status |= LINK_10TFD;
1824 else
1825 bp->link_status |= LINK_10THD;
1826 break;
1827
1828 case GP_STATUS_100M:
1829 bp->line_speed = SPEED_100;
1830 if (bp->duplex == DUPLEX_FULL)
1831 bp->link_status |= LINK_100TXFD;
1832 else
1833 bp->link_status |= LINK_100TXHD;
1834 break;
1835
1836 case GP_STATUS_1G:
1837 case GP_STATUS_1G_KX:
1838 bp->line_speed = SPEED_1000;
1839 if (bp->duplex == DUPLEX_FULL)
1840 bp->link_status |= LINK_1000TFD;
1841 else
1842 bp->link_status |= LINK_1000THD;
1843 break;
1844
1845 case GP_STATUS_2_5G:
1846 bp->line_speed = SPEED_2500;
1847 if (bp->duplex == DUPLEX_FULL)
1848 bp->link_status |= LINK_2500TFD;
1849 else
1850 bp->link_status |= LINK_2500THD;
1851 break;
1852
1853 case GP_STATUS_5G:
1854 case GP_STATUS_6G:
1855 BNX2X_ERR("link speed unsupported gp_status 0x%x\n",
1856 gp_status);
1857 break;
1858
1859 case GP_STATUS_10G_KX4:
1860 case GP_STATUS_10G_HIG:
1861 case GP_STATUS_10G_CX4:
1862 bp->line_speed = SPEED_10000;
1863 bp->link_status |= LINK_10GTFD;
1864 break;
1865
1866 case GP_STATUS_12G_HIG:
1867 bp->line_speed = SPEED_12000;
1868 bp->link_status |= LINK_12GTFD;
1869 break;
1870
1871 case GP_STATUS_12_5G:
1872 bp->line_speed = SPEED_12500;
1873 bp->link_status |= LINK_12_5GTFD;
1874 break;
1875
1876 case GP_STATUS_13G:
1877 bp->line_speed = SPEED_13000;
1878 bp->link_status |= LINK_13GTFD;
1879 break;
1880
1881 case GP_STATUS_15G:
1882 bp->line_speed = SPEED_15000;
1883 bp->link_status |= LINK_15GTFD;
1884 break;
1885
1886 case GP_STATUS_16G:
1887 bp->line_speed = SPEED_16000;
1888 bp->link_status |= LINK_16GTFD;
1889 break;
1890
1891 default:
1892 BNX2X_ERR("link speed unsupported gp_status 0x%x\n",
1893 gp_status);
1894 break;
1895 }
1896
1897 bp->link_status |= LINK_STATUS_SERDES_LINK;
1898
1899 if (bp->req_autoneg & AUTONEG_SPEED) {
1900 bp->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
1901
1902 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
1903 bp->link_status |=
1904 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
1905
1906 if (bp->autoneg & AUTONEG_PARALLEL)
1907 bp->link_status |=
1908 LINK_STATUS_PARALLEL_DETECTION_USED;
1909 }
1910
1911 if (bp->flow_ctrl & FLOW_CTRL_TX)
1912 bp->link_status |= LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
1913
1914 if (bp->flow_ctrl & FLOW_CTRL_RX)
1915 bp->link_status |= LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
1916
1917 } else { /* link_down */
1918 DP(NETIF_MSG_LINK, "phy link down\n");
1919
1920 bp->phy_link_up = 0;
1921
1922 bp->line_speed = 0;
1923 bp->duplex = DUPLEX_FULL;
1924 bp->flow_ctrl = 0;
1925 }
1926
1927 DP(NETIF_MSG_LINK, "gp_status 0x%x phy_link_up %d\n"
1928 DP_LEVEL " line_speed %d duplex %d flow_ctrl 0x%x"
1929 " link_status 0x%x\n",
1930 gp_status, bp->phy_link_up, bp->line_speed, bp->duplex,
1931 bp->flow_ctrl, bp->link_status);
1932}
1933
1934static void bnx2x_link_int_ack(struct bnx2x *bp, int is_10g)
1935{
1936 int port = bp->port;
1937
1938 /* first reset all status
1939 * we assume only one line will be change at a time */
1940 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
1941 (NIG_STATUS_XGXS0_LINK10G |
1942 NIG_STATUS_XGXS0_LINK_STATUS |
1943 NIG_STATUS_SERDES0_LINK_STATUS));
1944 if (bp->phy_link_up) {
1945 if (is_10g) {
1946 /* Disable the 10G link interrupt
1947 * by writing 1 to the status register
1948 */
1949 DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
1950 bnx2x_bits_en(bp,
1951 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
1952 NIG_STATUS_XGXS0_LINK10G);
1953
1954 } else if (bp->phy_flags & PHY_XGXS_FLAG) {
1955 /* Disable the link interrupt
1956 * by writing 1 to the relevant lane
1957 * in the status register
1958 */
1959 DP(NETIF_MSG_LINK, "1G XGXS phy link up\n");
1960 bnx2x_bits_en(bp,
1961 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
1962 ((1 << bp->ser_lane) <<
1963 NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
1964
1965 } else { /* SerDes */
1966 DP(NETIF_MSG_LINK, "SerDes phy link up\n");
1967 /* Disable the link interrupt
1968 * by writing 1 to the status register
1969 */
1970 bnx2x_bits_en(bp,
1971 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
1972 NIG_STATUS_SERDES0_LINK_STATUS);
1973 }
1974
1975 } else { /* link_down */
1976 }
1977}
1978
1979static int bnx2x_ext_phy_is_link_up(struct bnx2x *bp)
1980{ 1331{
1981 u32 ext_phy_type; 1332 switch (bp->link_vars.ieee_fc) {
1982 u32 ext_phy_addr; 1333 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
1983 u32 val1 = 0, val2; 1334 bp->advertising &= ~(ADVERTISED_Asym_Pause |
1984 u32 rx_sd, pcs_status; 1335 ADVERTISED_Pause);
1985
1986 if (bp->phy_flags & PHY_XGXS_FLAG) {
1987 ext_phy_addr = ((bp->ext_phy_config &
1988 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
1989 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
1990
1991 ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
1992 switch (ext_phy_type) {
1993 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
1994 DP(NETIF_MSG_LINK, "XGXS Direct\n");
1995 val1 = 1;
1996 break;
1997
1998 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
1999 DP(NETIF_MSG_LINK, "XGXS 8705\n");
2000 bnx2x_mdio45_read(bp, ext_phy_addr,
2001 EXT_PHY_OPT_WIS_DEVAD,
2002 EXT_PHY_OPT_LASI_STATUS, &val1);
2003 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
2004
2005 bnx2x_mdio45_read(bp, ext_phy_addr,
2006 EXT_PHY_OPT_WIS_DEVAD,
2007 EXT_PHY_OPT_LASI_STATUS, &val1);
2008 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
2009
2010 bnx2x_mdio45_read(bp, ext_phy_addr,
2011 EXT_PHY_OPT_PMA_PMD_DEVAD,
2012 EXT_PHY_OPT_PMD_RX_SD, &rx_sd);
2013 DP(NETIF_MSG_LINK, "8705 rx_sd 0x%x\n", rx_sd);
2014 val1 = (rx_sd & 0x1);
2015 break;
2016
2017 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
2018 DP(NETIF_MSG_LINK, "XGXS 8706\n");
2019 bnx2x_mdio45_read(bp, ext_phy_addr,
2020 EXT_PHY_OPT_PMA_PMD_DEVAD,
2021 EXT_PHY_OPT_LASI_STATUS, &val1);
2022 DP(NETIF_MSG_LINK, "8706 LASI status 0x%x\n", val1);
2023
2024 bnx2x_mdio45_read(bp, ext_phy_addr,
2025 EXT_PHY_OPT_PMA_PMD_DEVAD,
2026 EXT_PHY_OPT_LASI_STATUS, &val1);
2027 DP(NETIF_MSG_LINK, "8706 LASI status 0x%x\n", val1);
2028
2029 bnx2x_mdio45_read(bp, ext_phy_addr,
2030 EXT_PHY_OPT_PMA_PMD_DEVAD,
2031 EXT_PHY_OPT_PMD_RX_SD, &rx_sd);
2032 bnx2x_mdio45_read(bp, ext_phy_addr,
2033 EXT_PHY_OPT_PCS_DEVAD,
2034 EXT_PHY_OPT_PCS_STATUS, &pcs_status);
2035 bnx2x_mdio45_read(bp, ext_phy_addr,
2036 EXT_PHY_AUTO_NEG_DEVAD,
2037 EXT_PHY_OPT_AN_LINK_STATUS, &val2);
2038
2039 DP(NETIF_MSG_LINK, "8706 rx_sd 0x%x"
2040 " pcs_status 0x%x 1Gbps link_status 0x%x 0x%x\n",
2041 rx_sd, pcs_status, val2, (val2 & (1<<1)));
2042 /* link is up if both bit 0 of pmd_rx_sd and
2043 * bit 0 of pcs_status are set, or if the autoneg bit
2044 1 is set
2045 */
2046 val1 = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
2047 break;
2048
2049 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
2050 bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
2051
2052 /* clear the interrupt LASI status register */
2053 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2054 ext_phy_addr,
2055 EXT_PHY_KR_PCS_DEVAD,
2056 EXT_PHY_KR_LASI_STATUS, &val2);
2057 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2058 ext_phy_addr,
2059 EXT_PHY_KR_PCS_DEVAD,
2060 EXT_PHY_KR_LASI_STATUS, &val1);
2061 DP(NETIF_MSG_LINK, "KR LASI status 0x%x->0x%x\n",
2062 val2, val1);
2063 /* Check the LASI */
2064 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2065 ext_phy_addr,
2066 EXT_PHY_KR_PMA_PMD_DEVAD,
2067 0x9003, &val2);
2068 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2069 ext_phy_addr,
2070 EXT_PHY_KR_PMA_PMD_DEVAD,
2071 0x9003, &val1);
2072 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x->0x%x\n",
2073 val2, val1);
2074 /* Check the link status */
2075 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2076 ext_phy_addr,
2077 EXT_PHY_KR_PCS_DEVAD,
2078 EXT_PHY_KR_PCS_STATUS, &val2);
2079 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
2080 /* Check the link status on 1.1.2 */
2081 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2082 ext_phy_addr,
2083 EXT_PHY_OPT_PMA_PMD_DEVAD,
2084 EXT_PHY_KR_STATUS, &val2);
2085 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
2086 ext_phy_addr,
2087 EXT_PHY_OPT_PMA_PMD_DEVAD,
2088 EXT_PHY_KR_STATUS, &val1);
2089 DP(NETIF_MSG_LINK,
2090 "KR PMA status 0x%x->0x%x\n", val2, val1);
2091 val1 = ((val1 & 4) == 4);
2092 /* If 1G was requested assume the link is up */
2093 if (!(bp->req_autoneg & AUTONEG_SPEED) &&
2094 (bp->req_line_speed == SPEED_1000))
2095 val1 = 1;
2096 bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_8072_MDIO);
2097 break;
2098
2099 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
2100 bnx2x_mdio45_read(bp, ext_phy_addr,
2101 EXT_PHY_OPT_PMA_PMD_DEVAD,
2102 EXT_PHY_OPT_LASI_STATUS, &val2);
2103 bnx2x_mdio45_read(bp, ext_phy_addr,
2104 EXT_PHY_OPT_PMA_PMD_DEVAD,
2105 EXT_PHY_OPT_LASI_STATUS, &val1);
2106 DP(NETIF_MSG_LINK,
2107 "10G-base-T LASI status 0x%x->0x%x\n", val2, val1);
2108 bnx2x_mdio45_read(bp, ext_phy_addr,
2109 EXT_PHY_OPT_PMA_PMD_DEVAD,
2110 EXT_PHY_KR_STATUS, &val2);
2111 bnx2x_mdio45_read(bp, ext_phy_addr,
2112 EXT_PHY_OPT_PMA_PMD_DEVAD,
2113 EXT_PHY_KR_STATUS, &val1);
2114 DP(NETIF_MSG_LINK,
2115 "10G-base-T PMA status 0x%x->0x%x\n", val2, val1);
2116 val1 = ((val1 & 4) == 4);
2117 /* if link is up
2118 * print the AN outcome of the SFX7101 PHY
2119 */
2120 if (val1) {
2121 bnx2x_mdio45_read(bp, ext_phy_addr,
2122 EXT_PHY_KR_AUTO_NEG_DEVAD,
2123 0x21, &val2);
2124 DP(NETIF_MSG_LINK,
2125 "SFX7101 AN status 0x%x->%s\n", val2,
2126 (val2 & (1<<14)) ? "Master" : "Slave");
2127 }
2128 break;
2129
2130 default:
2131 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
2132 bp->ext_phy_config);
2133 val1 = 0;
2134 break;
2135 }
2136
2137 } else { /* SerDes */
2138 ext_phy_type = SERDES_EXT_PHY_TYPE(bp);
2139 switch (ext_phy_type) {
2140 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
2141 DP(NETIF_MSG_LINK, "SerDes Direct\n");
2142 val1 = 1;
2143 break;
2144
2145 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
2146 DP(NETIF_MSG_LINK, "SerDes 5482\n");
2147 val1 = 1;
2148 break;
2149
2150 default:
2151 DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
2152 bp->ext_phy_config);
2153 val1 = 0;
2154 break;
2155 }
2156 }
2157
2158 return val1;
2159}
2160
2161static void bnx2x_bmac_enable(struct bnx2x *bp, int is_lb)
2162{
2163 int port = bp->port;
2164 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2165 NIG_REG_INGRESS_BMAC0_MEM;
2166 u32 wb_write[2];
2167 u32 val;
2168
2169 DP(NETIF_MSG_LINK, "enabling BigMAC\n");
2170 /* reset and unreset the BigMac */
2171 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2172 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2173 msleep(5);
2174 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2175 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2176
2177 /* enable access for bmac registers */
2178 NIG_WR(NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2179
2180 /* XGXS control */
2181 wb_write[0] = 0x3c;
2182 wb_write[1] = 0;
2183 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2184 wb_write, 2);
2185
2186 /* tx MAC SA */
2187 wb_write[0] = ((bp->dev->dev_addr[2] << 24) |
2188 (bp->dev->dev_addr[3] << 16) |
2189 (bp->dev->dev_addr[4] << 8) |
2190 bp->dev->dev_addr[5]);
2191 wb_write[1] = ((bp->dev->dev_addr[0] << 8) |
2192 bp->dev->dev_addr[1]);
2193 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR,
2194 wb_write, 2);
2195
2196 /* tx control */
2197 val = 0xc0;
2198 if (bp->flow_ctrl & FLOW_CTRL_TX)
2199 val |= 0x800000;
2200 wb_write[0] = val;
2201 wb_write[1] = 0;
2202 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_write, 2);
2203
2204 /* set tx mtu */
2205 wb_write[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; /* -CRC */
2206 wb_write[1] = 0;
2207 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_write, 2);
2208
2209 /* mac control */
2210 val = 0x3;
2211 if (is_lb) {
2212 val |= 0x4;
2213 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2214 }
2215 wb_write[0] = val;
2216 wb_write[1] = 0;
2217 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
2218 wb_write, 2);
2219
2220 /* rx control set to don't strip crc */
2221 val = 0x14;
2222 if (bp->flow_ctrl & FLOW_CTRL_RX)
2223 val |= 0x20;
2224 wb_write[0] = val;
2225 wb_write[1] = 0;
2226 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_write, 2);
2227
2228 /* set rx mtu */
2229 wb_write[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2230 wb_write[1] = 0;
2231 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_write, 2);
2232
2233 /* set cnt max size */
2234 wb_write[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD; /* -VLAN */
2235 wb_write[1] = 0;
2236 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE,
2237 wb_write, 2);
2238
2239 /* configure safc */
2240 wb_write[0] = 0x1000200;
2241 wb_write[1] = 0;
2242 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2243 wb_write, 2);
2244
2245 /* fix for emulation */
2246 if (CHIP_REV(bp) == CHIP_REV_EMUL) {
2247 wb_write[0] = 0xf000;
2248 wb_write[1] = 0;
2249 REG_WR_DMAE(bp,
2250 bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
2251 wb_write, 2);
2252 }
2253
2254 /* reset old bmac stats */
2255 memset(&bp->old_bmac, 0, sizeof(struct bmac_stats));
2256
2257 NIG_WR(NIG_REG_XCM0_OUT_EN + port*4, 0x0);
2258
2259 /* select XGXS */
2260 NIG_WR(NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2261 NIG_WR(NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2262
2263 /* disable the NIG in/out to the emac */
2264 NIG_WR(NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2265 NIG_WR(NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2266 NIG_WR(NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2267
2268 /* enable the NIG in/out to the bmac */
2269 NIG_WR(NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2270
2271 NIG_WR(NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2272 val = 0;
2273 if (bp->flow_ctrl & FLOW_CTRL_TX)
2274 val = 1;
2275 NIG_WR(NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2276 NIG_WR(NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2277
2278 bp->phy_flags |= PHY_BMAC_FLAG;
2279
2280 bp->stats_state = STATS_STATE_ENABLE;
2281}
2282
2283static void bnx2x_bmac_rx_disable(struct bnx2x *bp)
2284{
2285 int port = bp->port;
2286 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2287 NIG_REG_INGRESS_BMAC0_MEM;
2288 u32 wb_write[2];
2289
2290 /* Only if the bmac is out of reset */
2291 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2292 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)) {
2293 /* Clear Rx Enable bit in BMAC_CONTROL register */
2294#ifdef BNX2X_DMAE_RD
2295 bnx2x_read_dmae(bp, bmac_addr +
2296 BIGMAC_REGISTER_BMAC_CONTROL, 2);
2297 wb_write[0] = *bnx2x_sp(bp, wb_data[0]);
2298 wb_write[1] = *bnx2x_sp(bp, wb_data[1]);
2299#else
2300 wb_write[0] = REG_RD(bp,
2301 bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL);
2302 wb_write[1] = REG_RD(bp,
2303 bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL + 4);
2304#endif
2305 wb_write[0] &= ~BMAC_CONTROL_RX_ENABLE;
2306 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
2307 wb_write, 2);
2308 msleep(1);
2309 }
2310}
2311
2312static void bnx2x_emac_enable(struct bnx2x *bp)
2313{
2314 int port = bp->port;
2315 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2316 u32 val;
2317 int timeout;
2318
2319 DP(NETIF_MSG_LINK, "enabling EMAC\n");
2320 /* reset and unreset the emac core */
2321 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2322 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
2323 msleep(5);
2324 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2325 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
2326
2327 /* enable emac and not bmac */
2328 NIG_WR(NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
2329
2330 /* for paladium */
2331 if (CHIP_REV(bp) == CHIP_REV_EMUL) {
2332 /* Use lane 1 (of lanes 0-3) */
2333 NIG_WR(NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
2334 NIG_WR(NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
2335 }
2336 /* for fpga */
2337 else if (CHIP_REV(bp) == CHIP_REV_FPGA) {
2338 /* Use lane 1 (of lanes 0-3) */
2339 NIG_WR(NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
2340 NIG_WR(NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
2341 }
2342 /* ASIC */
2343 else {
2344 if (bp->phy_flags & PHY_XGXS_FLAG) {
2345 DP(NETIF_MSG_LINK, "XGXS\n");
2346 /* select the master lanes (out of 0-3) */
2347 NIG_WR(NIG_REG_XGXS_LANE_SEL_P0 + port*4,
2348 bp->ser_lane);
2349 /* select XGXS */
2350 NIG_WR(NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
2351
2352 } else { /* SerDes */
2353 DP(NETIF_MSG_LINK, "SerDes\n");
2354 /* select SerDes */
2355 NIG_WR(NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
2356 }
2357 }
2358
2359 /* enable emac */
2360 NIG_WR(NIG_REG_NIG_EMAC0_EN + port*4, 1);
2361
2362 /* init emac - use read-modify-write */
2363 /* self clear reset */
2364 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
2365 EMAC_WR(EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
2366
2367 timeout = 200;
2368 while (val & EMAC_MODE_RESET) {
2369 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
2370 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
2371 if (!timeout) {
2372 BNX2X_ERR("EMAC timeout!\n");
2373 break;
2374 }
2375 timeout--;
2376 }
2377
2378 /* reset tx part */
2379 EMAC_WR(EMAC_REG_EMAC_TX_MODE, EMAC_TX_MODE_RESET);
2380
2381 timeout = 200;
2382 while (val & EMAC_TX_MODE_RESET) {
2383 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_TX_MODE);
2384 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
2385 if (!timeout) {
2386 BNX2X_ERR("EMAC timeout!\n");
2387 break;
2388 }
2389 timeout--;
2390 }
2391
2392 if (CHIP_REV_IS_SLOW(bp)) {
2393 /* config GMII mode */
2394 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
2395 EMAC_WR(EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
2396
2397 } else { /* ASIC */
2398 /* pause enable/disable */
2399 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
2400 EMAC_RX_MODE_FLOW_EN);
2401 if (bp->flow_ctrl & FLOW_CTRL_RX)
2402 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
2403 EMAC_RX_MODE_FLOW_EN);
2404
2405 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
2406 EMAC_TX_MODE_EXT_PAUSE_EN);
2407 if (bp->flow_ctrl & FLOW_CTRL_TX)
2408 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
2409 EMAC_TX_MODE_EXT_PAUSE_EN);
2410 }
2411
2412 /* KEEP_VLAN_TAG, promiscuous */
2413 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
2414 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
2415 EMAC_WR(EMAC_REG_EMAC_RX_MODE, val);
2416
2417 /* identify magic packets */
2418 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
2419 EMAC_WR(EMAC_REG_EMAC_MODE, (val | EMAC_MODE_MPKT));
2420
2421 /* enable emac for jumbo packets */
2422 EMAC_WR(EMAC_REG_EMAC_RX_MTU_SIZE,
2423 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
2424 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD))); /* -VLAN */
2425
2426 /* strip CRC */
2427 NIG_WR(NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
2428
2429 val = ((bp->dev->dev_addr[0] << 8) |
2430 bp->dev->dev_addr[1]);
2431 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH, val);
2432
2433 val = ((bp->dev->dev_addr[2] << 24) |
2434 (bp->dev->dev_addr[3] << 16) |
2435 (bp->dev->dev_addr[4] << 8) |
2436 bp->dev->dev_addr[5]);
2437 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + 4, val);
2438
2439 /* disable the NIG in/out to the bmac */
2440 NIG_WR(NIG_REG_BMAC0_IN_EN + port*4, 0x0);
2441 NIG_WR(NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
2442 NIG_WR(NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
2443
2444 /* enable the NIG in/out to the emac */
2445 NIG_WR(NIG_REG_EMAC0_IN_EN + port*4, 0x1);
2446 val = 0;
2447 if (bp->flow_ctrl & FLOW_CTRL_TX)
2448 val = 1;
2449 NIG_WR(NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
2450 NIG_WR(NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
2451
2452 if (CHIP_REV(bp) == CHIP_REV_FPGA) {
2453 /* take the BigMac out of reset */
2454 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2455 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2456
2457 /* enable access for bmac registers */
2458 NIG_WR(NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2459 }
2460
2461 bp->phy_flags |= PHY_EMAC_FLAG;
2462
2463 bp->stats_state = STATS_STATE_ENABLE;
2464}
2465
2466static void bnx2x_emac_program(struct bnx2x *bp)
2467{
2468 u16 mode = 0;
2469 int port = bp->port;
2470
2471 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
2472 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
2473 (EMAC_MODE_25G_MODE |
2474 EMAC_MODE_PORT_MII_10M |
2475 EMAC_MODE_HALF_DUPLEX));
2476 switch (bp->line_speed) {
2477 case SPEED_10:
2478 mode |= EMAC_MODE_PORT_MII_10M;
2479 break; 1336 break;
2480 1337 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2481 case SPEED_100: 1338 bp->advertising |= (ADVERTISED_Asym_Pause |
2482 mode |= EMAC_MODE_PORT_MII; 1339 ADVERTISED_Pause);
2483 break; 1340 break;
2484 1341 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2485 case SPEED_1000: 1342 bp->advertising |= ADVERTISED_Asym_Pause;
2486 mode |= EMAC_MODE_PORT_GMII;
2487 break;
2488
2489 case SPEED_2500:
2490 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
2491 break; 1343 break;
2492
2493 default: 1344 default:
2494 /* 10G not valid for EMAC */ 1345 bp->advertising &= ~(ADVERTISED_Asym_Pause |
2495 BNX2X_ERR("Invalid line_speed 0x%x\n", bp->line_speed); 1346 ADVERTISED_Pause);
2496 break; 1347 break;
2497 } 1348 }
2498
2499 if (bp->duplex == DUPLEX_HALF)
2500 mode |= EMAC_MODE_HALF_DUPLEX;
2501 bnx2x_bits_en(bp, GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
2502 mode);
2503
2504 bnx2x_leds_set(bp, bp->line_speed);
2505}
2506
2507static void bnx2x_set_sgmii_tx_driver(struct bnx2x *bp)
2508{
2509 u32 lp_up2;
2510 u32 tx_driver;
2511
2512 /* read precomp */
2513 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_OVER_1G);
2514 bnx2x_mdio22_read(bp, MDIO_OVER_1G_LP_UP2, &lp_up2);
2515
2516 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_TX0);
2517 bnx2x_mdio22_read(bp, MDIO_TX0_TX_DRIVER, &tx_driver);
2518
2519 /* bits [10:7] at lp_up2, positioned at [15:12] */
2520 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
2521 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
2522 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
2523
2524 if ((lp_up2 != 0) &&
2525 (lp_up2 != (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK))) {
2526 /* replace tx_driver bits [15:12] */
2527 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
2528 tx_driver |= lp_up2;
2529 bnx2x_mdio22_write(bp, MDIO_TX0_TX_DRIVER, tx_driver);
2530 }
2531}
2532
2533static void bnx2x_pbf_update(struct bnx2x *bp)
2534{
2535 int port = bp->port;
2536 u32 init_crd, crd;
2537 u32 count = 1000;
2538 u32 pause = 0;
2539
2540 /* disable port */
2541 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2542
2543 /* wait for init credit */
2544 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2545 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2546 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
2547
2548 while ((init_crd != crd) && count) {
2549 msleep(5);
2550
2551 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2552 count--;
2553 }
2554 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2555 if (init_crd != crd)
2556 BNX2X_ERR("BUG! init_crd 0x%x != crd 0x%x\n", init_crd, crd);
2557
2558 if (bp->flow_ctrl & FLOW_CTRL_RX)
2559 pause = 1;
2560 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, pause);
2561 if (pause) {
2562 /* update threshold */
2563 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2564 /* update init credit */
2565 init_crd = 778; /* (800-18-4) */
2566
2567 } else {
2568 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)/16;
2569
2570 /* update threshold */
2571 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2572 /* update init credit */
2573 switch (bp->line_speed) {
2574 case SPEED_10:
2575 case SPEED_100:
2576 case SPEED_1000:
2577 init_crd = thresh + 55 - 22;
2578 break;
2579
2580 case SPEED_2500:
2581 init_crd = thresh + 138 - 22;
2582 break;
2583
2584 case SPEED_10000:
2585 init_crd = thresh + 553 - 22;
2586 break;
2587
2588 default:
2589 BNX2X_ERR("Invalid line_speed 0x%x\n",
2590 bp->line_speed);
2591 break;
2592 }
2593 }
2594 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2595 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2596 bp->line_speed, init_crd);
2597
2598 /* probe the credit changes */
2599 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2600 msleep(5);
2601 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2602
2603 /* enable port */
2604 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2605}
2606
2607static void bnx2x_update_mng(struct bnx2x *bp)
2608{
2609 if (!nomcp)
2610 SHMEM_WR(bp, port_mb[bp->port].link_status,
2611 bp->link_status);
2612} 1349}
2613 1350
2614static void bnx2x_link_report(struct bnx2x *bp) 1351static void bnx2x_link_report(struct bnx2x *bp)
2615{ 1352{
2616 if (bp->link_up) { 1353 if (bp->link_vars.link_up) {
2617 netif_carrier_on(bp->dev); 1354 if (bp->state == BNX2X_STATE_OPEN)
1355 netif_carrier_on(bp->dev);
2618 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name); 1356 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
2619 1357
2620 printk("%d Mbps ", bp->line_speed); 1358 printk("%d Mbps ", bp->link_vars.line_speed);
2621 1359
2622 if (bp->duplex == DUPLEX_FULL) 1360 if (bp->link_vars.duplex == DUPLEX_FULL)
2623 printk("full duplex"); 1361 printk("full duplex");
2624 else 1362 else
2625 printk("half duplex"); 1363 printk("half duplex");
2626 1364
2627 if (bp->flow_ctrl) { 1365 if (bp->link_vars.flow_ctrl != FLOW_CTRL_NONE) {
2628 if (bp->flow_ctrl & FLOW_CTRL_RX) { 1366 if (bp->link_vars.flow_ctrl & FLOW_CTRL_RX) {
2629 printk(", receive "); 1367 printk(", receive ");
2630 if (bp->flow_ctrl & FLOW_CTRL_TX) 1368 if (bp->link_vars.flow_ctrl & FLOW_CTRL_TX)
2631 printk("& transmit "); 1369 printk("& transmit ");
2632 } else { 1370 } else {
2633 printk(", transmit "); 1371 printk(", transmit ");
@@ -2638,1318 +1376,78 @@ static void bnx2x_link_report(struct bnx2x *bp)
2638 1376
2639 } else { /* link_down */ 1377 } else { /* link_down */
2640 netif_carrier_off(bp->dev); 1378 netif_carrier_off(bp->dev);
2641 printk(KERN_INFO PFX "%s NIC Link is Down\n", bp->dev->name); 1379 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
2642 }
2643}
2644
2645static void bnx2x_link_up(struct bnx2x *bp)
2646{
2647 int port = bp->port;
2648
2649 /* PBF - link up */
2650 bnx2x_pbf_update(bp);
2651
2652 /* disable drain */
2653 NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
2654
2655 /* update shared memory */
2656 bnx2x_update_mng(bp);
2657
2658 /* indicate link up */
2659 bnx2x_link_report(bp);
2660}
2661
2662static void bnx2x_link_down(struct bnx2x *bp)
2663{
2664 int port = bp->port;
2665
2666 /* notify stats */
2667 if (bp->stats_state != STATS_STATE_DISABLE) {
2668 bp->stats_state = STATS_STATE_STOP;
2669 DP(BNX2X_MSG_STATS, "stats_state - STOP\n");
2670 }
2671
2672 /* indicate no mac active */
2673 bp->phy_flags &= ~(PHY_BMAC_FLAG | PHY_EMAC_FLAG);
2674
2675 /* update shared memory */
2676 bnx2x_update_mng(bp);
2677
2678 /* activate nig drain */
2679 NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
2680
2681 /* reset BigMac */
2682 bnx2x_bmac_rx_disable(bp);
2683 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2684 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2685
2686 /* indicate link down */
2687 bnx2x_link_report(bp);
2688}
2689
2690static void bnx2x_init_mac_stats(struct bnx2x *bp);
2691
2692/* This function is called upon link interrupt */
2693static void bnx2x_link_update(struct bnx2x *bp)
2694{
2695 int port = bp->port;
2696 int i;
2697 u32 gp_status;
2698 int link_10g;
2699
2700 DP(NETIF_MSG_LINK, "port %x, %s, int_status 0x%x,"
2701 " int_mask 0x%x, saved_mask 0x%x, MI_INT %x, SERDES_LINK %x,"
2702 " 10G %x, XGXS_LINK %x\n", port,
2703 (bp->phy_flags & PHY_XGXS_FLAG)? "XGXS":"SerDes",
2704 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4),
2705 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), bp->nig_mask,
2706 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
2707 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c),
2708 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
2709 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)
2710 );
2711
2712 might_sleep();
2713 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_GP_STATUS);
2714 /* avoid fast toggling */
2715 for (i = 0; i < 10; i++) {
2716 msleep(10);
2717 bnx2x_mdio22_read(bp, MDIO_GP_STATUS_TOP_AN_STATUS1,
2718 &gp_status);
2719 } 1380 }
2720
2721 bnx2x_link_settings_status(bp, gp_status);
2722
2723 /* anything 10 and over uses the bmac */
2724 link_10g = ((bp->line_speed >= SPEED_10000) &&
2725 (bp->line_speed <= SPEED_16000));
2726
2727 bnx2x_link_int_ack(bp, link_10g);
2728
2729 /* link is up only if both local phy and external phy are up */
2730 bp->link_up = (bp->phy_link_up && bnx2x_ext_phy_is_link_up(bp));
2731 if (bp->link_up) {
2732 if (link_10g) {
2733 bnx2x_bmac_enable(bp, 0);
2734 bnx2x_leds_set(bp, SPEED_10000);
2735
2736 } else {
2737 bnx2x_emac_enable(bp);
2738 bnx2x_emac_program(bp);
2739
2740 /* AN complete? */
2741 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
2742 if (!(bp->phy_flags & PHY_SGMII_FLAG))
2743 bnx2x_set_sgmii_tx_driver(bp);
2744 }
2745 }
2746 bnx2x_link_up(bp);
2747
2748 } else { /* link down */
2749 bnx2x_leds_unset(bp);
2750 bnx2x_link_down(bp);
2751 }
2752
2753 bnx2x_init_mac_stats(bp);
2754} 1381}
2755 1382
2756/* 1383static u8 bnx2x_initial_phy_init(struct bnx2x *bp)
2757 * Init service functions
2758 */
2759
2760static void bnx2x_set_aer_mmd(struct bnx2x *bp)
2761{ 1384{
2762 u16 offset = (bp->phy_flags & PHY_XGXS_FLAG) ? 1385 u8 rc;
2763 (bp->phy_addr + bp->ser_lane) : 0;
2764 1386
2765 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_AER_BLOCK); 1387 /* Initialize link parameters structure variables */
2766 bnx2x_mdio22_write(bp, MDIO_AER_BLOCK_AER_REG, 0x3800 + offset); 1388 bp->link_params.mtu = bp->dev->mtu;
2767}
2768 1389
2769static void bnx2x_set_master_ln(struct bnx2x *bp) 1390 bnx2x_phy_hw_lock(bp);
2770{ 1391 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2771 u32 new_master_ln; 1392 bnx2x_phy_hw_unlock(bp);
2772
2773 /* set the master_ln for AN */
2774 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_XGXS_BLOCK2);
2775 bnx2x_mdio22_read(bp, MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
2776 &new_master_ln);
2777 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
2778 (new_master_ln | bp->ser_lane));
2779}
2780
2781static void bnx2x_reset_unicore(struct bnx2x *bp)
2782{
2783 u32 mii_control;
2784 int i;
2785
2786 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
2787 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
2788 /* reset the unicore */
2789 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
2790 (mii_control | MDIO_COMBO_IEEO_MII_CONTROL_RESET));
2791
2792 /* wait for the reset to self clear */
2793 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
2794 udelay(5);
2795
2796 /* the reset erased the previous bank value */
2797 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
2798 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
2799 &mii_control);
2800
2801 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
2802 udelay(5);
2803 return;
2804 }
2805 }
2806
2807 BNX2X_ERR("BUG! %s (0x%x) is still in reset!\n",
2808 (bp->phy_flags & PHY_XGXS_FLAG)? "XGXS":"SerDes",
2809 bp->phy_addr);
2810}
2811
2812static void bnx2x_set_swap_lanes(struct bnx2x *bp)
2813{
2814 /* Each two bits represents a lane number:
2815 No swap is 0123 => 0x1b no need to enable the swap */
2816
2817 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_XGXS_BLOCK2);
2818 if (bp->rx_lane_swap != 0x1b) {
2819 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_RX_LN_SWAP,
2820 (bp->rx_lane_swap |
2821 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
2822 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
2823 } else {
2824 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
2825 }
2826
2827 if (bp->tx_lane_swap != 0x1b) {
2828 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_TX_LN_SWAP,
2829 (bp->tx_lane_swap |
2830 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
2831 } else {
2832 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
2833 }
2834}
2835
2836static void bnx2x_set_parallel_detection(struct bnx2x *bp)
2837{
2838 u32 control2;
2839
2840 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_SERDES_DIGITAL);
2841 bnx2x_mdio22_read(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
2842 &control2);
2843
2844 if (bp->autoneg & AUTONEG_PARALLEL) {
2845 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
2846 } else {
2847 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
2848 }
2849 bnx2x_mdio22_write(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
2850 control2);
2851
2852 if (bp->phy_flags & PHY_XGXS_FLAG) {
2853 DP(NETIF_MSG_LINK, "XGXS\n");
2854 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_10G_PARALLEL_DETECT);
2855
2856 bnx2x_mdio22_write(bp,
2857 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
2858 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
2859
2860 bnx2x_mdio22_read(bp,
2861 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
2862 &control2);
2863
2864 if (bp->autoneg & AUTONEG_PARALLEL) {
2865 control2 |=
2866 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
2867 } else {
2868 control2 &=
2869 ~MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
2870 }
2871 bnx2x_mdio22_write(bp,
2872 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
2873 control2);
2874
2875 /* Disable parallel detection of HiG */
2876 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_XGXS_BLOCK2);
2877 bnx2x_mdio22_write(bp, MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
2878 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
2879 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
2880 }
2881}
2882
2883static void bnx2x_set_autoneg(struct bnx2x *bp)
2884{
2885 u32 reg_val;
2886
2887 /* CL37 Autoneg */
2888 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
2889 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
2890 if ((bp->req_autoneg & AUTONEG_SPEED) &&
2891 (bp->autoneg & AUTONEG_CL37)) {
2892 /* CL37 Autoneg Enabled */
2893 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
2894 } else {
2895 /* CL37 Autoneg Disabled */
2896 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2897 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
2898 }
2899 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
2900
2901 /* Enable/Disable Autodetection */
2902 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_SERDES_DIGITAL);
2903 bnx2x_mdio22_read(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
2904 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN;
2905
2906 if ((bp->req_autoneg & AUTONEG_SPEED) &&
2907 (bp->autoneg & AUTONEG_SGMII_FIBER_AUTODET)) {
2908 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
2909 } else {
2910 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
2911 }
2912 bnx2x_mdio22_write(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
2913
2914 /* Enable TetonII and BAM autoneg */
2915 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_BAM_NEXT_PAGE);
2916 bnx2x_mdio22_read(bp, MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
2917 &reg_val);
2918 if ((bp->req_autoneg & AUTONEG_SPEED) &&
2919 (bp->autoneg & AUTONEG_CL37) && (bp->autoneg & AUTONEG_BAM)) {
2920 /* Enable BAM aneg Mode and TetonII aneg Mode */
2921 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
2922 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
2923 } else {
2924 /* TetonII and BAM Autoneg Disabled */
2925 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
2926 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
2927 }
2928 bnx2x_mdio22_write(bp, MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
2929 reg_val);
2930
2931 /* Enable Clause 73 Aneg */
2932 if ((bp->req_autoneg & AUTONEG_SPEED) &&
2933 (bp->autoneg & AUTONEG_CL73)) {
2934 /* Enable BAM Station Manager */
2935 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_USERB0);
2936 bnx2x_mdio22_write(bp, MDIO_CL73_USERB0_CL73_BAM_CTRL1,
2937 (MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
2938 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
2939 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN));
2940
2941 /* Merge CL73 and CL37 aneg resolution */
2942 bnx2x_mdio22_read(bp, MDIO_CL73_USERB0_CL73_BAM_CTRL3,
2943 &reg_val);
2944 bnx2x_mdio22_write(bp, MDIO_CL73_USERB0_CL73_BAM_CTRL3,
2945 (reg_val |
2946 MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR));
2947
2948 /* Set the CL73 AN speed */
2949 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_IEEEB1);
2950 bnx2x_mdio22_read(bp, MDIO_CL73_IEEEB1_AN_ADV2, &reg_val);
2951 /* In the SerDes we support only the 1G.
2952 In the XGXS we support the 10G KX4
2953 but we currently do not support the KR */
2954 if (bp->phy_flags & PHY_XGXS_FLAG) {
2955 DP(NETIF_MSG_LINK, "XGXS\n");
2956 /* 10G KX4 */
2957 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
2958 } else {
2959 DP(NETIF_MSG_LINK, "SerDes\n");
2960 /* 1000M KX */
2961 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
2962 }
2963 bnx2x_mdio22_write(bp, MDIO_CL73_IEEEB1_AN_ADV2, reg_val);
2964
2965 /* CL73 Autoneg Enabled */
2966 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
2967 } else {
2968 /* CL73 Autoneg Disabled */
2969 reg_val = 0;
2970 }
2971 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_IEEEB0);
2972 bnx2x_mdio22_write(bp, MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
2973}
2974
2975/* program SerDes, forced speed */
2976static void bnx2x_program_serdes(struct bnx2x *bp)
2977{
2978 u32 reg_val;
2979
2980 /* program duplex, disable autoneg */
2981 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
2982 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
2983 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
2984 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN);
2985 if (bp->req_duplex == DUPLEX_FULL)
2986 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
2987 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
2988
2989 /* program speed
2990 - needed only if the speed is greater than 1G (2.5G or 10G) */
2991 if (bp->req_line_speed > SPEED_1000) {
2992 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_SERDES_DIGITAL);
2993 bnx2x_mdio22_read(bp, MDIO_SERDES_DIGITAL_MISC1, &reg_val);
2994 /* clearing the speed value before setting the right speed */
2995 reg_val &= ~MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK;
2996 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
2997 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
2998 if (bp->req_line_speed == SPEED_10000)
2999 reg_val |=
3000 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
3001 bnx2x_mdio22_write(bp, MDIO_SERDES_DIGITAL_MISC1, reg_val);
3002 }
3003}
3004
3005static void bnx2x_set_brcm_cl37_advertisment(struct bnx2x *bp)
3006{
3007 u32 val = 0;
3008
3009 /* configure the 48 bits for BAM AN */
3010 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_OVER_1G);
3011
3012 /* set extended capabilities */
3013 if (bp->advertising & ADVERTISED_2500baseX_Full)
3014 val |= MDIO_OVER_1G_UP1_2_5G;
3015 if (bp->advertising & ADVERTISED_10000baseT_Full)
3016 val |= MDIO_OVER_1G_UP1_10G;
3017 bnx2x_mdio22_write(bp, MDIO_OVER_1G_UP1, val);
3018
3019 bnx2x_mdio22_write(bp, MDIO_OVER_1G_UP3, 0);
3020}
3021
3022static void bnx2x_set_ieee_aneg_advertisment(struct bnx2x *bp)
3023{
3024 u32 an_adv;
3025
3026 /* for AN, we are always publishing full duplex */
3027 an_adv = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3028
3029 /* resolve pause mode and advertisement
3030 * Please refer to Table 28B-3 of the 802.3ab-1999 spec */
3031 if (bp->req_autoneg & AUTONEG_FLOW_CTRL) {
3032 switch (bp->req_flow_ctrl) {
3033 case FLOW_CTRL_AUTO:
3034 if (bp->dev->mtu <= 4500) {
3035 an_adv |=
3036 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3037 bp->advertising |= (ADVERTISED_Pause |
3038 ADVERTISED_Asym_Pause);
3039 } else {
3040 an_adv |=
3041 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3042 bp->advertising |= ADVERTISED_Asym_Pause;
3043 }
3044 break;
3045
3046 case FLOW_CTRL_TX:
3047 an_adv |=
3048 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3049 bp->advertising |= ADVERTISED_Asym_Pause;
3050 break;
3051
3052 case FLOW_CTRL_RX:
3053 if (bp->dev->mtu <= 4500) {
3054 an_adv |=
3055 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3056 bp->advertising |= (ADVERTISED_Pause |
3057 ADVERTISED_Asym_Pause);
3058 } else {
3059 an_adv |=
3060 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3061 bp->advertising &= ~(ADVERTISED_Pause |
3062 ADVERTISED_Asym_Pause);
3063 }
3064 break;
3065
3066 case FLOW_CTRL_BOTH:
3067 if (bp->dev->mtu <= 4500) {
3068 an_adv |=
3069 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3070 bp->advertising |= (ADVERTISED_Pause |
3071 ADVERTISED_Asym_Pause);
3072 } else {
3073 an_adv |=
3074 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3075 bp->advertising |= ADVERTISED_Asym_Pause;
3076 }
3077 break;
3078
3079 case FLOW_CTRL_NONE:
3080 default:
3081 an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3082 bp->advertising &= ~(ADVERTISED_Pause |
3083 ADVERTISED_Asym_Pause);
3084 break;
3085 }
3086 } else { /* forced mode */
3087 switch (bp->req_flow_ctrl) {
3088 case FLOW_CTRL_AUTO:
3089 DP(NETIF_MSG_LINK, "req_flow_ctrl 0x%x while"
3090 " req_autoneg 0x%x\n",
3091 bp->req_flow_ctrl, bp->req_autoneg);
3092 break;
3093
3094 case FLOW_CTRL_TX:
3095 an_adv |=
3096 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3097 bp->advertising |= ADVERTISED_Asym_Pause;
3098 break;
3099
3100 case FLOW_CTRL_RX:
3101 case FLOW_CTRL_BOTH:
3102 an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3103 bp->advertising |= (ADVERTISED_Pause |
3104 ADVERTISED_Asym_Pause);
3105 break;
3106
3107 case FLOW_CTRL_NONE:
3108 default:
3109 an_adv |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3110 bp->advertising &= ~(ADVERTISED_Pause |
3111 ADVERTISED_Asym_Pause);
3112 break;
3113 }
3114 }
3115
3116 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
3117 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_AUTO_NEG_ADV, an_adv);
3118}
3119
3120static void bnx2x_restart_autoneg(struct bnx2x *bp)
3121{
3122 if (bp->autoneg & AUTONEG_CL73) {
3123 /* enable and restart clause 73 aneg */
3124 u32 an_ctrl;
3125
3126 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_IEEEB0);
3127 bnx2x_mdio22_read(bp, MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
3128 &an_ctrl);
3129 bnx2x_mdio22_write(bp, MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
3130 (an_ctrl |
3131 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
3132 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
3133
3134 } else {
3135 /* Enable and restart BAM/CL37 aneg */
3136 u32 mii_control;
3137
3138 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
3139 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
3140 &mii_control);
3141 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
3142 (mii_control |
3143 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
3144 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
3145 }
3146}
3147
3148static void bnx2x_initialize_sgmii_process(struct bnx2x *bp)
3149{
3150 u32 control1;
3151
3152 /* in SGMII mode, the unicore is always slave */
3153 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_SERDES_DIGITAL);
3154 bnx2x_mdio22_read(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
3155 &control1);
3156 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
3157 /* set sgmii mode (and not fiber) */
3158 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
3159 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
3160 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
3161 bnx2x_mdio22_write(bp, MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
3162 control1);
3163
3164 /* if forced speed */
3165 if (!(bp->req_autoneg & AUTONEG_SPEED)) {
3166 /* set speed, disable autoneg */
3167 u32 mii_control;
3168
3169 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0);
3170 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
3171 &mii_control);
3172 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
3173 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK |
3174 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
3175
3176 switch (bp->req_line_speed) {
3177 case SPEED_100:
3178 mii_control |=
3179 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
3180 break;
3181 case SPEED_1000:
3182 mii_control |=
3183 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
3184 break;
3185 case SPEED_10:
3186 /* there is nothing to set for 10M */
3187 break;
3188 default:
3189 /* invalid speed for SGMII */
3190 DP(NETIF_MSG_LINK, "Invalid req_line_speed 0x%x\n",
3191 bp->req_line_speed);
3192 break;
3193 }
3194
3195 /* setting the full duplex */
3196 if (bp->req_duplex == DUPLEX_FULL)
3197 mii_control |=
3198 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
3199 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
3200 mii_control);
3201
3202 } else { /* AN mode */
3203 /* enable and restart AN */
3204 bnx2x_restart_autoneg(bp);
3205 }
3206}
3207
3208static void bnx2x_link_int_enable(struct bnx2x *bp)
3209{
3210 int port = bp->port;
3211 u32 ext_phy_type;
3212 u32 mask;
3213
3214 /* setting the status to report on link up
3215 for either XGXS or SerDes */
3216 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3217 (NIG_STATUS_XGXS0_LINK10G |
3218 NIG_STATUS_XGXS0_LINK_STATUS |
3219 NIG_STATUS_SERDES0_LINK_STATUS));
3220
3221 if (bp->phy_flags & PHY_XGXS_FLAG) {
3222 mask = (NIG_MASK_XGXS0_LINK10G |
3223 NIG_MASK_XGXS0_LINK_STATUS);
3224 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
3225 ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
3226 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3227 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
3228 (ext_phy_type !=
3229 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) {
3230 mask |= NIG_MASK_MI_INT;
3231 DP(NETIF_MSG_LINK, "enabled external phy int\n");
3232 }
3233
3234 } else { /* SerDes */
3235 mask = NIG_MASK_SERDES0_LINK_STATUS;
3236 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
3237 ext_phy_type = SERDES_EXT_PHY_TYPE(bp);
3238 if ((ext_phy_type !=
3239 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
3240 (ext_phy_type !=
3241 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN)) {
3242 mask |= NIG_MASK_MI_INT;
3243 DP(NETIF_MSG_LINK, "enabled external phy int\n");
3244 }
3245 }
3246 bnx2x_bits_en(bp,
3247 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
3248 mask);
3249 DP(NETIF_MSG_LINK, "port %x, %s, int_status 0x%x,"
3250 " int_mask 0x%x, MI_INT %x, SERDES_LINK %x,"
3251 " 10G %x, XGXS_LINK %x\n", port,
3252 (bp->phy_flags & PHY_XGXS_FLAG)? "XGXS":"SerDes",
3253 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4),
3254 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
3255 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
3256 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c),
3257 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
3258 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)
3259 );
3260}
3261
3262static void bnx2x_bcm8072_external_rom_boot(struct bnx2x *bp)
3263{
3264 u32 ext_phy_addr = ((bp->ext_phy_config &
3265 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3266 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3267 u32 fw_ver1, fw_ver2;
3268
3269 /* Need to wait 200ms after reset */
3270 msleep(200);
3271 /* Boot port from external ROM
3272 * Set ser_boot_ctl bit in the MISC_CTRL1 register
3273 */
3274 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3275 EXT_PHY_KR_PMA_PMD_DEVAD,
3276 EXT_PHY_KR_MISC_CTRL1, 0x0001);
3277
3278 /* Reset internal microprocessor */
3279 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3280 EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_GEN_CTRL,
3281 EXT_PHY_KR_ROM_RESET_INTERNAL_MP);
3282 /* set micro reset = 0 */
3283 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3284 EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_GEN_CTRL,
3285 EXT_PHY_KR_ROM_MICRO_RESET);
3286 /* Reset internal microprocessor */
3287 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3288 EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_GEN_CTRL,
3289 EXT_PHY_KR_ROM_RESET_INTERNAL_MP);
3290 /* wait for 100ms for code download via SPI port */
3291 msleep(100);
3292
3293 /* Clear ser_boot_ctl bit */
3294 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3295 EXT_PHY_KR_PMA_PMD_DEVAD,
3296 EXT_PHY_KR_MISC_CTRL1, 0x0000);
3297 /* Wait 100ms */
3298 msleep(100);
3299
3300 /* Print the PHY FW version */
3301 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0, ext_phy_addr,
3302 EXT_PHY_KR_PMA_PMD_DEVAD,
3303 0xca19, &fw_ver1);
3304 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0, ext_phy_addr,
3305 EXT_PHY_KR_PMA_PMD_DEVAD,
3306 0xca1a, &fw_ver2);
3307 DP(NETIF_MSG_LINK,
3308 "8072 FW version 0x%x:0x%x\n", fw_ver1, fw_ver2);
3309}
3310
3311static void bnx2x_bcm8072_force_10G(struct bnx2x *bp)
3312{
3313 u32 ext_phy_addr = ((bp->ext_phy_config &
3314 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3315 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3316
3317 /* Force KR or KX */
3318 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3319 EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_CTRL,
3320 0x2040);
3321 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3322 EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_CTRL2,
3323 0x000b);
3324 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3325 EXT_PHY_KR_PMA_PMD_DEVAD, EXT_PHY_KR_PMD_CTRL,
3326 0x0000);
3327 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0, ext_phy_addr,
3328 EXT_PHY_KR_AUTO_NEG_DEVAD, EXT_PHY_KR_CTRL,
3329 0x0000);
3330}
3331
3332static void bnx2x_ext_phy_init(struct bnx2x *bp)
3333{
3334 u32 ext_phy_type;
3335 u32 ext_phy_addr;
3336 u32 cnt;
3337 u32 ctrl;
3338 u32 val = 0;
3339
3340 if (bp->phy_flags & PHY_XGXS_FLAG) {
3341 ext_phy_addr = ((bp->ext_phy_config &
3342 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3343 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3344
3345 ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
3346 /* Make sure that the soft reset is off (expect for the 8072:
3347 * due to the lock, it will be done inside the specific
3348 * handling)
3349 */
3350 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3351 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
3352 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) &&
3353 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072)) {
3354 /* Wait for soft reset to get cleared upto 1 sec */
3355 for (cnt = 0; cnt < 1000; cnt++) {
3356 bnx2x_mdio45_read(bp, ext_phy_addr,
3357 EXT_PHY_OPT_PMA_PMD_DEVAD,
3358 EXT_PHY_OPT_CNTL, &ctrl);
3359 if (!(ctrl & (1<<15)))
3360 break;
3361 msleep(1);
3362 }
3363 DP(NETIF_MSG_LINK,
3364 "control reg 0x%x (after %d ms)\n", ctrl, cnt);
3365 }
3366
3367 switch (ext_phy_type) {
3368 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
3369 DP(NETIF_MSG_LINK, "XGXS Direct\n");
3370 break;
3371
3372 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
3373 DP(NETIF_MSG_LINK, "XGXS 8705\n");
3374
3375 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3376 EXT_PHY_OPT_PMA_PMD_DEVAD,
3377 EXT_PHY_OPT_PMD_MISC_CNTL,
3378 0x8288);
3379 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3380 EXT_PHY_OPT_PMA_PMD_DEVAD,
3381 EXT_PHY_OPT_PHY_IDENTIFIER,
3382 0x7fbf);
3383 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3384 EXT_PHY_OPT_PMA_PMD_DEVAD,
3385 EXT_PHY_OPT_CMU_PLL_BYPASS,
3386 0x0100);
3387 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3388 EXT_PHY_OPT_WIS_DEVAD,
3389 EXT_PHY_OPT_LASI_CNTL, 0x1);
3390 break;
3391
3392 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
3393 DP(NETIF_MSG_LINK, "XGXS 8706\n");
3394
3395 if (!(bp->req_autoneg & AUTONEG_SPEED)) {
3396 /* Force speed */
3397 if (bp->req_line_speed == SPEED_10000) {
3398 DP(NETIF_MSG_LINK,
3399 "XGXS 8706 force 10Gbps\n");
3400 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3401 EXT_PHY_OPT_PMA_PMD_DEVAD,
3402 EXT_PHY_OPT_PMD_DIGITAL_CNT,
3403 0x400);
3404 } else {
3405 /* Force 1Gbps */
3406 DP(NETIF_MSG_LINK,
3407 "XGXS 8706 force 1Gbps\n");
3408
3409 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3410 EXT_PHY_OPT_PMA_PMD_DEVAD,
3411 EXT_PHY_OPT_CNTL,
3412 0x0040);
3413
3414 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3415 EXT_PHY_OPT_PMA_PMD_DEVAD,
3416 EXT_PHY_OPT_CNTL2,
3417 0x000D);
3418 }
3419 1393
3420 /* Enable LASI */ 1394 if (bp->link_vars.link_up)
3421 bnx2x_mdio45_vwrite(bp, ext_phy_addr, 1395 bnx2x_link_report(bp);
3422 EXT_PHY_OPT_PMA_PMD_DEVAD,
3423 EXT_PHY_OPT_LASI_CNTL,
3424 0x1);
3425 } else {
3426 /* AUTONEG */
3427 /* Allow CL37 through CL73 */
3428 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
3429 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3430 EXT_PHY_AUTO_NEG_DEVAD,
3431 EXT_PHY_OPT_AN_CL37_CL73,
3432 0x040c);
3433
3434 /* Enable Full-Duplex advertisment on CL37 */
3435 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3436 EXT_PHY_AUTO_NEG_DEVAD,
3437 EXT_PHY_OPT_AN_CL37_FD,
3438 0x0020);
3439 /* Enable CL37 AN */
3440 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3441 EXT_PHY_AUTO_NEG_DEVAD,
3442 EXT_PHY_OPT_AN_CL37_AN,
3443 0x1000);
3444 /* Advertise 10G/1G support */
3445 if (bp->advertising &
3446 ADVERTISED_1000baseT_Full)
3447 val = (1<<5);
3448 if (bp->advertising &
3449 ADVERTISED_10000baseT_Full)
3450 val |= (1<<7);
3451
3452 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3453 EXT_PHY_AUTO_NEG_DEVAD,
3454 EXT_PHY_OPT_AN_ADV, val);
3455 /* Enable LASI */
3456 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3457 EXT_PHY_OPT_PMA_PMD_DEVAD,
3458 EXT_PHY_OPT_LASI_CNTL,
3459 0x1);
3460
3461 /* Enable clause 73 AN */
3462 bnx2x_mdio45_write(bp, ext_phy_addr,
3463 EXT_PHY_AUTO_NEG_DEVAD,
3464 EXT_PHY_OPT_CNTL,
3465 0x1200);
3466 }
3467 break;
3468
3469 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
3470 bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
3471 /* Wait for soft reset to get cleared upto 1 sec */
3472 for (cnt = 0; cnt < 1000; cnt++) {
3473 bnx2x_mdio45_ctrl_read(bp, GRCBASE_EMAC0,
3474 ext_phy_addr,
3475 EXT_PHY_OPT_PMA_PMD_DEVAD,
3476 EXT_PHY_OPT_CNTL, &ctrl);
3477 if (!(ctrl & (1<<15)))
3478 break;
3479 msleep(1);
3480 }
3481 DP(NETIF_MSG_LINK,
3482 "8072 control reg 0x%x (after %d ms)\n",
3483 ctrl, cnt);
3484
3485 bnx2x_bcm8072_external_rom_boot(bp);
3486 DP(NETIF_MSG_LINK, "Finshed loading 8072 KR ROM\n");
3487
3488 /* enable LASI */
3489 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3490 ext_phy_addr,
3491 EXT_PHY_KR_PMA_PMD_DEVAD,
3492 0x9000, 0x0400);
3493 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3494 ext_phy_addr,
3495 EXT_PHY_KR_PMA_PMD_DEVAD,
3496 EXT_PHY_KR_LASI_CNTL, 0x0004);
3497
3498 /* If this is forced speed, set to KR or KX
3499 * (all other are not supported)
3500 */
3501 if (!(bp->req_autoneg & AUTONEG_SPEED)) {
3502 if (bp->req_line_speed == SPEED_10000) {
3503 bnx2x_bcm8072_force_10G(bp);
3504 DP(NETIF_MSG_LINK,
3505 "Forced speed 10G on 8072\n");
3506 /* unlock */
3507 bnx2x_hw_unlock(bp,
3508 HW_LOCK_RESOURCE_8072_MDIO);
3509 break;
3510 } else
3511 val = (1<<5);
3512 } else {
3513
3514 /* Advertise 10G/1G support */
3515 if (bp->advertising &
3516 ADVERTISED_1000baseT_Full)
3517 val = (1<<5);
3518 if (bp->advertising &
3519 ADVERTISED_10000baseT_Full)
3520 val |= (1<<7);
3521 }
3522 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3523 ext_phy_addr,
3524 EXT_PHY_KR_AUTO_NEG_DEVAD,
3525 0x11, val);
3526 /* Add support for CL37 ( passive mode ) I */
3527 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3528 ext_phy_addr,
3529 EXT_PHY_KR_AUTO_NEG_DEVAD,
3530 0x8370, 0x040c);
3531 /* Add support for CL37 ( passive mode ) II */
3532 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3533 ext_phy_addr,
3534 EXT_PHY_KR_AUTO_NEG_DEVAD,
3535 0xffe4, 0x20);
3536 /* Add support for CL37 ( passive mode ) III */
3537 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3538 ext_phy_addr,
3539 EXT_PHY_KR_AUTO_NEG_DEVAD,
3540 0xffe0, 0x1000);
3541 /* Restart autoneg */
3542 msleep(500);
3543 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3544 ext_phy_addr,
3545 EXT_PHY_KR_AUTO_NEG_DEVAD,
3546 EXT_PHY_KR_CTRL, 0x1200);
3547 DP(NETIF_MSG_LINK, "8072 Autoneg Restart: "
3548 "1G %ssupported 10G %ssupported\n",
3549 (val & (1<<5)) ? "" : "not ",
3550 (val & (1<<7)) ? "" : "not ");
3551
3552 /* unlock */
3553 bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_8072_MDIO);
3554 break;
3555
3556 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
3557 DP(NETIF_MSG_LINK,
3558 "Setting the SFX7101 LASI indication\n");
3559 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3560 EXT_PHY_OPT_PMA_PMD_DEVAD,
3561 EXT_PHY_OPT_LASI_CNTL, 0x1);
3562 DP(NETIF_MSG_LINK,
3563 "Setting the SFX7101 LED to blink on traffic\n");
3564 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3565 EXT_PHY_OPT_PMA_PMD_DEVAD,
3566 0xC007, (1<<3));
3567
3568 /* read modify write pause advertizing */
3569 bnx2x_mdio45_read(bp, ext_phy_addr,
3570 EXT_PHY_KR_AUTO_NEG_DEVAD,
3571 EXT_PHY_KR_AUTO_NEG_ADVERT, &val);
3572 val &= ~EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_BOTH;
3573 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3574 if (bp->advertising & ADVERTISED_Pause)
3575 val |= EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE;
3576
3577 if (bp->advertising & ADVERTISED_Asym_Pause) {
3578 val |=
3579 EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_ASYMMETRIC;
3580 }
3581 DP(NETIF_MSG_LINK, "SFX7101 AN advertize 0x%x\n", val);
3582 bnx2x_mdio45_vwrite(bp, ext_phy_addr,
3583 EXT_PHY_KR_AUTO_NEG_DEVAD,
3584 EXT_PHY_KR_AUTO_NEG_ADVERT, val);
3585 /* Restart autoneg */
3586 bnx2x_mdio45_read(bp, ext_phy_addr,
3587 EXT_PHY_KR_AUTO_NEG_DEVAD,
3588 EXT_PHY_KR_CTRL, &val);
3589 val |= 0x200;
3590 bnx2x_mdio45_write(bp, ext_phy_addr,
3591 EXT_PHY_KR_AUTO_NEG_DEVAD,
3592 EXT_PHY_KR_CTRL, val);
3593 break;
3594
3595 default:
3596 BNX2X_ERR("BAD XGXS ext_phy_config 0x%x\n",
3597 bp->ext_phy_config);
3598 break;
3599 }
3600
3601 } else { /* SerDes */
3602/* ext_phy_addr = ((bp->ext_phy_config &
3603 PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK) >>
3604 PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT);
3605*/
3606 ext_phy_type = SERDES_EXT_PHY_TYPE(bp);
3607 switch (ext_phy_type) {
3608 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
3609 DP(NETIF_MSG_LINK, "SerDes Direct\n");
3610 break;
3611
3612 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
3613 DP(NETIF_MSG_LINK, "SerDes 5482\n");
3614 break;
3615
3616 default:
3617 DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
3618 bp->ext_phy_config);
3619 break;
3620 }
3621 }
3622}
3623
3624static void bnx2x_ext_phy_reset(struct bnx2x *bp)
3625{
3626 u32 ext_phy_type;
3627 u32 ext_phy_addr = ((bp->ext_phy_config &
3628 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3629 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3630 u32 board = (bp->board & SHARED_HW_CFG_BOARD_TYPE_MASK);
3631
3632 /* The PHY reset is controled by GPIO 1
3633 * Give it 1ms of reset pulse
3634 */
3635 if ((board != SHARED_HW_CFG_BOARD_TYPE_BCM957710T1002G) &&
3636 (board != SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G)) {
3637 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3638 MISC_REGISTERS_GPIO_OUTPUT_LOW);
3639 msleep(1);
3640 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3641 MISC_REGISTERS_GPIO_OUTPUT_HIGH);
3642 }
3643
3644 if (bp->phy_flags & PHY_XGXS_FLAG) {
3645 ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
3646 switch (ext_phy_type) {
3647 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
3648 DP(NETIF_MSG_LINK, "XGXS Direct\n");
3649 break;
3650
3651 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
3652 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
3653 DP(NETIF_MSG_LINK, "XGXS 8705/8706\n");
3654 bnx2x_mdio45_write(bp, ext_phy_addr,
3655 EXT_PHY_OPT_PMA_PMD_DEVAD,
3656 EXT_PHY_OPT_CNTL, 0xa040);
3657 break;
3658
3659 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
3660 DP(NETIF_MSG_LINK, "XGXS 8072\n");
3661 bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
3662 bnx2x_mdio45_ctrl_write(bp, GRCBASE_EMAC0,
3663 ext_phy_addr,
3664 EXT_PHY_KR_PMA_PMD_DEVAD,
3665 0, 1<<15);
3666 bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_8072_MDIO);
3667 break;
3668
3669 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
3670 DP(NETIF_MSG_LINK, "XGXS SFX7101\n");
3671 break;
3672
3673 default:
3674 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
3675 bp->ext_phy_config);
3676 break;
3677 }
3678
3679 } else { /* SerDes */
3680 ext_phy_type = SERDES_EXT_PHY_TYPE(bp);
3681 switch (ext_phy_type) {
3682 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
3683 DP(NETIF_MSG_LINK, "SerDes Direct\n");
3684 break;
3685
3686 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
3687 DP(NETIF_MSG_LINK, "SerDes 5482\n");
3688 break;
3689 1396
3690 default: 1397 bnx2x_calc_fc_adv(bp);
3691 DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n", 1398 return rc;
3692 bp->ext_phy_config);
3693 break;
3694 }
3695 }
3696} 1399}
3697 1400
3698static void bnx2x_link_initialize(struct bnx2x *bp) 1401static void bnx2x_link_set(struct bnx2x *bp)
3699{ 1402{
3700 int port = bp->port; 1403 bnx2x_phy_hw_lock(bp);
3701 1404 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
3702 /* disable attentions */ 1405 bnx2x_phy_hw_unlock(bp);
3703 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
3704 (NIG_MASK_XGXS0_LINK_STATUS |
3705 NIG_MASK_XGXS0_LINK10G |
3706 NIG_MASK_SERDES0_LINK_STATUS |
3707 NIG_MASK_MI_INT));
3708
3709 /* Activate the external PHY */
3710 bnx2x_ext_phy_reset(bp);
3711
3712 bnx2x_set_aer_mmd(bp);
3713
3714 if (bp->phy_flags & PHY_XGXS_FLAG)
3715 bnx2x_set_master_ln(bp);
3716
3717 /* reset the SerDes and wait for reset bit return low */
3718 bnx2x_reset_unicore(bp);
3719
3720 bnx2x_set_aer_mmd(bp);
3721
3722 /* setting the masterLn_def again after the reset */
3723 if (bp->phy_flags & PHY_XGXS_FLAG) {
3724 bnx2x_set_master_ln(bp);
3725 bnx2x_set_swap_lanes(bp);
3726 }
3727
3728 /* Set Parallel Detect */
3729 if (bp->req_autoneg & AUTONEG_SPEED)
3730 bnx2x_set_parallel_detection(bp);
3731
3732 if (bp->phy_flags & PHY_XGXS_FLAG) {
3733 if (bp->req_line_speed &&
3734 bp->req_line_speed < SPEED_1000) {
3735 bp->phy_flags |= PHY_SGMII_FLAG;
3736 } else {
3737 bp->phy_flags &= ~PHY_SGMII_FLAG;
3738 }
3739 }
3740
3741 if (!(bp->phy_flags & PHY_SGMII_FLAG)) {
3742 u16 bank, rx_eq;
3743
3744 rx_eq = ((bp->serdes_config &
3745 PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK) >>
3746 PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT);
3747
3748 DP(NETIF_MSG_LINK, "setting rx eq to %d\n", rx_eq);
3749 for (bank = MDIO_REG_BANK_RX0; bank <= MDIO_REG_BANK_RX_ALL;
3750 bank += (MDIO_REG_BANK_RX1 - MDIO_REG_BANK_RX0)) {
3751 MDIO_SET_REG_BANK(bp, bank);
3752 bnx2x_mdio22_write(bp, MDIO_RX0_RX_EQ_BOOST,
3753 ((rx_eq &
3754 MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK) |
3755 MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL));
3756 }
3757
3758 /* forced speed requested? */
3759 if (!(bp->req_autoneg & AUTONEG_SPEED)) {
3760 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
3761
3762 /* disable autoneg */
3763 bnx2x_set_autoneg(bp);
3764
3765 /* program speed and duplex */
3766 bnx2x_program_serdes(bp);
3767
3768 } else { /* AN_mode */
3769 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
3770
3771 /* AN enabled */
3772 bnx2x_set_brcm_cl37_advertisment(bp);
3773
3774 /* program duplex & pause advertisement (for aneg) */
3775 bnx2x_set_ieee_aneg_advertisment(bp);
3776
3777 /* enable autoneg */
3778 bnx2x_set_autoneg(bp);
3779
3780 /* enable and restart AN */
3781 bnx2x_restart_autoneg(bp);
3782 }
3783
3784 } else { /* SGMII mode */
3785 DP(NETIF_MSG_LINK, "SGMII\n");
3786
3787 bnx2x_initialize_sgmii_process(bp);
3788 }
3789
3790 /* init ext phy and enable link state int */
3791 bnx2x_ext_phy_init(bp);
3792 1406
3793 /* enable the interrupt */ 1407 bnx2x_calc_fc_adv(bp);
3794 bnx2x_link_int_enable(bp);
3795} 1408}
3796 1409
3797static void bnx2x_phy_deassert(struct bnx2x *bp) 1410static void bnx2x__link_reset(struct bnx2x *bp)
3798{ 1411{
3799 int port = bp->port; 1412 bnx2x_phy_hw_lock(bp);
3800 u32 val; 1413 bnx2x_link_reset(&bp->link_params, &bp->link_vars);
3801 1414 bnx2x_phy_hw_unlock(bp);
3802 if (bp->phy_flags & PHY_XGXS_FLAG) {
3803 DP(NETIF_MSG_LINK, "XGXS\n");
3804 val = XGXS_RESET_BITS;
3805
3806 } else { /* SerDes */
3807 DP(NETIF_MSG_LINK, "SerDes\n");
3808 val = SERDES_RESET_BITS;
3809 }
3810
3811 val = val << (port*16);
3812
3813 /* reset and unreset the SerDes/XGXS */
3814 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3815 msleep(5);
3816 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3817} 1415}
3818 1416
3819static int bnx2x_phy_init(struct bnx2x *bp) 1417static u8 bnx2x_link_test(struct bnx2x *bp)
3820{ 1418{
3821 DP(NETIF_MSG_LINK, "started\n"); 1419 u8 rc;
3822 if (CHIP_REV(bp) == CHIP_REV_FPGA) {
3823 bp->phy_flags |= PHY_EMAC_FLAG;
3824 bp->link_up = 1;
3825 bp->line_speed = SPEED_10000;
3826 bp->duplex = DUPLEX_FULL;
3827 NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + bp->port*4, 0);
3828 bnx2x_emac_enable(bp);
3829 bnx2x_link_report(bp);
3830 return 0;
3831 1420
3832 } else if (CHIP_REV(bp) == CHIP_REV_EMUL) { 1421 bnx2x_phy_hw_lock(bp);
3833 bp->phy_flags |= PHY_BMAC_FLAG; 1422 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars);
3834 bp->link_up = 1; 1423 bnx2x_phy_hw_unlock(bp);
3835 bp->line_speed = SPEED_10000;
3836 bp->duplex = DUPLEX_FULL;
3837 NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + bp->port*4, 0);
3838 bnx2x_bmac_enable(bp, 0);
3839 bnx2x_link_report(bp);
3840 return 0;
3841 1424
3842 } else { 1425 return rc;
3843 bnx2x_phy_deassert(bp);
3844 bnx2x_link_initialize(bp);
3845 }
3846
3847 return 0;
3848} 1426}
3849 1427
3850static void bnx2x_link_reset(struct bnx2x *bp) 1428/* This function is called upon link interrupt */
1429static void bnx2x_link_attn(struct bnx2x *bp)
3851{ 1430{
3852 int port = bp->port; 1431 bnx2x_phy_hw_lock(bp);
3853 u32 board = (bp->board & SHARED_HW_CFG_BOARD_TYPE_MASK); 1432 bnx2x_link_update(&bp->link_params, &bp->link_vars);
3854 1433 bnx2x_phy_hw_unlock(bp);
3855 /* update shared memory */
3856 bp->link_status = 0;
3857 bnx2x_update_mng(bp);
3858
3859 /* disable attentions */
3860 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
3861 (NIG_MASK_XGXS0_LINK_STATUS |
3862 NIG_MASK_XGXS0_LINK10G |
3863 NIG_MASK_SERDES0_LINK_STATUS |
3864 NIG_MASK_MI_INT));
3865
3866 /* activate nig drain */
3867 NIG_WR(NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
3868
3869 /* disable nig egress interface */
3870 NIG_WR(NIG_REG_BMAC0_OUT_EN + port*4, 0);
3871 NIG_WR(NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
3872
3873 /* Stop BigMac rx */
3874 bnx2x_bmac_rx_disable(bp);
3875
3876 /* disable emac */
3877 NIG_WR(NIG_REG_NIG_EMAC0_EN + port*4, 0);
3878
3879 msleep(10);
3880 1434
3881 /* The PHY reset is controled by GPIO 1 1435 /* indicate link status */
3882 * Hold it as output low 1436 bnx2x_link_report(bp);
3883 */
3884 if ((board != SHARED_HW_CFG_BOARD_TYPE_BCM957710T1002G) &&
3885 (board != SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G)) {
3886 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3887 MISC_REGISTERS_GPIO_OUTPUT_LOW);
3888 DP(NETIF_MSG_LINK, "reset external PHY\n");
3889 }
3890
3891 /* reset the SerDes/XGXS */
3892 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
3893 (0x1ff << (port*16)));
3894
3895 /* reset BigMac */
3896 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
3897 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
3898
3899 /* disable nig ingress interface */
3900 NIG_WR(NIG_REG_BMAC0_IN_EN + port*4, 0);
3901 NIG_WR(NIG_REG_EMAC0_IN_EN + port*4, 0);
3902
3903 /* set link down */
3904 bp->link_up = 0;
3905} 1437}
3906 1438
3907#ifdef BNX2X_XGXS_LB 1439static void bnx2x__link_status_update(struct bnx2x *bp)
3908static void bnx2x_set_xgxs_loopback(struct bnx2x *bp, int is_10g)
3909{ 1440{
3910 int port = bp->port; 1441 if (bp->state != BNX2X_STATE_OPEN)
3911 1442 return;
3912 if (is_10g) {
3913 u32 md_devad;
3914
3915 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
3916
3917 /* change the uni_phy_addr in the nig */
3918 REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18),
3919 &md_devad);
3920 NIG_WR(NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
3921
3922 /* change the aer mmd */
3923 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_AER_BLOCK);
3924 bnx2x_mdio22_write(bp, MDIO_AER_BLOCK_AER_REG, 0x2800);
3925
3926 /* config combo IEEE0 control reg for loopback */
3927 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_CL73_IEEEB0);
3928 bnx2x_mdio22_write(bp, MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
3929 0x6041);
3930
3931 /* set aer mmd back */
3932 bnx2x_set_aer_mmd(bp);
3933
3934 /* and md_devad */
3935 NIG_WR(NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, md_devad);
3936
3937 } else {
3938 u32 mii_control;
3939 1443
3940 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n"); 1444 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
3941 1445
3942 MDIO_SET_REG_BANK(bp, MDIO_REG_BANK_COMBO_IEEE0); 1446 /* indicate link status */
3943 bnx2x_mdio22_read(bp, MDIO_COMBO_IEEE0_MII_CONTROL, 1447 bnx2x_link_report(bp);
3944 &mii_control);
3945 bnx2x_mdio22_write(bp, MDIO_COMBO_IEEE0_MII_CONTROL,
3946 (mii_control |
3947 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK));
3948 }
3949} 1448}
3950#endif
3951 1449
3952/* end of PHY/MAC */ 1450/* end of Link */
3953 1451
3954/* slow path */ 1452/* slow path */
3955 1453
@@ -4113,7 +1611,7 @@ static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
4113 bp->nig_mask = REG_RD(bp, nig_int_mask_addr); 1611 bp->nig_mask = REG_RD(bp, nig_int_mask_addr);
4114 REG_WR(bp, nig_int_mask_addr, 0); 1612 REG_WR(bp, nig_int_mask_addr, 0);
4115 1613
4116 bnx2x_link_update(bp); 1614 bnx2x_link_attn(bp);
4117 1615
4118 /* handle unicore attn? */ 1616 /* handle unicore attn? */
4119 } 1617 }
@@ -4196,14 +1694,14 @@ static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4196 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 1694 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4197 MISC_REGISTERS_GPIO_OUTPUT_LOW); 1695 MISC_REGISTERS_GPIO_OUTPUT_LOW);
4198 /* mark the failure */ 1696 /* mark the failure */
4199 bp->ext_phy_config &= 1697 bp->link_params.ext_phy_config &=
4200 ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 1698 ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4201 bp->ext_phy_config |= 1699 bp->link_params.ext_phy_config |=
4202 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; 1700 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4203 SHMEM_WR(bp, 1701 SHMEM_WR(bp,
4204 dev_info.port_hw_config[port]. 1702 dev_info.port_hw_config[port].
4205 external_phy_config, 1703 external_phy_config,
4206 bp->ext_phy_config); 1704 bp->link_params.ext_phy_config);
4207 /* log the failure */ 1705 /* log the failure */
4208 printk(KERN_ERR PFX "Fan Failure on Network" 1706 printk(KERN_ERR PFX "Fan Failure on Network"
4209 " Controller %s has caused the driver to" 1707 " Controller %s has caused the driver to"
@@ -4580,7 +2078,7 @@ static void bnx2x_init_mac_stats(struct bnx2x *bp)
4580#endif 2078#endif
4581 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0)); 2079 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
4582 2080
4583 if (bp->link_up) 2081 if (bp->link_vars.link_up)
4584 opcode |= (DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE); 2082 opcode |= (DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE);
4585 2083
4586 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]); 2084 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
@@ -4593,7 +2091,7 @@ static void bnx2x_init_mac_stats(struct bnx2x *bp)
4593 dmae->dst_addr_hi = 0; 2091 dmae->dst_addr_hi = 0;
4594 dmae->len = (offsetof(struct bnx2x_eth_stats, mac_stx_end) - 2092 dmae->len = (offsetof(struct bnx2x_eth_stats, mac_stx_end) -
4595 sizeof(u32)) >> 2; 2093 sizeof(u32)) >> 2;
4596 if (bp->link_up) { 2094 if (bp->link_vars.link_up) {
4597 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2; 2095 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
4598 dmae->comp_addr_hi = 0; 2096 dmae->comp_addr_hi = 0;
4599 dmae->comp_val = 1; 2097 dmae->comp_val = 1;
@@ -4604,7 +2102,7 @@ static void bnx2x_init_mac_stats(struct bnx2x *bp)
4604 } 2102 }
4605 } 2103 }
4606 2104
4607 if (!bp->link_up) { 2105 if (!bp->link_vars.link_up) {
4608 /* no need to collect statistics in link down */ 2106 /* no need to collect statistics in link down */
4609 return; 2107 return;
4610 } 2108 }
@@ -4619,7 +2117,7 @@ static void bnx2x_init_mac_stats(struct bnx2x *bp)
4619#endif 2117#endif
4620 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0)); 2118 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0));
4621 2119
4622 if (bp->phy_flags & PHY_BMAC_FLAG) { 2120 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
4623 2121
4624 mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM : 2122 mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
4625 NIG_REG_INGRESS_BMAC0_MEM); 2123 NIG_REG_INGRESS_BMAC0_MEM);
@@ -4656,7 +2154,7 @@ static void bnx2x_init_mac_stats(struct bnx2x *bp)
4656 dmae->comp_addr_hi = 0; 2154 dmae->comp_addr_hi = 0;
4657 dmae->comp_val = 1; 2155 dmae->comp_val = 1;
4658 2156
4659 } else if (bp->phy_flags & PHY_EMAC_FLAG) { 2157 } else if (bp->link_vars.mac_type == MAC_TYPE_EMAC) {
4660 2158
4661 mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0); 2159 mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
4662 2160
@@ -5099,10 +2597,10 @@ static void bnx2x_update_stats(struct bnx2x *bp)
5099 2597
5100 if (!bnx2x_update_storm_stats(bp)) { 2598 if (!bnx2x_update_storm_stats(bp)) {
5101 2599
5102 if (bp->phy_flags & PHY_BMAC_FLAG) { 2600 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
5103 bnx2x_update_bmac_stats(bp); 2601 bnx2x_update_bmac_stats(bp);
5104 2602
5105 } else if (bp->phy_flags & PHY_EMAC_FLAG) { 2603 } else if (bp->link_vars.mac_type == MAC_TYPE_EMAC) {
5106 bnx2x_update_emac_stats(bp); 2604 bnx2x_update_emac_stats(bp);
5107 2605
5108 } else { /* unreached */ 2606 } else { /* unreached */
@@ -6568,7 +4066,7 @@ static int bnx2x_function_init(struct bnx2x *bp, int mode)
6568 break; 4066 break;
6569 } 4067 }
6570 4068
6571 bnx2x_link_reset(bp); 4069 bnx2x__link_reset(bp);
6572 4070
6573 /* Reset PCIE errors for debug */ 4071 /* Reset PCIE errors for debug */
6574 REG_WR(bp, 0x2114, 0xffffffff); 4072 REG_WR(bp, 0x2114, 0xffffffff);
@@ -7210,7 +4708,7 @@ static int bnx2x_nic_load(struct bnx2x *bp, int req_irq)
7210 4708
7211 bnx2x_set_mac_addr(bp); 4709 bnx2x_set_mac_addr(bp);
7212 4710
7213 bnx2x_phy_init(bp); 4711 bnx2x_initial_phy_init(bp);
7214 4712
7215 /* Start fast path */ 4713 /* Start fast path */
7216 if (req_irq) { /* IRQ is only requested from bnx2x_open */ 4714 if (req_irq) { /* IRQ is only requested from bnx2x_open */
@@ -7435,7 +4933,7 @@ static int bnx2x_nic_unload(struct bnx2x *bp, int free_irq)
7435 } 4933 }
7436 4934
7437unload_error: 4935unload_error:
7438 bnx2x_link_reset(bp); 4936 bnx2x__link_reset(bp);
7439 4937
7440 if (!nomcp) 4938 if (!nomcp)
7441 reset_code = bnx2x_fw_command(bp, reset_code); 4939 reset_code = bnx2x_fw_command(bp, reset_code);
@@ -7477,13 +4975,12 @@ static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
7477 int port = bp->port; 4975 int port = bp->port;
7478 u32 ext_phy_type; 4976 u32 ext_phy_type;
7479 4977
7480 bp->phy_flags = 0;
7481
7482 switch (switch_cfg) { 4978 switch (switch_cfg) {
7483 case SWITCH_CFG_1G: 4979 case SWITCH_CFG_1G:
7484 BNX2X_DEV_INFO("switch_cfg 0x%x (1G)\n", switch_cfg); 4980 BNX2X_DEV_INFO("switch_cfg 0x%x (1G)\n", switch_cfg);
7485 4981
7486 ext_phy_type = SERDES_EXT_PHY_TYPE(bp); 4982 ext_phy_type =
4983 SERDES_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
7487 switch (ext_phy_type) { 4984 switch (ext_phy_type) {
7488 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT: 4985 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
7489 BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n", 4986 BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
@@ -7505,8 +5002,6 @@ static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
7505 BNX2X_DEV_INFO("ext_phy_type 0x%x (5482)\n", 5002 BNX2X_DEV_INFO("ext_phy_type 0x%x (5482)\n",
7506 ext_phy_type); 5003 ext_phy_type);
7507 5004
7508 bp->phy_flags |= PHY_SGMII_FLAG;
7509
7510 bp->supported |= (SUPPORTED_10baseT_Half | 5005 bp->supported |= (SUPPORTED_10baseT_Half |
7511 SUPPORTED_10baseT_Full | 5006 SUPPORTED_10baseT_Full |
7512 SUPPORTED_100baseT_Half | 5007 SUPPORTED_100baseT_Half |
@@ -7521,7 +5016,7 @@ static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
7521 default: 5016 default:
7522 BNX2X_ERR("NVRAM config error. " 5017 BNX2X_ERR("NVRAM config error. "
7523 "BAD SerDes ext_phy_config 0x%x\n", 5018 "BAD SerDes ext_phy_config 0x%x\n",
7524 bp->ext_phy_config); 5019 bp->link_params.ext_phy_config);
7525 return; 5020 return;
7526 } 5021 }
7527 5022
@@ -7533,9 +5028,8 @@ static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
7533 case SWITCH_CFG_10G: 5028 case SWITCH_CFG_10G:
7534 BNX2X_DEV_INFO("switch_cfg 0x%x (10G)\n", switch_cfg); 5029 BNX2X_DEV_INFO("switch_cfg 0x%x (10G)\n", switch_cfg);
7535 5030
7536 bp->phy_flags |= PHY_XGXS_FLAG; 5031 ext_phy_type =
7537 5032 XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
7538 ext_phy_type = XGXS_EXT_PHY_TYPE(bp);
7539 switch (ext_phy_type) { 5033 switch (ext_phy_type) {
7540 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 5034 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7541 BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n", 5035 BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
@@ -7588,6 +5082,19 @@ static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
7588 SUPPORTED_Asym_Pause); 5082 SUPPORTED_Asym_Pause);
7589 break; 5083 break;
7590 5084
5085 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
5086 BNX2X_DEV_INFO("ext_phy_type 0x%x (8073)\n",
5087 ext_phy_type);
5088
5089 bp->supported |= (SUPPORTED_10000baseT_Full |
5090 SUPPORTED_2500baseX_Full |
5091 SUPPORTED_1000baseT_Full |
5092 SUPPORTED_FIBRE |
5093 SUPPORTED_Autoneg |
5094 SUPPORTED_Pause |
5095 SUPPORTED_Asym_Pause);
5096 break;
5097
7591 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: 5098 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
7592 BNX2X_DEV_INFO("ext_phy_type 0x%x (SFX7101)\n", 5099 BNX2X_DEV_INFO("ext_phy_type 0x%x (SFX7101)\n",
7593 ext_phy_type); 5100 ext_phy_type);
@@ -7599,10 +5106,15 @@ static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
7599 SUPPORTED_Asym_Pause); 5106 SUPPORTED_Asym_Pause);
7600 break; 5107 break;
7601 5108
5109 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
5110 BNX2X_ERR("XGXS PHY Failure detected 0x%x\n",
5111 bp->link_params.ext_phy_config);
5112 break;
5113
7602 default: 5114 default:
7603 BNX2X_ERR("NVRAM config error. " 5115 BNX2X_ERR("NVRAM config error. "
7604 "BAD XGXS ext_phy_config 0x%x\n", 5116 "BAD XGXS ext_phy_config 0x%x\n",
7605 bp->ext_phy_config); 5117 bp->link_params.ext_phy_config);
7606 return; 5118 return;
7607 } 5119 }
7608 5120
@@ -7610,17 +5122,6 @@ static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
7610 port*0x18); 5122 port*0x18);
7611 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->phy_addr); 5123 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->phy_addr);
7612 5124
7613 bp->ser_lane = ((bp->lane_config &
7614 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
7615 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
7616 bp->rx_lane_swap = ((bp->lane_config &
7617 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
7618 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
7619 bp->tx_lane_swap = ((bp->lane_config &
7620 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
7621 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
7622 BNX2X_DEV_INFO("rx_lane_swap 0x%x tx_lane_swap 0x%x\n",
7623 bp->rx_lane_swap, bp->tx_lane_swap);
7624 break; 5125 break;
7625 5126
7626 default: 5127 default:
@@ -7628,32 +5129,36 @@ static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
7628 bp->link_config); 5129 bp->link_config);
7629 return; 5130 return;
7630 } 5131 }
5132 bp->link_params.phy_addr = bp->phy_addr;
7631 5133
7632 /* mask what we support according to speed_cap_mask */ 5134 /* mask what we support according to speed_cap_mask */
7633 if (!(bp->speed_cap_mask & 5135 if (!(bp->link_params.speed_cap_mask &
7634 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) 5136 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
7635 bp->supported &= ~SUPPORTED_10baseT_Half; 5137 bp->supported &= ~SUPPORTED_10baseT_Half;
7636 5138
7637 if (!(bp->speed_cap_mask & 5139 if (!(bp->link_params.speed_cap_mask &
7638 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) 5140 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
7639 bp->supported &= ~SUPPORTED_10baseT_Full; 5141 bp->supported &= ~SUPPORTED_10baseT_Full;
7640 5142
7641 if (!(bp->speed_cap_mask & 5143 if (!(bp->link_params.speed_cap_mask &
7642 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) 5144 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
7643 bp->supported &= ~SUPPORTED_100baseT_Half; 5145 bp->supported &= ~SUPPORTED_100baseT_Half;
7644 5146
7645 if (!(bp->speed_cap_mask & 5147 if (!(bp->link_params.speed_cap_mask &
7646 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) 5148 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
7647 bp->supported &= ~SUPPORTED_100baseT_Full; 5149 bp->supported &= ~SUPPORTED_100baseT_Full;
7648 5150
7649 if (!(bp->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) 5151 if (!(bp->link_params.speed_cap_mask &
5152 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
7650 bp->supported &= ~(SUPPORTED_1000baseT_Half | 5153 bp->supported &= ~(SUPPORTED_1000baseT_Half |
7651 SUPPORTED_1000baseT_Full); 5154 SUPPORTED_1000baseT_Full);
7652 5155
7653 if (!(bp->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 5156 if (!(bp->link_params.speed_cap_mask &
5157 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7654 bp->supported &= ~SUPPORTED_2500baseX_Full; 5158 bp->supported &= ~SUPPORTED_2500baseX_Full;
7655 5159
7656 if (!(bp->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) 5160 if (!(bp->link_params.speed_cap_mask &
5161 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
7657 bp->supported &= ~SUPPORTED_10000baseT_Full; 5162 bp->supported &= ~SUPPORTED_10000baseT_Full;
7658 5163
7659 BNX2X_DEV_INFO("supported 0x%x\n", bp->supported); 5164 BNX2X_DEV_INFO("supported 0x%x\n", bp->supported);
@@ -7661,20 +5166,23 @@ static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
7661 5166
7662static void bnx2x_link_settings_requested(struct bnx2x *bp) 5167static void bnx2x_link_settings_requested(struct bnx2x *bp)
7663{ 5168{
7664 bp->req_autoneg = 0; 5169 bp->link_params.req_duplex = DUPLEX_FULL;
7665 bp->req_duplex = DUPLEX_FULL;
7666 5170
7667 switch (bp->link_config & PORT_FEATURE_LINK_SPEED_MASK) { 5171 switch (bp->link_config & PORT_FEATURE_LINK_SPEED_MASK) {
7668 case PORT_FEATURE_LINK_SPEED_AUTO: 5172 case PORT_FEATURE_LINK_SPEED_AUTO:
7669 if (bp->supported & SUPPORTED_Autoneg) { 5173 if (bp->supported & SUPPORTED_Autoneg) {
7670 bp->req_autoneg |= AUTONEG_SPEED; 5174 bp->link_params.req_line_speed = SPEED_AUTO_NEG;
7671 bp->req_line_speed = 0;
7672 bp->advertising = bp->supported; 5175 bp->advertising = bp->supported;
7673 } else { 5176 } else {
7674 if (XGXS_EXT_PHY_TYPE(bp) == 5177 u32 ext_phy_type =
7675 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) { 5178 XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
5179
5180 if ((ext_phy_type ==
5181 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
5182 (ext_phy_type ==
5183 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706)) {
7676 /* force 10G, no AN */ 5184 /* force 10G, no AN */
7677 bp->req_line_speed = SPEED_10000; 5185 bp->link_params.req_line_speed = SPEED_10000;
7678 bp->advertising = 5186 bp->advertising =
7679 (ADVERTISED_10000baseT_Full | 5187 (ADVERTISED_10000baseT_Full |
7680 ADVERTISED_FIBRE); 5188 ADVERTISED_FIBRE);
@@ -7690,86 +5198,92 @@ static void bnx2x_link_settings_requested(struct bnx2x *bp)
7690 5198
7691 case PORT_FEATURE_LINK_SPEED_10M_FULL: 5199 case PORT_FEATURE_LINK_SPEED_10M_FULL:
7692 if (bp->supported & SUPPORTED_10baseT_Full) { 5200 if (bp->supported & SUPPORTED_10baseT_Full) {
7693 bp->req_line_speed = SPEED_10; 5201 bp->link_params.req_line_speed = SPEED_10;
7694 bp->advertising = (ADVERTISED_10baseT_Full | 5202 bp->advertising = (ADVERTISED_10baseT_Full |
7695 ADVERTISED_TP); 5203 ADVERTISED_TP);
7696 } else { 5204 } else {
7697 BNX2X_ERR("NVRAM config error. " 5205 BNX2X_ERR("NVRAM config error. "
7698 "Invalid link_config 0x%x" 5206 "Invalid link_config 0x%x"
7699 " speed_cap_mask 0x%x\n", 5207 " speed_cap_mask 0x%x\n",
7700 bp->link_config, bp->speed_cap_mask); 5208 bp->link_config,
5209 bp->link_params.speed_cap_mask);
7701 return; 5210 return;
7702 } 5211 }
7703 break; 5212 break;
7704 5213
7705 case PORT_FEATURE_LINK_SPEED_10M_HALF: 5214 case PORT_FEATURE_LINK_SPEED_10M_HALF:
7706 if (bp->supported & SUPPORTED_10baseT_Half) { 5215 if (bp->supported & SUPPORTED_10baseT_Half) {
7707 bp->req_line_speed = SPEED_10; 5216 bp->link_params.req_line_speed = SPEED_10;
7708 bp->req_duplex = DUPLEX_HALF; 5217 bp->link_params.req_duplex = DUPLEX_HALF;
7709 bp->advertising = (ADVERTISED_10baseT_Half | 5218 bp->advertising = (ADVERTISED_10baseT_Half |
7710 ADVERTISED_TP); 5219 ADVERTISED_TP);
7711 } else { 5220 } else {
7712 BNX2X_ERR("NVRAM config error. " 5221 BNX2X_ERR("NVRAM config error. "
7713 "Invalid link_config 0x%x" 5222 "Invalid link_config 0x%x"
7714 " speed_cap_mask 0x%x\n", 5223 " speed_cap_mask 0x%x\n",
7715 bp->link_config, bp->speed_cap_mask); 5224 bp->link_config,
5225 bp->link_params.speed_cap_mask);
7716 return; 5226 return;
7717 } 5227 }
7718 break; 5228 break;
7719 5229
7720 case PORT_FEATURE_LINK_SPEED_100M_FULL: 5230 case PORT_FEATURE_LINK_SPEED_100M_FULL:
7721 if (bp->supported & SUPPORTED_100baseT_Full) { 5231 if (bp->supported & SUPPORTED_100baseT_Full) {
7722 bp->req_line_speed = SPEED_100; 5232 bp->link_params.req_line_speed = SPEED_100;
7723 bp->advertising = (ADVERTISED_100baseT_Full | 5233 bp->advertising = (ADVERTISED_100baseT_Full |
7724 ADVERTISED_TP); 5234 ADVERTISED_TP);
7725 } else { 5235 } else {
7726 BNX2X_ERR("NVRAM config error. " 5236 BNX2X_ERR("NVRAM config error. "
7727 "Invalid link_config 0x%x" 5237 "Invalid link_config 0x%x"
7728 " speed_cap_mask 0x%x\n", 5238 " speed_cap_mask 0x%x\n",
7729 bp->link_config, bp->speed_cap_mask); 5239 bp->link_config,
5240 bp->link_params.speed_cap_mask);
7730 return; 5241 return;
7731 } 5242 }
7732 break; 5243 break;
7733 5244
7734 case PORT_FEATURE_LINK_SPEED_100M_HALF: 5245 case PORT_FEATURE_LINK_SPEED_100M_HALF:
7735 if (bp->supported & SUPPORTED_100baseT_Half) { 5246 if (bp->supported & SUPPORTED_100baseT_Half) {
7736 bp->req_line_speed = SPEED_100; 5247 bp->link_params.req_line_speed = SPEED_100;
7737 bp->req_duplex = DUPLEX_HALF; 5248 bp->link_params.req_duplex = DUPLEX_HALF;
7738 bp->advertising = (ADVERTISED_100baseT_Half | 5249 bp->advertising = (ADVERTISED_100baseT_Half |
7739 ADVERTISED_TP); 5250 ADVERTISED_TP);
7740 } else { 5251 } else {
7741 BNX2X_ERR("NVRAM config error. " 5252 BNX2X_ERR("NVRAM config error. "
7742 "Invalid link_config 0x%x" 5253 "Invalid link_config 0x%x"
7743 " speed_cap_mask 0x%x\n", 5254 " speed_cap_mask 0x%x\n",
7744 bp->link_config, bp->speed_cap_mask); 5255 bp->link_config,
5256 bp->link_params.speed_cap_mask);
7745 return; 5257 return;
7746 } 5258 }
7747 break; 5259 break;
7748 5260
7749 case PORT_FEATURE_LINK_SPEED_1G: 5261 case PORT_FEATURE_LINK_SPEED_1G:
7750 if (bp->supported & SUPPORTED_1000baseT_Full) { 5262 if (bp->supported & SUPPORTED_1000baseT_Full) {
7751 bp->req_line_speed = SPEED_1000; 5263 bp->link_params.req_line_speed = SPEED_1000;
7752 bp->advertising = (ADVERTISED_1000baseT_Full | 5264 bp->advertising = (ADVERTISED_1000baseT_Full |
7753 ADVERTISED_TP); 5265 ADVERTISED_TP);
7754 } else { 5266 } else {
7755 BNX2X_ERR("NVRAM config error. " 5267 BNX2X_ERR("NVRAM config error. "
7756 "Invalid link_config 0x%x" 5268 "Invalid link_config 0x%x"
7757 " speed_cap_mask 0x%x\n", 5269 " speed_cap_mask 0x%x\n",
7758 bp->link_config, bp->speed_cap_mask); 5270 bp->link_config,
5271 bp->link_params.speed_cap_mask);
7759 return; 5272 return;
7760 } 5273 }
7761 break; 5274 break;
7762 5275
7763 case PORT_FEATURE_LINK_SPEED_2_5G: 5276 case PORT_FEATURE_LINK_SPEED_2_5G:
7764 if (bp->supported & SUPPORTED_2500baseX_Full) { 5277 if (bp->supported & SUPPORTED_2500baseX_Full) {
7765 bp->req_line_speed = SPEED_2500; 5278 bp->link_params.req_line_speed = SPEED_2500;
7766 bp->advertising = (ADVERTISED_2500baseX_Full | 5279 bp->advertising = (ADVERTISED_2500baseX_Full |
7767 ADVERTISED_TP); 5280 ADVERTISED_TP);
7768 } else { 5281 } else {
7769 BNX2X_ERR("NVRAM config error. " 5282 BNX2X_ERR("NVRAM config error. "
7770 "Invalid link_config 0x%x" 5283 "Invalid link_config 0x%x"
7771 " speed_cap_mask 0x%x\n", 5284 " speed_cap_mask 0x%x\n",
7772 bp->link_config, bp->speed_cap_mask); 5285 bp->link_config,
5286 bp->link_params.speed_cap_mask);
7773 return; 5287 return;
7774 } 5288 }
7775 break; 5289 break;
@@ -7778,14 +5292,15 @@ static void bnx2x_link_settings_requested(struct bnx2x *bp)
7778 case PORT_FEATURE_LINK_SPEED_10G_KX4: 5292 case PORT_FEATURE_LINK_SPEED_10G_KX4:
7779 case PORT_FEATURE_LINK_SPEED_10G_KR: 5293 case PORT_FEATURE_LINK_SPEED_10G_KR:
7780 if (bp->supported & SUPPORTED_10000baseT_Full) { 5294 if (bp->supported & SUPPORTED_10000baseT_Full) {
7781 bp->req_line_speed = SPEED_10000; 5295 bp->link_params.req_line_speed = SPEED_10000;
7782 bp->advertising = (ADVERTISED_10000baseT_Full | 5296 bp->advertising = (ADVERTISED_10000baseT_Full |
7783 ADVERTISED_FIBRE); 5297 ADVERTISED_FIBRE);
7784 } else { 5298 } else {
7785 BNX2X_ERR("NVRAM config error. " 5299 BNX2X_ERR("NVRAM config error. "
7786 "Invalid link_config 0x%x" 5300 "Invalid link_config 0x%x"
7787 " speed_cap_mask 0x%x\n", 5301 " speed_cap_mask 0x%x\n",
7788 bp->link_config, bp->speed_cap_mask); 5302 bp->link_config,
5303 bp->link_params.speed_cap_mask);
7789 return; 5304 return;
7790 } 5305 }
7791 break; 5306 break;
@@ -7794,30 +5309,28 @@ static void bnx2x_link_settings_requested(struct bnx2x *bp)
7794 BNX2X_ERR("NVRAM config error. " 5309 BNX2X_ERR("NVRAM config error. "
7795 "BAD link speed link_config 0x%x\n", 5310 "BAD link speed link_config 0x%x\n",
7796 bp->link_config); 5311 bp->link_config);
7797 bp->req_autoneg |= AUTONEG_SPEED; 5312 bp->link_params.req_line_speed = SPEED_AUTO_NEG;
7798 bp->req_line_speed = 0;
7799 bp->advertising = bp->supported; 5313 bp->advertising = bp->supported;
7800 break; 5314 break;
7801 } 5315 }
7802 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d\n",
7803 bp->req_line_speed, bp->req_duplex);
7804 5316
7805 bp->req_flow_ctrl = (bp->link_config & 5317 bp->link_params.req_flow_ctrl = (bp->link_config &
7806 PORT_FEATURE_FLOW_CONTROL_MASK); 5318 PORT_FEATURE_FLOW_CONTROL_MASK);
7807 if ((bp->req_flow_ctrl == FLOW_CTRL_AUTO) && 5319 if ((bp->link_params.req_flow_ctrl == FLOW_CTRL_AUTO) &&
7808 (bp->supported & SUPPORTED_Autoneg)) 5320 (!bp->supported & SUPPORTED_Autoneg))
7809 bp->req_autoneg |= AUTONEG_FLOW_CTRL; 5321 bp->link_params.req_flow_ctrl = FLOW_CTRL_NONE;
7810 5322
7811 BNX2X_DEV_INFO("req_autoneg 0x%x req_flow_ctrl 0x%x" 5323 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x"
7812 " advertising 0x%x\n", 5324 " advertising 0x%x\n",
7813 bp->req_autoneg, bp->req_flow_ctrl, bp->advertising); 5325 bp->link_params.req_line_speed,
5326 bp->link_params.req_duplex,
5327 bp->link_params.req_flow_ctrl, bp->advertising);
7814} 5328}
7815 5329
7816static void bnx2x_get_hwinfo(struct bnx2x *bp) 5330static void bnx2x_get_hwinfo(struct bnx2x *bp)
7817{ 5331{
7818 u32 val, val2, val3, val4, id; 5332 u32 val, val2, val3, val4, id;
7819 int port = bp->port; 5333 int port = bp->port;
7820 u32 switch_cfg;
7821 5334
7822 bp->shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); 5335 bp->shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7823 BNX2X_DEV_INFO("shmem offset is %x\n", bp->shmem_base); 5336 BNX2X_DEV_INFO("shmem offset is %x\n", bp->shmem_base);
@@ -7835,6 +5348,8 @@ static void bnx2x_get_hwinfo(struct bnx2x *bp)
7835 bp->chip_id = id; 5348 bp->chip_id = id;
7836 BNX2X_DEV_INFO("chip ID is %x\n", id); 5349 BNX2X_DEV_INFO("chip ID is %x\n", id);
7837 5350
5351 bp->link_params.bp = bp;
5352
7838 if (!bp->shmem_base || (bp->shmem_base != 0xAF900)) { 5353 if (!bp->shmem_base || (bp->shmem_base != 0xAF900)) {
7839 BNX2X_DEV_INFO("MCP not active\n"); 5354 BNX2X_DEV_INFO("MCP not active\n");
7840 nomcp = 1; 5355 nomcp = 1;
@@ -7851,35 +5366,32 @@ static void bnx2x_get_hwinfo(struct bnx2x *bp)
7851 5366
7852 bp->hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); 5367 bp->hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
7853 bp->board = SHMEM_RD(bp, dev_info.shared_hw_config.board); 5368 bp->board = SHMEM_RD(bp, dev_info.shared_hw_config.board);
7854 bp->serdes_config = 5369 bp->link_params.serdes_config =
7855 SHMEM_RD(bp, dev_info.port_hw_config[port].serdes_config); 5370 SHMEM_RD(bp, dev_info.port_hw_config[port].serdes_config);
7856 bp->lane_config = 5371 bp->link_params.lane_config =
7857 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); 5372 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
7858 bp->ext_phy_config = 5373 bp->link_params.ext_phy_config =
7859 SHMEM_RD(bp, 5374 SHMEM_RD(bp,
7860 dev_info.port_hw_config[port].external_phy_config); 5375 dev_info.port_hw_config[port].external_phy_config);
7861 bp->speed_cap_mask = 5376 bp->link_params.speed_cap_mask =
7862 SHMEM_RD(bp, 5377 SHMEM_RD(bp,
7863 dev_info.port_hw_config[port].speed_capability_mask); 5378 dev_info.port_hw_config[port].speed_capability_mask);
7864 5379
7865 bp->link_config = 5380 bp->link_config =
7866 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); 5381 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
7867 5382
7868 BNX2X_DEV_INFO("hw_config (%08x) board (%08x) serdes_config (%08x)\n" 5383 BNX2X_DEV_INFO("serdes_config (%08x) lane_config (%08x)\n"
7869 KERN_INFO " lane_config (%08x) ext_phy_config (%08x)\n" 5384 KERN_INFO " ext_phy_config (%08x) speed_cap_mask (%08x)"
7870 KERN_INFO " speed_cap_mask (%08x) link_config (%08x)" 5385 " link_config (%08x)\n",
7871 " fw_seq (%08x)\n", 5386 bp->link_params.serdes_config,
7872 bp->hw_config, bp->board, bp->serdes_config, 5387 bp->link_params.lane_config,
7873 bp->lane_config, bp->ext_phy_config, 5388 bp->link_params.ext_phy_config,
7874 bp->speed_cap_mask, bp->link_config, bp->fw_seq); 5389 bp->link_params.speed_cap_mask,
7875 5390 bp->link_config);
7876 switch_cfg = (bp->link_config & PORT_FEATURE_CONNECTED_SWITCH_MASK);
7877 bnx2x_link_settings_supported(bp, switch_cfg);
7878 5391
7879 bp->autoneg = (bp->hw_config & SHARED_HW_CFG_AN_ENABLE_MASK); 5392 bp->link_params.switch_cfg = (bp->link_config &
7880 /* for now disable cl73 */ 5393 PORT_FEATURE_CONNECTED_SWITCH_MASK);
7881 bp->autoneg &= ~SHARED_HW_CFG_AN_ENABLE_CL73; 5394 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
7882 BNX2X_DEV_INFO("autoneg 0x%x\n", bp->autoneg);
7883 5395
7884 bnx2x_link_settings_requested(bp); 5396 bnx2x_link_settings_requested(bp);
7885 5397
@@ -7891,8 +5403,9 @@ static void bnx2x_get_hwinfo(struct bnx2x *bp)
7891 bp->dev->dev_addr[3] = (u8)(val >> 16 & 0xff); 5403 bp->dev->dev_addr[3] = (u8)(val >> 16 & 0xff);
7892 bp->dev->dev_addr[4] = (u8)(val >> 8 & 0xff); 5404 bp->dev->dev_addr[4] = (u8)(val >> 8 & 0xff);
7893 bp->dev->dev_addr[5] = (u8)(val & 0xff); 5405 bp->dev->dev_addr[5] = (u8)(val & 0xff);
5406 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
5407 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
7894 5408
7895 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, 6);
7896 5409
7897 5410
7898 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); 5411 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
@@ -7945,21 +5458,23 @@ static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7945 cmd->advertising = bp->advertising; 5458 cmd->advertising = bp->advertising;
7946 5459
7947 if (netif_carrier_ok(dev)) { 5460 if (netif_carrier_ok(dev)) {
7948 cmd->speed = bp->line_speed; 5461 cmd->speed = bp->link_vars.line_speed;
7949 cmd->duplex = bp->duplex; 5462 cmd->duplex = bp->link_vars.duplex;
7950 } else { 5463 } else {
7951 cmd->speed = bp->req_line_speed; 5464 cmd->speed = bp->link_params.req_line_speed;
7952 cmd->duplex = bp->req_duplex; 5465 cmd->duplex = bp->link_params.req_duplex;
7953 } 5466 }
7954 5467
7955 if (bp->phy_flags & PHY_XGXS_FLAG) { 5468 if (bp->link_params.switch_cfg == SWITCH_CFG_10G) {
7956 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp); 5469 u32 ext_phy_type =
5470 XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
7957 5471
7958 switch (ext_phy_type) { 5472 switch (ext_phy_type) {
7959 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 5473 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7960 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: 5474 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
7961 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: 5475 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
7962 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: 5476 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
5477 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
7963 cmd->port = PORT_FIBRE; 5478 cmd->port = PORT_FIBRE;
7964 break; 5479 break;
7965 5480
@@ -7967,9 +5482,15 @@ static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7967 cmd->port = PORT_TP; 5482 cmd->port = PORT_TP;
7968 break; 5483 break;
7969 5484
5485 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
5486 BNX2X_ERR("XGXS PHY Failure detected 0x%x\n",
5487 bp->link_params.ext_phy_config);
5488 break;
5489
7970 default: 5490 default:
7971 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n", 5491 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
7972 bp->ext_phy_config); 5492 bp->link_params.ext_phy_config);
5493 break;
7973 } 5494 }
7974 } else 5495 } else
7975 cmd->port = PORT_TP; 5496 cmd->port = PORT_TP;
@@ -7977,7 +5498,7 @@ static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7977 cmd->phy_address = bp->phy_addr; 5498 cmd->phy_address = bp->phy_addr;
7978 cmd->transceiver = XCVR_INTERNAL; 5499 cmd->transceiver = XCVR_INTERNAL;
7979 5500
7980 if (bp->req_autoneg & AUTONEG_SPEED) 5501 if (bp->link_params.req_line_speed == SPEED_AUTO_NEG)
7981 cmd->autoneg = AUTONEG_ENABLE; 5502 cmd->autoneg = AUTONEG_ENABLE;
7982 else 5503 else
7983 cmd->autoneg = AUTONEG_DISABLE; 5504 cmd->autoneg = AUTONEG_DISABLE;
@@ -8018,9 +5539,8 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8018 /* advertise the requested speed and duplex if supported */ 5539 /* advertise the requested speed and duplex if supported */
8019 cmd->advertising &= bp->supported; 5540 cmd->advertising &= bp->supported;
8020 5541
8021 bp->req_autoneg |= AUTONEG_SPEED; 5542 bp->link_params.req_line_speed = SPEED_AUTO_NEG;
8022 bp->req_line_speed = 0; 5543 bp->link_params.req_duplex = DUPLEX_FULL;
8023 bp->req_duplex = DUPLEX_FULL;
8024 bp->advertising |= (ADVERTISED_Autoneg | cmd->advertising); 5544 bp->advertising |= (ADVERTISED_Autoneg | cmd->advertising);
8025 5545
8026 } else { /* forced speed */ 5546 } else { /* forced speed */
@@ -8126,34 +5646,45 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8126 return -EINVAL; 5646 return -EINVAL;
8127 } 5647 }
8128 5648
8129 bp->req_autoneg &= ~AUTONEG_SPEED; 5649 bp->link_params.req_line_speed = cmd->speed;
8130 bp->req_line_speed = cmd->speed; 5650 bp->link_params.req_duplex = cmd->duplex;
8131 bp->req_duplex = cmd->duplex;
8132 bp->advertising = advertising; 5651 bp->advertising = advertising;
8133 } 5652 }
8134 5653
8135 DP(NETIF_MSG_LINK, "req_autoneg 0x%x req_line_speed %d\n" 5654 DP(NETIF_MSG_LINK, "req_line_speed %d\n"
8136 DP_LEVEL " req_duplex %d advertising 0x%x\n", 5655 DP_LEVEL " req_duplex %d advertising 0x%x\n",
8137 bp->req_autoneg, bp->req_line_speed, bp->req_duplex, 5656 bp->link_params.req_line_speed, bp->link_params.req_duplex,
8138 bp->advertising); 5657 bp->advertising);
8139 5658
8140 bnx2x_stop_stats(bp); 5659 bnx2x_stop_stats(bp);
8141 bnx2x_link_initialize(bp); 5660 bnx2x_link_set(bp);
8142 5661
8143 return 0; 5662 return 0;
8144} 5663}
8145 5664
5665#define PHY_FW_VER_LEN 10
5666
8146static void bnx2x_get_drvinfo(struct net_device *dev, 5667static void bnx2x_get_drvinfo(struct net_device *dev,
8147 struct ethtool_drvinfo *info) 5668 struct ethtool_drvinfo *info)
8148{ 5669{
8149 struct bnx2x *bp = netdev_priv(dev); 5670 struct bnx2x *bp = netdev_priv(dev);
5671 char phy_fw_ver[PHY_FW_VER_LEN];
8150 5672
8151 strcpy(info->driver, DRV_MODULE_NAME); 5673 strcpy(info->driver, DRV_MODULE_NAME);
8152 strcpy(info->version, DRV_MODULE_VERSION); 5674 strcpy(info->version, DRV_MODULE_VERSION);
8153 snprintf(info->fw_version, 32, "%d.%d.%d:%d (BC VER %x)", 5675
5676 phy_fw_ver[0] = '\0';
5677 bnx2x_phy_hw_lock(bp);
5678 bnx2x_get_ext_phy_fw_version(&bp->link_params,
5679 (bp->state != BNX2X_STATE_CLOSED),
5680 phy_fw_ver, PHY_FW_VER_LEN);
5681 bnx2x_phy_hw_unlock(bp);
5682
5683 snprintf(info->fw_version, 32, "%d.%d.%d:%d BC:%x%s%s",
8154 BCM_5710_FW_MAJOR_VERSION, BCM_5710_FW_MINOR_VERSION, 5684 BCM_5710_FW_MAJOR_VERSION, BCM_5710_FW_MINOR_VERSION,
8155 BCM_5710_FW_REVISION_VERSION, BCM_5710_FW_COMPILE_FLAGS, 5685 BCM_5710_FW_REVISION_VERSION,
8156 bp->bc_ver); 5686 BCM_5710_FW_COMPILE_FLAGS, bp->bc_ver,
5687 ((phy_fw_ver[0] != '\0')? " PHY:":""), phy_fw_ver);
8157 strcpy(info->bus_info, pci_name(bp->pdev)); 5688 strcpy(info->bus_info, pci_name(bp->pdev));
8158 info->n_stats = BNX2X_NUM_STATS; 5689 info->n_stats = BNX2X_NUM_STATS;
8159 info->testinfo_len = BNX2X_NUM_TESTS; 5690 info->testinfo_len = BNX2X_NUM_TESTS;
@@ -8221,7 +5752,7 @@ static int bnx2x_nway_reset(struct net_device *dev)
8221 } 5752 }
8222 5753
8223 bnx2x_stop_stats(bp); 5754 bnx2x_stop_stats(bp);
8224 bnx2x_link_initialize(bp); 5755 bnx2x_link_set(bp);
8225 5756
8226 return 0; 5757 return 0;
8227} 5758}
@@ -8605,7 +6136,22 @@ static int bnx2x_set_eeprom(struct net_device *dev,
8605 6136
8606 /* parameters already validated in ethtool_set_eeprom */ 6137 /* parameters already validated in ethtool_set_eeprom */
8607 6138
8608 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len); 6139 /* If the magic number is PHY (0x00504859) upgrade the PHY FW */
6140 if (eeprom->magic == 0x00504859) {
6141
6142 bnx2x_phy_hw_lock(bp);
6143 rc = bnx2x_flash_download(bp, bp->port,
6144 bp->link_params.ext_phy_config,
6145 (bp->state != BNX2X_STATE_CLOSED),
6146 eebuf, eeprom->len);
6147 rc |= bnx2x_link_reset(&bp->link_params,
6148 &bp->link_vars);
6149 rc |= bnx2x_phy_init(&bp->link_params,
6150 &bp->link_vars);
6151 bnx2x_phy_hw_unlock(bp);
6152
6153 } else
6154 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
8609 6155
8610 return rc; 6156 return rc;
8611} 6157}
@@ -8691,10 +6237,13 @@ static void bnx2x_get_pauseparam(struct net_device *dev,
8691{ 6237{
8692 struct bnx2x *bp = netdev_priv(dev); 6238 struct bnx2x *bp = netdev_priv(dev);
8693 6239
8694 epause->autoneg = 6240 epause->autoneg = (bp->link_params.req_flow_ctrl == FLOW_CTRL_AUTO) &&
8695 ((bp->req_autoneg & AUTONEG_FLOW_CTRL) == AUTONEG_FLOW_CTRL); 6241 (bp->link_params.req_line_speed == SPEED_AUTO_NEG);
8696 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) == FLOW_CTRL_RX); 6242
8697 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) == FLOW_CTRL_TX); 6243 epause->rx_pause = ((bp->link_vars.flow_ctrl & FLOW_CTRL_RX) ==
6244 FLOW_CTRL_RX);
6245 epause->tx_pause = ((bp->link_vars.flow_ctrl & FLOW_CTRL_TX) ==
6246 FLOW_CTRL_TX);
8698 6247
8699 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n" 6248 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
8700 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n", 6249 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
@@ -8710,32 +6259,31 @@ static int bnx2x_set_pauseparam(struct net_device *dev,
8710 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n", 6259 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
8711 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 6260 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
8712 6261
8713 if (epause->autoneg) { 6262 bp->link_params.req_flow_ctrl = FLOW_CTRL_AUTO;
8714 if (!(bp->supported & SUPPORTED_Autoneg)) {
8715 DP(NETIF_MSG_LINK, "Aotoneg not supported\n");
8716 return -EINVAL;
8717 }
8718
8719 bp->req_autoneg |= AUTONEG_FLOW_CTRL;
8720 } else
8721 bp->req_autoneg &= ~AUTONEG_FLOW_CTRL;
8722
8723 bp->req_flow_ctrl = FLOW_CTRL_AUTO;
8724 6263
8725 if (epause->rx_pause) 6264 if (epause->rx_pause)
8726 bp->req_flow_ctrl |= FLOW_CTRL_RX; 6265 bp->link_params.req_flow_ctrl |= FLOW_CTRL_RX;
6266
8727 if (epause->tx_pause) 6267 if (epause->tx_pause)
8728 bp->req_flow_ctrl |= FLOW_CTRL_TX; 6268 bp->link_params.req_flow_ctrl |= FLOW_CTRL_TX;
8729 6269
8730 if (!(bp->req_autoneg & AUTONEG_FLOW_CTRL) && 6270 if (bp->link_params.req_flow_ctrl == FLOW_CTRL_AUTO)
8731 (bp->req_flow_ctrl == FLOW_CTRL_AUTO)) 6271 bp->link_params.req_flow_ctrl = FLOW_CTRL_NONE;
8732 bp->req_flow_ctrl = FLOW_CTRL_NONE;
8733 6272
8734 DP(NETIF_MSG_LINK, "req_autoneg 0x%x req_flow_ctrl 0x%x\n", 6273 if (epause->autoneg) {
8735 bp->req_autoneg, bp->req_flow_ctrl); 6274 if (!(bp->supported & SUPPORTED_Autoneg)) {
6275 DP(NETIF_MSG_LINK, "Autoneg not supported\n");
6276 return -EINVAL;
6277 }
6278
6279 if (bp->link_params.req_line_speed == SPEED_AUTO_NEG)
6280 bp->link_params.req_flow_ctrl = FLOW_CTRL_AUTO;
6281 }
8736 6282
6283 DP(NETIF_MSG_LINK,
6284 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl);
8737 bnx2x_stop_stats(bp); 6285 bnx2x_stop_stats(bp);
8738 bnx2x_link_initialize(bp); 6286 bnx2x_link_set(bp);
8739 6287
8740 return 0; 6288 return 0;
8741} 6289}
@@ -8943,18 +6491,25 @@ static int bnx2x_phys_id(struct net_device *dev, u32 data)
8943 data = 2; 6491 data = 2;
8944 6492
8945 for (i = 0; i < (data * 2); i++) { 6493 for (i = 0; i < (data * 2); i++) {
8946 if ((i % 2) == 0) { 6494 if ((i % 2) == 0)
8947 bnx2x_leds_set(bp, SPEED_1000); 6495 bnx2x_set_led(bp, bp->port, LED_MODE_OPER, SPEED_1000,
8948 } else { 6496 bp->link_params.hw_led_mode,
8949 bnx2x_leds_unset(bp); 6497 bp->link_params.chip_id);
8950 } 6498 else
6499 bnx2x_set_led(bp, bp->port, LED_MODE_OFF, 0,
6500 bp->link_params.hw_led_mode,
6501 bp->link_params.chip_id);
6502
8951 msleep_interruptible(500); 6503 msleep_interruptible(500);
8952 if (signal_pending(current)) 6504 if (signal_pending(current))
8953 break; 6505 break;
8954 } 6506 }
8955 6507
8956 if (bp->link_up) 6508 if (bp->link_vars.link_up)
8957 bnx2x_leds_set(bp, bp->line_speed); 6509 bnx2x_set_led(bp, bp->port, LED_MODE_OPER,
6510 bp->link_vars.line_speed,
6511 bp->link_params.hw_led_mode,
6512 bp->link_params.chip_id);
8958 6513
8959 return 0; 6514 return 0;
8960} 6515}
@@ -9470,7 +7025,7 @@ static int bnx2x_change_mac_addr(struct net_device *dev, void *p)
9470 return 0; 7025 return 0;
9471} 7026}
9472 7027
9473/* Called with rtnl_lock */ 7028/* called with rtnl_lock */
9474static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 7029static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9475{ 7030{
9476 struct mii_ioctl_data *data = if_mii(ifr); 7031 struct mii_ioctl_data *data = if_mii(ifr);
@@ -9482,19 +7037,19 @@ static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9482 data->phy_id = bp->phy_addr; 7037 data->phy_id = bp->phy_addr;
9483 7038
9484 /* fallthrough */ 7039 /* fallthrough */
7040
9485 case SIOCGMIIREG: { 7041 case SIOCGMIIREG: {
9486 u32 mii_regval; 7042 u16 mii_regval;
9487 7043
9488 spin_lock_bh(&bp->phy_lock); 7044 if (!netif_running(dev))
9489 if (bp->state == BNX2X_STATE_OPEN) { 7045 return -EAGAIN;
9490 err = bnx2x_mdio22_read(bp, data->reg_num & 0x1f,
9491 &mii_regval);
9492 7046
9493 data->val_out = mii_regval; 7047 mutex_lock(&bp->phy_mutex);
9494 } else { 7048 err = bnx2x_cl45_read(bp, bp->port, 0, bp->phy_addr,
9495 err = -EAGAIN; 7049 DEFAULT_PHY_DEV_ADDR,
9496 } 7050 (data->reg_num & 0x1f), &mii_regval);
9497 spin_unlock_bh(&bp->phy_lock); 7051 data->val_out = mii_regval;
7052 mutex_unlock(&bp->phy_mutex);
9498 return err; 7053 return err;
9499 } 7054 }
9500 7055
@@ -9502,14 +7057,14 @@ static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9502 if (!capable(CAP_NET_ADMIN)) 7057 if (!capable(CAP_NET_ADMIN))
9503 return -EPERM; 7058 return -EPERM;
9504 7059
9505 spin_lock_bh(&bp->phy_lock); 7060 if (!netif_running(dev))
9506 if (bp->state == BNX2X_STATE_OPEN) { 7061 return -EAGAIN;
9507 err = bnx2x_mdio22_write(bp, data->reg_num & 0x1f, 7062
9508 data->val_in); 7063 mutex_lock(&bp->phy_mutex);
9509 } else { 7064 err = bnx2x_cl45_write(bp, bp->port, 0, bp->phy_addr,
9510 err = -EAGAIN; 7065 DEFAULT_PHY_DEV_ADDR,
9511 } 7066 (data->reg_num & 0x1f), data->val_in);
9512 spin_unlock_bh(&bp->phy_lock); 7067 mutex_unlock(&bp->phy_mutex);
9513 return err; 7068 return err;
9514 7069
9515 default: 7070 default:
@@ -9682,8 +7237,6 @@ static int __devinit bnx2x_init_board(struct pci_dev *pdev,
9682 bp->dev = dev; 7237 bp->dev = dev;
9683 bp->pdev = pdev; 7238 bp->pdev = pdev;
9684 7239
9685 spin_lock_init(&bp->phy_lock);
9686
9687 INIT_WORK(&bp->reset_task, bnx2x_reset_task); 7240 INIT_WORK(&bp->reset_task, bnx2x_reset_task);
9688 INIT_WORK(&bp->sp_task, bnx2x_sp_task); 7241 INIT_WORK(&bp->sp_task, bnx2x_sp_task);
9689 7242
diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h
index 5a1aa0b55044..8707c0d05d9a 100644
--- a/drivers/net/bnx2x_reg.h
+++ b/drivers/net/bnx2x_reg.h
@@ -72,6 +72,8 @@
72#define CCM_REG_CCM_INT_MASK 0xd01e4 72#define CCM_REG_CCM_INT_MASK 0xd01e4
73/* [R 11] Interrupt register #0 read */ 73/* [R 11] Interrupt register #0 read */
74#define CCM_REG_CCM_INT_STS 0xd01d8 74#define CCM_REG_CCM_INT_STS 0xd01d8
75/* [R 27] Parity register #0 read */
76#define CCM_REG_CCM_PRTY_STS 0xd01e8
75/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS 77/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
76 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 78 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
77 Is used to determine the number of the AG context REG-pairs written back; 79 Is used to determine the number of the AG context REG-pairs written back;
@@ -190,25 +192,20 @@
190 weight 8 (the most prioritised); 1 stands for weight 1(least 192 weight 8 (the most prioritised); 1 stands for weight 1(least
191 prioritised); 2 stands for weight 2; tc. */ 193 prioritised); 2 stands for weight 2; tc. */
192#define CCM_REG_PBF_WEIGHT 0xd00ac 194#define CCM_REG_PBF_WEIGHT 0xd00ac
193/* [RW 6] The physical queue number of queue number 1 per port index. */
194#define CCM_REG_PHYS_QNUM1_0 0xd0134 195#define CCM_REG_PHYS_QNUM1_0 0xd0134
195#define CCM_REG_PHYS_QNUM1_1 0xd0138 196#define CCM_REG_PHYS_QNUM1_1 0xd0138
196/* [RW 6] The physical queue number of queue number 2 per port index. */
197#define CCM_REG_PHYS_QNUM2_0 0xd013c 197#define CCM_REG_PHYS_QNUM2_0 0xd013c
198#define CCM_REG_PHYS_QNUM2_1 0xd0140 198#define CCM_REG_PHYS_QNUM2_1 0xd0140
199/* [RW 6] The physical queue number of queue number 3 per port index. */
200#define CCM_REG_PHYS_QNUM3_0 0xd0144 199#define CCM_REG_PHYS_QNUM3_0 0xd0144
201/* [RW 6] The physical queue number of queue number 0 with QOS equal 0 port 200#define CCM_REG_PHYS_QNUM3_1 0xd0148
202 index 0. */
203#define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114 201#define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114
204#define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118 202#define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118
205/* [RW 6] The physical queue number of queue number 0 with QOS equal 1 port
206 index 0. */
207#define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c 203#define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c
208#define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120 204#define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120
209/* [RW 6] The physical queue number of queue number 0 with QOS equal 2 port
210 index 0. */
211#define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124 205#define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124
206#define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128
207#define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c
208#define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130
212/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is 209/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
213 disregarded; acknowledge output is deasserted; all other signals are 210 disregarded; acknowledge output is deasserted; all other signals are
214 treated as usual; if 1 - normal activity. */ 211 treated as usual; if 1 - normal activity. */
@@ -253,6 +250,7 @@
253 mechanism. The fields are: [5:0] - message length; [12:6] - message 250 mechanism. The fields are: [5:0] - message length; [12:6] - message
254 pointer; 18:13] - next pointer. */ 251 pointer; 18:13] - next pointer. */
255#define CCM_REG_XX_DESCR_TABLE 0xd0300 252#define CCM_REG_XX_DESCR_TABLE 0xd0300
253#define CCM_REG_XX_DESCR_TABLE_SIZE 36
256/* [R 7] Used to read the value of XX protection Free counter. */ 254/* [R 7] Used to read the value of XX protection Free counter. */
257#define CCM_REG_XX_FREE 0xd0184 255#define CCM_REG_XX_FREE 0xd0184
258/* [RW 6] Initial value for the credit counter; responsible for fulfilling 256/* [RW 6] Initial value for the credit counter; responsible for fulfilling
@@ -296,6 +294,8 @@
296/* [WB 24] MATT ram access. each entry has the following 294/* [WB 24] MATT ram access. each entry has the following
297 format:{RegionLength[11:0]; egionOffset[11:0]} */ 295 format:{RegionLength[11:0]; egionOffset[11:0]} */
298#define CDU_REG_MATT 0x101100 296#define CDU_REG_MATT 0x101100
297/* [RW 1] when this bit is set the CDU operates in e1hmf mode */
298#define CDU_REG_MF_MODE 0x101050
299/* [R 1] indication the initializing the activity counter by the hardware 299/* [R 1] indication the initializing the activity counter by the hardware
300 was done. */ 300 was done. */
301#define CFC_REG_AC_INIT_DONE 0x104078 301#define CFC_REG_AC_INIT_DONE 0x104078
@@ -330,6 +330,9 @@
330 field allows changing the priorities of the weighted-round-robin arbiter 330 field allows changing the priorities of the weighted-round-robin arbiter
331 which selects which CFC load client should be served next */ 331 which selects which CFC load client should be served next */
332#define CFC_REG_LCREQ_WEIGHTS 0x104084 332#define CFC_REG_LCREQ_WEIGHTS 0x104084
333/* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */
334#define CFC_REG_LINK_LIST 0x104c00
335#define CFC_REG_LINK_LIST_SIZE 256
333/* [R 1] indication the initializing the link list by the hardware was done. */ 336/* [R 1] indication the initializing the link list by the hardware was done. */
334#define CFC_REG_LL_INIT_DONE 0x104074 337#define CFC_REG_LL_INIT_DONE 0x104074
335/* [R 9] Number of allocated LCIDs which are at empty state */ 338/* [R 9] Number of allocated LCIDs which are at empty state */
@@ -342,6 +345,45 @@
342#define CFC_REG_NUM_LCIDS_LEAVING 0x104018 345#define CFC_REG_NUM_LCIDS_LEAVING 0x104018
343/* [RW 8] The event id for aggregated interrupt 0 */ 346/* [RW 8] The event id for aggregated interrupt 0 */
344#define CSDM_REG_AGG_INT_EVENT_0 0xc2038 347#define CSDM_REG_AGG_INT_EVENT_0 0xc2038
348#define CSDM_REG_AGG_INT_EVENT_1 0xc203c
349#define CSDM_REG_AGG_INT_EVENT_10 0xc2060
350#define CSDM_REG_AGG_INT_EVENT_11 0xc2064
351#define CSDM_REG_AGG_INT_EVENT_12 0xc2068
352#define CSDM_REG_AGG_INT_EVENT_13 0xc206c
353#define CSDM_REG_AGG_INT_EVENT_14 0xc2070
354#define CSDM_REG_AGG_INT_EVENT_15 0xc2074
355#define CSDM_REG_AGG_INT_EVENT_16 0xc2078
356#define CSDM_REG_AGG_INT_EVENT_17 0xc207c
357#define CSDM_REG_AGG_INT_EVENT_18 0xc2080
358#define CSDM_REG_AGG_INT_EVENT_19 0xc2084
359#define CSDM_REG_AGG_INT_EVENT_2 0xc2040
360#define CSDM_REG_AGG_INT_EVENT_20 0xc2088
361#define CSDM_REG_AGG_INT_EVENT_21 0xc208c
362#define CSDM_REG_AGG_INT_EVENT_22 0xc2090
363#define CSDM_REG_AGG_INT_EVENT_23 0xc2094
364#define CSDM_REG_AGG_INT_EVENT_24 0xc2098
365#define CSDM_REG_AGG_INT_EVENT_25 0xc209c
366#define CSDM_REG_AGG_INT_EVENT_26 0xc20a0
367#define CSDM_REG_AGG_INT_EVENT_27 0xc20a4
368#define CSDM_REG_AGG_INT_EVENT_28 0xc20a8
369#define CSDM_REG_AGG_INT_EVENT_29 0xc20ac
370#define CSDM_REG_AGG_INT_EVENT_3 0xc2044
371#define CSDM_REG_AGG_INT_EVENT_30 0xc20b0
372#define CSDM_REG_AGG_INT_EVENT_31 0xc20b4
373#define CSDM_REG_AGG_INT_EVENT_4 0xc2048
374/* [RW 1] The T bit for aggregated interrupt 0 */
375#define CSDM_REG_AGG_INT_T_0 0xc20b8
376#define CSDM_REG_AGG_INT_T_1 0xc20bc
377#define CSDM_REG_AGG_INT_T_10 0xc20e0
378#define CSDM_REG_AGG_INT_T_11 0xc20e4
379#define CSDM_REG_AGG_INT_T_12 0xc20e8
380#define CSDM_REG_AGG_INT_T_13 0xc20ec
381#define CSDM_REG_AGG_INT_T_14 0xc20f0
382#define CSDM_REG_AGG_INT_T_15 0xc20f4
383#define CSDM_REG_AGG_INT_T_16 0xc20f8
384#define CSDM_REG_AGG_INT_T_17 0xc20fc
385#define CSDM_REG_AGG_INT_T_18 0xc2100
386#define CSDM_REG_AGG_INT_T_19 0xc2104
345/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 387/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
346#define CSDM_REG_CFC_RSP_START_ADDR 0xc2008 388#define CSDM_REG_CFC_RSP_START_ADDR 0xc2008
347/* [RW 16] The maximum value of the competion counter #0 */ 389/* [RW 16] The maximum value of the competion counter #0 */
@@ -358,6 +400,9 @@
358/* [RW 32] Interrupt mask register #0 read/write */ 400/* [RW 32] Interrupt mask register #0 read/write */
359#define CSDM_REG_CSDM_INT_MASK_0 0xc229c 401#define CSDM_REG_CSDM_INT_MASK_0 0xc229c
360#define CSDM_REG_CSDM_INT_MASK_1 0xc22ac 402#define CSDM_REG_CSDM_INT_MASK_1 0xc22ac
403/* [R 32] Interrupt register #0 read */
404#define CSDM_REG_CSDM_INT_STS_0 0xc2290
405#define CSDM_REG_CSDM_INT_STS_1 0xc22a0
361/* [RW 11] Parity mask register #0 read/write */ 406/* [RW 11] Parity mask register #0 read/write */
362#define CSDM_REG_CSDM_PRTY_MASK 0xc22bc 407#define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
363/* [R 11] Parity register #0 read */ 408/* [R 11] Parity register #0 read */
@@ -443,6 +488,9 @@
443/* [RW 32] Interrupt mask register #0 read/write */ 488/* [RW 32] Interrupt mask register #0 read/write */
444#define CSEM_REG_CSEM_INT_MASK_0 0x200110 489#define CSEM_REG_CSEM_INT_MASK_0 0x200110
445#define CSEM_REG_CSEM_INT_MASK_1 0x200120 490#define CSEM_REG_CSEM_INT_MASK_1 0x200120
491/* [R 32] Interrupt register #0 read */
492#define CSEM_REG_CSEM_INT_STS_0 0x200104
493#define CSEM_REG_CSEM_INT_STS_1 0x200114
446/* [RW 32] Parity mask register #0 read/write */ 494/* [RW 32] Parity mask register #0 read/write */
447#define CSEM_REG_CSEM_PRTY_MASK_0 0x200130 495#define CSEM_REG_CSEM_PRTY_MASK_0 0x200130
448#define CSEM_REG_CSEM_PRTY_MASK_1 0x200140 496#define CSEM_REG_CSEM_PRTY_MASK_1 0x200140
@@ -453,9 +501,8 @@
453#define CSEM_REG_ENABLE_OUT 0x2000a8 501#define CSEM_REG_ENABLE_OUT 0x2000a8
454/* [RW 32] This address space contains all registers and memories that are 502/* [RW 32] This address space contains all registers and memories that are
455 placed in SEM_FAST block. The SEM_FAST registers are described in 503 placed in SEM_FAST block. The SEM_FAST registers are described in
456 appendix B. In order to access the SEM_FAST registers the base address 504 appendix B. In order to access the sem_fast registers the base address
457 CSEM_REGISTERS_FAST_MEMORY (Offset: 0x220000) should be added to each 505 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
458 SEM_FAST register offset. */
459#define CSEM_REG_FAST_MEMORY 0x220000 506#define CSEM_REG_FAST_MEMORY 0x220000
460/* [RW 1] Disables input messages from FIC0 May be updated during run_time 507/* [RW 1] Disables input messages from FIC0 May be updated during run_time
461 by the microcode */ 508 by the microcode */
@@ -466,6 +513,7 @@
466/* [RW 15] Interrupt table Read and write access to it is not possible in 513/* [RW 15] Interrupt table Read and write access to it is not possible in
467 the middle of the work */ 514 the middle of the work */
468#define CSEM_REG_INT_TABLE 0x200400 515#define CSEM_REG_INT_TABLE 0x200400
516#define CSEM_REG_INT_TABLE_SIZE 256
469/* [ST 24] Statistics register. The number of messages that entered through 517/* [ST 24] Statistics register. The number of messages that entered through
470 FIC0 */ 518 FIC0 */
471#define CSEM_REG_MSG_NUM_FIC0 0x200000 519#define CSEM_REG_MSG_NUM_FIC0 0x200000
@@ -630,6 +678,8 @@
630#define DORQ_REG_AGG_CMD3 0x17006c 678#define DORQ_REG_AGG_CMD3 0x17006c
631/* [RW 28] UCM Header. */ 679/* [RW 28] UCM Header. */
632#define DORQ_REG_CMHEAD_RX 0x170050 680#define DORQ_REG_CMHEAD_RX 0x170050
681/* [RW 32] Doorbell address for RBC doorbells (function 0). */
682#define DORQ_REG_DB_ADDR0 0x17008c
633/* [RW 5] Interrupt mask register #0 read/write */ 683/* [RW 5] Interrupt mask register #0 read/write */
634#define DORQ_REG_DORQ_INT_MASK 0x170180 684#define DORQ_REG_DORQ_INT_MASK 0x170180
635/* [R 5] Interrupt register #0 read */ 685/* [R 5] Interrupt register #0 read */
@@ -690,75 +740,33 @@
690#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1) 740#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
691#define HC_REG_AGG_INT_0 0x108050 741#define HC_REG_AGG_INT_0 0x108050
692#define HC_REG_AGG_INT_1 0x108054 742#define HC_REG_AGG_INT_1 0x108054
693/* [RW 16] attention bit and attention acknowledge bits status for port 0
694 and 1 according to the following address map: addr 0 - attn_bit_0; addr 1
695 - attn_ack_bit_0; addr 2 - attn_bit_1; addr 3 - attn_ack_bit_1; */
696#define HC_REG_ATTN_BIT 0x108120 743#define HC_REG_ATTN_BIT 0x108120
697/* [RW 16] attn bits status index for attn bit msg; addr 0 - function 0;
698 addr 1 - functin 1 */
699#define HC_REG_ATTN_IDX 0x108100 744#define HC_REG_ATTN_IDX 0x108100
700/* [RW 32] port 0 lower 32 bits address field for attn messag. */
701#define HC_REG_ATTN_MSG0_ADDR_L 0x108018 745#define HC_REG_ATTN_MSG0_ADDR_L 0x108018
702/* [RW 32] port 1 lower 32 bits address field for attn messag. */
703#define HC_REG_ATTN_MSG1_ADDR_L 0x108020 746#define HC_REG_ATTN_MSG1_ADDR_L 0x108020
704/* [RW 8] status block number for attn bit msg - function 0; */
705#define HC_REG_ATTN_NUM_P0 0x108038 747#define HC_REG_ATTN_NUM_P0 0x108038
706/* [RW 8] status block number for attn bit msg - function 1 */
707#define HC_REG_ATTN_NUM_P1 0x10803c 748#define HC_REG_ATTN_NUM_P1 0x10803c
708#define HC_REG_CONFIG_0 0x108000 749#define HC_REG_CONFIG_0 0x108000
709#define HC_REG_CONFIG_1 0x108004 750#define HC_REG_CONFIG_1 0x108004
751#define HC_REG_FUNC_NUM_P0 0x1080ac
752#define HC_REG_FUNC_NUM_P1 0x1080b0
710/* [RW 3] Parity mask register #0 read/write */ 753/* [RW 3] Parity mask register #0 read/write */
711#define HC_REG_HC_PRTY_MASK 0x1080a0 754#define HC_REG_HC_PRTY_MASK 0x1080a0
712/* [R 3] Parity register #0 read */ 755/* [R 3] Parity register #0 read */
713#define HC_REG_HC_PRTY_STS 0x108094 756#define HC_REG_HC_PRTY_STS 0x108094
714/* [RW 17] status block interrupt mask; one in each bit means unmask; zerow
715 in each bit means mask; bit 0 - default SB; bit 1 - SB_0; bit 2 - SB_1...
716 bit 16- SB_15; addr 0 - port 0; addr 1 - port 1 */
717#define HC_REG_INT_MASK 0x108108 757#define HC_REG_INT_MASK 0x108108
718/* [RW 16] port 0 attn bit condition monitoring; each bit that is set will
719 lock a change fron 0 to 1 in the corresponding attention signals that
720 comes from the AEU */
721#define HC_REG_LEADING_EDGE_0 0x108040 758#define HC_REG_LEADING_EDGE_0 0x108040
722#define HC_REG_LEADING_EDGE_1 0x108048 759#define HC_REG_LEADING_EDGE_1 0x108048
723/* [RW 16] all producer and consumer of port 0 according to the following
724 addresses; U_prod: 0-15; C_prod: 16-31; U_cons: 32-47; C_cons:48-63;
725 Defoult_prod: U/C/X/T/Attn-64/65/66/67/68; Defoult_cons:
726 U/C/X/T/Attn-69/70/71/72/73 */
727#define HC_REG_P0_PROD_CONS 0x108200 760#define HC_REG_P0_PROD_CONS 0x108200
728/* [RW 16] all producer and consumer of port 1according to the following
729 addresses; U_prod: 0-15; C_prod: 16-31; U_cons: 32-47; C_cons:48-63;
730 Defoult_prod: U/C/X/T/Attn-64/65/66/67/68; Defoult_cons:
731 U/C/X/T/Attn-69/70/71/72/73 */
732#define HC_REG_P1_PROD_CONS 0x108400 761#define HC_REG_P1_PROD_CONS 0x108400
733/* [W 1] This register is write only and has 4 addresses as follow: 0 =
734 clear all PBA bits port 0; 1 = clear all pending interrupts request
735 port0; 2 = clear all PBA bits port 1; 3 = clear all pending interrupts
736 request port1; here is no meaning for the data in this register */
737#define HC_REG_PBA_COMMAND 0x108140 762#define HC_REG_PBA_COMMAND 0x108140
738#define HC_REG_PCI_CONFIG_0 0x108010 763#define HC_REG_PCI_CONFIG_0 0x108010
739#define HC_REG_PCI_CONFIG_1 0x108014 764#define HC_REG_PCI_CONFIG_1 0x108014
740/* [RW 24] all counters acording to the following address: LSB: 0=read; 1=
741 read_clear; 0-71 = HW counters (the inside order is the same as the
742 interrupt table in the spec); 72-219 = SW counters 1 (stops after first
743 consumer upd) the inside order is: 72-103 - U_non_default_p0; 104-135
744 C_non_defaul_p0; 36-145 U/C/X/T/Attn_default_p0; 146-177
745 U_non_default_p1; 178-209 C_non_defaul_p1; 10-219 U/C/X/T/Attn_default_p1
746 ; 220-367 = SW counters 2 (stops when prod=cons) the inside order is:
747 220-251 - U_non_default_p0; 252-283 C_non_defaul_p0; 84-293
748 U/C/X/T/Attn_default_p0; 294-325 U_non_default_p1; 326-357
749 C_non_defaul_p1; 58-367 U/C/X/T/Attn_default_p1 ; 368-515 = mailbox
750 counters; (the inside order of the mailbox counter is 368-431 U and C
751 non_default_p0; 432-441 U/C/X/T/Attn_default_p0; 442-505 U and C
752 non_default_p1; 506-515 U/C/X/T/Attn_default_p1) */
753#define HC_REG_STATISTIC_COUNTERS 0x109000 765#define HC_REG_STATISTIC_COUNTERS 0x109000
754/* [RW 16] port 0 attn bit condition monitoring; each bit that is set will
755 lock a change fron 1 to 0 in the corresponding attention signals that
756 comes from the AEU */
757#define HC_REG_TRAILING_EDGE_0 0x108044 766#define HC_REG_TRAILING_EDGE_0 0x108044
758#define HC_REG_TRAILING_EDGE_1 0x10804c 767#define HC_REG_TRAILING_EDGE_1 0x10804c
759#define HC_REG_UC_RAM_ADDR_0 0x108028 768#define HC_REG_UC_RAM_ADDR_0 0x108028
760#define HC_REG_UC_RAM_ADDR_1 0x108030 769#define HC_REG_UC_RAM_ADDR_1 0x108030
761/* [RW 16] ustorm address for coalesc now message */
762#define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068 770#define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068
763#define HC_REG_VQID_0 0x108008 771#define HC_REG_VQID_0 0x108008
764#define HC_REG_VQID_1 0x10800c 772#define HC_REG_VQID_1 0x10800c
@@ -883,14 +891,16 @@
883 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched 891 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
884 ump_tx_parity; [31] MCP Latched scpad_parity; */ 892 ump_tx_parity; [31] MCP Latched scpad_parity; */
885#define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458 893#define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458
886/* [W 11] write to this register results with the clear of the latched 894/* [W 14] write to this register results with the clear of the latched
887 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in 895 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
888 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP 896 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
889 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears 897 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
890 GRC Latched reserved access attention; one in d7 clears Latched 898 GRC Latched reserved access attention; one in d7 clears Latched
891 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears 899 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
892 Latched ump_tx_parity; one in d10 clears Latched scpad_parity; read from 900 Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both
893 this register return zero */ 901 ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears
902 pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read
903 from this register return zero */
894#define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c 904#define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c
895/* [RW 32] first 32b for enabling the output for function 0 output0. mapped 905/* [RW 32] first 32b for enabling the output for function 0 output0. mapped
896 as follows: [0] NIG attention for function0; [1] NIG attention for 906 as follows: [0] NIG attention for function0; [1] NIG attention for
@@ -907,7 +917,11 @@
907 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 917 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
908#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c 918#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c
909#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c 919#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c
920#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c
910#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c 921#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c
922#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc
923#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc
924#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc
911/* [RW 32] first 32b for enabling the output for function 1 output0. mapped 925/* [RW 32] first 32b for enabling the output for function 1 output0. mapped
912 as follows: [0] NIG attention for function0; [1] NIG attention for 926 as follows: [0] NIG attention for function0; [1] NIG attention for
913 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function 927 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
@@ -923,9 +937,13 @@
923 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 937 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
924#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c 938#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c
925#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c 939#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c
940#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c
926#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c 941#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c
927/* [RW 32] first 32b for enabling the output for close the gate nig 0. 942#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c
928 mapped as follows: [0] NIG attention for function0; [1] NIG attention for 943#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c
944#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c
945/* [RW 32] first 32b for enabling the output for close the gate nig. mapped
946 as follows: [0] NIG attention for function0; [1] NIG attention for
929 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 947 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
930 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 948 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
931 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 949 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
@@ -939,8 +957,8 @@
939 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 957 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
940#define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec 958#define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec
941#define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c 959#define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c
942/* [RW 32] first 32b for enabling the output for close the gate pxp 0. 960/* [RW 32] first 32b for enabling the output for close the gate pxp. mapped
943 mapped as follows: [0] NIG attention for function0; [1] NIG attention for 961 as follows: [0] NIG attention for function0; [1] NIG attention for
944 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 962 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
945 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 963 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
946 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 964 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
@@ -984,34 +1002,34 @@
984 interrupt; */ 1002 interrupt; */
985#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110 1003#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110
986#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120 1004#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120
987/* [RW 32] second 32b for enabling the output for close the gate nig 0. 1005/* [RW 32] second 32b for enabling the output for close the gate nig. mapped
988 mapped as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; 1006 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
989 [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] 1007 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
990 Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] 1008 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
991 XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] 1009 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
992 XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw 1010 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
993 interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI 1011 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
994 core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity 1012 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
995 error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw 1013 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
996 interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI 1014 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
997 Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw 1015 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
998 interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM 1016 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
999 Parity error; [31] CCM Hw interrupt; */ 1017 interrupt; */
1000#define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0 1018#define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0
1001#define MISC_REG_AEU_ENABLE2_NIG_1 0xa190 1019#define MISC_REG_AEU_ENABLE2_NIG_1 0xa190
1002/* [RW 32] second 32b for enabling the output for close the gate pxp 0. 1020/* [RW 32] second 32b for enabling the output for close the gate pxp. mapped
1003 mapped as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; 1021 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1004 [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] 1022 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1005 Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] 1023 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1006 XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] 1024 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1007 XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw 1025 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1008 interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI 1026 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1009 core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity 1027 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1010 error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw 1028 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1011 interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI 1029 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1012 Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw 1030 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1013 interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM 1031 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1014 Parity error; [31] CCM Hw interrupt; */ 1032 interrupt; */
1015#define MISC_REG_AEU_ENABLE2_PXP_0 0xa100 1033#define MISC_REG_AEU_ENABLE2_PXP_0 0xa100
1016#define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0 1034#define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0
1017/* [RW 32] third 32b for enabling the output for function 0 output0. mapped 1035/* [RW 32] third 32b for enabling the output for function 0 output0. mapped
@@ -1044,34 +1062,34 @@
1044 attn1; */ 1062 attn1; */
1045#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114 1063#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114
1046#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124 1064#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124
1047/* [RW 32] third 32b for enabling the output for close the gate nig 0. 1065/* [RW 32] third 32b for enabling the output for close the gate nig. mapped
1048 mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] 1066 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1049 PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity 1067 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1050 error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC 1068 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1051 Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE 1069 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1052 Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] 1070 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1053 IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; 1071 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1054 [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; 1072 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1055 [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; 1073 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1056 [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; 1074 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1057 [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers 1075 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1058 attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] 1076 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1059 General attn1; */ 1077 attn1; */
1060#define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4 1078#define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4
1061#define MISC_REG_AEU_ENABLE3_NIG_1 0xa194 1079#define MISC_REG_AEU_ENABLE3_NIG_1 0xa194
1062/* [RW 32] third 32b for enabling the output for close the gate pxp 0. 1080/* [RW 32] third 32b for enabling the output for close the gate pxp. mapped
1063 mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] 1081 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1064 PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity 1082 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1065 error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC 1083 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1066 Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE 1084 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1067 Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] 1085 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1068 IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; 1086 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1069 [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; 1087 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1070 [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; 1088 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1071 [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; 1089 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1072 [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers 1090 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1073 attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] 1091 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1074 General attn1; */ 1092 attn1; */
1075#define MISC_REG_AEU_ENABLE3_PXP_0 0xa104 1093#define MISC_REG_AEU_ENABLE3_PXP_0 0xa104
1076#define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4 1094#define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4
1077/* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped 1095/* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
@@ -1088,6 +1106,10 @@
1088 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1106 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1089#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078 1107#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078
1090#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098 1108#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098
1109#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8
1110#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8
1111#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8
1112#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8
1091/* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped 1113/* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
1092 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1114 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1093 General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1115 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
@@ -1102,34 +1124,36 @@
1102 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1124 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1103#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118 1125#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118
1104#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138 1126#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138
1105/* [RW 32] fourth 32b for enabling the output for close the gate nig 1127#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158
1106 0.mapped as follows: [0] General attn2; [1] General attn3; [2] General 1128#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168
1107 attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] 1129#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178
1108 General attn8; [7] General attn9; [8] General attn10; [9] General attn11; 1130#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188
1109 [10] General attn12; [11] General attn13; [12] General attn14; [13] 1131/* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped
1110 General attn15; [14] General attn16; [15] General attn17; [16] General 1132 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1111 attn18; [17] General attn19; [18] General attn20; [19] General attn21; 1133 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1112 [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched 1134 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1113 attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched 1135 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1114 attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved 1136 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1115 access attention; [28] MCP Latched rom_parity; [29] MCP Latched 1137 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1116 ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched 1138 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1117 scpad_parity; */ 1139 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1140 Latched timeout attention; [27] GRC Latched reserved access attention;
1141 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1142 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1118#define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8 1143#define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8
1119#define MISC_REG_AEU_ENABLE4_NIG_1 0xa198 1144#define MISC_REG_AEU_ENABLE4_NIG_1 0xa198
1120/* [RW 32] fourth 32b for enabling the output for close the gate pxp 1145/* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped
1121 0.mapped as follows: [0] General attn2; [1] General attn3; [2] General 1146 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1122 attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6] 1147 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1123 General attn8; [7] General attn9; [8] General attn10; [9] General attn11; 1148 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1124 [10] General attn12; [11] General attn13; [12] General attn14; [13] 1149 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1125 General attn15; [14] General attn16; [15] General attn17; [16] General 1150 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1126 attn18; [17] General attn19; [18] General attn20; [19] General attn21; 1151 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1127 [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched 1152 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1128 attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched 1153 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1129 attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved 1154 Latched timeout attention; [27] GRC Latched reserved access attention;
1130 access attention; [28] MCP Latched rom_parity; [29] MCP Latched 1155 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1131 ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched 1156 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1132 scpad_parity; */
1133#define MISC_REG_AEU_ENABLE4_PXP_0 0xa108 1157#define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
1134#define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8 1158#define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
1135/* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu 1159/* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
@@ -1148,6 +1172,7 @@
1148#define MISC_REG_AEU_GENERAL_ATTN_19 0xa04c 1172#define MISC_REG_AEU_GENERAL_ATTN_19 0xa04c
1149#define MISC_REG_AEU_GENERAL_ATTN_10 0xa028 1173#define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1150#define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c 1174#define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1175#define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
1151#define MISC_REG_AEU_GENERAL_ATTN_2 0xa008 1176#define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
1152#define MISC_REG_AEU_GENERAL_ATTN_20 0xa050 1177#define MISC_REG_AEU_GENERAL_ATTN_20 0xa050
1153#define MISC_REG_AEU_GENERAL_ATTN_21 0xa054 1178#define MISC_REG_AEU_GENERAL_ATTN_21 0xa054
@@ -1158,6 +1183,7 @@
1158#define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c 1183#define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c
1159#define MISC_REG_AEU_GENERAL_ATTN_8 0xa020 1184#define MISC_REG_AEU_GENERAL_ATTN_8 0xa020
1160#define MISC_REG_AEU_GENERAL_ATTN_9 0xa024 1185#define MISC_REG_AEU_GENERAL_ATTN_9 0xa024
1186#define MISC_REG_AEU_GENERAL_MASK 0xa61c
1161/* [RW 32] first 32b for inverting the input for function 0; for each bit: 1187/* [RW 32] first 32b for inverting the input for function 0; for each bit:
1162 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for 1188 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
1163 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; 1189 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
@@ -1189,10 +1215,29 @@
1189#define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230 1215#define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230
1190#define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240 1216#define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240
1191/* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0; 1217/* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
1192 [9:8] = mask close the gates signals of function 0 toward PXP [8] and NIG 1218 [9:8] = raserved. Zero = mask; one = unmask */
1193 [9]. Zero = mask; one = unmask */
1194#define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060 1219#define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060
1195#define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064 1220#define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064
1221/* [RW 1] If set a system kill occurred */
1222#define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610
1223/* [RW 32] Represent the status of the input vector to the AEU when a system
1224 kill occurred. The register is reset in por reset. Mapped as follows: [0]
1225 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1226 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1227 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1228 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1229 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1230 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1231 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1232 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1233 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1234 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1235 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1236 interrupt; */
1237#define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600
1238#define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604
1239#define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608
1240#define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c
1196/* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1 1241/* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
1197 Port. */ 1242 Port. */
1198#define MISC_REG_BOND_ID 0xa400 1243#define MISC_REG_BOND_ID 0xa400
@@ -1206,8 +1251,80 @@
1206 starts at 0x0 for the A0 tape-out and increments by one for each 1251 starts at 0x0 for the A0 tape-out and increments by one for each
1207 all-layer tape-out. */ 1252 all-layer tape-out. */
1208#define MISC_REG_CHIP_REV 0xa40c 1253#define MISC_REG_CHIP_REV 0xa40c
1209/* [RW 32] The following driver registers(1..6) represent 6 drivers and 32 1254/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1210 clients. Each client can be controlled by one driver only. One in each 1255 32 clients. Each client can be controlled by one driver only. One in each
1256 bit represent that this driver control the appropriate client (Ex: bit 5
1257 is set means this driver control client number 5). addr1 = set; addr0 =
1258 clear; read from both addresses will give the same result = status. write
1259 to address 1 will set a request to control all the clients that their
1260 appropriate bit (in the write command) is set. if the client is free (the
1261 appropriate bit in all the other drivers is clear) one will be written to
1262 that driver register; if the client isn't free the bit will remain zero.
1263 if the appropriate bit is set (the driver request to gain control on a
1264 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1265 interrupt will be asserted). write to address 0 will set a request to
1266 free all the clients that their appropriate bit (in the write command) is
1267 set. if the appropriate bit is clear (the driver request to free a client
1268 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1269 be asserted). */
1270#define MISC_REG_DRIVER_CONTROL_10 0xa3e0
1271#define MISC_REG_DRIVER_CONTROL_10_SIZE 2
1272/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1273 32 clients. Each client can be controlled by one driver only. One in each
1274 bit represent that this driver control the appropriate client (Ex: bit 5
1275 is set means this driver control client number 5). addr1 = set; addr0 =
1276 clear; read from both addresses will give the same result = status. write
1277 to address 1 will set a request to control all the clients that their
1278 appropriate bit (in the write command) is set. if the client is free (the
1279 appropriate bit in all the other drivers is clear) one will be written to
1280 that driver register; if the client isn't free the bit will remain zero.
1281 if the appropriate bit is set (the driver request to gain control on a
1282 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1283 interrupt will be asserted). write to address 0 will set a request to
1284 free all the clients that their appropriate bit (in the write command) is
1285 set. if the appropriate bit is clear (the driver request to free a client
1286 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1287 be asserted). */
1288#define MISC_REG_DRIVER_CONTROL_11 0xa3e8
1289#define MISC_REG_DRIVER_CONTROL_11_SIZE 2
1290/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1291 32 clients. Each client can be controlled by one driver only. One in each
1292 bit represent that this driver control the appropriate client (Ex: bit 5
1293 is set means this driver control client number 5). addr1 = set; addr0 =
1294 clear; read from both addresses will give the same result = status. write
1295 to address 1 will set a request to control all the clients that their
1296 appropriate bit (in the write command) is set. if the client is free (the
1297 appropriate bit in all the other drivers is clear) one will be written to
1298 that driver register; if the client isn't free the bit will remain zero.
1299 if the appropriate bit is set (the driver request to gain control on a
1300 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1301 interrupt will be asserted). write to address 0 will set a request to
1302 free all the clients that their appropriate bit (in the write command) is
1303 set. if the appropriate bit is clear (the driver request to free a client
1304 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1305 be asserted). */
1306#define MISC_REG_DRIVER_CONTROL_12 0xa3f0
1307#define MISC_REG_DRIVER_CONTROL_12_SIZE 2
1308/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1309 32 clients. Each client can be controlled by one driver only. One in each
1310 bit represent that this driver control the appropriate client (Ex: bit 5
1311 is set means this driver control client number 5). addr1 = set; addr0 =
1312 clear; read from both addresses will give the same result = status. write
1313 to address 1 will set a request to control all the clients that their
1314 appropriate bit (in the write command) is set. if the client is free (the
1315 appropriate bit in all the other drivers is clear) one will be written to
1316 that driver register; if the client isn't free the bit will remain zero.
1317 if the appropriate bit is set (the driver request to gain control on a
1318 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1319 interrupt will be asserted). write to address 0 will set a request to
1320 free all the clients that their appropriate bit (in the write command) is
1321 set. if the appropriate bit is clear (the driver request to free a client
1322 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1323 be asserted). */
1324#define MISC_REG_DRIVER_CONTROL_13 0xa3f8
1325#define MISC_REG_DRIVER_CONTROL_13_SIZE 2
1326/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1327 32 clients. Each client can be controlled by one driver only. One in each
1211 bit represent that this driver control the appropriate client (Ex: bit 5 1328 bit represent that this driver control the appropriate client (Ex: bit 5
1212 is set means this driver control client number 5). addr1 = set; addr0 = 1329 is set means this driver control client number 5). addr1 = set; addr0 =
1213 clear; read from both addresses will give the same result = status. write 1330 clear; read from both addresses will give the same result = status. write
@@ -1223,6 +1340,47 @@
1223 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will 1340 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1224 be asserted). */ 1341 be asserted). */
1225#define MISC_REG_DRIVER_CONTROL_1 0xa510 1342#define MISC_REG_DRIVER_CONTROL_1 0xa510
1343#define MISC_REG_DRIVER_CONTROL_14 0xa5e0
1344#define MISC_REG_DRIVER_CONTROL_14_SIZE 2
1345/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1346 32 clients. Each client can be controlled by one driver only. One in each
1347 bit represent that this driver control the appropriate client (Ex: bit 5
1348 is set means this driver control client number 5). addr1 = set; addr0 =
1349 clear; read from both addresses will give the same result = status. write
1350 to address 1 will set a request to control all the clients that their
1351 appropriate bit (in the write command) is set. if the client is free (the
1352 appropriate bit in all the other drivers is clear) one will be written to
1353 that driver register; if the client isn't free the bit will remain zero.
1354 if the appropriate bit is set (the driver request to gain control on a
1355 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1356 interrupt will be asserted). write to address 0 will set a request to
1357 free all the clients that their appropriate bit (in the write command) is
1358 set. if the appropriate bit is clear (the driver request to free a client
1359 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1360 be asserted). */
1361#define MISC_REG_DRIVER_CONTROL_15 0xa5e8
1362#define MISC_REG_DRIVER_CONTROL_15_SIZE 2
1363/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1364 32 clients. Each client can be controlled by one driver only. One in each
1365 bit represent that this driver control the appropriate client (Ex: bit 5
1366 is set means this driver control client number 5). addr1 = set; addr0 =
1367 clear; read from both addresses will give the same result = status. write
1368 to address 1 will set a request to control all the clients that their
1369 appropriate bit (in the write command) is set. if the client is free (the
1370 appropriate bit in all the other drivers is clear) one will be written to
1371 that driver register; if the client isn't free the bit will remain zero.
1372 if the appropriate bit is set (the driver request to gain control on a
1373 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1374 interrupt will be asserted). write to address 0 will set a request to
1375 free all the clients that their appropriate bit (in the write command) is
1376 set. if the appropriate bit is clear (the driver request to free a client
1377 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1378 be asserted). */
1379#define MISC_REG_DRIVER_CONTROL_16 0xa5f0
1380#define MISC_REG_DRIVER_CONTROL_16_SIZE 2
1381/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
1382 only. */
1383#define MISC_REG_E1HMF_MODE 0xa5f8
1226/* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of 1384/* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
1227 these bits is written as a '1'; the corresponding SPIO bit will turn off 1385 these bits is written as a '1'; the corresponding SPIO bit will turn off
1228 it's drivers and become an input. This is the reset state of all GPIO 1386 it's drivers and become an input. This is the reset state of all GPIO
@@ -1240,6 +1398,18 @@
1240 This is the result value of the pin; not the drive value. Writing these 1398 This is the result value of the pin; not the drive value. Writing these
1241 bits will have not effect. */ 1399 bits will have not effect. */
1242#define MISC_REG_GPIO 0xa490 1400#define MISC_REG_GPIO 0xa490
1401/* [R 28] this field hold the last information that caused reserved
1402 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1403 [27:24] the master thatcaused the attention - according to the following
1404 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1405 dbu; 8 = dmae */
1406#define MISC_REG_GRC_RSV_ATTN 0xa3c0
1407/* [R 28] this field hold the last information that caused timeout
1408 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1409 [27:24] the master thatcaused the attention - according to the following
1410 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1411 dbu; 8 = dmae */
1412#define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4
1243/* [RW 1] Setting this bit enables a timer in the GRC block to timeout any 1413/* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
1244 access that does not finish within 1414 access that does not finish within
1245 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is 1415 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
@@ -1282,6 +1452,11 @@
1282#define MISC_REG_MISC_PRTY_MASK 0xa398 1452#define MISC_REG_MISC_PRTY_MASK 0xa398
1283/* [R 1] Parity register #0 read */ 1453/* [R 1] Parity register #0 read */
1284#define MISC_REG_MISC_PRTY_STS 0xa38c 1454#define MISC_REG_MISC_PRTY_STS 0xa38c
1455#define MISC_REG_NIG_WOL_P0 0xa270
1456#define MISC_REG_NIG_WOL_P1 0xa274
1457/* [R 1] If set indicate that the pcie_rst_b was asserted without perst
1458 assertion */
1459#define MISC_REG_PCIE_HOT_RESET 0xa618
1285/* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911. 1460/* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
1286 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1 1461 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
1287 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1 1462 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
@@ -1303,7 +1478,7 @@
1303#define MISC_REG_PLL_STORM_CTRL_2 0xa298 1478#define MISC_REG_PLL_STORM_CTRL_2 0xa298
1304#define MISC_REG_PLL_STORM_CTRL_3 0xa29c 1479#define MISC_REG_PLL_STORM_CTRL_3 0xa29c
1305#define MISC_REG_PLL_STORM_CTRL_4 0xa2a0 1480#define MISC_REG_PLL_STORM_CTRL_4 0xa2a0
1306/* [RW 32] reset reg#1; rite/read one = the specific block is out of reset; 1481/* [RW 32] reset reg#2; rite/read one = the specific block is out of reset;
1307 write/read zero = the specific block is in reset; addr 0-wr- the write 1482 write/read zero = the specific block is in reset; addr 0-wr- the write
1308 value will be written to the register; addr 1-set - one will be written 1483 value will be written to the register; addr 1-set - one will be written
1309 to all the bits that have the value of one in the data written (bits that 1484 to all the bits that have the value of one in the data written (bits that
@@ -1311,14 +1486,12 @@
1311 written to all the bits that have the value of one in the data written 1486 written to all the bits that have the value of one in the data written
1312 (bits that have the value of zero will not be change); addr 3-ignore; 1487 (bits that have the value of zero will not be change); addr 3-ignore;
1313 read ignore from all addr except addr 00; inside order of the bits is: 1488 read ignore from all addr except addr 00; inside order of the bits is:
1314 [0] rst_brb1; [1] rst_prs; [2] rst_src; [3] rst_tsdm; [4] rst_tsem; [5] 1489 [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc;
1315 rst_tcm; [6] rst_rbcr; [7] rst_nig; [8] rst_usdm; [9] rst_ucm; [10] 1490 [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7]
1316 rst_usem; [11] rst_upb; [12] rst_ccm; [13] rst_csem; [14] rst_csdm; [15] 1491 rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn;
1317 rst_rbcu; [16] rst_pbf; [17] rst_qm; [18] rst_tm; [19] rst_dorq; [20] 1492 [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13]
1318 rst_xcm; [21] rst_xsdm; [22] rst_xsem; [23] rst_rbct; [24] rst_cdu; [25] 1493 Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16]
1319 rst_cfc; [26] rst_pxp; [27] rst_pxpv; [28] rst_rbcp; [29] rst_hc; [30] 1494 rst_pxp_rq_rd_wr; 31:17] reserved */
1320 rst_dmae; [31] rst_semi_rtc; */
1321#define MISC_REG_RESET_REG_1 0xa580
1322#define MISC_REG_RESET_REG_2 0xa590 1495#define MISC_REG_RESET_REG_2 0xa590
1323/* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is 1496/* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1324 shared with the driver resides */ 1497 shared with the driver resides */
@@ -1345,7 +1518,7 @@
1345 select VAUX supply. (This is an output pin only; it is not controlled by 1518 select VAUX supply. (This is an output pin only; it is not controlled by
1346 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT 1519 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
1347 field is not applicable for this pin; only the VALUE fields is relevant - 1520 field is not applicable for this pin; only the VALUE fields is relevant -
1348 it reflects the output value); [3] reserved; [4] spio_4; [5] spio_5; [6] 1521 it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]
1349 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP 1522 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
1350 device ID select; read by UMP firmware. */ 1523 device ID select; read by UMP firmware. */
1351#define MISC_REG_SPIO 0xa4fc 1524#define MISC_REG_SPIO 0xa4fc
@@ -1394,8 +1567,9 @@
1394#define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8 1567#define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
1395/* [RW 1] output enable for RX BRB1 LP IF */ 1568/* [RW 1] output enable for RX BRB1 LP IF */
1396#define NIG_REG_BRB_LB_OUT_EN 0x10100 1569#define NIG_REG_BRB_LB_OUT_EN 0x10100
1397/* [WB_W 72] Debug packet to LP from RBC; Data spelling:[63:0] data; 64] 1570/* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
1398 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush */ 1571 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush;
1572 72:73]-vnic_num; 81:74]-sideband_info */
1399#define NIG_REG_DEBUG_PACKET_LB 0x10800 1573#define NIG_REG_DEBUG_PACKET_LB 0x10800
1400/* [RW 1] Input enable for TX Debug packet */ 1574/* [RW 1] Input enable for TX Debug packet */
1401#define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc 1575#define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc
@@ -1409,6 +1583,8 @@
1409/* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs 1583/* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
1410 to emac for port0; other way to bmac for port0 */ 1584 to emac for port0; other way to bmac for port0 */
1411#define NIG_REG_EGRESS_EMAC0_PORT 0x10058 1585#define NIG_REG_EGRESS_EMAC0_PORT 0x10058
1586/* [RW 32] TX_MNG_FIFO in NIG_TX_PORT0; data[31:0] written in FIFO order. */
1587#define NIG_REG_EGRESS_MNG0_FIFO 0x1045c
1412/* [RW 1] Input enable for TX PBF user packet port0 IF */ 1588/* [RW 1] Input enable for TX PBF user packet port0 IF */
1413#define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc 1589#define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc
1414/* [RW 1] Input enable for TX PBF user packet port1 IF */ 1590/* [RW 1] Input enable for TX PBF user packet port1 IF */
@@ -1438,6 +1614,8 @@
1438#define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4 1614#define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
1439/* [RW 1] led 10g for port 0 */ 1615/* [RW 1] led 10g for port 0 */
1440#define NIG_REG_LED_10G_P0 0x10320 1616#define NIG_REG_LED_10G_P0 0x10320
1617/* [RW 1] led 10g for port 1 */
1618#define NIG_REG_LED_10G_P1 0x10324
1441/* [RW 1] Port0: This bit is set to enable the use of the 1619/* [RW 1] Port0: This bit is set to enable the use of the
1442 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field 1620 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
1443 defined below. If this bit is cleared; then the blink rate will be about 1621 defined below. If this bit is cleared; then the blink rate will be about
@@ -1470,19 +1648,47 @@
1470/* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3; 1648/* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
1471 9-11PHY7; 12 MAC4; 13-15 PHY10; */ 1649 9-11PHY7; 12 MAC4; 13-15 PHY10; */
1472#define NIG_REG_LED_MODE_P0 0x102f0 1650#define NIG_REG_LED_MODE_P0 0x102f0
1651#define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c
1652#define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154
1473#define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244 1653#define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
1654#define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048
1474/* [RW 1] send to BRB1 if no match on any of RMP rules. */ 1655/* [RW 1] send to BRB1 if no match on any of RMP rules. */
1475#define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c 1656#define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c
1657/* [RW 2] Determine the classification participants. 0: no classification.1:
1658 classification upon VLAN id. 2: classification upon MAC address. 3:
1659 classification upon both VLAN id & MAC addr. */
1660#define NIG_REG_LLH0_CLS_TYPE 0x16080
1476/* [RW 32] cm header for llh0 */ 1661/* [RW 32] cm header for llh0 */
1477#define NIG_REG_LLH0_CM_HEADER 0x1007c 1662#define NIG_REG_LLH0_CM_HEADER 0x1007c
1663#define NIG_REG_LLH0_DEST_IP_0_1 0x101dc
1664#define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0
1665/* [RW 16] destination TCP address 1. The LLH will look for this address in
1666 all incoming packets. */
1667#define NIG_REG_LLH0_DEST_TCP_0 0x10220
1668/* [RW 16] destination UDP address 1 The LLH will look for this address in
1669 all incoming packets. */
1670#define NIG_REG_LLH0_DEST_UDP_0 0x10214
1478#define NIG_REG_LLH0_ERROR_MASK 0x1008c 1671#define NIG_REG_LLH0_ERROR_MASK 0x1008c
1479/* [RW 8] event id for llh0 */ 1672/* [RW 8] event id for llh0 */
1480#define NIG_REG_LLH0_EVENT_ID 0x10084 1673#define NIG_REG_LLH0_EVENT_ID 0x10084
1674#define NIG_REG_LLH0_FUNC_EN 0x160fc
1675#define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100
1676/* [RW 1] Determine the IP version to look for in
1677 ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */
1678#define NIG_REG_LLH0_IPV4_IPV6_0 0x10208
1679/* [RW 1] t bit for llh0 */
1680#define NIG_REG_LLH0_T_BIT 0x10074
1681/* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */
1682#define NIG_REG_LLH0_VLAN_ID_0 0x1022c
1481/* [RW 8] init credit counter for port0 in LLH */ 1683/* [RW 8] init credit counter for port0 in LLH */
1482#define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554 1684#define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554
1483#define NIG_REG_LLH0_XCM_MASK 0x10130 1685#define NIG_REG_LLH0_XCM_MASK 0x10130
1484/* [RW 1] send to BRB1 if no match on any of RMP rules. */ 1686/* [RW 1] send to BRB1 if no match on any of RMP rules. */
1485#define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc 1687#define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
1688/* [RW 2] Determine the classification participants. 0: no classification.1:
1689 classification upon VLAN id. 2: classification upon MAC address. 3:
1690 classification upon both VLAN id & MAC addr. */
1691#define NIG_REG_LLH1_CLS_TYPE 0x16084
1486/* [RW 32] cm header for llh1 */ 1692/* [RW 32] cm header for llh1 */
1487#define NIG_REG_LLH1_CM_HEADER 0x10080 1693#define NIG_REG_LLH1_CM_HEADER 0x10080
1488#define NIG_REG_LLH1_ERROR_MASK 0x10090 1694#define NIG_REG_LLH1_ERROR_MASK 0x10090
@@ -1491,13 +1697,26 @@
1491/* [RW 8] init credit counter for port1 in LLH */ 1697/* [RW 8] init credit counter for port1 in LLH */
1492#define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564 1698#define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564
1493#define NIG_REG_LLH1_XCM_MASK 0x10134 1699#define NIG_REG_LLH1_XCM_MASK 0x10134
1700/* [RW 1] When this bit is set; the LLH will expect all packets to be with
1701 e1hov */
1702#define NIG_REG_LLH_E1HOV_MODE 0x160d8
1703/* [RW 1] When this bit is set; the LLH will classify the packet before
1704 sending it to the BRB or calculating WoL on it. */
1705#define NIG_REG_LLH_MF_MODE 0x16024
1494#define NIG_REG_MASK_INTERRUPT_PORT0 0x10330 1706#define NIG_REG_MASK_INTERRUPT_PORT0 0x10330
1495#define NIG_REG_MASK_INTERRUPT_PORT1 0x10334 1707#define NIG_REG_MASK_INTERRUPT_PORT1 0x10334
1496/* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */ 1708/* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
1497#define NIG_REG_NIG_EMAC0_EN 0x1003c 1709#define NIG_REG_NIG_EMAC0_EN 0x1003c
1710/* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */
1711#define NIG_REG_NIG_EMAC1_EN 0x10040
1498/* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the 1712/* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the
1499 EMAC0 to strip the CRC from the ingress packets. */ 1713 EMAC0 to strip the CRC from the ingress packets. */
1500#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044 1714#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044
1715/* [R 32] Interrupt register #0 read */
1716#define NIG_REG_NIG_INT_STS_0 0x103b0
1717#define NIG_REG_NIG_INT_STS_1 0x103c0
1718/* [R 32] Parity register #0 read */
1719#define NIG_REG_NIG_PRTY_STS 0x103d0
1501/* [RW 1] Input enable for RX PBF LP IF */ 1720/* [RW 1] Input enable for RX PBF LP IF */
1502#define NIG_REG_PBF_LB_IN_EN 0x100b4 1721#define NIG_REG_PBF_LB_IN_EN 0x100b4
1503/* [RW 1] Value of this register will be transmitted to port swap when 1722/* [RW 1] Value of this register will be transmitted to port swap when
@@ -1529,8 +1748,12 @@
1529#define NIG_REG_XCM0_OUT_EN 0x100f0 1748#define NIG_REG_XCM0_OUT_EN 0x100f0
1530/* [RW 1] output enable for RX_XCM1 IF */ 1749/* [RW 1] output enable for RX_XCM1 IF */
1531#define NIG_REG_XCM1_OUT_EN 0x100f4 1750#define NIG_REG_XCM1_OUT_EN 0x100f4
1751/* [RW 1] control to xgxs - remote PHY in-band MDIO */
1752#define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348
1532/* [RW 5] control to xgxs - CL45 DEVAD */ 1753/* [RW 5] control to xgxs - CL45 DEVAD */
1533#define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c 1754#define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c
1755/* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
1756#define NIG_REG_XGXS0_CTRL_MD_ST 0x10338
1534/* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */ 1757/* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
1535#define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340 1758#define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
1536/* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */ 1759/* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
@@ -1658,11 +1881,15 @@
1658#define PRS_REG_CM_HDR_TYPE_4 0x40088 1881#define PRS_REG_CM_HDR_TYPE_4 0x40088
1659/* [RW 32] The CM header in case there was not a match on the connection */ 1882/* [RW 32] The CM header in case there was not a match on the connection */
1660#define PRS_REG_CM_NO_MATCH_HDR 0x400b8 1883#define PRS_REG_CM_NO_MATCH_HDR 0x400b8
1884/* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */
1885#define PRS_REG_E1HOV_MODE 0x401c8
1661/* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet 1886/* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
1662 start message to TCM. */ 1887 start message to TCM. */
1663#define PRS_REG_EVENT_ID_1 0x40054 1888#define PRS_REG_EVENT_ID_1 0x40054
1664#define PRS_REG_EVENT_ID_2 0x40058 1889#define PRS_REG_EVENT_ID_2 0x40058
1665#define PRS_REG_EVENT_ID_3 0x4005c 1890#define PRS_REG_EVENT_ID_3 0x4005c
1891/* [RW 16] The Ethernet type value for FCoE */
1892#define PRS_REG_FCOE_TYPE 0x401d0
1666/* [RW 8] Context region for flush packet with packet type 0. Used in CFC 1893/* [RW 8] Context region for flush packet with packet type 0. Used in CFC
1667 load request message. */ 1894 load request message. */
1668#define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004 1895#define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004
@@ -1732,6 +1959,11 @@
1732#define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478 1959#define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
1733#define PXP2_REG_PGL_CONTROL0 0x120490 1960#define PXP2_REG_PGL_CONTROL0 0x120490
1734#define PXP2_REG_PGL_CONTROL1 0x120514 1961#define PXP2_REG_PGL_CONTROL1 0x120514
1962/* [RW 32] third dword data of expansion rom request. this register is
1963 special. reading from it provides a vector outstanding read requests. if
1964 a bit is zero it means that a read request on the corresponding tag did
1965 not finish yet (not all completions have arrived for it) */
1966#define PXP2_REG_PGL_EXP_ROM2 0x120808
1735/* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask; 1967/* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
1736 its[15:0]-address */ 1968 its[15:0]-address */
1737#define PXP2_REG_PGL_INT_CSDM_0 0x1204f4 1969#define PXP2_REG_PGL_INT_CSDM_0 0x1204f4
@@ -1775,8 +2007,7 @@
1775/* [R 1] this bit indicates that a read request was blocked because of 2007/* [R 1] this bit indicates that a read request was blocked because of
1776 bus_master_en was deasserted */ 2008 bus_master_en was deasserted */
1777#define PXP2_REG_PGL_READ_BLOCKED 0x120568 2009#define PXP2_REG_PGL_READ_BLOCKED 0x120568
1778/* [R 6] debug only */ 2010#define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8
1779#define PXP2_REG_PGL_TXR_CDTS 0x120528
1780/* [R 18] debug only */ 2011/* [R 18] debug only */
1781#define PXP2_REG_PGL_TXW_CDTS 0x12052c 2012#define PXP2_REG_PGL_TXW_CDTS 0x12052c
1782/* [R 1] this bit indicates that a write request was blocked because of 2013/* [R 1] this bit indicates that a write request was blocked because of
@@ -1828,6 +2059,7 @@
1828#define PXP2_REG_PSWRQ_QM0_L2P 0x120038 2059#define PXP2_REG_PSWRQ_QM0_L2P 0x120038
1829#define PXP2_REG_PSWRQ_SRC0_L2P 0x120054 2060#define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
1830#define PXP2_REG_PSWRQ_TM0_L2P 0x12001c 2061#define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
2062#define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0
1831/* [RW 25] Interrupt mask register #0 read/write */ 2063/* [RW 25] Interrupt mask register #0 read/write */
1832#define PXP2_REG_PXP2_INT_MASK 0x120578 2064#define PXP2_REG_PXP2_INT_MASK 0x120578
1833/* [R 25] Interrupt register #0 read */ 2065/* [R 25] Interrupt register #0 read */
@@ -2016,8 +2248,12 @@
2016#define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4 2248#define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4
2017/* [RW 7] Bandwidth upper bound for VQ30 */ 2249/* [RW 7] Bandwidth upper bound for VQ30 */
2018#define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8 2250#define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8
2251/* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */
2252#define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008
2019/* [RW 2] Endian mode for cdu */ 2253/* [RW 2] Endian mode for cdu */
2020#define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0 2254#define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0
2255#define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c
2256#define PXP2_REG_RQ_CDU_LAST_ILT 0x120620
2021/* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k; 2257/* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
2022 -128k */ 2258 -128k */
2023#define PXP2_REG_RQ_CDU_P_SIZE 0x120018 2259#define PXP2_REG_RQ_CDU_P_SIZE 0x120018
@@ -2029,14 +2265,26 @@
2029/* [RW 1] When '1'; requests will enter input buffers but wont get out 2265/* [RW 1] When '1'; requests will enter input buffers but wont get out
2030 towards the glue */ 2266 towards the glue */
2031#define PXP2_REG_RQ_DISABLE_INPUTS 0x120330 2267#define PXP2_REG_RQ_DISABLE_INPUTS 0x120330
2268/* [RW 1] 1 - SR will be aligned by 64B; 0 - SR will be aligned by 8B */
2269#define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0
2270/* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will
2271 be asserted */
2272#define PXP2_REG_RQ_ELT_DISABLE 0x12066c
2032/* [RW 2] Endian mode for hc */ 2273/* [RW 2] Endian mode for hc */
2033#define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8 2274#define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8
2275/* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back
2276 compatibility needs; Note that different registers are used per mode */
2277#define PXP2_REG_RQ_ILT_MODE 0x1205b4
2034/* [WB 53] Onchip address table */ 2278/* [WB 53] Onchip address table */
2035#define PXP2_REG_RQ_ONCHIP_AT 0x122000 2279#define PXP2_REG_RQ_ONCHIP_AT 0x122000
2280/* [WB 53] Onchip address table - B0 */
2281#define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000
2036/* [RW 13] Pending read limiter threshold; in Dwords */ 2282/* [RW 13] Pending read limiter threshold; in Dwords */
2037#define PXP2_REG_RQ_PDR_LIMIT 0x12033c 2283#define PXP2_REG_RQ_PDR_LIMIT 0x12033c
2038/* [RW 2] Endian mode for qm */ 2284/* [RW 2] Endian mode for qm */
2039#define PXP2_REG_RQ_QM_ENDIAN_M 0x120194 2285#define PXP2_REG_RQ_QM_ENDIAN_M 0x120194
2286#define PXP2_REG_RQ_QM_FIRST_ILT 0x120634
2287#define PXP2_REG_RQ_QM_LAST_ILT 0x120638
2040/* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k; 2288/* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
2041 -128k */ 2289 -128k */
2042#define PXP2_REG_RQ_QM_P_SIZE 0x120050 2290#define PXP2_REG_RQ_QM_P_SIZE 0x120050
@@ -2050,16 +2298,22 @@
2050#define PXP2_REG_RQ_RD_MBS1 0x120168 2298#define PXP2_REG_RQ_RD_MBS1 0x120168
2051/* [RW 2] Endian mode for src */ 2299/* [RW 2] Endian mode for src */
2052#define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c 2300#define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c
2301#define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c
2302#define PXP2_REG_RQ_SRC_LAST_ILT 0x120640
2053/* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k; 2303/* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
2054 -128k */ 2304 -128k */
2055#define PXP2_REG_RQ_SRC_P_SIZE 0x12006c 2305#define PXP2_REG_RQ_SRC_P_SIZE 0x12006c
2056/* [RW 2] Endian mode for tm */ 2306/* [RW 2] Endian mode for tm */
2057#define PXP2_REG_RQ_TM_ENDIAN_M 0x120198 2307#define PXP2_REG_RQ_TM_ENDIAN_M 0x120198
2308#define PXP2_REG_RQ_TM_FIRST_ILT 0x120644
2309#define PXP2_REG_RQ_TM_LAST_ILT 0x120648
2058/* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k; 2310/* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
2059 -128k */ 2311 -128k */
2060#define PXP2_REG_RQ_TM_P_SIZE 0x120034 2312#define PXP2_REG_RQ_TM_P_SIZE 0x120034
2061/* [R 5] Number of entries in the ufifo; his fifo has l2p completions */ 2313/* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
2062#define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c 2314#define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c
2315/* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */
2316#define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094
2063/* [R 8] Number of entries occupied by vq 0 in pswrq memory */ 2317/* [R 8] Number of entries occupied by vq 0 in pswrq memory */
2064#define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810 2318#define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810
2065/* [R 8] Number of entries occupied by vq 10 in pswrq memory */ 2319/* [R 8] Number of entries occupied by vq 10 in pswrq memory */
@@ -2130,19 +2384,63 @@
2130/* [RW 3] Max burst size filed for write requests port 1; 000 - 128B; 2384/* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
2131 001:256B; 010: 512B; */ 2385 001:256B; 010: 512B; */
2132#define PXP2_REG_RQ_WR_MBS1 0x120164 2386#define PXP2_REG_RQ_WR_MBS1 0x120164
2387/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2388 buffer reaches this number has_payload will be asserted */
2389#define PXP2_REG_WR_CDU_MPS 0x1205f0
2390/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2391 buffer reaches this number has_payload will be asserted */
2392#define PXP2_REG_WR_CSDM_MPS 0x1205d0
2393/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2394 buffer reaches this number has_payload will be asserted */
2395#define PXP2_REG_WR_DBG_MPS 0x1205e8
2396/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2397 buffer reaches this number has_payload will be asserted */
2398#define PXP2_REG_WR_DMAE_MPS 0x1205ec
2133/* [RW 10] if Number of entries in dmae fifo will be higer than this 2399/* [RW 10] if Number of entries in dmae fifo will be higer than this
2134 threshold then has_payload indication will be asserted; the default value 2400 threshold then has_payload indication will be asserted; the default value
2135 should be equal to &gt; write MBS size! */ 2401 should be equal to &gt; write MBS size! */
2136#define PXP2_REG_WR_DMAE_TH 0x120368 2402#define PXP2_REG_WR_DMAE_TH 0x120368
2403/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2404 buffer reaches this number has_payload will be asserted */
2405#define PXP2_REG_WR_HC_MPS 0x1205c8
2406/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2407 buffer reaches this number has_payload will be asserted */
2408#define PXP2_REG_WR_QM_MPS 0x1205dc
2409/* [RW 1] 0 - working in A0 mode; - working in B0 mode */
2410#define PXP2_REG_WR_REV_MODE 0x120670
2411/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2412 buffer reaches this number has_payload will be asserted */
2413#define PXP2_REG_WR_SRC_MPS 0x1205e4
2414/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2415 buffer reaches this number has_payload will be asserted */
2416#define PXP2_REG_WR_TM_MPS 0x1205e0
2417/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2418 buffer reaches this number has_payload will be asserted */
2419#define PXP2_REG_WR_TSDM_MPS 0x1205d4
2137/* [RW 10] if Number of entries in usdmdp fifo will be higer than this 2420/* [RW 10] if Number of entries in usdmdp fifo will be higer than this
2138 threshold then has_payload indication will be asserted; the default value 2421 threshold then has_payload indication will be asserted; the default value
2139 should be equal to &gt; write MBS size! */ 2422 should be equal to &gt; write MBS size! */
2140#define PXP2_REG_WR_USDMDP_TH 0x120348 2423#define PXP2_REG_WR_USDMDP_TH 0x120348
2424/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2425 buffer reaches this number has_payload will be asserted */
2426#define PXP2_REG_WR_USDM_MPS 0x1205cc
2427/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2428 buffer reaches this number has_payload will be asserted */
2429#define PXP2_REG_WR_XSDM_MPS 0x1205d8
2141/* [R 1] debug only: Indication if PSWHST arbiter is idle */ 2430/* [R 1] debug only: Indication if PSWHST arbiter is idle */
2142#define PXP_REG_HST_ARB_IS_IDLE 0x103004 2431#define PXP_REG_HST_ARB_IS_IDLE 0x103004
2143/* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means 2432/* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
2144 this client is waiting for the arbiter. */ 2433 this client is waiting for the arbiter. */
2145#define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008 2434#define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008
2435/* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit
2436 should update accoring to 'hst_discard_doorbells' register when the state
2437 machine is idle */
2438#define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0
2439/* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1'
2440 means this PSWHST is discarding inputs from this client. Each bit should
2441 update accoring to 'hst_discard_internal_writes' register when the state
2442 machine is idle. */
2443#define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c
2146/* [WB 160] Used for initialization of the inbound interrupts memory */ 2444/* [WB 160] Used for initialization of the inbound interrupts memory */
2147#define PXP_REG_HST_INBOUND_INT 0x103800 2445#define PXP_REG_HST_INBOUND_INT 0x103800
2148/* [RW 32] Interrupt mask register #0 read/write */ 2446/* [RW 32] Interrupt mask register #0 read/write */
@@ -2165,18 +2463,25 @@
2165#define QM_REG_ACTCTRINITVAL_3 0x16804c 2463#define QM_REG_ACTCTRINITVAL_3 0x16804c
2166/* [RW 32] The base logical address (in bytes) of each physical queue. The 2464/* [RW 32] The base logical address (in bytes) of each physical queue. The
2167 index I represents the physical queue number. The 12 lsbs are ignore and 2465 index I represents the physical queue number. The 12 lsbs are ignore and
2168 considered zero so practically there are only 20 bits in this register. */ 2466 considered zero so practically there are only 20 bits in this register;
2467 queues 63-0 */
2169#define QM_REG_BASEADDR 0x168900 2468#define QM_REG_BASEADDR 0x168900
2170/* [RW 16] The byte credit cost for each task. This value is for both ports */ 2469/* [RW 16] The byte credit cost for each task. This value is for both ports */
2171#define QM_REG_BYTECRDCOST 0x168234 2470#define QM_REG_BYTECRDCOST 0x168234
2172/* [RW 16] The initial byte credit value for both ports. */ 2471/* [RW 16] The initial byte credit value for both ports. */
2173#define QM_REG_BYTECRDINITVAL 0x168238 2472#define QM_REG_BYTECRDINITVAL 0x168238
2174/* [RW 32] A bit per physical queue. If the bit is cleared then the physical 2473/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2175 queue uses port 0 else it uses port 1. */ 2474 queue uses port 0 else it uses port 1; queues 31-0 */
2176#define QM_REG_BYTECRDPORT_LSB 0x168228 2475#define QM_REG_BYTECRDPORT_LSB 0x168228
2177/* [RW 32] A bit per physical queue. If the bit is cleared then the physical 2476/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2178 queue uses port 0 else it uses port 1. */ 2477 queue uses port 0 else it uses port 1; queues 95-64 */
2478#define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e520
2479/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2480 queue uses port 0 else it uses port 1; queues 63-32 */
2179#define QM_REG_BYTECRDPORT_MSB 0x168224 2481#define QM_REG_BYTECRDPORT_MSB 0x168224
2482/* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2483 queue uses port 0 else it uses port 1; queues 127-96 */
2484#define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51c
2180/* [RW 16] The byte credit value that if above the QM is considered almost 2485/* [RW 16] The byte credit value that if above the QM is considered almost
2181 full */ 2486 full */
2182#define QM_REG_BYTECREDITAFULLTHR 0x168094 2487#define QM_REG_BYTECREDITAFULLTHR 0x168094
@@ -2203,7 +2508,7 @@
2203#define QM_REG_CMINTVOQMASK_6 0x16820c 2508#define QM_REG_CMINTVOQMASK_6 0x16820c
2204#define QM_REG_CMINTVOQMASK_7 0x168210 2509#define QM_REG_CMINTVOQMASK_7 0x168210
2205/* [RW 20] The number of connections divided by 16 which dictates the size 2510/* [RW 20] The number of connections divided by 16 which dictates the size
2206 of each queue per port 0 */ 2511 of each queue which belongs to even function number. */
2207#define QM_REG_CONNNUM_0 0x168020 2512#define QM_REG_CONNNUM_0 0x168020
2208/* [R 6] Keep the fill level of the fifo from write client 4 */ 2513/* [R 6] Keep the fill level of the fifo from write client 4 */
2209#define QM_REG_CQM_WRC_FIFOLVL 0x168018 2514#define QM_REG_CQM_WRC_FIFOLVL 0x168018
@@ -2216,74 +2521,179 @@
2216 bypass enable */ 2521 bypass enable */
2217#define QM_REG_ENBYPVOQMASK 0x16823c 2522#define QM_REG_ENBYPVOQMASK 0x16823c
2218/* [RW 32] A bit mask per each physical queue. If a bit is set then the 2523/* [RW 32] A bit mask per each physical queue. If a bit is set then the
2219 physical queue uses the byte credit */ 2524 physical queue uses the byte credit; queues 31-0 */
2220#define QM_REG_ENBYTECRD_LSB 0x168220 2525#define QM_REG_ENBYTECRD_LSB 0x168220
2221/* [RW 32] A bit mask per each physical queue. If a bit is set then the 2526/* [RW 32] A bit mask per each physical queue. If a bit is set then the
2222 physical queue uses the byte credit */ 2527 physical queue uses the byte credit; queues 95-64 */
2528#define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e518
2529/* [RW 32] A bit mask per each physical queue. If a bit is set then the
2530 physical queue uses the byte credit; queues 63-32 */
2223#define QM_REG_ENBYTECRD_MSB 0x16821c 2531#define QM_REG_ENBYTECRD_MSB 0x16821c
2532/* [RW 32] A bit mask per each physical queue. If a bit is set then the
2533 physical queue uses the byte credit; queues 127-96 */
2534#define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e514
2224/* [RW 4] If cleared then the secondary interface will not be served by the 2535/* [RW 4] If cleared then the secondary interface will not be served by the
2225 RR arbiter */ 2536 RR arbiter */
2226#define QM_REG_ENSEC 0x1680f0 2537#define QM_REG_ENSEC 0x1680f0
2227/* [RW 32] A bit vector per each physical queue which selects which function 2538/* [RW 32] NA */
2228 number to use on PCI access for that queue. */
2229#define QM_REG_FUNCNUMSEL_LSB 0x168230 2539#define QM_REG_FUNCNUMSEL_LSB 0x168230
2230/* [RW 32] A bit vector per each physical queue which selects which function 2540/* [RW 32] NA */
2231 number to use on PCI access for that queue. */
2232#define QM_REG_FUNCNUMSEL_MSB 0x16822c 2541#define QM_REG_FUNCNUMSEL_MSB 0x16822c
2233/* [RW 32] A mask register to mask the Almost empty signals which will not 2542/* [RW 32] A mask register to mask the Almost empty signals which will not
2234 be use for the almost empty indication to the HW block */ 2543 be use for the almost empty indication to the HW block; queues 31:0 */
2235#define QM_REG_HWAEMPTYMASK_LSB 0x168218 2544#define QM_REG_HWAEMPTYMASK_LSB 0x168218
2236/* [RW 32] A mask register to mask the Almost empty signals which will not 2545/* [RW 32] A mask register to mask the Almost empty signals which will not
2237 be use for the almost empty indication to the HW block */ 2546 be use for the almost empty indication to the HW block; queues 95-64 */
2547#define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e510
2548/* [RW 32] A mask register to mask the Almost empty signals which will not
2549 be use for the almost empty indication to the HW block; queues 63:32 */
2238#define QM_REG_HWAEMPTYMASK_MSB 0x168214 2550#define QM_REG_HWAEMPTYMASK_MSB 0x168214
2551/* [RW 32] A mask register to mask the Almost empty signals which will not
2552 be use for the almost empty indication to the HW block; queues 127-96 */
2553#define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50c
2239/* [RW 4] The number of outstanding request to CFC */ 2554/* [RW 4] The number of outstanding request to CFC */
2240#define QM_REG_OUTLDREQ 0x168804 2555#define QM_REG_OUTLDREQ 0x168804
2241/* [RC 1] A flag to indicate that overflow error occurred in one of the 2556/* [RC 1] A flag to indicate that overflow error occurred in one of the
2242 queues. */ 2557 queues. */
2243#define QM_REG_OVFERROR 0x16805c 2558#define QM_REG_OVFERROR 0x16805c
2244/* [RC 6] the Q were the qverflow occurs */ 2559/* [RC 7] the Q were the qverflow occurs */
2245#define QM_REG_OVFQNUM 0x168058 2560#define QM_REG_OVFQNUM 0x168058
2246/* [R 32] Pause state for physical queues 31-0 */ 2561/* [R 16] Pause state for physical queues 15-0 */
2247#define QM_REG_PAUSESTATE0 0x168410 2562#define QM_REG_PAUSESTATE0 0x168410
2248/* [R 32] Pause state for physical queues 64-32 */ 2563/* [R 16] Pause state for physical queues 31-16 */
2249#define QM_REG_PAUSESTATE1 0x168414 2564#define QM_REG_PAUSESTATE1 0x168414
2565/* [R 16] Pause state for physical queues 47-32 */
2566#define QM_REG_PAUSESTATE2 0x16e684
2567/* [R 16] Pause state for physical queues 63-48 */
2568#define QM_REG_PAUSESTATE3 0x16e688
2569/* [R 16] Pause state for physical queues 79-64 */
2570#define QM_REG_PAUSESTATE4 0x16e68c
2571/* [R 16] Pause state for physical queues 95-80 */
2572#define QM_REG_PAUSESTATE5 0x16e690
2573/* [R 16] Pause state for physical queues 111-96 */
2574#define QM_REG_PAUSESTATE6 0x16e694
2575/* [R 16] Pause state for physical queues 127-112 */
2576#define QM_REG_PAUSESTATE7 0x16e698
2250/* [RW 2] The PCI attributes field used in the PCI request. */ 2577/* [RW 2] The PCI attributes field used in the PCI request. */
2251#define QM_REG_PCIREQAT 0x168054 2578#define QM_REG_PCIREQAT 0x168054
2252/* [R 16] The byte credit of port 0 */ 2579/* [R 16] The byte credit of port 0 */
2253#define QM_REG_PORT0BYTECRD 0x168300 2580#define QM_REG_PORT0BYTECRD 0x168300
2254/* [R 16] The byte credit of port 1 */ 2581/* [R 16] The byte credit of port 1 */
2255#define QM_REG_PORT1BYTECRD 0x168304 2582#define QM_REG_PORT1BYTECRD 0x168304
2256/* [WB 54] Pointer Table Memory; The mapping is as follow: ptrtbl[53:30] 2583/* [RW 3] pci function number of queues 15-0 */
2257 read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read bank0; 2584#define QM_REG_PQ2PCIFUNC_0 0x16e6bc
2258 ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */ 2585#define QM_REG_PQ2PCIFUNC_1 0x16e6c0
2586#define QM_REG_PQ2PCIFUNC_2 0x16e6c4
2587#define QM_REG_PQ2PCIFUNC_3 0x16e6c8
2588#define QM_REG_PQ2PCIFUNC_4 0x16e6cc
2589#define QM_REG_PQ2PCIFUNC_5 0x16e6d0
2590#define QM_REG_PQ2PCIFUNC_6 0x16e6d4
2591#define QM_REG_PQ2PCIFUNC_7 0x16e6d8
2592/* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:
2593 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
2594 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
2259#define QM_REG_PTRTBL 0x168a00 2595#define QM_REG_PTRTBL 0x168a00
2596/* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow:
2597 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
2598 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
2599#define QM_REG_PTRTBL_EXT_A 0x16e200
2260/* [RW 2] Interrupt mask register #0 read/write */ 2600/* [RW 2] Interrupt mask register #0 read/write */
2261#define QM_REG_QM_INT_MASK 0x168444 2601#define QM_REG_QM_INT_MASK 0x168444
2262/* [R 2] Interrupt register #0 read */ 2602/* [R 2] Interrupt register #0 read */
2263#define QM_REG_QM_INT_STS 0x168438 2603#define QM_REG_QM_INT_STS 0x168438
2264/* [RW 9] Parity mask register #0 read/write */ 2604/* [RW 12] Parity mask register #0 read/write */
2265#define QM_REG_QM_PRTY_MASK 0x168454 2605#define QM_REG_QM_PRTY_MASK 0x168454
2266/* [R 9] Parity register #0 read */ 2606/* [R 12] Parity register #0 read */
2267#define QM_REG_QM_PRTY_STS 0x168448 2607#define QM_REG_QM_PRTY_STS 0x168448
2268/* [R 32] Current queues in pipeline: Queues from 32 to 63 */ 2608/* [R 32] Current queues in pipeline: Queues from 32 to 63 */
2269#define QM_REG_QSTATUS_HIGH 0x16802c 2609#define QM_REG_QSTATUS_HIGH 0x16802c
2610/* [R 32] Current queues in pipeline: Queues from 96 to 127 */
2611#define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408
2270/* [R 32] Current queues in pipeline: Queues from 0 to 31 */ 2612/* [R 32] Current queues in pipeline: Queues from 0 to 31 */
2271#define QM_REG_QSTATUS_LOW 0x168028 2613#define QM_REG_QSTATUS_LOW 0x168028
2272/* [R 24] The number of tasks queued for each queue */ 2614/* [R 32] Current queues in pipeline: Queues from 64 to 95 */
2615#define QM_REG_QSTATUS_LOW_EXT_A 0x16e404
2616/* [R 24] The number of tasks queued for each queue; queues 63-0 */
2273#define QM_REG_QTASKCTR_0 0x168308 2617#define QM_REG_QTASKCTR_0 0x168308
2618/* [R 24] The number of tasks queued for each queue; queues 127-64 */
2619#define QM_REG_QTASKCTR_EXT_A_0 0x16e584
2274/* [RW 4] Queue tied to VOQ */ 2620/* [RW 4] Queue tied to VOQ */
2275#define QM_REG_QVOQIDX_0 0x1680f4 2621#define QM_REG_QVOQIDX_0 0x1680f4
2276#define QM_REG_QVOQIDX_10 0x16811c 2622#define QM_REG_QVOQIDX_10 0x16811c
2623#define QM_REG_QVOQIDX_100 0x16e49c
2624#define QM_REG_QVOQIDX_101 0x16e4a0
2625#define QM_REG_QVOQIDX_102 0x16e4a4
2626#define QM_REG_QVOQIDX_103 0x16e4a8
2627#define QM_REG_QVOQIDX_104 0x16e4ac
2628#define QM_REG_QVOQIDX_105 0x16e4b0
2629#define QM_REG_QVOQIDX_106 0x16e4b4
2630#define QM_REG_QVOQIDX_107 0x16e4b8
2631#define QM_REG_QVOQIDX_108 0x16e4bc
2632#define QM_REG_QVOQIDX_109 0x16e4c0
2633#define QM_REG_QVOQIDX_100 0x16e49c
2634#define QM_REG_QVOQIDX_101 0x16e4a0
2635#define QM_REG_QVOQIDX_102 0x16e4a4
2636#define QM_REG_QVOQIDX_103 0x16e4a8
2637#define QM_REG_QVOQIDX_104 0x16e4ac
2638#define QM_REG_QVOQIDX_105 0x16e4b0
2639#define QM_REG_QVOQIDX_106 0x16e4b4
2640#define QM_REG_QVOQIDX_107 0x16e4b8
2641#define QM_REG_QVOQIDX_108 0x16e4bc
2642#define QM_REG_QVOQIDX_109 0x16e4c0
2277#define QM_REG_QVOQIDX_11 0x168120 2643#define QM_REG_QVOQIDX_11 0x168120
2644#define QM_REG_QVOQIDX_110 0x16e4c4
2645#define QM_REG_QVOQIDX_111 0x16e4c8
2646#define QM_REG_QVOQIDX_112 0x16e4cc
2647#define QM_REG_QVOQIDX_113 0x16e4d0
2648#define QM_REG_QVOQIDX_114 0x16e4d4
2649#define QM_REG_QVOQIDX_115 0x16e4d8
2650#define QM_REG_QVOQIDX_116 0x16e4dc
2651#define QM_REG_QVOQIDX_117 0x16e4e0
2652#define QM_REG_QVOQIDX_118 0x16e4e4
2653#define QM_REG_QVOQIDX_119 0x16e4e8
2654#define QM_REG_QVOQIDX_110 0x16e4c4
2655#define QM_REG_QVOQIDX_111 0x16e4c8
2656#define QM_REG_QVOQIDX_112 0x16e4cc
2657#define QM_REG_QVOQIDX_113 0x16e4d0
2658#define QM_REG_QVOQIDX_114 0x16e4d4
2659#define QM_REG_QVOQIDX_115 0x16e4d8
2660#define QM_REG_QVOQIDX_116 0x16e4dc
2661#define QM_REG_QVOQIDX_117 0x16e4e0
2662#define QM_REG_QVOQIDX_118 0x16e4e4
2663#define QM_REG_QVOQIDX_119 0x16e4e8
2278#define QM_REG_QVOQIDX_12 0x168124 2664#define QM_REG_QVOQIDX_12 0x168124
2665#define QM_REG_QVOQIDX_120 0x16e4ec
2666#define QM_REG_QVOQIDX_121 0x16e4f0
2667#define QM_REG_QVOQIDX_122 0x16e4f4
2668#define QM_REG_QVOQIDX_123 0x16e4f8
2669#define QM_REG_QVOQIDX_124 0x16e4fc
2670#define QM_REG_QVOQIDX_125 0x16e500
2671#define QM_REG_QVOQIDX_126 0x16e504
2672#define QM_REG_QVOQIDX_127 0x16e508
2673#define QM_REG_QVOQIDX_120 0x16e4ec
2674#define QM_REG_QVOQIDX_121 0x16e4f0
2675#define QM_REG_QVOQIDX_122 0x16e4f4
2676#define QM_REG_QVOQIDX_123 0x16e4f8
2677#define QM_REG_QVOQIDX_124 0x16e4fc
2678#define QM_REG_QVOQIDX_125 0x16e500
2679#define QM_REG_QVOQIDX_126 0x16e504
2680#define QM_REG_QVOQIDX_127 0x16e508
2279#define QM_REG_QVOQIDX_13 0x168128 2681#define QM_REG_QVOQIDX_13 0x168128
2280#define QM_REG_QVOQIDX_14 0x16812c 2682#define QM_REG_QVOQIDX_14 0x16812c
2281#define QM_REG_QVOQIDX_15 0x168130 2683#define QM_REG_QVOQIDX_15 0x168130
2282#define QM_REG_QVOQIDX_16 0x168134 2684#define QM_REG_QVOQIDX_16 0x168134
2283#define QM_REG_QVOQIDX_17 0x168138 2685#define QM_REG_QVOQIDX_17 0x168138
2284#define QM_REG_QVOQIDX_21 0x168148 2686#define QM_REG_QVOQIDX_21 0x168148
2687#define QM_REG_QVOQIDX_22 0x16814c
2688#define QM_REG_QVOQIDX_23 0x168150
2689#define QM_REG_QVOQIDX_24 0x168154
2285#define QM_REG_QVOQIDX_25 0x168158 2690#define QM_REG_QVOQIDX_25 0x168158
2691#define QM_REG_QVOQIDX_26 0x16815c
2692#define QM_REG_QVOQIDX_27 0x168160
2693#define QM_REG_QVOQIDX_28 0x168164
2286#define QM_REG_QVOQIDX_29 0x168168 2694#define QM_REG_QVOQIDX_29 0x168168
2695#define QM_REG_QVOQIDX_30 0x16816c
2696#define QM_REG_QVOQIDX_31 0x168170
2287#define QM_REG_QVOQIDX_32 0x168174 2697#define QM_REG_QVOQIDX_32 0x168174
2288#define QM_REG_QVOQIDX_33 0x168178 2698#define QM_REG_QVOQIDX_33 0x168178
2289#define QM_REG_QVOQIDX_34 0x16817c 2699#define QM_REG_QVOQIDX_34 0x16817c
@@ -2328,17 +2738,95 @@
2328#define QM_REG_QVOQIDX_61 0x1681e8 2738#define QM_REG_QVOQIDX_61 0x1681e8
2329#define QM_REG_QVOQIDX_62 0x1681ec 2739#define QM_REG_QVOQIDX_62 0x1681ec
2330#define QM_REG_QVOQIDX_63 0x1681f0 2740#define QM_REG_QVOQIDX_63 0x1681f0
2741#define QM_REG_QVOQIDX_64 0x16e40c
2742#define QM_REG_QVOQIDX_65 0x16e410
2743#define QM_REG_QVOQIDX_66 0x16e414
2744#define QM_REG_QVOQIDX_67 0x16e418
2745#define QM_REG_QVOQIDX_68 0x16e41c
2746#define QM_REG_QVOQIDX_69 0x16e420
2331#define QM_REG_QVOQIDX_60 0x1681e4 2747#define QM_REG_QVOQIDX_60 0x1681e4
2332#define QM_REG_QVOQIDX_61 0x1681e8 2748#define QM_REG_QVOQIDX_61 0x1681e8
2333#define QM_REG_QVOQIDX_62 0x1681ec 2749#define QM_REG_QVOQIDX_62 0x1681ec
2334#define QM_REG_QVOQIDX_63 0x1681f0 2750#define QM_REG_QVOQIDX_63 0x1681f0
2751#define QM_REG_QVOQIDX_64 0x16e40c
2752#define QM_REG_QVOQIDX_65 0x16e410
2753#define QM_REG_QVOQIDX_69 0x16e420
2335#define QM_REG_QVOQIDX_7 0x168110 2754#define QM_REG_QVOQIDX_7 0x168110
2755#define QM_REG_QVOQIDX_70 0x16e424
2756#define QM_REG_QVOQIDX_71 0x16e428
2757#define QM_REG_QVOQIDX_72 0x16e42c
2758#define QM_REG_QVOQIDX_73 0x16e430
2759#define QM_REG_QVOQIDX_74 0x16e434
2760#define QM_REG_QVOQIDX_75 0x16e438
2761#define QM_REG_QVOQIDX_76 0x16e43c
2762#define QM_REG_QVOQIDX_77 0x16e440
2763#define QM_REG_QVOQIDX_78 0x16e444
2764#define QM_REG_QVOQIDX_79 0x16e448
2765#define QM_REG_QVOQIDX_70 0x16e424
2766#define QM_REG_QVOQIDX_71 0x16e428
2767#define QM_REG_QVOQIDX_72 0x16e42c
2768#define QM_REG_QVOQIDX_73 0x16e430
2769#define QM_REG_QVOQIDX_74 0x16e434
2770#define QM_REG_QVOQIDX_75 0x16e438
2771#define QM_REG_QVOQIDX_76 0x16e43c
2772#define QM_REG_QVOQIDX_77 0x16e440
2773#define QM_REG_QVOQIDX_78 0x16e444
2774#define QM_REG_QVOQIDX_79 0x16e448
2336#define QM_REG_QVOQIDX_8 0x168114 2775#define QM_REG_QVOQIDX_8 0x168114
2776#define QM_REG_QVOQIDX_80 0x16e44c
2777#define QM_REG_QVOQIDX_81 0x16e450
2778#define QM_REG_QVOQIDX_82 0x16e454
2779#define QM_REG_QVOQIDX_83 0x16e458
2780#define QM_REG_QVOQIDX_84 0x16e45c
2781#define QM_REG_QVOQIDX_85 0x16e460
2782#define QM_REG_QVOQIDX_86 0x16e464
2783#define QM_REG_QVOQIDX_87 0x16e468
2784#define QM_REG_QVOQIDX_88 0x16e46c
2785#define QM_REG_QVOQIDX_89 0x16e470
2786#define QM_REG_QVOQIDX_80 0x16e44c
2787#define QM_REG_QVOQIDX_81 0x16e450
2788#define QM_REG_QVOQIDX_85 0x16e460
2789#define QM_REG_QVOQIDX_86 0x16e464
2790#define QM_REG_QVOQIDX_87 0x16e468
2791#define QM_REG_QVOQIDX_88 0x16e46c
2792#define QM_REG_QVOQIDX_89 0x16e470
2337#define QM_REG_QVOQIDX_9 0x168118 2793#define QM_REG_QVOQIDX_9 0x168118
2338/* [R 24] Remaining pause timeout for port 0 */ 2794#define QM_REG_QVOQIDX_90 0x16e474
2795#define QM_REG_QVOQIDX_91 0x16e478
2796#define QM_REG_QVOQIDX_92 0x16e47c
2797#define QM_REG_QVOQIDX_93 0x16e480
2798#define QM_REG_QVOQIDX_94 0x16e484
2799#define QM_REG_QVOQIDX_95 0x16e488
2800#define QM_REG_QVOQIDX_96 0x16e48c
2801#define QM_REG_QVOQIDX_97 0x16e490
2802#define QM_REG_QVOQIDX_98 0x16e494
2803#define QM_REG_QVOQIDX_99 0x16e498
2804#define QM_REG_QVOQIDX_90 0x16e474
2805#define QM_REG_QVOQIDX_91 0x16e478
2806#define QM_REG_QVOQIDX_92 0x16e47c
2807#define QM_REG_QVOQIDX_93 0x16e480
2808#define QM_REG_QVOQIDX_94 0x16e484
2809#define QM_REG_QVOQIDX_95 0x16e488
2810#define QM_REG_QVOQIDX_96 0x16e48c
2811#define QM_REG_QVOQIDX_97 0x16e490
2812#define QM_REG_QVOQIDX_98 0x16e494
2813#define QM_REG_QVOQIDX_99 0x16e498
2814/* [R 24] Remaining pause timeout for queues 15-0 */
2339#define QM_REG_REMAINPAUSETM0 0x168418 2815#define QM_REG_REMAINPAUSETM0 0x168418
2340/* [R 24] Remaining pause timeout for port 1 */ 2816/* [R 24] Remaining pause timeout for queues 31-16 */
2341#define QM_REG_REMAINPAUSETM1 0x16841c 2817#define QM_REG_REMAINPAUSETM1 0x16841c
2818/* [R 24] Remaining pause timeout for queues 47-32 */
2819#define QM_REG_REMAINPAUSETM2 0x16e69c
2820/* [R 24] Remaining pause timeout for queues 63-48 */
2821#define QM_REG_REMAINPAUSETM3 0x16e6a0
2822/* [R 24] Remaining pause timeout for queues 79-64 */
2823#define QM_REG_REMAINPAUSETM4 0x16e6a4
2824/* [R 24] Remaining pause timeout for queues 95-80 */
2825#define QM_REG_REMAINPAUSETM5 0x16e6a8
2826/* [R 24] Remaining pause timeout for queues 111-96 */
2827#define QM_REG_REMAINPAUSETM6 0x16e6ac
2828/* [R 24] Remaining pause timeout for queues 127-112 */
2829#define QM_REG_REMAINPAUSETM7 0x16e6b0
2342/* [RW 1] Initialization bit command */ 2830/* [RW 1] Initialization bit command */
2343#define QM_REG_SOFT_RESET 0x168428 2831#define QM_REG_SOFT_RESET 0x168428
2344/* [RW 8] The credit cost per every task in the QM. A value per each VOQ */ 2832/* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
@@ -2372,44 +2860,103 @@
2372#define QM_REG_VOQINITCREDIT_4 0x168070 2860#define QM_REG_VOQINITCREDIT_4 0x168070
2373#define QM_REG_VOQINITCREDIT_5 0x168074 2861#define QM_REG_VOQINITCREDIT_5 0x168074
2374/* [RW 1] The port of which VOQ belongs */ 2862/* [RW 1] The port of which VOQ belongs */
2863#define QM_REG_VOQPORT_0 0x1682a0
2375#define QM_REG_VOQPORT_1 0x1682a4 2864#define QM_REG_VOQPORT_1 0x1682a4
2376#define QM_REG_VOQPORT_10 0x1682c8 2865#define QM_REG_VOQPORT_10 0x1682c8
2377#define QM_REG_VOQPORT_11 0x1682cc 2866#define QM_REG_VOQPORT_11 0x1682cc
2378#define QM_REG_VOQPORT_2 0x1682a8 2867#define QM_REG_VOQPORT_2 0x1682a8
2379/* [RW 32] The physical queue number associated with each VOQ */ 2868/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2380#define QM_REG_VOQQMASK_0_LSB 0x168240 2869#define QM_REG_VOQQMASK_0_LSB 0x168240
2381/* [RW 32] The physical queue number associated with each VOQ */ 2870/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2871#define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e524
2872/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2382#define QM_REG_VOQQMASK_0_MSB 0x168244 2873#define QM_REG_VOQQMASK_0_MSB 0x168244
2383/* [RW 32] The physical queue number associated with each VOQ */ 2874/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2875#define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e528
2876/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2877#define QM_REG_VOQQMASK_10_LSB 0x168290
2878/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2879#define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e574
2880/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2881#define QM_REG_VOQQMASK_10_MSB 0x168294
2882/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2883#define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e578
2884/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2885#define QM_REG_VOQQMASK_11_LSB 0x168298
2886/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2887#define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57c
2888/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2889#define QM_REG_VOQQMASK_11_MSB 0x16829c
2890/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2891#define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e580
2892/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2893#define QM_REG_VOQQMASK_1_LSB 0x168248
2894/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2895#define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52c
2896/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2384#define QM_REG_VOQQMASK_1_MSB 0x16824c 2897#define QM_REG_VOQQMASK_1_MSB 0x16824c
2385/* [RW 32] The physical queue number associated with each VOQ */ 2898/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2899#define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e530
2900/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2386#define QM_REG_VOQQMASK_2_LSB 0x168250 2901#define QM_REG_VOQQMASK_2_LSB 0x168250
2387/* [RW 32] The physical queue number associated with each VOQ */ 2902/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2903#define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e534
2904/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2388#define QM_REG_VOQQMASK_2_MSB 0x168254 2905#define QM_REG_VOQQMASK_2_MSB 0x168254
2389/* [RW 32] The physical queue number associated with each VOQ */ 2906/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2907#define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e538
2908/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2390#define QM_REG_VOQQMASK_3_LSB 0x168258 2909#define QM_REG_VOQQMASK_3_LSB 0x168258
2391/* [RW 32] The physical queue number associated with each VOQ */ 2910/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2911#define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53c
2912/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2913#define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e540
2914/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2392#define QM_REG_VOQQMASK_4_LSB 0x168260 2915#define QM_REG_VOQQMASK_4_LSB 0x168260
2393/* [RW 32] The physical queue number associated with each VOQ */ 2916/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2917#define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e544
2918/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2394#define QM_REG_VOQQMASK_4_MSB 0x168264 2919#define QM_REG_VOQQMASK_4_MSB 0x168264
2395/* [RW 32] The physical queue number associated with each VOQ */ 2920/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2921#define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e548
2922/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2396#define QM_REG_VOQQMASK_5_LSB 0x168268 2923#define QM_REG_VOQQMASK_5_LSB 0x168268
2397/* [RW 32] The physical queue number associated with each VOQ */ 2924/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2925#define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54c
2926/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2398#define QM_REG_VOQQMASK_5_MSB 0x16826c 2927#define QM_REG_VOQQMASK_5_MSB 0x16826c
2399/* [RW 32] The physical queue number associated with each VOQ */ 2928/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2929#define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e550
2930/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2400#define QM_REG_VOQQMASK_6_LSB 0x168270 2931#define QM_REG_VOQQMASK_6_LSB 0x168270
2401/* [RW 32] The physical queue number associated with each VOQ */ 2932/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2933#define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e554
2934/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2402#define QM_REG_VOQQMASK_6_MSB 0x168274 2935#define QM_REG_VOQQMASK_6_MSB 0x168274
2403/* [RW 32] The physical queue number associated with each VOQ */ 2936/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2937#define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e558
2938/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2404#define QM_REG_VOQQMASK_7_LSB 0x168278 2939#define QM_REG_VOQQMASK_7_LSB 0x168278
2405/* [RW 32] The physical queue number associated with each VOQ */ 2940/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2941#define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55c
2942/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2406#define QM_REG_VOQQMASK_7_MSB 0x16827c 2943#define QM_REG_VOQQMASK_7_MSB 0x16827c
2407/* [RW 32] The physical queue number associated with each VOQ */ 2944/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2945#define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e560
2946/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2408#define QM_REG_VOQQMASK_8_LSB 0x168280 2947#define QM_REG_VOQQMASK_8_LSB 0x168280
2409/* [RW 32] The physical queue number associated with each VOQ */ 2948/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2949#define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e564
2950/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2410#define QM_REG_VOQQMASK_8_MSB 0x168284 2951#define QM_REG_VOQQMASK_8_MSB 0x168284
2411/* [RW 32] The physical queue number associated with each VOQ */ 2952/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2953#define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e568
2954/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2412#define QM_REG_VOQQMASK_9_LSB 0x168288 2955#define QM_REG_VOQQMASK_9_LSB 0x168288
2956/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2957#define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56c
2958/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2959#define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e570
2413/* [RW 32] Wrr weights */ 2960/* [RW 32] Wrr weights */
2414#define QM_REG_WRRWEIGHTS_0 0x16880c 2961#define QM_REG_WRRWEIGHTS_0 0x16880c
2415#define QM_REG_WRRWEIGHTS_1 0x168810 2962#define QM_REG_WRRWEIGHTS_1 0x168810
@@ -2431,14 +2978,78 @@
2431#define QM_REG_WRRWEIGHTS_15 0x168828 2978#define QM_REG_WRRWEIGHTS_15 0x168828
2432#define QM_REG_WRRWEIGHTS_15_SIZE 1 2979#define QM_REG_WRRWEIGHTS_15_SIZE 1
2433/* [RW 32] Wrr weights */ 2980/* [RW 32] Wrr weights */
2981#define QM_REG_WRRWEIGHTS_16 0x16e000
2982#define QM_REG_WRRWEIGHTS_16_SIZE 1
2983/* [RW 32] Wrr weights */
2984#define QM_REG_WRRWEIGHTS_17 0x16e004
2985#define QM_REG_WRRWEIGHTS_17_SIZE 1
2986/* [RW 32] Wrr weights */
2987#define QM_REG_WRRWEIGHTS_18 0x16e008
2988#define QM_REG_WRRWEIGHTS_18_SIZE 1
2989/* [RW 32] Wrr weights */
2990#define QM_REG_WRRWEIGHTS_19 0x16e00c
2991#define QM_REG_WRRWEIGHTS_19_SIZE 1
2992/* [RW 32] Wrr weights */
2434#define QM_REG_WRRWEIGHTS_10 0x168814 2993#define QM_REG_WRRWEIGHTS_10 0x168814
2435#define QM_REG_WRRWEIGHTS_11 0x168818 2994#define QM_REG_WRRWEIGHTS_11 0x168818
2436#define QM_REG_WRRWEIGHTS_12 0x16881c 2995#define QM_REG_WRRWEIGHTS_12 0x16881c
2437#define QM_REG_WRRWEIGHTS_13 0x168820 2996#define QM_REG_WRRWEIGHTS_13 0x168820
2438#define QM_REG_WRRWEIGHTS_14 0x168824 2997#define QM_REG_WRRWEIGHTS_14 0x168824
2439#define QM_REG_WRRWEIGHTS_15 0x168828 2998#define QM_REG_WRRWEIGHTS_15 0x168828
2999#define QM_REG_WRRWEIGHTS_16 0x16e000
3000#define QM_REG_WRRWEIGHTS_17 0x16e004
3001#define QM_REG_WRRWEIGHTS_18 0x16e008
3002#define QM_REG_WRRWEIGHTS_19 0x16e00c
2440#define QM_REG_WRRWEIGHTS_2 0x16882c 3003#define QM_REG_WRRWEIGHTS_2 0x16882c
3004#define QM_REG_WRRWEIGHTS_20 0x16e010
3005#define QM_REG_WRRWEIGHTS_20_SIZE 1
3006/* [RW 32] Wrr weights */
3007#define QM_REG_WRRWEIGHTS_21 0x16e014
3008#define QM_REG_WRRWEIGHTS_21_SIZE 1
3009/* [RW 32] Wrr weights */
3010#define QM_REG_WRRWEIGHTS_22 0x16e018
3011#define QM_REG_WRRWEIGHTS_22_SIZE 1
3012/* [RW 32] Wrr weights */
3013#define QM_REG_WRRWEIGHTS_23 0x16e01c
3014#define QM_REG_WRRWEIGHTS_23_SIZE 1
3015/* [RW 32] Wrr weights */
3016#define QM_REG_WRRWEIGHTS_24 0x16e020
3017#define QM_REG_WRRWEIGHTS_24_SIZE 1
3018/* [RW 32] Wrr weights */
3019#define QM_REG_WRRWEIGHTS_25 0x16e024
3020#define QM_REG_WRRWEIGHTS_25_SIZE 1
3021/* [RW 32] Wrr weights */
3022#define QM_REG_WRRWEIGHTS_26 0x16e028
3023#define QM_REG_WRRWEIGHTS_26_SIZE 1
3024/* [RW 32] Wrr weights */
3025#define QM_REG_WRRWEIGHTS_27 0x16e02c
3026#define QM_REG_WRRWEIGHTS_27_SIZE 1
3027/* [RW 32] Wrr weights */
3028#define QM_REG_WRRWEIGHTS_28 0x16e030
3029#define QM_REG_WRRWEIGHTS_28_SIZE 1
3030/* [RW 32] Wrr weights */
3031#define QM_REG_WRRWEIGHTS_29 0x16e034
3032#define QM_REG_WRRWEIGHTS_29_SIZE 1
3033/* [RW 32] Wrr weights */
3034#define QM_REG_WRRWEIGHTS_20 0x16e010
3035#define QM_REG_WRRWEIGHTS_21 0x16e014
3036#define QM_REG_WRRWEIGHTS_22 0x16e018
3037#define QM_REG_WRRWEIGHTS_23 0x16e01c
3038#define QM_REG_WRRWEIGHTS_24 0x16e020
3039#define QM_REG_WRRWEIGHTS_25 0x16e024
3040#define QM_REG_WRRWEIGHTS_26 0x16e028
3041#define QM_REG_WRRWEIGHTS_27 0x16e02c
3042#define QM_REG_WRRWEIGHTS_28 0x16e030
3043#define QM_REG_WRRWEIGHTS_29 0x16e034
2441#define QM_REG_WRRWEIGHTS_3 0x168830 3044#define QM_REG_WRRWEIGHTS_3 0x168830
3045#define QM_REG_WRRWEIGHTS_30 0x16e038
3046#define QM_REG_WRRWEIGHTS_30_SIZE 1
3047/* [RW 32] Wrr weights */
3048#define QM_REG_WRRWEIGHTS_31 0x16e03c
3049#define QM_REG_WRRWEIGHTS_31_SIZE 1
3050/* [RW 32] Wrr weights */
3051#define QM_REG_WRRWEIGHTS_30 0x16e038
3052#define QM_REG_WRRWEIGHTS_31 0x16e03c
2442#define QM_REG_WRRWEIGHTS_4 0x168834 3053#define QM_REG_WRRWEIGHTS_4 0x168834
2443#define QM_REG_WRRWEIGHTS_5 0x168838 3054#define QM_REG_WRRWEIGHTS_5 0x168838
2444#define QM_REG_WRRWEIGHTS_6 0x16883c 3055#define QM_REG_WRRWEIGHTS_6 0x16883c
@@ -2447,6 +3058,70 @@
2447#define QM_REG_WRRWEIGHTS_9 0x168848 3058#define QM_REG_WRRWEIGHTS_9 0x168848
2448/* [R 6] Keep the fill level of the fifo from write client 1 */ 3059/* [R 6] Keep the fill level of the fifo from write client 1 */
2449#define QM_REG_XQM_WRC_FIFOLVL 0x168000 3060#define QM_REG_XQM_WRC_FIFOLVL 0x168000
3061#define BRB1_BRB1_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3062#define BRB1_BRB1_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3063#define BRB1_BRB1_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3064#define BRB1_BRB1_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3065#define BRB1_BRB1_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3066#define BRB1_BRB1_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3067#define BRB1_BRB1_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3068#define BRB1_BRB1_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3069#define CCM_CCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3070#define CCM_CCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3071#define CCM_CCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3072#define CCM_CCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3073#define CCM_CCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3074#define CCM_CCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3075#define CCM_CCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3076#define CCM_CCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3077#define CDU_CDU_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3078#define CDU_CDU_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3079#define CDU_CDU_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3080#define CDU_CDU_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3081#define CDU_CDU_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3082#define CDU_CDU_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3083#define CDU_CDU_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3084#define CDU_CDU_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3085#define CFC_CFC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3086#define CFC_CFC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3087#define CFC_CFC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3088#define CFC_CFC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3089#define CFC_CFC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3090#define CFC_CFC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3091#define CFC_CFC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3092#define CFC_CFC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3093#define CSDM_CSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3094#define CSDM_CSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3095#define CSDM_CSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3096#define CSDM_CSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3097#define CSDM_CSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3098#define CSDM_CSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3099#define CSDM_CSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3100#define CSDM_CSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3101#define CSEM_CSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3102#define CSEM_CSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3103#define CSEM_CSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3104#define CSEM_CSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3105#define CSEM_CSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3106#define CSEM_CSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3107#define CSEM_CSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3108#define CSEM_CSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3109#define DBG_DBG_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3110#define DBG_DBG_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3111#define DBG_DBG_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3112#define DBG_DBG_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3113#define DBG_DBG_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3114#define DBG_DBG_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3115#define DBG_DBG_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3116#define DBG_DBG_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3117#define DMAE_DMAE_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3118#define DMAE_DMAE_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3119#define DMAE_DMAE_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3120#define DMAE_DMAE_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3121#define DMAE_DMAE_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3122#define DMAE_DMAE_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3123#define DMAE_DMAE_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3124#define DMAE_DMAE_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
2450#define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 3125#define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
2451#define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR_SIZE 0 3126#define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR_SIZE 0
2452#define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) 3127#define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
@@ -2455,6 +3130,22 @@
2455#define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 3130#define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
2456#define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) 3131#define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
2457#define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 3132#define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3133#define HC_HC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3134#define HC_HC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3135#define HC_HC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3136#define HC_HC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3137#define HC_HC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3138#define HC_HC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3139#define HC_HC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3140#define HC_HC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3141#define MISC_MISC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3142#define MISC_MISC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3143#define MISC_MISC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3144#define MISC_MISC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3145#define MISC_MISC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3146#define MISC_MISC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3147#define MISC_MISC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3148#define MISC_MISC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
2458#define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0) 3149#define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
2459#define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0 3150#define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
2460#define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0) 3151#define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
@@ -2463,6 +3154,70 @@
2463#define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0 3154#define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
2464#define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0) 3155#define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
2465#define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0 3156#define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3157#define PBF_PBF_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3158#define PBF_PBF_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3159#define PBF_PBF_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3160#define PBF_PBF_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3161#define PBF_PBF_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3162#define PBF_PBF_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3163#define PBF_PBF_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3164#define PBF_PBF_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3165#define PB_PB_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3166#define PB_PB_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3167#define PB_PB_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3168#define PB_PB_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3169#define PB_PB_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3170#define PB_PB_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3171#define PB_PB_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3172#define PB_PB_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3173#define PRS_PRS_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3174#define PRS_PRS_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3175#define PRS_PRS_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3176#define PRS_PRS_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3177#define PRS_PRS_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3178#define PRS_PRS_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3179#define PRS_PRS_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3180#define PRS_PRS_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3181#define PXP2_PXP2_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3182#define PXP2_PXP2_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3183#define PXP2_PXP2_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3184#define PXP2_PXP2_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3185#define PXP2_PXP2_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3186#define PXP2_PXP2_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3187#define PXP2_PXP2_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3188#define PXP2_PXP2_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3189#define PXP_PXP_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3190#define PXP_PXP_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3191#define PXP_PXP_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3192#define PXP_PXP_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3193#define PXP_PXP_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3194#define PXP_PXP_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3195#define PXP_PXP_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3196#define PXP_PXP_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3197#define QM_QM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3198#define QM_QM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3199#define QM_QM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3200#define QM_QM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3201#define QM_QM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3202#define QM_QM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3203#define QM_QM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3204#define QM_QM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3205#define SEM_FAST_SEM_FAST_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3206#define SEM_FAST_SEM_FAST_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3207#define SEM_FAST_SEM_FAST_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3208#define SEM_FAST_SEM_FAST_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3209#define SEM_FAST_SEM_FAST_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3210#define SEM_FAST_SEM_FAST_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3211#define SEM_FAST_SEM_FAST_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3212#define SEM_FAST_SEM_FAST_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3213#define SRC_SRC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3214#define SRC_SRC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3215#define SRC_SRC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3216#define SRC_SRC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3217#define SRC_SRC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3218#define SRC_SRC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3219#define SRC_SRC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3220#define SRC_SRC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
2466#define TCM_TCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 3221#define TCM_TCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
2467#define TCM_TCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0 3222#define TCM_TCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
2468#define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0) 3223#define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
@@ -2471,6 +3226,78 @@
2471#define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0 3226#define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
2472#define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0) 3227#define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
2473#define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0 3228#define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3229#define TM_TM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3230#define TM_TM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3231#define TM_TM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3232#define TM_TM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3233#define TM_TM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3234#define TM_TM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3235#define TM_TM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3236#define TM_TM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3237#define TSDM_TSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3238#define TSDM_TSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3239#define TSDM_TSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3240#define TSDM_TSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3241#define TSDM_TSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3242#define TSDM_TSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3243#define TSDM_TSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3244#define TSDM_TSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3245#define TSEM_TSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3246#define TSEM_TSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3247#define TSEM_TSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3248#define TSEM_TSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3249#define TSEM_TSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3250#define TSEM_TSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3251#define TSEM_TSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3252#define TSEM_TSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3253#define UCM_UCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3254#define UCM_UCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3255#define UCM_UCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3256#define UCM_UCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3257#define UCM_UCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3258#define UCM_UCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3259#define UCM_UCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3260#define UCM_UCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3261#define USDM_USDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3262#define USDM_USDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3263#define USDM_USDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3264#define USDM_USDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3265#define USDM_USDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3266#define USDM_USDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3267#define USDM_USDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3268#define USDM_USDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3269#define USEM_USEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3270#define USEM_USEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3271#define USEM_USEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3272#define USEM_USEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3273#define USEM_USEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3274#define USEM_USEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3275#define USEM_USEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3276#define USEM_USEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3277#define XCM_XCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3278#define XCM_XCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3279#define XCM_XCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3280#define XCM_XCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3281#define XCM_XCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3282#define XCM_XCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3283#define XCM_XCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3284#define XCM_XCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3285#define XSDM_XSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3286#define XSDM_XSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3287#define XSDM_XSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3288#define XSDM_XSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3289#define XSDM_XSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3290#define XSDM_XSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3291#define XSDM_XSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3292#define XSDM_XSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3293#define XSEM_XSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3294#define XSEM_XSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3295#define XSEM_XSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3296#define XSEM_XSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3297#define XSEM_XSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3298#define XSEM_XSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3299#define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3300#define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
2474#define CFC_DEBUG1_REG_WRITE_AC (0x1<<4) 3301#define CFC_DEBUG1_REG_WRITE_AC (0x1<<4)
2475#define CFC_DEBUG1_REG_WRITE_AC_SIZE 4 3302#define CFC_DEBUG1_REG_WRITE_AC_SIZE 4
2476/* [R 1] debug only: This bit indicates wheter indicates that external 3303/* [R 1] debug only: This bit indicates wheter indicates that external
@@ -2483,6 +3310,14 @@
2483 ~dbg_registers_debug_target=0 (internal buffer) */ 3310 ~dbg_registers_debug_target=0 (internal buffer) */
2484#define DBG_REG_WRAP_ON_INT_BUFFER 0xc128 3311#define DBG_REG_WRAP_ON_INT_BUFFER 0xc128
2485#define DBG_REG_WRAP_ON_INT_BUFFER_SIZE 1 3312#define DBG_REG_WRAP_ON_INT_BUFFER_SIZE 1
3313#define QM_QM_PRTY_STS_REG_WRBUFF (0x1<<8)
3314#define QM_QM_PRTY_STS_REG_WRBUFF_SIZE 8
3315#define QM_QM_PRTY_STS_CLR_REG_WRBUFF (0x1<<8)
3316#define QM_QM_PRTY_STS_CLR_REG_WRBUFF_SIZE 8
3317#define QM_QM_PRTY_STS_WR_REG_WRBUFF (0x1<<8)
3318#define QM_QM_PRTY_STS_WR_REG_WRBUFF_SIZE 8
3319#define QM_QM_PRTY_MASK_REG_WRBUFF (0x1<<8)
3320#define QM_QM_PRTY_MASK_REG_WRBUFF_SIZE 8
2486/* [RW 32] Wrr weights */ 3321/* [RW 32] Wrr weights */
2487#define QM_REG_WRRWEIGHTS_0 0x16880c 3322#define QM_REG_WRRWEIGHTS_0 0x16880c
2488#define QM_REG_WRRWEIGHTS_0_SIZE 1 3323#define QM_REG_WRRWEIGHTS_0_SIZE 1
@@ -2531,20 +3366,67 @@
2531/* [RW 32] Wrr weights */ 3366/* [RW 32] Wrr weights */
2532#define QM_REG_WRRWEIGHTS_9 0x168848 3367#define QM_REG_WRRWEIGHTS_9 0x168848
2533#define QM_REG_WRRWEIGHTS_9_SIZE 1 3368#define QM_REG_WRRWEIGHTS_9_SIZE 1
2534/* [RW 22] Number of free element in the free list of T2 entries - port 0. */ 3369/* [RW 32] Wrr weights */
3370#define QM_REG_WRRWEIGHTS_16 0x16e000
3371#define QM_REG_WRRWEIGHTS_16_SIZE 1
3372/* [RW 32] Wrr weights */
3373#define QM_REG_WRRWEIGHTS_17 0x16e004
3374#define QM_REG_WRRWEIGHTS_17_SIZE 1
3375/* [RW 32] Wrr weights */
3376#define QM_REG_WRRWEIGHTS_18 0x16e008
3377#define QM_REG_WRRWEIGHTS_18_SIZE 1
3378/* [RW 32] Wrr weights */
3379#define QM_REG_WRRWEIGHTS_19 0x16e00c
3380#define QM_REG_WRRWEIGHTS_19_SIZE 1
3381/* [RW 32] Wrr weights */
3382#define QM_REG_WRRWEIGHTS_20 0x16e010
3383#define QM_REG_WRRWEIGHTS_20_SIZE 1
3384/* [RW 32] Wrr weights */
3385#define QM_REG_WRRWEIGHTS_21 0x16e014
3386#define QM_REG_WRRWEIGHTS_21_SIZE 1
3387/* [RW 32] Wrr weights */
3388#define QM_REG_WRRWEIGHTS_22 0x16e018
3389#define QM_REG_WRRWEIGHTS_22_SIZE 1
3390/* [RW 32] Wrr weights */
3391#define QM_REG_WRRWEIGHTS_23 0x16e01c
3392#define QM_REG_WRRWEIGHTS_23_SIZE 1
3393/* [RW 32] Wrr weights */
3394#define QM_REG_WRRWEIGHTS_24 0x16e020
3395#define QM_REG_WRRWEIGHTS_24_SIZE 1
3396/* [RW 32] Wrr weights */
3397#define QM_REG_WRRWEIGHTS_25 0x16e024
3398#define QM_REG_WRRWEIGHTS_25_SIZE 1
3399/* [RW 32] Wrr weights */
3400#define QM_REG_WRRWEIGHTS_26 0x16e028
3401#define QM_REG_WRRWEIGHTS_26_SIZE 1
3402/* [RW 32] Wrr weights */
3403#define QM_REG_WRRWEIGHTS_27 0x16e02c
3404#define QM_REG_WRRWEIGHTS_27_SIZE 1
3405/* [RW 32] Wrr weights */
3406#define QM_REG_WRRWEIGHTS_28 0x16e030
3407#define QM_REG_WRRWEIGHTS_28_SIZE 1
3408/* [RW 32] Wrr weights */
3409#define QM_REG_WRRWEIGHTS_29 0x16e034
3410#define QM_REG_WRRWEIGHTS_29_SIZE 1
3411/* [RW 32] Wrr weights */
3412#define QM_REG_WRRWEIGHTS_30 0x16e038
3413#define QM_REG_WRRWEIGHTS_30_SIZE 1
3414/* [RW 32] Wrr weights */
3415#define QM_REG_WRRWEIGHTS_31 0x16e03c
3416#define QM_REG_WRRWEIGHTS_31_SIZE 1
2535#define SRC_REG_COUNTFREE0 0x40500 3417#define SRC_REG_COUNTFREE0 0x40500
2536/* [WB 64] First free element in the free list of T2 entries - port 0. */ 3418/* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
3419 ports. If set the searcher support 8 functions. */
3420#define SRC_REG_E1HMF_ENABLE 0x404cc
2537#define SRC_REG_FIRSTFREE0 0x40510 3421#define SRC_REG_FIRSTFREE0 0x40510
2538#define SRC_REG_KEYRSS0_0 0x40408 3422#define SRC_REG_KEYRSS0_0 0x40408
3423#define SRC_REG_KEYRSS0_7 0x40424
2539#define SRC_REG_KEYRSS1_9 0x40454 3424#define SRC_REG_KEYRSS1_9 0x40454
2540/* [WB 64] Last free element in the free list of T2 entries - port 0. */
2541#define SRC_REG_LASTFREE0 0x40530 3425#define SRC_REG_LASTFREE0 0x40530
2542/* [RW 5] The number of hash bits used for the search (h); Values can be 8
2543 to 24. */
2544#define SRC_REG_NUMBER_HASH_BITS0 0x40400 3426#define SRC_REG_NUMBER_HASH_BITS0 0x40400
2545/* [RW 1] Reset internal state machines. */ 3427/* [RW 1] Reset internal state machines. */
2546#define SRC_REG_SOFT_RST 0x4049c 3428#define SRC_REG_SOFT_RST 0x4049c
2547/* [R 1] Interrupt register #0 read */ 3429/* [R 3] Interrupt register #0 read */
2548#define SRC_REG_SRC_INT_STS 0x404ac 3430#define SRC_REG_SRC_INT_STS 0x404ac
2549/* [RW 3] Parity mask register #0 read/write */ 3431/* [RW 3] Parity mask register #0 read/write */
2550#define SRC_REG_SRC_PRTY_MASK 0x404c8 3432#define SRC_REG_SRC_PRTY_MASK 0x404c8
@@ -2637,11 +3519,14 @@
2637 weight 8 (the most prioritised); 1 stands for weight 1(least 3519 weight 8 (the most prioritised); 1 stands for weight 1(least
2638 prioritised); 2 stands for weight 2; tc. */ 3520 prioritised); 2 stands for weight 2; tc. */
2639#define TCM_REG_PBF_WEIGHT 0x500b4 3521#define TCM_REG_PBF_WEIGHT 0x500b4
2640/* [RW 6] The physical queue number 0 per port index. */
2641#define TCM_REG_PHYS_QNUM0_0 0x500e0 3522#define TCM_REG_PHYS_QNUM0_0 0x500e0
2642#define TCM_REG_PHYS_QNUM0_1 0x500e4 3523#define TCM_REG_PHYS_QNUM0_1 0x500e4
2643/* [RW 6] The physical queue number 1 per port index. */
2644#define TCM_REG_PHYS_QNUM1_0 0x500e8 3524#define TCM_REG_PHYS_QNUM1_0 0x500e8
3525#define TCM_REG_PHYS_QNUM1_1 0x500ec
3526#define TCM_REG_PHYS_QNUM2_0 0x500f0
3527#define TCM_REG_PHYS_QNUM2_1 0x500f4
3528#define TCM_REG_PHYS_QNUM3_0 0x500f8
3529#define TCM_REG_PHYS_QNUM3_1 0x500fc
2645/* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded; 3530/* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
2646 acknowledge output is deasserted; all other signals are treated as usual; 3531 acknowledge output is deasserted; all other signals are treated as usual;
2647 if 1 - normal activity. */ 3532 if 1 - normal activity. */
@@ -2670,6 +3555,8 @@
2670#define TCM_REG_TCM_INT_MASK 0x501dc 3555#define TCM_REG_TCM_INT_MASK 0x501dc
2671/* [R 11] Interrupt register #0 read */ 3556/* [R 11] Interrupt register #0 read */
2672#define TCM_REG_TCM_INT_STS 0x501d0 3557#define TCM_REG_TCM_INT_STS 0x501d0
3558/* [R 27] Parity register #0 read */
3559#define TCM_REG_TCM_PRTY_STS 0x501e0
2673/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS 3560/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
2674 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 3561 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
2675 Is used to determine the number of the AG context REG-pairs written back; 3562 Is used to determine the number of the AG context REG-pairs written back;
@@ -2729,6 +3616,7 @@
2729 mechanism. The fields are: [5:0] - length of the message; 15:6] - message 3616 mechanism. The fields are: [5:0] - length of the message; 15:6] - message
2730 pointer; 20:16] - next pointer. */ 3617 pointer; 20:16] - next pointer. */
2731#define TCM_REG_XX_DESCR_TABLE 0x50280 3618#define TCM_REG_XX_DESCR_TABLE 0x50280
3619#define TCM_REG_XX_DESCR_TABLE_SIZE 32
2732/* [R 6] Use to read the value of XX protection Free counter. */ 3620/* [R 6] Use to read the value of XX protection Free counter. */
2733#define TCM_REG_XX_FREE 0x50178 3621#define TCM_REG_XX_FREE 0x50178
2734/* [RW 6] Initial value for the credit counter; responsible for fulfilling 3622/* [RW 6] Initial value for the credit counter; responsible for fulfilling
@@ -2780,7 +3668,7 @@
2780/* [RW 4] Load value for expiration credit cnt. CFC max number of 3668/* [RW 4] Load value for expiration credit cnt. CFC max number of
2781 outstanding load requests for timers (expiration) context loading. */ 3669 outstanding load requests for timers (expiration) context loading. */
2782#define TM_REG_EXP_CRDCNT_VAL 0x164238 3670#define TM_REG_EXP_CRDCNT_VAL 0x164238
2783/* [RW 18] Linear0 Max active cid. */ 3671/* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
2784#define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048 3672#define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
2785/* [WB 64] Linear0 phy address. */ 3673/* [WB 64] Linear0 phy address. */
2786#define TM_REG_LIN0_PHY_ADDR 0x164270 3674#define TM_REG_LIN0_PHY_ADDR 0x164270
@@ -2804,6 +3692,21 @@
2804#define TM_REG_TM_INT_STS 0x1640f0 3692#define TM_REG_TM_INT_STS 0x1640f0
2805/* [RW 8] The event id for aggregated interrupt 0 */ 3693/* [RW 8] The event id for aggregated interrupt 0 */
2806#define TSDM_REG_AGG_INT_EVENT_0 0x42038 3694#define TSDM_REG_AGG_INT_EVENT_0 0x42038
3695#define TSDM_REG_AGG_INT_EVENT_2 0x42040
3696#define TSDM_REG_AGG_INT_EVENT_20 0x42088
3697#define TSDM_REG_AGG_INT_EVENT_21 0x4208c
3698#define TSDM_REG_AGG_INT_EVENT_22 0x42090
3699#define TSDM_REG_AGG_INT_EVENT_23 0x42094
3700#define TSDM_REG_AGG_INT_EVENT_24 0x42098
3701#define TSDM_REG_AGG_INT_EVENT_25 0x4209c
3702#define TSDM_REG_AGG_INT_EVENT_26 0x420a0
3703#define TSDM_REG_AGG_INT_EVENT_27 0x420a4
3704#define TSDM_REG_AGG_INT_EVENT_28 0x420a8
3705#define TSDM_REG_AGG_INT_EVENT_29 0x420ac
3706#define TSDM_REG_AGG_INT_EVENT_3 0x42044
3707#define TSDM_REG_AGG_INT_EVENT_30 0x420b0
3708#define TSDM_REG_AGG_INT_EVENT_31 0x420b4
3709#define TSDM_REG_AGG_INT_EVENT_4 0x42048
2807/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 3710/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
2808#define TSDM_REG_CFC_RSP_START_ADDR 0x42008 3711#define TSDM_REG_CFC_RSP_START_ADDR 0x42008
2809/* [RW 16] The maximum value of the competion counter #0 */ 3712/* [RW 16] The maximum value of the competion counter #0 */
@@ -2868,6 +3771,9 @@
2868/* [RW 32] Interrupt mask register #0 read/write */ 3771/* [RW 32] Interrupt mask register #0 read/write */
2869#define TSDM_REG_TSDM_INT_MASK_0 0x4229c 3772#define TSDM_REG_TSDM_INT_MASK_0 0x4229c
2870#define TSDM_REG_TSDM_INT_MASK_1 0x422ac 3773#define TSDM_REG_TSDM_INT_MASK_1 0x422ac
3774/* [R 32] Interrupt register #0 read */
3775#define TSDM_REG_TSDM_INT_STS_0 0x42290
3776#define TSDM_REG_TSDM_INT_STS_1 0x422a0
2871/* [RW 11] Parity mask register #0 read/write */ 3777/* [RW 11] Parity mask register #0 read/write */
2872#define TSDM_REG_TSDM_PRTY_MASK 0x422bc 3778#define TSDM_REG_TSDM_PRTY_MASK 0x422bc
2873/* [R 11] Parity register #0 read */ 3779/* [R 11] Parity register #0 read */
@@ -2908,9 +3814,8 @@
2908#define TSEM_REG_ENABLE_OUT 0x1800a8 3814#define TSEM_REG_ENABLE_OUT 0x1800a8
2909/* [RW 32] This address space contains all registers and memories that are 3815/* [RW 32] This address space contains all registers and memories that are
2910 placed in SEM_FAST block. The SEM_FAST registers are described in 3816 placed in SEM_FAST block. The SEM_FAST registers are described in
2911 appendix B. In order to access the SEM_FAST registers the base address 3817 appendix B. In order to access the sem_fast registers the base address
2912 TSEM_REGISTERS_FAST_MEMORY (Offset: 0x1a0000) should be added to each 3818 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
2913 SEM_FAST register offset. */
2914#define TSEM_REG_FAST_MEMORY 0x1a0000 3819#define TSEM_REG_FAST_MEMORY 0x1a0000
2915/* [RW 1] Disables input messages from FIC0 May be updated during run_time 3820/* [RW 1] Disables input messages from FIC0 May be updated during run_time
2916 by the microcode */ 3821 by the microcode */
@@ -2921,6 +3826,7 @@
2921/* [RW 15] Interrupt table Read and write access to it is not possible in 3826/* [RW 15] Interrupt table Read and write access to it is not possible in
2922 the middle of the work */ 3827 the middle of the work */
2923#define TSEM_REG_INT_TABLE 0x180400 3828#define TSEM_REG_INT_TABLE 0x180400
3829#define TSEM_REG_INT_TABLE_SIZE 256
2924/* [ST 24] Statistics register. The number of messages that entered through 3830/* [ST 24] Statistics register. The number of messages that entered through
2925 FIC0 */ 3831 FIC0 */
2926#define TSEM_REG_MSG_NUM_FIC0 0x180000 3832#define TSEM_REG_MSG_NUM_FIC0 0x180000
@@ -2993,6 +3899,9 @@
2993/* [RW 32] Interrupt mask register #0 read/write */ 3899/* [RW 32] Interrupt mask register #0 read/write */
2994#define TSEM_REG_TSEM_INT_MASK_0 0x180100 3900#define TSEM_REG_TSEM_INT_MASK_0 0x180100
2995#define TSEM_REG_TSEM_INT_MASK_1 0x180110 3901#define TSEM_REG_TSEM_INT_MASK_1 0x180110
3902/* [R 32] Interrupt register #0 read */
3903#define TSEM_REG_TSEM_INT_STS_0 0x1800f4
3904#define TSEM_REG_TSEM_INT_STS_1 0x180104
2996/* [RW 32] Parity mask register #0 read/write */ 3905/* [RW 32] Parity mask register #0 read/write */
2997#define TSEM_REG_TSEM_PRTY_MASK_0 0x180120 3906#define TSEM_REG_TSEM_PRTY_MASK_0 0x180120
2998#define TSEM_REG_TSEM_PRTY_MASK_1 0x180130 3907#define TSEM_REG_TSEM_PRTY_MASK_1 0x180130
@@ -3088,12 +3997,15 @@
3088#define UCM_REG_N_SM_CTX_LD_2 0xe005c 3997#define UCM_REG_N_SM_CTX_LD_2 0xe005c
3089#define UCM_REG_N_SM_CTX_LD_3 0xe0060 3998#define UCM_REG_N_SM_CTX_LD_3 0xe0060
3090#define UCM_REG_N_SM_CTX_LD_4 0xe0064 3999#define UCM_REG_N_SM_CTX_LD_4 0xe0064
3091/* [RW 6] The physical queue number 0 per port index (CID[23]) */ 4000#define UCM_REG_N_SM_CTX_LD_5 0xe0068
3092#define UCM_REG_PHYS_QNUM0_0 0xe0110 4001#define UCM_REG_PHYS_QNUM0_0 0xe0110
3093#define UCM_REG_PHYS_QNUM0_1 0xe0114 4002#define UCM_REG_PHYS_QNUM0_1 0xe0114
3094/* [RW 6] The physical queue number 1 per port index (CID[23]) */
3095#define UCM_REG_PHYS_QNUM1_0 0xe0118 4003#define UCM_REG_PHYS_QNUM1_0 0xe0118
3096#define UCM_REG_PHYS_QNUM1_1 0xe011c 4004#define UCM_REG_PHYS_QNUM1_1 0xe011c
4005#define UCM_REG_PHYS_QNUM2_0 0xe0120
4006#define UCM_REG_PHYS_QNUM2_1 0xe0124
4007#define UCM_REG_PHYS_QNUM3_0 0xe0128
4008#define UCM_REG_PHYS_QNUM3_1 0xe012c
3097/* [RW 8] The Event ID for Timers formatting in case of stop done. */ 4009/* [RW 8] The Event ID for Timers formatting in case of stop done. */
3098#define UCM_REG_STOP_EVNT_ID 0xe00ac 4010#define UCM_REG_STOP_EVNT_ID 0xe00ac
3099/* [RC 1] Set when the message length mismatch (relative to last indication) 4011/* [RC 1] Set when the message length mismatch (relative to last indication)
@@ -3132,6 +4044,8 @@
3132#define UCM_REG_UCM_INT_MASK 0xe01d4 4044#define UCM_REG_UCM_INT_MASK 0xe01d4
3133/* [R 11] Interrupt register #0 read */ 4045/* [R 11] Interrupt register #0 read */
3134#define UCM_REG_UCM_INT_STS 0xe01c8 4046#define UCM_REG_UCM_INT_STS 0xe01c8
4047/* [R 27] Parity register #0 read */
4048#define UCM_REG_UCM_PRTY_STS 0xe01d8
3135/* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS 4049/* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
3136 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 4050 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
3137 Is used to determine the number of the AG context REG-pairs written back; 4051 Is used to determine the number of the AG context REG-pairs written back;
@@ -3189,6 +4103,7 @@
3189 mechanism. The fields are:[5:0] - message length; 14:6] - message 4103 mechanism. The fields are:[5:0] - message length; 14:6] - message
3190 pointer; 19:15] - next pointer. */ 4104 pointer; 19:15] - next pointer. */
3191#define UCM_REG_XX_DESCR_TABLE 0xe0280 4105#define UCM_REG_XX_DESCR_TABLE 0xe0280
4106#define UCM_REG_XX_DESCR_TABLE_SIZE 32
3192/* [R 6] Use to read the XX protection Free counter. */ 4107/* [R 6] Use to read the XX protection Free counter. */
3193#define UCM_REG_XX_FREE 0xe016c 4108#define UCM_REG_XX_FREE 0xe016c
3194/* [RW 6] Initial value for the credit counter; responsible for fulfilling 4109/* [RW 6] Initial value for the credit counter; responsible for fulfilling
@@ -3218,6 +4133,21 @@
3218#define USDM_REG_AGG_INT_EVENT_17 0xc407c 4133#define USDM_REG_AGG_INT_EVENT_17 0xc407c
3219#define USDM_REG_AGG_INT_EVENT_18 0xc4080 4134#define USDM_REG_AGG_INT_EVENT_18 0xc4080
3220#define USDM_REG_AGG_INT_EVENT_19 0xc4084 4135#define USDM_REG_AGG_INT_EVENT_19 0xc4084
4136#define USDM_REG_AGG_INT_EVENT_2 0xc4040
4137#define USDM_REG_AGG_INT_EVENT_20 0xc4088
4138#define USDM_REG_AGG_INT_EVENT_21 0xc408c
4139#define USDM_REG_AGG_INT_EVENT_22 0xc4090
4140#define USDM_REG_AGG_INT_EVENT_23 0xc4094
4141#define USDM_REG_AGG_INT_EVENT_24 0xc4098
4142#define USDM_REG_AGG_INT_EVENT_25 0xc409c
4143#define USDM_REG_AGG_INT_EVENT_26 0xc40a0
4144#define USDM_REG_AGG_INT_EVENT_27 0xc40a4
4145#define USDM_REG_AGG_INT_EVENT_28 0xc40a8
4146#define USDM_REG_AGG_INT_EVENT_29 0xc40ac
4147#define USDM_REG_AGG_INT_EVENT_3 0xc4044
4148#define USDM_REG_AGG_INT_EVENT_30 0xc40b0
4149#define USDM_REG_AGG_INT_EVENT_31 0xc40b4
4150#define USDM_REG_AGG_INT_EVENT_4 0xc4048
3221/* [RW 1] For each aggregated interrupt index whether the mode is normal (0) 4151/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
3222 or auto-mask-mode (1) */ 4152 or auto-mask-mode (1) */
3223#define USDM_REG_AGG_INT_MODE_0 0xc41b8 4153#define USDM_REG_AGG_INT_MODE_0 0xc41b8
@@ -3298,6 +4228,9 @@
3298/* [RW 32] Interrupt mask register #0 read/write */ 4228/* [RW 32] Interrupt mask register #0 read/write */
3299#define USDM_REG_USDM_INT_MASK_0 0xc42a0 4229#define USDM_REG_USDM_INT_MASK_0 0xc42a0
3300#define USDM_REG_USDM_INT_MASK_1 0xc42b0 4230#define USDM_REG_USDM_INT_MASK_1 0xc42b0
4231/* [R 32] Interrupt register #0 read */
4232#define USDM_REG_USDM_INT_STS_0 0xc4294
4233#define USDM_REG_USDM_INT_STS_1 0xc42a4
3301/* [RW 11] Parity mask register #0 read/write */ 4234/* [RW 11] Parity mask register #0 read/write */
3302#define USDM_REG_USDM_PRTY_MASK 0xc42c0 4235#define USDM_REG_USDM_PRTY_MASK 0xc42c0
3303/* [R 11] Parity register #0 read */ 4236/* [R 11] Parity register #0 read */
@@ -3338,9 +4271,8 @@
3338#define USEM_REG_ENABLE_OUT 0x3000a8 4271#define USEM_REG_ENABLE_OUT 0x3000a8
3339/* [RW 32] This address space contains all registers and memories that are 4272/* [RW 32] This address space contains all registers and memories that are
3340 placed in SEM_FAST block. The SEM_FAST registers are described in 4273 placed in SEM_FAST block. The SEM_FAST registers are described in
3341 appendix B. In order to access the SEM_FAST registers... the base address 4274 appendix B. In order to access the sem_fast registers the base address
3342 USEM_REGISTERS_FAST_MEMORY (Offset: 0x320000) should be added to each 4275 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
3343 SEM_FAST register offset. */
3344#define USEM_REG_FAST_MEMORY 0x320000 4276#define USEM_REG_FAST_MEMORY 0x320000
3345/* [RW 1] Disables input messages from FIC0 May be updated during run_time 4277/* [RW 1] Disables input messages from FIC0 May be updated during run_time
3346 by the microcode */ 4278 by the microcode */
@@ -3351,6 +4283,7 @@
3351/* [RW 15] Interrupt table Read and write access to it is not possible in 4283/* [RW 15] Interrupt table Read and write access to it is not possible in
3352 the middle of the work */ 4284 the middle of the work */
3353#define USEM_REG_INT_TABLE 0x300400 4285#define USEM_REG_INT_TABLE 0x300400
4286#define USEM_REG_INT_TABLE_SIZE 256
3354/* [ST 24] Statistics register. The number of messages that entered through 4287/* [ST 24] Statistics register. The number of messages that entered through
3355 FIC0 */ 4288 FIC0 */
3356#define USEM_REG_MSG_NUM_FIC0 0x300000 4289#define USEM_REG_MSG_NUM_FIC0 0x300000
@@ -3423,6 +4356,9 @@
3423/* [RW 32] Interrupt mask register #0 read/write */ 4356/* [RW 32] Interrupt mask register #0 read/write */
3424#define USEM_REG_USEM_INT_MASK_0 0x300110 4357#define USEM_REG_USEM_INT_MASK_0 0x300110
3425#define USEM_REG_USEM_INT_MASK_1 0x300120 4358#define USEM_REG_USEM_INT_MASK_1 0x300120
4359/* [R 32] Interrupt register #0 read */
4360#define USEM_REG_USEM_INT_STS_0 0x300104
4361#define USEM_REG_USEM_INT_STS_1 0x300114
3426/* [RW 32] Parity mask register #0 read/write */ 4362/* [RW 32] Parity mask register #0 read/write */
3427#define USEM_REG_USEM_PRTY_MASK_0 0x300130 4363#define USEM_REG_USEM_PRTY_MASK_0 0x300130
3428#define USEM_REG_USEM_PRTY_MASK_1 0x300140 4364#define USEM_REG_USEM_PRTY_MASK_1 0x300140
@@ -3491,11 +4427,8 @@
3491 writes the initial credit value; read returns the current value of the 4427 writes the initial credit value; read returns the current value of the
3492 credit counter. Must be initialized to 64 at start-up. */ 4428 credit counter. Must be initialized to 64 at start-up. */
3493#define XCM_REG_FIC1_INIT_CRD 0x20410 4429#define XCM_REG_FIC1_INIT_CRD 0x20410
3494/* [RW 8] The maximum delayed ACK counter value.Must be at least 2. Per port
3495 value. */
3496#define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118 4430#define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118
3497#define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c 4431#define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c
3498/* [RW 28] The delayed ACK timeout in ticks. Per port value. */
3499#define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108 4432#define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108
3500#define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c 4433#define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c
3501/* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1 4434/* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
@@ -3545,6 +4478,7 @@
3545#define XCM_REG_N_SM_CTX_LD_2 0x20068 4478#define XCM_REG_N_SM_CTX_LD_2 0x20068
3546#define XCM_REG_N_SM_CTX_LD_3 0x2006c 4479#define XCM_REG_N_SM_CTX_LD_3 0x2006c
3547#define XCM_REG_N_SM_CTX_LD_4 0x20070 4480#define XCM_REG_N_SM_CTX_LD_4 0x20070
4481#define XCM_REG_N_SM_CTX_LD_5 0x20074
3548/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; 4482/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
3549 acknowledge output is deasserted; all other signals are treated as usual; 4483 acknowledge output is deasserted; all other signals are treated as usual;
3550 if 1 - normal activity. */ 4484 if 1 - normal activity. */
@@ -3556,6 +4490,8 @@
3556 weight 8 (the most prioritised); 1 stands for weight 1(least 4490 weight 8 (the most prioritised); 1 stands for weight 1(least
3557 prioritised); 2 stands for weight 2; tc. */ 4491 prioritised); 2 stands for weight 2; tc. */
3558#define XCM_REG_PBF_WEIGHT 0x200d0 4492#define XCM_REG_PBF_WEIGHT 0x200d0
4493#define XCM_REG_PHYS_QNUM3_0 0x20100
4494#define XCM_REG_PHYS_QNUM3_1 0x20104
3559/* [RW 8] The Event ID for Timers formatting in case of stop done. */ 4495/* [RW 8] The Event ID for Timers formatting in case of stop done. */
3560#define XCM_REG_STOP_EVNT_ID 0x200b8 4496#define XCM_REG_STOP_EVNT_ID 0x200b8
3561/* [RC 1] Set at message length mismatch (relative to last indication) at 4497/* [RC 1] Set at message length mismatch (relative to last indication) at
@@ -3603,53 +4539,17 @@
3603 weight 8 (the most prioritised); 1 stands for weight 1(least 4539 weight 8 (the most prioritised); 1 stands for weight 1(least
3604 prioritised); 2 stands for weight 2; tc. */ 4540 prioritised); 2 stands for weight 2; tc. */
3605#define XCM_REG_USEM_WEIGHT 0x200c8 4541#define XCM_REG_USEM_WEIGHT 0x200c8
3606/* [RW 2] DA counter command; used in case of window update doorbell.The
3607 first index stands for the value DaEnable of that connection. The second
3608 index stands for port number. */
3609#define XCM_REG_WU_DA_CNT_CMD00 0x201d4 4542#define XCM_REG_WU_DA_CNT_CMD00 0x201d4
3610/* [RW 2] DA counter command; used in case of window update doorbell.The
3611 first index stands for the value DaEnable of that connection. The second
3612 index stands for port number. */
3613#define XCM_REG_WU_DA_CNT_CMD01 0x201d8 4543#define XCM_REG_WU_DA_CNT_CMD01 0x201d8
3614/* [RW 2] DA counter command; used in case of window update doorbell.The
3615 first index stands for the value DaEnable of that connection. The second
3616 index stands for port number. */
3617#define XCM_REG_WU_DA_CNT_CMD10 0x201dc 4544#define XCM_REG_WU_DA_CNT_CMD10 0x201dc
3618/* [RW 2] DA counter command; used in case of window update doorbell.The
3619 first index stands for the value DaEnable of that connection. The second
3620 index stands for port number. */
3621#define XCM_REG_WU_DA_CNT_CMD11 0x201e0 4545#define XCM_REG_WU_DA_CNT_CMD11 0x201e0
3622/* [RW 8] DA counter update value used in case of window update doorbell.The
3623 first index stands for the value DaEnable of that connection. The second
3624 index stands for port number. */
3625#define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4 4546#define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4
3626/* [RW 8] DA counter update value; used in case of window update
3627 doorbell.The first index stands for the value DaEnable of that
3628 connection. The second index stands for port number. */
3629#define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8 4547#define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8
3630/* [RW 8] DA counter update value; used in case of window update
3631 doorbell.The first index stands for the value DaEnable of that
3632 connection. The second index stands for port number. */
3633#define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec 4548#define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec
3634/* [RW 8] DA counter update value; used in case of window update
3635 doorbell.The first index stands for the value DaEnable of that
3636 connection. The second index stands for port number. */
3637#define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0 4549#define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0
3638/* [RW 1] DA timer command; used in case of window update doorbell.The first
3639 index stands for the value DaEnable of that connection. The second index
3640 stands for port number. */
3641#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4 4550#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4
3642/* [RW 1] DA timer command; used in case of window update doorbell.The first
3643 index stands for the value DaEnable of that connection. The second index
3644 stands for port number. */
3645#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8 4551#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8
3646/* [RW 1] DA timer command; used in case of window update doorbell.The first
3647 index stands for the value DaEnable of that connection. The second index
3648 stands for port number. */
3649#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc 4552#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc
3650/* [RW 1] DA timer command; used in case of window update doorbell.The first
3651 index stands for the value DaEnable of that connection. The second index
3652 stands for port number. */
3653#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0 4553#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0
3654/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; 4554/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
3655 acknowledge output is deasserted; all other signals are treated as usual; 4555 acknowledge output is deasserted; all other signals are treated as usual;
@@ -3659,6 +4559,8 @@
3659#define XCM_REG_XCM_INT_MASK 0x202b4 4559#define XCM_REG_XCM_INT_MASK 0x202b4
3660/* [R 14] Interrupt register #0 read */ 4560/* [R 14] Interrupt register #0 read */
3661#define XCM_REG_XCM_INT_STS 0x202a8 4561#define XCM_REG_XCM_INT_STS 0x202a8
4562/* [R 30] Parity register #0 read */
4563#define XCM_REG_XCM_PRTY_STS 0x202b8
3662/* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS 4564/* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
3663 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 4565 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
3664 Is used to determine the number of the AG context REG-pairs written back; 4566 Is used to determine the number of the AG context REG-pairs written back;
@@ -3715,6 +4617,7 @@
3715 mechanism. The fields are: [5:0] - message length; 11:6] - message 4617 mechanism. The fields are: [5:0] - message length; 11:6] - message
3716 pointer; 16:12] - next pointer. */ 4618 pointer; 16:12] - next pointer. */
3717#define XCM_REG_XX_DESCR_TABLE 0x20480 4619#define XCM_REG_XX_DESCR_TABLE 0x20480
4620#define XCM_REG_XX_DESCR_TABLE_SIZE 32
3718/* [R 6] Used to read the XX protection Free counter. */ 4621/* [R 6] Used to read the XX protection Free counter. */
3719#define XCM_REG_XX_FREE 0x20240 4622#define XCM_REG_XX_FREE 0x20240
3720/* [RW 6] Initial value for the credit counter; responsible for fulfilling 4623/* [RW 6] Initial value for the credit counter; responsible for fulfilling
@@ -3728,7 +4631,7 @@
3728#define XCM_REG_XX_MSG_NUM 0x20428 4631#define XCM_REG_XX_MSG_NUM 0x20428
3729/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 4632/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
3730#define XCM_REG_XX_OVFL_EVNT_ID 0x20058 4633#define XCM_REG_XX_OVFL_EVNT_ID 0x20058
3731/* [RW 15] Indirect access to the XX table of the XX protection mechanism. 4634/* [RW 16] Indirect access to the XX table of the XX protection mechanism.
3732 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] - 4635 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
3733 header pointer. */ 4636 header pointer. */
3734#define XCM_REG_XX_TABLE 0x20500 4637#define XCM_REG_XX_TABLE 0x20500
@@ -3745,6 +4648,9 @@
3745#define XSDM_REG_AGG_INT_EVENT_17 0x16607c 4648#define XSDM_REG_AGG_INT_EVENT_17 0x16607c
3746#define XSDM_REG_AGG_INT_EVENT_18 0x166080 4649#define XSDM_REG_AGG_INT_EVENT_18 0x166080
3747#define XSDM_REG_AGG_INT_EVENT_19 0x166084 4650#define XSDM_REG_AGG_INT_EVENT_19 0x166084
4651#define XSDM_REG_AGG_INT_EVENT_10 0x166060
4652#define XSDM_REG_AGG_INT_EVENT_11 0x166064
4653#define XSDM_REG_AGG_INT_EVENT_12 0x166068
3748#define XSDM_REG_AGG_INT_EVENT_2 0x166040 4654#define XSDM_REG_AGG_INT_EVENT_2 0x166040
3749#define XSDM_REG_AGG_INT_EVENT_20 0x166088 4655#define XSDM_REG_AGG_INT_EVENT_20 0x166088
3750#define XSDM_REG_AGG_INT_EVENT_21 0x16608c 4656#define XSDM_REG_AGG_INT_EVENT_21 0x16608c
@@ -3756,6 +4662,15 @@
3756#define XSDM_REG_AGG_INT_EVENT_27 0x1660a4 4662#define XSDM_REG_AGG_INT_EVENT_27 0x1660a4
3757#define XSDM_REG_AGG_INT_EVENT_28 0x1660a8 4663#define XSDM_REG_AGG_INT_EVENT_28 0x1660a8
3758#define XSDM_REG_AGG_INT_EVENT_29 0x1660ac 4664#define XSDM_REG_AGG_INT_EVENT_29 0x1660ac
4665#define XSDM_REG_AGG_INT_EVENT_3 0x166044
4666#define XSDM_REG_AGG_INT_EVENT_30 0x1660b0
4667#define XSDM_REG_AGG_INT_EVENT_31 0x1660b4
4668#define XSDM_REG_AGG_INT_EVENT_4 0x166048
4669#define XSDM_REG_AGG_INT_EVENT_5 0x16604c
4670#define XSDM_REG_AGG_INT_EVENT_6 0x166050
4671#define XSDM_REG_AGG_INT_EVENT_7 0x166054
4672#define XSDM_REG_AGG_INT_EVENT_8 0x166058
4673#define XSDM_REG_AGG_INT_EVENT_9 0x16605c
3759/* [RW 1] For each aggregated interrupt index whether the mode is normal (0) 4674/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
3760 or auto-mask-mode (1) */ 4675 or auto-mask-mode (1) */
3761#define XSDM_REG_AGG_INT_MODE_0 0x1661b8 4676#define XSDM_REG_AGG_INT_MODE_0 0x1661b8
@@ -3832,6 +4747,9 @@
3832/* [RW 32] Interrupt mask register #0 read/write */ 4747/* [RW 32] Interrupt mask register #0 read/write */
3833#define XSDM_REG_XSDM_INT_MASK_0 0x16629c 4748#define XSDM_REG_XSDM_INT_MASK_0 0x16629c
3834#define XSDM_REG_XSDM_INT_MASK_1 0x1662ac 4749#define XSDM_REG_XSDM_INT_MASK_1 0x1662ac
4750/* [R 32] Interrupt register #0 read */
4751#define XSDM_REG_XSDM_INT_STS_0 0x166290
4752#define XSDM_REG_XSDM_INT_STS_1 0x1662a0
3835/* [RW 11] Parity mask register #0 read/write */ 4753/* [RW 11] Parity mask register #0 read/write */
3836#define XSDM_REG_XSDM_PRTY_MASK 0x1662bc 4754#define XSDM_REG_XSDM_PRTY_MASK 0x1662bc
3837/* [R 11] Parity register #0 read */ 4755/* [R 11] Parity register #0 read */
@@ -3872,9 +4790,8 @@
3872#define XSEM_REG_ENABLE_OUT 0x2800a8 4790#define XSEM_REG_ENABLE_OUT 0x2800a8
3873/* [RW 32] This address space contains all registers and memories that are 4791/* [RW 32] This address space contains all registers and memories that are
3874 placed in SEM_FAST block. The SEM_FAST registers are described in 4792 placed in SEM_FAST block. The SEM_FAST registers are described in
3875 appendix B. In order to access the SEM_FAST registers the base address 4793 appendix B. In order to access the sem_fast registers the base address
3876 XSEM_REGISTERS_FAST_MEMORY (Offset: 0x2a0000) should be added to each 4794 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
3877 SEM_FAST register offset. */
3878#define XSEM_REG_FAST_MEMORY 0x2a0000 4795#define XSEM_REG_FAST_MEMORY 0x2a0000
3879/* [RW 1] Disables input messages from FIC0 May be updated during run_time 4796/* [RW 1] Disables input messages from FIC0 May be updated during run_time
3880 by the microcode */ 4797 by the microcode */
@@ -3885,6 +4802,7 @@
3885/* [RW 15] Interrupt table Read and write access to it is not possible in 4802/* [RW 15] Interrupt table Read and write access to it is not possible in
3886 the middle of the work */ 4803 the middle of the work */
3887#define XSEM_REG_INT_TABLE 0x280400 4804#define XSEM_REG_INT_TABLE 0x280400
4805#define XSEM_REG_INT_TABLE_SIZE 256
3888/* [ST 24] Statistics register. The number of messages that entered through 4806/* [ST 24] Statistics register. The number of messages that entered through
3889 FIC0 */ 4807 FIC0 */
3890#define XSEM_REG_MSG_NUM_FIC0 0x280000 4808#define XSEM_REG_MSG_NUM_FIC0 0x280000
@@ -3957,6 +4875,9 @@
3957/* [RW 32] Interrupt mask register #0 read/write */ 4875/* [RW 32] Interrupt mask register #0 read/write */
3958#define XSEM_REG_XSEM_INT_MASK_0 0x280110 4876#define XSEM_REG_XSEM_INT_MASK_0 0x280110
3959#define XSEM_REG_XSEM_INT_MASK_1 0x280120 4877#define XSEM_REG_XSEM_INT_MASK_1 0x280120
4878/* [R 32] Interrupt register #0 read */
4879#define XSEM_REG_XSEM_INT_STS_0 0x280104
4880#define XSEM_REG_XSEM_INT_STS_1 0x280114
3960/* [RW 32] Parity mask register #0 read/write */ 4881/* [RW 32] Parity mask register #0 read/write */
3961#define XSEM_REG_XSEM_PRTY_MASK_0 0x280130 4882#define XSEM_REG_XSEM_PRTY_MASK_0 0x280130
3962#define XSEM_REG_XSEM_PRTY_MASK_1 0x280140 4883#define XSEM_REG_XSEM_PRTY_MASK_1 0x280140
@@ -3993,10 +4914,14 @@
3993#define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3) 4914#define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
3994#define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3) 4915#define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
3995#define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3) 4916#define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
4917#define EMAC_LED_1000MB_OVERRIDE (1L<<1)
4918#define EMAC_LED_100MB_OVERRIDE (1L<<2)
4919#define EMAC_LED_10MB_OVERRIDE (1L<<3)
4920#define EMAC_LED_2500MB_OVERRIDE (1L<<12)
4921#define EMAC_LED_OVERRIDE (1L<<0)
4922#define EMAC_LED_TRAFFIC (1L<<6)
3996#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26) 4923#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
3997#define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26)
3998#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26) 4924#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
3999#define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26)
4000#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26) 4925#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
4001#define EMAC_MDIO_COMM_DATA (0xffffL<<0) 4926#define EMAC_MDIO_COMM_DATA (0xffffL<<0)
4002#define EMAC_MDIO_COMM_START_BUSY (1L<<29) 4927#define EMAC_MDIO_COMM_START_BUSY (1L<<29)
@@ -4013,6 +4938,7 @@
4013#define EMAC_MODE_PORT_MII (1L<<2) 4938#define EMAC_MODE_PORT_MII (1L<<2)
4014#define EMAC_MODE_PORT_MII_10M (3L<<2) 4939#define EMAC_MODE_PORT_MII_10M (3L<<2)
4015#define EMAC_MODE_RESET (1L<<0) 4940#define EMAC_MODE_RESET (1L<<0)
4941#define EMAC_REG_EMAC_LED 0xc
4016#define EMAC_REG_EMAC_MAC_MATCH 0x10 4942#define EMAC_REG_EMAC_MAC_MATCH 0x10
4017#define EMAC_REG_EMAC_MDIO_COMM 0xac 4943#define EMAC_REG_EMAC_MDIO_COMM 0xac
4018#define EMAC_REG_EMAC_MDIO_MODE 0xb4 4944#define EMAC_REG_EMAC_MDIO_MODE 0xb4
@@ -4030,14 +4956,16 @@
4030#define EMAC_RX_MODE_PROMISCUOUS (1L<<8) 4956#define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
4031#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) 4957#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
4032#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) 4958#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
4033#define EMAC_TX_MODE_RESET (1L<<0) 4959#define MISC_REGISTERS_GPIO_0 0
4034#define MISC_REGISTERS_GPIO_1 1 4960#define MISC_REGISTERS_GPIO_1 1
4035#define MISC_REGISTERS_GPIO_2 2 4961#define MISC_REGISTERS_GPIO_2 2
4036#define MISC_REGISTERS_GPIO_3 3 4962#define MISC_REGISTERS_GPIO_3 3
4037#define MISC_REGISTERS_GPIO_CLR_POS 16 4963#define MISC_REGISTERS_GPIO_CLR_POS 16
4038#define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24) 4964#define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)
4039#define MISC_REGISTERS_GPIO_FLOAT_POS 24 4965#define MISC_REGISTERS_GPIO_FLOAT_POS 24
4966#define MISC_REGISTERS_GPIO_HIGH 1
4040#define MISC_REGISTERS_GPIO_INPUT_HI_Z 2 4967#define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
4968#define MISC_REGISTERS_GPIO_LOW 0
4041#define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1 4969#define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
4042#define MISC_REGISTERS_GPIO_OUTPUT_LOW 0 4970#define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
4043#define MISC_REGISTERS_GPIO_PORT_SHIFT 4 4971#define MISC_REGISTERS_GPIO_PORT_SHIFT 4
@@ -4127,7 +5055,7 @@
4127#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (1<<10) 5055#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (1<<10)
4128#define RESERVED_GENERAL_ATTENTION_BIT_0 0 5056#define RESERVED_GENERAL_ATTENTION_BIT_0 0
4129 5057
4130#define EVEREST_GEN_ATTN_IN_USE_MASK 0x3e0 5058#define EVEREST_GEN_ATTN_IN_USE_MASK 0x3ffe0
4131#define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000 5059#define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
4132 5060
4133#define RESERVED_GENERAL_ATTENTION_BIT_6 6 5061#define RESERVED_GENERAL_ATTENTION_BIT_6 6
@@ -4156,6 +5084,17 @@
4156/* mcp error attention bit */ 5084/* mcp error attention bit */
4157#define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11 5085#define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11
4158 5086
5087/*E1H NIG status sync attention mapped to group 4-7*/
5088#define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12
5089#define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13
5090#define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14
5091#define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15
5092#define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16
5093#define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17
5094#define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18
5095#define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19
5096
5097
4159#define LATCHED_ATTN_RBCR 23 5098#define LATCHED_ATTN_RBCR 23
4160#define LATCHED_ATTN_RBCT 24 5099#define LATCHED_ATTN_RBCT 24
4161#define LATCHED_ATTN_RBCN 25 5100#define LATCHED_ATTN_RBCN 25
@@ -4221,22 +5160,41 @@
4221#define PCICFG_OFFSET 0x2000 5160#define PCICFG_OFFSET 0x2000
4222#define PCICFG_VENDOR_ID_OFFSET 0x00 5161#define PCICFG_VENDOR_ID_OFFSET 0x00
4223#define PCICFG_DEVICE_ID_OFFSET 0x02 5162#define PCICFG_DEVICE_ID_OFFSET 0x02
4224#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c 5163#define PCICFG_COMMAND_OFFSET 0x04
4225#define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e 5164#define PCICFG_STATUS_OFFSET 0x06
4226#define PCICFG_INT_LINE 0x3c 5165#define PCICFG_REVESION_ID 0x08
4227#define PCICFG_INT_PIN 0x3d
4228#define PCICFG_CACHE_LINE_SIZE 0x0c 5166#define PCICFG_CACHE_LINE_SIZE 0x0c
4229#define PCICFG_LATENCY_TIMER 0x0d 5167#define PCICFG_LATENCY_TIMER 0x0d
4230#define PCICFG_REVESION_ID 0x08 5168#define PCICFG_BAR_1_LOW 0x10
4231#define PCICFG_BAR_1_LOW 0x10 5169#define PCICFG_BAR_1_HIGH 0x14
4232#define PCICFG_BAR_1_HIGH 0x14 5170#define PCICFG_BAR_2_LOW 0x18
4233#define PCICFG_BAR_2_LOW 0x18 5171#define PCICFG_BAR_2_HIGH 0x1c
4234#define PCICFG_BAR_2_HIGH 0x1c 5172#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
4235#define PCICFG_GRC_ADDRESS 0x78 5173#define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
4236#define PCICFG_GRC_DATA 0x80 5174#define PCICFG_INT_LINE 0x3c
5175#define PCICFG_INT_PIN 0x3d
5176#define PCICFG_PM_CSR_OFFSET 0x4c
5177#define PCICFG_GRC_ADDRESS 0x78
5178#define PCICFG_GRC_DATA 0x80
4237#define PCICFG_DEVICE_CONTROL 0xb4 5179#define PCICFG_DEVICE_CONTROL 0xb4
4238#define PCICFG_LINK_CONTROL 0xbc 5180#define PCICFG_LINK_CONTROL 0xbc
4239 5181
5182#define PCICFG_COMMAND_IO_SPACE (1<<0)
5183#define PCICFG_COMMAND_MEM_SPACE (1<<1)
5184#define PCICFG_COMMAND_BUS_MASTER (1<<2)
5185#define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
5186#define PCICFG_COMMAND_MWI_CYCLES (1<<4)
5187#define PCICFG_COMMAND_VGA_SNOOP (1<<5)
5188#define PCICFG_COMMAND_PERR_ENA (1<<6)
5189#define PCICFG_COMMAND_STEPPING (1<<7)
5190#define PCICFG_COMMAND_SERR_ENA (1<<8)
5191#define PCICFG_COMMAND_FAST_B2B (1<<9)
5192#define PCICFG_COMMAND_INT_DISABLE (1<<10)
5193#define PCICFG_COMMAND_RESERVED (0x1f<<11)
5194
5195#define PCICFG_PM_CSR_STATE (0x3<<0)
5196#define PCICFG_PM_CSR_PME_STATUS (1<<15)
5197
4240#define BAR_USTRORM_INTMEM 0x400000 5198#define BAR_USTRORM_INTMEM 0x400000
4241#define BAR_CSTRORM_INTMEM 0x410000 5199#define BAR_CSTRORM_INTMEM 0x410000
4242#define BAR_XSTRORM_INTMEM 0x420000 5200#define BAR_XSTRORM_INTMEM 0x420000
@@ -4336,7 +5294,7 @@
4336#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000 5294#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
4337 5295
4338#define MDIO_REG_BANK_CL73_IEEEB1 0x10 5296#define MDIO_REG_BANK_CL73_IEEEB1 0x10
4339#define MDIO_CL73_IEEEB1_AN_ADV2 0x01 5297#define MDIO_CL73_IEEEB1_AN_ADV2 0x01
4340#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000 5298#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
4341#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020 5299#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
4342#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040 5300#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
@@ -4365,7 +5323,7 @@
4365#define MDIO_REG_BANK_RX_ALL 0x80f0 5323#define MDIO_REG_BANK_RX_ALL 0x80f0
4366#define MDIO_RX_ALL_RX_EQ_BOOST 0x1c 5324#define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
4367#define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 5325#define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
4368#define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10 5326#define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
4369 5327
4370#define MDIO_REG_BANK_TX0 0x8060 5328#define MDIO_REG_BANK_TX0 0x8060
4371#define MDIO_TX0_TX_DRIVER 0x17 5329#define MDIO_TX0_TX_DRIVER 0x17
@@ -4392,213 +5350,266 @@
4392#define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10 5350#define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
4393#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000 5351#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
4394#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000 5352#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
4395#define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11 5353#define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
4396#define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000 5354#define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
4397#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14 5355#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
4398#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001 5356#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
4399#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010 5357#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
4400#define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15 5358#define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
4401 5359
4402#define MDIO_REG_BANK_GP_STATUS 0x8120 5360#define MDIO_REG_BANK_GP_STATUS 0x8120
4403#define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B 5361#define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
4404#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001 5362#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
4405#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002 5363#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
4406#define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004 5364#define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
4407#define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008 5365#define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
4408#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010 5366#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
4409#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020 5367#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
4410 5368#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
4411#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040 5369#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
4412#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080 5370#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
4413#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00 5371#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
4414#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000 5372#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
4415#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100 5373#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
4416#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200 5374#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
4417#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300 5375#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
4418#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400 5376#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
4419#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500 5377#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
4420#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600 5378#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
4421#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700 5379#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
4422#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800 5380#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
4423#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900 5381#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
4424#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00 5382#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
4425#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00 5383#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
4426#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00 5384#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
4427#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00 5385#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
4428#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
4429 5386
4430 5387
4431#define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130 5388#define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
4432#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11 5389#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
4433#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1 5390#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
4434#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13 5391#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
4435#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1) 5392#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
4436 5393
4437#define MDIO_REG_BANK_SERDES_DIGITAL 0x8300 5394#define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
4438#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10 5395#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
4439#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001 5396#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
4440#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002 5397#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
4441#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004 5398#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
4442#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008 5399#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
4443#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010 5400#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
4444#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020 5401#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
4445#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11 5402#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
4446#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001 5403#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
4447#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040 5404#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
4448#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14 5405#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
4449#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004 5406#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
4450#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018 5407#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
4451#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3 5408#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
4452#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018 5409#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
4453#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010 5410#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
4454#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008 5411#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
4455#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000 5412#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
4456#define MDIO_SERDES_DIGITAL_MISC1 0x18 5413#define MDIO_SERDES_DIGITAL_MISC1 0x18
4457#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000 5414#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
4458#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000 5415#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
4459#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000 5416#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
4460#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000 5417#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
4461#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000 5418#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
4462#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000 5419#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
4463#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010 5420#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
4464#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f 5421#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
4465#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000 5422#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
4466#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001 5423#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
4467#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002 5424#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
4468#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003 5425#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
4469#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004 5426#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
4470#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005 5427#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
4471#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006 5428#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
4472#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007 5429#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
4473#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008 5430#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
4474#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009 5431#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
4475 5432
4476#define MDIO_REG_BANK_OVER_1G 0x8320 5433#define MDIO_REG_BANK_OVER_1G 0x8320
4477#define MDIO_OVER_1G_DIGCTL_3_4 0x14 5434#define MDIO_OVER_1G_DIGCTL_3_4 0x14
4478#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0 5435#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
4479#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5 5436#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
4480#define MDIO_OVER_1G_UP1 0x19 5437#define MDIO_OVER_1G_UP1 0x19
4481#define MDIO_OVER_1G_UP1_2_5G 0x0001 5438#define MDIO_OVER_1G_UP1_2_5G 0x0001
4482#define MDIO_OVER_1G_UP1_5G 0x0002 5439#define MDIO_OVER_1G_UP1_5G 0x0002
4483#define MDIO_OVER_1G_UP1_6G 0x0004 5440#define MDIO_OVER_1G_UP1_6G 0x0004
4484#define MDIO_OVER_1G_UP1_10G 0x0010 5441#define MDIO_OVER_1G_UP1_10G 0x0010
4485#define MDIO_OVER_1G_UP1_10GH 0x0008 5442#define MDIO_OVER_1G_UP1_10GH 0x0008
4486#define MDIO_OVER_1G_UP1_12G 0x0020 5443#define MDIO_OVER_1G_UP1_12G 0x0020
4487#define MDIO_OVER_1G_UP1_12_5G 0x0040 5444#define MDIO_OVER_1G_UP1_12_5G 0x0040
4488#define MDIO_OVER_1G_UP1_13G 0x0080 5445#define MDIO_OVER_1G_UP1_13G 0x0080
4489#define MDIO_OVER_1G_UP1_15G 0x0100 5446#define MDIO_OVER_1G_UP1_15G 0x0100
4490#define MDIO_OVER_1G_UP1_16G 0x0200 5447#define MDIO_OVER_1G_UP1_16G 0x0200
4491#define MDIO_OVER_1G_UP2 0x1A 5448#define MDIO_OVER_1G_UP2 0x1A
4492#define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007 5449#define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
4493#define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038 5450#define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
4494#define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0 5451#define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
4495#define MDIO_OVER_1G_UP3 0x1B 5452#define MDIO_OVER_1G_UP3 0x1B
4496#define MDIO_OVER_1G_UP3_HIGIG2 0x0001 5453#define MDIO_OVER_1G_UP3_HIGIG2 0x0001
4497#define MDIO_OVER_1G_LP_UP1 0x1C 5454#define MDIO_OVER_1G_LP_UP1 0x1C
4498#define MDIO_OVER_1G_LP_UP2 0x1D 5455#define MDIO_OVER_1G_LP_UP2 0x1D
4499#define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff 5456#define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
4500#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780 5457#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
4501#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7 5458#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
4502#define MDIO_OVER_1G_LP_UP3 0x1E 5459#define MDIO_OVER_1G_LP_UP3 0x1E
4503 5460
4504#define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350 5461#define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
4505#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10 5462#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
4506#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001 5463#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
4507#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002 5464#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
5465
5466#define MDIO_REG_BANK_CL73_USERB0 0x8370
5467#define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
5468#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
5469#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
5470#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
5471#define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
5472#define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
5473
5474#define MDIO_REG_BANK_AER_BLOCK 0xFFD0
5475#define MDIO_AER_BLOCK_AER_REG 0x1E
5476
5477#define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
5478#define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
5479#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
5480#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
5481#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
5482#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
5483#define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
5484#define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
5485#define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
5486#define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
5487#define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
5488#define MDIO_COMBO_IEEE0_MII_STATUS 0x11
5489#define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
5490#define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
5491#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
5492#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
5493#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
5494#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
5495#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
5496#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
5497#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
5498#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
5499#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
5500#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
5501#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
5502#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
5503#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
5504#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
5505#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
5506#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
5507#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
5508/*WhenthelinkpartnerisinSGMIImode(bit0=1),then
5509bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
5510Theotherbitsarereservedandshouldbezero*/
5511#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
5512
5513
5514#define MDIO_PMA_DEVAD 0x1
5515/*ieee*/
5516#define MDIO_PMA_REG_CTRL 0x0
5517#define MDIO_PMA_REG_STATUS 0x1
5518#define MDIO_PMA_REG_10G_CTRL2 0x7
5519#define MDIO_PMA_REG_RX_SD 0xa
5520/*bcm*/
5521#define MDIO_PMA_REG_BCM_CTRL 0x0096
5522#define MDIO_PMA_REG_FEC_CTRL 0x00ab
5523#define MDIO_PMA_REG_RX_ALARM_CTRL 0x9000
5524#define MDIO_PMA_REG_LASI_CTRL 0x9002
5525#define MDIO_PMA_REG_RX_ALARM 0x9003
5526#define MDIO_PMA_REG_TX_ALARM 0x9004
5527#define MDIO_PMA_REG_LASI_STATUS 0x9005
5528#define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
5529#define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
5530#define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
5531#define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
5532#define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
5533#define MDIO_PMA_REG_MISC_CTRL 0xca0a
5534#define MDIO_PMA_REG_GEN_CTRL 0xca10
5535#define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
5536#define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
5537#define MDIO_PMA_REG_ROM_VER1 0xca19
5538#define MDIO_PMA_REG_ROM_VER2 0xca1a
5539#define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
5540#define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
5541#define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
5542#define MDIO_PMA_REG_MISC_CTRL1 0xca85
5543
5544#define MDIO_PMA_REG_7101_RESET 0xc000
5545#define MDIO_PMA_REG_7107_LED_CNTL 0xc007
5546#define MDIO_PMA_REG_7101_VER1 0xc026
5547#define MDIO_PMA_REG_7101_VER2 0xc027
5548
5549
5550#define MDIO_WIS_DEVAD 0x2
5551/*bcm*/
5552#define MDIO_WIS_REG_LASI_CNTL 0x9002
5553#define MDIO_WIS_REG_LASI_STATUS 0x9005
5554
5555#define MDIO_PCS_DEVAD 0x3
5556#define MDIO_PCS_REG_STATUS 0x0020
5557#define MDIO_PCS_REG_LASI_STATUS 0x9005
5558#define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
5559#define MDIO_PCS_REG_7101_SPI_MUX 0xD008
5560#define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
5561#define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
5562#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
5563#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
5564#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
5565#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
5566#define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
5567
4508 5568
4509#define MDIO_REG_BANK_CL73_USERB0 0x8370 5569#define MDIO_XS_DEVAD 0x4
4510#define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12 5570#define MDIO_XS_PLL_SEQUENCER 0x8000
4511#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000 5571#define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
4512#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
4513#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
4514#define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
4515#define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
4516 5572
4517#define MDIO_REG_BANK_AER_BLOCK 0xFFD0 5573#define MDIO_AN_DEVAD 0x7
4518#define MDIO_AER_BLOCK_AER_REG 0x1E 5574/*ieee*/
5575#define MDIO_AN_REG_CTRL 0x0000
5576#define MDIO_AN_REG_STATUS 0x0001
5577#define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
5578#define MDIO_AN_REG_ADV_PAUSE 0x0010
5579#define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
5580#define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
5581#define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
5582#define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
5583#define MDIO_AN_REG_ADV 0x0011
5584#define MDIO_AN_REG_ADV2 0x0012
5585#define MDIO_AN_REG_LP_AUTO_NEG 0x0013
5586#define MDIO_AN_REG_MASTER_STATUS 0x0021
5587/*bcm*/
5588#define MDIO_AN_REG_LINK_STATUS 0x8304
5589#define MDIO_AN_REG_CL37_CL73 0x8370
5590#define MDIO_AN_REG_CL37_AN 0xffe0
5591#define MDIO_AN_REG_CL37_FD 0xffe4
4519 5592
4520#define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
4521#define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
4522#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
4523#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
4524#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
4525#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
4526#define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
4527#define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
4528#define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
4529#define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
4530#define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
4531#define MDIO_COMBO_IEEE0_MII_STATUS 0x11
4532#define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
4533#define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
4534#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
4535#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
4536#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
4537#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
4538#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
4539#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
4540#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
4541#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
4542#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
4543#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
4544#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
4545#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
4546#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
4547#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE\
4548 0x0000
4549#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH\
4550 0x0180
4551#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
4552#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
4553#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
4554 5593
5594#define IGU_FUNC_BASE 0x0400
4555 5595
4556#define EXT_PHY_AUTO_NEG_DEVAD 0x7 5596#define IGU_ADDR_MSIX 0x0000
4557#define EXT_PHY_OPT_PMA_PMD_DEVAD 0x1 5597#define IGU_ADDR_INT_ACK 0x0200
4558#define EXT_PHY_OPT_WIS_DEVAD 0x2 5598#define IGU_ADDR_PROD_UPD 0x0201
4559#define EXT_PHY_OPT_PCS_DEVAD 0x3 5599#define IGU_ADDR_ATTN_BITS_UPD 0x0202
4560#define EXT_PHY_OPT_PHY_XS_DEVAD 0x4 5600#define IGU_ADDR_ATTN_BITS_SET 0x0203
4561#define EXT_PHY_OPT_CNTL 0x0 5601#define IGU_ADDR_ATTN_BITS_CLR 0x0204
4562#define EXT_PHY_OPT_CNTL2 0x7 5602#define IGU_ADDR_COALESCE_NOW 0x0205
4563#define EXT_PHY_OPT_PMD_RX_SD 0xa 5603#define IGU_ADDR_SIMD_MASK 0x0206
4564#define EXT_PHY_OPT_PMD_MISC_CNTL 0xca0a 5604#define IGU_ADDR_SIMD_NOMASK 0x0207
4565#define EXT_PHY_OPT_PHY_IDENTIFIER 0xc800 5605#define IGU_ADDR_MSI_CTL 0x0210
4566#define EXT_PHY_OPT_PMD_DIGITAL_CNT 0xc808 5606#define IGU_ADDR_MSI_ADDR_LO 0x0211
4567#define EXT_PHY_OPT_PMD_DIGITAL_SATUS 0xc809 5607#define IGU_ADDR_MSI_ADDR_HI 0x0212
4568#define EXT_PHY_OPT_CMU_PLL_BYPASS 0xca09 5608#define IGU_ADDR_MSI_DATA 0x0213
4569#define EXT_PHY_OPT_LASI_CNTL 0x9002
4570#define EXT_PHY_OPT_RX_ALARM 0x9003
4571#define EXT_PHY_OPT_LASI_STATUS 0x9005
4572#define EXT_PHY_OPT_PCS_STATUS 0x0020
4573#define EXT_PHY_OPT_XGXS_LANE_STATUS 0x0018
4574#define EXT_PHY_OPT_AN_LINK_STATUS 0x8304
4575#define EXT_PHY_OPT_AN_CL37_CL73 0x8370
4576#define EXT_PHY_OPT_AN_CL37_FD 0xffe4
4577#define EXT_PHY_OPT_AN_CL37_AN 0xffe0
4578#define EXT_PHY_OPT_AN_ADV 0x11
4579 5609
4580#define EXT_PHY_KR_PMA_PMD_DEVAD 0x1 5610#define IGU_INT_ENABLE 0
4581#define EXT_PHY_KR_PCS_DEVAD 0x3 5611#define IGU_INT_DISABLE 1
4582#define EXT_PHY_KR_AUTO_NEG_DEVAD 0x7 5612#define IGU_INT_NOP 2
4583#define EXT_PHY_KR_CTRL 0x0000 5613#define IGU_INT_NOP2 3
4584#define EXT_PHY_KR_STATUS 0x0001
4585#define EXT_PHY_KR_AUTO_NEG_COMPLETE 0x0020
4586#define EXT_PHY_KR_AUTO_NEG_ADVERT 0x0010
4587#define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE 0x0400
4588#define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_ASYMMETRIC 0x0800
4589#define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_BOTH 0x0C00
4590#define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_MASK 0x0C00
4591#define EXT_PHY_KR_LP_AUTO_NEG 0x0013
4592#define EXT_PHY_KR_CTRL2 0x0007
4593#define EXT_PHY_KR_PCS_STATUS 0x0020
4594#define EXT_PHY_KR_PMD_CTRL 0x0096
4595#define EXT_PHY_KR_LASI_CNTL 0x9002
4596#define EXT_PHY_KR_LASI_STATUS 0x9005
4597#define EXT_PHY_KR_MISC_CTRL1 0xca85
4598#define EXT_PHY_KR_GEN_CTRL 0xca10
4599#define EXT_PHY_KR_ROM_CODE 0xca19
4600#define EXT_PHY_KR_ROM_RESET_INTERNAL_MP 0x0188
4601#define EXT_PHY_KR_ROM_MICRO_RESET 0x018a
4602 5614
4603#define EXT_PHY_SFX7101_XGXS_TEST1 0xc00a
4604 5615
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-30 15:28:35 -0400