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authorStephen Hemminger <shemminger@osdl.org>2006-12-05 15:02:50 -0500
committerJeff Garzik <jeff@garzik.org>2006-12-07 04:59:20 -0500
commit7f4b45c5269049e223eda31c7e3879c226039e4a (patch)
tree50924e3e760420f3a4e9324c3e8e65bcd0fb3d94 /drivers/net
parente67bda55e27d3308ba0b4ce8cf2da51850ef1453 (diff)
[PATCH] skge: fix sparse warnings
Fix sparse warnings from using enum as part of arithmetic expression, and comment indentation fixes Signed-off-by: Stephen Hemminger <shemminger@osdl.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/skge.h150
1 files changed, 75 insertions, 75 deletions
diff --git a/drivers/net/skge.h b/drivers/net/skge.h
index 23e5275d920c..f6223c533c01 100644
--- a/drivers/net/skge.h
+++ b/drivers/net/skge.h
@@ -389,10 +389,10 @@ enum {
389/* Packet Arbiter Registers */ 389/* Packet Arbiter Registers */
390/* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */ 390/* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */
391enum { 391enum {
392 PA_CLR_TO_TX2 = 1<<13, /* Clear IRQ Packet Timeout TX2 */ 392 PA_CLR_TO_TX2 = 1<<13,/* Clear IRQ Packet Timeout TX2 */
393 PA_CLR_TO_TX1 = 1<<12, /* Clear IRQ Packet Timeout TX1 */ 393 PA_CLR_TO_TX1 = 1<<12,/* Clear IRQ Packet Timeout TX1 */
394 PA_CLR_TO_RX2 = 1<<11, /* Clear IRQ Packet Timeout RX2 */ 394 PA_CLR_TO_RX2 = 1<<11,/* Clear IRQ Packet Timeout RX2 */
395 PA_CLR_TO_RX1 = 1<<10, /* Clear IRQ Packet Timeout RX1 */ 395 PA_CLR_TO_RX1 = 1<<10,/* Clear IRQ Packet Timeout RX1 */
396 PA_ENA_TO_TX2 = 1<<9, /* Enable Timeout Timer TX2 */ 396 PA_ENA_TO_TX2 = 1<<9, /* Enable Timeout Timer TX2 */
397 PA_DIS_TO_TX2 = 1<<8, /* Disable Timeout Timer TX2 */ 397 PA_DIS_TO_TX2 = 1<<8, /* Disable Timeout Timer TX2 */
398 PA_ENA_TO_TX1 = 1<<7, /* Enable Timeout Timer TX1 */ 398 PA_ENA_TO_TX1 = 1<<7, /* Enable Timeout Timer TX1 */
@@ -481,14 +481,14 @@ enum {
481/* RAM Buffer Register Offsets */ 481/* RAM Buffer Register Offsets */
482enum { 482enum {
483 483
484 RB_START = 0x00,/* 32 bit RAM Buffer Start Address */ 484 RB_START= 0x00,/* 32 bit RAM Buffer Start Address */
485 RB_END = 0x04,/* 32 bit RAM Buffer End Address */ 485 RB_END = 0x04,/* 32 bit RAM Buffer End Address */
486 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */ 486 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
487 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */ 487 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
488 RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */ 488 RB_RX_UTPP= 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
489 RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */ 489 RB_RX_LTPP= 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
490 RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */ 490 RB_RX_UTHP= 0x18,/* 32 bit Rx Upper Threshold, High Prio */
491 RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */ 491 RB_RX_LTHP= 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
492 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */ 492 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
493 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */ 493 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
494 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */ 494 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
@@ -532,7 +532,7 @@ enum {
532 PHY_ADDR_MARV = 0, 532 PHY_ADDR_MARV = 0,
533}; 533};
534 534
535#define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs)) 535#define RB_ADDR(offs, queue) ((u16)B16_RAM_REGS + (u16)(queue) + (offs))
536 536
537/* Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) */ 537/* Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) */
538enum { 538enum {
@@ -578,15 +578,15 @@ enum {
578 MFF_DIS_TIST = 1<<2, /* Disable Time Stamp Gener */ 578 MFF_DIS_TIST = 1<<2, /* Disable Time Stamp Gener */
579 MFF_CLR_INTIST = 1<<1, /* Clear IRQ No Time Stamp */ 579 MFF_CLR_INTIST = 1<<1, /* Clear IRQ No Time Stamp */
580 MFF_CLR_INSTAT = 1<<0, /* Clear IRQ No Status */ 580 MFF_CLR_INSTAT = 1<<0, /* Clear IRQ No Status */
581#define MFF_RX_CTRL_DEF MFF_ENA_TIM_PAT 581 MFF_RX_CTRL_DEF = MFF_ENA_TIM_PAT,
582}; 582};
583 583
584/* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */ 584/* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */
585enum { 585enum {
586 MFF_CLR_PERR = 1<<15, /* Clear Parity Error IRQ */ 586 MFF_CLR_PERR = 1<<15, /* Clear Parity Error IRQ */
587 /* Bit 14: reserved */ 587
588 MFF_ENA_PKT_REC = 1<<13, /* Enable Packet Recovery */ 588 MFF_ENA_PKT_REC = 1<<13, /* Enable Packet Recovery */
589 MFF_DIS_PKT_REC = 1<<12, /* Disable Packet Recovery */ 589 MFF_DIS_PKT_REC = 1<<12, /* Disable Packet Recovery */
590 590
591 MFF_ENA_W4E = 1<<7, /* Enable Wait for Empty */ 591 MFF_ENA_W4E = 1<<7, /* Enable Wait for Empty */
592 MFF_DIS_W4E = 1<<6, /* Disable Wait for Empty */ 592 MFF_DIS_W4E = 1<<6, /* Disable Wait for Empty */
@@ -595,9 +595,10 @@ enum {
595 MFF_DIS_LOOPB = 1<<2, /* Disable Loopback */ 595 MFF_DIS_LOOPB = 1<<2, /* Disable Loopback */
596 MFF_CLR_MAC_RST = 1<<1, /* Clear XMAC Reset */ 596 MFF_CLR_MAC_RST = 1<<1, /* Clear XMAC Reset */
597 MFF_SET_MAC_RST = 1<<0, /* Set XMAC Reset */ 597 MFF_SET_MAC_RST = 1<<0, /* Set XMAC Reset */
598
599 MFF_TX_CTRL_DEF = MFF_ENA_PKT_REC | (u16) MFF_ENA_TIM_PAT | MFF_ENA_FLUSH,
598}; 600};
599 601
600#define MFF_TX_CTRL_DEF (MFF_ENA_PKT_REC | MFF_ENA_TIM_PAT | MFF_ENA_FLUSH)
601 602
602/* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */ 603/* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */
603/* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */ 604/* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */
@@ -1304,8 +1305,8 @@ enum {
1304 1305
1305/* special defines for FIBER (88E1011S only) */ 1306/* special defines for FIBER (88E1011S only) */
1306enum { 1307enum {
1307 PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */ 1308 PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
1308 PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */ 1309 PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
1309 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */ 1310 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1310 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */ 1311 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1311}; 1312};
@@ -1320,7 +1321,7 @@ enum {
1320 1321
1321/***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ 1322/***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1322enum { 1323enum {
1323 PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */ 1324 PHY_M_1000C_TEST= 7<<13,/* Bit 15..13: Test Modes */
1324 PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */ 1325 PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
1325 PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */ 1326 PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
1326 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */ 1327 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
@@ -1349,7 +1350,7 @@ enum {
1349 PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */ 1350 PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
1350}; 1351};
1351 1352
1352#define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK) 1353#define PHY_M_PC_MDI_XMODE(x) ((((u16)(x)<<5) & PHY_M_PC_MDIX_MSK)
1353 1354
1354enum { 1355enum {
1355 PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */ 1356 PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
@@ -1432,24 +1433,24 @@ enum {
1432 PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */ 1433 PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
1433 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */ 1434 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
1434 /* (88E1011 only) */ 1435 /* (88E1011 only) */
1435 PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */ 1436 PHY_M_EC_S_DSC_MSK = 3<<8, /* Bit 9.. 8: Slave Downshift Counter */
1436 /* (88E1011 only) */ 1437 /* (88E1011 only) */
1437 PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */ 1438 PHY_M_EC_M_DSC_MSK2 = 7<<9, /* Bit 11.. 9: Master Downshift Counter */
1438 /* (88E1111 only) */ 1439 /* (88E1111 only) */
1439 PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */ 1440 PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
1440 /* !!! Errata in spec. (1 = disable) */ 1441 /* !!! Errata in spec. (1 = disable) */
1441 PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/ 1442 PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
1442 PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */ 1443 PHY_M_EC_MAC_S_MSK = 7<<4, /* Bit 6.. 4: Def. MAC interface speed */
1443 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */ 1444 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1444 PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */ 1445 PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
1445 PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */ 1446 PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
1446 PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */}; 1447 PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
1447 1448
1448#define PHY_M_EC_M_DSC(x) ((x)<<10) /* 00=1x; 01=2x; 10=3x; 11=4x */ 1449#define PHY_M_EC_M_DSC(x) ((u16)(x)<<10) /* 00=1x; 01=2x; 10=3x; 11=4x */
1449#define PHY_M_EC_S_DSC(x) ((x)<<8) /* 00=dis; 01=1x; 10=2x; 11=3x */ 1450#define PHY_M_EC_S_DSC(x) ((u16)(x)<<8) /* 00=dis; 01=1x; 10=2x; 11=3x */
1450#define PHY_M_EC_MAC_S(x) ((x)<<4) /* 01X=0; 110=2.5; 111=25 (MHz) */ 1451#define PHY_M_EC_MAC_S(x) ((u16)(x)<<4) /* 01X=0; 110=2.5; 111=25 (MHz) */
1451 1452
1452#define PHY_M_EC_M_DSC_2(x) ((x)<<9) /* 000=1x; 001=2x; 010=3x; 011=4x */ 1453#define PHY_M_EC_M_DSC_2(x) ((u16)(x)<<9) /* 000=1x; 001=2x; 010=3x; 011=4x */
1453 /* 100=5x; 101=6x; 110=7x; 111=8x */ 1454 /* 100=5x; 101=6x; 110=7x; 111=8x */
1454enum { 1455enum {
1455 MAC_TX_CLK_0_MHZ = 2, 1456 MAC_TX_CLK_0_MHZ = 2,
@@ -1468,10 +1469,12 @@ enum {
1468 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */ 1469 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
1469 /* (88E1111 only) */ 1470 /* (88E1111 only) */
1470}; 1471};
1472#define PHY_M_LED_PULS_DUR(x) (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)
1473#define PHY_M_LED_BLINK_RT(x) (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)
1471 1474
1472enum { 1475enum {
1473 PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */ 1476 PHY_M_LEDC_LINK_MSK = 3<<3, /* Bit 4.. 3: Link Control Mask */
1474 /* (88E1011 only) */ 1477 /* (88E1011 only) */
1475 PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */ 1478 PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
1476 PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */ 1479 PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
1477 PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */ 1480 PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
@@ -1479,27 +1482,24 @@ enum {
1479 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */ 1482 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
1480}; 1483};
1481 1484
1482#define PHY_M_LED_PULS_DUR(x) (((x)<<12) & PHY_M_LEDC_PULS_MSK)
1483
1484enum { 1485enum {
1485 PULS_NO_STR = 0,/* no pulse stretching */ 1486 PULS_NO_STR = 0, /* no pulse stretching */
1486 PULS_21MS = 1,/* 21 ms to 42 ms */ 1487 PULS_21MS = 1, /* 21 ms to 42 ms */
1487 PULS_42MS = 2,/* 42 ms to 84 ms */ 1488 PULS_42MS = 2, /* 42 ms to 84 ms */
1488 PULS_84MS = 3,/* 84 ms to 170 ms */ 1489 PULS_84MS = 3, /* 84 ms to 170 ms */
1489 PULS_170MS = 4,/* 170 ms to 340 ms */ 1490 PULS_170MS = 4, /* 170 ms to 340 ms */
1490 PULS_340MS = 5,/* 340 ms to 670 ms */ 1491 PULS_340MS = 5, /* 340 ms to 670 ms */
1491 PULS_670MS = 6,/* 670 ms to 1.3 s */ 1492 PULS_670MS = 6, /* 670 ms to 1.3 s */
1492 PULS_1300MS = 7,/* 1.3 s to 2.7 s */ 1493 PULS_1300MS = 7, /* 1.3 s to 2.7 s */
1493}; 1494};
1494 1495
1495#define PHY_M_LED_BLINK_RT(x) (((x)<<8) & PHY_M_LEDC_BL_R_MSK)
1496 1496
1497enum { 1497enum {
1498 BLINK_42MS = 0,/* 42 ms */ 1498 BLINK_42MS = 0, /* 42 ms */
1499 BLINK_84MS = 1,/* 84 ms */ 1499 BLINK_84MS = 1, /* 84 ms */
1500 BLINK_170MS = 2,/* 170 ms */ 1500 BLINK_170MS = 2, /* 170 ms */
1501 BLINK_340MS = 3,/* 340 ms */ 1501 BLINK_340MS = 3, /* 340 ms */
1502 BLINK_670MS = 4,/* 670 ms */ 1502 BLINK_670MS = 4, /* 670 ms */
1503}; 1503};
1504 1504
1505/***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/ 1505/***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
@@ -1525,7 +1525,7 @@ enum {
1525 PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */ 1525 PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
1526 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */ 1526 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
1527 PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */ 1527 PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
1528 PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */ 1528 PHY_M_EC2_FO_AM_MSK = 7, /* Bit 2.. 0: Fiber Output Amplitude */
1529}; 1529};
1530 1530
1531/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/ 1531/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
@@ -1550,7 +1550,7 @@ enum {
1550 PHY_M_CABD_DIS_WAIT = 1<<15, /* Disable Waiting Period (Page 1) */ 1550 PHY_M_CABD_DIS_WAIT = 1<<15, /* Disable Waiting Period (Page 1) */
1551 /* (88E1111 only) */ 1551 /* (88E1111 only) */
1552 PHY_M_CABD_STAT_MSK = 3<<13, /* Bit 14..13: Status Mask */ 1552 PHY_M_CABD_STAT_MSK = 3<<13, /* Bit 14..13: Status Mask */
1553 PHY_M_CABD_AMPL_MSK = 0x1f<<8,/* Bit 12.. 8: Amplitude Mask */ 1553 PHY_M_CABD_AMPL_MSK = 0x1f<<8, /* Bit 12.. 8: Amplitude Mask */
1554 /* (88E1111 only) */ 1554 /* (88E1111 only) */
1555 PHY_M_CABD_DIST_MSK = 0xff, /* Bit 7.. 0: Distance Mask */ 1555 PHY_M_CABD_DIST_MSK = 0xff, /* Bit 7.. 0: Distance Mask */
1556}; 1556};
@@ -1605,9 +1605,9 @@ enum {
1605 1605
1606/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/ 1606/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1607enum { 1607enum {
1608 PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */ 1608 PHY_M_LEDC_LOS_MSK = 0xf<<12, /* Bit 15..12: LOS LED Ctrl. Mask */
1609 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */ 1609 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1610 PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */ 1610 PHY_M_LEDC_STA1_MSK = 0xf<<4, /* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1611 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */ 1611 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1612}; 1612};
1613 1613
@@ -1804,8 +1804,8 @@ enum {
1804 1804
1805/* GM_SMI_CTRL 16 bit r/w SMI Control Register */ 1805/* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1806enum { 1806enum {
1807 GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */ 1807 GM_SMI_CT_PHY_A_MSK = 0x1f<<11, /* Bit 15..11: PHY Device Address */
1808 GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */ 1808 GM_SMI_CT_REG_A_MSK = 0x1f<<6, /* Bit 10.. 6: PHY Register Address */
1809 GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/ 1809 GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
1810 GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */ 1810 GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
1811 GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */ 1811 GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
@@ -1875,9 +1875,9 @@ enum {
1875 1875
1876/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */ 1876/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
1877enum { 1877enum {
1878 GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */ 1878 GMF_WSP_TST_ON = 1<<18, /* Write Shadow Pointer Test On */
1879 GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */ 1879 GMF_WSP_TST_OFF = 1<<17, /* Write Shadow Pointer Test Off */
1880 GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */ 1880 GMF_WSP_STEP = 1<<16, /* Write Shadow Pointer Step/Increment */
1881 1881
1882 GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */ 1882 GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
1883 GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */ 1883 GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
@@ -2111,18 +2111,18 @@ enum {
2111 2111
2112/* XM_MMU_CMD 16 bit r/w MMU Command Register */ 2112/* XM_MMU_CMD 16 bit r/w MMU Command Register */
2113enum { 2113enum {
2114 XM_MMU_PHY_RDY = 1<<12,/* Bit 12: PHY Read Ready */ 2114 XM_MMU_PHY_RDY = 1<<12, /* Bit 12: PHY Read Ready */
2115 XM_MMU_PHY_BUSY = 1<<11,/* Bit 11: PHY Busy */ 2115 XM_MMU_PHY_BUSY = 1<<11, /* Bit 11: PHY Busy */
2116 XM_MMU_IGN_PF = 1<<10,/* Bit 10: Ignore Pause Frame */ 2116 XM_MMU_IGN_PF = 1<<10, /* Bit 10: Ignore Pause Frame */
2117 XM_MMU_MAC_LB = 1<<9, /* Bit 9: Enable MAC Loopback */ 2117 XM_MMU_MAC_LB = 1<<9, /* Bit 9: Enable MAC Loopback */
2118 XM_MMU_FRC_COL = 1<<7, /* Bit 7: Force Collision */ 2118 XM_MMU_FRC_COL = 1<<7, /* Bit 7: Force Collision */
2119 XM_MMU_SIM_COL = 1<<6, /* Bit 6: Simulate Collision */ 2119 XM_MMU_SIM_COL = 1<<6, /* Bit 6: Simulate Collision */
2120 XM_MMU_NO_PRE = 1<<5, /* Bit 5: No MDIO Preamble */ 2120 XM_MMU_NO_PRE = 1<<5, /* Bit 5: No MDIO Preamble */
2121 XM_MMU_GMII_FD = 1<<4, /* Bit 4: GMII uses Full Duplex */ 2121 XM_MMU_GMII_FD = 1<<4, /* Bit 4: GMII uses Full Duplex */
2122 XM_MMU_RAT_CTRL = 1<<3, /* Bit 3: Enable Rate Control */ 2122 XM_MMU_RAT_CTRL = 1<<3, /* Bit 3: Enable Rate Control */
2123 XM_MMU_GMII_LOOP= 1<<2, /* Bit 2: PHY is in Loopback Mode */ 2123 XM_MMU_GMII_LOOP= 1<<2, /* Bit 2: PHY is in Loopback Mode */
2124 XM_MMU_ENA_RX = 1<<1, /* Bit 1: Enable Receiver */ 2124 XM_MMU_ENA_RX = 1<<1, /* Bit 1: Enable Receiver */
2125 XM_MMU_ENA_TX = 1<<0, /* Bit 0: Enable Transmitter */ 2125 XM_MMU_ENA_TX = 1<<0, /* Bit 0: Enable Transmitter */
2126}; 2126};
2127 2127
2128 2128
@@ -2506,7 +2506,7 @@ static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val)
2506} 2506}
2507 2507
2508/* MAC Related Registers inside the device. */ 2508/* MAC Related Registers inside the device. */
2509#define SK_REG(port,reg) (((port)<<7)+(reg)) 2509#define SK_REG(port,reg) (((port)<<7)+(u16)(reg))
2510#define SK_XMAC_REG(port, reg) \ 2510#define SK_XMAC_REG(port, reg) \
2511 ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1) 2511 ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
2512 2512