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authorLennert Buytenhek <buytenh@wantstofly.org>2008-05-31 19:41:29 -0400
committerLennert Buytenhek <buytenh@wantstofly.org>2008-06-12 02:40:29 -0400
commit7ca72a3b166fe5e7e7e2bf0fb9e48089cba6c25e (patch)
tree708d9642dce40545564d10969b2ba4b2ebfa8b71 /drivers/net
parenta2a41689fea5d9c6ae01d6becee513b7888dd53b (diff)
mv643xx_eth: clean up rx/tx descriptor field defines
Remove the unused rx/tx descriptor field defines, and move the ones that are actually used to the actual definitions of the rx/tx descriptor format. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Dale Farnsworth <dale@farnsworth.org>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/mv643xx_eth.c82
1 files changed, 28 insertions, 54 deletions
diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
index 6324556ccb67..307cfbeb2d47 100644
--- a/drivers/net/mv643xx_eth.c
+++ b/drivers/net/mv643xx_eth.c
@@ -176,57 +176,6 @@ static char mv643xx_driver_version[] = "1.0";
176#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */ 176#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */
177#define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */ 177#define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
178 178
179/* Interrupt Cause Register Bit Definitions */
180
181/* SDMA command status fields macros */
182
183/* Tx & Rx descriptors status */
184#define ETH_ERROR_SUMMARY 0x00000001
185
186/* Tx & Rx descriptors command */
187#define ETH_BUFFER_OWNED_BY_DMA 0x80000000
188
189/* Tx descriptors status */
190#define ETH_LC_ERROR 0
191#define ETH_UR_ERROR 0x00000002
192#define ETH_RL_ERROR 0x00000004
193#define ETH_LLC_SNAP_FORMAT 0x00000200
194
195/* Rx descriptors status */
196#define ETH_OVERRUN_ERROR 0x00000002
197#define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004
198#define ETH_RESOURCE_ERROR 0x00000006
199#define ETH_VLAN_TAGGED 0x00080000
200#define ETH_BPDU_FRAME 0x00100000
201#define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000
202#define ETH_OTHER_FRAME_TYPE 0x00400000
203#define ETH_LAYER_2_IS_ETH_V_2 0x00800000
204#define ETH_FRAME_TYPE_IP_V_4 0x01000000
205#define ETH_FRAME_HEADER_OK 0x02000000
206#define ETH_RX_LAST_DESC 0x04000000
207#define ETH_RX_FIRST_DESC 0x08000000
208#define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000
209#define ETH_RX_ENABLE_INTERRUPT 0x20000000
210#define ETH_LAYER_4_CHECKSUM_OK 0x40000000
211
212/* Rx descriptors byte count */
213#define ETH_FRAME_FRAGMENTED 0x00000004
214
215/* Tx descriptors command */
216#define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400
217#define ETH_FRAME_SET_TO_VLAN 0x00008000
218#define ETH_UDP_FRAME 0x00010000
219#define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000
220#define ETH_GEN_IP_V_4_CHECKSUM 0x00040000
221#define ETH_ZERO_PADDING 0x00080000
222#define ETH_TX_LAST_DESC 0x00100000
223#define ETH_TX_FIRST_DESC 0x00200000
224#define ETH_GEN_CRC 0x00400000
225#define ETH_TX_ENABLE_INTERRUPT 0x00800000
226#define ETH_AUTO_MODE 0x40000000
227
228#define ETH_TX_IHL_SHIFT 11
229
230/* typedefs */ 179/* typedefs */
231 180
232typedef enum _eth_func_ret_status { 181typedef enum _eth_func_ret_status {
@@ -238,8 +187,8 @@ typedef enum _eth_func_ret_status {
238 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */ 187 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
239} ETH_FUNC_RET_STATUS; 188} ETH_FUNC_RET_STATUS;
240 189
241/* These are for big-endian machines. Little endian needs different 190/*
242 * definitions. 191 * RX/TX descriptors.
243 */ 192 */
244#if defined(__BIG_ENDIAN) 193#if defined(__BIG_ENDIAN)
245struct eth_rx_desc { 194struct eth_rx_desc {
@@ -277,6 +226,31 @@ struct eth_tx_desc {
277#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined 226#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
278#endif 227#endif
279 228
229/* RX & TX descriptor command */
230#define ETH_BUFFER_OWNED_BY_DMA 0x80000000
231
232/* RX & TX descriptor status */
233#define ETH_ERROR_SUMMARY 0x00000001
234
235/* RX descriptor status */
236#define ETH_LAYER_4_CHECKSUM_OK 0x40000000
237#define ETH_RX_ENABLE_INTERRUPT 0x20000000
238#define ETH_RX_FIRST_DESC 0x08000000
239#define ETH_RX_LAST_DESC 0x04000000
240
241/* TX descriptor command */
242#define ETH_TX_ENABLE_INTERRUPT 0x00800000
243#define ETH_GEN_CRC 0x00400000
244#define ETH_TX_FIRST_DESC 0x00200000
245#define ETH_TX_LAST_DESC 0x00100000
246#define ETH_ZERO_PADDING 0x00080000
247#define ETH_GEN_IP_V4_CHECKSUM 0x00040000
248#define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000
249#define ETH_UDP_FRAME 0x00010000
250
251#define ETH_TX_IHL_SHIFT 11
252
253
280/* Unified struct for Rx and Tx operations. The user is not required to */ 254/* Unified struct for Rx and Tx operations. The user is not required to */
281/* be familier with neither Tx nor Rx descriptors. */ 255/* be familier with neither Tx nor Rx descriptors. */
282struct pkt_info { 256struct pkt_info {
@@ -905,7 +879,7 @@ static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp,
905 BUG_ON(skb->protocol != htons(ETH_P_IP)); 879 BUG_ON(skb->protocol != htons(ETH_P_IP));
906 880
907 cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM | 881 cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM |
908 ETH_GEN_IP_V_4_CHECKSUM | 882 ETH_GEN_IP_V4_CHECKSUM |
909 ip_hdr(skb)->ihl << ETH_TX_IHL_SHIFT; 883 ip_hdr(skb)->ihl << ETH_TX_IHL_SHIFT;
910 884
911 switch (ip_hdr(skb)->protocol) { 885 switch (ip_hdr(skb)->protocol) {