diff options
author | Yaniv Rosner <yanivr@broadcom.com> | 2011-05-31 17:25:55 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2011-06-01 16:10:55 -0400 |
commit | e4d78f120c039bbd18ae449a6b2af3df83ca02bf (patch) | |
tree | a6c81e02d4817a0a6cca475b5184f7546a41afda /drivers/net | |
parent | 34b1ef04fc050d171e055f75d6a3384e1323bd38 (diff) |
bnx2x: Add new phy BCM8722
Add support for new phy BCM8722.
Signed-off-by: Yaniv Rosner <yanivr@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r-- | drivers/net/bnx2x/bnx2x_hsi.h | 2 | ||||
-rw-r--r-- | drivers/net/bnx2x/bnx2x_link.c | 85 |
2 files changed, 62 insertions, 25 deletions
diff --git a/drivers/net/bnx2x/bnx2x_hsi.h b/drivers/net/bnx2x/bnx2x_hsi.h index cdf19fe7c7f6..6ee6160ce95d 100644 --- a/drivers/net/bnx2x/bnx2x_hsi.h +++ b/drivers/net/bnx2x/bnx2x_hsi.h | |||
@@ -417,6 +417,7 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ | |||
417 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00 | 417 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00 |
418 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00 | 418 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00 |
419 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00 | 419 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00 |
420 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00 | ||
420 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00 | 421 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00 |
421 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00 | 422 | #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00 |
422 | 423 | ||
@@ -473,6 +474,7 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ | |||
473 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 | 474 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 |
474 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 | 475 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 |
475 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00 | 476 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00 |
477 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00 | ||
476 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 | 478 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 |
477 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 | 479 | #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 |
478 | 480 | ||
diff --git a/drivers/net/bnx2x/bnx2x_link.c b/drivers/net/bnx2x/bnx2x_link.c index 076e11f5769f..56b5ed8f6342 100644 --- a/drivers/net/bnx2x/bnx2x_link.c +++ b/drivers/net/bnx2x/bnx2x_link.c | |||
@@ -3146,8 +3146,10 @@ u8 bnx2x_set_led(struct link_params *params, | |||
3146 | if (!vars->link_up) | 3146 | if (!vars->link_up) |
3147 | break; | 3147 | break; |
3148 | case LED_MODE_ON: | 3148 | case LED_MODE_ON: |
3149 | if (params->phy[EXT_PHY1].type == | 3149 | if (((params->phy[EXT_PHY1].type == |
3150 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 && | 3150 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) || |
3151 | (params->phy[EXT_PHY1].type == | ||
3152 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) && | ||
3151 | CHIP_IS_E2(bp) && params->num_phys == 2) { | 3153 | CHIP_IS_E2(bp) && params->num_phys == 2) { |
3152 | /* | 3154 | /* |
3153 | * This is a work-around for E2+8727 Configurations | 3155 | * This is a work-around for E2+8727 Configurations |
@@ -4657,13 +4659,19 @@ u8 bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy, | |||
4657 | struct link_params *params, u16 addr, | 4659 | struct link_params *params, u16 addr, |
4658 | u8 byte_cnt, u8 *o_buf) | 4660 | u8 byte_cnt, u8 *o_buf) |
4659 | { | 4661 | { |
4660 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) | 4662 | u8 rc = -EINVAL; |
4661 | return bnx2x_8726_read_sfp_module_eeprom(phy, params, addr, | 4663 | switch (phy->type) { |
4662 | byte_cnt, o_buf); | 4664 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: |
4663 | else if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) | 4665 | rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr, |
4664 | return bnx2x_8727_read_sfp_module_eeprom(phy, params, addr, | 4666 | byte_cnt, o_buf); |
4665 | byte_cnt, o_buf); | 4667 | break; |
4666 | return -EINVAL; | 4668 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: |
4669 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: | ||
4670 | rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr, | ||
4671 | byte_cnt, o_buf); | ||
4672 | break; | ||
4673 | } | ||
4674 | return rc; | ||
4667 | } | 4675 | } |
4668 | 4676 | ||
4669 | static u8 bnx2x_get_edc_mode(struct bnx2x_phy *phy, | 4677 | static u8 bnx2x_get_edc_mode(struct bnx2x_phy *phy, |
@@ -5021,6 +5029,38 @@ static void bnx2x_set_sfp_module_fault_led(struct link_params *params, | |||
5021 | } | 5029 | } |
5022 | } | 5030 | } |
5023 | 5031 | ||
5032 | static void bnx2x_power_sfp_module(struct link_params *params, | ||
5033 | struct bnx2x_phy *phy, | ||
5034 | u8 power) | ||
5035 | { | ||
5036 | struct bnx2x *bp = params->bp; | ||
5037 | DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power); | ||
5038 | |||
5039 | switch (phy->type) { | ||
5040 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: | ||
5041 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: | ||
5042 | bnx2x_8727_power_module(params->bp, phy, power); | ||
5043 | break; | ||
5044 | default: | ||
5045 | break; | ||
5046 | } | ||
5047 | } | ||
5048 | |||
5049 | static void bnx2x_set_limiting_mode(struct link_params *params, | ||
5050 | struct bnx2x_phy *phy, | ||
5051 | u16 edc_mode) | ||
5052 | { | ||
5053 | switch (phy->type) { | ||
5054 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: | ||
5055 | bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode); | ||
5056 | break; | ||
5057 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: | ||
5058 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: | ||
5059 | bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode); | ||
5060 | break; | ||
5061 | } | ||
5062 | } | ||
5063 | |||
5024 | static u8 bnx2x_sfp_module_detection(struct bnx2x_phy *phy, | 5064 | static u8 bnx2x_sfp_module_detection(struct bnx2x_phy *phy, |
5025 | struct link_params *params) | 5065 | struct link_params *params) |
5026 | { | 5066 | { |
@@ -5034,7 +5074,8 @@ static u8 bnx2x_sfp_module_detection(struct bnx2x_phy *phy, | |||
5034 | 5074 | ||
5035 | DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n", | 5075 | DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n", |
5036 | params->port); | 5076 | params->port); |
5037 | 5077 | /* Power up module */ | |
5078 | bnx2x_power_sfp_module(params, phy, 1); | ||
5038 | if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) { | 5079 | if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) { |
5039 | DP(NETIF_MSG_LINK, "Failed to get valid module type\n"); | 5080 | DP(NETIF_MSG_LINK, "Failed to get valid module type\n"); |
5040 | return -EINVAL; | 5081 | return -EINVAL; |
@@ -5046,12 +5087,11 @@ static u8 bnx2x_sfp_module_detection(struct bnx2x_phy *phy, | |||
5046 | bnx2x_set_sfp_module_fault_led(params, | 5087 | bnx2x_set_sfp_module_fault_led(params, |
5047 | MISC_REGISTERS_GPIO_HIGH); | 5088 | MISC_REGISTERS_GPIO_HIGH); |
5048 | 5089 | ||
5049 | if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) && | 5090 | /* Check if need to power down the SFP+ module */ |
5050 | ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == | 5091 | if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == |
5051 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN)) { | 5092 | PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) { |
5052 | /* Shutdown SFP+ module */ | ||
5053 | DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n"); | 5093 | DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n"); |
5054 | bnx2x_8727_power_module(bp, phy, 0); | 5094 | bnx2x_power_sfp_module(params, phy, 0); |
5055 | return rc; | 5095 | return rc; |
5056 | } | 5096 | } |
5057 | } else { | 5097 | } else { |
@@ -5059,18 +5099,12 @@ static u8 bnx2x_sfp_module_detection(struct bnx2x_phy *phy, | |||
5059 | bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW); | 5099 | bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW); |
5060 | } | 5100 | } |
5061 | 5101 | ||
5062 | /* power up the SFP module */ | ||
5063 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) | ||
5064 | bnx2x_8727_power_module(bp, phy, 1); | ||
5065 | |||
5066 | /* | 5102 | /* |
5067 | * Check and set limiting mode / LRM mode on 8726. On 8727 it | 5103 | * Check and set limiting mode / LRM mode on 8726. On 8727 it |
5068 | * is done automatically | 5104 | * is done automatically |
5069 | */ | 5105 | */ |
5070 | if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) | 5106 | bnx2x_set_limiting_mode(params, phy, edc_mode); |
5071 | bnx2x_8726_set_limiting_mode(bp, phy, edc_mode); | 5107 | |
5072 | else | ||
5073 | bnx2x_8727_set_limiting_mode(bp, phy, edc_mode); | ||
5074 | /* | 5108 | /* |
5075 | * Enable transmit for this module if the module is approved, or | 5109 | * Enable transmit for this module if the module is approved, or |
5076 | * if unapproved modules should also enable the Tx laser | 5110 | * if unapproved modules should also enable the Tx laser |
@@ -5100,7 +5134,7 @@ void bnx2x_handle_module_detect_int(struct link_params *params) | |||
5100 | 5134 | ||
5101 | /* Call the handling function in case module is detected */ | 5135 | /* Call the handling function in case module is detected */ |
5102 | if (gpio_val == 0) { | 5136 | if (gpio_val == 0) { |
5103 | 5137 | bnx2x_power_sfp_module(params, phy, 1); | |
5104 | bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3, | 5138 | bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3, |
5105 | MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, | 5139 | MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, |
5106 | port); | 5140 | port); |
@@ -7336,6 +7370,7 @@ static u8 bnx2x_populate_ext_phy(struct bnx2x *bp, | |||
7336 | *phy = phy_8727; | 7370 | *phy = phy_8727; |
7337 | phy->flags |= FLAGS_NOC; | 7371 | phy->flags |= FLAGS_NOC; |
7338 | break; | 7372 | break; |
7373 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: | ||
7339 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: | 7374 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: |
7340 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; | 7375 | mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; |
7341 | *phy = phy_8727; | 7376 | *phy = phy_8727; |
@@ -8135,7 +8170,7 @@ static u8 bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[], | |||
8135 | shmem2_base_path, | 8170 | shmem2_base_path, |
8136 | phy_index, chip_id); | 8171 | phy_index, chip_id); |
8137 | break; | 8172 | break; |
8138 | 8173 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: | |
8139 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: | 8174 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: |
8140 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: | 8175 | case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: |
8141 | rc = bnx2x_8727_common_init_phy(bp, shmem_base_path, | 8176 | rc = bnx2x_8727_common_init_phy(bp, shmem_base_path, |