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authorEmil Tantilov <emil.s.tantilov@intel.com>2011-03-15 21:55:55 -0400
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-04-13 22:20:37 -0400
commitc9130180a8dc48943f2a072acec4a53616a1f0ab (patch)
treecdcc703266672f4af4ab38afe3f2bbf4636f8a04 /drivers/net
parent2ea5ea5fc4f4f1daa74708c2a14e364d8474812d (diff)
ixgbe: correct function number for some 82598 parts
Some 82598 parts have LAN0 disabled and LAN1 enabled and the LAN ID bits in Device Status register report the NIC as having only LAN1 as enabled. This causes ixgbe_set_lan_id_multi_port_pcie() to set bus->func = 1 which is incorrect. Force bus->func to 0 when LAN0 is disabled in the EEPROM. Signed-off-by: Emil Tantilov <emil.s.tantilov@intel.com> Tested-by: Evan Swanson <evan.swanson@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/ixgbe/ixgbe_82598.c34
-rw-r--r--drivers/net/ixgbe/ixgbe_type.h5
2 files changed, 38 insertions, 1 deletions
diff --git a/drivers/net/ixgbe/ixgbe_82598.c b/drivers/net/ixgbe/ixgbe_82598.c
index 845c679c8b87..c9b6574cdd72 100644
--- a/drivers/net/ixgbe/ixgbe_82598.c
+++ b/drivers/net/ixgbe/ixgbe_82598.c
@@ -1188,6 +1188,38 @@ out:
1188 return physical_layer; 1188 return physical_layer;
1189} 1189}
1190 1190
1191/**
1192 * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple
1193 * port devices.
1194 * @hw: pointer to the HW structure
1195 *
1196 * Calls common function and corrects issue with some single port devices
1197 * that enable LAN1 but not LAN0.
1198 **/
1199static void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)
1200{
1201 struct ixgbe_bus_info *bus = &hw->bus;
1202 u16 pci_gen = 0;
1203 u16 pci_ctrl2 = 0;
1204
1205 ixgbe_set_lan_id_multi_port_pcie(hw);
1206
1207 /* check if LAN0 is disabled */
1208 hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen);
1209 if ((pci_gen != 0) && (pci_gen != 0xFFFF)) {
1210
1211 hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2);
1212
1213 /* if LAN0 is completely disabled force function to 0 */
1214 if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) &&
1215 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) &&
1216 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) {
1217
1218 bus->func = 0;
1219 }
1220 }
1221}
1222
1191static struct ixgbe_mac_operations mac_ops_82598 = { 1223static struct ixgbe_mac_operations mac_ops_82598 = {
1192 .init_hw = &ixgbe_init_hw_generic, 1224 .init_hw = &ixgbe_init_hw_generic,
1193 .reset_hw = &ixgbe_reset_hw_82598, 1225 .reset_hw = &ixgbe_reset_hw_82598,
@@ -1199,7 +1231,7 @@ static struct ixgbe_mac_operations mac_ops_82598 = {
1199 .get_mac_addr = &ixgbe_get_mac_addr_generic, 1231 .get_mac_addr = &ixgbe_get_mac_addr_generic,
1200 .stop_adapter = &ixgbe_stop_adapter_generic, 1232 .stop_adapter = &ixgbe_stop_adapter_generic,
1201 .get_bus_info = &ixgbe_get_bus_info_generic, 1233 .get_bus_info = &ixgbe_get_bus_info_generic,
1202 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, 1234 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598,
1203 .read_analog_reg8 = &ixgbe_read_analog_reg8_82598, 1235 .read_analog_reg8 = &ixgbe_read_analog_reg8_82598,
1204 .write_analog_reg8 = &ixgbe_write_analog_reg8_82598, 1236 .write_analog_reg8 = &ixgbe_write_analog_reg8_82598,
1205 .setup_link = &ixgbe_setup_mac_link_82598, 1237 .setup_link = &ixgbe_setup_mac_link_82598,
diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h
index 25c1fb7eda06..cd1c2b62ec49 100644
--- a/drivers/net/ixgbe/ixgbe_type.h
+++ b/drivers/net/ixgbe/ixgbe_type.h
@@ -1616,6 +1616,11 @@
1616#define IXGBE_FLUDONE_ATTEMPTS 20000 1616#define IXGBE_FLUDONE_ATTEMPTS 20000
1617#endif 1617#endif
1618 1618
1619#define IXGBE_PCIE_CTRL2 0x5 /* PCIe Control 2 Offset */
1620#define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */
1621#define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */
1622#define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */
1623
1619#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0 1624#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0
1620#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3 1625#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3
1621#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1 1626#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1