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authorStephen Hemminger <shemminger@osdl.org>2005-12-14 18:47:47 -0500
committerJeff Garzik <jgarzik@pobox.com>2005-12-24 09:36:06 -0500
commit2770b5172e9b3d135b16d1e5d8344919ac09319d (patch)
treefc36114e4a8cbe74cb09a2c83482989648fe3cbf /drivers/net
parent7731a4ea1bbb7c9336bcdec8ef4050cf08a35268 (diff)
[PATCH] skge: get rid of Yukon2 defines
Don't need to keep Yukon-2 related definitions around for Skge driver that is only for Yukon-1 and Genesis. Signed-off-by: Stephen Hemminger <shemminger@osdl.org> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/skge.h73
1 files changed, 1 insertions, 72 deletions
diff --git a/drivers/net/skge.h b/drivers/net/skge.h
index ee123c15f545..2efdacc290e5 100644
--- a/drivers/net/skge.h
+++ b/drivers/net/skge.h
@@ -475,18 +475,6 @@ enum {
475 Q_T2 = 0x40, /* 32 bit Test Register 2 */ 475 Q_T2 = 0x40, /* 32 bit Test Register 2 */
476 Q_T3 = 0x44, /* 32 bit Test Register 3 */ 476 Q_T3 = 0x44, /* 32 bit Test Register 3 */
477 477
478/* Yukon-2 */
479 Q_DONE = 0x24, /* 16 bit Done Index (Yukon-2 only) */
480 Q_WM = 0x40, /* 16 bit FIFO Watermark */
481 Q_AL = 0x42, /* 8 bit FIFO Alignment */
482 Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
483 Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */
484 Q_RP = 0x48, /* 8 bit FIFO Read Pointer */
485 Q_RL = 0x4a, /* 8 bit FIFO Read Level */
486 Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */
487 Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */
488 Q_WL = 0x4e, /* 8 bit FIFO Write Level */
489 Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */
490}; 478};
491#define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs)) 479#define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
492 480
@@ -675,22 +663,16 @@ enum {
675 LED_OFF = 1<<0, /* switch LED off */ 663 LED_OFF = 1<<0, /* switch LED off */
676}; 664};
677 665
678/* Receive GMAC FIFO (YUKON and Yukon-2) */ 666/* Receive GMAC FIFO (YUKON) */
679enum { 667enum {
680 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */ 668 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
681 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */ 669 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
682 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */ 670 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
683 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */ 671 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
684 RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */ 672 RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
685 RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
686
687 RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
688 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */ 673 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
689
690 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */ 674 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
691
692 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */ 675 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
693
694 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */ 676 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
695}; 677};
696 678
@@ -855,48 +837,6 @@ enum {
855 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */ 837 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
856}; 838};
857 839
858/* Status BMU Registers (Yukon-2 only)*/
859enum {
860 STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */
861 STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */
862 /* 0x0e85 - 0x0e86: reserved */
863 STAT_LIST_ADDR_LO = 0x0e88,/* 32 bit Status List Start Addr (low) */
864 STAT_LIST_ADDR_HI = 0x0e8c,/* 32 bit Status List Start Addr (high) */
865 STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
866 STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
867 STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
868 STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
869 STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
870 STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */
871
872/* FIFO Control/Status Registers (Yukon-2 only)*/
873 STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
874 STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
875 STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
876 STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */
877 STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
878 STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */
879 STAT_FIFO_ISR_WM = 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
880
881/* Level and ISR Timer Registers (Yukon-2 only)*/
882 STAT_LEV_TIMER_INI = 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
883 STAT_LEV_TIMER_CNT = 0x0eb4,/* 32 bit Level Timer Counter Reg */
884 STAT_LEV_TIMER_CTRL = 0x0eb8,/* 8 bit Level Timer Control Reg */
885 STAT_LEV_TIMER_TEST = 0x0eb9,/* 8 bit Level Timer Test Reg */
886 STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
887 STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
888 STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
889 STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
890 STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
891 STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
892 STAT_ISR_TIMER_CTRL = 0x0ed8,/* 8 bit ISR Timer Control Reg */
893 STAT_ISR_TIMER_TEST = 0x0ed9,/* 8 bit ISR Timer Test Reg */
894
895 ST_LAST_IDX_MASK = 0x007f,/* Last Index Mask */
896 ST_TXRP_IDX_MASK = 0x0fff,/* Tx Report Index Mask */
897 ST_TXTH_IDX_MASK = 0x0fff,/* Tx Threshold Index Mask */
898 ST_WM_IDX_MASK = 0x3f,/* FIFO Watermark Index Mask */
899};
900 840
901enum { 841enum {
902 LINKLED_OFF = 0x01, 842 LINKLED_OFF = 0x01,
@@ -923,8 +863,6 @@ enum {
923 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */ 863 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
924 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */ 864 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
925 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */ 865 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
926 WOL_PATT_PME = 0x0f2a,/* 8 bit WOL PME Match Enable (Yukon-2) */
927 WOL_PATT_ASFM = 0x0f2b,/* 8 bit WOL ASF Match Enable (Yukon-2) */
928 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */ 866 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
929 867
930/* WOL Pattern Length Registers (YUKON only) */ 868/* WOL Pattern Length Registers (YUKON only) */
@@ -1641,15 +1579,6 @@ enum {
1641 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */ 1579 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1642}; 1580};
1643 1581
1644/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1645/***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
1646enum {
1647 PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
1648 PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
1649 PHY_M_MAC_MD_COPPER = 5,/* Copper only */
1650 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
1651};
1652#define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK)
1653 1582
1654/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/ 1583/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1655enum { 1584enum {