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authorPhil Edworthy <PHIL.EDWORTHY@renesas.com>2012-08-14 16:33:29 -0400
committerDavid S. Miller <davem@davemloft.net>2012-08-20 05:16:54 -0400
commitd0418bb7123f44b23d69ac349eec7daf9103472f (patch)
tree18b922d5e0b574abe897aea1a2c224c25c38f158 /drivers/net
parent61abcb7b058853900a3092f2c21988a444e3aaea (diff)
net: sh_eth: Add eth support for R8A7779 device
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/ethernet/renesas/Kconfig4
-rw-r--r--drivers/net/ethernet/renesas/sh_eth.c11
2 files changed, 10 insertions, 5 deletions
diff --git a/drivers/net/ethernet/renesas/Kconfig b/drivers/net/ethernet/renesas/Kconfig
index 46df3a04030c..24c2305d7948 100644
--- a/drivers/net/ethernet/renesas/Kconfig
+++ b/drivers/net/ethernet/renesas/Kconfig
@@ -8,7 +8,7 @@ config SH_ETH
8 (CPU_SUBTYPE_SH7710 || CPU_SUBTYPE_SH7712 || \ 8 (CPU_SUBTYPE_SH7710 || CPU_SUBTYPE_SH7712 || \
9 CPU_SUBTYPE_SH7763 || CPU_SUBTYPE_SH7619 || \ 9 CPU_SUBTYPE_SH7763 || CPU_SUBTYPE_SH7619 || \
10 CPU_SUBTYPE_SH7724 || CPU_SUBTYPE_SH7734 || \ 10 CPU_SUBTYPE_SH7724 || CPU_SUBTYPE_SH7734 || \
11 CPU_SUBTYPE_SH7757 || ARCH_R8A7740) 11 CPU_SUBTYPE_SH7757 || ARCH_R8A7740 || ARCH_R8A7779)
12 select CRC32 12 select CRC32
13 select NET_CORE 13 select NET_CORE
14 select MII 14 select MII
@@ -18,4 +18,4 @@ config SH_ETH
18 Renesas SuperH Ethernet device driver. 18 Renesas SuperH Ethernet device driver.
19 This driver supporting CPUs are: 19 This driver supporting CPUs are:
20 - SH7619, SH7710, SH7712, SH7724, SH7734, SH7763, SH7757, 20 - SH7619, SH7710, SH7712, SH7724, SH7734, SH7763, SH7757,
21 and R8A7740. 21 R8A7740 and R8A7779.
diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
index af0b867a6cf6..bad8f2eec9b4 100644
--- a/drivers/net/ethernet/renesas/sh_eth.c
+++ b/drivers/net/ethernet/renesas/sh_eth.c
@@ -78,7 +78,7 @@ static void sh_eth_select_mii(struct net_device *ndev)
78#endif 78#endif
79 79
80/* There is CPU dependent code */ 80/* There is CPU dependent code */
81#if defined(CONFIG_CPU_SUBTYPE_SH7724) 81#if defined(CONFIG_CPU_SUBTYPE_SH7724) || defined(CONFIG_ARCH_R8A7779)
82#define SH_ETH_RESET_DEFAULT 1 82#define SH_ETH_RESET_DEFAULT 1
83static void sh_eth_set_duplex(struct net_device *ndev) 83static void sh_eth_set_duplex(struct net_device *ndev)
84{ 84{
@@ -93,13 +93,18 @@ static void sh_eth_set_duplex(struct net_device *ndev)
93static void sh_eth_set_rate(struct net_device *ndev) 93static void sh_eth_set_rate(struct net_device *ndev)
94{ 94{
95 struct sh_eth_private *mdp = netdev_priv(ndev); 95 struct sh_eth_private *mdp = netdev_priv(ndev);
96 unsigned int bits = ECMR_RTM;
97
98#if defined(CONFIG_ARCH_R8A7779)
99 bits |= ECMR_ELB;
100#endif
96 101
97 switch (mdp->speed) { 102 switch (mdp->speed) {
98 case 10: /* 10BASE */ 103 case 10: /* 10BASE */
99 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR); 104 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~bits, ECMR);
100 break; 105 break;
101 case 100:/* 100BASE */ 106 case 100:/* 100BASE */
102 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR); 107 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | bits, ECMR);
103 break; 108 break;
104 default: 109 default:
105 break; 110 break;