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authorRasesh Mody <rmody@brocade.com>2010-08-23 23:24:12 -0400
committerDavid S. Miller <davem@davemloft.net>2010-08-23 23:24:12 -0400
commit8b230ed8ec96c933047dd0625cf95f739e4939a6 (patch)
tree517e761a804a2b2f9631b755abcbf525240b916e /drivers/net
parent231cc2aaf14bad3b2325be0b19b8385ff5e75485 (diff)
bna: Brocade 10Gb Ethernet device driver
This is patch 1/6 which contains linux driver source for Brocade's BR1010/BR1020 10Gb CEE capable ethernet adapter. Signed-off-by: Debashis Dutt <ddutt@brocade.com> Signed-off-by: Rasesh Mody <rmody@brocade.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/Kconfig14
-rw-r--r--drivers/net/Makefile1
-rw-r--r--drivers/net/bna/Makefile11
-rw-r--r--drivers/net/bna/bfa_cee.c407
-rw-r--r--drivers/net/bna/bfa_cee.h72
-rw-r--r--drivers/net/bna/bfa_defs.h243
-rw-r--r--drivers/net/bna/bfa_defs_cna.h223
-rw-r--r--drivers/net/bna/bfa_defs_mfg_comm.h244
-rw-r--r--drivers/net/bna/bfa_defs_status.h216
-rw-r--r--drivers/net/bna/bfa_ioc.c1839
-rw-r--r--drivers/net/bna/bfa_ioc.h343
-rw-r--r--drivers/net/bna/bfa_ioc_ct.c391
-rw-r--r--drivers/net/bna/bfa_sm.h88
-rw-r--r--drivers/net/bna/bfa_wc.h69
-rw-r--r--drivers/net/bna/bfi.h392
-rw-r--r--drivers/net/bna/bfi_cna.h199
-rw-r--r--drivers/net/bna/bfi_ctreg.h637
-rw-r--r--drivers/net/bna/bfi_ll.h438
-rw-r--r--drivers/net/bna/bna.h654
-rw-r--r--drivers/net/bna/bna_ctrl.c3626
-rw-r--r--drivers/net/bna/bna_hw.h1491
-rw-r--r--drivers/net/bna/bna_txrx.c4209
-rw-r--r--drivers/net/bna/bna_types.h1128
-rw-r--r--drivers/net/bna/bnad.c3270
-rw-r--r--drivers/net/bna/bnad.h334
-rw-r--r--drivers/net/bna/bnad_ethtool.c1282
-rw-r--r--drivers/net/bna/cna.h81
-rw-r--r--drivers/net/bna/cna_fwimg.c64
28 files changed, 21966 insertions, 0 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 85485287192a..53c4810b119e 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2869,6 +2869,20 @@ config QLGE
2869 To compile this driver as a module, choose M here: the module 2869 To compile this driver as a module, choose M here: the module
2870 will be called qlge. 2870 will be called qlge.
2871 2871
2872config BNA
2873 tristate "Brocade 1010/1020 10Gb Ethernet Driver support"
2874 depends on PCI
2875 ---help---
2876 This driver supports Brocade 1010/1020 10Gb CEE capable Ethernet
2877 cards.
2878 To compile this driver as a module, choose M here: the module
2879 will be called bna.
2880
2881 For general information and support, go to the Brocade support
2882 website at:
2883
2884 <http://support.brocade.com>
2885
2872source "drivers/net/sfc/Kconfig" 2886source "drivers/net/sfc/Kconfig"
2873 2887
2874source "drivers/net/benet/Kconfig" 2888source "drivers/net/benet/Kconfig"
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index f34b3baf7ee6..18a277709a2a 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_ENIC) += enic/
34obj-$(CONFIG_JME) += jme.o 34obj-$(CONFIG_JME) += jme.o
35obj-$(CONFIG_BE2NET) += benet/ 35obj-$(CONFIG_BE2NET) += benet/
36obj-$(CONFIG_VMXNET3) += vmxnet3/ 36obj-$(CONFIG_VMXNET3) += vmxnet3/
37obj-$(CONFIG_BNA) += bna/
37 38
38gianfar_driver-objs := gianfar.o \ 39gianfar_driver-objs := gianfar.o \
39 gianfar_ethtool.o \ 40 gianfar_ethtool.o \
diff --git a/drivers/net/bna/Makefile b/drivers/net/bna/Makefile
new file mode 100644
index 000000000000..a5d604de7fea
--- /dev/null
+++ b/drivers/net/bna/Makefile
@@ -0,0 +1,11 @@
1#
2# Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
3# All rights reserved.
4#
5
6obj-$(CONFIG_BNA) += bna.o
7
8bna-objs := bnad.o bnad_ethtool.o bna_ctrl.o bna_txrx.o
9bna-objs += bfa_ioc.o bfa_ioc_ct.o bfa_cee.o cna_fwimg.o
10
11EXTRA_CFLAGS := -Idrivers/net/bna
diff --git a/drivers/net/bna/bfa_cee.c b/drivers/net/bna/bfa_cee.c
new file mode 100644
index 000000000000..1545fc9720f8
--- /dev/null
+++ b/drivers/net/bna/bfa_cee.c
@@ -0,0 +1,407 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18
19#include "bfa_defs_cna.h"
20#include "cna.h"
21#include "bfa_cee.h"
22#include "bfi_cna.h"
23#include "bfa_ioc.h"
24
25#define bfa_ioc_portid(__ioc) ((__ioc)->port_id)
26#define bfa_lpuid(__arg) bfa_ioc_portid(&(__arg)->ioc)
27
28static void bfa_cee_format_lldp_cfg(struct bfa_cee_lldp_cfg *lldp_cfg);
29static void bfa_cee_format_cee_cfg(void *buffer);
30
31static void
32bfa_cee_format_cee_cfg(void *buffer)
33{
34 struct bfa_cee_attr *cee_cfg = buffer;
35 bfa_cee_format_lldp_cfg(&cee_cfg->lldp_remote);
36}
37
38static void
39bfa_cee_stats_swap(struct bfa_cee_stats *stats)
40{
41 u32 *buffer = (u32 *)stats;
42 int i;
43
44 for (i = 0; i < (sizeof(struct bfa_cee_stats) / sizeof(u32));
45 i++) {
46 buffer[i] = ntohl(buffer[i]);
47 }
48}
49
50static void
51bfa_cee_format_lldp_cfg(struct bfa_cee_lldp_cfg *lldp_cfg)
52{
53 lldp_cfg->time_to_live =
54 ntohs(lldp_cfg->time_to_live);
55 lldp_cfg->enabled_system_cap =
56 ntohs(lldp_cfg->enabled_system_cap);
57}
58
59/**
60 * bfa_cee_attr_meminfo()
61 *
62 * @brief Returns the size of the DMA memory needed by CEE attributes
63 *
64 * @param[in] void
65 *
66 * @return Size of DMA region
67 */
68static u32
69bfa_cee_attr_meminfo(void)
70{
71 return roundup(sizeof(struct bfa_cee_attr), BFA_DMA_ALIGN_SZ);
72}
73/**
74 * bfa_cee_stats_meminfo()
75 *
76 * @brief Returns the size of the DMA memory needed by CEE stats
77 *
78 * @param[in] void
79 *
80 * @return Size of DMA region
81 */
82static u32
83bfa_cee_stats_meminfo(void)
84{
85 return roundup(sizeof(struct bfa_cee_stats), BFA_DMA_ALIGN_SZ);
86}
87
88/**
89 * bfa_cee_get_attr_isr()
90 *
91 * @brief CEE ISR for get-attributes responses from f/w
92 *
93 * @param[in] cee - Pointer to the CEE module
94 * status - Return status from the f/w
95 *
96 * @return void
97 */
98static void
99bfa_cee_get_attr_isr(struct bfa_cee *cee, enum bfa_status status)
100{
101 cee->get_attr_status = status;
102 if (status == BFA_STATUS_OK) {
103 memcpy(cee->attr, cee->attr_dma.kva,
104 sizeof(struct bfa_cee_attr));
105 bfa_cee_format_cee_cfg(cee->attr);
106 }
107 cee->get_attr_pending = false;
108 if (cee->cbfn.get_attr_cbfn)
109 cee->cbfn.get_attr_cbfn(cee->cbfn.get_attr_cbarg, status);
110}
111
112/**
113 * bfa_cee_get_attr_isr()
114 *
115 * @brief CEE ISR for get-stats responses from f/w
116 *
117 * @param[in] cee - Pointer to the CEE module
118 * status - Return status from the f/w
119 *
120 * @return void
121 */
122static void
123bfa_cee_get_stats_isr(struct bfa_cee *cee, enum bfa_status status)
124{
125 cee->get_stats_status = status;
126 if (status == BFA_STATUS_OK) {
127 memcpy(cee->stats, cee->stats_dma.kva,
128 sizeof(struct bfa_cee_stats));
129 bfa_cee_stats_swap(cee->stats);
130 }
131 cee->get_stats_pending = false;
132 if (cee->cbfn.get_stats_cbfn)
133 cee->cbfn.get_stats_cbfn(cee->cbfn.get_stats_cbarg, status);
134}
135
136/**
137 * bfa_cee_get_attr_isr()
138 *
139 * @brief CEE ISR for reset-stats responses from f/w
140 *
141 * @param[in] cee - Pointer to the CEE module
142 * status - Return status from the f/w
143 *
144 * @return void
145 */
146static void
147bfa_cee_reset_stats_isr(struct bfa_cee *cee, enum bfa_status status)
148{
149 cee->reset_stats_status = status;
150 cee->reset_stats_pending = false;
151 if (cee->cbfn.reset_stats_cbfn)
152 cee->cbfn.reset_stats_cbfn(cee->cbfn.reset_stats_cbarg, status);
153}
154/**
155 * bfa_cee_meminfo()
156 *
157 * @brief Returns the size of the DMA memory needed by CEE module
158 *
159 * @param[in] void
160 *
161 * @return Size of DMA region
162 */
163u32
164bfa_cee_meminfo(void)
165{
166 return bfa_cee_attr_meminfo() + bfa_cee_stats_meminfo();
167}
168
169/**
170 * bfa_cee_mem_claim()
171 *
172 * @brief Initialized CEE DMA Memory
173 *
174 * @param[in] cee CEE module pointer
175 * dma_kva Kernel Virtual Address of CEE DMA Memory
176 * dma_pa Physical Address of CEE DMA Memory
177 *
178 * @return void
179 */
180void
181bfa_cee_mem_claim(struct bfa_cee *cee, u8 *dma_kva, u64 dma_pa)
182{
183 cee->attr_dma.kva = dma_kva;
184 cee->attr_dma.pa = dma_pa;
185 cee->stats_dma.kva = dma_kva + bfa_cee_attr_meminfo();
186 cee->stats_dma.pa = dma_pa + bfa_cee_attr_meminfo();
187 cee->attr = (struct bfa_cee_attr *) dma_kva;
188 cee->stats = (struct bfa_cee_stats *)
189 (dma_kva + bfa_cee_attr_meminfo());
190}
191
192/**
193 * bfa_cee_get_attr()
194 *
195 * @brief
196 * Send the request to the f/w to fetch CEE attributes.
197 *
198 * @param[in] Pointer to the CEE module data structure.
199 *
200 * @return Status
201 */
202
203enum bfa_status
204bfa_cee_get_attr(struct bfa_cee *cee, struct bfa_cee_attr *attr,
205 bfa_cee_get_attr_cbfn_t cbfn, void *cbarg)
206{
207 struct bfi_cee_get_req *cmd;
208
209 BUG_ON(!((cee != NULL) && (cee->ioc != NULL)));
210 if (!bfa_ioc_is_operational(cee->ioc))
211 return BFA_STATUS_IOC_FAILURE;
212 if (cee->get_attr_pending == true)
213 return BFA_STATUS_DEVBUSY;
214 cee->get_attr_pending = true;
215 cmd = (struct bfi_cee_get_req *) cee->get_cfg_mb.msg;
216 cee->attr = attr;
217 cee->cbfn.get_attr_cbfn = cbfn;
218 cee->cbfn.get_attr_cbarg = cbarg;
219 bfi_h2i_set(cmd->mh, BFI_MC_CEE, BFI_CEE_H2I_GET_CFG_REQ,
220 bfa_ioc_portid(cee->ioc));
221 bfa_dma_be_addr_set(cmd->dma_addr, cee->attr_dma.pa);
222 bfa_ioc_mbox_queue(cee->ioc, &cee->get_cfg_mb);
223
224 return BFA_STATUS_OK;
225}
226
227/**
228 * bfa_cee_get_stats()
229 *
230 * @brief
231 * Send the request to the f/w to fetch CEE statistics.
232 *
233 * @param[in] Pointer to the CEE module data structure.
234 *
235 * @return Status
236 */
237
238enum bfa_status
239bfa_cee_get_stats(struct bfa_cee *cee, struct bfa_cee_stats *stats,
240 bfa_cee_get_stats_cbfn_t cbfn, void *cbarg)
241{
242 struct bfi_cee_get_req *cmd;
243
244 BUG_ON(!((cee != NULL) && (cee->ioc != NULL)));
245
246 if (!bfa_ioc_is_operational(cee->ioc))
247 return BFA_STATUS_IOC_FAILURE;
248 if (cee->get_stats_pending == true)
249 return BFA_STATUS_DEVBUSY;
250 cee->get_stats_pending = true;
251 cmd = (struct bfi_cee_get_req *) cee->get_stats_mb.msg;
252 cee->stats = stats;
253 cee->cbfn.get_stats_cbfn = cbfn;
254 cee->cbfn.get_stats_cbarg = cbarg;
255 bfi_h2i_set(cmd->mh, BFI_MC_CEE, BFI_CEE_H2I_GET_STATS_REQ,
256 bfa_ioc_portid(cee->ioc));
257 bfa_dma_be_addr_set(cmd->dma_addr, cee->stats_dma.pa);
258 bfa_ioc_mbox_queue(cee->ioc, &cee->get_stats_mb);
259
260 return BFA_STATUS_OK;
261}
262
263/**
264 * bfa_cee_reset_stats()
265 *
266 * @brief Clears CEE Stats in the f/w.
267 *
268 * @param[in] Pointer to the CEE module data structure.
269 *
270 * @return Status
271 */
272
273enum bfa_status
274bfa_cee_reset_stats(struct bfa_cee *cee, bfa_cee_reset_stats_cbfn_t cbfn,
275 void *cbarg)
276{
277 struct bfi_cee_reset_stats *cmd;
278
279 BUG_ON(!((cee != NULL) && (cee->ioc != NULL)));
280 if (!bfa_ioc_is_operational(cee->ioc))
281 return BFA_STATUS_IOC_FAILURE;
282 if (cee->reset_stats_pending == true)
283 return BFA_STATUS_DEVBUSY;
284 cee->reset_stats_pending = true;
285 cmd = (struct bfi_cee_reset_stats *) cee->reset_stats_mb.msg;
286 cee->cbfn.reset_stats_cbfn = cbfn;
287 cee->cbfn.reset_stats_cbarg = cbarg;
288 bfi_h2i_set(cmd->mh, BFI_MC_CEE, BFI_CEE_H2I_RESET_STATS,
289 bfa_ioc_portid(cee->ioc));
290 bfa_ioc_mbox_queue(cee->ioc, &cee->reset_stats_mb);
291 return BFA_STATUS_OK;
292}
293
294/**
295 * bfa_cee_isrs()
296 *
297 * @brief Handles Mail-box interrupts for CEE module.
298 *
299 * @param[in] Pointer to the CEE module data structure.
300 *
301 * @return void
302 */
303
304void
305bfa_cee_isr(void *cbarg, struct bfi_mbmsg *m)
306{
307 union bfi_cee_i2h_msg_u *msg;
308 struct bfi_cee_get_rsp *get_rsp;
309 struct bfa_cee *cee = (struct bfa_cee *) cbarg;
310 msg = (union bfi_cee_i2h_msg_u *) m;
311 get_rsp = (struct bfi_cee_get_rsp *) m;
312 switch (msg->mh.msg_id) {
313 case BFI_CEE_I2H_GET_CFG_RSP:
314 bfa_cee_get_attr_isr(cee, get_rsp->cmd_status);
315 break;
316 case BFI_CEE_I2H_GET_STATS_RSP:
317 bfa_cee_get_stats_isr(cee, get_rsp->cmd_status);
318 break;
319 case BFI_CEE_I2H_RESET_STATS_RSP:
320 bfa_cee_reset_stats_isr(cee, get_rsp->cmd_status);
321 break;
322 default:
323 BUG_ON(1);
324 }
325}
326
327/**
328 * bfa_cee_hbfail()
329 *
330 * @brief CEE module heart-beat failure handler.
331 *
332 * @param[in] Pointer to the CEE module data structure.
333 *
334 * @return void
335 */
336
337void
338bfa_cee_hbfail(void *arg)
339{
340 struct bfa_cee *cee;
341 cee = (struct bfa_cee *) arg;
342
343 if (cee->get_attr_pending == true) {
344 cee->get_attr_status = BFA_STATUS_FAILED;
345 cee->get_attr_pending = false;
346 if (cee->cbfn.get_attr_cbfn) {
347 cee->cbfn.get_attr_cbfn(cee->cbfn.get_attr_cbarg,
348 BFA_STATUS_FAILED);
349 }
350 }
351 if (cee->get_stats_pending == true) {
352 cee->get_stats_status = BFA_STATUS_FAILED;
353 cee->get_stats_pending = false;
354 if (cee->cbfn.get_stats_cbfn) {
355 cee->cbfn.get_stats_cbfn(cee->cbfn.get_stats_cbarg,
356 BFA_STATUS_FAILED);
357 }
358 }
359 if (cee->reset_stats_pending == true) {
360 cee->reset_stats_status = BFA_STATUS_FAILED;
361 cee->reset_stats_pending = false;
362 if (cee->cbfn.reset_stats_cbfn) {
363 cee->cbfn.reset_stats_cbfn(cee->cbfn.reset_stats_cbarg,
364 BFA_STATUS_FAILED);
365 }
366 }
367}
368
369/**
370 * bfa_cee_attach()
371 *
372 * @brief CEE module-attach API
373 *
374 * @param[in] cee - Pointer to the CEE module data structure
375 * ioc - Pointer to the ioc module data structure
376 * dev - Pointer to the device driver module data structure
377 * The device driver specific mbox ISR functions have
378 * this pointer as one of the parameters.
379 *
380 * @return void
381 */
382void
383bfa_cee_attach(struct bfa_cee *cee, struct bfa_ioc *ioc,
384 void *dev)
385{
386 BUG_ON(!(cee != NULL));
387 cee->dev = dev;
388 cee->ioc = ioc;
389
390 bfa_ioc_mbox_regisr(cee->ioc, BFI_MC_CEE, bfa_cee_isr, cee);
391 bfa_ioc_hbfail_init(&cee->hbfail, bfa_cee_hbfail, cee);
392 bfa_ioc_hbfail_register(cee->ioc, &cee->hbfail);
393}
394
395/**
396 * bfa_cee_detach()
397 *
398 * @brief CEE module-detach API
399 *
400 * @param[in] cee - Pointer to the CEE module data structure
401 *
402 * @return void
403 */
404void
405bfa_cee_detach(struct bfa_cee *cee)
406{
407}
diff --git a/drivers/net/bna/bfa_cee.h b/drivers/net/bna/bfa_cee.h
new file mode 100644
index 000000000000..1208cadeceed
--- /dev/null
+++ b/drivers/net/bna/bfa_cee.h
@@ -0,0 +1,72 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18
19#ifndef __BFA_CEE_H__
20#define __BFA_CEE_H__
21
22#include "bfa_defs_cna.h"
23#include "bfa_ioc.h"
24
25typedef void (*bfa_cee_get_attr_cbfn_t) (void *dev, enum bfa_status status);
26typedef void (*bfa_cee_get_stats_cbfn_t) (void *dev, enum bfa_status status);
27typedef void (*bfa_cee_reset_stats_cbfn_t) (void *dev, enum bfa_status status);
28typedef void (*bfa_cee_hbfail_cbfn_t) (void *dev, enum bfa_status status);
29
30struct bfa_cee_cbfn {
31 bfa_cee_get_attr_cbfn_t get_attr_cbfn;
32 void *get_attr_cbarg;
33 bfa_cee_get_stats_cbfn_t get_stats_cbfn;
34 void *get_stats_cbarg;
35 bfa_cee_reset_stats_cbfn_t reset_stats_cbfn;
36 void *reset_stats_cbarg;
37};
38
39struct bfa_cee {
40 void *dev;
41 bool get_attr_pending;
42 bool get_stats_pending;
43 bool reset_stats_pending;
44 enum bfa_status get_attr_status;
45 enum bfa_status get_stats_status;
46 enum bfa_status reset_stats_status;
47 struct bfa_cee_cbfn cbfn;
48 struct bfa_ioc_hbfail_notify hbfail;
49 struct bfa_cee_attr *attr;
50 struct bfa_cee_stats *stats;
51 struct bfa_dma attr_dma;
52 struct bfa_dma stats_dma;
53 struct bfa_ioc *ioc;
54 struct bfa_mbox_cmd get_cfg_mb;
55 struct bfa_mbox_cmd get_stats_mb;
56 struct bfa_mbox_cmd reset_stats_mb;
57};
58
59u32 bfa_cee_meminfo(void);
60void bfa_cee_mem_claim(struct bfa_cee *cee, u8 *dma_kva,
61 u64 dma_pa);
62void bfa_cee_attach(struct bfa_cee *cee, struct bfa_ioc *ioc, void *dev);
63void bfa_cee_detach(struct bfa_cee *cee);
64enum bfa_status bfa_cee_get_attr(struct bfa_cee *cee,
65 struct bfa_cee_attr *attr, bfa_cee_get_attr_cbfn_t cbfn, void *cbarg);
66enum bfa_status bfa_cee_get_stats(struct bfa_cee *cee,
67 struct bfa_cee_stats *stats, bfa_cee_get_stats_cbfn_t cbfn,
68 void *cbarg);
69enum bfa_status bfa_cee_reset_stats(struct bfa_cee *cee,
70 bfa_cee_reset_stats_cbfn_t cbfn, void *cbarg);
71
72#endif /* __BFA_CEE_H__ */
diff --git a/drivers/net/bna/bfa_defs.h b/drivers/net/bna/bfa_defs.h
new file mode 100644
index 000000000000..29c1b8de2c2d
--- /dev/null
+++ b/drivers/net/bna/bfa_defs.h
@@ -0,0 +1,243 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18
19#ifndef __BFA_DEFS_H__
20#define __BFA_DEFS_H__
21
22#include "cna.h"
23#include "bfa_defs_status.h"
24#include "bfa_defs_mfg_comm.h"
25
26#define BFA_STRING_32 32
27#define BFA_VERSION_LEN 64
28
29/**
30 * ---------------------- adapter definitions ------------
31 */
32
33/**
34 * BFA adapter level attributes.
35 */
36enum {
37 BFA_ADAPTER_SERIAL_NUM_LEN = STRSZ(BFA_MFG_SERIALNUM_SIZE),
38 /*
39 *!< adapter serial num length
40 */
41 BFA_ADAPTER_MODEL_NAME_LEN = 16, /*!< model name length */
42 BFA_ADAPTER_MODEL_DESCR_LEN = 128, /*!< model description length */
43 BFA_ADAPTER_MFG_NAME_LEN = 8, /*!< manufacturer name length */
44 BFA_ADAPTER_SYM_NAME_LEN = 64, /*!< adapter symbolic name length */
45 BFA_ADAPTER_OS_TYPE_LEN = 64, /*!< adapter os type length */
46};
47
48struct bfa_adapter_attr {
49 char manufacturer[BFA_ADAPTER_MFG_NAME_LEN];
50 char serial_num[BFA_ADAPTER_SERIAL_NUM_LEN];
51 u32 card_type;
52 char model[BFA_ADAPTER_MODEL_NAME_LEN];
53 char model_descr[BFA_ADAPTER_MODEL_DESCR_LEN];
54 u64 pwwn;
55 char node_symname[FC_SYMNAME_MAX];
56 char hw_ver[BFA_VERSION_LEN];
57 char fw_ver[BFA_VERSION_LEN];
58 char optrom_ver[BFA_VERSION_LEN];
59 char os_type[BFA_ADAPTER_OS_TYPE_LEN];
60 struct bfa_mfg_vpd vpd;
61 struct mac mac;
62
63 u8 nports;
64 u8 max_speed;
65 u8 prototype;
66 char asic_rev;
67
68 u8 pcie_gen;
69 u8 pcie_lanes_orig;
70 u8 pcie_lanes;
71 u8 cna_capable;
72
73 u8 is_mezz;
74 u8 trunk_capable;
75};
76
77/**
78 * ---------------------- IOC definitions ------------
79 */
80
81enum {
82 BFA_IOC_DRIVER_LEN = 16,
83 BFA_IOC_CHIP_REV_LEN = 8,
84};
85
86/**
87 * Driver and firmware versions.
88 */
89struct bfa_ioc_driver_attr {
90 char driver[BFA_IOC_DRIVER_LEN]; /*!< driver name */
91 char driver_ver[BFA_VERSION_LEN]; /*!< driver version */
92 char fw_ver[BFA_VERSION_LEN]; /*!< firmware version */
93 char bios_ver[BFA_VERSION_LEN]; /*!< bios version */
94 char efi_ver[BFA_VERSION_LEN]; /*!< EFI version */
95 char ob_ver[BFA_VERSION_LEN]; /*!< openboot version */
96};
97
98/**
99 * IOC PCI device attributes
100 */
101struct bfa_ioc_pci_attr {
102 u16 vendor_id; /*!< PCI vendor ID */
103 u16 device_id; /*!< PCI device ID */
104 u16 ssid; /*!< subsystem ID */
105 u16 ssvid; /*!< subsystem vendor ID */
106 u32 pcifn; /*!< PCI device function */
107 u32 rsvd; /* padding */
108 char chip_rev[BFA_IOC_CHIP_REV_LEN]; /*!< chip revision */
109};
110
111/**
112 * IOC states
113 */
114enum bfa_ioc_state {
115 BFA_IOC_RESET = 1, /*!< IOC is in reset state */
116 BFA_IOC_SEMWAIT = 2, /*!< Waiting for IOC h/w semaphore */
117 BFA_IOC_HWINIT = 3, /*!< IOC h/w is being initialized */
118 BFA_IOC_GETATTR = 4, /*!< IOC is being configured */
119 BFA_IOC_OPERATIONAL = 5, /*!< IOC is operational */
120 BFA_IOC_INITFAIL = 6, /*!< IOC hardware failure */
121 BFA_IOC_HBFAIL = 7, /*!< IOC heart-beat failure */
122 BFA_IOC_DISABLING = 8, /*!< IOC is being disabled */
123 BFA_IOC_DISABLED = 9, /*!< IOC is disabled */
124 BFA_IOC_FWMISMATCH = 10, /*!< IOC f/w different from drivers */
125};
126
127/**
128 * IOC firmware stats
129 */
130struct bfa_fw_ioc_stats {
131 u32 enable_reqs;
132 u32 disable_reqs;
133 u32 get_attr_reqs;
134 u32 dbg_sync;
135 u32 dbg_dump;
136 u32 unknown_reqs;
137};
138
139/**
140 * IOC driver stats
141 */
142struct bfa_ioc_drv_stats {
143 u32 ioc_isrs;
144 u32 ioc_enables;
145 u32 ioc_disables;
146 u32 ioc_hbfails;
147 u32 ioc_boots;
148 u32 stats_tmos;
149 u32 hb_count;
150 u32 disable_reqs;
151 u32 enable_reqs;
152 u32 disable_replies;
153 u32 enable_replies;
154};
155
156/**
157 * IOC statistics
158 */
159struct bfa_ioc_stats {
160 struct bfa_ioc_drv_stats drv_stats; /*!< driver IOC stats */
161 struct bfa_fw_ioc_stats fw_stats; /*!< firmware IOC stats */
162};
163
164enum bfa_ioc_type {
165 BFA_IOC_TYPE_FC = 1,
166 BFA_IOC_TYPE_FCoE = 2,
167 BFA_IOC_TYPE_LL = 3,
168};
169
170/**
171 * IOC attributes returned in queries
172 */
173struct bfa_ioc_attr {
174 enum bfa_ioc_type ioc_type;
175 enum bfa_ioc_state state; /*!< IOC state */
176 struct bfa_adapter_attr adapter_attr; /*!< HBA attributes */
177 struct bfa_ioc_driver_attr driver_attr; /*!< driver attr */
178 struct bfa_ioc_pci_attr pci_attr;
179 u8 port_id; /*!< port number */
180 u8 rsvd[7]; /*!< 64bit align */
181};
182
183/**
184 * ---------------------- mfg definitions ------------
185 */
186
187/**
188 * Checksum size
189 */
190#define BFA_MFG_CHKSUM_SIZE 16
191
192#define BFA_MFG_PARTNUM_SIZE 14
193#define BFA_MFG_SUPPLIER_ID_SIZE 10
194#define BFA_MFG_SUPPLIER_PARTNUM_SIZE 20
195#define BFA_MFG_SUPPLIER_SERIALNUM_SIZE 20
196#define BFA_MFG_SUPPLIER_REVISION_SIZE 4
197
198#pragma pack(1)
199
200/**
201 * @brief BFA adapter manufacturing block definition.
202 *
203 * All numerical fields are in big-endian format.
204 */
205struct bfa_mfg_block {
206 u8 version; /*!< manufacturing block version */
207 u8 mfg_sig[3]; /*!< characters 'M', 'F', 'G' */
208 u16 mfgsize; /*!< mfg block size */
209 u16 u16_chksum; /*!< old u16 checksum */
210 char brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)];
211 char brcd_partnum[STRSZ(BFA_MFG_PARTNUM_SIZE)];
212 u8 mfg_day; /*!< manufacturing day */
213 u8 mfg_month; /*!< manufacturing month */
214 u16 mfg_year; /*!< manufacturing year */
215 u64 mfg_wwn; /*!< wwn base for this adapter */
216 u8 num_wwn; /*!< number of wwns assigned */
217 u8 mfg_speeds; /*!< speeds allowed for this adapter */
218 u8 rsv[2];
219 char supplier_id[STRSZ(BFA_MFG_SUPPLIER_ID_SIZE)];
220 char supplier_partnum[STRSZ(BFA_MFG_SUPPLIER_PARTNUM_SIZE)];
221 char
222 supplier_serialnum[STRSZ(BFA_MFG_SUPPLIER_SERIALNUM_SIZE)];
223 char
224 supplier_revision[STRSZ(BFA_MFG_SUPPLIER_REVISION_SIZE)];
225 mac_t mfg_mac; /*!< mac address */
226 u8 num_mac; /*!< number of mac addresses */
227 u8 rsv2;
228 u32 mfg_type; /*!< card type */
229 u8 rsv3[108];
230 u8 md5_chksum[BFA_MFG_CHKSUM_SIZE]; /*!< md5 checksum */
231};
232
233#pragma pack()
234
235/**
236 * ---------------------- pci definitions ------------
237 */
238
239#define bfa_asic_id_ct(devid) \
240 ((devid) == PCI_DEVICE_ID_BROCADE_CT || \
241 (devid) == PCI_DEVICE_ID_BROCADE_CT_FC)
242
243#endif /* __BFA_DEFS_H__ */
diff --git a/drivers/net/bna/bfa_defs_cna.h b/drivers/net/bna/bfa_defs_cna.h
new file mode 100644
index 000000000000..7e0a9187bdd5
--- /dev/null
+++ b/drivers/net/bna/bfa_defs_cna.h
@@ -0,0 +1,223 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18
19#ifndef __BFA_DEFS_CNA_H__
20#define __BFA_DEFS_CNA_H__
21
22#include "bfa_defs.h"
23
24/**
25 * @brief
26 * FC physical port statistics.
27 */
28struct bfa_port_fc_stats {
29 u64 secs_reset; /*!< Seconds since stats is reset */
30 u64 tx_frames; /*!< Tx frames */
31 u64 tx_words; /*!< Tx words */
32 u64 tx_lip; /*!< Tx LIP */
33 u64 tx_nos; /*!< Tx NOS */
34 u64 tx_ols; /*!< Tx OLS */
35 u64 tx_lr; /*!< Tx LR */
36 u64 tx_lrr; /*!< Tx LRR */
37 u64 rx_frames; /*!< Rx frames */
38 u64 rx_words; /*!< Rx words */
39 u64 lip_count; /*!< Rx LIP */
40 u64 nos_count; /*!< Rx NOS */
41 u64 ols_count; /*!< Rx OLS */
42 u64 lr_count; /*!< Rx LR */
43 u64 lrr_count; /*!< Rx LRR */
44 u64 invalid_crcs; /*!< Rx CRC err frames */
45 u64 invalid_crc_gd_eof; /*!< Rx CRC err good EOF frames */
46 u64 undersized_frm; /*!< Rx undersized frames */
47 u64 oversized_frm; /*!< Rx oversized frames */
48 u64 bad_eof_frm; /*!< Rx frames with bad EOF */
49 u64 error_frames; /*!< Errored frames */
50 u64 dropped_frames; /*!< Dropped frames */
51 u64 link_failures; /*!< Link Failure (LF) count */
52 u64 loss_of_syncs; /*!< Loss of sync count */
53 u64 loss_of_signals; /*!< Loss of signal count */
54 u64 primseq_errs; /*!< Primitive sequence protocol err. */
55 u64 bad_os_count; /*!< Invalid ordered sets */
56 u64 err_enc_out; /*!< Encoding err nonframe_8b10b */
57 u64 err_enc; /*!< Encoding err frame_8b10b */
58};
59
60/**
61 * @brief
62 * Eth Physical Port statistics.
63 */
64struct bfa_port_eth_stats {
65 u64 secs_reset; /*!< Seconds since stats is reset */
66 u64 frame_64; /*!< Frames 64 bytes */
67 u64 frame_65_127; /*!< Frames 65-127 bytes */
68 u64 frame_128_255; /*!< Frames 128-255 bytes */
69 u64 frame_256_511; /*!< Frames 256-511 bytes */
70 u64 frame_512_1023; /*!< Frames 512-1023 bytes */
71 u64 frame_1024_1518; /*!< Frames 1024-1518 bytes */
72 u64 frame_1519_1522; /*!< Frames 1519-1522 bytes */
73 u64 tx_bytes; /*!< Tx bytes */
74 u64 tx_packets; /*!< Tx packets */
75 u64 tx_mcast_packets; /*!< Tx multicast packets */
76 u64 tx_bcast_packets; /*!< Tx broadcast packets */
77 u64 tx_control_frame; /*!< Tx control frame */
78 u64 tx_drop; /*!< Tx drops */
79 u64 tx_jabber; /*!< Tx jabber */
80 u64 tx_fcs_error; /*!< Tx FCS errors */
81 u64 tx_fragments; /*!< Tx fragments */
82 u64 rx_bytes; /*!< Rx bytes */
83 u64 rx_packets; /*!< Rx packets */
84 u64 rx_mcast_packets; /*!< Rx multicast packets */
85 u64 rx_bcast_packets; /*!< Rx broadcast packets */
86 u64 rx_control_frames; /*!< Rx control frames */
87 u64 rx_unknown_opcode; /*!< Rx unknown opcode */
88 u64 rx_drop; /*!< Rx drops */
89 u64 rx_jabber; /*!< Rx jabber */
90 u64 rx_fcs_error; /*!< Rx FCS errors */
91 u64 rx_alignment_error; /*!< Rx alignment errors */
92 u64 rx_frame_length_error; /*!< Rx frame len errors */
93 u64 rx_code_error; /*!< Rx code errors */
94 u64 rx_fragments; /*!< Rx fragments */
95 u64 rx_pause; /*!< Rx pause */
96 u64 rx_zero_pause; /*!< Rx zero pause */
97 u64 tx_pause; /*!< Tx pause */
98 u64 tx_zero_pause; /*!< Tx zero pause */
99 u64 rx_fcoe_pause; /*!< Rx FCoE pause */
100 u64 rx_fcoe_zero_pause; /*!< Rx FCoE zero pause */
101 u64 tx_fcoe_pause; /*!< Tx FCoE pause */
102 u64 tx_fcoe_zero_pause; /*!< Tx FCoE zero pause */
103};
104
105/**
106 * @brief
107 * Port statistics.
108 */
109union bfa_port_stats_u {
110 struct bfa_port_fc_stats fc;
111 struct bfa_port_eth_stats eth;
112};
113
114#pragma pack(1)
115
116#define BFA_CEE_LLDP_MAX_STRING_LEN (128)
117#define BFA_CEE_DCBX_MAX_PRIORITY (8)
118#define BFA_CEE_DCBX_MAX_PGID (8)
119
120#define BFA_CEE_LLDP_SYS_CAP_OTHER 0x0001
121#define BFA_CEE_LLDP_SYS_CAP_REPEATER 0x0002
122#define BFA_CEE_LLDP_SYS_CAP_MAC_BRIDGE 0x0004
123#define BFA_CEE_LLDP_SYS_CAP_WLAN_AP 0x0008
124#define BFA_CEE_LLDP_SYS_CAP_ROUTER 0x0010
125#define BFA_CEE_LLDP_SYS_CAP_TELEPHONE 0x0020
126#define BFA_CEE_LLDP_SYS_CAP_DOCSIS_CD 0x0040
127#define BFA_CEE_LLDP_SYS_CAP_STATION 0x0080
128#define BFA_CEE_LLDP_SYS_CAP_CVLAN 0x0100
129#define BFA_CEE_LLDP_SYS_CAP_SVLAN 0x0200
130#define BFA_CEE_LLDP_SYS_CAP_TPMR 0x0400
131
132/* LLDP string type */
133struct bfa_cee_lldp_str {
134 u8 sub_type;
135 u8 len;
136 u8 rsvd[2];
137 u8 value[BFA_CEE_LLDP_MAX_STRING_LEN];
138};
139
140/* LLDP paramters */
141struct bfa_cee_lldp_cfg {
142 struct bfa_cee_lldp_str chassis_id;
143 struct bfa_cee_lldp_str port_id;
144 struct bfa_cee_lldp_str port_desc;
145 struct bfa_cee_lldp_str sys_name;
146 struct bfa_cee_lldp_str sys_desc;
147 struct bfa_cee_lldp_str mgmt_addr;
148 u16 time_to_live;
149 u16 enabled_system_cap;
150};
151
152enum bfa_cee_dcbx_version {
153 DCBX_PROTOCOL_PRECEE = 1,
154 DCBX_PROTOCOL_CEE = 2,
155};
156
157enum bfa_cee_lls {
158 /* LLS is down because the TLV not sent by the peer */
159 CEE_LLS_DOWN_NO_TLV = 0,
160 /* LLS is down as advertised by the peer */
161 CEE_LLS_DOWN = 1,
162 CEE_LLS_UP = 2,
163};
164
165/* CEE/DCBX parameters */
166struct bfa_cee_dcbx_cfg {
167 u8 pgid[BFA_CEE_DCBX_MAX_PRIORITY];
168 u8 pg_percentage[BFA_CEE_DCBX_MAX_PGID];
169 u8 pfc_primap; /* bitmap of priorties with PFC enabled */
170 u8 fcoe_primap; /* bitmap of priorities used for FcoE traffic */
171 u8 iscsi_primap; /* bitmap of priorities used for iSCSI traffic */
172 u8 dcbx_version; /* operating version:CEE or preCEE */
173 u8 lls_fcoe; /* FCoE Logical Link Status */
174 u8 lls_lan; /* LAN Logical Link Status */
175 u8 rsvd[2];
176};
177
178/* CEE status */
179/* Making this to tri-state for the benefit of port list command */
180enum bfa_cee_status {
181 CEE_UP = 0,
182 CEE_PHY_UP = 1,
183 CEE_LOOPBACK = 2,
184 CEE_PHY_DOWN = 3,
185};
186
187/* CEE Query */
188struct bfa_cee_attr {
189 u8 cee_status;
190 u8 error_reason;
191 struct bfa_cee_lldp_cfg lldp_remote;
192 struct bfa_cee_dcbx_cfg dcbx_remote;
193 mac_t src_mac;
194 u8 link_speed;
195 u8 nw_priority;
196 u8 filler[2];
197};
198
199/* LLDP/DCBX/CEE Statistics */
200struct bfa_cee_stats {
201 u32 lldp_tx_frames; /*!< LLDP Tx Frames */
202 u32 lldp_rx_frames; /*!< LLDP Rx Frames */
203 u32 lldp_rx_frames_invalid; /*!< LLDP Rx Frames invalid */
204 u32 lldp_rx_frames_new; /*!< LLDP Rx Frames new */
205 u32 lldp_tlvs_unrecognized; /*!< LLDP Rx unrecognized TLVs */
206 u32 lldp_rx_shutdown_tlvs; /*!< LLDP Rx shutdown TLVs */
207 u32 lldp_info_aged_out; /*!< LLDP remote info aged out */
208 u32 dcbx_phylink_ups; /*!< DCBX phy link ups */
209 u32 dcbx_phylink_downs; /*!< DCBX phy link downs */
210 u32 dcbx_rx_tlvs; /*!< DCBX Rx TLVs */
211 u32 dcbx_rx_tlvs_invalid; /*!< DCBX Rx TLVs invalid */
212 u32 dcbx_control_tlv_error; /*!< DCBX control TLV errors */
213 u32 dcbx_feature_tlv_error; /*!< DCBX feature TLV errors */
214 u32 dcbx_cee_cfg_new; /*!< DCBX new CEE cfg rcvd */
215 u32 cee_status_down; /*!< CEE status down */
216 u32 cee_status_up; /*!< CEE status up */
217 u32 cee_hw_cfg_changed; /*!< CEE hw cfg changed */
218 u32 cee_rx_invalid_cfg; /*!< CEE invalid cfg */
219};
220
221#pragma pack()
222
223#endif /* __BFA_DEFS_CNA_H__ */
diff --git a/drivers/net/bna/bfa_defs_mfg_comm.h b/drivers/net/bna/bfa_defs_mfg_comm.h
new file mode 100644
index 000000000000..987978fcb3fe
--- /dev/null
+++ b/drivers/net/bna/bfa_defs_mfg_comm.h
@@ -0,0 +1,244 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18#ifndef __BFA_DEFS_MFG_COMM_H__
19#define __BFA_DEFS_MFG_COMM_H__
20
21#include "cna.h"
22
23/**
24 * Manufacturing block version
25 */
26#define BFA_MFG_VERSION 2
27#define BFA_MFG_VERSION_UNINIT 0xFF
28
29/**
30 * Manufacturing block encrypted version
31 */
32#define BFA_MFG_ENC_VER 2
33
34/**
35 * Manufacturing block version 1 length
36 */
37#define BFA_MFG_VER1_LEN 128
38
39/**
40 * Manufacturing block header length
41 */
42#define BFA_MFG_HDR_LEN 4
43
44#define BFA_MFG_SERIALNUM_SIZE 11
45#define STRSZ(_n) (((_n) + 4) & ~3)
46
47/**
48 * Manufacturing card type
49 */
50enum {
51 BFA_MFG_TYPE_CB_MAX = 825, /*!< Crossbow card type max */
52 BFA_MFG_TYPE_FC8P2 = 825, /*!< 8G 2port FC card */
53 BFA_MFG_TYPE_FC8P1 = 815, /*!< 8G 1port FC card */
54 BFA_MFG_TYPE_FC4P2 = 425, /*!< 4G 2port FC card */
55 BFA_MFG_TYPE_FC4P1 = 415, /*!< 4G 1port FC card */
56 BFA_MFG_TYPE_CNA10P2 = 1020, /*!< 10G 2port CNA card */
57 BFA_MFG_TYPE_CNA10P1 = 1010, /*!< 10G 1port CNA card */
58 BFA_MFG_TYPE_JAYHAWK = 804, /*!< Jayhawk mezz card */
59 BFA_MFG_TYPE_WANCHESE = 1007, /*!< Wanchese mezz card */
60 BFA_MFG_TYPE_ASTRA = 807, /*!< Astra mezz card */
61 BFA_MFG_TYPE_LIGHTNING_P0 = 902, /*!< Lightning mezz card - old */
62 BFA_MFG_TYPE_LIGHTNING = 1741, /*!< Lightning mezz card */
63 BFA_MFG_TYPE_INVALID = 0, /*!< Invalid card type */
64};
65
66#pragma pack(1)
67
68/**
69 * Check if 1-port card
70 */
71#define bfa_mfg_is_1port(type) (( \
72 (type) == BFA_MFG_TYPE_FC8P1 || \
73 (type) == BFA_MFG_TYPE_FC4P1 || \
74 (type) == BFA_MFG_TYPE_CNA10P1))
75
76/**
77 * Check if Mezz card
78 */
79#define bfa_mfg_is_mezz(type) (( \
80 (type) == BFA_MFG_TYPE_JAYHAWK || \
81 (type) == BFA_MFG_TYPE_WANCHESE || \
82 (type) == BFA_MFG_TYPE_ASTRA || \
83 (type) == BFA_MFG_TYPE_LIGHTNING_P0 || \
84 (type) == BFA_MFG_TYPE_LIGHTNING))
85
86/**
87 * Check if card type valid
88 */
89#define bfa_mfg_is_card_type_valid(type) (( \
90 (type) == BFA_MFG_TYPE_FC8P2 || \
91 (type) == BFA_MFG_TYPE_FC8P1 || \
92 (type) == BFA_MFG_TYPE_FC4P2 || \
93 (type) == BFA_MFG_TYPE_FC4P1 || \
94 (type) == BFA_MFG_TYPE_CNA10P2 || \
95 (type) == BFA_MFG_TYPE_CNA10P1 || \
96 bfa_mfg_is_mezz(type)))
97
98/**
99 * Check if the card having old wwn/mac handling
100 */
101#define bfa_mfg_is_old_wwn_mac_model(type) (( \
102 (type) == BFA_MFG_TYPE_FC8P2 || \
103 (type) == BFA_MFG_TYPE_FC8P1 || \
104 (type) == BFA_MFG_TYPE_FC4P2 || \
105 (type) == BFA_MFG_TYPE_FC4P1 || \
106 (type) == BFA_MFG_TYPE_CNA10P2 || \
107 (type) == BFA_MFG_TYPE_CNA10P1 || \
108 (type) == BFA_MFG_TYPE_JAYHAWK || \
109 (type) == BFA_MFG_TYPE_WANCHESE))
110
111#define bfa_mfg_increment_wwn_mac(m, i) \
112do { \
113 u32 t = ((m)[0] << 16) | ((m)[1] << 8) | (m)[2]; \
114 t += (i); \
115 (m)[0] = (t >> 16) & 0xFF; \
116 (m)[1] = (t >> 8) & 0xFF; \
117 (m)[2] = t & 0xFF; \
118} while (0)
119
120#define bfa_mfg_adapter_prop_init_flash(card_type, prop) \
121do { \
122 switch ((card_type)) { \
123 case BFA_MFG_TYPE_FC8P2: \
124 case BFA_MFG_TYPE_JAYHAWK: \
125 case BFA_MFG_TYPE_ASTRA: \
126 (prop) = BFI_ADAPTER_SETP(NPORTS, 2) | \
127 BFI_ADAPTER_SETP(SPEED, 8); \
128 break; \
129 case BFA_MFG_TYPE_FC8P1: \
130 (prop) = BFI_ADAPTER_SETP(NPORTS, 1) | \
131 BFI_ADAPTER_SETP(SPEED, 8); \
132 break; \
133 case BFA_MFG_TYPE_FC4P2: \
134 (prop) = BFI_ADAPTER_SETP(NPORTS, 2) | \
135 BFI_ADAPTER_SETP(SPEED, 4); \
136 break; \
137 case BFA_MFG_TYPE_FC4P1: \
138 (prop) = BFI_ADAPTER_SETP(NPORTS, 1) | \
139 BFI_ADAPTER_SETP(SPEED, 4); \
140 break; \
141 case BFA_MFG_TYPE_CNA10P2: \
142 case BFA_MFG_TYPE_WANCHESE: \
143 case BFA_MFG_TYPE_LIGHTNING_P0: \
144 case BFA_MFG_TYPE_LIGHTNING: \
145 (prop) = BFI_ADAPTER_SETP(NPORTS, 2); \
146 (prop) |= BFI_ADAPTER_SETP(SPEED, 10); \
147 break; \
148 case BFA_MFG_TYPE_CNA10P1: \
149 (prop) = BFI_ADAPTER_SETP(NPORTS, 1); \
150 (prop) |= BFI_ADAPTER_SETP(SPEED, 10); \
151 break; \
152 default: \
153 (prop) = BFI_ADAPTER_UNSUPP; \
154 } \
155} while (0)
156
157enum {
158 CB_GPIO_TTV = (1), /*!< TTV debug capable cards */
159 CB_GPIO_FC8P2 = (2), /*!< 8G 2port FC card */
160 CB_GPIO_FC8P1 = (3), /*!< 8G 1port FC card */
161 CB_GPIO_FC4P2 = (4), /*!< 4G 2port FC card */
162 CB_GPIO_FC4P1 = (5), /*!< 4G 1port FC card */
163 CB_GPIO_DFLY = (6), /*!< 8G 2port FC mezzanine card */
164 CB_GPIO_PROTO = (1 << 7) /*!< 8G 2port FC prototypes */
165};
166
167#define bfa_mfg_adapter_prop_init_gpio(gpio, card_type, prop) \
168do { \
169 if ((gpio) & CB_GPIO_PROTO) { \
170 (prop) |= BFI_ADAPTER_PROTO; \
171 (gpio) &= ~CB_GPIO_PROTO; \
172 } \
173 switch ((gpio)) { \
174 case CB_GPIO_TTV: \
175 (prop) |= BFI_ADAPTER_TTV; \
176 case CB_GPIO_DFLY: \
177 case CB_GPIO_FC8P2: \
178 (prop) |= BFI_ADAPTER_SETP(NPORTS, 2); \
179 (prop) |= BFI_ADAPTER_SETP(SPEED, 8); \
180 (card_type) = BFA_MFG_TYPE_FC8P2; \
181 break; \
182 case CB_GPIO_FC8P1: \
183 (prop) |= BFI_ADAPTER_SETP(NPORTS, 1); \
184 (prop) |= BFI_ADAPTER_SETP(SPEED, 8); \
185 (card_type) = BFA_MFG_TYPE_FC8P1; \
186 break; \
187 case CB_GPIO_FC4P2: \
188 (prop) |= BFI_ADAPTER_SETP(NPORTS, 2); \
189 (prop) |= BFI_ADAPTER_SETP(SPEED, 4); \
190 (card_type) = BFA_MFG_TYPE_FC4P2; \
191 break; \
192 case CB_GPIO_FC4P1: \
193 (prop) |= BFI_ADAPTER_SETP(NPORTS, 1); \
194 (prop) |= BFI_ADAPTER_SETP(SPEED, 4); \
195 (card_type) = BFA_MFG_TYPE_FC4P1; \
196 break; \
197 default: \
198 (prop) |= BFI_ADAPTER_UNSUPP; \
199 (card_type) = BFA_MFG_TYPE_INVALID; \
200 } \
201} while (0)
202
203/**
204 * VPD data length
205 */
206#define BFA_MFG_VPD_LEN 512
207#define BFA_MFG_VPD_LEN_INVALID 0
208
209#define BFA_MFG_VPD_PCI_HDR_OFF 137
210#define BFA_MFG_VPD_PCI_VER_MASK 0x07 /*!< version mask 3 bits */
211#define BFA_MFG_VPD_PCI_VDR_MASK 0xf8 /*!< vendor mask 5 bits */
212
213/**
214 * VPD vendor tag
215 */
216enum {
217 BFA_MFG_VPD_UNKNOWN = 0, /*!< vendor unknown */
218 BFA_MFG_VPD_IBM = 1, /*!< vendor IBM */
219 BFA_MFG_VPD_HP = 2, /*!< vendor HP */
220 BFA_MFG_VPD_DELL = 3, /*!< vendor DELL */
221 BFA_MFG_VPD_PCI_IBM = 0x08, /*!< PCI VPD IBM */
222 BFA_MFG_VPD_PCI_HP = 0x10, /*!< PCI VPD HP */
223 BFA_MFG_VPD_PCI_DELL = 0x20, /*!< PCI VPD DELL */
224 BFA_MFG_VPD_PCI_BRCD = 0xf8, /*!< PCI VPD Brocade */
225};
226
227/**
228 * @brief BFA adapter flash vpd data definition.
229 *
230 * All numerical fields are in big-endian format.
231 */
232struct bfa_mfg_vpd {
233 u8 version; /*!< vpd data version */
234 u8 vpd_sig[3]; /*!< characters 'V', 'P', 'D' */
235 u8 chksum; /*!< u8 checksum */
236 u8 vendor; /*!< vendor */
237 u8 len; /*!< vpd data length excluding header */
238 u8 rsv;
239 u8 data[BFA_MFG_VPD_LEN]; /*!< vpd data */
240};
241
242#pragma pack()
243
244#endif /* __BFA_DEFS_MFG_H__ */
diff --git a/drivers/net/bna/bfa_defs_status.h b/drivers/net/bna/bfa_defs_status.h
new file mode 100644
index 000000000000..af951126375c
--- /dev/null
+++ b/drivers/net/bna/bfa_defs_status.h
@@ -0,0 +1,216 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18#ifndef __BFA_DEFS_STATUS_H__
19#define __BFA_DEFS_STATUS_H__
20
21/**
22 * API status return values
23 *
24 * NOTE: The error msgs are auto generated from the comments. Only singe line
25 * comments are supported
26 */
27enum bfa_status {
28 BFA_STATUS_OK = 0,
29 BFA_STATUS_FAILED = 1,
30 BFA_STATUS_EINVAL = 2,
31 BFA_STATUS_ENOMEM = 3,
32 BFA_STATUS_ENOSYS = 4,
33 BFA_STATUS_ETIMER = 5,
34 BFA_STATUS_EPROTOCOL = 6,
35 BFA_STATUS_ENOFCPORTS = 7,
36 BFA_STATUS_NOFLASH = 8,
37 BFA_STATUS_BADFLASH = 9,
38 BFA_STATUS_SFP_UNSUPP = 10,
39 BFA_STATUS_UNKNOWN_VFID = 11,
40 BFA_STATUS_DATACORRUPTED = 12,
41 BFA_STATUS_DEVBUSY = 13,
42 BFA_STATUS_ABORTED = 14,
43 BFA_STATUS_NODEV = 15,
44 BFA_STATUS_HDMA_FAILED = 16,
45 BFA_STATUS_FLASH_BAD_LEN = 17,
46 BFA_STATUS_UNKNOWN_LWWN = 18,
47 BFA_STATUS_UNKNOWN_RWWN = 19,
48 BFA_STATUS_FCPT_LS_RJT = 20,
49 BFA_STATUS_VPORT_EXISTS = 21,
50 BFA_STATUS_VPORT_MAX = 22,
51 BFA_STATUS_UNSUPP_SPEED = 23,
52 BFA_STATUS_INVLD_DFSZ = 24,
53 BFA_STATUS_CNFG_FAILED = 25,
54 BFA_STATUS_CMD_NOTSUPP = 26,
55 BFA_STATUS_NO_ADAPTER = 27,
56 BFA_STATUS_LINKDOWN = 28,
57 BFA_STATUS_FABRIC_RJT = 29,
58 BFA_STATUS_UNKNOWN_VWWN = 30,
59 BFA_STATUS_NSLOGIN_FAILED = 31,
60 BFA_STATUS_NO_RPORTS = 32,
61 BFA_STATUS_NSQUERY_FAILED = 33,
62 BFA_STATUS_PORT_OFFLINE = 34,
63 BFA_STATUS_RPORT_OFFLINE = 35,
64 BFA_STATUS_TGTOPEN_FAILED = 36,
65 BFA_STATUS_BAD_LUNS = 37,
66 BFA_STATUS_IO_FAILURE = 38,
67 BFA_STATUS_NO_FABRIC = 39,
68 BFA_STATUS_EBADF = 40,
69 BFA_STATUS_EINTR = 41,
70 BFA_STATUS_EIO = 42,
71 BFA_STATUS_ENOTTY = 43,
72 BFA_STATUS_ENXIO = 44,
73 BFA_STATUS_EFOPEN = 45,
74 BFA_STATUS_VPORT_WWN_BP = 46,
75 BFA_STATUS_PORT_NOT_DISABLED = 47,
76 BFA_STATUS_BADFRMHDR = 48,
77 BFA_STATUS_BADFRMSZ = 49,
78 BFA_STATUS_MISSINGFRM = 50,
79 BFA_STATUS_LINKTIMEOUT = 51,
80 BFA_STATUS_NO_FCPIM_NEXUS = 52,
81 BFA_STATUS_CHECKSUM_FAIL = 53,
82 BFA_STATUS_GZME_FAILED = 54,
83 BFA_STATUS_SCSISTART_REQD = 55,
84 BFA_STATUS_IOC_FAILURE = 56,
85 BFA_STATUS_INVALID_WWN = 57,
86 BFA_STATUS_MISMATCH = 58,
87 BFA_STATUS_IOC_ENABLED = 59,
88 BFA_STATUS_ADAPTER_ENABLED = 60,
89 BFA_STATUS_IOC_NON_OP = 61,
90 BFA_STATUS_ADDR_MAP_FAILURE = 62,
91 BFA_STATUS_SAME_NAME = 63,
92 BFA_STATUS_PENDING = 64,
93 BFA_STATUS_8G_SPD = 65,
94 BFA_STATUS_4G_SPD = 66,
95 BFA_STATUS_AD_IS_ENABLE = 67,
96 BFA_STATUS_EINVAL_TOV = 68,
97 BFA_STATUS_EINVAL_QDEPTH = 69,
98 BFA_STATUS_VERSION_FAIL = 70,
99 BFA_STATUS_DIAG_BUSY = 71,
100 BFA_STATUS_BEACON_ON = 72,
101 BFA_STATUS_BEACON_OFF = 73,
102 BFA_STATUS_LBEACON_ON = 74,
103 BFA_STATUS_LBEACON_OFF = 75,
104 BFA_STATUS_PORT_NOT_INITED = 76,
105 BFA_STATUS_RPSC_ENABLED = 77,
106 BFA_STATUS_ENOFSAVE = 78,
107 BFA_STATUS_BAD_FILE = 79,
108 BFA_STATUS_RLIM_EN = 80,
109 BFA_STATUS_RLIM_DIS = 81,
110 BFA_STATUS_IOC_DISABLED = 82,
111 BFA_STATUS_ADAPTER_DISABLED = 83,
112 BFA_STATUS_BIOS_DISABLED = 84,
113 BFA_STATUS_AUTH_ENABLED = 85,
114 BFA_STATUS_AUTH_DISABLED = 86,
115 BFA_STATUS_ERROR_TRL_ENABLED = 87,
116 BFA_STATUS_ERROR_QOS_ENABLED = 88,
117 BFA_STATUS_NO_SFP_DEV = 89,
118 BFA_STATUS_MEMTEST_FAILED = 90,
119 BFA_STATUS_INVALID_DEVID = 91,
120 BFA_STATUS_QOS_ENABLED = 92,
121 BFA_STATUS_QOS_DISABLED = 93,
122 BFA_STATUS_INCORRECT_DRV_CONFIG = 94,
123 BFA_STATUS_REG_FAIL = 95,
124 BFA_STATUS_IM_INV_CODE = 96,
125 BFA_STATUS_IM_INV_VLAN = 97,
126 BFA_STATUS_IM_INV_ADAPT_NAME = 98,
127 BFA_STATUS_IM_LOW_RESOURCES = 99,
128 BFA_STATUS_IM_VLANID_IS_PVID = 100,
129 BFA_STATUS_IM_VLANID_EXISTS = 101,
130 BFA_STATUS_IM_FW_UPDATE_FAIL = 102,
131 BFA_STATUS_PORTLOG_ENABLED = 103,
132 BFA_STATUS_PORTLOG_DISABLED = 104,
133 BFA_STATUS_FILE_NOT_FOUND = 105,
134 BFA_STATUS_QOS_FC_ONLY = 106,
135 BFA_STATUS_RLIM_FC_ONLY = 107,
136 BFA_STATUS_CT_SPD = 108,
137 BFA_STATUS_LEDTEST_OP = 109,
138 BFA_STATUS_CEE_NOT_DN = 110,
139 BFA_STATUS_10G_SPD = 111,
140 BFA_STATUS_IM_INV_TEAM_NAME = 112,
141 BFA_STATUS_IM_DUP_TEAM_NAME = 113,
142 BFA_STATUS_IM_ADAPT_ALREADY_IN_TEAM = 114,
143 BFA_STATUS_IM_ADAPT_HAS_VLANS = 115,
144 BFA_STATUS_IM_PVID_MISMATCH = 116,
145 BFA_STATUS_IM_LINK_SPEED_MISMATCH = 117,
146 BFA_STATUS_IM_MTU_MISMATCH = 118,
147 BFA_STATUS_IM_RSS_MISMATCH = 119,
148 BFA_STATUS_IM_HDS_MISMATCH = 120,
149 BFA_STATUS_IM_OFFLOAD_MISMATCH = 121,
150 BFA_STATUS_IM_PORT_PARAMS = 122,
151 BFA_STATUS_IM_PORT_NOT_IN_TEAM = 123,
152 BFA_STATUS_IM_CANNOT_REM_PRI = 124,
153 BFA_STATUS_IM_MAX_PORTS_REACHED = 125,
154 BFA_STATUS_IM_LAST_PORT_DELETE = 126,
155 BFA_STATUS_IM_NO_DRIVER = 127,
156 BFA_STATUS_IM_MAX_VLANS_REACHED = 128,
157 BFA_STATUS_TOMCAT_SPD_NOT_ALLOWED = 129,
158 BFA_STATUS_NO_MINPORT_DRIVER = 130,
159 BFA_STATUS_CARD_TYPE_MISMATCH = 131,
160 BFA_STATUS_BAD_ASICBLK = 132,
161 BFA_STATUS_NO_DRIVER = 133,
162 BFA_STATUS_INVALID_MAC = 134,
163 BFA_STATUS_IM_NO_VLAN = 135,
164 BFA_STATUS_IM_ETH_LB_FAILED = 136,
165 BFA_STATUS_IM_PVID_REMOVE = 137,
166 BFA_STATUS_IM_PVID_EDIT = 138,
167 BFA_STATUS_CNA_NO_BOOT = 139,
168 BFA_STATUS_IM_PVID_NON_ZERO = 140,
169 BFA_STATUS_IM_INETCFG_LOCK_FAILED = 141,
170 BFA_STATUS_IM_GET_INETCFG_FAILED = 142,
171 BFA_STATUS_IM_NOT_BOUND = 143,
172 BFA_STATUS_INSUFFICIENT_PERMS = 144,
173 BFA_STATUS_IM_INV_VLAN_NAME = 145,
174 BFA_STATUS_CMD_NOTSUPP_CNA = 146,
175 BFA_STATUS_IM_PASSTHRU_EDIT = 147,
176 BFA_STATUS_IM_BIND_FAILED = 148,
177 BFA_STATUS_IM_UNBIND_FAILED = 149,
178 BFA_STATUS_IM_PORT_IN_TEAM = 150,
179 BFA_STATUS_IM_VLAN_NOT_FOUND = 151,
180 BFA_STATUS_IM_TEAM_NOT_FOUND = 152,
181 BFA_STATUS_IM_TEAM_CFG_NOT_ALLOWED = 153,
182 BFA_STATUS_PBC = 154,
183 BFA_STATUS_DEVID_MISSING = 155,
184 BFA_STATUS_BAD_FWCFG = 156,
185 BFA_STATUS_CREATE_FILE = 157,
186 BFA_STATUS_INVALID_VENDOR = 158,
187 BFA_STATUS_SFP_NOT_READY = 159,
188 BFA_STATUS_FLASH_UNINIT = 160,
189 BFA_STATUS_FLASH_EMPTY = 161,
190 BFA_STATUS_FLASH_CKFAIL = 162,
191 BFA_STATUS_TRUNK_UNSUPP = 163,
192 BFA_STATUS_TRUNK_ENABLED = 164,
193 BFA_STATUS_TRUNK_DISABLED = 165,
194 BFA_STATUS_TRUNK_ERROR_TRL_ENABLED = 166,
195 BFA_STATUS_BOOT_CODE_UPDATED = 167,
196 BFA_STATUS_BOOT_VERSION = 168,
197 BFA_STATUS_CARDTYPE_MISSING = 169,
198 BFA_STATUS_INVALID_CARDTYPE = 170,
199 BFA_STATUS_NO_TOPOLOGY_FOR_CNA = 171,
200 BFA_STATUS_IM_VLAN_OVER_TEAM_DELETE_FAILED = 172,
201 BFA_STATUS_ETHBOOT_ENABLED = 173,
202 BFA_STATUS_ETHBOOT_DISABLED = 174,
203 BFA_STATUS_IOPROFILE_OFF = 175,
204 BFA_STATUS_NO_PORT_INSTANCE = 176,
205 BFA_STATUS_BOOT_CODE_TIMEDOUT = 177,
206 BFA_STATUS_NO_VPORT_LOCK = 178,
207 BFA_STATUS_VPORT_NO_CNFG = 179,
208 BFA_STATUS_MAX_VAL
209};
210
211enum bfa_eproto_status {
212 BFA_EPROTO_BAD_ACCEPT = 0,
213 BFA_EPROTO_UNKNOWN_RSP = 1
214};
215
216#endif /* __BFA_DEFS_STATUS_H__ */
diff --git a/drivers/net/bna/bfa_ioc.c b/drivers/net/bna/bfa_ioc.c
new file mode 100644
index 000000000000..cdc2cb1597ec
--- /dev/null
+++ b/drivers/net/bna/bfa_ioc.c
@@ -0,0 +1,1839 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18
19#include "bfa_ioc.h"
20#include "cna.h"
21#include "bfi.h"
22#include "bfi_ctreg.h"
23#include "bfa_defs.h"
24
25/**
26 * IOC local definitions
27 */
28
29#define bfa_ioc_timer_start(__ioc) \
30 mod_timer(&(__ioc)->ioc_timer, jiffies + \
31 msecs_to_jiffies(BFA_IOC_TOV))
32#define bfa_ioc_timer_stop(__ioc) del_timer(&(__ioc)->ioc_timer)
33
34#define bfa_ioc_recovery_timer_start(__ioc) \
35 mod_timer(&(__ioc)->ioc_timer, jiffies + \
36 msecs_to_jiffies(BFA_IOC_TOV_RECOVER))
37
38#define bfa_sem_timer_start(__ioc) \
39 mod_timer(&(__ioc)->sem_timer, jiffies + \
40 msecs_to_jiffies(BFA_IOC_HWSEM_TOV))
41#define bfa_sem_timer_stop(__ioc) del_timer(&(__ioc)->sem_timer)
42
43#define bfa_hb_timer_start(__ioc) \
44 mod_timer(&(__ioc)->hb_timer, jiffies + \
45 msecs_to_jiffies(BFA_IOC_HB_TOV))
46#define bfa_hb_timer_stop(__ioc) del_timer(&(__ioc)->hb_timer)
47
48/**
49 * Asic specific macros : see bfa_hw_cb.c and bfa_hw_ct.c for details.
50 */
51
52#define bfa_ioc_firmware_lock(__ioc) \
53 ((__ioc)->ioc_hwif->ioc_firmware_lock(__ioc))
54#define bfa_ioc_firmware_unlock(__ioc) \
55 ((__ioc)->ioc_hwif->ioc_firmware_unlock(__ioc))
56#define bfa_ioc_reg_init(__ioc) ((__ioc)->ioc_hwif->ioc_reg_init(__ioc))
57#define bfa_ioc_map_port(__ioc) ((__ioc)->ioc_hwif->ioc_map_port(__ioc))
58#define bfa_ioc_notify_hbfail(__ioc) \
59 ((__ioc)->ioc_hwif->ioc_notify_hbfail(__ioc))
60
61#define bfa_ioc_is_optrom(__ioc) \
62 (bfa_cb_image_get_size(BFA_IOC_FWIMG_TYPE(__ioc)) < BFA_IOC_FWIMG_MINSZ)
63
64#define bfa_ioc_mbox_cmd_pending(__ioc) \
65 (!list_empty(&((__ioc)->mbox_mod.cmd_q)) || \
66 readl((__ioc)->ioc_regs.hfn_mbox_cmd))
67
68bool bfa_auto_recover = true;
69
70/*
71 * forward declarations
72 */
73static void bfa_ioc_hw_sem_get(struct bfa_ioc *ioc);
74static void bfa_ioc_hw_sem_get_cancel(struct bfa_ioc *ioc);
75static void bfa_ioc_hwinit(struct bfa_ioc *ioc, bool force);
76static void bfa_ioc_send_enable(struct bfa_ioc *ioc);
77static void bfa_ioc_send_disable(struct bfa_ioc *ioc);
78static void bfa_ioc_send_getattr(struct bfa_ioc *ioc);
79static void bfa_ioc_hb_monitor(struct bfa_ioc *ioc);
80static void bfa_ioc_hb_stop(struct bfa_ioc *ioc);
81static void bfa_ioc_reset(struct bfa_ioc *ioc, bool force);
82static void bfa_ioc_mbox_poll(struct bfa_ioc *ioc);
83static void bfa_ioc_mbox_hbfail(struct bfa_ioc *ioc);
84static void bfa_ioc_recover(struct bfa_ioc *ioc);
85static void bfa_ioc_check_attr_wwns(struct bfa_ioc *ioc);
86static void bfa_ioc_disable_comp(struct bfa_ioc *ioc);
87static void bfa_ioc_lpu_stop(struct bfa_ioc *ioc);
88
89/**
90 * IOC state machine events
91 */
92enum ioc_event {
93 IOC_E_ENABLE = 1, /*!< IOC enable request */
94 IOC_E_DISABLE = 2, /*!< IOC disable request */
95 IOC_E_TIMEOUT = 3, /*!< f/w response timeout */
96 IOC_E_FWREADY = 4, /*!< f/w initialization done */
97 IOC_E_FWRSP_GETATTR = 5, /*!< IOC get attribute response */
98 IOC_E_FWRSP_ENABLE = 6, /*!< enable f/w response */
99 IOC_E_FWRSP_DISABLE = 7, /*!< disable f/w response */
100 IOC_E_HBFAIL = 8, /*!< heartbeat failure */
101 IOC_E_HWERROR = 9, /*!< hardware error interrupt */
102 IOC_E_SEMLOCKED = 10, /*!< h/w semaphore is locked */
103 IOC_E_DETACH = 11, /*!< driver detach cleanup */
104};
105
106bfa_fsm_state_decl(bfa_ioc, reset, struct bfa_ioc, enum ioc_event);
107bfa_fsm_state_decl(bfa_ioc, fwcheck, struct bfa_ioc, enum ioc_event);
108bfa_fsm_state_decl(bfa_ioc, mismatch, struct bfa_ioc, enum ioc_event);
109bfa_fsm_state_decl(bfa_ioc, semwait, struct bfa_ioc, enum ioc_event);
110bfa_fsm_state_decl(bfa_ioc, hwinit, struct bfa_ioc, enum ioc_event);
111bfa_fsm_state_decl(bfa_ioc, enabling, struct bfa_ioc, enum ioc_event);
112bfa_fsm_state_decl(bfa_ioc, getattr, struct bfa_ioc, enum ioc_event);
113bfa_fsm_state_decl(bfa_ioc, op, struct bfa_ioc, enum ioc_event);
114bfa_fsm_state_decl(bfa_ioc, initfail, struct bfa_ioc, enum ioc_event);
115bfa_fsm_state_decl(bfa_ioc, hbfail, struct bfa_ioc, enum ioc_event);
116bfa_fsm_state_decl(bfa_ioc, disabling, struct bfa_ioc, enum ioc_event);
117bfa_fsm_state_decl(bfa_ioc, disabled, struct bfa_ioc, enum ioc_event);
118
119static struct bfa_sm_table ioc_sm_table[] = {
120 {BFA_SM(bfa_ioc_sm_reset), BFA_IOC_RESET},
121 {BFA_SM(bfa_ioc_sm_fwcheck), BFA_IOC_FWMISMATCH},
122 {BFA_SM(bfa_ioc_sm_mismatch), BFA_IOC_FWMISMATCH},
123 {BFA_SM(bfa_ioc_sm_semwait), BFA_IOC_SEMWAIT},
124 {BFA_SM(bfa_ioc_sm_hwinit), BFA_IOC_HWINIT},
125 {BFA_SM(bfa_ioc_sm_enabling), BFA_IOC_HWINIT},
126 {BFA_SM(bfa_ioc_sm_getattr), BFA_IOC_GETATTR},
127 {BFA_SM(bfa_ioc_sm_op), BFA_IOC_OPERATIONAL},
128 {BFA_SM(bfa_ioc_sm_initfail), BFA_IOC_INITFAIL},
129 {BFA_SM(bfa_ioc_sm_hbfail), BFA_IOC_HBFAIL},
130 {BFA_SM(bfa_ioc_sm_disabling), BFA_IOC_DISABLING},
131 {BFA_SM(bfa_ioc_sm_disabled), BFA_IOC_DISABLED},
132};
133
134/**
135 * Reset entry actions -- initialize state machine
136 */
137static void
138bfa_ioc_sm_reset_entry(struct bfa_ioc *ioc)
139{
140 ioc->retry_count = 0;
141 ioc->auto_recover = bfa_auto_recover;
142}
143
144/**
145 * Beginning state. IOC is in reset state.
146 */
147static void
148bfa_ioc_sm_reset(struct bfa_ioc *ioc, enum ioc_event event)
149{
150 switch (event) {
151 case IOC_E_ENABLE:
152 bfa_fsm_set_state(ioc, bfa_ioc_sm_fwcheck);
153 break;
154
155 case IOC_E_DISABLE:
156 bfa_ioc_disable_comp(ioc);
157 break;
158
159 case IOC_E_DETACH:
160 break;
161
162 default:
163 bfa_sm_fault(ioc, event);
164 }
165}
166
167/**
168 * Semaphore should be acquired for version check.
169 */
170static void
171bfa_ioc_sm_fwcheck_entry(struct bfa_ioc *ioc)
172{
173 bfa_ioc_hw_sem_get(ioc);
174}
175
176/**
177 * Awaiting h/w semaphore to continue with version check.
178 */
179static void
180bfa_ioc_sm_fwcheck(struct bfa_ioc *ioc, enum ioc_event event)
181{
182 switch (event) {
183 case IOC_E_SEMLOCKED:
184 if (bfa_ioc_firmware_lock(ioc)) {
185 ioc->retry_count = 0;
186 bfa_fsm_set_state(ioc, bfa_ioc_sm_hwinit);
187 } else {
188 bfa_ioc_hw_sem_release(ioc);
189 bfa_fsm_set_state(ioc, bfa_ioc_sm_mismatch);
190 }
191 break;
192
193 case IOC_E_DISABLE:
194 bfa_ioc_disable_comp(ioc);
195 /* fall through */
196
197 case IOC_E_DETACH:
198 bfa_ioc_hw_sem_get_cancel(ioc);
199 bfa_fsm_set_state(ioc, bfa_ioc_sm_reset);
200 break;
201
202 case IOC_E_FWREADY:
203 break;
204
205 default:
206 bfa_sm_fault(ioc, event);
207 }
208}
209
210/**
211 * Notify enable completion callback and generate mismatch AEN.
212 */
213static void
214bfa_ioc_sm_mismatch_entry(struct bfa_ioc *ioc)
215{
216 /**
217 * Provide enable completion callback and AEN notification only once.
218 */
219 if (ioc->retry_count == 0)
220 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
221 ioc->retry_count++;
222 bfa_ioc_timer_start(ioc);
223}
224
225/**
226 * Awaiting firmware version match.
227 */
228static void
229bfa_ioc_sm_mismatch(struct bfa_ioc *ioc, enum ioc_event event)
230{
231 switch (event) {
232 case IOC_E_TIMEOUT:
233 bfa_fsm_set_state(ioc, bfa_ioc_sm_fwcheck);
234 break;
235
236 case IOC_E_DISABLE:
237 bfa_ioc_disable_comp(ioc);
238 /* fall through */
239
240 case IOC_E_DETACH:
241 bfa_ioc_timer_stop(ioc);
242 bfa_fsm_set_state(ioc, bfa_ioc_sm_reset);
243 break;
244
245 case IOC_E_FWREADY:
246 break;
247
248 default:
249 bfa_sm_fault(ioc, event);
250 }
251}
252
253/**
254 * Request for semaphore.
255 */
256static void
257bfa_ioc_sm_semwait_entry(struct bfa_ioc *ioc)
258{
259 bfa_ioc_hw_sem_get(ioc);
260}
261
262/**
263 * Awaiting semaphore for h/w initialzation.
264 */
265static void
266bfa_ioc_sm_semwait(struct bfa_ioc *ioc, enum ioc_event event)
267{
268 switch (event) {
269 case IOC_E_SEMLOCKED:
270 ioc->retry_count = 0;
271 bfa_fsm_set_state(ioc, bfa_ioc_sm_hwinit);
272 break;
273
274 case IOC_E_DISABLE:
275 bfa_ioc_hw_sem_get_cancel(ioc);
276 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
277 break;
278
279 default:
280 bfa_sm_fault(ioc, event);
281 }
282}
283
284static void
285bfa_ioc_sm_hwinit_entry(struct bfa_ioc *ioc)
286{
287 bfa_ioc_timer_start(ioc);
288 bfa_ioc_reset(ioc, false);
289}
290
291/**
292 * @brief
293 * Hardware is being initialized. Interrupts are enabled.
294 * Holding hardware semaphore lock.
295 */
296static void
297bfa_ioc_sm_hwinit(struct bfa_ioc *ioc, enum ioc_event event)
298{
299 switch (event) {
300 case IOC_E_FWREADY:
301 bfa_ioc_timer_stop(ioc);
302 bfa_fsm_set_state(ioc, bfa_ioc_sm_enabling);
303 break;
304
305 case IOC_E_HWERROR:
306 bfa_ioc_timer_stop(ioc);
307 /* fall through */
308
309 case IOC_E_TIMEOUT:
310 ioc->retry_count++;
311 if (ioc->retry_count < BFA_IOC_HWINIT_MAX) {
312 bfa_ioc_timer_start(ioc);
313 bfa_ioc_reset(ioc, true);
314 break;
315 }
316
317 bfa_ioc_hw_sem_release(ioc);
318 bfa_fsm_set_state(ioc, bfa_ioc_sm_initfail);
319 break;
320
321 case IOC_E_DISABLE:
322 bfa_ioc_hw_sem_release(ioc);
323 bfa_ioc_timer_stop(ioc);
324 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
325 break;
326
327 default:
328 bfa_sm_fault(ioc, event);
329 }
330}
331
332static void
333bfa_ioc_sm_enabling_entry(struct bfa_ioc *ioc)
334{
335 bfa_ioc_timer_start(ioc);
336 bfa_ioc_send_enable(ioc);
337}
338
339/**
340 * Host IOC function is being enabled, awaiting response from firmware.
341 * Semaphore is acquired.
342 */
343static void
344bfa_ioc_sm_enabling(struct bfa_ioc *ioc, enum ioc_event event)
345{
346 switch (event) {
347 case IOC_E_FWRSP_ENABLE:
348 bfa_ioc_timer_stop(ioc);
349 bfa_ioc_hw_sem_release(ioc);
350 bfa_fsm_set_state(ioc, bfa_ioc_sm_getattr);
351 break;
352
353 case IOC_E_HWERROR:
354 bfa_ioc_timer_stop(ioc);
355 /* fall through */
356
357 case IOC_E_TIMEOUT:
358 ioc->retry_count++;
359 if (ioc->retry_count < BFA_IOC_HWINIT_MAX) {
360 writel(BFI_IOC_UNINIT,
361 ioc->ioc_regs.ioc_fwstate);
362 bfa_fsm_set_state(ioc, bfa_ioc_sm_hwinit);
363 break;
364 }
365
366 bfa_ioc_hw_sem_release(ioc);
367 bfa_fsm_set_state(ioc, bfa_ioc_sm_initfail);
368 break;
369
370 case IOC_E_DISABLE:
371 bfa_ioc_timer_stop(ioc);
372 bfa_ioc_hw_sem_release(ioc);
373 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
374 break;
375
376 case IOC_E_FWREADY:
377 bfa_ioc_send_enable(ioc);
378 break;
379
380 default:
381 bfa_sm_fault(ioc, event);
382 }
383}
384
385static void
386bfa_ioc_sm_getattr_entry(struct bfa_ioc *ioc)
387{
388 bfa_ioc_timer_start(ioc);
389 bfa_ioc_send_getattr(ioc);
390}
391
392/**
393 * @brief
394 * IOC configuration in progress. Timer is active.
395 */
396static void
397bfa_ioc_sm_getattr(struct bfa_ioc *ioc, enum ioc_event event)
398{
399 switch (event) {
400 case IOC_E_FWRSP_GETATTR:
401 bfa_ioc_timer_stop(ioc);
402 bfa_ioc_check_attr_wwns(ioc);
403 bfa_fsm_set_state(ioc, bfa_ioc_sm_op);
404 break;
405
406 case IOC_E_HWERROR:
407 bfa_ioc_timer_stop(ioc);
408 /* fall through */
409
410 case IOC_E_TIMEOUT:
411 bfa_fsm_set_state(ioc, bfa_ioc_sm_initfail);
412 break;
413
414 case IOC_E_DISABLE:
415 bfa_ioc_timer_stop(ioc);
416 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
417 break;
418
419 default:
420 bfa_sm_fault(ioc, event);
421 }
422}
423
424static void
425bfa_ioc_sm_op_entry(struct bfa_ioc *ioc)
426{
427 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_OK);
428 bfa_ioc_hb_monitor(ioc);
429}
430
431static void
432bfa_ioc_sm_op(struct bfa_ioc *ioc, enum ioc_event event)
433{
434 switch (event) {
435 case IOC_E_ENABLE:
436 break;
437
438 case IOC_E_DISABLE:
439 bfa_ioc_hb_stop(ioc);
440 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
441 break;
442
443 case IOC_E_HWERROR:
444 case IOC_E_FWREADY:
445 /**
446 * Hard error or IOC recovery by other function.
447 * Treat it same as heartbeat failure.
448 */
449 bfa_ioc_hb_stop(ioc);
450 /* !!! fall through !!! */
451
452 case IOC_E_HBFAIL:
453 bfa_fsm_set_state(ioc, bfa_ioc_sm_hbfail);
454 break;
455
456 default:
457 bfa_sm_fault(ioc, event);
458 }
459}
460
461static void
462bfa_ioc_sm_disabling_entry(struct bfa_ioc *ioc)
463{
464 bfa_ioc_timer_start(ioc);
465 bfa_ioc_send_disable(ioc);
466}
467
468/**
469 * IOC is being disabled
470 */
471static void
472bfa_ioc_sm_disabling(struct bfa_ioc *ioc, enum ioc_event event)
473{
474 switch (event) {
475 case IOC_E_FWRSP_DISABLE:
476 bfa_ioc_timer_stop(ioc);
477 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
478 break;
479
480 case IOC_E_HWERROR:
481 bfa_ioc_timer_stop(ioc);
482 /*
483 * !!! fall through !!!
484 */
485
486 case IOC_E_TIMEOUT:
487 writel(BFI_IOC_FAIL, ioc->ioc_regs.ioc_fwstate);
488 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
489 break;
490
491 default:
492 bfa_sm_fault(ioc, event);
493 }
494}
495
496/**
497 * IOC disable completion entry.
498 */
499static void
500bfa_ioc_sm_disabled_entry(struct bfa_ioc *ioc)
501{
502 bfa_ioc_disable_comp(ioc);
503}
504
505static void
506bfa_ioc_sm_disabled(struct bfa_ioc *ioc, enum ioc_event event)
507{
508 switch (event) {
509 case IOC_E_ENABLE:
510 bfa_fsm_set_state(ioc, bfa_ioc_sm_semwait);
511 break;
512
513 case IOC_E_DISABLE:
514 ioc->cbfn->disable_cbfn(ioc->bfa);
515 break;
516
517 case IOC_E_FWREADY:
518 break;
519
520 case IOC_E_DETACH:
521 bfa_ioc_firmware_unlock(ioc);
522 bfa_fsm_set_state(ioc, bfa_ioc_sm_reset);
523 break;
524
525 default:
526 bfa_sm_fault(ioc, event);
527 }
528}
529
530static void
531bfa_ioc_sm_initfail_entry(struct bfa_ioc *ioc)
532{
533 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
534 bfa_ioc_timer_start(ioc);
535}
536
537/**
538 * @brief
539 * Hardware initialization failed.
540 */
541static void
542bfa_ioc_sm_initfail(struct bfa_ioc *ioc, enum ioc_event event)
543{
544 switch (event) {
545 case IOC_E_DISABLE:
546 bfa_ioc_timer_stop(ioc);
547 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
548 break;
549
550 case IOC_E_DETACH:
551 bfa_ioc_timer_stop(ioc);
552 bfa_ioc_firmware_unlock(ioc);
553 bfa_fsm_set_state(ioc, bfa_ioc_sm_reset);
554 break;
555
556 case IOC_E_TIMEOUT:
557 bfa_fsm_set_state(ioc, bfa_ioc_sm_semwait);
558 break;
559
560 default:
561 bfa_sm_fault(ioc, event);
562 }
563}
564
565static void
566bfa_ioc_sm_hbfail_entry(struct bfa_ioc *ioc)
567{
568 struct list_head *qe;
569 struct bfa_ioc_hbfail_notify *notify;
570
571 /**
572 * Mark IOC as failed in hardware and stop firmware.
573 */
574 bfa_ioc_lpu_stop(ioc);
575 writel(BFI_IOC_FAIL, ioc->ioc_regs.ioc_fwstate);
576
577 /**
578 * Notify other functions on HB failure.
579 */
580 bfa_ioc_notify_hbfail(ioc);
581
582 /**
583 * Notify driver and common modules registered for notification.
584 */
585 ioc->cbfn->hbfail_cbfn(ioc->bfa);
586 list_for_each(qe, &ioc->hb_notify_q) {
587 notify = (struct bfa_ioc_hbfail_notify *) qe;
588 notify->cbfn(notify->cbarg);
589 }
590
591 /**
592 * Flush any queued up mailbox requests.
593 */
594 bfa_ioc_mbox_hbfail(ioc);
595
596 /**
597 * Trigger auto-recovery after a delay.
598 */
599 if (ioc->auto_recover)
600 mod_timer(&ioc->ioc_timer, jiffies +
601 msecs_to_jiffies(BFA_IOC_TOV_RECOVER));
602}
603
604/**
605 * @brief
606 * IOC heartbeat failure.
607 */
608static void
609bfa_ioc_sm_hbfail(struct bfa_ioc *ioc, enum ioc_event event)
610{
611 switch (event) {
612
613 case IOC_E_ENABLE:
614 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
615 break;
616
617 case IOC_E_DISABLE:
618 if (ioc->auto_recover)
619 bfa_ioc_timer_stop(ioc);
620 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
621 break;
622
623 case IOC_E_TIMEOUT:
624 bfa_fsm_set_state(ioc, bfa_ioc_sm_semwait);
625 break;
626
627 case IOC_E_FWREADY:
628 /**
629 * Recovery is already initiated by other function.
630 */
631 break;
632
633 case IOC_E_HWERROR:
634 /*
635 * HB failure notification, ignore.
636 */
637 break;
638 default:
639 bfa_sm_fault(ioc, event);
640 }
641}
642
643/**
644 * BFA IOC private functions
645 */
646
647static void
648bfa_ioc_disable_comp(struct bfa_ioc *ioc)
649{
650 struct list_head *qe;
651 struct bfa_ioc_hbfail_notify *notify;
652
653 ioc->cbfn->disable_cbfn(ioc->bfa);
654
655 /**
656 * Notify common modules registered for notification.
657 */
658 list_for_each(qe, &ioc->hb_notify_q) {
659 notify = (struct bfa_ioc_hbfail_notify *) qe;
660 notify->cbfn(notify->cbarg);
661 }
662}
663
664void
665bfa_ioc_sem_timeout(void *ioc_arg)
666{
667 struct bfa_ioc *ioc = (struct bfa_ioc *) ioc_arg;
668
669 bfa_ioc_hw_sem_get(ioc);
670}
671
672bool
673bfa_ioc_sem_get(void __iomem *sem_reg)
674{
675 u32 r32;
676 int cnt = 0;
677#define BFA_SEM_SPINCNT 3000
678
679 r32 = readl(sem_reg);
680
681 while (r32 && (cnt < BFA_SEM_SPINCNT)) {
682 cnt++;
683 udelay(2);
684 r32 = readl(sem_reg);
685 }
686
687 if (r32 == 0)
688 return true;
689
690 BUG_ON(!(cnt < BFA_SEM_SPINCNT));
691 return false;
692}
693
694void
695bfa_ioc_sem_release(void __iomem *sem_reg)
696{
697 writel(1, sem_reg);
698}
699
700static void
701bfa_ioc_hw_sem_get(struct bfa_ioc *ioc)
702{
703 u32 r32;
704
705 /**
706 * First read to the semaphore register will return 0, subsequent reads
707 * will return 1. Semaphore is released by writing 1 to the register
708 */
709 r32 = readl(ioc->ioc_regs.ioc_sem_reg);
710 if (r32 == 0) {
711 bfa_fsm_send_event(ioc, IOC_E_SEMLOCKED);
712 return;
713 }
714
715 mod_timer(&ioc->sem_timer, jiffies +
716 msecs_to_jiffies(BFA_IOC_HWSEM_TOV));
717}
718
719void
720bfa_ioc_hw_sem_release(struct bfa_ioc *ioc)
721{
722 writel(1, ioc->ioc_regs.ioc_sem_reg);
723}
724
725static void
726bfa_ioc_hw_sem_get_cancel(struct bfa_ioc *ioc)
727{
728 del_timer(&ioc->sem_timer);
729}
730
731/**
732 * @brief
733 * Initialize LPU local memory (aka secondary memory / SRAM)
734 */
735static void
736bfa_ioc_lmem_init(struct bfa_ioc *ioc)
737{
738 u32 pss_ctl;
739 int i;
740#define PSS_LMEM_INIT_TIME 10000
741
742 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg);
743 pss_ctl &= ~__PSS_LMEM_RESET;
744 pss_ctl |= __PSS_LMEM_INIT_EN;
745
746 /*
747 * i2c workaround 12.5khz clock
748 */
749 pss_ctl |= __PSS_I2C_CLK_DIV(3UL);
750 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
751
752 /**
753 * wait for memory initialization to be complete
754 */
755 i = 0;
756 do {
757 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg);
758 i++;
759 } while (!(pss_ctl & __PSS_LMEM_INIT_DONE) && (i < PSS_LMEM_INIT_TIME));
760
761 /**
762 * If memory initialization is not successful, IOC timeout will catch
763 * such failures.
764 */
765 BUG_ON(!(pss_ctl & __PSS_LMEM_INIT_DONE));
766
767 pss_ctl &= ~(__PSS_LMEM_INIT_DONE | __PSS_LMEM_INIT_EN);
768 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
769}
770
771static void
772bfa_ioc_lpu_start(struct bfa_ioc *ioc)
773{
774 u32 pss_ctl;
775
776 /**
777 * Take processor out of reset.
778 */
779 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg);
780 pss_ctl &= ~__PSS_LPU0_RESET;
781
782 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
783}
784
785static void
786bfa_ioc_lpu_stop(struct bfa_ioc *ioc)
787{
788 u32 pss_ctl;
789
790 /**
791 * Put processors in reset.
792 */
793 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg);
794 pss_ctl |= (__PSS_LPU0_RESET | __PSS_LPU1_RESET);
795
796 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg);
797}
798
799/**
800 * Get driver and firmware versions.
801 */
802void
803bfa_ioc_fwver_get(struct bfa_ioc *ioc, struct bfi_ioc_image_hdr *fwhdr)
804{
805 u32 pgnum, pgoff;
806 u32 loff = 0;
807 int i;
808 u32 *fwsig = (u32 *) fwhdr;
809
810 pgnum = bfa_ioc_smem_pgnum(ioc, loff);
811 pgoff = bfa_ioc_smem_pgoff(ioc, loff);
812 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
813
814 for (i = 0; i < (sizeof(struct bfi_ioc_image_hdr) / sizeof(u32));
815 i++) {
816 fwsig[i] =
817 swab32(readl((loff) + (ioc->ioc_regs.smem_page_start)));
818 loff += sizeof(u32);
819 }
820}
821
822/**
823 * Returns TRUE if same.
824 */
825bool
826bfa_ioc_fwver_cmp(struct bfa_ioc *ioc, struct bfi_ioc_image_hdr *fwhdr)
827{
828 struct bfi_ioc_image_hdr *drv_fwhdr;
829 int i;
830
831 drv_fwhdr = (struct bfi_ioc_image_hdr *)
832 bfa_cb_image_get_chunk(BFA_IOC_FWIMG_TYPE(ioc), 0);
833
834 for (i = 0; i < BFI_IOC_MD5SUM_SZ; i++) {
835 if (fwhdr->md5sum[i] != drv_fwhdr->md5sum[i])
836 return false;
837 }
838
839 return true;
840}
841
842/**
843 * Return true if current running version is valid. Firmware signature and
844 * execution context (driver/bios) must match.
845 */
846static bool
847bfa_ioc_fwver_valid(struct bfa_ioc *ioc)
848{
849 struct bfi_ioc_image_hdr fwhdr, *drv_fwhdr;
850
851 /**
852 * If bios/efi boot (flash based) -- return true
853 */
854 if (bfa_ioc_is_optrom(ioc))
855 return true;
856
857 bfa_ioc_fwver_get(ioc, &fwhdr);
858 drv_fwhdr = (struct bfi_ioc_image_hdr *)
859 bfa_cb_image_get_chunk(BFA_IOC_FWIMG_TYPE(ioc), 0);
860
861 if (fwhdr.signature != drv_fwhdr->signature)
862 return false;
863
864 if (fwhdr.exec != drv_fwhdr->exec)
865 return false;
866
867 return bfa_ioc_fwver_cmp(ioc, &fwhdr);
868}
869
870/**
871 * Conditionally flush any pending message from firmware at start.
872 */
873static void
874bfa_ioc_msgflush(struct bfa_ioc *ioc)
875{
876 u32 r32;
877
878 r32 = readl(ioc->ioc_regs.lpu_mbox_cmd);
879 if (r32)
880 writel(1, ioc->ioc_regs.lpu_mbox_cmd);
881}
882
883/**
884 * @img ioc_init_logic.jpg
885 */
886static void
887bfa_ioc_hwinit(struct bfa_ioc *ioc, bool force)
888{
889 enum bfi_ioc_state ioc_fwstate;
890 bool fwvalid;
891
892 ioc_fwstate = readl(ioc->ioc_regs.ioc_fwstate);
893
894 if (force)
895 ioc_fwstate = BFI_IOC_UNINIT;
896
897 /**
898 * check if firmware is valid
899 */
900 fwvalid = (ioc_fwstate == BFI_IOC_UNINIT) ?
901 false : bfa_ioc_fwver_valid(ioc);
902
903 if (!fwvalid) {
904 bfa_ioc_boot(ioc, BFI_BOOT_TYPE_NORMAL, ioc->pcidev.device_id);
905 return;
906 }
907
908 /**
909 * If hardware initialization is in progress (initialized by other IOC),
910 * just wait for an initialization completion interrupt.
911 */
912 if (ioc_fwstate == BFI_IOC_INITING) {
913 ioc->cbfn->reset_cbfn(ioc->bfa);
914 return;
915 }
916
917 /**
918 * If IOC function is disabled and firmware version is same,
919 * just re-enable IOC.
920 *
921 * If option rom, IOC must not be in operational state. With
922 * convergence, IOC will be in operational state when 2nd driver
923 * is loaded.
924 */
925 if (ioc_fwstate == BFI_IOC_DISABLED ||
926 (!bfa_ioc_is_optrom(ioc) && ioc_fwstate == BFI_IOC_OP)) {
927 /**
928 * When using MSI-X any pending firmware ready event should
929 * be flushed. Otherwise MSI-X interrupts are not delivered.
930 */
931 bfa_ioc_msgflush(ioc);
932 ioc->cbfn->reset_cbfn(ioc->bfa);
933 bfa_fsm_send_event(ioc, IOC_E_FWREADY);
934 return;
935 }
936
937 /**
938 * Initialize the h/w for any other states.
939 */
940 bfa_ioc_boot(ioc, BFI_BOOT_TYPE_NORMAL, ioc->pcidev.device_id);
941}
942
943void
944bfa_ioc_timeout(void *ioc_arg)
945{
946 struct bfa_ioc *ioc = (struct bfa_ioc *) ioc_arg;
947
948 bfa_fsm_send_event(ioc, IOC_E_TIMEOUT);
949}
950
951void
952bfa_ioc_mbox_send(struct bfa_ioc *ioc, void *ioc_msg, int len)
953{
954 u32 *msgp = (u32 *) ioc_msg;
955 u32 i;
956
957 BUG_ON(!(len <= BFI_IOC_MSGLEN_MAX));
958
959 /*
960 * first write msg to mailbox registers
961 */
962 for (i = 0; i < len / sizeof(u32); i++)
963 writel(cpu_to_le32(msgp[i]),
964 ioc->ioc_regs.hfn_mbox + i * sizeof(u32));
965
966 for (; i < BFI_IOC_MSGLEN_MAX / sizeof(u32); i++)
967 writel(0, ioc->ioc_regs.hfn_mbox + i * sizeof(u32));
968
969 /*
970 * write 1 to mailbox CMD to trigger LPU event
971 */
972 writel(1, ioc->ioc_regs.hfn_mbox_cmd);
973 (void) readl(ioc->ioc_regs.hfn_mbox_cmd);
974}
975
976static void
977bfa_ioc_send_enable(struct bfa_ioc *ioc)
978{
979 struct bfi_ioc_ctrl_req enable_req;
980 struct timeval tv;
981
982 bfi_h2i_set(enable_req.mh, BFI_MC_IOC, BFI_IOC_H2I_ENABLE_REQ,
983 bfa_ioc_portid(ioc));
984 enable_req.ioc_class = ioc->ioc_mc;
985 do_gettimeofday(&tv);
986 enable_req.tv_sec = ntohl(tv.tv_sec);
987 bfa_ioc_mbox_send(ioc, &enable_req, sizeof(struct bfi_ioc_ctrl_req));
988}
989
990static void
991bfa_ioc_send_disable(struct bfa_ioc *ioc)
992{
993 struct bfi_ioc_ctrl_req disable_req;
994
995 bfi_h2i_set(disable_req.mh, BFI_MC_IOC, BFI_IOC_H2I_DISABLE_REQ,
996 bfa_ioc_portid(ioc));
997 bfa_ioc_mbox_send(ioc, &disable_req, sizeof(struct bfi_ioc_ctrl_req));
998}
999
1000static void
1001bfa_ioc_send_getattr(struct bfa_ioc *ioc)
1002{
1003 struct bfi_ioc_getattr_req attr_req;
1004
1005 bfi_h2i_set(attr_req.mh, BFI_MC_IOC, BFI_IOC_H2I_GETATTR_REQ,
1006 bfa_ioc_portid(ioc));
1007 bfa_dma_be_addr_set(attr_req.attr_addr, ioc->attr_dma.pa);
1008 bfa_ioc_mbox_send(ioc, &attr_req, sizeof(attr_req));
1009}
1010
1011void
1012bfa_ioc_hb_check(void *cbarg)
1013{
1014 struct bfa_ioc *ioc = cbarg;
1015 u32 hb_count;
1016
1017 hb_count = readl(ioc->ioc_regs.heartbeat);
1018 if (ioc->hb_count == hb_count) {
1019 pr_crit("Firmware heartbeat failure at %d", hb_count);
1020 bfa_ioc_recover(ioc);
1021 return;
1022 } else {
1023 ioc->hb_count = hb_count;
1024 }
1025
1026 bfa_ioc_mbox_poll(ioc);
1027 mod_timer(&ioc->hb_timer, jiffies +
1028 msecs_to_jiffies(BFA_IOC_HB_TOV));
1029}
1030
1031static void
1032bfa_ioc_hb_monitor(struct bfa_ioc *ioc)
1033{
1034 ioc->hb_count = readl(ioc->ioc_regs.heartbeat);
1035 mod_timer(&ioc->hb_timer, jiffies +
1036 msecs_to_jiffies(BFA_IOC_HB_TOV));
1037}
1038
1039static void
1040bfa_ioc_hb_stop(struct bfa_ioc *ioc)
1041{
1042 del_timer(&ioc->hb_timer);
1043}
1044
1045/**
1046 * @brief
1047 * Initiate a full firmware download.
1048 */
1049static void
1050bfa_ioc_download_fw(struct bfa_ioc *ioc, u32 boot_type,
1051 u32 boot_param)
1052{
1053 u32 *fwimg;
1054 u32 pgnum, pgoff;
1055 u32 loff = 0;
1056 u32 chunkno = 0;
1057 u32 i;
1058
1059 /**
1060 * Initialize LMEM first before code download
1061 */
1062 bfa_ioc_lmem_init(ioc);
1063
1064 /**
1065 * Flash based firmware boot
1066 */
1067 if (bfa_ioc_is_optrom(ioc))
1068 boot_type = BFI_BOOT_TYPE_FLASH;
1069 fwimg = bfa_cb_image_get_chunk(BFA_IOC_FWIMG_TYPE(ioc), chunkno);
1070
1071 pgnum = bfa_ioc_smem_pgnum(ioc, loff);
1072 pgoff = bfa_ioc_smem_pgoff(ioc, loff);
1073
1074 writel(pgnum, ioc->ioc_regs.host_page_num_fn);
1075
1076 for (i = 0; i < bfa_cb_image_get_size(BFA_IOC_FWIMG_TYPE(ioc)); i++) {
1077 if (BFA_IOC_FLASH_CHUNK_NO(i) != chunkno) {
1078 chunkno = BFA_IOC_FLASH_CHUNK_NO(i);
1079 fwimg = bfa_cb_image_get_chunk(BFA_IOC_FWIMG_TYPE(ioc),
1080 BFA_IOC_FLASH_CHUNK_ADDR(chunkno));
1081 }
1082
1083 /**
1084 * write smem
1085 */
1086 writel((swab32(fwimg[BFA_IOC_FLASH_OFFSET_IN_CHUNK(i)])),
1087 ((ioc->ioc_regs.smem_page_start) + (loff)));
1088
1089 loff += sizeof(u32);
1090
1091 /**
1092 * handle page offset wrap around
1093 */
1094 loff = PSS_SMEM_PGOFF(loff);
1095 if (loff == 0) {
1096 pgnum++;
1097 writel(pgnum,
1098 ioc->ioc_regs.host_page_num_fn);
1099 }
1100 }
1101
1102 writel(bfa_ioc_smem_pgnum(ioc, 0),
1103 ioc->ioc_regs.host_page_num_fn);
1104
1105 /*
1106 * Set boot type and boot param at the end.
1107 */
1108 writel((swab32(swab32(boot_type))), ((ioc->ioc_regs.smem_page_start)
1109 + (BFI_BOOT_TYPE_OFF)));
1110 writel((swab32(swab32(boot_param))), ((ioc->ioc_regs.smem_page_start)
1111 + (BFI_BOOT_PARAM_OFF)));
1112}
1113
1114static void
1115bfa_ioc_reset(struct bfa_ioc *ioc, bool force)
1116{
1117 bfa_ioc_hwinit(ioc, force);
1118}
1119
1120/**
1121 * @brief
1122 * Update BFA configuration from firmware configuration.
1123 */
1124static void
1125bfa_ioc_getattr_reply(struct bfa_ioc *ioc)
1126{
1127 struct bfi_ioc_attr *attr = ioc->attr;
1128
1129 attr->adapter_prop = ntohl(attr->adapter_prop);
1130 attr->card_type = ntohl(attr->card_type);
1131 attr->maxfrsize = ntohs(attr->maxfrsize);
1132
1133 bfa_fsm_send_event(ioc, IOC_E_FWRSP_GETATTR);
1134}
1135
1136/**
1137 * Attach time initialization of mbox logic.
1138 */
1139static void
1140bfa_ioc_mbox_attach(struct bfa_ioc *ioc)
1141{
1142 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
1143 int mc;
1144
1145 INIT_LIST_HEAD(&mod->cmd_q);
1146 for (mc = 0; mc < BFI_MC_MAX; mc++) {
1147 mod->mbhdlr[mc].cbfn = NULL;
1148 mod->mbhdlr[mc].cbarg = ioc->bfa;
1149 }
1150}
1151
1152/**
1153 * Mbox poll timer -- restarts any pending mailbox requests.
1154 */
1155static void
1156bfa_ioc_mbox_poll(struct bfa_ioc *ioc)
1157{
1158 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
1159 struct bfa_mbox_cmd *cmd;
1160 u32 stat;
1161
1162 /**
1163 * If no command pending, do nothing
1164 */
1165 if (list_empty(&mod->cmd_q))
1166 return;
1167
1168 /**
1169 * If previous command is not yet fetched by firmware, do nothing
1170 */
1171 stat = readl(ioc->ioc_regs.hfn_mbox_cmd);
1172 if (stat)
1173 return;
1174
1175 /**
1176 * Enqueue command to firmware.
1177 */
1178 bfa_q_deq(&mod->cmd_q, &cmd);
1179 bfa_ioc_mbox_send(ioc, cmd->msg, sizeof(cmd->msg));
1180}
1181
1182/**
1183 * Cleanup any pending requests.
1184 */
1185static void
1186bfa_ioc_mbox_hbfail(struct bfa_ioc *ioc)
1187{
1188 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
1189 struct bfa_mbox_cmd *cmd;
1190
1191 while (!list_empty(&mod->cmd_q))
1192 bfa_q_deq(&mod->cmd_q, &cmd);
1193}
1194
1195/**
1196 * IOC public
1197 */
1198enum bfa_status
1199bfa_ioc_pll_init(struct bfa_ioc *ioc)
1200{
1201 /*
1202 * Hold semaphore so that nobody can access the chip during init.
1203 */
1204 bfa_ioc_sem_get(ioc->ioc_regs.ioc_init_sem_reg);
1205
1206 bfa_ioc_pll_init_asic(ioc);
1207
1208 ioc->pllinit = true;
1209 /*
1210 * release semaphore.
1211 */
1212 bfa_ioc_sem_release(ioc->ioc_regs.ioc_init_sem_reg);
1213
1214 return BFA_STATUS_OK;
1215}
1216
1217/**
1218 * Interface used by diag module to do firmware boot with memory test
1219 * as the entry vector.
1220 */
1221void
1222bfa_ioc_boot(struct bfa_ioc *ioc, u32 boot_type, u32 boot_param)
1223{
1224 void __iomem *rb;
1225
1226 bfa_ioc_stats(ioc, ioc_boots);
1227
1228 if (bfa_ioc_pll_init(ioc) != BFA_STATUS_OK)
1229 return;
1230
1231 /**
1232 * Initialize IOC state of all functions on a chip reset.
1233 */
1234 rb = ioc->pcidev.pci_bar_kva;
1235 if (boot_param == BFI_BOOT_TYPE_MEMTEST) {
1236 writel(BFI_IOC_MEMTEST, (rb + BFA_IOC0_STATE_REG));
1237 writel(BFI_IOC_MEMTEST, (rb + BFA_IOC1_STATE_REG));
1238 } else {
1239 writel(BFI_IOC_INITING, (rb + BFA_IOC0_STATE_REG));
1240 writel(BFI_IOC_INITING, (rb + BFA_IOC1_STATE_REG));
1241 }
1242
1243 bfa_ioc_msgflush(ioc);
1244 bfa_ioc_download_fw(ioc, boot_type, boot_param);
1245
1246 /**
1247 * Enable interrupts just before starting LPU
1248 */
1249 ioc->cbfn->reset_cbfn(ioc->bfa);
1250 bfa_ioc_lpu_start(ioc);
1251}
1252
1253/**
1254 * Enable/disable IOC failure auto recovery.
1255 */
1256void
1257bfa_ioc_auto_recover(bool auto_recover)
1258{
1259 bfa_auto_recover = auto_recover;
1260}
1261
1262bool
1263bfa_ioc_is_operational(struct bfa_ioc *ioc)
1264{
1265 return bfa_fsm_cmp_state(ioc, bfa_ioc_sm_op);
1266}
1267
1268bool
1269bfa_ioc_is_initialized(struct bfa_ioc *ioc)
1270{
1271 u32 r32 = readl(ioc->ioc_regs.ioc_fwstate);
1272
1273 return ((r32 != BFI_IOC_UNINIT) &&
1274 (r32 != BFI_IOC_INITING) &&
1275 (r32 != BFI_IOC_MEMTEST));
1276}
1277
1278void
1279bfa_ioc_msgget(struct bfa_ioc *ioc, void *mbmsg)
1280{
1281 u32 *msgp = mbmsg;
1282 u32 r32;
1283 int i;
1284
1285 /**
1286 * read the MBOX msg
1287 */
1288 for (i = 0; i < (sizeof(union bfi_ioc_i2h_msg_u) / sizeof(u32));
1289 i++) {
1290 r32 = readl(ioc->ioc_regs.lpu_mbox +
1291 i * sizeof(u32));
1292 msgp[i] = htonl(r32);
1293 }
1294
1295 /**
1296 * turn off mailbox interrupt by clearing mailbox status
1297 */
1298 writel(1, ioc->ioc_regs.lpu_mbox_cmd);
1299 readl(ioc->ioc_regs.lpu_mbox_cmd);
1300}
1301
1302void
1303bfa_ioc_isr(struct bfa_ioc *ioc, struct bfi_mbmsg *m)
1304{
1305 union bfi_ioc_i2h_msg_u *msg;
1306
1307 msg = (union bfi_ioc_i2h_msg_u *) m;
1308
1309 bfa_ioc_stats(ioc, ioc_isrs);
1310
1311 switch (msg->mh.msg_id) {
1312 case BFI_IOC_I2H_HBEAT:
1313 break;
1314
1315 case BFI_IOC_I2H_READY_EVENT:
1316 bfa_fsm_send_event(ioc, IOC_E_FWREADY);
1317 break;
1318
1319 case BFI_IOC_I2H_ENABLE_REPLY:
1320 bfa_fsm_send_event(ioc, IOC_E_FWRSP_ENABLE);
1321 break;
1322
1323 case BFI_IOC_I2H_DISABLE_REPLY:
1324 bfa_fsm_send_event(ioc, IOC_E_FWRSP_DISABLE);
1325 break;
1326
1327 case BFI_IOC_I2H_GETATTR_REPLY:
1328 bfa_ioc_getattr_reply(ioc);
1329 break;
1330
1331 default:
1332 BUG_ON(1);
1333 }
1334}
1335
1336/**
1337 * IOC attach time initialization and setup.
1338 *
1339 * @param[in] ioc memory for IOC
1340 * @param[in] bfa driver instance structure
1341 */
1342void
1343bfa_ioc_attach(struct bfa_ioc *ioc, void *bfa, struct bfa_ioc_cbfn *cbfn)
1344{
1345 ioc->bfa = bfa;
1346 ioc->cbfn = cbfn;
1347 ioc->fcmode = false;
1348 ioc->pllinit = false;
1349 ioc->dbg_fwsave_once = true;
1350
1351 bfa_ioc_mbox_attach(ioc);
1352 INIT_LIST_HEAD(&ioc->hb_notify_q);
1353
1354 bfa_fsm_set_state(ioc, bfa_ioc_sm_reset);
1355}
1356
1357/**
1358 * Driver detach time IOC cleanup.
1359 */
1360void
1361bfa_ioc_detach(struct bfa_ioc *ioc)
1362{
1363 bfa_fsm_send_event(ioc, IOC_E_DETACH);
1364}
1365
1366/**
1367 * Setup IOC PCI properties.
1368 *
1369 * @param[in] pcidev PCI device information for this IOC
1370 */
1371void
1372bfa_ioc_pci_init(struct bfa_ioc *ioc, struct bfa_pcidev *pcidev,
1373 enum bfi_mclass mc)
1374{
1375 ioc->ioc_mc = mc;
1376 ioc->pcidev = *pcidev;
1377 ioc->ctdev = bfa_asic_id_ct(ioc->pcidev.device_id);
1378 ioc->cna = ioc->ctdev && !ioc->fcmode;
1379
1380 bfa_ioc_set_ct_hwif(ioc);
1381
1382 bfa_ioc_map_port(ioc);
1383 bfa_ioc_reg_init(ioc);
1384}
1385
1386/**
1387 * Initialize IOC dma memory
1388 *
1389 * @param[in] dm_kva kernel virtual address of IOC dma memory
1390 * @param[in] dm_pa physical address of IOC dma memory
1391 */
1392void
1393bfa_ioc_mem_claim(struct bfa_ioc *ioc, u8 *dm_kva, u64 dm_pa)
1394{
1395 /**
1396 * dma memory for firmware attribute
1397 */
1398 ioc->attr_dma.kva = dm_kva;
1399 ioc->attr_dma.pa = dm_pa;
1400 ioc->attr = (struct bfi_ioc_attr *) dm_kva;
1401}
1402
1403/**
1404 * Return size of dma memory required.
1405 */
1406u32
1407bfa_ioc_meminfo(void)
1408{
1409 return roundup(sizeof(struct bfi_ioc_attr), BFA_DMA_ALIGN_SZ);
1410}
1411
1412void
1413bfa_ioc_enable(struct bfa_ioc *ioc)
1414{
1415 bfa_ioc_stats(ioc, ioc_enables);
1416 ioc->dbg_fwsave_once = true;
1417
1418 bfa_fsm_send_event(ioc, IOC_E_ENABLE);
1419}
1420
1421void
1422bfa_ioc_disable(struct bfa_ioc *ioc)
1423{
1424 bfa_ioc_stats(ioc, ioc_disables);
1425 bfa_fsm_send_event(ioc, IOC_E_DISABLE);
1426}
1427
1428u32
1429bfa_ioc_smem_pgnum(struct bfa_ioc *ioc, u32 fmaddr)
1430{
1431 return PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, fmaddr);
1432}
1433
1434u32
1435bfa_ioc_smem_pgoff(struct bfa_ioc *ioc, u32 fmaddr)
1436{
1437 return PSS_SMEM_PGOFF(fmaddr);
1438}
1439
1440/**
1441 * Register mailbox message handler functions
1442 *
1443 * @param[in] ioc IOC instance
1444 * @param[in] mcfuncs message class handler functions
1445 */
1446void
1447bfa_ioc_mbox_register(struct bfa_ioc *ioc, bfa_ioc_mbox_mcfunc_t *mcfuncs)
1448{
1449 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
1450 int mc;
1451
1452 for (mc = 0; mc < BFI_MC_MAX; mc++)
1453 mod->mbhdlr[mc].cbfn = mcfuncs[mc];
1454}
1455
1456/**
1457 * Register mailbox message handler function, to be called by common modules
1458 */
1459void
1460bfa_ioc_mbox_regisr(struct bfa_ioc *ioc, enum bfi_mclass mc,
1461 bfa_ioc_mbox_mcfunc_t cbfn, void *cbarg)
1462{
1463 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
1464
1465 mod->mbhdlr[mc].cbfn = cbfn;
1466 mod->mbhdlr[mc].cbarg = cbarg;
1467}
1468
1469/**
1470 * Queue a mailbox command request to firmware. Waits if mailbox is busy.
1471 * Responsibility of caller to serialize
1472 *
1473 * @param[in] ioc IOC instance
1474 * @param[i] cmd Mailbox command
1475 */
1476void
1477bfa_ioc_mbox_queue(struct bfa_ioc *ioc, struct bfa_mbox_cmd *cmd)
1478{
1479 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
1480 u32 stat;
1481
1482 /**
1483 * If a previous command is pending, queue new command
1484 */
1485 if (!list_empty(&mod->cmd_q)) {
1486 list_add_tail(&cmd->qe, &mod->cmd_q);
1487 return;
1488 }
1489
1490 /**
1491 * If mailbox is busy, queue command for poll timer
1492 */
1493 stat = readl(ioc->ioc_regs.hfn_mbox_cmd);
1494 if (stat) {
1495 list_add_tail(&cmd->qe, &mod->cmd_q);
1496 return;
1497 }
1498
1499 /**
1500 * mailbox is free -- queue command to firmware
1501 */
1502 bfa_ioc_mbox_send(ioc, cmd->msg, sizeof(cmd->msg));
1503}
1504
1505/**
1506 * Handle mailbox interrupts
1507 */
1508void
1509bfa_ioc_mbox_isr(struct bfa_ioc *ioc)
1510{
1511 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod;
1512 struct bfi_mbmsg m;
1513 int mc;
1514
1515 bfa_ioc_msgget(ioc, &m);
1516
1517 /**
1518 * Treat IOC message class as special.
1519 */
1520 mc = m.mh.msg_class;
1521 if (mc == BFI_MC_IOC) {
1522 bfa_ioc_isr(ioc, &m);
1523 return;
1524 }
1525
1526 if ((mc > BFI_MC_MAX) || (mod->mbhdlr[mc].cbfn == NULL))
1527 return;
1528
1529 mod->mbhdlr[mc].cbfn(mod->mbhdlr[mc].cbarg, &m);
1530}
1531
1532void
1533bfa_ioc_error_isr(struct bfa_ioc *ioc)
1534{
1535 bfa_fsm_send_event(ioc, IOC_E_HWERROR);
1536}
1537
1538void
1539bfa_ioc_set_fcmode(struct bfa_ioc *ioc)
1540{
1541 ioc->fcmode = true;
1542 ioc->port_id = bfa_ioc_pcifn(ioc);
1543}
1544
1545/**
1546 * return true if IOC is disabled
1547 */
1548bool
1549bfa_ioc_is_disabled(struct bfa_ioc *ioc)
1550{
1551 return bfa_fsm_cmp_state(ioc, bfa_ioc_sm_disabling) ||
1552 bfa_fsm_cmp_state(ioc, bfa_ioc_sm_disabled);
1553}
1554
1555/**
1556 * return true if IOC firmware is different.
1557 */
1558bool
1559bfa_ioc_fw_mismatch(struct bfa_ioc *ioc)
1560{
1561 return bfa_fsm_cmp_state(ioc, bfa_ioc_sm_reset) ||
1562 bfa_fsm_cmp_state(ioc, bfa_ioc_sm_fwcheck) ||
1563 bfa_fsm_cmp_state(ioc, bfa_ioc_sm_mismatch);
1564}
1565
1566#define bfa_ioc_state_disabled(__sm) \
1567 (((__sm) == BFI_IOC_UNINIT) || \
1568 ((__sm) == BFI_IOC_INITING) || \
1569 ((__sm) == BFI_IOC_HWINIT) || \
1570 ((__sm) == BFI_IOC_DISABLED) || \
1571 ((__sm) == BFI_IOC_FAIL) || \
1572 ((__sm) == BFI_IOC_CFG_DISABLED))
1573
1574/**
1575 * Check if adapter is disabled -- both IOCs should be in a disabled
1576 * state.
1577 */
1578bool
1579bfa_ioc_adapter_is_disabled(struct bfa_ioc *ioc)
1580{
1581 u32 ioc_state;
1582 void __iomem *rb = ioc->pcidev.pci_bar_kva;
1583
1584 if (!bfa_fsm_cmp_state(ioc, bfa_ioc_sm_disabled))
1585 return false;
1586
1587 ioc_state = readl(rb + BFA_IOC0_STATE_REG);
1588 if (!bfa_ioc_state_disabled(ioc_state))
1589 return false;
1590
1591 if (ioc->pcidev.device_id != PCI_DEVICE_ID_BROCADE_FC_8G1P) {
1592 ioc_state = readl(rb + BFA_IOC1_STATE_REG);
1593 if (!bfa_ioc_state_disabled(ioc_state))
1594 return false;
1595 }
1596
1597 return true;
1598}
1599
1600/**
1601 * Add to IOC heartbeat failure notification queue. To be used by common
1602 * modules such as cee, port, diag.
1603 */
1604void
1605bfa_ioc_hbfail_register(struct bfa_ioc *ioc,
1606 struct bfa_ioc_hbfail_notify *notify)
1607{
1608 list_add_tail(&notify->qe, &ioc->hb_notify_q);
1609}
1610
1611#define BFA_MFG_NAME "Brocade"
1612void
1613bfa_ioc_get_adapter_attr(struct bfa_ioc *ioc,
1614 struct bfa_adapter_attr *ad_attr)
1615{
1616 struct bfi_ioc_attr *ioc_attr;
1617
1618 ioc_attr = ioc->attr;
1619
1620 bfa_ioc_get_adapter_serial_num(ioc, ad_attr->serial_num);
1621 bfa_ioc_get_adapter_fw_ver(ioc, ad_attr->fw_ver);
1622 bfa_ioc_get_adapter_optrom_ver(ioc, ad_attr->optrom_ver);
1623 bfa_ioc_get_adapter_manufacturer(ioc, ad_attr->manufacturer);
1624 memcpy(&ad_attr->vpd, &ioc_attr->vpd,
1625 sizeof(struct bfa_mfg_vpd));
1626
1627 ad_attr->nports = bfa_ioc_get_nports(ioc);
1628 ad_attr->max_speed = bfa_ioc_speed_sup(ioc);
1629
1630 bfa_ioc_get_adapter_model(ioc, ad_attr->model);
1631 /* For now, model descr uses same model string */
1632 bfa_ioc_get_adapter_model(ioc, ad_attr->model_descr);
1633
1634 ad_attr->card_type = ioc_attr->card_type;
1635 ad_attr->is_mezz = bfa_mfg_is_mezz(ioc_attr->card_type);
1636
1637 if (BFI_ADAPTER_IS_SPECIAL(ioc_attr->adapter_prop))
1638 ad_attr->prototype = 1;
1639 else
1640 ad_attr->prototype = 0;
1641
1642 ad_attr->pwwn = bfa_ioc_get_pwwn(ioc);
1643 ad_attr->mac = bfa_ioc_get_mac(ioc);
1644
1645 ad_attr->pcie_gen = ioc_attr->pcie_gen;
1646 ad_attr->pcie_lanes = ioc_attr->pcie_lanes;
1647 ad_attr->pcie_lanes_orig = ioc_attr->pcie_lanes_orig;
1648 ad_attr->asic_rev = ioc_attr->asic_rev;
1649
1650 bfa_ioc_get_pci_chip_rev(ioc, ad_attr->hw_ver);
1651
1652 ad_attr->cna_capable = ioc->cna;
1653 ad_attr->trunk_capable = (ad_attr->nports > 1) && !ioc->cna;
1654}
1655
1656enum bfa_ioc_type
1657bfa_ioc_get_type(struct bfa_ioc *ioc)
1658{
1659 if (!ioc->ctdev || ioc->fcmode)
1660 return BFA_IOC_TYPE_FC;
1661 else if (ioc->ioc_mc == BFI_MC_IOCFC)
1662 return BFA_IOC_TYPE_FCoE;
1663 else if (ioc->ioc_mc == BFI_MC_LL)
1664 return BFA_IOC_TYPE_LL;
1665 else {
1666 BUG_ON(!(ioc->ioc_mc == BFI_MC_LL));
1667 return BFA_IOC_TYPE_LL;
1668 }
1669}
1670
1671void
1672bfa_ioc_get_adapter_serial_num(struct bfa_ioc *ioc, char *serial_num)
1673{
1674 memset(serial_num, 0, BFA_ADAPTER_SERIAL_NUM_LEN);
1675 memcpy(serial_num,
1676 (void *)ioc->attr->brcd_serialnum,
1677 BFA_ADAPTER_SERIAL_NUM_LEN);
1678}
1679
1680void
1681bfa_ioc_get_adapter_fw_ver(struct bfa_ioc *ioc, char *fw_ver)
1682{
1683 memset(fw_ver, 0, BFA_VERSION_LEN);
1684 memcpy(fw_ver, ioc->attr->fw_version, BFA_VERSION_LEN);
1685}
1686
1687void
1688bfa_ioc_get_pci_chip_rev(struct bfa_ioc *ioc, char *chip_rev)
1689{
1690 BUG_ON(!(chip_rev));
1691
1692 memset(chip_rev, 0, BFA_IOC_CHIP_REV_LEN);
1693
1694 chip_rev[0] = 'R';
1695 chip_rev[1] = 'e';
1696 chip_rev[2] = 'v';
1697 chip_rev[3] = '-';
1698 chip_rev[4] = ioc->attr->asic_rev;
1699 chip_rev[5] = '\0';
1700}
1701
1702void
1703bfa_ioc_get_adapter_optrom_ver(struct bfa_ioc *ioc, char *optrom_ver)
1704{
1705 memset(optrom_ver, 0, BFA_VERSION_LEN);
1706 memcpy(optrom_ver, ioc->attr->optrom_version,
1707 BFA_VERSION_LEN);
1708}
1709
1710void
1711bfa_ioc_get_adapter_manufacturer(struct bfa_ioc *ioc, char *manufacturer)
1712{
1713 memset(manufacturer, 0, BFA_ADAPTER_MFG_NAME_LEN);
1714 memcpy(manufacturer, BFA_MFG_NAME, BFA_ADAPTER_MFG_NAME_LEN);
1715}
1716
1717void
1718bfa_ioc_get_adapter_model(struct bfa_ioc *ioc, char *model)
1719{
1720 struct bfi_ioc_attr *ioc_attr;
1721
1722 BUG_ON(!(model));
1723 memset(model, 0, BFA_ADAPTER_MODEL_NAME_LEN);
1724
1725 ioc_attr = ioc->attr;
1726
1727 /**
1728 * model name
1729 */
1730 snprintf(model, BFA_ADAPTER_MODEL_NAME_LEN, "%s-%u",
1731 BFA_MFG_NAME, ioc_attr->card_type);
1732}
1733
1734enum bfa_ioc_state
1735bfa_ioc_get_state(struct bfa_ioc *ioc)
1736{
1737 return bfa_sm_to_state(ioc_sm_table, ioc->fsm);
1738}
1739
1740void
1741bfa_ioc_get_attr(struct bfa_ioc *ioc, struct bfa_ioc_attr *ioc_attr)
1742{
1743 memset((void *)ioc_attr, 0, sizeof(struct bfa_ioc_attr));
1744
1745 ioc_attr->state = bfa_ioc_get_state(ioc);
1746 ioc_attr->port_id = ioc->port_id;
1747
1748 ioc_attr->ioc_type = bfa_ioc_get_type(ioc);
1749
1750 bfa_ioc_get_adapter_attr(ioc, &ioc_attr->adapter_attr);
1751
1752 ioc_attr->pci_attr.device_id = ioc->pcidev.device_id;
1753 ioc_attr->pci_attr.pcifn = ioc->pcidev.pci_func;
1754 bfa_ioc_get_pci_chip_rev(ioc, ioc_attr->pci_attr.chip_rev);
1755}
1756
1757/**
1758 * WWN public
1759 */
1760u64
1761bfa_ioc_get_pwwn(struct bfa_ioc *ioc)
1762{
1763 return ioc->attr->pwwn;
1764}
1765
1766u64
1767bfa_ioc_get_nwwn(struct bfa_ioc *ioc)
1768{
1769 return ioc->attr->nwwn;
1770}
1771
1772u64
1773bfa_ioc_get_adid(struct bfa_ioc *ioc)
1774{
1775 return ioc->attr->mfg_pwwn;
1776}
1777
1778mac_t
1779bfa_ioc_get_mac(struct bfa_ioc *ioc)
1780{
1781 /*
1782 * Currently mfg mac is used as FCoE enode mac (not configured by PBC)
1783 */
1784 if (bfa_ioc_get_type(ioc) == BFA_IOC_TYPE_FCoE)
1785 return bfa_ioc_get_mfg_mac(ioc);
1786 else
1787 return ioc->attr->mac;
1788}
1789
1790u64
1791bfa_ioc_get_mfg_pwwn(struct bfa_ioc *ioc)
1792{
1793 return ioc->attr->mfg_pwwn;
1794}
1795
1796u64
1797bfa_ioc_get_mfg_nwwn(struct bfa_ioc *ioc)
1798{
1799 return ioc->attr->mfg_nwwn;
1800}
1801
1802mac_t
1803bfa_ioc_get_mfg_mac(struct bfa_ioc *ioc)
1804{
1805 mac_t m;
1806
1807 m = ioc->attr->mfg_mac;
1808 if (bfa_mfg_is_old_wwn_mac_model(ioc->attr->card_type))
1809 m.mac[MAC_ADDRLEN - 1] += bfa_ioc_pcifn(ioc);
1810 else
1811 bfa_mfg_increment_wwn_mac(&(m.mac[MAC_ADDRLEN-3]),
1812 bfa_ioc_pcifn(ioc));
1813
1814 return m;
1815}
1816
1817bool
1818bfa_ioc_get_fcmode(struct bfa_ioc *ioc)
1819{
1820 return ioc->fcmode || !bfa_asic_id_ct(ioc->pcidev.device_id);
1821}
1822
1823/**
1824 * Firmware failure detected. Start recovery actions.
1825 */
1826static void
1827bfa_ioc_recover(struct bfa_ioc *ioc)
1828{
1829 bfa_ioc_stats(ioc, ioc_hbfails);
1830 bfa_fsm_send_event(ioc, IOC_E_HBFAIL);
1831}
1832
1833static void
1834bfa_ioc_check_attr_wwns(struct bfa_ioc *ioc)
1835{
1836 if (bfa_ioc_get_type(ioc) == BFA_IOC_TYPE_LL)
1837 return;
1838
1839}
diff --git a/drivers/net/bna/bfa_ioc.h b/drivers/net/bna/bfa_ioc.h
new file mode 100644
index 000000000000..2e5c0adef899
--- /dev/null
+++ b/drivers/net/bna/bfa_ioc.h
@@ -0,0 +1,343 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18
19#ifndef __BFA_IOC_H__
20#define __BFA_IOC_H__
21
22#include "bfa_sm.h"
23#include "bfi.h"
24#include "cna.h"
25
26#define BFA_IOC_TOV 3000 /* msecs */
27#define BFA_IOC_HWSEM_TOV 500 /* msecs */
28#define BFA_IOC_HB_TOV 500 /* msecs */
29#define BFA_IOC_HWINIT_MAX 2
30#define BFA_IOC_TOV_RECOVER BFA_IOC_HB_TOV
31
32/**
33 * Generic Scatter Gather Element used by driver
34 */
35struct bfa_sge {
36 u32 sg_len;
37 void *sg_addr;
38};
39
40/**
41 * PCI device information required by IOC
42 */
43struct bfa_pcidev {
44 int pci_slot;
45 u8 pci_func;
46 u16 device_id;
47 void __iomem *pci_bar_kva;
48};
49
50/**
51 * Structure used to remember the DMA-able memory block's KVA and Physical
52 * Address
53 */
54struct bfa_dma {
55 void *kva; /* ! Kernel virtual address */
56 u64 pa; /* ! Physical address */
57};
58
59#define BFA_DMA_ALIGN_SZ 256
60
61/**
62 * smem size for Crossbow and Catapult
63 */
64#define BFI_SMEM_CB_SIZE 0x200000U /* ! 2MB for crossbow */
65#define BFI_SMEM_CT_SIZE 0x280000U /* ! 2.5MB for catapult */
66
67/**
68 * @brief BFA dma address assignment macro
69 */
70#define bfa_dma_addr_set(dma_addr, pa) \
71 __bfa_dma_addr_set(&dma_addr, (u64)pa)
72
73static inline void
74__bfa_dma_addr_set(union bfi_addr_u *dma_addr, u64 pa)
75{
76 dma_addr->a32.addr_lo = (u32) pa;
77 dma_addr->a32.addr_hi = (u32) (upper_32_bits(pa));
78}
79
80/**
81 * @brief BFA dma address assignment macro. (big endian format)
82 */
83#define bfa_dma_be_addr_set(dma_addr, pa) \
84 __bfa_dma_be_addr_set(&dma_addr, (u64)pa)
85static inline void
86__bfa_dma_be_addr_set(union bfi_addr_u *dma_addr, u64 pa)
87{
88 dma_addr->a32.addr_lo = (u32) htonl(pa);
89 dma_addr->a32.addr_hi = (u32) htonl(upper_32_bits(pa));
90}
91
92struct bfa_ioc_regs {
93 void __iomem *hfn_mbox_cmd;
94 void __iomem *hfn_mbox;
95 void __iomem *lpu_mbox_cmd;
96 void __iomem *lpu_mbox;
97 void __iomem *pss_ctl_reg;
98 void __iomem *pss_err_status_reg;
99 void __iomem *app_pll_fast_ctl_reg;
100 void __iomem *app_pll_slow_ctl_reg;
101 void __iomem *ioc_sem_reg;
102 void __iomem *ioc_usage_sem_reg;
103 void __iomem *ioc_init_sem_reg;
104 void __iomem *ioc_usage_reg;
105 void __iomem *host_page_num_fn;
106 void __iomem *heartbeat;
107 void __iomem *ioc_fwstate;
108 void __iomem *ll_halt;
109 void __iomem *err_set;
110 void __iomem *shirq_isr_next;
111 void __iomem *shirq_msk_next;
112 void __iomem *smem_page_start;
113 u32 smem_pg0;
114};
115
116/**
117 * IOC Mailbox structures
118 */
119struct bfa_mbox_cmd {
120 struct list_head qe;
121 u32 msg[BFI_IOC_MSGSZ];
122};
123
124/**
125 * IOC mailbox module
126 */
127typedef void (*bfa_ioc_mbox_mcfunc_t)(void *cbarg, struct bfi_mbmsg *m);
128struct bfa_ioc_mbox_mod {
129 struct list_head cmd_q; /*!< pending mbox queue */
130 int nmclass; /*!< number of handlers */
131 struct {
132 bfa_ioc_mbox_mcfunc_t cbfn; /*!< message handlers */
133 void *cbarg;
134 } mbhdlr[BFI_MC_MAX];
135};
136
137/**
138 * IOC callback function interfaces
139 */
140typedef void (*bfa_ioc_enable_cbfn_t)(void *bfa, enum bfa_status status);
141typedef void (*bfa_ioc_disable_cbfn_t)(void *bfa);
142typedef void (*bfa_ioc_hbfail_cbfn_t)(void *bfa);
143typedef void (*bfa_ioc_reset_cbfn_t)(void *bfa);
144struct bfa_ioc_cbfn {
145 bfa_ioc_enable_cbfn_t enable_cbfn;
146 bfa_ioc_disable_cbfn_t disable_cbfn;
147 bfa_ioc_hbfail_cbfn_t hbfail_cbfn;
148 bfa_ioc_reset_cbfn_t reset_cbfn;
149};
150
151/**
152 * Heartbeat failure notification queue element.
153 */
154struct bfa_ioc_hbfail_notify {
155 struct list_head qe;
156 bfa_ioc_hbfail_cbfn_t cbfn;
157 void *cbarg;
158};
159
160/**
161 * Initialize a heartbeat failure notification structure
162 */
163#define bfa_ioc_hbfail_init(__notify, __cbfn, __cbarg) do { \
164 (__notify)->cbfn = (__cbfn); \
165 (__notify)->cbarg = (__cbarg); \
166} while (0)
167
168struct bfa_ioc {
169 bfa_fsm_t fsm;
170 struct bfa *bfa;
171 struct bfa_pcidev pcidev;
172 struct bfa_timer_mod *timer_mod;
173 struct timer_list ioc_timer;
174 struct timer_list sem_timer;
175 struct timer_list hb_timer;
176 u32 hb_count;
177 u32 retry_count;
178 struct list_head hb_notify_q;
179 void *dbg_fwsave;
180 int dbg_fwsave_len;
181 bool dbg_fwsave_once;
182 enum bfi_mclass ioc_mc;
183 struct bfa_ioc_regs ioc_regs;
184 struct bfa_ioc_drv_stats stats;
185 bool auto_recover;
186 bool fcmode;
187 bool ctdev;
188 bool cna;
189 bool pllinit;
190 bool stats_busy; /*!< outstanding stats */
191 u8 port_id;
192
193 struct bfa_dma attr_dma;
194 struct bfi_ioc_attr *attr;
195 struct bfa_ioc_cbfn *cbfn;
196 struct bfa_ioc_mbox_mod mbox_mod;
197 struct bfa_ioc_hwif *ioc_hwif;
198};
199
200struct bfa_ioc_hwif {
201 enum bfa_status (*ioc_pll_init) (void __iomem *rb, bool fcmode);
202 bool (*ioc_firmware_lock) (struct bfa_ioc *ioc);
203 void (*ioc_firmware_unlock) (struct bfa_ioc *ioc);
204 void (*ioc_reg_init) (struct bfa_ioc *ioc);
205 void (*ioc_map_port) (struct bfa_ioc *ioc);
206 void (*ioc_isr_mode_set) (struct bfa_ioc *ioc,
207 bool msix);
208 void (*ioc_notify_hbfail) (struct bfa_ioc *ioc);
209 void (*ioc_ownership_reset) (struct bfa_ioc *ioc);
210};
211
212#define bfa_ioc_pcifn(__ioc) ((__ioc)->pcidev.pci_func)
213#define bfa_ioc_devid(__ioc) ((__ioc)->pcidev.device_id)
214#define bfa_ioc_bar0(__ioc) ((__ioc)->pcidev.pci_bar_kva)
215#define bfa_ioc_portid(__ioc) ((__ioc)->port_id)
216#define bfa_ioc_fetch_stats(__ioc, __stats) \
217 (((__stats)->drv_stats) = (__ioc)->stats)
218#define bfa_ioc_clr_stats(__ioc) \
219 memset(&(__ioc)->stats, 0, sizeof((__ioc)->stats))
220#define bfa_ioc_maxfrsize(__ioc) ((__ioc)->attr->maxfrsize)
221#define bfa_ioc_rx_bbcredit(__ioc) ((__ioc)->attr->rx_bbcredit)
222#define bfa_ioc_speed_sup(__ioc) \
223 BFI_ADAPTER_GETP(SPEED, (__ioc)->attr->adapter_prop)
224#define bfa_ioc_get_nports(__ioc) \
225 BFI_ADAPTER_GETP(NPORTS, (__ioc)->attr->adapter_prop)
226
227#define bfa_ioc_stats(_ioc, _stats) ((_ioc)->stats._stats++)
228#define BFA_IOC_FWIMG_MINSZ (16 * 1024)
229#define BFA_IOC_FWIMG_TYPE(__ioc) \
230 (((__ioc)->ctdev) ? \
231 (((__ioc)->fcmode) ? BFI_IMAGE_CT_FC : BFI_IMAGE_CT_CNA) : \
232 BFI_IMAGE_CB_FC)
233#define BFA_IOC_FW_SMEM_SIZE(__ioc) \
234 (((__ioc)->ctdev) ? BFI_SMEM_CT_SIZE : BFI_SMEM_CB_SIZE)
235#define BFA_IOC_FLASH_CHUNK_NO(off) (off / BFI_FLASH_CHUNK_SZ_WORDS)
236#define BFA_IOC_FLASH_OFFSET_IN_CHUNK(off) (off % BFI_FLASH_CHUNK_SZ_WORDS)
237#define BFA_IOC_FLASH_CHUNK_ADDR(chunkno) (chunkno * BFI_FLASH_CHUNK_SZ_WORDS)
238
239/**
240 * IOC mailbox interface
241 */
242void bfa_ioc_mbox_queue(struct bfa_ioc *ioc, struct bfa_mbox_cmd *cmd);
243void bfa_ioc_mbox_register(struct bfa_ioc *ioc,
244 bfa_ioc_mbox_mcfunc_t *mcfuncs);
245void bfa_ioc_mbox_isr(struct bfa_ioc *ioc);
246void bfa_ioc_mbox_send(struct bfa_ioc *ioc, void *ioc_msg, int len);
247void bfa_ioc_msgget(struct bfa_ioc *ioc, void *mbmsg);
248void bfa_ioc_mbox_regisr(struct bfa_ioc *ioc, enum bfi_mclass mc,
249 bfa_ioc_mbox_mcfunc_t cbfn, void *cbarg);
250
251/**
252 * IOC interfaces
253 */
254
255#define bfa_ioc_pll_init_asic(__ioc) \
256 ((__ioc)->ioc_hwif->ioc_pll_init((__ioc)->pcidev.pci_bar_kva, \
257 (__ioc)->fcmode))
258
259enum bfa_status bfa_ioc_pll_init(struct bfa_ioc *ioc);
260enum bfa_status bfa_ioc_cb_pll_init(void __iomem *rb, bool fcmode);
261enum bfa_status bfa_ioc_ct_pll_init(void __iomem *rb, bool fcmode);
262
263#define bfa_ioc_isr_mode_set(__ioc, __msix) \
264 ((__ioc)->ioc_hwif->ioc_isr_mode_set(__ioc, __msix))
265#define bfa_ioc_ownership_reset(__ioc) \
266 ((__ioc)->ioc_hwif->ioc_ownership_reset(__ioc))
267
268void bfa_ioc_set_ct_hwif(struct bfa_ioc *ioc);
269
270void bfa_ioc_attach(struct bfa_ioc *ioc, void *bfa,
271 struct bfa_ioc_cbfn *cbfn);
272void bfa_ioc_auto_recover(bool auto_recover);
273void bfa_ioc_detach(struct bfa_ioc *ioc);
274void bfa_ioc_pci_init(struct bfa_ioc *ioc, struct bfa_pcidev *pcidev,
275 enum bfi_mclass mc);
276u32 bfa_ioc_meminfo(void);
277void bfa_ioc_mem_claim(struct bfa_ioc *ioc, u8 *dm_kva, u64 dm_pa);
278void bfa_ioc_enable(struct bfa_ioc *ioc);
279void bfa_ioc_disable(struct bfa_ioc *ioc);
280bool bfa_ioc_intx_claim(struct bfa_ioc *ioc);
281
282void bfa_ioc_boot(struct bfa_ioc *ioc, u32 boot_type,
283 u32 boot_param);
284void bfa_ioc_isr(struct bfa_ioc *ioc, struct bfi_mbmsg *msg);
285void bfa_ioc_error_isr(struct bfa_ioc *ioc);
286bool bfa_ioc_is_operational(struct bfa_ioc *ioc);
287bool bfa_ioc_is_initialized(struct bfa_ioc *ioc);
288bool bfa_ioc_is_disabled(struct bfa_ioc *ioc);
289bool bfa_ioc_fw_mismatch(struct bfa_ioc *ioc);
290bool bfa_ioc_adapter_is_disabled(struct bfa_ioc *ioc);
291void bfa_ioc_cfg_complete(struct bfa_ioc *ioc);
292enum bfa_ioc_type bfa_ioc_get_type(struct bfa_ioc *ioc);
293void bfa_ioc_get_adapter_serial_num(struct bfa_ioc *ioc, char *serial_num);
294void bfa_ioc_get_adapter_fw_ver(struct bfa_ioc *ioc, char *fw_ver);
295void bfa_ioc_get_adapter_optrom_ver(struct bfa_ioc *ioc, char *optrom_ver);
296void bfa_ioc_get_adapter_model(struct bfa_ioc *ioc, char *model);
297void bfa_ioc_get_adapter_manufacturer(struct bfa_ioc *ioc,
298 char *manufacturer);
299void bfa_ioc_get_pci_chip_rev(struct bfa_ioc *ioc, char *chip_rev);
300enum bfa_ioc_state bfa_ioc_get_state(struct bfa_ioc *ioc);
301
302void bfa_ioc_get_attr(struct bfa_ioc *ioc, struct bfa_ioc_attr *ioc_attr);
303void bfa_ioc_get_adapter_attr(struct bfa_ioc *ioc,
304 struct bfa_adapter_attr *ad_attr);
305u32 bfa_ioc_smem_pgnum(struct bfa_ioc *ioc, u32 fmaddr);
306u32 bfa_ioc_smem_pgoff(struct bfa_ioc *ioc, u32 fmaddr);
307void bfa_ioc_set_fcmode(struct bfa_ioc *ioc);
308bool bfa_ioc_get_fcmode(struct bfa_ioc *ioc);
309void bfa_ioc_hbfail_register(struct bfa_ioc *ioc,
310 struct bfa_ioc_hbfail_notify *notify);
311bool bfa_ioc_sem_get(void __iomem *sem_reg);
312void bfa_ioc_sem_release(void __iomem *sem_reg);
313void bfa_ioc_hw_sem_release(struct bfa_ioc *ioc);
314void bfa_ioc_fwver_get(struct bfa_ioc *ioc,
315 struct bfi_ioc_image_hdr *fwhdr);
316bool bfa_ioc_fwver_cmp(struct bfa_ioc *ioc,
317 struct bfi_ioc_image_hdr *fwhdr);
318
319/*
320 * Timeout APIs
321 */
322void bfa_ioc_timeout(void *ioc);
323void bfa_ioc_hb_check(void *ioc);
324void bfa_ioc_sem_timeout(void *ioc);
325
326/*
327 * bfa mfg wwn API functions
328 */
329u64 bfa_ioc_get_pwwn(struct bfa_ioc *ioc);
330u64 bfa_ioc_get_nwwn(struct bfa_ioc *ioc);
331mac_t bfa_ioc_get_mac(struct bfa_ioc *ioc);
332u64 bfa_ioc_get_mfg_pwwn(struct bfa_ioc *ioc);
333u64 bfa_ioc_get_mfg_nwwn(struct bfa_ioc *ioc);
334mac_t bfa_ioc_get_mfg_mac(struct bfa_ioc *ioc);
335u64 bfa_ioc_get_adid(struct bfa_ioc *ioc);
336
337/*
338 * F/W Image Size & Chunk
339 */
340u32 *bfa_cb_image_get_chunk(int type, u32 off);
341u32 bfa_cb_image_get_size(int type);
342
343#endif /* __BFA_IOC_H__ */
diff --git a/drivers/net/bna/bfa_ioc_ct.c b/drivers/net/bna/bfa_ioc_ct.c
new file mode 100644
index 000000000000..870046e32c8d
--- /dev/null
+++ b/drivers/net/bna/bfa_ioc_ct.c
@@ -0,0 +1,391 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18
19#include "bfa_ioc.h"
20#include "cna.h"
21#include "bfi.h"
22#include "bfi_ctreg.h"
23#include "bfa_defs.h"
24
25/*
26 * forward declarations
27 */
28static bool bfa_ioc_ct_firmware_lock(struct bfa_ioc *ioc);
29static void bfa_ioc_ct_firmware_unlock(struct bfa_ioc *ioc);
30static void bfa_ioc_ct_reg_init(struct bfa_ioc *ioc);
31static void bfa_ioc_ct_map_port(struct bfa_ioc *ioc);
32static void bfa_ioc_ct_isr_mode_set(struct bfa_ioc *ioc, bool msix);
33static void bfa_ioc_ct_notify_hbfail(struct bfa_ioc *ioc);
34static void bfa_ioc_ct_ownership_reset(struct bfa_ioc *ioc);
35
36struct bfa_ioc_hwif hwif_ct;
37
38/**
39 * Called from bfa_ioc_attach() to map asic specific calls.
40 */
41void
42bfa_ioc_set_ct_hwif(struct bfa_ioc *ioc)
43{
44 hwif_ct.ioc_pll_init = bfa_ioc_ct_pll_init;
45 hwif_ct.ioc_firmware_lock = bfa_ioc_ct_firmware_lock;
46 hwif_ct.ioc_firmware_unlock = bfa_ioc_ct_firmware_unlock;
47 hwif_ct.ioc_reg_init = bfa_ioc_ct_reg_init;
48 hwif_ct.ioc_map_port = bfa_ioc_ct_map_port;
49 hwif_ct.ioc_isr_mode_set = bfa_ioc_ct_isr_mode_set;
50 hwif_ct.ioc_notify_hbfail = bfa_ioc_ct_notify_hbfail;
51 hwif_ct.ioc_ownership_reset = bfa_ioc_ct_ownership_reset;
52
53 ioc->ioc_hwif = &hwif_ct;
54}
55
56/**
57 * Return true if firmware of current driver matches the running firmware.
58 */
59static bool
60bfa_ioc_ct_firmware_lock(struct bfa_ioc *ioc)
61{
62 enum bfi_ioc_state ioc_fwstate;
63 u32 usecnt;
64 struct bfi_ioc_image_hdr fwhdr;
65
66 /**
67 * Firmware match check is relevant only for CNA.
68 */
69 if (!ioc->cna)
70 return true;
71
72 /**
73 * If bios boot (flash based) -- do not increment usage count
74 */
75 if (bfa_cb_image_get_size(BFA_IOC_FWIMG_TYPE(ioc)) <
76 BFA_IOC_FWIMG_MINSZ)
77 return true;
78
79 bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
80 usecnt = readl(ioc->ioc_regs.ioc_usage_reg);
81
82 /**
83 * If usage count is 0, always return TRUE.
84 */
85 if (usecnt == 0) {
86 writel(1, ioc->ioc_regs.ioc_usage_reg);
87 bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
88 return true;
89 }
90
91 ioc_fwstate = readl(ioc->ioc_regs.ioc_fwstate);
92
93 /**
94 * Use count cannot be non-zero and chip in uninitialized state.
95 */
96 BUG_ON(!(ioc_fwstate != BFI_IOC_UNINIT));
97
98 /**
99 * Check if another driver with a different firmware is active
100 */
101 bfa_ioc_fwver_get(ioc, &fwhdr);
102 if (!bfa_ioc_fwver_cmp(ioc, &fwhdr)) {
103 bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
104 return false;
105 }
106
107 /**
108 * Same firmware version. Increment the reference count.
109 */
110 usecnt++;
111 writel(usecnt, ioc->ioc_regs.ioc_usage_reg);
112 bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
113 return true;
114}
115
116static void
117bfa_ioc_ct_firmware_unlock(struct bfa_ioc *ioc)
118{
119 u32 usecnt;
120
121 /**
122 * Firmware lock is relevant only for CNA.
123 */
124 if (!ioc->cna)
125 return;
126
127 /**
128 * If bios boot (flash based) -- do not decrement usage count
129 */
130 if (bfa_cb_image_get_size(BFA_IOC_FWIMG_TYPE(ioc)) <
131 BFA_IOC_FWIMG_MINSZ)
132 return;
133
134 /**
135 * decrement usage count
136 */
137 bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
138 usecnt = readl(ioc->ioc_regs.ioc_usage_reg);
139 BUG_ON(!(usecnt > 0));
140
141 usecnt--;
142 writel(usecnt, ioc->ioc_regs.ioc_usage_reg);
143
144 bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
145}
146
147/**
148 * Notify other functions on HB failure.
149 */
150static void
151bfa_ioc_ct_notify_hbfail(struct bfa_ioc *ioc)
152{
153 if (ioc->cna) {
154 writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt);
155 /* Wait for halt to take effect */
156 readl(ioc->ioc_regs.ll_halt);
157 } else {
158 writel(__PSS_ERR_STATUS_SET, ioc->ioc_regs.err_set);
159 readl(ioc->ioc_regs.err_set);
160 }
161}
162
163/**
164 * Host to LPU mailbox message addresses
165 */
166static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = {
167 { HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0 },
168 { HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1 },
169 { HOSTFN2_LPU_MBOX0_0, LPU_HOSTFN2_MBOX0_0, HOST_PAGE_NUM_FN2 },
170 { HOSTFN3_LPU_MBOX0_8, LPU_HOSTFN3_MBOX0_8, HOST_PAGE_NUM_FN3 }
171};
172
173/**
174 * Host <-> LPU mailbox command/status registers - port 0
175 */
176static struct { u32 hfn, lpu; } iocreg_mbcmd_p0[] = {
177 { HOSTFN0_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN0_MBOX0_CMD_STAT },
178 { HOSTFN1_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN1_MBOX0_CMD_STAT },
179 { HOSTFN2_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN2_MBOX0_CMD_STAT },
180 { HOSTFN3_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN3_MBOX0_CMD_STAT }
181};
182
183/**
184 * Host <-> LPU mailbox command/status registers - port 1
185 */
186static struct { u32 hfn, lpu; } iocreg_mbcmd_p1[] = {
187 { HOSTFN0_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN0_MBOX0_CMD_STAT },
188 { HOSTFN1_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN1_MBOX0_CMD_STAT },
189 { HOSTFN2_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN2_MBOX0_CMD_STAT },
190 { HOSTFN3_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN3_MBOX0_CMD_STAT }
191};
192
193static void
194bfa_ioc_ct_reg_init(struct bfa_ioc *ioc)
195{
196 void __iomem *rb;
197 int pcifn = bfa_ioc_pcifn(ioc);
198
199 rb = bfa_ioc_bar0(ioc);
200
201 ioc->ioc_regs.hfn_mbox = rb + iocreg_fnreg[pcifn].hfn_mbox;
202 ioc->ioc_regs.lpu_mbox = rb + iocreg_fnreg[pcifn].lpu_mbox;
203 ioc->ioc_regs.host_page_num_fn = rb + iocreg_fnreg[pcifn].hfn_pgn;
204
205 if (ioc->port_id == 0) {
206 ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG;
207 ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG;
208 ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd_p0[pcifn].hfn;
209 ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd_p0[pcifn].lpu;
210 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0;
211 } else {
212 ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG);
213 ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG);
214 ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd_p1[pcifn].hfn;
215 ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd_p1[pcifn].lpu;
216 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1;
217 }
218
219 /*
220 * PSS control registers
221 */
222 ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG);
223 ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG);
224 ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_425_CTL_REG);
225 ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_312_CTL_REG);
226
227 /*
228 * IOC semaphore registers and serialization
229 */
230 ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG);
231 ioc->ioc_regs.ioc_usage_sem_reg = (rb + HOST_SEM1_REG);
232 ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG);
233 ioc->ioc_regs.ioc_usage_reg = (rb + BFA_FW_USE_COUNT);
234
235 /**
236 * sram memory access
237 */
238 ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START);
239 ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CT;
240
241 /*
242 * err set reg : for notification of hb failure in fcmode
243 */
244 ioc->ioc_regs.err_set = (rb + ERR_SET_REG);
245}
246
247/**
248 * Initialize IOC to port mapping.
249 */
250
251#define FNC_PERS_FN_SHIFT(__fn) ((__fn) * 8)
252static void
253bfa_ioc_ct_map_port(struct bfa_ioc *ioc)
254{
255 void __iomem *rb = ioc->pcidev.pci_bar_kva;
256 u32 r32;
257
258 /**
259 * For catapult, base port id on personality register and IOC type
260 */
261 r32 = readl(rb + FNC_PERS_REG);
262 r32 >>= FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc));
263 ioc->port_id = (r32 & __F0_PORT_MAP_MK) >> __F0_PORT_MAP_SH;
264
265}
266
267/**
268 * Set interrupt mode for a function: INTX or MSIX
269 */
270static void
271bfa_ioc_ct_isr_mode_set(struct bfa_ioc *ioc, bool msix)
272{
273 void __iomem *rb = ioc->pcidev.pci_bar_kva;
274 u32 r32, mode;
275
276 r32 = readl(rb + FNC_PERS_REG);
277
278 mode = (r32 >> FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc))) &
279 __F0_INTX_STATUS;
280
281 /**
282 * If already in desired mode, do not change anything
283 */
284 if (!msix && mode)
285 return;
286
287 if (msix)
288 mode = __F0_INTX_STATUS_MSIX;
289 else
290 mode = __F0_INTX_STATUS_INTA;
291
292 r32 &= ~(__F0_INTX_STATUS << FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc)));
293 r32 |= (mode << FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc)));
294
295 writel(r32, rb + FNC_PERS_REG);
296}
297
298/**
299 * Cleanup hw semaphore and usecnt registers
300 */
301static void
302bfa_ioc_ct_ownership_reset(struct bfa_ioc *ioc)
303{
304 if (ioc->cna) {
305 bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
306 writel(0, ioc->ioc_regs.ioc_usage_reg);
307 bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
308 }
309
310 /*
311 * Read the hw sem reg to make sure that it is locked
312 * before we clear it. If it is not locked, writing 1
313 * will lock it instead of clearing it.
314 */
315 readl(ioc->ioc_regs.ioc_sem_reg);
316 bfa_ioc_hw_sem_release(ioc);
317}
318
319enum bfa_status
320bfa_ioc_ct_pll_init(void __iomem *rb, bool fcmode)
321{
322 u32 pll_sclk, pll_fclk, r32;
323
324 pll_sclk = __APP_PLL_312_LRESETN | __APP_PLL_312_ENARST |
325 __APP_PLL_312_RSEL200500 | __APP_PLL_312_P0_1(3U) |
326 __APP_PLL_312_JITLMT0_1(3U) |
327 __APP_PLL_312_CNTLMT0_1(1U);
328 pll_fclk = __APP_PLL_425_LRESETN | __APP_PLL_425_ENARST |
329 __APP_PLL_425_RSEL200500 | __APP_PLL_425_P0_1(3U) |
330 __APP_PLL_425_JITLMT0_1(3U) |
331 __APP_PLL_425_CNTLMT0_1(1U);
332 if (fcmode) {
333 writel(0, (rb + OP_MODE));
334 writel(__APP_EMS_CMLCKSEL |
335 __APP_EMS_REFCKBUFEN2 |
336 __APP_EMS_CHANNEL_SEL,
337 (rb + ETH_MAC_SER_REG));
338 } else {
339 writel(__GLOBAL_FCOE_MODE, (rb + OP_MODE));
340 writel(__APP_EMS_REFCKBUFEN1,
341 (rb + ETH_MAC_SER_REG));
342 }
343 writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG));
344 writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG));
345 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
346 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
347 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
348 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
349 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
350 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
351 writel(pll_sclk |
352 __APP_PLL_312_LOGIC_SOFT_RESET,
353 rb + APP_PLL_312_CTL_REG);
354 writel(pll_fclk |
355 __APP_PLL_425_LOGIC_SOFT_RESET,
356 rb + APP_PLL_425_CTL_REG);
357 writel(pll_sclk |
358 __APP_PLL_312_LOGIC_SOFT_RESET | __APP_PLL_312_ENABLE,
359 rb + APP_PLL_312_CTL_REG);
360 writel(pll_fclk |
361 __APP_PLL_425_LOGIC_SOFT_RESET | __APP_PLL_425_ENABLE,
362 rb + APP_PLL_425_CTL_REG);
363 readl(rb + HOSTFN0_INT_MSK);
364 udelay(2000);
365 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
366 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
367 writel(pll_sclk |
368 __APP_PLL_312_ENABLE,
369 rb + APP_PLL_312_CTL_REG);
370 writel(pll_fclk |
371 __APP_PLL_425_ENABLE,
372 rb + APP_PLL_425_CTL_REG);
373 if (!fcmode) {
374 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P0));
375 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P1));
376 }
377 r32 = readl((rb + PSS_CTL_REG));
378 r32 &= ~__PSS_LMEM_RESET;
379 writel(r32, (rb + PSS_CTL_REG));
380 udelay(1000);
381 if (!fcmode) {
382 writel(0, (rb + PMM_1T_RESET_REG_P0));
383 writel(0, (rb + PMM_1T_RESET_REG_P1));
384 }
385
386 writel(__EDRAM_BISTR_START, (rb + MBIST_CTL_REG));
387 udelay(1000);
388 r32 = readl((rb + MBIST_STAT_REG));
389 writel(0, (rb + MBIST_CTL_REG));
390 return BFA_STATUS_OK;
391}
diff --git a/drivers/net/bna/bfa_sm.h b/drivers/net/bna/bfa_sm.h
new file mode 100644
index 000000000000..1d3d975d6f68
--- /dev/null
+++ b/drivers/net/bna/bfa_sm.h
@@ -0,0 +1,88 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18
19/**
20 * @file bfasm.h State machine defines
21 */
22
23#ifndef __BFA_SM_H__
24#define __BFA_SM_H__
25
26#include "cna.h"
27
28typedef void (*bfa_sm_t)(void *sm, int event);
29
30/**
31 * oc - object class eg. bfa_ioc
32 * st - state, eg. reset
33 * otype - object type, eg. struct bfa_ioc
34 * etype - object type, eg. enum ioc_event
35 */
36#define bfa_sm_state_decl(oc, st, otype, etype) \
37 static void oc ## _sm_ ## st(otype * fsm, etype event)
38
39#define bfa_sm_set_state(_sm, _state) ((_sm)->sm = (bfa_sm_t)(_state))
40#define bfa_sm_send_event(_sm, _event) ((_sm)->sm((_sm), (_event)))
41#define bfa_sm_get_state(_sm) ((_sm)->sm)
42#define bfa_sm_cmp_state(_sm, _state) ((_sm)->sm == (bfa_sm_t)(_state))
43
44/**
45 * For converting from state machine function to state encoding.
46 */
47struct bfa_sm_table {
48 bfa_sm_t sm; /*!< state machine function */
49 int state; /*!< state machine encoding */
50 char *name; /*!< state name for display */
51};
52#define BFA_SM(_sm) ((bfa_sm_t)(_sm))
53
54/**
55 * State machine with entry actions.
56 */
57typedef void (*bfa_fsm_t)(void *fsm, int event);
58
59/**
60 * oc - object class eg. bfa_ioc
61 * st - state, eg. reset
62 * otype - object type, eg. struct bfa_ioc
63 * etype - object type, eg. enum ioc_event
64 */
65#define bfa_fsm_state_decl(oc, st, otype, etype) \
66 static void oc ## _sm_ ## st(otype * fsm, etype event); \
67 static void oc ## _sm_ ## st ## _entry(otype * fsm)
68
69#define bfa_fsm_set_state(_fsm, _state) do { \
70 (_fsm)->fsm = (bfa_fsm_t)(_state); \
71 _state ## _entry(_fsm); \
72} while (0)
73
74#define bfa_fsm_send_event(_fsm, _event) ((_fsm)->fsm((_fsm), (_event)))
75#define bfa_fsm_get_state(_fsm) ((_fsm)->fsm)
76#define bfa_fsm_cmp_state(_fsm, _state) \
77 ((_fsm)->fsm == (bfa_fsm_t)(_state))
78
79static inline int
80bfa_sm_to_state(struct bfa_sm_table *smt, bfa_sm_t sm)
81{
82 int i = 0;
83
84 while (smt[i].sm && smt[i].sm != sm)
85 i++;
86 return smt[i].state;
87}
88#endif
diff --git a/drivers/net/bna/bfa_wc.h b/drivers/net/bna/bfa_wc.h
new file mode 100644
index 000000000000..d0e4caee67b0
--- /dev/null
+++ b/drivers/net/bna/bfa_wc.h
@@ -0,0 +1,69 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18
19/**
20 * @file bfa_wc.h Generic wait counter.
21 */
22
23#ifndef __BFA_WC_H__
24#define __BFA_WC_H__
25
26typedef void (*bfa_wc_resume_t) (void *cbarg);
27
28struct bfa_wc {
29 bfa_wc_resume_t wc_resume;
30 void *wc_cbarg;
31 int wc_count;
32};
33
34static inline void
35bfa_wc_up(struct bfa_wc *wc)
36{
37 wc->wc_count++;
38}
39
40static inline void
41bfa_wc_down(struct bfa_wc *wc)
42{
43 wc->wc_count--;
44 if (wc->wc_count == 0)
45 wc->wc_resume(wc->wc_cbarg);
46}
47
48/**
49 * Initialize a waiting counter.
50 */
51static inline void
52bfa_wc_init(struct bfa_wc *wc, bfa_wc_resume_t wc_resume, void *wc_cbarg)
53{
54 wc->wc_resume = wc_resume;
55 wc->wc_cbarg = wc_cbarg;
56 wc->wc_count = 0;
57 bfa_wc_up(wc);
58}
59
60/**
61 * Wait for counter to reach zero
62 */
63static inline void
64bfa_wc_wait(struct bfa_wc *wc)
65{
66 bfa_wc_down(wc);
67}
68
69#endif
diff --git a/drivers/net/bna/bfi.h b/drivers/net/bna/bfi.h
new file mode 100644
index 000000000000..a97396811050
--- /dev/null
+++ b/drivers/net/bna/bfi.h
@@ -0,0 +1,392 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18
19#ifndef __BFI_H__
20#define __BFI_H__
21
22#include "bfa_defs.h"
23
24#pragma pack(1)
25
26/**
27 * BFI FW image type
28 */
29#define BFI_FLASH_CHUNK_SZ 256 /*!< Flash chunk size */
30#define BFI_FLASH_CHUNK_SZ_WORDS (BFI_FLASH_CHUNK_SZ/sizeof(u32))
31enum {
32 BFI_IMAGE_CB_FC,
33 BFI_IMAGE_CT_FC,
34 BFI_IMAGE_CT_CNA,
35 BFI_IMAGE_MAX,
36};
37
38/**
39 * Msg header common to all msgs
40 */
41struct bfi_mhdr {
42 u8 msg_class; /*!< @ref enum bfi_mclass */
43 u8 msg_id; /*!< msg opcode with in the class */
44 union {
45 struct {
46 u8 rsvd;
47 u8 lpu_id; /*!< msg destination */
48 } h2i;
49 u16 i2htok; /*!< token in msgs to host */
50 } mtag;
51};
52
53#define bfi_h2i_set(_mh, _mc, _op, _lpuid) do { \
54 (_mh).msg_class = (_mc); \
55 (_mh).msg_id = (_op); \
56 (_mh).mtag.h2i.lpu_id = (_lpuid); \
57} while (0)
58
59#define bfi_i2h_set(_mh, _mc, _op, _i2htok) do { \
60 (_mh).msg_class = (_mc); \
61 (_mh).msg_id = (_op); \
62 (_mh).mtag.i2htok = (_i2htok); \
63} while (0)
64
65/*
66 * Message opcodes: 0-127 to firmware, 128-255 to host
67 */
68#define BFI_I2H_OPCODE_BASE 128
69#define BFA_I2HM(_x) ((_x) + BFI_I2H_OPCODE_BASE)
70
71/**
72 ****************************************************************************
73 *
74 * Scatter Gather Element and Page definition
75 *
76 ****************************************************************************
77 */
78
79#define BFI_SGE_INLINE 1
80#define BFI_SGE_INLINE_MAX (BFI_SGE_INLINE + 1)
81
82/**
83 * SG Flags
84 */
85enum {
86 BFI_SGE_DATA = 0, /*!< data address, not last */
87 BFI_SGE_DATA_CPL = 1, /*!< data addr, last in current page */
88 BFI_SGE_DATA_LAST = 3, /*!< data address, last */
89 BFI_SGE_LINK = 2, /*!< link address */
90 BFI_SGE_PGDLEN = 2, /*!< cumulative data length for page */
91};
92
93/**
94 * DMA addresses
95 */
96union bfi_addr_u {
97 struct {
98 u32 addr_lo;
99 u32 addr_hi;
100 } a32;
101};
102
103/**
104 * Scatter Gather Element
105 */
106struct bfi_sge {
107#ifdef __BIGENDIAN
108 u32 flags:2,
109 rsvd:2,
110 sg_len:28;
111#else
112 u32 sg_len:28,
113 rsvd:2,
114 flags:2;
115#endif
116 union bfi_addr_u sga;
117};
118
119/**
120 * Scatter Gather Page
121 */
122#define BFI_SGPG_DATA_SGES 7
123#define BFI_SGPG_SGES_MAX (BFI_SGPG_DATA_SGES + 1)
124#define BFI_SGPG_RSVD_WD_LEN 8
125struct bfi_sgpg {
126 struct bfi_sge sges[BFI_SGPG_SGES_MAX];
127 u32 rsvd[BFI_SGPG_RSVD_WD_LEN];
128};
129
130/*
131 * Large Message structure - 128 Bytes size Msgs
132 */
133#define BFI_LMSG_SZ 128
134#define BFI_LMSG_PL_WSZ \
135 ((BFI_LMSG_SZ - sizeof(struct bfi_mhdr)) / 4)
136
137struct bfi_msg {
138 struct bfi_mhdr mhdr;
139 u32 pl[BFI_LMSG_PL_WSZ];
140};
141
142/**
143 * Mailbox message structure
144 */
145#define BFI_MBMSG_SZ 7
146struct bfi_mbmsg {
147 struct bfi_mhdr mh;
148 u32 pl[BFI_MBMSG_SZ];
149};
150
151/**
152 * Message Classes
153 */
154enum bfi_mclass {
155 BFI_MC_IOC = 1, /*!< IO Controller (IOC) */
156 BFI_MC_DIAG = 2, /*!< Diagnostic Msgs */
157 BFI_MC_FLASH = 3, /*!< Flash message class */
158 BFI_MC_CEE = 4, /*!< CEE */
159 BFI_MC_FCPORT = 5, /*!< FC port */
160 BFI_MC_IOCFC = 6, /*!< FC - IO Controller (IOC) */
161 BFI_MC_LL = 7, /*!< Link Layer */
162 BFI_MC_UF = 8, /*!< Unsolicited frame receive */
163 BFI_MC_FCXP = 9, /*!< FC Transport */
164 BFI_MC_LPS = 10, /*!< lport fc login services */
165 BFI_MC_RPORT = 11, /*!< Remote port */
166 BFI_MC_ITNIM = 12, /*!< I-T nexus (Initiator mode) */
167 BFI_MC_IOIM_READ = 13, /*!< read IO (Initiator mode) */
168 BFI_MC_IOIM_WRITE = 14, /*!< write IO (Initiator mode) */
169 BFI_MC_IOIM_IO = 15, /*!< IO (Initiator mode) */
170 BFI_MC_IOIM = 16, /*!< IO (Initiator mode) */
171 BFI_MC_IOIM_IOCOM = 17, /*!< good IO completion */
172 BFI_MC_TSKIM = 18, /*!< Initiator Task management */
173 BFI_MC_SBOOT = 19, /*!< SAN boot services */
174 BFI_MC_IPFC = 20, /*!< IP over FC Msgs */
175 BFI_MC_PORT = 21, /*!< Physical port */
176 BFI_MC_SFP = 22, /*!< SFP module */
177 BFI_MC_MSGQ = 23, /*!< MSGQ */
178 BFI_MC_ENET = 24, /*!< ENET commands/responses */
179 BFI_MC_MAX = 32
180};
181
182#define BFI_IOC_MAX_CQS 4
183#define BFI_IOC_MAX_CQS_ASIC 8
184#define BFI_IOC_MSGLEN_MAX 32 /* 32 bytes */
185
186#define BFI_BOOT_TYPE_OFF 8
187#define BFI_BOOT_PARAM_OFF 12
188
189#define BFI_BOOT_TYPE_NORMAL 0 /* param is device id */
190#define BFI_BOOT_TYPE_FLASH 1
191#define BFI_BOOT_TYPE_MEMTEST 2
192
193#define BFI_BOOT_MEMTEST_RES_ADDR 0x900
194#define BFI_BOOT_MEMTEST_RES_SIG 0xA0A1A2A3
195
196/**
197 *----------------------------------------------------------------------
198 * IOC
199 *----------------------------------------------------------------------
200 */
201
202enum bfi_ioc_h2i_msgs {
203 BFI_IOC_H2I_ENABLE_REQ = 1,
204 BFI_IOC_H2I_DISABLE_REQ = 2,
205 BFI_IOC_H2I_GETATTR_REQ = 3,
206 BFI_IOC_H2I_DBG_SYNC = 4,
207 BFI_IOC_H2I_DBG_DUMP = 5,
208};
209
210enum bfi_ioc_i2h_msgs {
211 BFI_IOC_I2H_ENABLE_REPLY = BFA_I2HM(1),
212 BFI_IOC_I2H_DISABLE_REPLY = BFA_I2HM(2),
213 BFI_IOC_I2H_GETATTR_REPLY = BFA_I2HM(3),
214 BFI_IOC_I2H_READY_EVENT = BFA_I2HM(4),
215 BFI_IOC_I2H_HBEAT = BFA_I2HM(5),
216};
217
218/**
219 * BFI_IOC_H2I_GETATTR_REQ message
220 */
221struct bfi_ioc_getattr_req {
222 struct bfi_mhdr mh;
223 union bfi_addr_u attr_addr;
224};
225
226struct bfi_ioc_attr {
227 u64 mfg_pwwn; /*!< Mfg port wwn */
228 u64 mfg_nwwn; /*!< Mfg node wwn */
229 mac_t mfg_mac; /*!< Mfg mac */
230 u16 rsvd_a;
231 u64 pwwn;
232 u64 nwwn;
233 mac_t mac; /*!< PBC or Mfg mac */
234 u16 rsvd_b;
235 mac_t fcoe_mac;
236 u16 rsvd_c;
237 char brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)];
238 u8 pcie_gen;
239 u8 pcie_lanes_orig;
240 u8 pcie_lanes;
241 u8 rx_bbcredit; /*!< receive buffer credits */
242 u32 adapter_prop; /*!< adapter properties */
243 u16 maxfrsize; /*!< max receive frame size */
244 char asic_rev;
245 u8 rsvd_d;
246 char fw_version[BFA_VERSION_LEN];
247 char optrom_version[BFA_VERSION_LEN];
248 struct bfa_mfg_vpd vpd;
249 u32 card_type; /*!< card type */
250};
251
252/**
253 * BFI_IOC_I2H_GETATTR_REPLY message
254 */
255struct bfi_ioc_getattr_reply {
256 struct bfi_mhdr mh; /*!< Common msg header */
257 u8 status; /*!< cfg reply status */
258 u8 rsvd[3];
259};
260
261/**
262 * Firmware memory page offsets
263 */
264#define BFI_IOC_SMEM_PG0_CB (0x40)
265#define BFI_IOC_SMEM_PG0_CT (0x180)
266
267/**
268 * Firmware statistic offset
269 */
270#define BFI_IOC_FWSTATS_OFF (0x6B40)
271#define BFI_IOC_FWSTATS_SZ (4096)
272
273/**
274 * Firmware trace offset
275 */
276#define BFI_IOC_TRC_OFF (0x4b00)
277#define BFI_IOC_TRC_ENTS 256
278
279#define BFI_IOC_FW_SIGNATURE (0xbfadbfad)
280#define BFI_IOC_MD5SUM_SZ 4
281struct bfi_ioc_image_hdr {
282 u32 signature; /*!< constant signature */
283 u32 rsvd_a;
284 u32 exec; /*!< exec vector */
285 u32 param; /*!< parameters */
286 u32 rsvd_b[4];
287 u32 md5sum[BFI_IOC_MD5SUM_SZ];
288};
289
290/**
291 * BFI_IOC_I2H_READY_EVENT message
292 */
293struct bfi_ioc_rdy_event {
294 struct bfi_mhdr mh; /*!< common msg header */
295 u8 init_status; /*!< init event status */
296 u8 rsvd[3];
297};
298
299struct bfi_ioc_hbeat {
300 struct bfi_mhdr mh; /*!< common msg header */
301 u32 hb_count; /*!< current heart beat count */
302};
303
304/**
305 * IOC hardware/firmware state
306 */
307enum bfi_ioc_state {
308 BFI_IOC_UNINIT = 0, /*!< not initialized */
309 BFI_IOC_INITING = 1, /*!< h/w is being initialized */
310 BFI_IOC_HWINIT = 2, /*!< h/w is initialized */
311 BFI_IOC_CFG = 3, /*!< IOC configuration in progress */
312 BFI_IOC_OP = 4, /*!< IOC is operational */
313 BFI_IOC_DISABLING = 5, /*!< IOC is being disabled */
314 BFI_IOC_DISABLED = 6, /*!< IOC is disabled */
315 BFI_IOC_CFG_DISABLED = 7, /*!< IOC is being disabled;transient */
316 BFI_IOC_FAIL = 8, /*!< IOC heart-beat failure */
317 BFI_IOC_MEMTEST = 9, /*!< IOC is doing memtest */
318};
319
320#define BFI_IOC_ENDIAN_SIG 0x12345678
321
322enum {
323 BFI_ADAPTER_TYPE_FC = 0x01, /*!< FC adapters */
324 BFI_ADAPTER_TYPE_MK = 0x0f0000, /*!< adapter type mask */
325 BFI_ADAPTER_TYPE_SH = 16, /*!< adapter type shift */
326 BFI_ADAPTER_NPORTS_MK = 0xff00, /*!< number of ports mask */
327 BFI_ADAPTER_NPORTS_SH = 8, /*!< number of ports shift */
328 BFI_ADAPTER_SPEED_MK = 0xff, /*!< adapter speed mask */
329 BFI_ADAPTER_SPEED_SH = 0, /*!< adapter speed shift */
330 BFI_ADAPTER_PROTO = 0x100000, /*!< prototype adapaters */
331 BFI_ADAPTER_TTV = 0x200000, /*!< TTV debug capable */
332 BFI_ADAPTER_UNSUPP = 0x400000, /*!< unknown adapter type */
333};
334
335#define BFI_ADAPTER_GETP(__prop, __adap_prop) \
336 (((__adap_prop) & BFI_ADAPTER_ ## __prop ## _MK) >> \
337 BFI_ADAPTER_ ## __prop ## _SH)
338#define BFI_ADAPTER_SETP(__prop, __val) \
339 ((__val) << BFI_ADAPTER_ ## __prop ## _SH)
340#define BFI_ADAPTER_IS_PROTO(__adap_type) \
341 ((__adap_type) & BFI_ADAPTER_PROTO)
342#define BFI_ADAPTER_IS_TTV(__adap_type) \
343 ((__adap_type) & BFI_ADAPTER_TTV)
344#define BFI_ADAPTER_IS_UNSUPP(__adap_type) \
345 ((__adap_type) & BFI_ADAPTER_UNSUPP)
346#define BFI_ADAPTER_IS_SPECIAL(__adap_type) \
347 ((__adap_type) & (BFI_ADAPTER_TTV | BFI_ADAPTER_PROTO | \
348 BFI_ADAPTER_UNSUPP))
349
350/**
351 * BFI_IOC_H2I_ENABLE_REQ & BFI_IOC_H2I_DISABLE_REQ messages
352 */
353struct bfi_ioc_ctrl_req {
354 struct bfi_mhdr mh;
355 u8 ioc_class;
356 u8 rsvd[3];
357 u32 tv_sec;
358};
359
360/**
361 * BFI_IOC_I2H_ENABLE_REPLY & BFI_IOC_I2H_DISABLE_REPLY messages
362 */
363struct bfi_ioc_ctrl_reply {
364 struct bfi_mhdr mh; /*!< Common msg header */
365 u8 status; /*!< enable/disable status */
366 u8 rsvd[3];
367};
368
369#define BFI_IOC_MSGSZ 8
370/**
371 * H2I Messages
372 */
373union bfi_ioc_h2i_msg_u {
374 struct bfi_mhdr mh;
375 struct bfi_ioc_ctrl_req enable_req;
376 struct bfi_ioc_ctrl_req disable_req;
377 struct bfi_ioc_getattr_req getattr_req;
378 u32 mboxmsg[BFI_IOC_MSGSZ];
379};
380
381/**
382 * I2H Messages
383 */
384union bfi_ioc_i2h_msg_u {
385 struct bfi_mhdr mh;
386 struct bfi_ioc_rdy_event rdy_event;
387 u32 mboxmsg[BFI_IOC_MSGSZ];
388};
389
390#pragma pack()
391
392#endif /* __BFI_H__ */
diff --git a/drivers/net/bna/bfi_cna.h b/drivers/net/bna/bfi_cna.h
new file mode 100644
index 000000000000..4eecabea397b
--- /dev/null
+++ b/drivers/net/bna/bfi_cna.h
@@ -0,0 +1,199 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18#ifndef __BFI_CNA_H__
19#define __BFI_CNA_H__
20
21#include "bfi.h"
22#include "bfa_defs_cna.h"
23
24#pragma pack(1)
25
26enum bfi_port_h2i {
27 BFI_PORT_H2I_ENABLE_REQ = (1),
28 BFI_PORT_H2I_DISABLE_REQ = (2),
29 BFI_PORT_H2I_GET_STATS_REQ = (3),
30 BFI_PORT_H2I_CLEAR_STATS_REQ = (4),
31};
32
33enum bfi_port_i2h {
34 BFI_PORT_I2H_ENABLE_RSP = BFA_I2HM(1),
35 BFI_PORT_I2H_DISABLE_RSP = BFA_I2HM(2),
36 BFI_PORT_I2H_GET_STATS_RSP = BFA_I2HM(3),
37 BFI_PORT_I2H_CLEAR_STATS_RSP = BFA_I2HM(4),
38};
39
40/**
41 * Generic REQ type
42 */
43struct bfi_port_generic_req {
44 struct bfi_mhdr mh; /*!< msg header */
45 u32 msgtag; /*!< msgtag for reply */
46 u32 rsvd;
47};
48
49/**
50 * Generic RSP type
51 */
52struct bfi_port_generic_rsp {
53 struct bfi_mhdr mh; /*!< common msg header */
54 u8 status; /*!< port enable status */
55 u8 rsvd[3];
56 u32 msgtag; /*!< msgtag for reply */
57};
58
59/**
60 * @todo
61 * BFI_PORT_H2I_ENABLE_REQ
62 */
63
64/**
65 * @todo
66 * BFI_PORT_I2H_ENABLE_RSP
67 */
68
69/**
70 * BFI_PORT_H2I_DISABLE_REQ
71 */
72
73/**
74 * BFI_PORT_I2H_DISABLE_RSP
75 */
76
77/**
78 * BFI_PORT_H2I_GET_STATS_REQ
79 */
80struct bfi_port_get_stats_req {
81 struct bfi_mhdr mh; /*!< common msg header */
82 union bfi_addr_u dma_addr;
83};
84
85/**
86 * BFI_PORT_I2H_GET_STATS_RSP
87 */
88
89/**
90 * BFI_PORT_H2I_CLEAR_STATS_REQ
91 */
92
93/**
94 * BFI_PORT_I2H_CLEAR_STATS_RSP
95 */
96
97union bfi_port_h2i_msg_u {
98 struct bfi_mhdr mh;
99 struct bfi_port_generic_req enable_req;
100 struct bfi_port_generic_req disable_req;
101 struct bfi_port_get_stats_req getstats_req;
102 struct bfi_port_generic_req clearstats_req;
103};
104
105union bfi_port_i2h_msg_u {
106 struct bfi_mhdr mh;
107 struct bfi_port_generic_rsp enable_rsp;
108 struct bfi_port_generic_rsp disable_rsp;
109 struct bfi_port_generic_rsp getstats_rsp;
110 struct bfi_port_generic_rsp clearstats_rsp;
111};
112
113/* @brief Mailbox commands from host to (DCBX/LLDP) firmware */
114enum bfi_cee_h2i_msgs {
115 BFI_CEE_H2I_GET_CFG_REQ = 1,
116 BFI_CEE_H2I_RESET_STATS = 2,
117 BFI_CEE_H2I_GET_STATS_REQ = 3,
118};
119
120/* @brief Mailbox reply and AEN messages from DCBX/LLDP firmware to host */
121enum bfi_cee_i2h_msgs {
122 BFI_CEE_I2H_GET_CFG_RSP = BFA_I2HM(1),
123 BFI_CEE_I2H_RESET_STATS_RSP = BFA_I2HM(2),
124 BFI_CEE_I2H_GET_STATS_RSP = BFA_I2HM(3),
125};
126
127/* Data structures */
128
129/*
130 * @brief H2I command structure for resetting the stats.
131 * BFI_CEE_H2I_RESET_STATS
132 */
133struct bfi_lldp_reset_stats {
134 struct bfi_mhdr mh;
135};
136
137/*
138 * @brief H2I command structure for resetting the stats.
139 * BFI_CEE_H2I_RESET_STATS
140 */
141struct bfi_cee_reset_stats {
142 struct bfi_mhdr mh;
143};
144
145/*
146 * @brief get configuration command from host
147 * BFI_CEE_H2I_GET_CFG_REQ
148 */
149struct bfi_cee_get_req {
150 struct bfi_mhdr mh;
151 union bfi_addr_u dma_addr;
152};
153
154/*
155 * @brief reply message from firmware
156 * BFI_CEE_I2H_GET_CFG_RSP
157 */
158struct bfi_cee_get_rsp {
159 struct bfi_mhdr mh;
160 u8 cmd_status;
161 u8 rsvd[3];
162};
163
164/*
165 * @brief get configuration command from host
166 * BFI_CEE_H2I_GET_STATS_REQ
167 */
168struct bfi_cee_stats_req {
169 struct bfi_mhdr mh;
170 union bfi_addr_u dma_addr;
171};
172
173/*
174 * @brief reply message from firmware
175 * BFI_CEE_I2H_GET_STATS_RSP
176 */
177struct bfi_cee_stats_rsp {
178 struct bfi_mhdr mh;
179 u8 cmd_status;
180 u8 rsvd[3];
181};
182
183/* @brief mailbox command structures from host to firmware */
184union bfi_cee_h2i_msg_u {
185 struct bfi_mhdr mh;
186 struct bfi_cee_get_req get_req;
187 struct bfi_cee_stats_req stats_req;
188};
189
190/* @brief mailbox message structures from firmware to host */
191union bfi_cee_i2h_msg_u {
192 struct bfi_mhdr mh;
193 struct bfi_cee_get_rsp get_rsp;
194 struct bfi_cee_stats_rsp stats_rsp;
195};
196
197#pragma pack()
198
199#endif /* __BFI_CNA_H__ */
diff --git a/drivers/net/bna/bfi_ctreg.h b/drivers/net/bna/bfi_ctreg.h
new file mode 100644
index 000000000000..404ea351d4a1
--- /dev/null
+++ b/drivers/net/bna/bfi_ctreg.h
@@ -0,0 +1,637 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18
19/*
20 * bfi_ctreg.h catapult host block register definitions
21 *
22 * !!! Do not edit. Auto generated. !!!
23 */
24
25#ifndef __BFI_CTREG_H__
26#define __BFI_CTREG_H__
27
28#define HOSTFN0_LPU_MBOX0_0 0x00019200
29#define HOSTFN1_LPU_MBOX0_8 0x00019260
30#define LPU_HOSTFN0_MBOX0_0 0x00019280
31#define LPU_HOSTFN1_MBOX0_8 0x000192e0
32#define HOSTFN2_LPU_MBOX0_0 0x00019400
33#define HOSTFN3_LPU_MBOX0_8 0x00019460
34#define LPU_HOSTFN2_MBOX0_0 0x00019480
35#define LPU_HOSTFN3_MBOX0_8 0x000194e0
36#define HOSTFN0_INT_STATUS 0x00014000
37#define __HOSTFN0_HALT_OCCURRED 0x01000000
38#define __HOSTFN0_INT_STATUS_LVL_MK 0x00f00000
39#define __HOSTFN0_INT_STATUS_LVL_SH 20
40#define __HOSTFN0_INT_STATUS_LVL(_v) ((_v) << __HOSTFN0_INT_STATUS_LVL_SH)
41#define __HOSTFN0_INT_STATUS_P_MK 0x000f0000
42#define __HOSTFN0_INT_STATUS_P_SH 16
43#define __HOSTFN0_INT_STATUS_P(_v) ((_v) << __HOSTFN0_INT_STATUS_P_SH)
44#define __HOSTFN0_INT_STATUS_F 0x0000ffff
45#define HOSTFN0_INT_MSK 0x00014004
46#define HOST_PAGE_NUM_FN0 0x00014008
47#define __HOST_PAGE_NUM_FN 0x000001ff
48#define HOST_MSIX_ERR_INDEX_FN0 0x0001400c
49#define __MSIX_ERR_INDEX_FN 0x000001ff
50#define HOSTFN1_INT_STATUS 0x00014100
51#define __HOSTFN1_HALT_OCCURRED 0x01000000
52#define __HOSTFN1_INT_STATUS_LVL_MK 0x00f00000
53#define __HOSTFN1_INT_STATUS_LVL_SH 20
54#define __HOSTFN1_INT_STATUS_LVL(_v) ((_v) << __HOSTFN1_INT_STATUS_LVL_SH)
55#define __HOSTFN1_INT_STATUS_P_MK 0x000f0000
56#define __HOSTFN1_INT_STATUS_P_SH 16
57#define __HOSTFN1_INT_STATUS_P(_v) ((_v) << __HOSTFN1_INT_STATUS_P_SH)
58#define __HOSTFN1_INT_STATUS_F 0x0000ffff
59#define HOSTFN1_INT_MSK 0x00014104
60#define HOST_PAGE_NUM_FN1 0x00014108
61#define HOST_MSIX_ERR_INDEX_FN1 0x0001410c
62#define APP_PLL_425_CTL_REG 0x00014204
63#define __P_425_PLL_LOCK 0x80000000
64#define __APP_PLL_425_SRAM_USE_100MHZ 0x00100000
65#define __APP_PLL_425_RESET_TIMER_MK 0x000e0000
66#define __APP_PLL_425_RESET_TIMER_SH 17
67#define __APP_PLL_425_RESET_TIMER(_v) ((_v) << __APP_PLL_425_RESET_TIMER_SH)
68#define __APP_PLL_425_LOGIC_SOFT_RESET 0x00010000
69#define __APP_PLL_425_CNTLMT0_1_MK 0x0000c000
70#define __APP_PLL_425_CNTLMT0_1_SH 14
71#define __APP_PLL_425_CNTLMT0_1(_v) ((_v) << __APP_PLL_425_CNTLMT0_1_SH)
72#define __APP_PLL_425_JITLMT0_1_MK 0x00003000
73#define __APP_PLL_425_JITLMT0_1_SH 12
74#define __APP_PLL_425_JITLMT0_1(_v) ((_v) << __APP_PLL_425_JITLMT0_1_SH)
75#define __APP_PLL_425_HREF 0x00000800
76#define __APP_PLL_425_HDIV 0x00000400
77#define __APP_PLL_425_P0_1_MK 0x00000300
78#define __APP_PLL_425_P0_1_SH 8
79#define __APP_PLL_425_P0_1(_v) ((_v) << __APP_PLL_425_P0_1_SH)
80#define __APP_PLL_425_Z0_2_MK 0x000000e0
81#define __APP_PLL_425_Z0_2_SH 5
82#define __APP_PLL_425_Z0_2(_v) ((_v) << __APP_PLL_425_Z0_2_SH)
83#define __APP_PLL_425_RSEL200500 0x00000010
84#define __APP_PLL_425_ENARST 0x00000008
85#define __APP_PLL_425_BYPASS 0x00000004
86#define __APP_PLL_425_LRESETN 0x00000002
87#define __APP_PLL_425_ENABLE 0x00000001
88#define APP_PLL_312_CTL_REG 0x00014208
89#define __P_312_PLL_LOCK 0x80000000
90#define __ENABLE_MAC_AHB_1 0x00800000
91#define __ENABLE_MAC_AHB_0 0x00400000
92#define __ENABLE_MAC_1 0x00200000
93#define __ENABLE_MAC_0 0x00100000
94#define __APP_PLL_312_RESET_TIMER_MK 0x000e0000
95#define __APP_PLL_312_RESET_TIMER_SH 17
96#define __APP_PLL_312_RESET_TIMER(_v) ((_v) << __APP_PLL_312_RESET_TIMER_SH)
97#define __APP_PLL_312_LOGIC_SOFT_RESET 0x00010000
98#define __APP_PLL_312_CNTLMT0_1_MK 0x0000c000
99#define __APP_PLL_312_CNTLMT0_1_SH 14
100#define __APP_PLL_312_CNTLMT0_1(_v) ((_v) << __APP_PLL_312_CNTLMT0_1_SH)
101#define __APP_PLL_312_JITLMT0_1_MK 0x00003000
102#define __APP_PLL_312_JITLMT0_1_SH 12
103#define __APP_PLL_312_JITLMT0_1(_v) ((_v) << __APP_PLL_312_JITLMT0_1_SH)
104#define __APP_PLL_312_HREF 0x00000800
105#define __APP_PLL_312_HDIV 0x00000400
106#define __APP_PLL_312_P0_1_MK 0x00000300
107#define __APP_PLL_312_P0_1_SH 8
108#define __APP_PLL_312_P0_1(_v) ((_v) << __APP_PLL_312_P0_1_SH)
109#define __APP_PLL_312_Z0_2_MK 0x000000e0
110#define __APP_PLL_312_Z0_2_SH 5
111#define __APP_PLL_312_Z0_2(_v) ((_v) << __APP_PLL_312_Z0_2_SH)
112#define __APP_PLL_312_RSEL200500 0x00000010
113#define __APP_PLL_312_ENARST 0x00000008
114#define __APP_PLL_312_BYPASS 0x00000004
115#define __APP_PLL_312_LRESETN 0x00000002
116#define __APP_PLL_312_ENABLE 0x00000001
117#define MBIST_CTL_REG 0x00014220
118#define __EDRAM_BISTR_START 0x00000004
119#define __MBIST_RESET 0x00000002
120#define __MBIST_START 0x00000001
121#define MBIST_STAT_REG 0x00014224
122#define __EDRAM_BISTR_STATUS 0x00000008
123#define __EDRAM_BISTR_DONE 0x00000004
124#define __MEM_BIT_STATUS 0x00000002
125#define __MBIST_DONE 0x00000001
126#define HOST_SEM0_REG 0x00014230
127#define __HOST_SEMAPHORE 0x00000001
128#define HOST_SEM1_REG 0x00014234
129#define HOST_SEM2_REG 0x00014238
130#define HOST_SEM3_REG 0x0001423c
131#define HOST_SEM0_INFO_REG 0x00014240
132#define HOST_SEM1_INFO_REG 0x00014244
133#define HOST_SEM2_INFO_REG 0x00014248
134#define HOST_SEM3_INFO_REG 0x0001424c
135#define ETH_MAC_SER_REG 0x00014288
136#define __APP_EMS_CKBUFAMPIN 0x00000020
137#define __APP_EMS_REFCLKSEL 0x00000010
138#define __APP_EMS_CMLCKSEL 0x00000008
139#define __APP_EMS_REFCKBUFEN2 0x00000004
140#define __APP_EMS_REFCKBUFEN1 0x00000002
141#define __APP_EMS_CHANNEL_SEL 0x00000001
142#define HOSTFN2_INT_STATUS 0x00014300
143#define __HOSTFN2_HALT_OCCURRED 0x01000000
144#define __HOSTFN2_INT_STATUS_LVL_MK 0x00f00000
145#define __HOSTFN2_INT_STATUS_LVL_SH 20
146#define __HOSTFN2_INT_STATUS_LVL(_v) ((_v) << __HOSTFN2_INT_STATUS_LVL_SH)
147#define __HOSTFN2_INT_STATUS_P_MK 0x000f0000
148#define __HOSTFN2_INT_STATUS_P_SH 16
149#define __HOSTFN2_INT_STATUS_P(_v) ((_v) << __HOSTFN2_INT_STATUS_P_SH)
150#define __HOSTFN2_INT_STATUS_F 0x0000ffff
151#define HOSTFN2_INT_MSK 0x00014304
152#define HOST_PAGE_NUM_FN2 0x00014308
153#define HOST_MSIX_ERR_INDEX_FN2 0x0001430c
154#define HOSTFN3_INT_STATUS 0x00014400
155#define __HALT_OCCURRED 0x01000000
156#define __HOSTFN3_INT_STATUS_LVL_MK 0x00f00000
157#define __HOSTFN3_INT_STATUS_LVL_SH 20
158#define __HOSTFN3_INT_STATUS_LVL(_v) ((_v) << __HOSTFN3_INT_STATUS_LVL_SH)
159#define __HOSTFN3_INT_STATUS_P_MK 0x000f0000
160#define __HOSTFN3_INT_STATUS_P_SH 16
161#define __HOSTFN3_INT_STATUS_P(_v) ((_v) << __HOSTFN3_INT_STATUS_P_SH)
162#define __HOSTFN3_INT_STATUS_F 0x0000ffff
163#define HOSTFN3_INT_MSK 0x00014404
164#define HOST_PAGE_NUM_FN3 0x00014408
165#define HOST_MSIX_ERR_INDEX_FN3 0x0001440c
166#define FNC_ID_REG 0x00014600
167#define __FUNCTION_NUMBER 0x00000007
168#define FNC_PERS_REG 0x00014604
169#define __F3_FUNCTION_ACTIVE 0x80000000
170#define __F3_FUNCTION_MODE 0x40000000
171#define __F3_PORT_MAP_MK 0x30000000
172#define __F3_PORT_MAP_SH 28
173#define __F3_PORT_MAP(_v) ((_v) << __F3_PORT_MAP_SH)
174#define __F3_VM_MODE 0x08000000
175#define __F3_INTX_STATUS_MK 0x07000000
176#define __F3_INTX_STATUS_SH 24
177#define __F3_INTX_STATUS(_v) ((_v) << __F3_INTX_STATUS_SH)
178#define __F2_FUNCTION_ACTIVE 0x00800000
179#define __F2_FUNCTION_MODE 0x00400000
180#define __F2_PORT_MAP_MK 0x00300000
181#define __F2_PORT_MAP_SH 20
182#define __F2_PORT_MAP(_v) ((_v) << __F2_PORT_MAP_SH)
183#define __F2_VM_MODE 0x00080000
184#define __F2_INTX_STATUS_MK 0x00070000
185#define __F2_INTX_STATUS_SH 16
186#define __F2_INTX_STATUS(_v) ((_v) << __F2_INTX_STATUS_SH)
187#define __F1_FUNCTION_ACTIVE 0x00008000
188#define __F1_FUNCTION_MODE 0x00004000
189#define __F1_PORT_MAP_MK 0x00003000
190#define __F1_PORT_MAP_SH 12
191#define __F1_PORT_MAP(_v) ((_v) << __F1_PORT_MAP_SH)
192#define __F1_VM_MODE 0x00000800
193#define __F1_INTX_STATUS_MK 0x00000700
194#define __F1_INTX_STATUS_SH 8
195#define __F1_INTX_STATUS(_v) ((_v) << __F1_INTX_STATUS_SH)
196#define __F0_FUNCTION_ACTIVE 0x00000080
197#define __F0_FUNCTION_MODE 0x00000040
198#define __F0_PORT_MAP_MK 0x00000030
199#define __F0_PORT_MAP_SH 4
200#define __F0_PORT_MAP(_v) ((_v) << __F0_PORT_MAP_SH)
201#define __F0_VM_MODE 0x00000008
202#define __F0_INTX_STATUS 0x00000007
203enum {
204 __F0_INTX_STATUS_MSIX = 0x0,
205 __F0_INTX_STATUS_INTA = 0x1,
206 __F0_INTX_STATUS_INTB = 0x2,
207 __F0_INTX_STATUS_INTC = 0x3,
208 __F0_INTX_STATUS_INTD = 0x4,
209};
210#define OP_MODE 0x0001460c
211#define __APP_ETH_CLK_LOWSPEED 0x00000004
212#define __GLOBAL_CORECLK_HALFSPEED 0x00000002
213#define __GLOBAL_FCOE_MODE 0x00000001
214#define HOST_SEM4_REG 0x00014610
215#define HOST_SEM5_REG 0x00014614
216#define HOST_SEM6_REG 0x00014618
217#define HOST_SEM7_REG 0x0001461c
218#define HOST_SEM4_INFO_REG 0x00014620
219#define HOST_SEM5_INFO_REG 0x00014624
220#define HOST_SEM6_INFO_REG 0x00014628
221#define HOST_SEM7_INFO_REG 0x0001462c
222#define HOSTFN0_LPU0_MBOX0_CMD_STAT 0x00019000
223#define __HOSTFN0_LPU0_MBOX0_INFO_MK 0xfffffffe
224#define __HOSTFN0_LPU0_MBOX0_INFO_SH 1
225#define __HOSTFN0_LPU0_MBOX0_INFO(_v) ((_v) << __HOSTFN0_LPU0_MBOX0_INFO_SH)
226#define __HOSTFN0_LPU0_MBOX0_CMD_STATUS 0x00000001
227#define HOSTFN0_LPU1_MBOX0_CMD_STAT 0x00019004
228#define __HOSTFN0_LPU1_MBOX0_INFO_MK 0xfffffffe
229#define __HOSTFN0_LPU1_MBOX0_INFO_SH 1
230#define __HOSTFN0_LPU1_MBOX0_INFO(_v) ((_v) << __HOSTFN0_LPU1_MBOX0_INFO_SH)
231#define __HOSTFN0_LPU1_MBOX0_CMD_STATUS 0x00000001
232#define LPU0_HOSTFN0_MBOX0_CMD_STAT 0x00019008
233#define __LPU0_HOSTFN0_MBOX0_INFO_MK 0xfffffffe
234#define __LPU0_HOSTFN0_MBOX0_INFO_SH 1
235#define __LPU0_HOSTFN0_MBOX0_INFO(_v) ((_v) << __LPU0_HOSTFN0_MBOX0_INFO_SH)
236#define __LPU0_HOSTFN0_MBOX0_CMD_STATUS 0x00000001
237#define LPU1_HOSTFN0_MBOX0_CMD_STAT 0x0001900c
238#define __LPU1_HOSTFN0_MBOX0_INFO_MK 0xfffffffe
239#define __LPU1_HOSTFN0_MBOX0_INFO_SH 1
240#define __LPU1_HOSTFN0_MBOX0_INFO(_v) ((_v) << __LPU1_HOSTFN0_MBOX0_INFO_SH)
241#define __LPU1_HOSTFN0_MBOX0_CMD_STATUS 0x00000001
242#define HOSTFN1_LPU0_MBOX0_CMD_STAT 0x00019010
243#define __HOSTFN1_LPU0_MBOX0_INFO_MK 0xfffffffe
244#define __HOSTFN1_LPU0_MBOX0_INFO_SH 1
245#define __HOSTFN1_LPU0_MBOX0_INFO(_v) ((_v) << __HOSTFN1_LPU0_MBOX0_INFO_SH)
246#define __HOSTFN1_LPU0_MBOX0_CMD_STATUS 0x00000001
247#define HOSTFN1_LPU1_MBOX0_CMD_STAT 0x00019014
248#define __HOSTFN1_LPU1_MBOX0_INFO_MK 0xfffffffe
249#define __HOSTFN1_LPU1_MBOX0_INFO_SH 1
250#define __HOSTFN1_LPU1_MBOX0_INFO(_v) ((_v) << __HOSTFN1_LPU1_MBOX0_INFO_SH)
251#define __HOSTFN1_LPU1_MBOX0_CMD_STATUS 0x00000001
252#define LPU0_HOSTFN1_MBOX0_CMD_STAT 0x00019018
253#define __LPU0_HOSTFN1_MBOX0_INFO_MK 0xfffffffe
254#define __LPU0_HOSTFN1_MBOX0_INFO_SH 1
255#define __LPU0_HOSTFN1_MBOX0_INFO(_v) ((_v) << __LPU0_HOSTFN1_MBOX0_INFO_SH)
256#define __LPU0_HOSTFN1_MBOX0_CMD_STATUS 0x00000001
257#define LPU1_HOSTFN1_MBOX0_CMD_STAT 0x0001901c
258#define __LPU1_HOSTFN1_MBOX0_INFO_MK 0xfffffffe
259#define __LPU1_HOSTFN1_MBOX0_INFO_SH 1
260#define __LPU1_HOSTFN1_MBOX0_INFO(_v) ((_v) << __LPU1_HOSTFN1_MBOX0_INFO_SH)
261#define __LPU1_HOSTFN1_MBOX0_CMD_STATUS 0x00000001
262#define HOSTFN2_LPU0_MBOX0_CMD_STAT 0x00019150
263#define __HOSTFN2_LPU0_MBOX0_INFO_MK 0xfffffffe
264#define __HOSTFN2_LPU0_MBOX0_INFO_SH 1
265#define __HOSTFN2_LPU0_MBOX0_INFO(_v) ((_v) << __HOSTFN2_LPU0_MBOX0_INFO_SH)
266#define __HOSTFN2_LPU0_MBOX0_CMD_STATUS 0x00000001
267#define HOSTFN2_LPU1_MBOX0_CMD_STAT 0x00019154
268#define __HOSTFN2_LPU1_MBOX0_INFO_MK 0xfffffffe
269#define __HOSTFN2_LPU1_MBOX0_INFO_SH 1
270#define __HOSTFN2_LPU1_MBOX0_INFO(_v) ((_v) << __HOSTFN2_LPU1_MBOX0_INFO_SH)
271#define __HOSTFN2_LPU1_MBOX0BOX0_CMD_STATUS 0x00000001
272#define LPU0_HOSTFN2_MBOX0_CMD_STAT 0x00019158
273#define __LPU0_HOSTFN2_MBOX0_INFO_MK 0xfffffffe
274#define __LPU0_HOSTFN2_MBOX0_INFO_SH 1
275#define __LPU0_HOSTFN2_MBOX0_INFO(_v) ((_v) << __LPU0_HOSTFN2_MBOX0_INFO_SH)
276#define __LPU0_HOSTFN2_MBOX0_CMD_STATUS 0x00000001
277#define LPU1_HOSTFN2_MBOX0_CMD_STAT 0x0001915c
278#define __LPU1_HOSTFN2_MBOX0_INFO_MK 0xfffffffe
279#define __LPU1_HOSTFN2_MBOX0_INFO_SH 1
280#define __LPU1_HOSTFN2_MBOX0_INFO(_v) ((_v) << __LPU1_HOSTFN2_MBOX0_INFO_SH)
281#define __LPU1_HOSTFN2_MBOX0_CMD_STATUS 0x00000001
282#define HOSTFN3_LPU0_MBOX0_CMD_STAT 0x00019160
283#define __HOSTFN3_LPU0_MBOX0_INFO_MK 0xfffffffe
284#define __HOSTFN3_LPU0_MBOX0_INFO_SH 1
285#define __HOSTFN3_LPU0_MBOX0_INFO(_v) ((_v) << __HOSTFN3_LPU0_MBOX0_INFO_SH)
286#define __HOSTFN3_LPU0_MBOX0_CMD_STATUS 0x00000001
287#define HOSTFN3_LPU1_MBOX0_CMD_STAT 0x00019164
288#define __HOSTFN3_LPU1_MBOX0_INFO_MK 0xfffffffe
289#define __HOSTFN3_LPU1_MBOX0_INFO_SH 1
290#define __HOSTFN3_LPU1_MBOX0_INFO(_v) ((_v) << __HOSTFN3_LPU1_MBOX0_INFO_SH)
291#define __HOSTFN3_LPU1_MBOX0_CMD_STATUS 0x00000001
292#define LPU0_HOSTFN3_MBOX0_CMD_STAT 0x00019168
293#define __LPU0_HOSTFN3_MBOX0_INFO_MK 0xfffffffe
294#define __LPU0_HOSTFN3_MBOX0_INFO_SH 1
295#define __LPU0_HOSTFN3_MBOX0_INFO(_v) ((_v) << __LPU0_HOSTFN3_MBOX0_INFO_SH)
296#define __LPU0_HOSTFN3_MBOX0_CMD_STATUS 0x00000001
297#define LPU1_HOSTFN3_MBOX0_CMD_STAT 0x0001916c
298#define __LPU1_HOSTFN3_MBOX0_INFO_MK 0xfffffffe
299#define __LPU1_HOSTFN3_MBOX0_INFO_SH 1
300#define __LPU1_HOSTFN3_MBOX0_INFO(_v) ((_v) << __LPU1_HOSTFN3_MBOX0_INFO_SH)
301#define __LPU1_HOSTFN3_MBOX0_CMD_STATUS 0x00000001
302#define FW_INIT_HALT_P0 0x000191ac
303#define __FW_INIT_HALT_P 0x00000001
304#define FW_INIT_HALT_P1 0x000191bc
305#define CPE_PI_PTR_Q0 0x00038000
306#define __CPE_PI_UNUSED_MK 0xffff0000
307#define __CPE_PI_UNUSED_SH 16
308#define __CPE_PI_UNUSED(_v) ((_v) << __CPE_PI_UNUSED_SH)
309#define __CPE_PI_PTR 0x0000ffff
310#define CPE_PI_PTR_Q1 0x00038040
311#define CPE_CI_PTR_Q0 0x00038004
312#define __CPE_CI_UNUSED_MK 0xffff0000
313#define __CPE_CI_UNUSED_SH 16
314#define __CPE_CI_UNUSED(_v) ((_v) << __CPE_CI_UNUSED_SH)
315#define __CPE_CI_PTR 0x0000ffff
316#define CPE_CI_PTR_Q1 0x00038044
317#define CPE_DEPTH_Q0 0x00038008
318#define __CPE_DEPTH_UNUSED_MK 0xf8000000
319#define __CPE_DEPTH_UNUSED_SH 27
320#define __CPE_DEPTH_UNUSED(_v) ((_v) << __CPE_DEPTH_UNUSED_SH)
321#define __CPE_MSIX_VEC_INDEX_MK 0x07ff0000
322#define __CPE_MSIX_VEC_INDEX_SH 16
323#define __CPE_MSIX_VEC_INDEX(_v) ((_v) << __CPE_MSIX_VEC_INDEX_SH)
324#define __CPE_DEPTH 0x0000ffff
325#define CPE_DEPTH_Q1 0x00038048
326#define CPE_QCTRL_Q0 0x0003800c
327#define __CPE_CTRL_UNUSED30_MK 0xfc000000
328#define __CPE_CTRL_UNUSED30_SH 26
329#define __CPE_CTRL_UNUSED30(_v) ((_v) << __CPE_CTRL_UNUSED30_SH)
330#define __CPE_FUNC_INT_CTRL_MK 0x03000000
331#define __CPE_FUNC_INT_CTRL_SH 24
332#define __CPE_FUNC_INT_CTRL(_v) ((_v) << __CPE_FUNC_INT_CTRL_SH)
333enum {
334 __CPE_FUNC_INT_CTRL_DISABLE = 0x0,
335 __CPE_FUNC_INT_CTRL_F2NF = 0x1,
336 __CPE_FUNC_INT_CTRL_3QUART = 0x2,
337 __CPE_FUNC_INT_CTRL_HALF = 0x3,
338};
339#define __CPE_CTRL_UNUSED20_MK 0x00f00000
340#define __CPE_CTRL_UNUSED20_SH 20
341#define __CPE_CTRL_UNUSED20(_v) ((_v) << __CPE_CTRL_UNUSED20_SH)
342#define __CPE_SCI_TH_MK 0x000f0000
343#define __CPE_SCI_TH_SH 16
344#define __CPE_SCI_TH(_v) ((_v) << __CPE_SCI_TH_SH)
345#define __CPE_CTRL_UNUSED10_MK 0x0000c000
346#define __CPE_CTRL_UNUSED10_SH 14
347#define __CPE_CTRL_UNUSED10(_v) ((_v) << __CPE_CTRL_UNUSED10_SH)
348#define __CPE_ACK_PENDING 0x00002000
349#define __CPE_CTRL_UNUSED40_MK 0x00001c00
350#define __CPE_CTRL_UNUSED40_SH 10
351#define __CPE_CTRL_UNUSED40(_v) ((_v) << __CPE_CTRL_UNUSED40_SH)
352#define __CPE_PCIEID_MK 0x00000300
353#define __CPE_PCIEID_SH 8
354#define __CPE_PCIEID(_v) ((_v) << __CPE_PCIEID_SH)
355#define __CPE_CTRL_UNUSED00_MK 0x000000fe
356#define __CPE_CTRL_UNUSED00_SH 1
357#define __CPE_CTRL_UNUSED00(_v) ((_v) << __CPE_CTRL_UNUSED00_SH)
358#define __CPE_ESIZE 0x00000001
359#define CPE_QCTRL_Q1 0x0003804c
360#define __CPE_CTRL_UNUSED31_MK 0xfc000000
361#define __CPE_CTRL_UNUSED31_SH 26
362#define __CPE_CTRL_UNUSED31(_v) ((_v) << __CPE_CTRL_UNUSED31_SH)
363#define __CPE_CTRL_UNUSED21_MK 0x00f00000
364#define __CPE_CTRL_UNUSED21_SH 20
365#define __CPE_CTRL_UNUSED21(_v) ((_v) << __CPE_CTRL_UNUSED21_SH)
366#define __CPE_CTRL_UNUSED11_MK 0x0000c000
367#define __CPE_CTRL_UNUSED11_SH 14
368#define __CPE_CTRL_UNUSED11(_v) ((_v) << __CPE_CTRL_UNUSED11_SH)
369#define __CPE_CTRL_UNUSED41_MK 0x00001c00
370#define __CPE_CTRL_UNUSED41_SH 10
371#define __CPE_CTRL_UNUSED41(_v) ((_v) << __CPE_CTRL_UNUSED41_SH)
372#define __CPE_CTRL_UNUSED01_MK 0x000000fe
373#define __CPE_CTRL_UNUSED01_SH 1
374#define __CPE_CTRL_UNUSED01(_v) ((_v) << __CPE_CTRL_UNUSED01_SH)
375#define RME_PI_PTR_Q0 0x00038020
376#define __LATENCY_TIME_STAMP_MK 0xffff0000
377#define __LATENCY_TIME_STAMP_SH 16
378#define __LATENCY_TIME_STAMP(_v) ((_v) << __LATENCY_TIME_STAMP_SH)
379#define __RME_PI_PTR 0x0000ffff
380#define RME_PI_PTR_Q1 0x00038060
381#define RME_CI_PTR_Q0 0x00038024
382#define __DELAY_TIME_STAMP_MK 0xffff0000
383#define __DELAY_TIME_STAMP_SH 16
384#define __DELAY_TIME_STAMP(_v) ((_v) << __DELAY_TIME_STAMP_SH)
385#define __RME_CI_PTR 0x0000ffff
386#define RME_CI_PTR_Q1 0x00038064
387#define RME_DEPTH_Q0 0x00038028
388#define __RME_DEPTH_UNUSED_MK 0xf8000000
389#define __RME_DEPTH_UNUSED_SH 27
390#define __RME_DEPTH_UNUSED(_v) ((_v) << __RME_DEPTH_UNUSED_SH)
391#define __RME_MSIX_VEC_INDEX_MK 0x07ff0000
392#define __RME_MSIX_VEC_INDEX_SH 16
393#define __RME_MSIX_VEC_INDEX(_v) ((_v) << __RME_MSIX_VEC_INDEX_SH)
394#define __RME_DEPTH 0x0000ffff
395#define RME_DEPTH_Q1 0x00038068
396#define RME_QCTRL_Q0 0x0003802c
397#define __RME_INT_LATENCY_TIMER_MK 0xff000000
398#define __RME_INT_LATENCY_TIMER_SH 24
399#define __RME_INT_LATENCY_TIMER(_v) ((_v) << __RME_INT_LATENCY_TIMER_SH)
400#define __RME_INT_DELAY_TIMER_MK 0x00ff0000
401#define __RME_INT_DELAY_TIMER_SH 16
402#define __RME_INT_DELAY_TIMER(_v) ((_v) << __RME_INT_DELAY_TIMER_SH)
403#define __RME_INT_DELAY_DISABLE 0x00008000
404#define __RME_DLY_DELAY_DISABLE 0x00004000
405#define __RME_ACK_PENDING 0x00002000
406#define __RME_FULL_INTERRUPT_DISABLE 0x00001000
407#define __RME_CTRL_UNUSED10_MK 0x00000c00
408#define __RME_CTRL_UNUSED10_SH 10
409#define __RME_CTRL_UNUSED10(_v) ((_v) << __RME_CTRL_UNUSED10_SH)
410#define __RME_PCIEID_MK 0x00000300
411#define __RME_PCIEID_SH 8
412#define __RME_PCIEID(_v) ((_v) << __RME_PCIEID_SH)
413#define __RME_CTRL_UNUSED00_MK 0x000000fe
414#define __RME_CTRL_UNUSED00_SH 1
415#define __RME_CTRL_UNUSED00(_v) ((_v) << __RME_CTRL_UNUSED00_SH)
416#define __RME_ESIZE 0x00000001
417#define RME_QCTRL_Q1 0x0003806c
418#define __RME_CTRL_UNUSED11_MK 0x00000c00
419#define __RME_CTRL_UNUSED11_SH 10
420#define __RME_CTRL_UNUSED11(_v) ((_v) << __RME_CTRL_UNUSED11_SH)
421#define __RME_CTRL_UNUSED01_MK 0x000000fe
422#define __RME_CTRL_UNUSED01_SH 1
423#define __RME_CTRL_UNUSED01(_v) ((_v) << __RME_CTRL_UNUSED01_SH)
424#define PSS_CTL_REG 0x00018800
425#define __PSS_I2C_CLK_DIV_MK 0x007f0000
426#define __PSS_I2C_CLK_DIV_SH 16
427#define __PSS_I2C_CLK_DIV(_v) ((_v) << __PSS_I2C_CLK_DIV_SH)
428#define __PSS_LMEM_INIT_DONE 0x00001000
429#define __PSS_LMEM_RESET 0x00000200
430#define __PSS_LMEM_INIT_EN 0x00000100
431#define __PSS_LPU1_RESET 0x00000002
432#define __PSS_LPU0_RESET 0x00000001
433#define PSS_ERR_STATUS_REG 0x00018810
434#define __PSS_LPU1_TCM_READ_ERR 0x00200000
435#define __PSS_LPU0_TCM_READ_ERR 0x00100000
436#define __PSS_LMEM5_CORR_ERR 0x00080000
437#define __PSS_LMEM4_CORR_ERR 0x00040000
438#define __PSS_LMEM3_CORR_ERR 0x00020000
439#define __PSS_LMEM2_CORR_ERR 0x00010000
440#define __PSS_LMEM1_CORR_ERR 0x00008000
441#define __PSS_LMEM0_CORR_ERR 0x00004000
442#define __PSS_LMEM5_UNCORR_ERR 0x00002000
443#define __PSS_LMEM4_UNCORR_ERR 0x00001000
444#define __PSS_LMEM3_UNCORR_ERR 0x00000800
445#define __PSS_LMEM2_UNCORR_ERR 0x00000400
446#define __PSS_LMEM1_UNCORR_ERR 0x00000200
447#define __PSS_LMEM0_UNCORR_ERR 0x00000100
448#define __PSS_BAL_PERR 0x00000080
449#define __PSS_DIP_IF_ERR 0x00000040
450#define __PSS_IOH_IF_ERR 0x00000020
451#define __PSS_TDS_IF_ERR 0x00000010
452#define __PSS_RDS_IF_ERR 0x00000008
453#define __PSS_SGM_IF_ERR 0x00000004
454#define __PSS_LPU1_RAM_ERR 0x00000002
455#define __PSS_LPU0_RAM_ERR 0x00000001
456#define ERR_SET_REG 0x00018818
457#define __PSS_ERR_STATUS_SET 0x003fffff
458#define PMM_1T_RESET_REG_P0 0x0002381c
459#define __PMM_1T_RESET_P 0x00000001
460#define PMM_1T_RESET_REG_P1 0x00023c1c
461#define HQM_QSET0_RXQ_DRBL_P0 0x00038000
462#define __RXQ0_ADD_VECTORS_P 0x80000000
463#define __RXQ0_STOP_P 0x40000000
464#define __RXQ0_PRD_PTR_P 0x0000ffff
465#define HQM_QSET1_RXQ_DRBL_P0 0x00038080
466#define __RXQ1_ADD_VECTORS_P 0x80000000
467#define __RXQ1_STOP_P 0x40000000
468#define __RXQ1_PRD_PTR_P 0x0000ffff
469#define HQM_QSET0_RXQ_DRBL_P1 0x0003c000
470#define HQM_QSET1_RXQ_DRBL_P1 0x0003c080
471#define HQM_QSET0_TXQ_DRBL_P0 0x00038020
472#define __TXQ0_ADD_VECTORS_P 0x80000000
473#define __TXQ0_STOP_P 0x40000000
474#define __TXQ0_PRD_PTR_P 0x0000ffff
475#define HQM_QSET1_TXQ_DRBL_P0 0x000380a0
476#define __TXQ1_ADD_VECTORS_P 0x80000000
477#define __TXQ1_STOP_P 0x40000000
478#define __TXQ1_PRD_PTR_P 0x0000ffff
479#define HQM_QSET0_TXQ_DRBL_P1 0x0003c020
480#define HQM_QSET1_TXQ_DRBL_P1 0x0003c0a0
481#define HQM_QSET0_IB_DRBL_1_P0 0x00038040
482#define __IB1_0_ACK_P 0x80000000
483#define __IB1_0_DISABLE_P 0x40000000
484#define __IB1_0_COALESCING_CFG_P_MK 0x00ff0000
485#define __IB1_0_COALESCING_CFG_P_SH 16
486#define __IB1_0_COALESCING_CFG_P(_v) ((_v) << __IB1_0_COALESCING_CFG_P_SH)
487#define __IB1_0_NUM_OF_ACKED_EVENTS_P 0x0000ffff
488#define HQM_QSET1_IB_DRBL_1_P0 0x000380c0
489#define __IB1_1_ACK_P 0x80000000
490#define __IB1_1_DISABLE_P 0x40000000
491#define __IB1_1_COALESCING_CFG_P_MK 0x00ff0000
492#define __IB1_1_COALESCING_CFG_P_SH 16
493#define __IB1_1_COALESCING_CFG_P(_v) ((_v) << __IB1_1_COALESCING_CFG_P_SH)
494#define __IB1_1_NUM_OF_ACKED_EVENTS_P 0x0000ffff
495#define HQM_QSET0_IB_DRBL_1_P1 0x0003c040
496#define HQM_QSET1_IB_DRBL_1_P1 0x0003c0c0
497#define HQM_QSET0_IB_DRBL_2_P0 0x00038060
498#define __IB2_0_ACK_P 0x80000000
499#define __IB2_0_DISABLE_P 0x40000000
500#define __IB2_0_COALESCING_CFG_P_MK 0x00ff0000
501#define __IB2_0_COALESCING_CFG_P_SH 16
502#define __IB2_0_COALESCING_CFG_P(_v) ((_v) << __IB2_0_COALESCING_CFG_P_SH)
503#define __IB2_0_NUM_OF_ACKED_EVENTS_P 0x0000ffff
504#define HQM_QSET1_IB_DRBL_2_P0 0x000380e0
505#define __IB2_1_ACK_P 0x80000000
506#define __IB2_1_DISABLE_P 0x40000000
507#define __IB2_1_COALESCING_CFG_P_MK 0x00ff0000
508#define __IB2_1_COALESCING_CFG_P_SH 16
509#define __IB2_1_COALESCING_CFG_P(_v) ((_v) << __IB2_1_COALESCING_CFG_P_SH)
510#define __IB2_1_NUM_OF_ACKED_EVENTS_P 0x0000ffff
511#define HQM_QSET0_IB_DRBL_2_P1 0x0003c060
512#define HQM_QSET1_IB_DRBL_2_P1 0x0003c0e0
513
514/*
515 * These definitions are either in error/missing in spec. Its auto-generated
516 * from hard coded values in regparse.pl.
517 */
518#define __EMPHPOST_AT_4G_MK_FIX 0x0000001c
519#define __EMPHPOST_AT_4G_SH_FIX 0x00000002
520#define __EMPHPRE_AT_4G_FIX 0x00000003
521#define __SFP_TXRATE_EN_FIX 0x00000100
522#define __SFP_RXRATE_EN_FIX 0x00000080
523
524/*
525 * These register definitions are auto-generated from hard coded values
526 * in regparse.pl.
527 */
528
529/*
530 * These register mapping definitions are auto-generated from mapping tables
531 * in regparse.pl.
532 */
533#define BFA_IOC0_HBEAT_REG HOST_SEM0_INFO_REG
534#define BFA_IOC0_STATE_REG HOST_SEM1_INFO_REG
535#define BFA_IOC1_HBEAT_REG HOST_SEM2_INFO_REG
536#define BFA_IOC1_STATE_REG HOST_SEM3_INFO_REG
537#define BFA_FW_USE_COUNT HOST_SEM4_INFO_REG
538
539#define CPE_DEPTH_Q(__n) \
540 (CPE_DEPTH_Q0 + (__n) * (CPE_DEPTH_Q1 - CPE_DEPTH_Q0))
541#define CPE_QCTRL_Q(__n) \
542 (CPE_QCTRL_Q0 + (__n) * (CPE_QCTRL_Q1 - CPE_QCTRL_Q0))
543#define CPE_PI_PTR_Q(__n) \
544 (CPE_PI_PTR_Q0 + (__n) * (CPE_PI_PTR_Q1 - CPE_PI_PTR_Q0))
545#define CPE_CI_PTR_Q(__n) \
546 (CPE_CI_PTR_Q0 + (__n) * (CPE_CI_PTR_Q1 - CPE_CI_PTR_Q0))
547#define RME_DEPTH_Q(__n) \
548 (RME_DEPTH_Q0 + (__n) * (RME_DEPTH_Q1 - RME_DEPTH_Q0))
549#define RME_QCTRL_Q(__n) \
550 (RME_QCTRL_Q0 + (__n) * (RME_QCTRL_Q1 - RME_QCTRL_Q0))
551#define RME_PI_PTR_Q(__n) \
552 (RME_PI_PTR_Q0 + (__n) * (RME_PI_PTR_Q1 - RME_PI_PTR_Q0))
553#define RME_CI_PTR_Q(__n) \
554 (RME_CI_PTR_Q0 + (__n) * (RME_CI_PTR_Q1 - RME_CI_PTR_Q0))
555#define HQM_QSET_RXQ_DRBL_P0(__n) (HQM_QSET0_RXQ_DRBL_P0 + (__n) \
556 * (HQM_QSET1_RXQ_DRBL_P0 - HQM_QSET0_RXQ_DRBL_P0))
557#define HQM_QSET_TXQ_DRBL_P0(__n) (HQM_QSET0_TXQ_DRBL_P0 + (__n) \
558 * (HQM_QSET1_TXQ_DRBL_P0 - HQM_QSET0_TXQ_DRBL_P0))
559#define HQM_QSET_IB_DRBL_1_P0(__n) (HQM_QSET0_IB_DRBL_1_P0 + (__n) \
560 * (HQM_QSET1_IB_DRBL_1_P0 - HQM_QSET0_IB_DRBL_1_P0))
561#define HQM_QSET_IB_DRBL_2_P0(__n) (HQM_QSET0_IB_DRBL_2_P0 + (__n) \
562 * (HQM_QSET1_IB_DRBL_2_P0 - HQM_QSET0_IB_DRBL_2_P0))
563#define HQM_QSET_RXQ_DRBL_P1(__n) (HQM_QSET0_RXQ_DRBL_P1 + (__n) \
564 * (HQM_QSET1_RXQ_DRBL_P1 - HQM_QSET0_RXQ_DRBL_P1))
565#define HQM_QSET_TXQ_DRBL_P1(__n) (HQM_QSET0_TXQ_DRBL_P1 + (__n) \
566 * (HQM_QSET1_TXQ_DRBL_P1 - HQM_QSET0_TXQ_DRBL_P1))
567#define HQM_QSET_IB_DRBL_1_P1(__n) (HQM_QSET0_IB_DRBL_1_P1 + (__n) \
568 * (HQM_QSET1_IB_DRBL_1_P1 - HQM_QSET0_IB_DRBL_1_P1))
569#define HQM_QSET_IB_DRBL_2_P1(__n) (HQM_QSET0_IB_DRBL_2_P1 + (__n) \
570 * (HQM_QSET1_IB_DRBL_2_P1 - HQM_QSET0_IB_DRBL_2_P1))
571
572#define CPE_Q_NUM(__fn, __q) (((__fn) << 2) + (__q))
573#define RME_Q_NUM(__fn, __q) (((__fn) << 2) + (__q))
574#define CPE_Q_MASK(__q) ((__q) & 0x3)
575#define RME_Q_MASK(__q) ((__q) & 0x3)
576
577/*
578 * PCI MSI-X vector defines
579 */
580enum {
581 BFA_MSIX_CPE_Q0 = 0,
582 BFA_MSIX_CPE_Q1 = 1,
583 BFA_MSIX_CPE_Q2 = 2,
584 BFA_MSIX_CPE_Q3 = 3,
585 BFA_MSIX_RME_Q0 = 4,
586 BFA_MSIX_RME_Q1 = 5,
587 BFA_MSIX_RME_Q2 = 6,
588 BFA_MSIX_RME_Q3 = 7,
589 BFA_MSIX_LPU_ERR = 8,
590 BFA_MSIX_CT_MAX = 9,
591};
592
593/*
594 * And corresponding host interrupt status bit field defines
595 */
596#define __HFN_INT_CPE_Q0 0x00000001U
597#define __HFN_INT_CPE_Q1 0x00000002U
598#define __HFN_INT_CPE_Q2 0x00000004U
599#define __HFN_INT_CPE_Q3 0x00000008U
600#define __HFN_INT_CPE_Q4 0x00000010U
601#define __HFN_INT_CPE_Q5 0x00000020U
602#define __HFN_INT_CPE_Q6 0x00000040U
603#define __HFN_INT_CPE_Q7 0x00000080U
604#define __HFN_INT_RME_Q0 0x00000100U
605#define __HFN_INT_RME_Q1 0x00000200U
606#define __HFN_INT_RME_Q2 0x00000400U
607#define __HFN_INT_RME_Q3 0x00000800U
608#define __HFN_INT_RME_Q4 0x00001000U
609#define __HFN_INT_RME_Q5 0x00002000U
610#define __HFN_INT_RME_Q6 0x00004000U
611#define __HFN_INT_RME_Q7 0x00008000U
612#define __HFN_INT_ERR_EMC 0x00010000U
613#define __HFN_INT_ERR_LPU0 0x00020000U
614#define __HFN_INT_ERR_LPU1 0x00040000U
615#define __HFN_INT_ERR_PSS 0x00080000U
616#define __HFN_INT_MBOX_LPU0 0x00100000U
617#define __HFN_INT_MBOX_LPU1 0x00200000U
618#define __HFN_INT_MBOX1_LPU0 0x00400000U
619#define __HFN_INT_MBOX1_LPU1 0x00800000U
620#define __HFN_INT_LL_HALT 0x01000000U
621#define __HFN_INT_CPE_MASK 0x000000ffU
622#define __HFN_INT_RME_MASK 0x0000ff00U
623
624/*
625 * catapult memory map.
626 */
627#define LL_PGN_HQM0 0x0096
628#define LL_PGN_HQM1 0x0097
629#define PSS_SMEM_PAGE_START 0x8000
630#define PSS_SMEM_PGNUM(_pg0, _ma) ((_pg0) + ((_ma) >> 15))
631#define PSS_SMEM_PGOFF(_ma) ((_ma) & 0x7fff)
632
633/*
634 * End of catapult memory map
635 */
636
637#endif /* __BFI_CTREG_H__ */
diff --git a/drivers/net/bna/bfi_ll.h b/drivers/net/bna/bfi_ll.h
new file mode 100644
index 000000000000..bee4d054066a
--- /dev/null
+++ b/drivers/net/bna/bfi_ll.h
@@ -0,0 +1,438 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18#ifndef __BFI_LL_H__
19#define __BFI_LL_H__
20
21#include "bfi.h"
22
23#pragma pack(1)
24
25/**
26 * @brief
27 * "enums" for all LL mailbox messages other than IOC
28 */
29enum {
30 BFI_LL_H2I_MAC_UCAST_SET_REQ = 1,
31 BFI_LL_H2I_MAC_UCAST_ADD_REQ = 2,
32 BFI_LL_H2I_MAC_UCAST_DEL_REQ = 3,
33
34 BFI_LL_H2I_MAC_MCAST_ADD_REQ = 4,
35 BFI_LL_H2I_MAC_MCAST_DEL_REQ = 5,
36 BFI_LL_H2I_MAC_MCAST_FILTER_REQ = 6,
37 BFI_LL_H2I_MAC_MCAST_DEL_ALL_REQ = 7,
38
39 BFI_LL_H2I_PORT_ADMIN_REQ = 8,
40 BFI_LL_H2I_STATS_GET_REQ = 9,
41 BFI_LL_H2I_STATS_CLEAR_REQ = 10,
42
43 BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ = 11,
44 BFI_LL_H2I_RXF_DEFAULT_SET_REQ = 12,
45
46 BFI_LL_H2I_TXQ_STOP_REQ = 13,
47 BFI_LL_H2I_RXQ_STOP_REQ = 14,
48
49 BFI_LL_H2I_DIAG_LOOPBACK_REQ = 15,
50
51 BFI_LL_H2I_SET_PAUSE_REQ = 16,
52 BFI_LL_H2I_MTU_INFO_REQ = 17,
53
54 BFI_LL_H2I_RX_REQ = 18,
55} ;
56
57enum {
58 BFI_LL_I2H_MAC_UCAST_SET_RSP = BFA_I2HM(1),
59 BFI_LL_I2H_MAC_UCAST_ADD_RSP = BFA_I2HM(2),
60 BFI_LL_I2H_MAC_UCAST_DEL_RSP = BFA_I2HM(3),
61
62 BFI_LL_I2H_MAC_MCAST_ADD_RSP = BFA_I2HM(4),
63 BFI_LL_I2H_MAC_MCAST_DEL_RSP = BFA_I2HM(5),
64 BFI_LL_I2H_MAC_MCAST_FILTER_RSP = BFA_I2HM(6),
65 BFI_LL_I2H_MAC_MCAST_DEL_ALL_RSP = BFA_I2HM(7),
66
67 BFI_LL_I2H_PORT_ADMIN_RSP = BFA_I2HM(8),
68 BFI_LL_I2H_STATS_GET_RSP = BFA_I2HM(9),
69 BFI_LL_I2H_STATS_CLEAR_RSP = BFA_I2HM(10),
70
71 BFI_LL_I2H_RXF_PROMISCUOUS_SET_RSP = BFA_I2HM(11),
72 BFI_LL_I2H_RXF_DEFAULT_SET_RSP = BFA_I2HM(12),
73
74 BFI_LL_I2H_TXQ_STOP_RSP = BFA_I2HM(13),
75 BFI_LL_I2H_RXQ_STOP_RSP = BFA_I2HM(14),
76
77 BFI_LL_I2H_DIAG_LOOPBACK_RSP = BFA_I2HM(15),
78
79 BFI_LL_I2H_SET_PAUSE_RSP = BFA_I2HM(16),
80
81 BFI_LL_I2H_MTU_INFO_RSP = BFA_I2HM(17),
82 BFI_LL_I2H_RX_RSP = BFA_I2HM(18),
83
84 BFI_LL_I2H_LINK_DOWN_AEN = BFA_I2HM(19),
85 BFI_LL_I2H_LINK_UP_AEN = BFA_I2HM(20),
86
87 BFI_LL_I2H_PORT_ENABLE_AEN = BFA_I2HM(21),
88 BFI_LL_I2H_PORT_DISABLE_AEN = BFA_I2HM(22),
89} ;
90
91/**
92 * @brief bfi_ll_mac_addr_req is used by:
93 * BFI_LL_H2I_MAC_UCAST_SET_REQ
94 * BFI_LL_H2I_MAC_UCAST_ADD_REQ
95 * BFI_LL_H2I_MAC_UCAST_DEL_REQ
96 * BFI_LL_H2I_MAC_MCAST_ADD_REQ
97 * BFI_LL_H2I_MAC_MCAST_DEL_REQ
98 */
99struct bfi_ll_mac_addr_req {
100 struct bfi_mhdr mh; /*!< common msg header */
101 u8 rxf_id;
102 u8 rsvd1[3];
103 mac_t mac_addr;
104 u8 rsvd2[2];
105};
106
107/**
108 * @brief bfi_ll_mcast_filter_req is used by:
109 * BFI_LL_H2I_MAC_MCAST_FILTER_REQ
110 */
111struct bfi_ll_mcast_filter_req {
112 struct bfi_mhdr mh; /*!< common msg header */
113 u8 rxf_id;
114 u8 enable;
115 u8 rsvd[2];
116};
117
118/**
119 * @brief bfi_ll_mcast_del_all is used by:
120 * BFI_LL_H2I_MAC_MCAST_DEL_ALL_REQ
121 */
122struct bfi_ll_mcast_del_all_req {
123 struct bfi_mhdr mh; /*!< common msg header */
124 u8 rxf_id;
125 u8 rsvd[3];
126};
127
128/**
129 * @brief bfi_ll_q_stop_req is used by:
130 * BFI_LL_H2I_TXQ_STOP_REQ
131 * BFI_LL_H2I_RXQ_STOP_REQ
132 */
133struct bfi_ll_q_stop_req {
134 struct bfi_mhdr mh; /*!< common msg header */
135 u32 q_id_mask[2]; /* !< bit-mask for queue ids */
136};
137
138/**
139 * @brief bfi_ll_stats_req is used by:
140 * BFI_LL_I2H_STATS_GET_REQ
141 * BFI_LL_I2H_STATS_CLEAR_REQ
142 */
143struct bfi_ll_stats_req {
144 struct bfi_mhdr mh; /*!< common msg header */
145 u16 stats_mask; /* !< bit-mask for non-function statistics */
146 u8 rsvd[2];
147 u32 rxf_id_mask[2]; /* !< bit-mask for RxF Statistics */
148 u32 txf_id_mask[2]; /* !< bit-mask for TxF Statistics */
149 union bfi_addr_u host_buffer; /* !< where statistics are returned */
150};
151
152/**
153 * @brief defines for "stats_mask" above.
154 */
155#define BFI_LL_STATS_MAC (1 << 0) /* !< MAC Statistics */
156#define BFI_LL_STATS_BPC (1 << 1) /* !< Pause Stats from BPC */
157#define BFI_LL_STATS_RAD (1 << 2) /* !< Rx Admission Statistics */
158#define BFI_LL_STATS_RX_FC (1 << 3) /* !< Rx FC Stats from RxA */
159#define BFI_LL_STATS_TX_FC (1 << 4) /* !< Tx FC Stats from TxA */
160
161#define BFI_LL_STATS_ALL 0x1f
162
163/**
164 * @brief bfi_ll_port_admin_req
165 */
166struct bfi_ll_port_admin_req {
167 struct bfi_mhdr mh; /*!< common msg header */
168 u8 up;
169 u8 rsvd[3];
170};
171
172/**
173 * @brief bfi_ll_rxf_req is used by:
174 * BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ
175 * BFI_LL_H2I_RXF_DEFAULT_SET_REQ
176 */
177struct bfi_ll_rxf_req {
178 struct bfi_mhdr mh; /*!< common msg header */
179 u8 rxf_id;
180 u8 enable;
181 u8 rsvd[2];
182};
183
184/**
185 * @brief bfi_ll_rxf_multi_req is used by:
186 * BFI_LL_H2I_RX_REQ
187 */
188struct bfi_ll_rxf_multi_req {
189 struct bfi_mhdr mh; /*!< common msg header */
190 u32 rxf_id_mask[2];
191 u8 enable;
192 u8 rsvd[3];
193};
194
195/**
196 * @brief enum for Loopback opmodes
197 */
198enum {
199 BFI_LL_DIAG_LB_OPMODE_EXT = 0,
200 BFI_LL_DIAG_LB_OPMODE_CBL = 1,
201};
202
203/**
204 * @brief bfi_ll_set_pause_req is used by:
205 * BFI_LL_H2I_SET_PAUSE_REQ
206 */
207struct bfi_ll_set_pause_req {
208 struct bfi_mhdr mh;
209 u8 tx_pause; /* 1 = enable, 0 = disable */
210 u8 rx_pause; /* 1 = enable, 0 = disable */
211 u8 rsvd[2];
212};
213
214/**
215 * @brief bfi_ll_mtu_info_req is used by:
216 * BFI_LL_H2I_MTU_INFO_REQ
217 */
218struct bfi_ll_mtu_info_req {
219 struct bfi_mhdr mh;
220 u16 mtu;
221 u8 rsvd[2];
222};
223
224/**
225 * @brief
226 * Response header format used by all responses
227 * For both responses and asynchronous notifications
228 */
229struct bfi_ll_rsp {
230 struct bfi_mhdr mh; /*!< common msg header */
231 u8 error;
232 u8 rsvd[3];
233};
234
235/**
236 * @brief bfi_ll_cee_aen is used by:
237 * BFI_LL_I2H_LINK_DOWN_AEN
238 * BFI_LL_I2H_LINK_UP_AEN
239 */
240struct bfi_ll_aen {
241 struct bfi_mhdr mh; /*!< common msg header */
242 u32 reason;
243 u8 cee_linkup;
244 u8 prio_map; /*!< LL priority bit-map */
245 u8 rsvd[2];
246};
247
248/**
249 * @brief
250 * The following error codes can be returned
251 * by the mbox commands
252 */
253enum {
254 BFI_LL_CMD_OK = 0,
255 BFI_LL_CMD_FAIL = 1,
256 BFI_LL_CMD_DUP_ENTRY = 2, /* !< Duplicate entry in CAM */
257 BFI_LL_CMD_CAM_FULL = 3, /* !< CAM is full */
258 BFI_LL_CMD_NOT_OWNER = 4, /* !< Not permitted, b'cos not owner */
259 BFI_LL_CMD_NOT_EXEC = 5, /* !< Was not sent to f/w at all */
260 BFI_LL_CMD_WAITING = 6, /* !< Waiting for completion (VMware) */
261 BFI_LL_CMD_PORT_DISABLED = 7, /* !< port in disabled state */
262} ;
263
264/* Statistics */
265#define BFI_LL_TXF_ID_MAX 64
266#define BFI_LL_RXF_ID_MAX 64
267
268/* TxF Frame Statistics */
269struct bfi_ll_stats_txf {
270 u64 ucast_octets;
271 u64 ucast;
272 u64 ucast_vlan;
273
274 u64 mcast_octets;
275 u64 mcast;
276 u64 mcast_vlan;
277
278 u64 bcast_octets;
279 u64 bcast;
280 u64 bcast_vlan;
281
282 u64 errors;
283 u64 filter_vlan; /* frames filtered due to VLAN */
284 u64 filter_mac_sa; /* frames filtered due to SA check */
285};
286
287/* RxF Frame Statistics */
288struct bfi_ll_stats_rxf {
289 u64 ucast_octets;
290 u64 ucast;
291 u64 ucast_vlan;
292
293 u64 mcast_octets;
294 u64 mcast;
295 u64 mcast_vlan;
296
297 u64 bcast_octets;
298 u64 bcast;
299 u64 bcast_vlan;
300 u64 frame_drops;
301};
302
303/* FC Tx Frame Statistics */
304struct bfi_ll_stats_fc_tx {
305 u64 txf_ucast_octets;
306 u64 txf_ucast;
307 u64 txf_ucast_vlan;
308
309 u64 txf_mcast_octets;
310 u64 txf_mcast;
311 u64 txf_mcast_vlan;
312
313 u64 txf_bcast_octets;
314 u64 txf_bcast;
315 u64 txf_bcast_vlan;
316
317 u64 txf_parity_errors;
318 u64 txf_timeout;
319 u64 txf_fid_parity_errors;
320};
321
322/* FC Rx Frame Statistics */
323struct bfi_ll_stats_fc_rx {
324 u64 rxf_ucast_octets;
325 u64 rxf_ucast;
326 u64 rxf_ucast_vlan;
327
328 u64 rxf_mcast_octets;
329 u64 rxf_mcast;
330 u64 rxf_mcast_vlan;
331
332 u64 rxf_bcast_octets;
333 u64 rxf_bcast;
334 u64 rxf_bcast_vlan;
335};
336
337/* RAD Frame Statistics */
338struct bfi_ll_stats_rad {
339 u64 rx_frames;
340 u64 rx_octets;
341 u64 rx_vlan_frames;
342
343 u64 rx_ucast;
344 u64 rx_ucast_octets;
345 u64 rx_ucast_vlan;
346
347 u64 rx_mcast;
348 u64 rx_mcast_octets;
349 u64 rx_mcast_vlan;
350
351 u64 rx_bcast;
352 u64 rx_bcast_octets;
353 u64 rx_bcast_vlan;
354
355 u64 rx_drops;
356};
357
358/* BPC Tx Registers */
359struct bfi_ll_stats_bpc {
360 /* transmit stats */
361 u64 tx_pause[8];
362 u64 tx_zero_pause[8]; /*!< Pause cancellation */
363 /*!<Pause initiation rather than retention */
364 u64 tx_first_pause[8];
365
366 /* receive stats */
367 u64 rx_pause[8];
368 u64 rx_zero_pause[8]; /*!< Pause cancellation */
369 /*!<Pause initiation rather than retention */
370 u64 rx_first_pause[8];
371};
372
373/* MAC Rx Statistics */
374struct bfi_ll_stats_mac {
375 u64 frame_64; /* both rx and tx counter */
376 u64 frame_65_127; /* both rx and tx counter */
377 u64 frame_128_255; /* both rx and tx counter */
378 u64 frame_256_511; /* both rx and tx counter */
379 u64 frame_512_1023; /* both rx and tx counter */
380 u64 frame_1024_1518; /* both rx and tx counter */
381 u64 frame_1519_1522; /* both rx and tx counter */
382
383 /* receive stats */
384 u64 rx_bytes;
385 u64 rx_packets;
386 u64 rx_fcs_error;
387 u64 rx_multicast;
388 u64 rx_broadcast;
389 u64 rx_control_frames;
390 u64 rx_pause;
391 u64 rx_unknown_opcode;
392 u64 rx_alignment_error;
393 u64 rx_frame_length_error;
394 u64 rx_code_error;
395 u64 rx_carrier_sense_error;
396 u64 rx_undersize;
397 u64 rx_oversize;
398 u64 rx_fragments;
399 u64 rx_jabber;
400 u64 rx_drop;
401
402 /* transmit stats */
403 u64 tx_bytes;
404 u64 tx_packets;
405 u64 tx_multicast;
406 u64 tx_broadcast;
407 u64 tx_pause;
408 u64 tx_deferral;
409 u64 tx_excessive_deferral;
410 u64 tx_single_collision;
411 u64 tx_muliple_collision;
412 u64 tx_late_collision;
413 u64 tx_excessive_collision;
414 u64 tx_total_collision;
415 u64 tx_pause_honored;
416 u64 tx_drop;
417 u64 tx_jabber;
418 u64 tx_fcs_error;
419 u64 tx_control_frame;
420 u64 tx_oversize;
421 u64 tx_undersize;
422 u64 tx_fragments;
423};
424
425/* Complete statistics */
426struct bfi_ll_stats {
427 struct bfi_ll_stats_mac mac_stats;
428 struct bfi_ll_stats_bpc bpc_stats;
429 struct bfi_ll_stats_rad rad_stats;
430 struct bfi_ll_stats_fc_rx fc_rx_stats;
431 struct bfi_ll_stats_fc_tx fc_tx_stats;
432 struct bfi_ll_stats_rxf rxf_stats[BFI_LL_RXF_ID_MAX];
433 struct bfi_ll_stats_txf txf_stats[BFI_LL_TXF_ID_MAX];
434};
435
436#pragma pack()
437
438#endif /* __BFI_LL_H__ */
diff --git a/drivers/net/bna/bna.h b/drivers/net/bna/bna.h
new file mode 100644
index 000000000000..6a2b3291c190
--- /dev/null
+++ b/drivers/net/bna/bna.h
@@ -0,0 +1,654 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13#ifndef __BNA_H__
14#define __BNA_H__
15
16#include "bfa_wc.h"
17#include "bfa_ioc.h"
18#include "cna.h"
19#include "bfi_ll.h"
20#include "bna_types.h"
21
22extern u32 bna_dim_vector[][BNA_BIAS_T_MAX];
23extern u32 bna_napi_dim_vector[][BNA_BIAS_T_MAX];
24
25/**
26 *
27 * Macros and constants
28 *
29 */
30
31#define BNA_IOC_TIMER_FREQ 200
32
33/* Log string size */
34#define BNA_MESSAGE_SIZE 256
35
36#define bna_device_timer(_dev) bfa_timer_beat(&((_dev)->timer_mod))
37
38/* MBOX API for PORT, TX, RX */
39#define bna_mbox_qe_fill(_qe, _cmd, _cmd_len, _cbfn, _cbarg) \
40do { \
41 memcpy(&((_qe)->cmd.msg[0]), (_cmd), (_cmd_len)); \
42 (_qe)->cbfn = (_cbfn); \
43 (_qe)->cbarg = (_cbarg); \
44} while (0)
45
46#define bna_is_small_rxq(rcb) ((rcb)->id == 1)
47
48#define BNA_MAC_IS_EQUAL(_mac1, _mac2) \
49 (!memcmp((_mac1), (_mac2), sizeof(mac_t)))
50
51#define BNA_POWER_OF_2(x) (((x) & ((x) - 1)) == 0)
52
53#define BNA_TO_POWER_OF_2(x) \
54do { \
55 int _shift = 0; \
56 while ((x) && (x) != 1) { \
57 (x) >>= 1; \
58 _shift++; \
59 } \
60 (x) <<= _shift; \
61} while (0)
62
63#define BNA_TO_POWER_OF_2_HIGH(x) \
64do { \
65 int n = 1; \
66 while (n < (x)) \
67 n <<= 1; \
68 (x) = n; \
69} while (0)
70
71/*
72 * input : _addr-> os dma addr in host endian format,
73 * output : _bna_dma_addr-> pointer to hw dma addr
74 */
75#define BNA_SET_DMA_ADDR(_addr, _bna_dma_addr) \
76do { \
77 u64 tmp_addr = \
78 cpu_to_be64((u64)(_addr)); \
79 (_bna_dma_addr)->msb = ((struct bna_dma_addr *)&tmp_addr)->msb; \
80 (_bna_dma_addr)->lsb = ((struct bna_dma_addr *)&tmp_addr)->lsb; \
81} while (0)
82
83/*
84 * input : _bna_dma_addr-> pointer to hw dma addr
85 * output : _addr-> os dma addr in host endian format
86 */
87#define BNA_GET_DMA_ADDR(_bna_dma_addr, _addr) \
88do { \
89 (_addr) = ((((u64)ntohl((_bna_dma_addr)->msb))) << 32) \
90 | ((ntohl((_bna_dma_addr)->lsb) & 0xffffffff)); \
91} while (0)
92
93#define containing_rec(addr, type, field) \
94 ((type *)((unsigned char *)(addr) - \
95 (unsigned char *)(&((type *)0)->field)))
96
97#define BNA_TXQ_WI_NEEDED(_vectors) (((_vectors) + 3) >> 2)
98
99/* TxQ element is 64 bytes */
100#define BNA_TXQ_PAGE_INDEX_MAX (PAGE_SIZE >> 6)
101#define BNA_TXQ_PAGE_INDEX_MAX_SHIFT (PAGE_SHIFT - 6)
102
103#define BNA_TXQ_QPGE_PTR_GET(_qe_idx, _qpt_ptr, _qe_ptr, _qe_ptr_range) \
104{ \
105 unsigned int page_index; /* index within a page */ \
106 void *page_addr; \
107 page_index = (_qe_idx) & (BNA_TXQ_PAGE_INDEX_MAX - 1); \
108 (_qe_ptr_range) = (BNA_TXQ_PAGE_INDEX_MAX - page_index); \
109 page_addr = (_qpt_ptr)[((_qe_idx) >> BNA_TXQ_PAGE_INDEX_MAX_SHIFT)];\
110 (_qe_ptr) = &((struct bna_txq_entry *)(page_addr))[page_index]; \
111}
112
113/* RxQ element is 8 bytes */
114#define BNA_RXQ_PAGE_INDEX_MAX (PAGE_SIZE >> 3)
115#define BNA_RXQ_PAGE_INDEX_MAX_SHIFT (PAGE_SHIFT - 3)
116
117#define BNA_RXQ_QPGE_PTR_GET(_qe_idx, _qpt_ptr, _qe_ptr, _qe_ptr_range) \
118{ \
119 unsigned int page_index; /* index within a page */ \
120 void *page_addr; \
121 page_index = (_qe_idx) & (BNA_RXQ_PAGE_INDEX_MAX - 1); \
122 (_qe_ptr_range) = (BNA_RXQ_PAGE_INDEX_MAX - page_index); \
123 page_addr = (_qpt_ptr)[((_qe_idx) >> \
124 BNA_RXQ_PAGE_INDEX_MAX_SHIFT)]; \
125 (_qe_ptr) = &((struct bna_rxq_entry *)(page_addr))[page_index]; \
126}
127
128/* CQ element is 16 bytes */
129#define BNA_CQ_PAGE_INDEX_MAX (PAGE_SIZE >> 4)
130#define BNA_CQ_PAGE_INDEX_MAX_SHIFT (PAGE_SHIFT - 4)
131
132#define BNA_CQ_QPGE_PTR_GET(_qe_idx, _qpt_ptr, _qe_ptr, _qe_ptr_range) \
133{ \
134 unsigned int page_index; /* index within a page */ \
135 void *page_addr; \
136 \
137 page_index = (_qe_idx) & (BNA_CQ_PAGE_INDEX_MAX - 1); \
138 (_qe_ptr_range) = (BNA_CQ_PAGE_INDEX_MAX - page_index); \
139 page_addr = (_qpt_ptr)[((_qe_idx) >> \
140 BNA_CQ_PAGE_INDEX_MAX_SHIFT)]; \
141 (_qe_ptr) = &((struct bna_cq_entry *)(page_addr))[page_index];\
142}
143
144#define BNA_QE_INDX_2_PTR(_cast, _qe_idx, _q_base) \
145 (&((_cast *)(_q_base))[(_qe_idx)])
146
147#define BNA_QE_INDX_RANGE(_qe_idx, _q_depth) ((_q_depth) - (_qe_idx))
148
149#define BNA_QE_INDX_ADD(_qe_idx, _qe_num, _q_depth) \
150 ((_qe_idx) = ((_qe_idx) + (_qe_num)) & ((_q_depth) - 1))
151
152#define BNA_Q_INDEX_CHANGE(_old_idx, _updated_idx, _q_depth) \
153 (((_updated_idx) - (_old_idx)) & ((_q_depth) - 1))
154
155#define BNA_QE_FREE_CNT(_q_ptr, _q_depth) \
156 (((_q_ptr)->consumer_index - (_q_ptr)->producer_index - 1) & \
157 ((_q_depth) - 1))
158
159#define BNA_QE_IN_USE_CNT(_q_ptr, _q_depth) \
160 ((((_q_ptr)->producer_index - (_q_ptr)->consumer_index)) & \
161 (_q_depth - 1))
162
163#define BNA_Q_GET_CI(_q_ptr) ((_q_ptr)->q.consumer_index)
164
165#define BNA_Q_GET_PI(_q_ptr) ((_q_ptr)->q.producer_index)
166
167#define BNA_Q_PI_ADD(_q_ptr, _num) \
168 (_q_ptr)->q.producer_index = \
169 (((_q_ptr)->q.producer_index + (_num)) & \
170 ((_q_ptr)->q.q_depth - 1))
171
172#define BNA_Q_CI_ADD(_q_ptr, _num) \
173 (_q_ptr)->q.consumer_index = \
174 (((_q_ptr)->q.consumer_index + (_num)) \
175 & ((_q_ptr)->q.q_depth - 1))
176
177#define BNA_Q_FREE_COUNT(_q_ptr) \
178 (BNA_QE_FREE_CNT(&((_q_ptr)->q), (_q_ptr)->q.q_depth))
179
180#define BNA_Q_IN_USE_COUNT(_q_ptr) \
181 (BNA_QE_IN_USE_CNT(&(_q_ptr)->q, (_q_ptr)->q.q_depth))
182
183/* These macros build the data portion of the TxQ/RxQ doorbell */
184#define BNA_DOORBELL_Q_PRD_IDX(_pi) (0x80000000 | (_pi))
185#define BNA_DOORBELL_Q_STOP (0x40000000)
186
187/* These macros build the data portion of the IB doorbell */
188#define BNA_DOORBELL_IB_INT_ACK(_timeout, _events) \
189 (0x80000000 | ((_timeout) << 16) | (_events))
190#define BNA_DOORBELL_IB_INT_DISABLE (0x40000000)
191
192/* Set the coalescing timer for the given ib */
193#define bna_ib_coalescing_timer_set(_i_dbell, _cls_timer) \
194 ((_i_dbell)->doorbell_ack = BNA_DOORBELL_IB_INT_ACK((_cls_timer), 0));
195
196/* Acks 'events' # of events for a given ib */
197#define bna_ib_ack(_i_dbell, _events) \
198 (writel(((_i_dbell)->doorbell_ack | (_events)), \
199 (_i_dbell)->doorbell_addr));
200
201#define bna_txq_prod_indx_doorbell(_tcb) \
202 (writel(BNA_DOORBELL_Q_PRD_IDX((_tcb)->producer_index), \
203 (_tcb)->q_dbell));
204
205#define bna_rxq_prod_indx_doorbell(_rcb) \
206 (writel(BNA_DOORBELL_Q_PRD_IDX((_rcb)->producer_index), \
207 (_rcb)->q_dbell));
208
209#define BNA_LARGE_PKT_SIZE 1000
210
211#define BNA_UPDATE_PKT_CNT(_pkt, _len) \
212do { \
213 if ((_len) > BNA_LARGE_PKT_SIZE) { \
214 (_pkt)->large_pkt_cnt++; \
215 } else { \
216 (_pkt)->small_pkt_cnt++; \
217 } \
218} while (0)
219
220#define call_rxf_stop_cbfn(rxf, status) \
221 if ((rxf)->stop_cbfn) { \
222 (*(rxf)->stop_cbfn)((rxf)->stop_cbarg, (status)); \
223 (rxf)->stop_cbfn = NULL; \
224 (rxf)->stop_cbarg = NULL; \
225 }
226
227#define call_rxf_start_cbfn(rxf, status) \
228 if ((rxf)->start_cbfn) { \
229 (*(rxf)->start_cbfn)((rxf)->start_cbarg, (status)); \
230 (rxf)->start_cbfn = NULL; \
231 (rxf)->start_cbarg = NULL; \
232 }
233
234#define call_rxf_cam_fltr_cbfn(rxf, status) \
235 if ((rxf)->cam_fltr_cbfn) { \
236 (*(rxf)->cam_fltr_cbfn)((rxf)->cam_fltr_cbarg, rxf->rx, \
237 (status)); \
238 (rxf)->cam_fltr_cbfn = NULL; \
239 (rxf)->cam_fltr_cbarg = NULL; \
240 }
241
242#define call_rxf_pause_cbfn(rxf, status) \
243 if ((rxf)->oper_state_cbfn) { \
244 (*(rxf)->oper_state_cbfn)((rxf)->oper_state_cbarg, rxf->rx,\
245 (status)); \
246 (rxf)->rxf_flags &= ~BNA_RXF_FL_OPERSTATE_CHANGED; \
247 (rxf)->oper_state_cbfn = NULL; \
248 (rxf)->oper_state_cbarg = NULL; \
249 }
250
251#define call_rxf_resume_cbfn(rxf, status) call_rxf_pause_cbfn(rxf, status)
252
253#define is_xxx_enable(mode, bitmask, xxx) ((bitmask & xxx) && (mode & xxx))
254
255#define is_xxx_disable(mode, bitmask, xxx) ((bitmask & xxx) && !(mode & xxx))
256
257#define xxx_enable(mode, bitmask, xxx) \
258do { \
259 bitmask |= xxx; \
260 mode |= xxx; \
261} while (0)
262
263#define xxx_disable(mode, bitmask, xxx) \
264do { \
265 bitmask |= xxx; \
266 mode &= ~xxx; \
267} while (0)
268
269#define xxx_inactive(mode, bitmask, xxx) \
270do { \
271 bitmask &= ~xxx; \
272 mode &= ~xxx; \
273} while (0)
274
275#define is_promisc_enable(mode, bitmask) \
276 is_xxx_enable(mode, bitmask, BNA_RXMODE_PROMISC)
277
278#define is_promisc_disable(mode, bitmask) \
279 is_xxx_disable(mode, bitmask, BNA_RXMODE_PROMISC)
280
281#define promisc_enable(mode, bitmask) \
282 xxx_enable(mode, bitmask, BNA_RXMODE_PROMISC)
283
284#define promisc_disable(mode, bitmask) \
285 xxx_disable(mode, bitmask, BNA_RXMODE_PROMISC)
286
287#define promisc_inactive(mode, bitmask) \
288 xxx_inactive(mode, bitmask, BNA_RXMODE_PROMISC)
289
290#define is_default_enable(mode, bitmask) \
291 is_xxx_enable(mode, bitmask, BNA_RXMODE_DEFAULT)
292
293#define is_default_disable(mode, bitmask) \
294 is_xxx_disable(mode, bitmask, BNA_RXMODE_DEFAULT)
295
296#define default_enable(mode, bitmask) \
297 xxx_enable(mode, bitmask, BNA_RXMODE_DEFAULT)
298
299#define default_disable(mode, bitmask) \
300 xxx_disable(mode, bitmask, BNA_RXMODE_DEFAULT)
301
302#define default_inactive(mode, bitmask) \
303 xxx_inactive(mode, bitmask, BNA_RXMODE_DEFAULT)
304
305#define is_allmulti_enable(mode, bitmask) \
306 is_xxx_enable(mode, bitmask, BNA_RXMODE_ALLMULTI)
307
308#define is_allmulti_disable(mode, bitmask) \
309 is_xxx_disable(mode, bitmask, BNA_RXMODE_ALLMULTI)
310
311#define allmulti_enable(mode, bitmask) \
312 xxx_enable(mode, bitmask, BNA_RXMODE_ALLMULTI)
313
314#define allmulti_disable(mode, bitmask) \
315 xxx_disable(mode, bitmask, BNA_RXMODE_ALLMULTI)
316
317#define allmulti_inactive(mode, bitmask) \
318 xxx_inactive(mode, bitmask, BNA_RXMODE_ALLMULTI)
319
320#define GET_RXQS(rxp, q0, q1) do { \
321 switch ((rxp)->type) { \
322 case BNA_RXP_SINGLE: \
323 (q0) = rxp->rxq.single.only; \
324 (q1) = NULL; \
325 break; \
326 case BNA_RXP_SLR: \
327 (q0) = rxp->rxq.slr.large; \
328 (q1) = rxp->rxq.slr.small; \
329 break; \
330 case BNA_RXP_HDS: \
331 (q0) = rxp->rxq.hds.data; \
332 (q1) = rxp->rxq.hds.hdr; \
333 break; \
334 } \
335} while (0)
336
337/**
338 *
339 * Function prototypes
340 *
341 */
342
343/**
344 * BNA
345 */
346
347/* Internal APIs */
348void bna_adv_res_req(struct bna_res_info *res_info);
349
350/* APIs for BNAD */
351void bna_res_req(struct bna_res_info *res_info);
352void bna_init(struct bna *bna, struct bnad *bnad,
353 struct bfa_pcidev *pcidev,
354 struct bna_res_info *res_info);
355void bna_uninit(struct bna *bna);
356void bna_stats_get(struct bna *bna);
357void bna_stats_clr(struct bna *bna);
358void bna_get_perm_mac(struct bna *bna, u8 *mac);
359
360/* APIs for Rx */
361int bna_rit_mod_can_satisfy(struct bna_rit_mod *rit_mod, int seg_size);
362
363/* APIs for RxF */
364struct bna_mac *bna_ucam_mod_mac_get(struct bna_ucam_mod *ucam_mod);
365void bna_ucam_mod_mac_put(struct bna_ucam_mod *ucam_mod,
366 struct bna_mac *mac);
367struct bna_mac *bna_mcam_mod_mac_get(struct bna_mcam_mod *mcam_mod);
368void bna_mcam_mod_mac_put(struct bna_mcam_mod *mcam_mod,
369 struct bna_mac *mac);
370struct bna_rit_segment *
371bna_rit_mod_seg_get(struct bna_rit_mod *rit_mod, int seg_size);
372void bna_rit_mod_seg_put(struct bna_rit_mod *rit_mod,
373 struct bna_rit_segment *seg);
374
375/**
376 * DEVICE
377 */
378
379/* Interanl APIs */
380void bna_adv_device_init(struct bna_device *device, struct bna *bna,
381 struct bna_res_info *res_info);
382
383/* APIs for BNA */
384void bna_device_init(struct bna_device *device, struct bna *bna,
385 struct bna_res_info *res_info);
386void bna_device_uninit(struct bna_device *device);
387void bna_device_cb_port_stopped(void *arg, enum bna_cb_status status);
388int bna_device_status_get(struct bna_device *device);
389int bna_device_state_get(struct bna_device *device);
390
391/* APIs for BNAD */
392void bna_device_enable(struct bna_device *device);
393void bna_device_disable(struct bna_device *device,
394 enum bna_cleanup_type type);
395
396/**
397 * MBOX
398 */
399
400/* APIs for DEVICE */
401void bna_mbox_mod_init(struct bna_mbox_mod *mbox_mod, struct bna *bna);
402void bna_mbox_mod_uninit(struct bna_mbox_mod *mbox_mod);
403void bna_mbox_mod_start(struct bna_mbox_mod *mbox_mod);
404void bna_mbox_mod_stop(struct bna_mbox_mod *mbox_mod);
405
406/* APIs for PORT, TX, RX */
407void bna_mbox_handler(struct bna *bna, u32 intr_status);
408void bna_mbox_send(struct bna *bna, struct bna_mbox_qe *mbox_qe);
409
410/**
411 * PORT
412 */
413
414/* APIs for BNA */
415void bna_port_init(struct bna_port *port, struct bna *bna);
416void bna_port_uninit(struct bna_port *port);
417int bna_port_state_get(struct bna_port *port);
418int bna_llport_state_get(struct bna_llport *llport);
419
420/* APIs for DEVICE */
421void bna_port_start(struct bna_port *port);
422void bna_port_stop(struct bna_port *port);
423void bna_port_fail(struct bna_port *port);
424
425/* API for RX */
426int bna_port_mtu_get(struct bna_port *port);
427void bna_llport_admin_up(struct bna_llport *llport);
428void bna_llport_admin_down(struct bna_llport *llport);
429
430/* API for BNAD */
431void bna_port_enable(struct bna_port *port);
432void bna_port_disable(struct bna_port *port, enum bna_cleanup_type type,
433 void (*cbfn)(void *, enum bna_cb_status));
434void bna_port_pause_config(struct bna_port *port,
435 struct bna_pause_config *pause_config,
436 void (*cbfn)(struct bnad *, enum bna_cb_status));
437void bna_port_mtu_set(struct bna_port *port, int mtu,
438 void (*cbfn)(struct bnad *, enum bna_cb_status));
439void bna_port_mac_get(struct bna_port *port, mac_t *mac);
440void bna_port_type_set(struct bna_port *port, enum bna_port_type type);
441void bna_port_linkcbfn_set(struct bna_port *port,
442 void (*linkcbfn)(struct bnad *,
443 enum bna_link_status));
444void bna_port_admin_up(struct bna_port *port);
445void bna_port_admin_down(struct bna_port *port);
446
447/* Callbacks for TX, RX */
448void bna_port_cb_tx_stopped(struct bna_port *port,
449 enum bna_cb_status status);
450void bna_port_cb_rx_stopped(struct bna_port *port,
451 enum bna_cb_status status);
452
453/* Callbacks for MBOX */
454void bna_port_cb_link_up(struct bna_port *port, struct bfi_ll_aen *aen,
455 int status);
456void bna_port_cb_link_down(struct bna_port *port, int status);
457
458/**
459 * IB
460 */
461
462/* APIs for BNA */
463void bna_ib_mod_init(struct bna_ib_mod *ib_mod, struct bna *bna,
464 struct bna_res_info *res_info);
465void bna_ib_mod_uninit(struct bna_ib_mod *ib_mod);
466
467/* APIs for TX, RX */
468struct bna_ib *bna_ib_get(struct bna_ib_mod *ib_mod,
469 enum bna_intr_type intr_type, int vector);
470void bna_ib_put(struct bna_ib_mod *ib_mod, struct bna_ib *ib);
471int bna_ib_reserve_idx(struct bna_ib *ib);
472void bna_ib_release_idx(struct bna_ib *ib, int idx);
473int bna_ib_config(struct bna_ib *ib, struct bna_ib_config *ib_config);
474void bna_ib_start(struct bna_ib *ib);
475void bna_ib_stop(struct bna_ib *ib);
476void bna_ib_fail(struct bna_ib *ib);
477void bna_ib_coalescing_timeo_set(struct bna_ib *ib, u8 coalescing_timeo);
478
479/**
480 * TX MODULE AND TX
481 */
482
483/* Internal APIs */
484void bna_tx_prio_changed(struct bna_tx *tx, int prio);
485
486/* APIs for BNA */
487void bna_tx_mod_init(struct bna_tx_mod *tx_mod, struct bna *bna,
488 struct bna_res_info *res_info);
489void bna_tx_mod_uninit(struct bna_tx_mod *tx_mod);
490int bna_tx_state_get(struct bna_tx *tx);
491
492/* APIs for PORT */
493void bna_tx_mod_start(struct bna_tx_mod *tx_mod, enum bna_tx_type type);
494void bna_tx_mod_stop(struct bna_tx_mod *tx_mod, enum bna_tx_type type);
495void bna_tx_mod_fail(struct bna_tx_mod *tx_mod);
496void bna_tx_mod_prio_changed(struct bna_tx_mod *tx_mod, int prio);
497void bna_tx_mod_cee_link_status(struct bna_tx_mod *tx_mod, int cee_link);
498
499/* APIs for BNAD */
500void bna_tx_res_req(int num_txq, int txq_depth,
501 struct bna_res_info *res_info);
502struct bna_tx *bna_tx_create(struct bna *bna, struct bnad *bnad,
503 struct bna_tx_config *tx_cfg,
504 struct bna_tx_event_cbfn *tx_cbfn,
505 struct bna_res_info *res_info, void *priv);
506void bna_tx_destroy(struct bna_tx *tx);
507void bna_tx_enable(struct bna_tx *tx);
508void bna_tx_disable(struct bna_tx *tx, enum bna_cleanup_type type,
509 void (*cbfn)(void *, struct bna_tx *,
510 enum bna_cb_status));
511enum bna_cb_status
512bna_tx_prio_set(struct bna_tx *tx, int prio,
513 void (*cbfn)(struct bnad *, struct bna_tx *,
514 enum bna_cb_status));
515void bna_tx_coalescing_timeo_set(struct bna_tx *tx, int coalescing_timeo);
516
517/**
518 * RX MODULE, RX, RXF
519 */
520
521/* Internal APIs */
522void rxf_cb_cam_fltr_mbox_cmd(void *arg, int status);
523void rxf_cam_mbox_cmd(struct bna_rxf *rxf, u8 cmd,
524 const struct bna_mac *mac_addr);
525void __rxf_vlan_filter_set(struct bna_rxf *rxf, enum bna_status status);
526void bna_rxf_adv_init(struct bna_rxf *rxf,
527 struct bna_rx *rx,
528 struct bna_rx_config *q_config);
529int rxf_process_packet_filter_ucast(struct bna_rxf *rxf);
530int rxf_process_packet_filter_promisc(struct bna_rxf *rxf);
531int rxf_process_packet_filter_default(struct bna_rxf *rxf);
532int rxf_process_packet_filter_allmulti(struct bna_rxf *rxf);
533int rxf_clear_packet_filter_ucast(struct bna_rxf *rxf);
534int rxf_clear_packet_filter_promisc(struct bna_rxf *rxf);
535int rxf_clear_packet_filter_default(struct bna_rxf *rxf);
536int rxf_clear_packet_filter_allmulti(struct bna_rxf *rxf);
537void rxf_reset_packet_filter_ucast(struct bna_rxf *rxf);
538void rxf_reset_packet_filter_promisc(struct bna_rxf *rxf);
539void rxf_reset_packet_filter_default(struct bna_rxf *rxf);
540void rxf_reset_packet_filter_allmulti(struct bna_rxf *rxf);
541
542/* APIs for BNA */
543void bna_rx_mod_init(struct bna_rx_mod *rx_mod, struct bna *bna,
544 struct bna_res_info *res_info);
545void bna_rx_mod_uninit(struct bna_rx_mod *rx_mod);
546int bna_rx_state_get(struct bna_rx *rx);
547int bna_rxf_state_get(struct bna_rxf *rxf);
548
549/* APIs for PORT */
550void bna_rx_mod_start(struct bna_rx_mod *rx_mod, enum bna_rx_type type);
551void bna_rx_mod_stop(struct bna_rx_mod *rx_mod, enum bna_rx_type type);
552void bna_rx_mod_fail(struct bna_rx_mod *rx_mod);
553
554/* APIs for BNAD */
555void bna_rx_res_req(struct bna_rx_config *rx_config,
556 struct bna_res_info *res_info);
557struct bna_rx *bna_rx_create(struct bna *bna, struct bnad *bnad,
558 struct bna_rx_config *rx_cfg,
559 struct bna_rx_event_cbfn *rx_cbfn,
560 struct bna_res_info *res_info, void *priv);
561void bna_rx_destroy(struct bna_rx *rx);
562void bna_rx_enable(struct bna_rx *rx);
563void bna_rx_disable(struct bna_rx *rx, enum bna_cleanup_type type,
564 void (*cbfn)(void *, struct bna_rx *,
565 enum bna_cb_status));
566void bna_rx_coalescing_timeo_set(struct bna_rx *rx, int coalescing_timeo);
567void bna_rx_dim_reconfig(struct bna *bna, u32 vector[][BNA_BIAS_T_MAX]);
568void bna_rx_dim_update(struct bna_ccb *ccb);
569enum bna_cb_status
570bna_rx_ucast_set(struct bna_rx *rx, u8 *ucmac,
571 void (*cbfn)(struct bnad *, struct bna_rx *,
572 enum bna_cb_status));
573enum bna_cb_status
574bna_rx_ucast_add(struct bna_rx *rx, u8* ucmac,
575 void (*cbfn)(struct bnad *, struct bna_rx *,
576 enum bna_cb_status));
577enum bna_cb_status
578bna_rx_ucast_del(struct bna_rx *rx, u8 *ucmac,
579 void (*cbfn)(struct bnad *, struct bna_rx *,
580 enum bna_cb_status));
581enum bna_cb_status
582bna_rx_mcast_add(struct bna_rx *rx, u8 *mcmac,
583 void (*cbfn)(struct bnad *, struct bna_rx *,
584 enum bna_cb_status));
585enum bna_cb_status
586bna_rx_mcast_del(struct bna_rx *rx, u8 *mcmac,
587 void (*cbfn)(struct bnad *, struct bna_rx *,
588 enum bna_cb_status));
589enum bna_cb_status
590bna_rx_mcast_listset(struct bna_rx *rx, int count, u8 *mcmac,
591 void (*cbfn)(struct bnad *, struct bna_rx *,
592 enum bna_cb_status));
593void bna_rx_mcast_delall(struct bna_rx *rx,
594 void (*cbfn)(struct bnad *, struct bna_rx *,
595 enum bna_cb_status));
596enum bna_cb_status
597bna_rx_mode_set(struct bna_rx *rx, enum bna_rxmode rxmode,
598 enum bna_rxmode bitmask,
599 void (*cbfn)(struct bnad *, struct bna_rx *,
600 enum bna_cb_status));
601void bna_rx_vlan_add(struct bna_rx *rx, int vlan_id);
602void bna_rx_vlan_del(struct bna_rx *rx, int vlan_id);
603void bna_rx_vlanfilter_enable(struct bna_rx *rx);
604void bna_rx_vlanfilter_disable(struct bna_rx *rx);
605void bna_rx_rss_enable(struct bna_rx *rx);
606void bna_rx_rss_disable(struct bna_rx *rx);
607void bna_rx_rss_reconfig(struct bna_rx *rx, struct bna_rxf_rss *rss_config);
608void bna_rx_rss_rit_set(struct bna_rx *rx, unsigned int *vectors,
609 int nvectors);
610void bna_rx_hds_enable(struct bna_rx *rx, struct bna_rxf_hds *hds_config,
611 void (*cbfn)(struct bnad *, struct bna_rx *,
612 enum bna_cb_status));
613void bna_rx_hds_disable(struct bna_rx *rx,
614 void (*cbfn)(struct bnad *, struct bna_rx *,
615 enum bna_cb_status));
616void bna_rx_receive_pause(struct bna_rx *rx,
617 void (*cbfn)(struct bnad *, struct bna_rx *,
618 enum bna_cb_status));
619void bna_rx_receive_resume(struct bna_rx *rx,
620 void (*cbfn)(struct bnad *, struct bna_rx *,
621 enum bna_cb_status));
622
623/* RxF APIs for RX */
624void bna_rxf_start(struct bna_rxf *rxf);
625void bna_rxf_stop(struct bna_rxf *rxf);
626void bna_rxf_fail(struct bna_rxf *rxf);
627void bna_rxf_init(struct bna_rxf *rxf, struct bna_rx *rx,
628 struct bna_rx_config *q_config);
629void bna_rxf_uninit(struct bna_rxf *rxf);
630
631/* Callback from RXF to RX */
632void bna_rx_cb_rxf_stopped(struct bna_rx *rx, enum bna_cb_status);
633void bna_rx_cb_rxf_started(struct bna_rx *rx, enum bna_cb_status);
634
635/**
636 * BNAD
637 */
638
639/* Callbacks for BNA */
640void bnad_cb_stats_get(struct bnad *bnad, enum bna_cb_status status,
641 struct bna_stats *stats);
642void bnad_cb_stats_clr(struct bnad *bnad);
643
644/* Callbacks for DEVICE */
645void bnad_cb_device_enabled(struct bnad *bnad, enum bna_cb_status status);
646void bnad_cb_device_disabled(struct bnad *bnad, enum bna_cb_status status);
647void bnad_cb_device_enable_mbox_intr(struct bnad *bnad);
648void bnad_cb_device_disable_mbox_intr(struct bnad *bnad);
649
650/* Callbacks for port */
651void bnad_cb_port_link_status(struct bnad *bnad,
652 enum bna_link_status status);
653
654#endif /* __BNA_H__ */
diff --git a/drivers/net/bna/bna_ctrl.c b/drivers/net/bna/bna_ctrl.c
new file mode 100644
index 000000000000..9d41ebf41cf4
--- /dev/null
+++ b/drivers/net/bna/bna_ctrl.c
@@ -0,0 +1,3626 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18#include "bna.h"
19#include "bfa_sm.h"
20#include "bfa_wc.h"
21
22/**
23 * MBOX
24 */
25static int
26bna_is_aen(u8 msg_id)
27{
28 return (msg_id == BFI_LL_I2H_LINK_DOWN_AEN ||
29 msg_id == BFI_LL_I2H_LINK_UP_AEN);
30}
31
32static void
33bna_mbox_aen_callback(struct bna *bna, struct bfi_mbmsg *msg)
34{
35 struct bfi_ll_aen *aen = (struct bfi_ll_aen *)(msg);
36
37 switch (aen->mh.msg_id) {
38 case BFI_LL_I2H_LINK_UP_AEN:
39 bna_port_cb_link_up(&bna->port, aen, aen->reason);
40 break;
41 case BFI_LL_I2H_LINK_DOWN_AEN:
42 bna_port_cb_link_down(&bna->port, aen->reason);
43 break;
44 default:
45 break;
46 }
47}
48
49static void
50bna_ll_isr(void *llarg, struct bfi_mbmsg *msg)
51{
52 struct bna *bna = (struct bna *)(llarg);
53 struct bfi_ll_rsp *mb_rsp = (struct bfi_ll_rsp *)(msg);
54 struct bfi_mhdr *cmd_h, *rsp_h;
55 struct bna_mbox_qe *mb_qe = NULL;
56 int to_post = 0;
57 u8 aen = 0;
58 char message[BNA_MESSAGE_SIZE];
59
60 aen = bna_is_aen(mb_rsp->mh.msg_id);
61
62 if (!aen) {
63 mb_qe = bfa_q_first(&bna->mbox_mod.posted_q);
64 cmd_h = (struct bfi_mhdr *)(&mb_qe->cmd.msg[0]);
65 rsp_h = (struct bfi_mhdr *)(&mb_rsp->mh);
66
67 if ((BFA_I2HM(cmd_h->msg_id) == rsp_h->msg_id) &&
68 (cmd_h->mtag.i2htok == rsp_h->mtag.i2htok)) {
69 /* Remove the request from posted_q, update state */
70 list_del(&mb_qe->qe);
71 bna->mbox_mod.msg_pending--;
72 if (list_empty(&bna->mbox_mod.posted_q))
73 bna->mbox_mod.state = BNA_MBOX_FREE;
74 else
75 to_post = 1;
76
77 /* Dispatch the cbfn */
78 if (mb_qe->cbfn)
79 mb_qe->cbfn(mb_qe->cbarg, mb_rsp->error);
80
81 /* Post the next entry, if needed */
82 if (to_post) {
83 mb_qe = bfa_q_first(&bna->mbox_mod.posted_q);
84 bfa_ioc_mbox_queue(&bna->device.ioc,
85 &mb_qe->cmd);
86 }
87 } else {
88 snprintf(message, BNA_MESSAGE_SIZE,
89 "No matching rsp for [%d:%d:%d]\n",
90 mb_rsp->mh.msg_class, mb_rsp->mh.msg_id,
91 mb_rsp->mh.mtag.i2htok);
92 pr_info("%s", message);
93 }
94
95 } else
96 bna_mbox_aen_callback(bna, msg);
97}
98
99void
100bna_err_handler(struct bna *bna, u32 intr_status)
101{
102 u32 init_halt;
103
104 if (intr_status & __HALT_STATUS_BITS) {
105 init_halt = readl(bna->device.ioc.ioc_regs.ll_halt);
106 init_halt &= ~__FW_INIT_HALT_P;
107 writel(init_halt, bna->device.ioc.ioc_regs.ll_halt);
108 }
109
110 bfa_ioc_error_isr(&bna->device.ioc);
111}
112
113void
114bna_mbox_handler(struct bna *bna, u32 intr_status)
115{
116 if (BNA_IS_ERR_INTR(intr_status)) {
117 bna_err_handler(bna, intr_status);
118 return;
119 }
120 if (BNA_IS_MBOX_INTR(intr_status))
121 bfa_ioc_mbox_isr(&bna->device.ioc);
122}
123
124void
125bna_mbox_send(struct bna *bna, struct bna_mbox_qe *mbox_qe)
126{
127 struct bfi_mhdr *mh;
128
129 mh = (struct bfi_mhdr *)(&mbox_qe->cmd.msg[0]);
130
131 mh->mtag.i2htok = htons(bna->mbox_mod.msg_ctr);
132 bna->mbox_mod.msg_ctr++;
133 bna->mbox_mod.msg_pending++;
134 if (bna->mbox_mod.state == BNA_MBOX_FREE) {
135 list_add_tail(&mbox_qe->qe, &bna->mbox_mod.posted_q);
136 bfa_ioc_mbox_queue(&bna->device.ioc, &mbox_qe->cmd);
137 bna->mbox_mod.state = BNA_MBOX_POSTED;
138 } else {
139 list_add_tail(&mbox_qe->qe, &bna->mbox_mod.posted_q);
140 }
141}
142
143void
144bna_mbox_flush_q(struct bna *bna, struct list_head *q)
145{
146 struct bna_mbox_qe *mb_qe = NULL;
147 struct bfi_mhdr *cmd_h;
148 struct list_head *mb_q;
149 void (*cbfn)(void *arg, int status);
150 void *cbarg;
151
152 mb_q = &bna->mbox_mod.posted_q;
153
154 while (!list_empty(mb_q)) {
155 bfa_q_deq(mb_q, &mb_qe);
156 cbfn = mb_qe->cbfn;
157 cbarg = mb_qe->cbarg;
158 bfa_q_qe_init(mb_qe);
159 bna->mbox_mod.msg_pending--;
160
161 cmd_h = (struct bfi_mhdr *)(&mb_qe->cmd.msg[0]);
162 if (cbfn)
163 cbfn(cbarg, BNA_CB_NOT_EXEC);
164 }
165
166 bna->mbox_mod.state = BNA_MBOX_FREE;
167}
168
169void
170bna_mbox_mod_start(struct bna_mbox_mod *mbox_mod)
171{
172}
173
174void
175bna_mbox_mod_stop(struct bna_mbox_mod *mbox_mod)
176{
177 bna_mbox_flush_q(mbox_mod->bna, &mbox_mod->posted_q);
178}
179
180void
181bna_mbox_mod_init(struct bna_mbox_mod *mbox_mod, struct bna *bna)
182{
183 bfa_ioc_mbox_regisr(&bna->device.ioc, BFI_MC_LL, bna_ll_isr, bna);
184 mbox_mod->state = BNA_MBOX_FREE;
185 mbox_mod->msg_ctr = mbox_mod->msg_pending = 0;
186 INIT_LIST_HEAD(&mbox_mod->posted_q);
187 mbox_mod->bna = bna;
188}
189
190void
191bna_mbox_mod_uninit(struct bna_mbox_mod *mbox_mod)
192{
193 mbox_mod->bna = NULL;
194}
195
196/**
197 * LLPORT
198 */
199#define call_llport_stop_cbfn(llport, status)\
200do {\
201 if ((llport)->stop_cbfn)\
202 (llport)->stop_cbfn(&(llport)->bna->port, status);\
203 (llport)->stop_cbfn = NULL;\
204} while (0)
205
206static void bna_fw_llport_up(struct bna_llport *llport);
207static void bna_fw_cb_llport_up(void *arg, int status);
208static void bna_fw_llport_down(struct bna_llport *llport);
209static void bna_fw_cb_llport_down(void *arg, int status);
210static void bna_llport_start(struct bna_llport *llport);
211static void bna_llport_stop(struct bna_llport *llport);
212static void bna_llport_fail(struct bna_llport *llport);
213
214enum bna_llport_event {
215 LLPORT_E_START = 1,
216 LLPORT_E_STOP = 2,
217 LLPORT_E_FAIL = 3,
218 LLPORT_E_UP = 4,
219 LLPORT_E_DOWN = 5,
220 LLPORT_E_FWRESP_UP = 6,
221 LLPORT_E_FWRESP_DOWN = 7
222};
223
224enum bna_llport_state {
225 BNA_LLPORT_STOPPED = 1,
226 BNA_LLPORT_DOWN = 2,
227 BNA_LLPORT_UP_RESP_WAIT = 3,
228 BNA_LLPORT_DOWN_RESP_WAIT = 4,
229 BNA_LLPORT_UP = 5,
230 BNA_LLPORT_LAST_RESP_WAIT = 6
231};
232
233bfa_fsm_state_decl(bna_llport, stopped, struct bna_llport,
234 enum bna_llport_event);
235bfa_fsm_state_decl(bna_llport, down, struct bna_llport,
236 enum bna_llport_event);
237bfa_fsm_state_decl(bna_llport, up_resp_wait, struct bna_llport,
238 enum bna_llport_event);
239bfa_fsm_state_decl(bna_llport, down_resp_wait, struct bna_llport,
240 enum bna_llport_event);
241bfa_fsm_state_decl(bna_llport, up, struct bna_llport,
242 enum bna_llport_event);
243bfa_fsm_state_decl(bna_llport, last_resp_wait, struct bna_llport,
244 enum bna_llport_event);
245
246static struct bfa_sm_table llport_sm_table[] = {
247 {BFA_SM(bna_llport_sm_stopped), BNA_LLPORT_STOPPED},
248 {BFA_SM(bna_llport_sm_down), BNA_LLPORT_DOWN},
249 {BFA_SM(bna_llport_sm_up_resp_wait), BNA_LLPORT_UP_RESP_WAIT},
250 {BFA_SM(bna_llport_sm_down_resp_wait), BNA_LLPORT_DOWN_RESP_WAIT},
251 {BFA_SM(bna_llport_sm_up), BNA_LLPORT_UP},
252 {BFA_SM(bna_llport_sm_last_resp_wait), BNA_LLPORT_LAST_RESP_WAIT}
253};
254
255static void
256bna_llport_sm_stopped_entry(struct bna_llport *llport)
257{
258 llport->bna->port.link_cbfn((llport)->bna->bnad, BNA_LINK_DOWN);
259 call_llport_stop_cbfn(llport, BNA_CB_SUCCESS);
260}
261
262static void
263bna_llport_sm_stopped(struct bna_llport *llport,
264 enum bna_llport_event event)
265{
266 switch (event) {
267 case LLPORT_E_START:
268 bfa_fsm_set_state(llport, bna_llport_sm_down);
269 break;
270
271 case LLPORT_E_STOP:
272 call_llport_stop_cbfn(llport, BNA_CB_SUCCESS);
273 break;
274
275 case LLPORT_E_FAIL:
276 break;
277
278 case LLPORT_E_DOWN:
279 /* This event is received due to Rx objects failing */
280 /* No-op */
281 break;
282
283 case LLPORT_E_FWRESP_UP:
284 case LLPORT_E_FWRESP_DOWN:
285 /**
286 * These events are received due to flushing of mbox when
287 * device fails
288 */
289 /* No-op */
290 break;
291
292 default:
293 bfa_sm_fault(llport->bna, event);
294 }
295}
296
297static void
298bna_llport_sm_down_entry(struct bna_llport *llport)
299{
300 bnad_cb_port_link_status((llport)->bna->bnad, BNA_LINK_DOWN);
301}
302
303static void
304bna_llport_sm_down(struct bna_llport *llport,
305 enum bna_llport_event event)
306{
307 switch (event) {
308 case LLPORT_E_STOP:
309 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
310 break;
311
312 case LLPORT_E_FAIL:
313 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
314 break;
315
316 case LLPORT_E_UP:
317 bfa_fsm_set_state(llport, bna_llport_sm_up_resp_wait);
318 bna_fw_llport_up(llport);
319 break;
320
321 default:
322 bfa_sm_fault(llport->bna, event);
323 }
324}
325
326static void
327bna_llport_sm_up_resp_wait_entry(struct bna_llport *llport)
328{
329 /**
330 * NOTE: Do not call bna_fw_llport_up() here. That will over step
331 * mbox due to down_resp_wait -> up_resp_wait transition on event
332 * LLPORT_E_UP
333 */
334}
335
336static void
337bna_llport_sm_up_resp_wait(struct bna_llport *llport,
338 enum bna_llport_event event)
339{
340 switch (event) {
341 case LLPORT_E_STOP:
342 bfa_fsm_set_state(llport, bna_llport_sm_last_resp_wait);
343 break;
344
345 case LLPORT_E_FAIL:
346 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
347 break;
348
349 case LLPORT_E_DOWN:
350 bfa_fsm_set_state(llport, bna_llport_sm_down_resp_wait);
351 break;
352
353 case LLPORT_E_FWRESP_UP:
354 bfa_fsm_set_state(llport, bna_llport_sm_up);
355 break;
356
357 case LLPORT_E_FWRESP_DOWN:
358 /* down_resp_wait -> up_resp_wait transition on LLPORT_E_UP */
359 bna_fw_llport_up(llport);
360 break;
361
362 default:
363 bfa_sm_fault(llport->bna, event);
364 }
365}
366
367static void
368bna_llport_sm_down_resp_wait_entry(struct bna_llport *llport)
369{
370 /**
371 * NOTE: Do not call bna_fw_llport_down() here. That will over step
372 * mbox due to up_resp_wait -> down_resp_wait transition on event
373 * LLPORT_E_DOWN
374 */
375}
376
377static void
378bna_llport_sm_down_resp_wait(struct bna_llport *llport,
379 enum bna_llport_event event)
380{
381 switch (event) {
382 case LLPORT_E_STOP:
383 bfa_fsm_set_state(llport, bna_llport_sm_last_resp_wait);
384 break;
385
386 case LLPORT_E_FAIL:
387 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
388 break;
389
390 case LLPORT_E_UP:
391 bfa_fsm_set_state(llport, bna_llport_sm_up_resp_wait);
392 break;
393
394 case LLPORT_E_FWRESP_UP:
395 /* up_resp_wait->down_resp_wait transition on LLPORT_E_DOWN */
396 bna_fw_llport_down(llport);
397 break;
398
399 case LLPORT_E_FWRESP_DOWN:
400 bfa_fsm_set_state(llport, bna_llport_sm_down);
401 break;
402
403 default:
404 bfa_sm_fault(llport->bna, event);
405 }
406}
407
408static void
409bna_llport_sm_up_entry(struct bna_llport *llport)
410{
411}
412
413static void
414bna_llport_sm_up(struct bna_llport *llport,
415 enum bna_llport_event event)
416{
417 switch (event) {
418 case LLPORT_E_STOP:
419 bfa_fsm_set_state(llport, bna_llport_sm_last_resp_wait);
420 bna_fw_llport_down(llport);
421 break;
422
423 case LLPORT_E_FAIL:
424 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
425 break;
426
427 case LLPORT_E_DOWN:
428 bfa_fsm_set_state(llport, bna_llport_sm_down_resp_wait);
429 bna_fw_llport_down(llport);
430 break;
431
432 default:
433 bfa_sm_fault(llport->bna, event);
434 }
435}
436
437static void
438bna_llport_sm_last_resp_wait_entry(struct bna_llport *llport)
439{
440}
441
442static void
443bna_llport_sm_last_resp_wait(struct bna_llport *llport,
444 enum bna_llport_event event)
445{
446 switch (event) {
447 case LLPORT_E_FAIL:
448 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
449 break;
450
451 case LLPORT_E_DOWN:
452 /**
453 * This event is received due to Rx objects stopping in
454 * parallel to llport
455 */
456 /* No-op */
457 break;
458
459 case LLPORT_E_FWRESP_UP:
460 /* up_resp_wait->last_resp_wait transition on LLPORT_T_STOP */
461 bna_fw_llport_down(llport);
462 break;
463
464 case LLPORT_E_FWRESP_DOWN:
465 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
466 break;
467
468 default:
469 bfa_sm_fault(llport->bna, event);
470 }
471}
472
473static void
474bna_fw_llport_admin_up(struct bna_llport *llport)
475{
476 struct bfi_ll_port_admin_req ll_req;
477
478 memset(&ll_req, 0, sizeof(ll_req));
479 ll_req.mh.msg_class = BFI_MC_LL;
480 ll_req.mh.msg_id = BFI_LL_H2I_PORT_ADMIN_REQ;
481 ll_req.mh.mtag.h2i.lpu_id = 0;
482
483 ll_req.up = BNA_STATUS_T_ENABLED;
484
485 bna_mbox_qe_fill(&llport->mbox_qe, &ll_req, sizeof(ll_req),
486 bna_fw_cb_llport_up, llport);
487
488 bna_mbox_send(llport->bna, &llport->mbox_qe);
489}
490
491static void
492bna_fw_llport_up(struct bna_llport *llport)
493{
494 if (llport->type == BNA_PORT_T_REGULAR)
495 bna_fw_llport_admin_up(llport);
496}
497
498static void
499bna_fw_cb_llport_up(void *arg, int status)
500{
501 struct bna_llport *llport = (struct bna_llport *)arg;
502
503 bfa_q_qe_init(&llport->mbox_qe.qe);
504 bfa_fsm_send_event(llport, LLPORT_E_FWRESP_UP);
505}
506
507static void
508bna_fw_llport_admin_down(struct bna_llport *llport)
509{
510 struct bfi_ll_port_admin_req ll_req;
511
512 memset(&ll_req, 0, sizeof(ll_req));
513 ll_req.mh.msg_class = BFI_MC_LL;
514 ll_req.mh.msg_id = BFI_LL_H2I_PORT_ADMIN_REQ;
515 ll_req.mh.mtag.h2i.lpu_id = 0;
516
517 ll_req.up = BNA_STATUS_T_DISABLED;
518
519 bna_mbox_qe_fill(&llport->mbox_qe, &ll_req, sizeof(ll_req),
520 bna_fw_cb_llport_down, llport);
521
522 bna_mbox_send(llport->bna, &llport->mbox_qe);
523}
524
525static void
526bna_fw_llport_down(struct bna_llport *llport)
527{
528 if (llport->type == BNA_PORT_T_REGULAR)
529 bna_fw_llport_admin_down(llport);
530}
531
532static void
533bna_fw_cb_llport_down(void *arg, int status)
534{
535 struct bna_llport *llport = (struct bna_llport *)arg;
536
537 bfa_q_qe_init(&llport->mbox_qe.qe);
538 bfa_fsm_send_event(llport, LLPORT_E_FWRESP_DOWN);
539}
540
541void
542bna_port_cb_llport_stopped(struct bna_port *port,
543 enum bna_cb_status status)
544{
545 bfa_wc_down(&port->chld_stop_wc);
546}
547
548static void
549bna_llport_init(struct bna_llport *llport, struct bna *bna)
550{
551 llport->flags |= BNA_LLPORT_F_ENABLED;
552 llport->type = BNA_PORT_T_REGULAR;
553 llport->bna = bna;
554
555 llport->link_status = BNA_LINK_DOWN;
556
557 llport->admin_up_count = 0;
558
559 llport->stop_cbfn = NULL;
560
561 bfa_q_qe_init(&llport->mbox_qe.qe);
562
563 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
564}
565
566static void
567bna_llport_uninit(struct bna_llport *llport)
568{
569 llport->flags &= ~BNA_LLPORT_F_ENABLED;
570
571 llport->bna = NULL;
572}
573
574static void
575bna_llport_start(struct bna_llport *llport)
576{
577 bfa_fsm_send_event(llport, LLPORT_E_START);
578}
579
580static void
581bna_llport_stop(struct bna_llport *llport)
582{
583 llport->stop_cbfn = bna_port_cb_llport_stopped;
584
585 bfa_fsm_send_event(llport, LLPORT_E_STOP);
586}
587
588static void
589bna_llport_fail(struct bna_llport *llport)
590{
591 bfa_fsm_send_event(llport, LLPORT_E_FAIL);
592}
593
594int
595bna_llport_state_get(struct bna_llport *llport)
596{
597 return bfa_sm_to_state(llport_sm_table, llport->fsm);
598}
599
600void
601bna_llport_admin_up(struct bna_llport *llport)
602{
603 llport->admin_up_count++;
604
605 if (llport->admin_up_count == 1) {
606 llport->flags |= BNA_LLPORT_F_RX_ENABLED;
607 if (llport->flags & BNA_LLPORT_F_ENABLED)
608 bfa_fsm_send_event(llport, LLPORT_E_UP);
609 }
610}
611
612void
613bna_llport_admin_down(struct bna_llport *llport)
614{
615 llport->admin_up_count--;
616
617 if (llport->admin_up_count == 0) {
618 llport->flags &= ~BNA_LLPORT_F_RX_ENABLED;
619 if (llport->flags & BNA_LLPORT_F_ENABLED)
620 bfa_fsm_send_event(llport, LLPORT_E_DOWN);
621 }
622}
623
624/**
625 * PORT
626 */
627#define bna_port_chld_start(port)\
628do {\
629 enum bna_tx_type tx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
630 BNA_TX_T_REGULAR : BNA_TX_T_LOOPBACK;\
631 enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
632 BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
633 bna_llport_start(&(port)->llport);\
634 bna_tx_mod_start(&(port)->bna->tx_mod, tx_type);\
635 bna_rx_mod_start(&(port)->bna->rx_mod, rx_type);\
636} while (0)
637
638#define bna_port_chld_stop(port)\
639do {\
640 enum bna_tx_type tx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
641 BNA_TX_T_REGULAR : BNA_TX_T_LOOPBACK;\
642 enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
643 BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
644 bfa_wc_up(&(port)->chld_stop_wc);\
645 bfa_wc_up(&(port)->chld_stop_wc);\
646 bfa_wc_up(&(port)->chld_stop_wc);\
647 bna_llport_stop(&(port)->llport);\
648 bna_tx_mod_stop(&(port)->bna->tx_mod, tx_type);\
649 bna_rx_mod_stop(&(port)->bna->rx_mod, rx_type);\
650} while (0)
651
652#define bna_port_chld_fail(port)\
653do {\
654 bna_llport_fail(&(port)->llport);\
655 bna_tx_mod_fail(&(port)->bna->tx_mod);\
656 bna_rx_mod_fail(&(port)->bna->rx_mod);\
657} while (0)
658
659#define bna_port_rx_start(port)\
660do {\
661 enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
662 BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
663 bna_rx_mod_start(&(port)->bna->rx_mod, rx_type);\
664} while (0)
665
666#define bna_port_rx_stop(port)\
667do {\
668 enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
669 BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
670 bfa_wc_up(&(port)->chld_stop_wc);\
671 bna_rx_mod_stop(&(port)->bna->rx_mod, rx_type);\
672} while (0)
673
674#define call_port_stop_cbfn(port, status)\
675do {\
676 if ((port)->stop_cbfn)\
677 (port)->stop_cbfn((port)->stop_cbarg, status);\
678 (port)->stop_cbfn = NULL;\
679 (port)->stop_cbarg = NULL;\
680} while (0)
681
682#define call_port_pause_cbfn(port, status)\
683do {\
684 if ((port)->pause_cbfn)\
685 (port)->pause_cbfn((port)->bna->bnad, status);\
686 (port)->pause_cbfn = NULL;\
687} while (0)
688
689#define call_port_mtu_cbfn(port, status)\
690do {\
691 if ((port)->mtu_cbfn)\
692 (port)->mtu_cbfn((port)->bna->bnad, status);\
693 (port)->mtu_cbfn = NULL;\
694} while (0)
695
696static void bna_fw_pause_set(struct bna_port *port);
697static void bna_fw_cb_pause_set(void *arg, int status);
698static void bna_fw_mtu_set(struct bna_port *port);
699static void bna_fw_cb_mtu_set(void *arg, int status);
700
701enum bna_port_event {
702 PORT_E_START = 1,
703 PORT_E_STOP = 2,
704 PORT_E_FAIL = 3,
705 PORT_E_PAUSE_CFG = 4,
706 PORT_E_MTU_CFG = 5,
707 PORT_E_CHLD_STOPPED = 6,
708 PORT_E_FWRESP_PAUSE = 7,
709 PORT_E_FWRESP_MTU = 8
710};
711
712enum bna_port_state {
713 BNA_PORT_STOPPED = 1,
714 BNA_PORT_MTU_INIT_WAIT = 2,
715 BNA_PORT_PAUSE_INIT_WAIT = 3,
716 BNA_PORT_LAST_RESP_WAIT = 4,
717 BNA_PORT_STARTED = 5,
718 BNA_PORT_PAUSE_CFG_WAIT = 6,
719 BNA_PORT_RX_STOP_WAIT = 7,
720 BNA_PORT_MTU_CFG_WAIT = 8,
721 BNA_PORT_CHLD_STOP_WAIT = 9
722};
723
724bfa_fsm_state_decl(bna_port, stopped, struct bna_port,
725 enum bna_port_event);
726bfa_fsm_state_decl(bna_port, mtu_init_wait, struct bna_port,
727 enum bna_port_event);
728bfa_fsm_state_decl(bna_port, pause_init_wait, struct bna_port,
729 enum bna_port_event);
730bfa_fsm_state_decl(bna_port, last_resp_wait, struct bna_port,
731 enum bna_port_event);
732bfa_fsm_state_decl(bna_port, started, struct bna_port,
733 enum bna_port_event);
734bfa_fsm_state_decl(bna_port, pause_cfg_wait, struct bna_port,
735 enum bna_port_event);
736bfa_fsm_state_decl(bna_port, rx_stop_wait, struct bna_port,
737 enum bna_port_event);
738bfa_fsm_state_decl(bna_port, mtu_cfg_wait, struct bna_port,
739 enum bna_port_event);
740bfa_fsm_state_decl(bna_port, chld_stop_wait, struct bna_port,
741 enum bna_port_event);
742
743static struct bfa_sm_table port_sm_table[] = {
744 {BFA_SM(bna_port_sm_stopped), BNA_PORT_STOPPED},
745 {BFA_SM(bna_port_sm_mtu_init_wait), BNA_PORT_MTU_INIT_WAIT},
746 {BFA_SM(bna_port_sm_pause_init_wait), BNA_PORT_PAUSE_INIT_WAIT},
747 {BFA_SM(bna_port_sm_last_resp_wait), BNA_PORT_LAST_RESP_WAIT},
748 {BFA_SM(bna_port_sm_started), BNA_PORT_STARTED},
749 {BFA_SM(bna_port_sm_pause_cfg_wait), BNA_PORT_PAUSE_CFG_WAIT},
750 {BFA_SM(bna_port_sm_rx_stop_wait), BNA_PORT_RX_STOP_WAIT},
751 {BFA_SM(bna_port_sm_mtu_cfg_wait), BNA_PORT_MTU_CFG_WAIT},
752 {BFA_SM(bna_port_sm_chld_stop_wait), BNA_PORT_CHLD_STOP_WAIT}
753};
754
755static void
756bna_port_sm_stopped_entry(struct bna_port *port)
757{
758 call_port_pause_cbfn(port, BNA_CB_SUCCESS);
759 call_port_mtu_cbfn(port, BNA_CB_SUCCESS);
760 call_port_stop_cbfn(port, BNA_CB_SUCCESS);
761}
762
763static void
764bna_port_sm_stopped(struct bna_port *port, enum bna_port_event event)
765{
766 switch (event) {
767 case PORT_E_START:
768 bfa_fsm_set_state(port, bna_port_sm_mtu_init_wait);
769 break;
770
771 case PORT_E_STOP:
772 call_port_stop_cbfn(port, BNA_CB_SUCCESS);
773 break;
774
775 case PORT_E_FAIL:
776 /* No-op */
777 break;
778
779 case PORT_E_PAUSE_CFG:
780 call_port_pause_cbfn(port, BNA_CB_SUCCESS);
781 break;
782
783 case PORT_E_MTU_CFG:
784 call_port_mtu_cbfn(port, BNA_CB_SUCCESS);
785 break;
786
787 case PORT_E_CHLD_STOPPED:
788 /**
789 * This event is received due to LLPort, Tx and Rx objects
790 * failing
791 */
792 /* No-op */
793 break;
794
795 case PORT_E_FWRESP_PAUSE:
796 case PORT_E_FWRESP_MTU:
797 /**
798 * These events are received due to flushing of mbox when
799 * device fails
800 */
801 /* No-op */
802 break;
803
804 default:
805 bfa_sm_fault(port->bna, event);
806 }
807}
808
809static void
810bna_port_sm_mtu_init_wait_entry(struct bna_port *port)
811{
812 bna_fw_mtu_set(port);
813}
814
815static void
816bna_port_sm_mtu_init_wait(struct bna_port *port, enum bna_port_event event)
817{
818 switch (event) {
819 case PORT_E_STOP:
820 bfa_fsm_set_state(port, bna_port_sm_last_resp_wait);
821 break;
822
823 case PORT_E_FAIL:
824 bfa_fsm_set_state(port, bna_port_sm_stopped);
825 break;
826
827 case PORT_E_PAUSE_CFG:
828 /* No-op */
829 break;
830
831 case PORT_E_MTU_CFG:
832 port->flags |= BNA_PORT_F_MTU_CHANGED;
833 break;
834
835 case PORT_E_FWRESP_MTU:
836 if (port->flags & BNA_PORT_F_MTU_CHANGED) {
837 port->flags &= ~BNA_PORT_F_MTU_CHANGED;
838 bna_fw_mtu_set(port);
839 } else {
840 bfa_fsm_set_state(port, bna_port_sm_pause_init_wait);
841 }
842 break;
843
844 default:
845 bfa_sm_fault(port->bna, event);
846 }
847}
848
849static void
850bna_port_sm_pause_init_wait_entry(struct bna_port *port)
851{
852 bna_fw_pause_set(port);
853}
854
855static void
856bna_port_sm_pause_init_wait(struct bna_port *port,
857 enum bna_port_event event)
858{
859 switch (event) {
860 case PORT_E_STOP:
861 bfa_fsm_set_state(port, bna_port_sm_last_resp_wait);
862 break;
863
864 case PORT_E_FAIL:
865 bfa_fsm_set_state(port, bna_port_sm_stopped);
866 break;
867
868 case PORT_E_PAUSE_CFG:
869 port->flags |= BNA_PORT_F_PAUSE_CHANGED;
870 break;
871
872 case PORT_E_MTU_CFG:
873 port->flags |= BNA_PORT_F_MTU_CHANGED;
874 break;
875
876 case PORT_E_FWRESP_PAUSE:
877 if (port->flags & BNA_PORT_F_PAUSE_CHANGED) {
878 port->flags &= ~BNA_PORT_F_PAUSE_CHANGED;
879 bna_fw_pause_set(port);
880 } else if (port->flags & BNA_PORT_F_MTU_CHANGED) {
881 port->flags &= ~BNA_PORT_F_MTU_CHANGED;
882 bfa_fsm_set_state(port, bna_port_sm_mtu_init_wait);
883 } else {
884 bfa_fsm_set_state(port, bna_port_sm_started);
885 bna_port_chld_start(port);
886 }
887 break;
888
889 default:
890 bfa_sm_fault(port->bna, event);
891 }
892}
893
894static void
895bna_port_sm_last_resp_wait_entry(struct bna_port *port)
896{
897}
898
899static void
900bna_port_sm_last_resp_wait(struct bna_port *port,
901 enum bna_port_event event)
902{
903 switch (event) {
904 case PORT_E_FAIL:
905 case PORT_E_FWRESP_PAUSE:
906 case PORT_E_FWRESP_MTU:
907 bfa_fsm_set_state(port, bna_port_sm_stopped);
908 break;
909
910 default:
911 bfa_sm_fault(port->bna, event);
912 }
913}
914
915static void
916bna_port_sm_started_entry(struct bna_port *port)
917{
918 /**
919 * NOTE: Do not call bna_port_chld_start() here, since it will be
920 * inadvertently called during pause_cfg_wait->started transition
921 * as well
922 */
923 call_port_pause_cbfn(port, BNA_CB_SUCCESS);
924 call_port_mtu_cbfn(port, BNA_CB_SUCCESS);
925}
926
927static void
928bna_port_sm_started(struct bna_port *port,
929 enum bna_port_event event)
930{
931 switch (event) {
932 case PORT_E_STOP:
933 bfa_fsm_set_state(port, bna_port_sm_chld_stop_wait);
934 break;
935
936 case PORT_E_FAIL:
937 bfa_fsm_set_state(port, bna_port_sm_stopped);
938 bna_port_chld_fail(port);
939 break;
940
941 case PORT_E_PAUSE_CFG:
942 bfa_fsm_set_state(port, bna_port_sm_pause_cfg_wait);
943 break;
944
945 case PORT_E_MTU_CFG:
946 bfa_fsm_set_state(port, bna_port_sm_rx_stop_wait);
947 break;
948
949 default:
950 bfa_sm_fault(port->bna, event);
951 }
952}
953
954static void
955bna_port_sm_pause_cfg_wait_entry(struct bna_port *port)
956{
957 bna_fw_pause_set(port);
958}
959
960static void
961bna_port_sm_pause_cfg_wait(struct bna_port *port,
962 enum bna_port_event event)
963{
964 switch (event) {
965 case PORT_E_FAIL:
966 bfa_fsm_set_state(port, bna_port_sm_stopped);
967 bna_port_chld_fail(port);
968 break;
969
970 case PORT_E_FWRESP_PAUSE:
971 bfa_fsm_set_state(port, bna_port_sm_started);
972 break;
973
974 default:
975 bfa_sm_fault(port->bna, event);
976 }
977}
978
979static void
980bna_port_sm_rx_stop_wait_entry(struct bna_port *port)
981{
982 bna_port_rx_stop(port);
983}
984
985static void
986bna_port_sm_rx_stop_wait(struct bna_port *port,
987 enum bna_port_event event)
988{
989 switch (event) {
990 case PORT_E_FAIL:
991 bfa_fsm_set_state(port, bna_port_sm_stopped);
992 bna_port_chld_fail(port);
993 break;
994
995 case PORT_E_CHLD_STOPPED:
996 bfa_fsm_set_state(port, bna_port_sm_mtu_cfg_wait);
997 break;
998
999 default:
1000 bfa_sm_fault(port->bna, event);
1001 }
1002}
1003
1004static void
1005bna_port_sm_mtu_cfg_wait_entry(struct bna_port *port)
1006{
1007 bna_fw_mtu_set(port);
1008}
1009
1010static void
1011bna_port_sm_mtu_cfg_wait(struct bna_port *port, enum bna_port_event event)
1012{
1013 switch (event) {
1014 case PORT_E_FAIL:
1015 bfa_fsm_set_state(port, bna_port_sm_stopped);
1016 bna_port_chld_fail(port);
1017 break;
1018
1019 case PORT_E_FWRESP_MTU:
1020 bfa_fsm_set_state(port, bna_port_sm_started);
1021 bna_port_rx_start(port);
1022 break;
1023
1024 default:
1025 bfa_sm_fault(port->bna, event);
1026 }
1027}
1028
1029static void
1030bna_port_sm_chld_stop_wait_entry(struct bna_port *port)
1031{
1032 bna_port_chld_stop(port);
1033}
1034
1035static void
1036bna_port_sm_chld_stop_wait(struct bna_port *port,
1037 enum bna_port_event event)
1038{
1039 switch (event) {
1040 case PORT_E_FAIL:
1041 bfa_fsm_set_state(port, bna_port_sm_stopped);
1042 bna_port_chld_fail(port);
1043 break;
1044
1045 case PORT_E_CHLD_STOPPED:
1046 bfa_fsm_set_state(port, bna_port_sm_stopped);
1047 break;
1048
1049 default:
1050 bfa_sm_fault(port->bna, event);
1051 }
1052}
1053
1054static void
1055bna_fw_pause_set(struct bna_port *port)
1056{
1057 struct bfi_ll_set_pause_req ll_req;
1058
1059 memset(&ll_req, 0, sizeof(ll_req));
1060 ll_req.mh.msg_class = BFI_MC_LL;
1061 ll_req.mh.msg_id = BFI_LL_H2I_SET_PAUSE_REQ;
1062 ll_req.mh.mtag.h2i.lpu_id = 0;
1063
1064 ll_req.tx_pause = port->pause_config.tx_pause;
1065 ll_req.rx_pause = port->pause_config.rx_pause;
1066
1067 bna_mbox_qe_fill(&port->mbox_qe, &ll_req, sizeof(ll_req),
1068 bna_fw_cb_pause_set, port);
1069
1070 bna_mbox_send(port->bna, &port->mbox_qe);
1071}
1072
1073static void
1074bna_fw_cb_pause_set(void *arg, int status)
1075{
1076 struct bna_port *port = (struct bna_port *)arg;
1077
1078 bfa_q_qe_init(&port->mbox_qe.qe);
1079 bfa_fsm_send_event(port, PORT_E_FWRESP_PAUSE);
1080}
1081
1082void
1083bna_fw_mtu_set(struct bna_port *port)
1084{
1085 struct bfi_ll_mtu_info_req ll_req;
1086
1087 bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_MTU_INFO_REQ, 0);
1088 ll_req.mtu = htons((u16)port->mtu);
1089
1090 bna_mbox_qe_fill(&port->mbox_qe, &ll_req, sizeof(ll_req),
1091 bna_fw_cb_mtu_set, port);
1092 bna_mbox_send(port->bna, &port->mbox_qe);
1093}
1094
1095void
1096bna_fw_cb_mtu_set(void *arg, int status)
1097{
1098 struct bna_port *port = (struct bna_port *)arg;
1099
1100 bfa_q_qe_init(&port->mbox_qe.qe);
1101 bfa_fsm_send_event(port, PORT_E_FWRESP_MTU);
1102}
1103
1104static void
1105bna_port_cb_chld_stopped(void *arg)
1106{
1107 struct bna_port *port = (struct bna_port *)arg;
1108
1109 bfa_fsm_send_event(port, PORT_E_CHLD_STOPPED);
1110}
1111
1112void
1113bna_port_init(struct bna_port *port, struct bna *bna)
1114{
1115 port->bna = bna;
1116 port->flags = 0;
1117 port->mtu = 0;
1118 port->type = BNA_PORT_T_REGULAR;
1119
1120 port->link_cbfn = bnad_cb_port_link_status;
1121
1122 port->chld_stop_wc.wc_resume = bna_port_cb_chld_stopped;
1123 port->chld_stop_wc.wc_cbarg = port;
1124 port->chld_stop_wc.wc_count = 0;
1125
1126 port->stop_cbfn = NULL;
1127 port->stop_cbarg = NULL;
1128
1129 port->pause_cbfn = NULL;
1130
1131 port->mtu_cbfn = NULL;
1132
1133 bfa_q_qe_init(&port->mbox_qe.qe);
1134
1135 bfa_fsm_set_state(port, bna_port_sm_stopped);
1136
1137 bna_llport_init(&port->llport, bna);
1138}
1139
1140void
1141bna_port_uninit(struct bna_port *port)
1142{
1143 bna_llport_uninit(&port->llport);
1144
1145 port->flags = 0;
1146
1147 port->bna = NULL;
1148}
1149
1150int
1151bna_port_state_get(struct bna_port *port)
1152{
1153 return bfa_sm_to_state(port_sm_table, port->fsm);
1154}
1155
1156void
1157bna_port_start(struct bna_port *port)
1158{
1159 port->flags |= BNA_PORT_F_DEVICE_READY;
1160 if (port->flags & BNA_PORT_F_ENABLED)
1161 bfa_fsm_send_event(port, PORT_E_START);
1162}
1163
1164void
1165bna_port_stop(struct bna_port *port)
1166{
1167 port->stop_cbfn = bna_device_cb_port_stopped;
1168 port->stop_cbarg = &port->bna->device;
1169
1170 port->flags &= ~BNA_PORT_F_DEVICE_READY;
1171 bfa_fsm_send_event(port, PORT_E_STOP);
1172}
1173
1174void
1175bna_port_fail(struct bna_port *port)
1176{
1177 port->flags &= ~BNA_PORT_F_DEVICE_READY;
1178 bfa_fsm_send_event(port, PORT_E_FAIL);
1179}
1180
1181void
1182bna_port_cb_tx_stopped(struct bna_port *port, enum bna_cb_status status)
1183{
1184 bfa_wc_down(&port->chld_stop_wc);
1185}
1186
1187void
1188bna_port_cb_rx_stopped(struct bna_port *port, enum bna_cb_status status)
1189{
1190 bfa_wc_down(&port->chld_stop_wc);
1191}
1192
1193void
1194bna_port_cb_link_up(struct bna_port *port, struct bfi_ll_aen *aen,
1195 int status)
1196{
1197 int i;
1198 u8 prio_map;
1199
1200 port->llport.link_status = BNA_LINK_UP;
1201 if (aen->cee_linkup)
1202 port->llport.link_status = BNA_CEE_UP;
1203
1204 /* Compute the priority */
1205 prio_map = aen->prio_map;
1206 if (prio_map) {
1207 for (i = 0; i < 8; i++) {
1208 if ((prio_map >> i) & 0x1)
1209 break;
1210 }
1211 port->priority = i;
1212 } else
1213 port->priority = 0;
1214
1215 /* Dispatch events */
1216 bna_tx_mod_cee_link_status(&port->bna->tx_mod, aen->cee_linkup);
1217 bna_tx_mod_prio_changed(&port->bna->tx_mod, port->priority);
1218 port->link_cbfn(port->bna->bnad, port->llport.link_status);
1219}
1220
1221void
1222bna_port_cb_link_down(struct bna_port *port, int status)
1223{
1224 port->llport.link_status = BNA_LINK_DOWN;
1225
1226 /* Dispatch events */
1227 bna_tx_mod_cee_link_status(&port->bna->tx_mod, BNA_LINK_DOWN);
1228 port->link_cbfn(port->bna->bnad, BNA_LINK_DOWN);
1229}
1230
1231int
1232bna_port_mtu_get(struct bna_port *port)
1233{
1234 return port->mtu;
1235}
1236
1237void
1238bna_port_enable(struct bna_port *port)
1239{
1240 if (port->fsm != (bfa_sm_t)bna_port_sm_stopped)
1241 return;
1242
1243 port->flags |= BNA_PORT_F_ENABLED;
1244
1245 if (port->flags & BNA_PORT_F_DEVICE_READY)
1246 bfa_fsm_send_event(port, PORT_E_START);
1247}
1248
1249void
1250bna_port_disable(struct bna_port *port, enum bna_cleanup_type type,
1251 void (*cbfn)(void *, enum bna_cb_status))
1252{
1253 if (type == BNA_SOFT_CLEANUP) {
1254 (*cbfn)(port->bna->bnad, BNA_CB_SUCCESS);
1255 return;
1256 }
1257
1258 port->stop_cbfn = cbfn;
1259 port->stop_cbarg = port->bna->bnad;
1260
1261 port->flags &= ~BNA_PORT_F_ENABLED;
1262
1263 bfa_fsm_send_event(port, PORT_E_STOP);
1264}
1265
1266void
1267bna_port_pause_config(struct bna_port *port,
1268 struct bna_pause_config *pause_config,
1269 void (*cbfn)(struct bnad *, enum bna_cb_status))
1270{
1271 port->pause_config = *pause_config;
1272
1273 port->pause_cbfn = cbfn;
1274
1275 bfa_fsm_send_event(port, PORT_E_PAUSE_CFG);
1276}
1277
1278void
1279bna_port_mtu_set(struct bna_port *port, int mtu,
1280 void (*cbfn)(struct bnad *, enum bna_cb_status))
1281{
1282 port->mtu = mtu;
1283
1284 port->mtu_cbfn = cbfn;
1285
1286 bfa_fsm_send_event(port, PORT_E_MTU_CFG);
1287}
1288
1289void
1290bna_port_mac_get(struct bna_port *port, mac_t *mac)
1291{
1292 *mac = bfa_ioc_get_mac(&port->bna->device.ioc);
1293}
1294
1295/**
1296 * Should be called only when port is disabled
1297 */
1298void
1299bna_port_type_set(struct bna_port *port, enum bna_port_type type)
1300{
1301 port->type = type;
1302 port->llport.type = type;
1303}
1304
1305/**
1306 * Should be called only when port is disabled
1307 */
1308void
1309bna_port_linkcbfn_set(struct bna_port *port,
1310 void (*linkcbfn)(struct bnad *, enum bna_link_status))
1311{
1312 port->link_cbfn = linkcbfn;
1313}
1314
1315void
1316bna_port_admin_up(struct bna_port *port)
1317{
1318 struct bna_llport *llport = &port->llport;
1319
1320 if (llport->flags & BNA_LLPORT_F_ENABLED)
1321 return;
1322
1323 llport->flags |= BNA_LLPORT_F_ENABLED;
1324
1325 if (llport->flags & BNA_LLPORT_F_RX_ENABLED)
1326 bfa_fsm_send_event(llport, LLPORT_E_UP);
1327}
1328
1329void
1330bna_port_admin_down(struct bna_port *port)
1331{
1332 struct bna_llport *llport = &port->llport;
1333
1334 if (!(llport->flags & BNA_LLPORT_F_ENABLED))
1335 return;
1336
1337 llport->flags &= ~BNA_LLPORT_F_ENABLED;
1338
1339 if (llport->flags & BNA_LLPORT_F_RX_ENABLED)
1340 bfa_fsm_send_event(llport, LLPORT_E_DOWN);
1341}
1342
1343/**
1344 * DEVICE
1345 */
1346#define enable_mbox_intr(_device)\
1347do {\
1348 u32 intr_status;\
1349 bna_intr_status_get((_device)->bna, intr_status);\
1350 bnad_cb_device_enable_mbox_intr((_device)->bna->bnad);\
1351 bna_mbox_intr_enable((_device)->bna);\
1352} while (0)
1353
1354#define disable_mbox_intr(_device)\
1355do {\
1356 bna_mbox_intr_disable((_device)->bna);\
1357 bnad_cb_device_disable_mbox_intr((_device)->bna->bnad);\
1358} while (0)
1359
1360const struct bna_chip_regs_offset reg_offset[] =
1361{{HOST_PAGE_NUM_FN0, HOSTFN0_INT_STATUS,
1362 HOSTFN0_INT_MASK, HOST_MSIX_ERR_INDEX_FN0},
1363{HOST_PAGE_NUM_FN1, HOSTFN1_INT_STATUS,
1364 HOSTFN1_INT_MASK, HOST_MSIX_ERR_INDEX_FN1},
1365{HOST_PAGE_NUM_FN2, HOSTFN2_INT_STATUS,
1366 HOSTFN2_INT_MASK, HOST_MSIX_ERR_INDEX_FN2},
1367{HOST_PAGE_NUM_FN3, HOSTFN3_INT_STATUS,
1368 HOSTFN3_INT_MASK, HOST_MSIX_ERR_INDEX_FN3},
1369};
1370
1371enum bna_device_event {
1372 DEVICE_E_ENABLE = 1,
1373 DEVICE_E_DISABLE = 2,
1374 DEVICE_E_IOC_READY = 3,
1375 DEVICE_E_IOC_FAILED = 4,
1376 DEVICE_E_IOC_DISABLED = 5,
1377 DEVICE_E_IOC_RESET = 6,
1378 DEVICE_E_PORT_STOPPED = 7,
1379};
1380
1381enum bna_device_state {
1382 BNA_DEVICE_STOPPED = 1,
1383 BNA_DEVICE_IOC_READY_WAIT = 2,
1384 BNA_DEVICE_READY = 3,
1385 BNA_DEVICE_PORT_STOP_WAIT = 4,
1386 BNA_DEVICE_IOC_DISABLE_WAIT = 5,
1387 BNA_DEVICE_FAILED = 6
1388};
1389
1390bfa_fsm_state_decl(bna_device, stopped, struct bna_device,
1391 enum bna_device_event);
1392bfa_fsm_state_decl(bna_device, ioc_ready_wait, struct bna_device,
1393 enum bna_device_event);
1394bfa_fsm_state_decl(bna_device, ready, struct bna_device,
1395 enum bna_device_event);
1396bfa_fsm_state_decl(bna_device, port_stop_wait, struct bna_device,
1397 enum bna_device_event);
1398bfa_fsm_state_decl(bna_device, ioc_disable_wait, struct bna_device,
1399 enum bna_device_event);
1400bfa_fsm_state_decl(bna_device, failed, struct bna_device,
1401 enum bna_device_event);
1402
1403static struct bfa_sm_table device_sm_table[] = {
1404 {BFA_SM(bna_device_sm_stopped), BNA_DEVICE_STOPPED},
1405 {BFA_SM(bna_device_sm_ioc_ready_wait), BNA_DEVICE_IOC_READY_WAIT},
1406 {BFA_SM(bna_device_sm_ready), BNA_DEVICE_READY},
1407 {BFA_SM(bna_device_sm_port_stop_wait), BNA_DEVICE_PORT_STOP_WAIT},
1408 {BFA_SM(bna_device_sm_ioc_disable_wait), BNA_DEVICE_IOC_DISABLE_WAIT},
1409 {BFA_SM(bna_device_sm_failed), BNA_DEVICE_FAILED},
1410};
1411
1412static void
1413bna_device_sm_stopped_entry(struct bna_device *device)
1414{
1415 if (device->stop_cbfn)
1416 device->stop_cbfn(device->stop_cbarg, BNA_CB_SUCCESS);
1417
1418 device->stop_cbfn = NULL;
1419 device->stop_cbarg = NULL;
1420}
1421
1422static void
1423bna_device_sm_stopped(struct bna_device *device,
1424 enum bna_device_event event)
1425{
1426 switch (event) {
1427 case DEVICE_E_ENABLE:
1428 if (device->intr_type == BNA_INTR_T_MSIX)
1429 bna_mbox_msix_idx_set(device);
1430 bfa_ioc_enable(&device->ioc);
1431 bfa_fsm_set_state(device, bna_device_sm_ioc_ready_wait);
1432 break;
1433
1434 case DEVICE_E_DISABLE:
1435 bfa_fsm_set_state(device, bna_device_sm_stopped);
1436 break;
1437
1438 case DEVICE_E_IOC_RESET:
1439 enable_mbox_intr(device);
1440 break;
1441
1442 case DEVICE_E_IOC_FAILED:
1443 bfa_fsm_set_state(device, bna_device_sm_failed);
1444 break;
1445
1446 default:
1447 bfa_sm_fault(device->bna, event);
1448 }
1449}
1450
1451static void
1452bna_device_sm_ioc_ready_wait_entry(struct bna_device *device)
1453{
1454 /**
1455 * Do not call bfa_ioc_enable() here. It must be called in the
1456 * previous state due to failed -> ioc_ready_wait transition.
1457 */
1458}
1459
1460static void
1461bna_device_sm_ioc_ready_wait(struct bna_device *device,
1462 enum bna_device_event event)
1463{
1464 switch (event) {
1465 case DEVICE_E_DISABLE:
1466 if (device->ready_cbfn)
1467 device->ready_cbfn(device->ready_cbarg,
1468 BNA_CB_INTERRUPT);
1469 device->ready_cbfn = NULL;
1470 device->ready_cbarg = NULL;
1471 bfa_fsm_set_state(device, bna_device_sm_ioc_disable_wait);
1472 break;
1473
1474 case DEVICE_E_IOC_READY:
1475 bfa_fsm_set_state(device, bna_device_sm_ready);
1476 break;
1477
1478 case DEVICE_E_IOC_FAILED:
1479 bfa_fsm_set_state(device, bna_device_sm_failed);
1480 break;
1481
1482 case DEVICE_E_IOC_RESET:
1483 enable_mbox_intr(device);
1484 break;
1485
1486 default:
1487 bfa_sm_fault(device->bna, event);
1488 }
1489}
1490
1491static void
1492bna_device_sm_ready_entry(struct bna_device *device)
1493{
1494 bna_mbox_mod_start(&device->bna->mbox_mod);
1495 bna_port_start(&device->bna->port);
1496
1497 if (device->ready_cbfn)
1498 device->ready_cbfn(device->ready_cbarg,
1499 BNA_CB_SUCCESS);
1500 device->ready_cbfn = NULL;
1501 device->ready_cbarg = NULL;
1502}
1503
1504static void
1505bna_device_sm_ready(struct bna_device *device, enum bna_device_event event)
1506{
1507 switch (event) {
1508 case DEVICE_E_DISABLE:
1509 bfa_fsm_set_state(device, bna_device_sm_port_stop_wait);
1510 break;
1511
1512 case DEVICE_E_IOC_FAILED:
1513 bfa_fsm_set_state(device, bna_device_sm_failed);
1514 break;
1515
1516 default:
1517 bfa_sm_fault(device->bna, event);
1518 }
1519}
1520
1521static void
1522bna_device_sm_port_stop_wait_entry(struct bna_device *device)
1523{
1524 bna_port_stop(&device->bna->port);
1525}
1526
1527static void
1528bna_device_sm_port_stop_wait(struct bna_device *device,
1529 enum bna_device_event event)
1530{
1531 switch (event) {
1532 case DEVICE_E_PORT_STOPPED:
1533 bna_mbox_mod_stop(&device->bna->mbox_mod);
1534 bfa_fsm_set_state(device, bna_device_sm_ioc_disable_wait);
1535 break;
1536
1537 case DEVICE_E_IOC_FAILED:
1538 disable_mbox_intr(device);
1539 bna_port_fail(&device->bna->port);
1540 break;
1541
1542 default:
1543 bfa_sm_fault(device->bna, event);
1544 }
1545}
1546
1547static void
1548bna_device_sm_ioc_disable_wait_entry(struct bna_device *device)
1549{
1550 bfa_ioc_disable(&device->ioc);
1551}
1552
1553static void
1554bna_device_sm_ioc_disable_wait(struct bna_device *device,
1555 enum bna_device_event event)
1556{
1557 switch (event) {
1558 case DEVICE_E_IOC_DISABLED:
1559 disable_mbox_intr(device);
1560 bfa_fsm_set_state(device, bna_device_sm_stopped);
1561 break;
1562
1563 default:
1564 bfa_sm_fault(device->bna, event);
1565 }
1566}
1567
1568static void
1569bna_device_sm_failed_entry(struct bna_device *device)
1570{
1571 disable_mbox_intr(device);
1572 bna_port_fail(&device->bna->port);
1573 bna_mbox_mod_stop(&device->bna->mbox_mod);
1574
1575 if (device->ready_cbfn)
1576 device->ready_cbfn(device->ready_cbarg,
1577 BNA_CB_FAIL);
1578 device->ready_cbfn = NULL;
1579 device->ready_cbarg = NULL;
1580}
1581
1582static void
1583bna_device_sm_failed(struct bna_device *device,
1584 enum bna_device_event event)
1585{
1586 switch (event) {
1587 case DEVICE_E_DISABLE:
1588 bfa_fsm_set_state(device, bna_device_sm_ioc_disable_wait);
1589 break;
1590
1591 case DEVICE_E_IOC_RESET:
1592 enable_mbox_intr(device);
1593 bfa_fsm_set_state(device, bna_device_sm_ioc_ready_wait);
1594 break;
1595
1596 default:
1597 bfa_sm_fault(device->bna, event);
1598 }
1599}
1600
1601/* IOC callback functions */
1602
1603static void
1604bna_device_cb_iocll_ready(void *dev, enum bfa_status error)
1605{
1606 struct bna_device *device = (struct bna_device *)dev;
1607
1608 if (error)
1609 bfa_fsm_send_event(device, DEVICE_E_IOC_FAILED);
1610 else
1611 bfa_fsm_send_event(device, DEVICE_E_IOC_READY);
1612}
1613
1614static void
1615bna_device_cb_iocll_disabled(void *dev)
1616{
1617 struct bna_device *device = (struct bna_device *)dev;
1618
1619 bfa_fsm_send_event(device, DEVICE_E_IOC_DISABLED);
1620}
1621
1622static void
1623bna_device_cb_iocll_failed(void *dev)
1624{
1625 struct bna_device *device = (struct bna_device *)dev;
1626
1627 bfa_fsm_send_event(device, DEVICE_E_IOC_FAILED);
1628}
1629
1630static void
1631bna_device_cb_iocll_reset(void *dev)
1632{
1633 struct bna_device *device = (struct bna_device *)dev;
1634
1635 bfa_fsm_send_event(device, DEVICE_E_IOC_RESET);
1636}
1637
1638static struct bfa_ioc_cbfn bfa_iocll_cbfn = {
1639 bna_device_cb_iocll_ready,
1640 bna_device_cb_iocll_disabled,
1641 bna_device_cb_iocll_failed,
1642 bna_device_cb_iocll_reset
1643};
1644
1645void
1646bna_device_init(struct bna_device *device, struct bna *bna,
1647 struct bna_res_info *res_info)
1648{
1649 u64 dma;
1650
1651 device->bna = bna;
1652
1653 /**
1654 * Attach IOC and claim:
1655 * 1. DMA memory for IOC attributes
1656 * 2. Kernel memory for FW trace
1657 */
1658 bfa_ioc_attach(&device->ioc, device, &bfa_iocll_cbfn);
1659 bfa_ioc_pci_init(&device->ioc, &bna->pcidev, BFI_MC_LL);
1660
1661 BNA_GET_DMA_ADDR(
1662 &res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.mdl[0].dma, dma);
1663 bfa_ioc_mem_claim(&device->ioc,
1664 res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.mdl[0].kva,
1665 dma);
1666
1667 bna_adv_device_init(device, bna, res_info);
1668 /*
1669 * Initialize mbox_mod only after IOC, so that mbox handler
1670 * registration goes through
1671 */
1672 device->intr_type =
1673 res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.intr_type;
1674 device->vector =
1675 res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.idl[0].vector;
1676 bna_mbox_mod_init(&bna->mbox_mod, bna);
1677
1678 device->ready_cbfn = device->stop_cbfn = NULL;
1679 device->ready_cbarg = device->stop_cbarg = NULL;
1680
1681 bfa_fsm_set_state(device, bna_device_sm_stopped);
1682}
1683
1684void
1685bna_device_uninit(struct bna_device *device)
1686{
1687 bna_mbox_mod_uninit(&device->bna->mbox_mod);
1688
1689 bfa_cee_detach(&device->bna->cee);
1690
1691 bfa_ioc_detach(&device->ioc);
1692
1693 device->bna = NULL;
1694}
1695
1696void
1697bna_device_cb_port_stopped(void *arg, enum bna_cb_status status)
1698{
1699 struct bna_device *device = (struct bna_device *)arg;
1700
1701 bfa_fsm_send_event(device, DEVICE_E_PORT_STOPPED);
1702}
1703
1704int
1705bna_device_status_get(struct bna_device *device)
1706{
1707 return (device->fsm == (bfa_fsm_t)bna_device_sm_ready);
1708}
1709
1710void
1711bna_device_enable(struct bna_device *device)
1712{
1713 if (device->fsm != (bfa_fsm_t)bna_device_sm_stopped) {
1714 bnad_cb_device_enabled(device->bna->bnad, BNA_CB_BUSY);
1715 return;
1716 }
1717
1718 device->ready_cbfn = bnad_cb_device_enabled;
1719 device->ready_cbarg = device->bna->bnad;
1720
1721 bfa_fsm_send_event(device, DEVICE_E_ENABLE);
1722}
1723
1724void
1725bna_device_disable(struct bna_device *device, enum bna_cleanup_type type)
1726{
1727 if (type == BNA_SOFT_CLEANUP) {
1728 bnad_cb_device_disabled(device->bna->bnad, BNA_CB_SUCCESS);
1729 return;
1730 }
1731
1732 device->stop_cbfn = bnad_cb_device_disabled;
1733 device->stop_cbarg = device->bna->bnad;
1734
1735 bfa_fsm_send_event(device, DEVICE_E_DISABLE);
1736}
1737
1738int
1739bna_device_state_get(struct bna_device *device)
1740{
1741 return bfa_sm_to_state(device_sm_table, device->fsm);
1742}
1743
1744u32 bna_dim_vector[BNA_LOAD_T_MAX][BNA_BIAS_T_MAX] = {
1745 {12, 20},
1746 {10, 18},
1747 {8, 16},
1748 {6, 12},
1749 {4, 8},
1750 {3, 6},
1751 {2, 4},
1752 {1, 2},
1753};
1754
1755u32 bna_napi_dim_vector[BNA_LOAD_T_MAX][BNA_BIAS_T_MAX] = {
1756 {12, 12},
1757 {6, 10},
1758 {5, 10},
1759 {4, 8},
1760 {3, 6},
1761 {3, 6},
1762 {2, 4},
1763 {1, 2},
1764};
1765
1766/* device */
1767void
1768bna_adv_device_init(struct bna_device *device, struct bna *bna,
1769 struct bna_res_info *res_info)
1770{
1771 u8 *kva;
1772 u64 dma;
1773
1774 device->bna = bna;
1775
1776 kva = res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.mdl[0].kva;
1777
1778 /**
1779 * Attach common modules (Diag, SFP, CEE, Port) and claim respective
1780 * DMA memory.
1781 */
1782 BNA_GET_DMA_ADDR(
1783 &res_info[BNA_RES_MEM_T_COM].res_u.mem_info.mdl[0].dma, dma);
1784 kva = res_info[BNA_RES_MEM_T_COM].res_u.mem_info.mdl[0].kva;
1785
1786 bfa_cee_attach(&bna->cee, &device->ioc, bna);
1787 bfa_cee_mem_claim(&bna->cee, kva, dma);
1788 kva += bfa_cee_meminfo();
1789 dma += bfa_cee_meminfo();
1790
1791}
1792
1793/* utils */
1794
1795void
1796bna_adv_res_req(struct bna_res_info *res_info)
1797{
1798 /* DMA memory for COMMON_MODULE */
1799 res_info[BNA_RES_MEM_T_COM].res_type = BNA_RES_T_MEM;
1800 res_info[BNA_RES_MEM_T_COM].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
1801 res_info[BNA_RES_MEM_T_COM].res_u.mem_info.num = 1;
1802 res_info[BNA_RES_MEM_T_COM].res_u.mem_info.len = ALIGN(
1803 bfa_cee_meminfo(), PAGE_SIZE);
1804
1805 /* Virtual memory for retreiving fw_trc */
1806 res_info[BNA_RES_MEM_T_FWTRC].res_type = BNA_RES_T_MEM;
1807 res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.mem_type = BNA_MEM_T_KVA;
1808 res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.num = 0;
1809 res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.len = 0;
1810
1811 /* DMA memory for retreiving stats */
1812 res_info[BNA_RES_MEM_T_STATS].res_type = BNA_RES_T_MEM;
1813 res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
1814 res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.num = 1;
1815 res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.len =
1816 ALIGN(BFI_HW_STATS_SIZE, PAGE_SIZE);
1817
1818 /* Virtual memory for soft stats */
1819 res_info[BNA_RES_MEM_T_SWSTATS].res_type = BNA_RES_T_MEM;
1820 res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.mem_type = BNA_MEM_T_KVA;
1821 res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.num = 1;
1822 res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.len =
1823 sizeof(struct bna_sw_stats);
1824}
1825
1826static void
1827bna_sw_stats_get(struct bna *bna, struct bna_sw_stats *sw_stats)
1828{
1829 struct bna_tx *tx;
1830 struct bna_txq *txq;
1831 struct bna_rx *rx;
1832 struct bna_rxp *rxp;
1833 struct list_head *qe;
1834 struct list_head *txq_qe;
1835 struct list_head *rxp_qe;
1836 struct list_head *mac_qe;
1837 int i;
1838
1839 sw_stats->device_state = bna_device_state_get(&bna->device);
1840 sw_stats->port_state = bna_port_state_get(&bna->port);
1841 sw_stats->port_flags = bna->port.flags;
1842 sw_stats->llport_state = bna_llport_state_get(&bna->port.llport);
1843 sw_stats->priority = bna->port.priority;
1844
1845 i = 0;
1846 list_for_each(qe, &bna->tx_mod.tx_active_q) {
1847 tx = (struct bna_tx *)qe;
1848 sw_stats->tx_stats[i].tx_state = bna_tx_state_get(tx);
1849 sw_stats->tx_stats[i].tx_flags = tx->flags;
1850
1851 sw_stats->tx_stats[i].num_txqs = 0;
1852 sw_stats->tx_stats[i].txq_bmap[0] = 0;
1853 sw_stats->tx_stats[i].txq_bmap[1] = 0;
1854 list_for_each(txq_qe, &tx->txq_q) {
1855 txq = (struct bna_txq *)txq_qe;
1856 if (txq->txq_id < 32)
1857 sw_stats->tx_stats[i].txq_bmap[0] |=
1858 ((u32)1 << txq->txq_id);
1859 else
1860 sw_stats->tx_stats[i].txq_bmap[1] |=
1861 ((u32)
1862 1 << (txq->txq_id - 32));
1863 sw_stats->tx_stats[i].num_txqs++;
1864 }
1865
1866 sw_stats->tx_stats[i].txf_id = tx->txf.txf_id;
1867
1868 i++;
1869 }
1870 sw_stats->num_active_tx = i;
1871
1872 i = 0;
1873 list_for_each(qe, &bna->rx_mod.rx_active_q) {
1874 rx = (struct bna_rx *)qe;
1875 sw_stats->rx_stats[i].rx_state = bna_rx_state_get(rx);
1876 sw_stats->rx_stats[i].rx_flags = rx->rx_flags;
1877
1878 sw_stats->rx_stats[i].num_rxps = 0;
1879 sw_stats->rx_stats[i].num_rxqs = 0;
1880 sw_stats->rx_stats[i].rxq_bmap[0] = 0;
1881 sw_stats->rx_stats[i].rxq_bmap[1] = 0;
1882 sw_stats->rx_stats[i].cq_bmap[0] = 0;
1883 sw_stats->rx_stats[i].cq_bmap[1] = 0;
1884 list_for_each(rxp_qe, &rx->rxp_q) {
1885 rxp = (struct bna_rxp *)rxp_qe;
1886
1887 sw_stats->rx_stats[i].num_rxqs += 1;
1888
1889 if (rxp->type == BNA_RXP_SINGLE) {
1890 if (rxp->rxq.single.only->rxq_id < 32) {
1891 sw_stats->rx_stats[i].rxq_bmap[0] |=
1892 ((u32)1 <<
1893 rxp->rxq.single.only->rxq_id);
1894 } else {
1895 sw_stats->rx_stats[i].rxq_bmap[1] |=
1896 ((u32)1 <<
1897 (rxp->rxq.single.only->rxq_id - 32));
1898 }
1899 } else {
1900 if (rxp->rxq.slr.large->rxq_id < 32) {
1901 sw_stats->rx_stats[i].rxq_bmap[0] |=
1902 ((u32)1 <<
1903 rxp->rxq.slr.large->rxq_id);
1904 } else {
1905 sw_stats->rx_stats[i].rxq_bmap[1] |=
1906 ((u32)1 <<
1907 (rxp->rxq.slr.large->rxq_id - 32));
1908 }
1909
1910 if (rxp->rxq.slr.small->rxq_id < 32) {
1911 sw_stats->rx_stats[i].rxq_bmap[0] |=
1912 ((u32)1 <<
1913 rxp->rxq.slr.small->rxq_id);
1914 } else {
1915 sw_stats->rx_stats[i].rxq_bmap[1] |=
1916 ((u32)1 <<
1917 (rxp->rxq.slr.small->rxq_id - 32));
1918 }
1919 sw_stats->rx_stats[i].num_rxqs += 1;
1920 }
1921
1922 if (rxp->cq.cq_id < 32)
1923 sw_stats->rx_stats[i].cq_bmap[0] |=
1924 (1 << rxp->cq.cq_id);
1925 else
1926 sw_stats->rx_stats[i].cq_bmap[1] |=
1927 (1 << (rxp->cq.cq_id - 32));
1928
1929 sw_stats->rx_stats[i].num_rxps++;
1930 }
1931
1932 sw_stats->rx_stats[i].rxf_id = rx->rxf.rxf_id;
1933 sw_stats->rx_stats[i].rxf_state = bna_rxf_state_get(&rx->rxf);
1934 sw_stats->rx_stats[i].rxf_oper_state = rx->rxf.rxf_oper_state;
1935
1936 sw_stats->rx_stats[i].num_active_ucast = 0;
1937 if (rx->rxf.ucast_active_mac)
1938 sw_stats->rx_stats[i].num_active_ucast++;
1939 list_for_each(mac_qe, &rx->rxf.ucast_active_q)
1940 sw_stats->rx_stats[i].num_active_ucast++;
1941
1942 sw_stats->rx_stats[i].num_active_mcast = 0;
1943 list_for_each(mac_qe, &rx->rxf.mcast_active_q)
1944 sw_stats->rx_stats[i].num_active_mcast++;
1945
1946 sw_stats->rx_stats[i].rxmode_active = rx->rxf.rxmode_active;
1947 sw_stats->rx_stats[i].vlan_filter_status =
1948 rx->rxf.vlan_filter_status;
1949 memcpy(sw_stats->rx_stats[i].vlan_filter_table,
1950 rx->rxf.vlan_filter_table,
1951 sizeof(u32) * ((BFI_MAX_VLAN + 1) / 32));
1952
1953 sw_stats->rx_stats[i].rss_status = rx->rxf.rss_status;
1954 sw_stats->rx_stats[i].hds_status = rx->rxf.hds_status;
1955
1956 i++;
1957 }
1958 sw_stats->num_active_rx = i;
1959}
1960
1961static void
1962bna_fw_cb_stats_get(void *arg, int status)
1963{
1964 struct bna *bna = (struct bna *)arg;
1965 u64 *p_stats;
1966 int i, count;
1967 int rxf_count, txf_count;
1968 u64 rxf_bmap, txf_bmap;
1969
1970 bfa_q_qe_init(&bna->mbox_qe.qe);
1971
1972 if (status == 0) {
1973 p_stats = (u64 *)bna->stats.hw_stats;
1974 count = sizeof(struct bfi_ll_stats) / sizeof(u64);
1975 for (i = 0; i < count; i++)
1976 p_stats[i] = cpu_to_be64(p_stats[i]);
1977
1978 rxf_count = 0;
1979 rxf_bmap = (u64)bna->stats.rxf_bmap[0] |
1980 ((u64)bna->stats.rxf_bmap[1] << 32);
1981 for (i = 0; i < BFI_LL_RXF_ID_MAX; i++)
1982 if (rxf_bmap & ((u64)1 << i))
1983 rxf_count++;
1984
1985 txf_count = 0;
1986 txf_bmap = (u64)bna->stats.txf_bmap[0] |
1987 ((u64)bna->stats.txf_bmap[1] << 32);
1988 for (i = 0; i < BFI_LL_TXF_ID_MAX; i++)
1989 if (txf_bmap & ((u64)1 << i))
1990 txf_count++;
1991
1992 p_stats = (u64 *)&bna->stats.hw_stats->rxf_stats[0] +
1993 ((rxf_count * sizeof(struct bfi_ll_stats_rxf) +
1994 txf_count * sizeof(struct bfi_ll_stats_txf))/
1995 sizeof(u64));
1996
1997 /* Populate the TXF stats from the firmware DMAed copy */
1998 for (i = (BFI_LL_TXF_ID_MAX - 1); i >= 0; i--)
1999 if (txf_bmap & ((u64)1 << i)) {
2000 p_stats -= sizeof(struct bfi_ll_stats_txf)/
2001 sizeof(u64);
2002 memcpy(&bna->stats.hw_stats->txf_stats[i],
2003 p_stats,
2004 sizeof(struct bfi_ll_stats_txf));
2005 }
2006
2007 /* Populate the RXF stats from the firmware DMAed copy */
2008 for (i = (BFI_LL_RXF_ID_MAX - 1); i >= 0; i--)
2009 if (rxf_bmap & ((u64)1 << i)) {
2010 p_stats -= sizeof(struct bfi_ll_stats_rxf)/
2011 sizeof(u64);
2012 memcpy(&bna->stats.hw_stats->rxf_stats[i],
2013 p_stats,
2014 sizeof(struct bfi_ll_stats_rxf));
2015 }
2016
2017 bna_sw_stats_get(bna, bna->stats.sw_stats);
2018 bnad_cb_stats_get(bna->bnad, BNA_CB_SUCCESS, &bna->stats);
2019 } else
2020 bnad_cb_stats_get(bna->bnad, BNA_CB_FAIL, &bna->stats);
2021}
2022
2023static void
2024bna_fw_stats_get(struct bna *bna)
2025{
2026 struct bfi_ll_stats_req ll_req;
2027
2028 bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_STATS_GET_REQ, 0);
2029 ll_req.stats_mask = htons(BFI_LL_STATS_ALL);
2030
2031 ll_req.rxf_id_mask[0] = htonl(bna->rx_mod.rxf_bmap[0]);
2032 ll_req.rxf_id_mask[1] = htonl(bna->rx_mod.rxf_bmap[1]);
2033 ll_req.txf_id_mask[0] = htonl(bna->tx_mod.txf_bmap[0]);
2034 ll_req.txf_id_mask[1] = htonl(bna->tx_mod.txf_bmap[1]);
2035
2036 ll_req.host_buffer.a32.addr_hi = bna->hw_stats_dma.msb;
2037 ll_req.host_buffer.a32.addr_lo = bna->hw_stats_dma.lsb;
2038
2039 bna_mbox_qe_fill(&bna->mbox_qe, &ll_req, sizeof(ll_req),
2040 bna_fw_cb_stats_get, bna);
2041 bna_mbox_send(bna, &bna->mbox_qe);
2042
2043 bna->stats.rxf_bmap[0] = bna->rx_mod.rxf_bmap[0];
2044 bna->stats.rxf_bmap[1] = bna->rx_mod.rxf_bmap[1];
2045 bna->stats.txf_bmap[0] = bna->tx_mod.txf_bmap[0];
2046 bna->stats.txf_bmap[1] = bna->tx_mod.txf_bmap[1];
2047}
2048
2049static void
2050bna_fw_cb_stats_clr(void *arg, int status)
2051{
2052 struct bna *bna = (struct bna *)arg;
2053
2054 bfa_q_qe_init(&bna->mbox_qe.qe);
2055
2056 memset(bna->stats.sw_stats, 0, sizeof(struct bna_sw_stats));
2057 memset(bna->stats.hw_stats, 0, sizeof(struct bfi_ll_stats));
2058
2059 bnad_cb_stats_clr(bna->bnad);
2060}
2061
2062static void
2063bna_fw_stats_clr(struct bna *bna)
2064{
2065 struct bfi_ll_stats_req ll_req;
2066
2067 bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_STATS_CLEAR_REQ, 0);
2068 ll_req.stats_mask = htons(BFI_LL_STATS_ALL);
2069 ll_req.rxf_id_mask[0] = htonl(0xffffffff);
2070 ll_req.rxf_id_mask[1] = htonl(0xffffffff);
2071 ll_req.txf_id_mask[0] = htonl(0xffffffff);
2072 ll_req.txf_id_mask[1] = htonl(0xffffffff);
2073
2074 bna_mbox_qe_fill(&bna->mbox_qe, &ll_req, sizeof(ll_req),
2075 bna_fw_cb_stats_clr, bna);
2076 bna_mbox_send(bna, &bna->mbox_qe);
2077}
2078
2079void
2080bna_stats_get(struct bna *bna)
2081{
2082 if (bna_device_status_get(&bna->device))
2083 bna_fw_stats_get(bna);
2084 else
2085 bnad_cb_stats_get(bna->bnad, BNA_CB_FAIL, &bna->stats);
2086}
2087
2088void
2089bna_stats_clr(struct bna *bna)
2090{
2091 if (bna_device_status_get(&bna->device))
2092 bna_fw_stats_clr(bna);
2093 else {
2094 memset(&bna->stats.sw_stats, 0,
2095 sizeof(struct bna_sw_stats));
2096 memset(bna->stats.hw_stats, 0,
2097 sizeof(struct bfi_ll_stats));
2098 bnad_cb_stats_clr(bna->bnad);
2099 }
2100}
2101
2102/* IB */
2103void
2104bna_ib_coalescing_timeo_set(struct bna_ib *ib, u8 coalescing_timeo)
2105{
2106 ib->ib_config.coalescing_timeo = coalescing_timeo;
2107
2108 if (ib->start_count)
2109 ib->door_bell.doorbell_ack = BNA_DOORBELL_IB_INT_ACK(
2110 (u32)ib->ib_config.coalescing_timeo, 0);
2111}
2112
2113/* RxF */
2114void
2115bna_rxf_adv_init(struct bna_rxf *rxf,
2116 struct bna_rx *rx,
2117 struct bna_rx_config *q_config)
2118{
2119 switch (q_config->rxp_type) {
2120 case BNA_RXP_SINGLE:
2121 /* No-op */
2122 break;
2123 case BNA_RXP_SLR:
2124 rxf->ctrl_flags |= BNA_RXF_CF_SM_LG_RXQ;
2125 break;
2126 case BNA_RXP_HDS:
2127 rxf->hds_cfg.hdr_type = q_config->hds_config.hdr_type;
2128 rxf->hds_cfg.header_size =
2129 q_config->hds_config.header_size;
2130 rxf->forced_offset = 0;
2131 break;
2132 default:
2133 break;
2134 }
2135
2136 if (q_config->rss_status == BNA_STATUS_T_ENABLED) {
2137 rxf->ctrl_flags |= BNA_RXF_CF_RSS_ENABLE;
2138 rxf->rss_cfg.hash_type = q_config->rss_config.hash_type;
2139 rxf->rss_cfg.hash_mask = q_config->rss_config.hash_mask;
2140 memcpy(&rxf->rss_cfg.toeplitz_hash_key[0],
2141 &q_config->rss_config.toeplitz_hash_key[0],
2142 sizeof(rxf->rss_cfg.toeplitz_hash_key));
2143 }
2144}
2145
2146static void
2147rxf_fltr_mbox_cmd(struct bna_rxf *rxf, u8 cmd, enum bna_status status)
2148{
2149 struct bfi_ll_rxf_req req;
2150
2151 bfi_h2i_set(req.mh, BFI_MC_LL, cmd, 0);
2152
2153 req.rxf_id = rxf->rxf_id;
2154 req.enable = status;
2155
2156 bna_mbox_qe_fill(&rxf->mbox_qe, &req, sizeof(req),
2157 rxf_cb_cam_fltr_mbox_cmd, rxf);
2158
2159 bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe);
2160}
2161
2162void
2163__rxf_default_function_config(struct bna_rxf *rxf, enum bna_status status)
2164{
2165 struct bna_rx_fndb_ram *rx_fndb_ram;
2166 u32 ctrl_flags;
2167 int i;
2168
2169 rx_fndb_ram = (struct bna_rx_fndb_ram *)
2170 BNA_GET_MEM_BASE_ADDR(rxf->rx->bna->pcidev.pci_bar_kva,
2171 RX_FNDB_RAM_BASE_OFFSET);
2172
2173 for (i = 0; i < BFI_MAX_RXF; i++) {
2174 if (status == BNA_STATUS_T_ENABLED) {
2175 if (i == rxf->rxf_id)
2176 continue;
2177
2178 ctrl_flags =
2179 readl(&rx_fndb_ram[i].control_flags);
2180 ctrl_flags |= BNA_RXF_CF_DEFAULT_FUNCTION_ENABLE;
2181 writel(ctrl_flags,
2182 &rx_fndb_ram[i].control_flags);
2183 } else {
2184 ctrl_flags =
2185 readl(&rx_fndb_ram[i].control_flags);
2186 ctrl_flags &= ~BNA_RXF_CF_DEFAULT_FUNCTION_ENABLE;
2187 writel(ctrl_flags,
2188 &rx_fndb_ram[i].control_flags);
2189 }
2190 }
2191}
2192
2193int
2194rxf_process_packet_filter_ucast(struct bna_rxf *rxf)
2195{
2196 struct bna_mac *mac = NULL;
2197 struct list_head *qe;
2198
2199 /* Add additional MAC entries */
2200 if (!list_empty(&rxf->ucast_pending_add_q)) {
2201 bfa_q_deq(&rxf->ucast_pending_add_q, &qe);
2202 bfa_q_qe_init(qe);
2203 mac = (struct bna_mac *)qe;
2204 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_ADD_REQ, mac);
2205 list_add_tail(&mac->qe, &rxf->ucast_active_q);
2206 return 1;
2207 }
2208
2209 /* Delete MAC addresses previousely added */
2210 if (!list_empty(&rxf->ucast_pending_del_q)) {
2211 bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
2212 bfa_q_qe_init(qe);
2213 mac = (struct bna_mac *)qe;
2214 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_DEL_REQ, mac);
2215 bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
2216 return 1;
2217 }
2218
2219 return 0;
2220}
2221
2222int
2223rxf_process_packet_filter_promisc(struct bna_rxf *rxf)
2224{
2225 struct bna *bna = rxf->rx->bna;
2226
2227 /* Enable/disable promiscuous mode */
2228 if (is_promisc_enable(rxf->rxmode_pending,
2229 rxf->rxmode_pending_bitmask)) {
2230 /* move promisc configuration from pending -> active */
2231 promisc_inactive(rxf->rxmode_pending,
2232 rxf->rxmode_pending_bitmask);
2233 rxf->rxmode_active |= BNA_RXMODE_PROMISC;
2234
2235 /* Disable VLAN filter to allow all VLANs */
2236 __rxf_vlan_filter_set(rxf, BNA_STATUS_T_DISABLED);
2237 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
2238 BNA_STATUS_T_ENABLED);
2239 return 1;
2240 } else if (is_promisc_disable(rxf->rxmode_pending,
2241 rxf->rxmode_pending_bitmask)) {
2242 /* move promisc configuration from pending -> active */
2243 promisc_inactive(rxf->rxmode_pending,
2244 rxf->rxmode_pending_bitmask);
2245 rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
2246 bna->rxf_promisc_id = BFI_MAX_RXF;
2247
2248 /* Revert VLAN filter */
2249 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
2250 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
2251 BNA_STATUS_T_DISABLED);
2252 return 1;
2253 }
2254
2255 return 0;
2256}
2257
2258int
2259rxf_process_packet_filter_default(struct bna_rxf *rxf)
2260{
2261 struct bna *bna = rxf->rx->bna;
2262
2263 /* Enable/disable default mode */
2264 if (is_default_enable(rxf->rxmode_pending,
2265 rxf->rxmode_pending_bitmask)) {
2266 /* move default configuration from pending -> active */
2267 default_inactive(rxf->rxmode_pending,
2268 rxf->rxmode_pending_bitmask);
2269 rxf->rxmode_active |= BNA_RXMODE_DEFAULT;
2270
2271 /* Disable VLAN filter to allow all VLANs */
2272 __rxf_vlan_filter_set(rxf, BNA_STATUS_T_DISABLED);
2273 /* Redirect all other RxF vlan filtering to this one */
2274 __rxf_default_function_config(rxf, BNA_STATUS_T_ENABLED);
2275 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_DEFAULT_SET_REQ,
2276 BNA_STATUS_T_ENABLED);
2277 return 1;
2278 } else if (is_default_disable(rxf->rxmode_pending,
2279 rxf->rxmode_pending_bitmask)) {
2280 /* move default configuration from pending -> active */
2281 default_inactive(rxf->rxmode_pending,
2282 rxf->rxmode_pending_bitmask);
2283 rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
2284 bna->rxf_default_id = BFI_MAX_RXF;
2285
2286 /* Revert VLAN filter */
2287 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
2288 /* Stop RxF vlan filter table redirection */
2289 __rxf_default_function_config(rxf, BNA_STATUS_T_DISABLED);
2290 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_DEFAULT_SET_REQ,
2291 BNA_STATUS_T_DISABLED);
2292 return 1;
2293 }
2294
2295 return 0;
2296}
2297
2298int
2299rxf_process_packet_filter_allmulti(struct bna_rxf *rxf)
2300{
2301 /* Enable/disable allmulti mode */
2302 if (is_allmulti_enable(rxf->rxmode_pending,
2303 rxf->rxmode_pending_bitmask)) {
2304 /* move allmulti configuration from pending -> active */
2305 allmulti_inactive(rxf->rxmode_pending,
2306 rxf->rxmode_pending_bitmask);
2307 rxf->rxmode_active |= BNA_RXMODE_ALLMULTI;
2308
2309 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
2310 BNA_STATUS_T_ENABLED);
2311 return 1;
2312 } else if (is_allmulti_disable(rxf->rxmode_pending,
2313 rxf->rxmode_pending_bitmask)) {
2314 /* move allmulti configuration from pending -> active */
2315 allmulti_inactive(rxf->rxmode_pending,
2316 rxf->rxmode_pending_bitmask);
2317 rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
2318
2319 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
2320 BNA_STATUS_T_DISABLED);
2321 return 1;
2322 }
2323
2324 return 0;
2325}
2326
2327int
2328rxf_clear_packet_filter_ucast(struct bna_rxf *rxf)
2329{
2330 struct bna_mac *mac = NULL;
2331 struct list_head *qe;
2332
2333 /* 1. delete pending ucast entries */
2334 if (!list_empty(&rxf->ucast_pending_del_q)) {
2335 bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
2336 bfa_q_qe_init(qe);
2337 mac = (struct bna_mac *)qe;
2338 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_DEL_REQ, mac);
2339 bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
2340 return 1;
2341 }
2342
2343 /* 2. clear active ucast entries; move them to pending_add_q */
2344 if (!list_empty(&rxf->ucast_active_q)) {
2345 bfa_q_deq(&rxf->ucast_active_q, &qe);
2346 bfa_q_qe_init(qe);
2347 mac = (struct bna_mac *)qe;
2348 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_DEL_REQ, mac);
2349 list_add_tail(&mac->qe, &rxf->ucast_pending_add_q);
2350 return 1;
2351 }
2352
2353 return 0;
2354}
2355
2356int
2357rxf_clear_packet_filter_promisc(struct bna_rxf *rxf)
2358{
2359 struct bna *bna = rxf->rx->bna;
2360
2361 /* 6. Execute pending promisc mode disable command */
2362 if (is_promisc_disable(rxf->rxmode_pending,
2363 rxf->rxmode_pending_bitmask)) {
2364 /* move promisc configuration from pending -> active */
2365 promisc_inactive(rxf->rxmode_pending,
2366 rxf->rxmode_pending_bitmask);
2367 rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
2368 bna->rxf_promisc_id = BFI_MAX_RXF;
2369
2370 /* Revert VLAN filter */
2371 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
2372 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
2373 BNA_STATUS_T_DISABLED);
2374 return 1;
2375 }
2376
2377 /* 7. Clear active promisc mode; move it to pending enable */
2378 if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
2379 /* move promisc configuration from active -> pending */
2380 promisc_enable(rxf->rxmode_pending,
2381 rxf->rxmode_pending_bitmask);
2382 rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
2383
2384 /* Revert VLAN filter */
2385 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
2386 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
2387 BNA_STATUS_T_DISABLED);
2388 return 1;
2389 }
2390
2391 return 0;
2392}
2393
2394int
2395rxf_clear_packet_filter_default(struct bna_rxf *rxf)
2396{
2397 struct bna *bna = rxf->rx->bna;
2398
2399 /* 8. Execute pending default mode disable command */
2400 if (is_default_disable(rxf->rxmode_pending,
2401 rxf->rxmode_pending_bitmask)) {
2402 /* move default configuration from pending -> active */
2403 default_inactive(rxf->rxmode_pending,
2404 rxf->rxmode_pending_bitmask);
2405 rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
2406 bna->rxf_default_id = BFI_MAX_RXF;
2407
2408 /* Revert VLAN filter */
2409 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
2410 /* Stop RxF vlan filter table redirection */
2411 __rxf_default_function_config(rxf, BNA_STATUS_T_DISABLED);
2412 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_DEFAULT_SET_REQ,
2413 BNA_STATUS_T_DISABLED);
2414 return 1;
2415 }
2416
2417 /* 9. Clear active default mode; move it to pending enable */
2418 if (rxf->rxmode_active & BNA_RXMODE_DEFAULT) {
2419 /* move default configuration from active -> pending */
2420 default_enable(rxf->rxmode_pending,
2421 rxf->rxmode_pending_bitmask);
2422 rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
2423
2424 /* Revert VLAN filter */
2425 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
2426 /* Stop RxF vlan filter table redirection */
2427 __rxf_default_function_config(rxf, BNA_STATUS_T_DISABLED);
2428 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_DEFAULT_SET_REQ,
2429 BNA_STATUS_T_DISABLED);
2430 return 1;
2431 }
2432
2433 return 0;
2434}
2435
2436int
2437rxf_clear_packet_filter_allmulti(struct bna_rxf *rxf)
2438{
2439 /* 10. Execute pending allmulti mode disable command */
2440 if (is_allmulti_disable(rxf->rxmode_pending,
2441 rxf->rxmode_pending_bitmask)) {
2442 /* move allmulti configuration from pending -> active */
2443 allmulti_inactive(rxf->rxmode_pending,
2444 rxf->rxmode_pending_bitmask);
2445 rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
2446 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
2447 BNA_STATUS_T_DISABLED);
2448 return 1;
2449 }
2450
2451 /* 11. Clear active allmulti mode; move it to pending enable */
2452 if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
2453 /* move allmulti configuration from active -> pending */
2454 allmulti_enable(rxf->rxmode_pending,
2455 rxf->rxmode_pending_bitmask);
2456 rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
2457 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
2458 BNA_STATUS_T_DISABLED);
2459 return 1;
2460 }
2461
2462 return 0;
2463}
2464
2465void
2466rxf_reset_packet_filter_ucast(struct bna_rxf *rxf)
2467{
2468 struct list_head *qe;
2469 struct bna_mac *mac;
2470
2471 /* 1. Move active ucast entries to pending_add_q */
2472 while (!list_empty(&rxf->ucast_active_q)) {
2473 bfa_q_deq(&rxf->ucast_active_q, &qe);
2474 bfa_q_qe_init(qe);
2475 list_add_tail(qe, &rxf->ucast_pending_add_q);
2476 }
2477
2478 /* 2. Throw away delete pending ucast entries */
2479 while (!list_empty(&rxf->ucast_pending_del_q)) {
2480 bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
2481 bfa_q_qe_init(qe);
2482 mac = (struct bna_mac *)qe;
2483 bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
2484 }
2485}
2486
2487void
2488rxf_reset_packet_filter_promisc(struct bna_rxf *rxf)
2489{
2490 struct bna *bna = rxf->rx->bna;
2491
2492 /* 6. Clear pending promisc mode disable */
2493 if (is_promisc_disable(rxf->rxmode_pending,
2494 rxf->rxmode_pending_bitmask)) {
2495 promisc_inactive(rxf->rxmode_pending,
2496 rxf->rxmode_pending_bitmask);
2497 rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
2498 bna->rxf_promisc_id = BFI_MAX_RXF;
2499 }
2500
2501 /* 7. Move promisc mode config from active -> pending */
2502 if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
2503 promisc_enable(rxf->rxmode_pending,
2504 rxf->rxmode_pending_bitmask);
2505 rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
2506 }
2507
2508}
2509
2510void
2511rxf_reset_packet_filter_default(struct bna_rxf *rxf)
2512{
2513 struct bna *bna = rxf->rx->bna;
2514
2515 /* 8. Clear pending default mode disable */
2516 if (is_default_disable(rxf->rxmode_pending,
2517 rxf->rxmode_pending_bitmask)) {
2518 default_inactive(rxf->rxmode_pending,
2519 rxf->rxmode_pending_bitmask);
2520 rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
2521 bna->rxf_default_id = BFI_MAX_RXF;
2522 }
2523
2524 /* 9. Move default mode config from active -> pending */
2525 if (rxf->rxmode_active & BNA_RXMODE_DEFAULT) {
2526 default_enable(rxf->rxmode_pending,
2527 rxf->rxmode_pending_bitmask);
2528 rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
2529 }
2530}
2531
2532void
2533rxf_reset_packet_filter_allmulti(struct bna_rxf *rxf)
2534{
2535 /* 10. Clear pending allmulti mode disable */
2536 if (is_allmulti_disable(rxf->rxmode_pending,
2537 rxf->rxmode_pending_bitmask)) {
2538 allmulti_inactive(rxf->rxmode_pending,
2539 rxf->rxmode_pending_bitmask);
2540 rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
2541 }
2542
2543 /* 11. Move allmulti mode config from active -> pending */
2544 if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
2545 allmulti_enable(rxf->rxmode_pending,
2546 rxf->rxmode_pending_bitmask);
2547 rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
2548 }
2549}
2550
2551/**
2552 * Should only be called by bna_rxf_mode_set.
2553 * Helps deciding if h/w configuration is needed or not.
2554 * Returns:
2555 * 0 = no h/w change
2556 * 1 = need h/w change
2557 */
2558int
2559rxf_promisc_enable(struct bna_rxf *rxf)
2560{
2561 struct bna *bna = rxf->rx->bna;
2562 int ret = 0;
2563
2564 /* There can not be any pending disable command */
2565
2566 /* Do nothing if pending enable or already enabled */
2567 if (is_promisc_enable(rxf->rxmode_pending,
2568 rxf->rxmode_pending_bitmask) ||
2569 (rxf->rxmode_active & BNA_RXMODE_PROMISC)) {
2570 /* Schedule enable */
2571 } else {
2572 /* Promisc mode should not be active in the system */
2573 promisc_enable(rxf->rxmode_pending,
2574 rxf->rxmode_pending_bitmask);
2575 bna->rxf_promisc_id = rxf->rxf_id;
2576 ret = 1;
2577 }
2578
2579 return ret;
2580}
2581
2582/**
2583 * Should only be called by bna_rxf_mode_set.
2584 * Helps deciding if h/w configuration is needed or not.
2585 * Returns:
2586 * 0 = no h/w change
2587 * 1 = need h/w change
2588 */
2589int
2590rxf_promisc_disable(struct bna_rxf *rxf)
2591{
2592 struct bna *bna = rxf->rx->bna;
2593 int ret = 0;
2594
2595 /* There can not be any pending disable */
2596
2597 /* Turn off pending enable command , if any */
2598 if (is_promisc_enable(rxf->rxmode_pending,
2599 rxf->rxmode_pending_bitmask)) {
2600 /* Promisc mode should not be active */
2601 /* system promisc state should be pending */
2602 promisc_inactive(rxf->rxmode_pending,
2603 rxf->rxmode_pending_bitmask);
2604 /* Remove the promisc state from the system */
2605 bna->rxf_promisc_id = BFI_MAX_RXF;
2606
2607 /* Schedule disable */
2608 } else if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
2609 /* Promisc mode should be active in the system */
2610 promisc_disable(rxf->rxmode_pending,
2611 rxf->rxmode_pending_bitmask);
2612 ret = 1;
2613
2614 /* Do nothing if already disabled */
2615 } else {
2616 }
2617
2618 return ret;
2619}
2620
2621/**
2622 * Should only be called by bna_rxf_mode_set.
2623 * Helps deciding if h/w configuration is needed or not.
2624 * Returns:
2625 * 0 = no h/w change
2626 * 1 = need h/w change
2627 */
2628int
2629rxf_default_enable(struct bna_rxf *rxf)
2630{
2631 struct bna *bna = rxf->rx->bna;
2632 int ret = 0;
2633
2634 /* There can not be any pending disable command */
2635
2636 /* Do nothing if pending enable or already enabled */
2637 if (is_default_enable(rxf->rxmode_pending,
2638 rxf->rxmode_pending_bitmask) ||
2639 (rxf->rxmode_active & BNA_RXMODE_DEFAULT)) {
2640 /* Schedule enable */
2641 } else {
2642 /* Default mode should not be active in the system */
2643 default_enable(rxf->rxmode_pending,
2644 rxf->rxmode_pending_bitmask);
2645 bna->rxf_default_id = rxf->rxf_id;
2646 ret = 1;
2647 }
2648
2649 return ret;
2650}
2651
2652/**
2653 * Should only be called by bna_rxf_mode_set.
2654 * Helps deciding if h/w configuration is needed or not.
2655 * Returns:
2656 * 0 = no h/w change
2657 * 1 = need h/w change
2658 */
2659int
2660rxf_default_disable(struct bna_rxf *rxf)
2661{
2662 struct bna *bna = rxf->rx->bna;
2663 int ret = 0;
2664
2665 /* There can not be any pending disable */
2666
2667 /* Turn off pending enable command , if any */
2668 if (is_default_enable(rxf->rxmode_pending,
2669 rxf->rxmode_pending_bitmask)) {
2670 /* Promisc mode should not be active */
2671 /* system default state should be pending */
2672 default_inactive(rxf->rxmode_pending,
2673 rxf->rxmode_pending_bitmask);
2674 /* Remove the default state from the system */
2675 bna->rxf_default_id = BFI_MAX_RXF;
2676
2677 /* Schedule disable */
2678 } else if (rxf->rxmode_active & BNA_RXMODE_DEFAULT) {
2679 /* Default mode should be active in the system */
2680 default_disable(rxf->rxmode_pending,
2681 rxf->rxmode_pending_bitmask);
2682 ret = 1;
2683
2684 /* Do nothing if already disabled */
2685 } else {
2686 }
2687
2688 return ret;
2689}
2690
2691/**
2692 * Should only be called by bna_rxf_mode_set.
2693 * Helps deciding if h/w configuration is needed or not.
2694 * Returns:
2695 * 0 = no h/w change
2696 * 1 = need h/w change
2697 */
2698int
2699rxf_allmulti_enable(struct bna_rxf *rxf)
2700{
2701 int ret = 0;
2702
2703 /* There can not be any pending disable command */
2704
2705 /* Do nothing if pending enable or already enabled */
2706 if (is_allmulti_enable(rxf->rxmode_pending,
2707 rxf->rxmode_pending_bitmask) ||
2708 (rxf->rxmode_active & BNA_RXMODE_ALLMULTI)) {
2709 /* Schedule enable */
2710 } else {
2711 allmulti_enable(rxf->rxmode_pending,
2712 rxf->rxmode_pending_bitmask);
2713 ret = 1;
2714 }
2715
2716 return ret;
2717}
2718
2719/**
2720 * Should only be called by bna_rxf_mode_set.
2721 * Helps deciding if h/w configuration is needed or not.
2722 * Returns:
2723 * 0 = no h/w change
2724 * 1 = need h/w change
2725 */
2726int
2727rxf_allmulti_disable(struct bna_rxf *rxf)
2728{
2729 int ret = 0;
2730
2731 /* There can not be any pending disable */
2732
2733 /* Turn off pending enable command , if any */
2734 if (is_allmulti_enable(rxf->rxmode_pending,
2735 rxf->rxmode_pending_bitmask)) {
2736 /* Allmulti mode should not be active */
2737 allmulti_inactive(rxf->rxmode_pending,
2738 rxf->rxmode_pending_bitmask);
2739
2740 /* Schedule disable */
2741 } else if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
2742 allmulti_disable(rxf->rxmode_pending,
2743 rxf->rxmode_pending_bitmask);
2744 ret = 1;
2745 }
2746
2747 return ret;
2748}
2749
2750/* RxF <- bnad */
2751void
2752bna_rx_mcast_delall(struct bna_rx *rx,
2753 void (*cbfn)(struct bnad *, struct bna_rx *,
2754 enum bna_cb_status))
2755{
2756 struct bna_rxf *rxf = &rx->rxf;
2757 struct list_head *qe;
2758 struct bna_mac *mac;
2759 int need_hw_config = 0;
2760
2761 /* Purge all entries from pending_add_q */
2762 while (!list_empty(&rxf->mcast_pending_add_q)) {
2763 bfa_q_deq(&rxf->mcast_pending_add_q, &qe);
2764 mac = (struct bna_mac *)qe;
2765 bfa_q_qe_init(&mac->qe);
2766 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
2767 }
2768
2769 /* Schedule all entries in active_q for deletion */
2770 while (!list_empty(&rxf->mcast_active_q)) {
2771 bfa_q_deq(&rxf->mcast_active_q, &qe);
2772 mac = (struct bna_mac *)qe;
2773 bfa_q_qe_init(&mac->qe);
2774 list_add_tail(&mac->qe, &rxf->mcast_pending_del_q);
2775 need_hw_config = 1;
2776 }
2777
2778 if (need_hw_config) {
2779 rxf->cam_fltr_cbfn = cbfn;
2780 rxf->cam_fltr_cbarg = rx->bna->bnad;
2781 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
2782 return;
2783 }
2784
2785 if (cbfn)
2786 (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
2787}
2788
2789/* RxF <- Rx */
2790void
2791bna_rx_receive_resume(struct bna_rx *rx,
2792 void (*cbfn)(struct bnad *, struct bna_rx *,
2793 enum bna_cb_status))
2794{
2795 struct bna_rxf *rxf = &rx->rxf;
2796
2797 if (rxf->rxf_oper_state == BNA_RXF_OPER_STATE_PAUSED) {
2798 rxf->oper_state_cbfn = cbfn;
2799 rxf->oper_state_cbarg = rx->bna->bnad;
2800 bfa_fsm_send_event(rxf, RXF_E_RESUME);
2801 } else if (cbfn)
2802 (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
2803}
2804
2805void
2806bna_rx_receive_pause(struct bna_rx *rx,
2807 void (*cbfn)(struct bnad *, struct bna_rx *,
2808 enum bna_cb_status))
2809{
2810 struct bna_rxf *rxf = &rx->rxf;
2811
2812 if (rxf->rxf_oper_state == BNA_RXF_OPER_STATE_RUNNING) {
2813 rxf->oper_state_cbfn = cbfn;
2814 rxf->oper_state_cbarg = rx->bna->bnad;
2815 bfa_fsm_send_event(rxf, RXF_E_PAUSE);
2816 } else if (cbfn)
2817 (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
2818}
2819
2820/* RxF <- bnad */
2821enum bna_cb_status
2822bna_rx_ucast_add(struct bna_rx *rx, u8 *addr,
2823 void (*cbfn)(struct bnad *, struct bna_rx *,
2824 enum bna_cb_status))
2825{
2826 struct bna_rxf *rxf = &rx->rxf;
2827 struct list_head *qe;
2828 struct bna_mac *mac;
2829
2830 /* Check if already added */
2831 list_for_each(qe, &rxf->ucast_active_q) {
2832 mac = (struct bna_mac *)qe;
2833 if (BNA_MAC_IS_EQUAL(mac->addr, addr)) {
2834 if (cbfn)
2835 (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
2836 return BNA_CB_SUCCESS;
2837 }
2838 }
2839
2840 /* Check if pending addition */
2841 list_for_each(qe, &rxf->ucast_pending_add_q) {
2842 mac = (struct bna_mac *)qe;
2843 if (BNA_MAC_IS_EQUAL(mac->addr, addr)) {
2844 if (cbfn)
2845 (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
2846 return BNA_CB_SUCCESS;
2847 }
2848 }
2849
2850 mac = bna_ucam_mod_mac_get(&rxf->rx->bna->ucam_mod);
2851 if (mac == NULL)
2852 return BNA_CB_UCAST_CAM_FULL;
2853 bfa_q_qe_init(&mac->qe);
2854 memcpy(mac->addr, addr, ETH_ALEN);
2855 list_add_tail(&mac->qe, &rxf->ucast_pending_add_q);
2856
2857 rxf->cam_fltr_cbfn = cbfn;
2858 rxf->cam_fltr_cbarg = rx->bna->bnad;
2859
2860 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
2861
2862 return BNA_CB_SUCCESS;
2863}
2864
2865/* RxF <- bnad */
2866enum bna_cb_status
2867bna_rx_ucast_del(struct bna_rx *rx, u8 *addr,
2868 void (*cbfn)(struct bnad *, struct bna_rx *,
2869 enum bna_cb_status))
2870{
2871 struct bna_rxf *rxf = &rx->rxf;
2872 struct list_head *qe;
2873 struct bna_mac *mac;
2874
2875 list_for_each(qe, &rxf->ucast_pending_add_q) {
2876 mac = (struct bna_mac *)qe;
2877 if (BNA_MAC_IS_EQUAL(mac->addr, addr)) {
2878 list_del(qe);
2879 bfa_q_qe_init(qe);
2880 bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
2881 if (cbfn)
2882 (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
2883 return BNA_CB_SUCCESS;
2884 }
2885 }
2886
2887 list_for_each(qe, &rxf->ucast_active_q) {
2888 mac = (struct bna_mac *)qe;
2889 if (BNA_MAC_IS_EQUAL(mac->addr, addr)) {
2890 list_del(qe);
2891 bfa_q_qe_init(qe);
2892 list_add_tail(qe, &rxf->ucast_pending_del_q);
2893 rxf->cam_fltr_cbfn = cbfn;
2894 rxf->cam_fltr_cbarg = rx->bna->bnad;
2895 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
2896 return BNA_CB_SUCCESS;
2897 }
2898 }
2899
2900 return BNA_CB_INVALID_MAC;
2901}
2902
2903/* RxF <- bnad */
2904enum bna_cb_status
2905bna_rx_mode_set(struct bna_rx *rx, enum bna_rxmode new_mode,
2906 enum bna_rxmode bitmask,
2907 void (*cbfn)(struct bnad *, struct bna_rx *,
2908 enum bna_cb_status))
2909{
2910 struct bna_rxf *rxf = &rx->rxf;
2911 int need_hw_config = 0;
2912
2913 /* Error checks */
2914
2915 if (is_promisc_enable(new_mode, bitmask)) {
2916 /* If promisc mode is already enabled elsewhere in the system */
2917 if ((rx->bna->rxf_promisc_id != BFI_MAX_RXF) &&
2918 (rx->bna->rxf_promisc_id != rxf->rxf_id))
2919 goto err_return;
2920
2921 /* If default mode is already enabled in the system */
2922 if (rx->bna->rxf_default_id != BFI_MAX_RXF)
2923 goto err_return;
2924
2925 /* Trying to enable promiscuous and default mode together */
2926 if (is_default_enable(new_mode, bitmask))
2927 goto err_return;
2928 }
2929
2930 if (is_default_enable(new_mode, bitmask)) {
2931 /* If default mode is already enabled elsewhere in the system */
2932 if ((rx->bna->rxf_default_id != BFI_MAX_RXF) &&
2933 (rx->bna->rxf_default_id != rxf->rxf_id)) {
2934 goto err_return;
2935 }
2936
2937 /* If promiscuous mode is already enabled in the system */
2938 if (rx->bna->rxf_promisc_id != BFI_MAX_RXF)
2939 goto err_return;
2940 }
2941
2942 /* Process the commands */
2943
2944 if (is_promisc_enable(new_mode, bitmask)) {
2945 if (rxf_promisc_enable(rxf))
2946 need_hw_config = 1;
2947 } else if (is_promisc_disable(new_mode, bitmask)) {
2948 if (rxf_promisc_disable(rxf))
2949 need_hw_config = 1;
2950 }
2951
2952 if (is_default_enable(new_mode, bitmask)) {
2953 if (rxf_default_enable(rxf))
2954 need_hw_config = 1;
2955 } else if (is_default_disable(new_mode, bitmask)) {
2956 if (rxf_default_disable(rxf))
2957 need_hw_config = 1;
2958 }
2959
2960 if (is_allmulti_enable(new_mode, bitmask)) {
2961 if (rxf_allmulti_enable(rxf))
2962 need_hw_config = 1;
2963 } else if (is_allmulti_disable(new_mode, bitmask)) {
2964 if (rxf_allmulti_disable(rxf))
2965 need_hw_config = 1;
2966 }
2967
2968 /* Trigger h/w if needed */
2969
2970 if (need_hw_config) {
2971 rxf->cam_fltr_cbfn = cbfn;
2972 rxf->cam_fltr_cbarg = rx->bna->bnad;
2973 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
2974 } else if (cbfn)
2975 (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
2976
2977 return BNA_CB_SUCCESS;
2978
2979err_return:
2980 return BNA_CB_FAIL;
2981}
2982
2983/* RxF <- bnad */
2984void
2985bna_rx_rss_enable(struct bna_rx *rx)
2986{
2987 struct bna_rxf *rxf = &rx->rxf;
2988
2989 rxf->rxf_flags |= BNA_RXF_FL_RSS_CONFIG_PENDING;
2990 rxf->rss_status = BNA_STATUS_T_ENABLED;
2991 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
2992}
2993
2994/* RxF <- bnad */
2995void
2996bna_rx_rss_disable(struct bna_rx *rx)
2997{
2998 struct bna_rxf *rxf = &rx->rxf;
2999
3000 rxf->rxf_flags |= BNA_RXF_FL_RSS_CONFIG_PENDING;
3001 rxf->rss_status = BNA_STATUS_T_DISABLED;
3002 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
3003}
3004
3005/* RxF <- bnad */
3006void
3007bna_rx_rss_reconfig(struct bna_rx *rx, struct bna_rxf_rss *rss_config)
3008{
3009 struct bna_rxf *rxf = &rx->rxf;
3010 rxf->rxf_flags |= BNA_RXF_FL_RSS_CONFIG_PENDING;
3011 rxf->rss_status = BNA_STATUS_T_ENABLED;
3012 rxf->rss_cfg = *rss_config;
3013 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
3014}
3015
3016void
3017/* RxF <- bnad */
3018bna_rx_vlanfilter_enable(struct bna_rx *rx)
3019{
3020 struct bna_rxf *rxf = &rx->rxf;
3021
3022 if (rxf->vlan_filter_status == BNA_STATUS_T_DISABLED) {
3023 rxf->rxf_flags |= BNA_RXF_FL_VLAN_CONFIG_PENDING;
3024 rxf->vlan_filter_status = BNA_STATUS_T_ENABLED;
3025 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
3026 }
3027}
3028
3029/* RxF <- bnad */
3030void
3031bna_rx_vlanfilter_disable(struct bna_rx *rx)
3032{
3033 struct bna_rxf *rxf = &rx->rxf;
3034
3035 if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED) {
3036 rxf->rxf_flags |= BNA_RXF_FL_VLAN_CONFIG_PENDING;
3037 rxf->vlan_filter_status = BNA_STATUS_T_DISABLED;
3038 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
3039 }
3040}
3041
3042/* Rx */
3043
3044struct bna_rxp *
3045bna_rx_get_rxp(struct bna_rx *rx, int vector)
3046{
3047 struct bna_rxp *rxp;
3048 struct list_head *qe;
3049
3050 list_for_each(qe, &rx->rxp_q) {
3051 rxp = (struct bna_rxp *)qe;
3052 if (rxp->vector == vector)
3053 return rxp;
3054 }
3055 return NULL;
3056}
3057
3058/*
3059 * bna_rx_rss_rit_set()
3060 * Sets the Q ids for the specified msi-x vectors in the RIT.
3061 * Maximum rit size supported is 64, which should be the max size of the
3062 * vectors array.
3063 */
3064
3065void
3066bna_rx_rss_rit_set(struct bna_rx *rx, unsigned int *vectors, int nvectors)
3067{
3068 int i;
3069 struct bna_rxp *rxp;
3070 struct bna_rxq *q0 = NULL, *q1 = NULL;
3071 struct bna *bna;
3072 struct bna_rxf *rxf;
3073
3074 /* Build the RIT contents for this RX */
3075 bna = rx->bna;
3076
3077 rxf = &rx->rxf;
3078 for (i = 0; i < nvectors; i++) {
3079 rxp = bna_rx_get_rxp(rx, vectors[i]);
3080
3081 GET_RXQS(rxp, q0, q1);
3082 rxf->rit_segment->rit[i].large_rxq_id = q0->rxq_id;
3083 rxf->rit_segment->rit[i].small_rxq_id = (q1 ? q1->rxq_id : 0);
3084 }
3085
3086 rxf->rit_segment->rit_size = nvectors;
3087
3088 /* Subsequent call to enable/reconfig RSS will update the RIT in h/w */
3089}
3090
3091/* Rx <- bnad */
3092void
3093bna_rx_coalescing_timeo_set(struct bna_rx *rx, int coalescing_timeo)
3094{
3095 struct bna_rxp *rxp;
3096 struct list_head *qe;
3097
3098 list_for_each(qe, &rx->rxp_q) {
3099 rxp = (struct bna_rxp *)qe;
3100 rxp->cq.ccb->rx_coalescing_timeo = coalescing_timeo;
3101 bna_ib_coalescing_timeo_set(rxp->cq.ib, coalescing_timeo);
3102 }
3103}
3104
3105/* Rx <- bnad */
3106void
3107bna_rx_dim_reconfig(struct bna *bna, u32 vector[][BNA_BIAS_T_MAX])
3108{
3109 int i, j;
3110
3111 for (i = 0; i < BNA_LOAD_T_MAX; i++)
3112 for (j = 0; j < BNA_BIAS_T_MAX; j++)
3113 bna->rx_mod.dim_vector[i][j] = vector[i][j];
3114}
3115
3116/* Rx <- bnad */
3117void
3118bna_rx_dim_update(struct bna_ccb *ccb)
3119{
3120 struct bna *bna = ccb->cq->rx->bna;
3121 u32 load, bias;
3122 u32 pkt_rt, small_rt, large_rt;
3123 u8 coalescing_timeo;
3124
3125 if ((ccb->pkt_rate.small_pkt_cnt == 0) &&
3126 (ccb->pkt_rate.large_pkt_cnt == 0))
3127 return;
3128
3129 /* Arrive at preconfigured coalescing timeo value based on pkt rate */
3130
3131 small_rt = ccb->pkt_rate.small_pkt_cnt;
3132 large_rt = ccb->pkt_rate.large_pkt_cnt;
3133
3134 pkt_rt = small_rt + large_rt;
3135
3136 if (pkt_rt < BNA_PKT_RATE_10K)
3137 load = BNA_LOAD_T_LOW_4;
3138 else if (pkt_rt < BNA_PKT_RATE_20K)
3139 load = BNA_LOAD_T_LOW_3;
3140 else if (pkt_rt < BNA_PKT_RATE_30K)
3141 load = BNA_LOAD_T_LOW_2;
3142 else if (pkt_rt < BNA_PKT_RATE_40K)
3143 load = BNA_LOAD_T_LOW_1;
3144 else if (pkt_rt < BNA_PKT_RATE_50K)
3145 load = BNA_LOAD_T_HIGH_1;
3146 else if (pkt_rt < BNA_PKT_RATE_60K)
3147 load = BNA_LOAD_T_HIGH_2;
3148 else if (pkt_rt < BNA_PKT_RATE_80K)
3149 load = BNA_LOAD_T_HIGH_3;
3150 else
3151 load = BNA_LOAD_T_HIGH_4;
3152
3153 if (small_rt > (large_rt << 1))
3154 bias = 0;
3155 else
3156 bias = 1;
3157
3158 ccb->pkt_rate.small_pkt_cnt = 0;
3159 ccb->pkt_rate.large_pkt_cnt = 0;
3160
3161 coalescing_timeo = bna->rx_mod.dim_vector[load][bias];
3162 ccb->rx_coalescing_timeo = coalescing_timeo;
3163
3164 /* Set it to IB */
3165 bna_ib_coalescing_timeo_set(ccb->cq->ib, coalescing_timeo);
3166}
3167
3168/* Tx */
3169/* TX <- bnad */
3170enum bna_cb_status
3171bna_tx_prio_set(struct bna_tx *tx, int prio,
3172 void (*cbfn)(struct bnad *, struct bna_tx *,
3173 enum bna_cb_status))
3174{
3175 if (tx->flags & BNA_TX_F_PRIO_LOCK)
3176 return BNA_CB_FAIL;
3177 else {
3178 tx->prio_change_cbfn = cbfn;
3179 bna_tx_prio_changed(tx, prio);
3180 }
3181
3182 return BNA_CB_SUCCESS;
3183}
3184
3185/* TX <- bnad */
3186void
3187bna_tx_coalescing_timeo_set(struct bna_tx *tx, int coalescing_timeo)
3188{
3189 struct bna_txq *txq;
3190 struct list_head *qe;
3191
3192 list_for_each(qe, &tx->txq_q) {
3193 txq = (struct bna_txq *)qe;
3194 bna_ib_coalescing_timeo_set(txq->ib, coalescing_timeo);
3195 }
3196}
3197
3198/*
3199 * Private data
3200 */
3201
3202struct bna_ritseg_pool_cfg {
3203 u32 pool_size;
3204 u32 pool_entry_size;
3205};
3206init_ritseg_pool(ritseg_pool_cfg);
3207
3208/*
3209 * Private functions
3210 */
3211static void
3212bna_ucam_mod_init(struct bna_ucam_mod *ucam_mod, struct bna *bna,
3213 struct bna_res_info *res_info)
3214{
3215 int i;
3216
3217 ucam_mod->ucmac = (struct bna_mac *)
3218 res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.mdl[0].kva;
3219
3220 INIT_LIST_HEAD(&ucam_mod->free_q);
3221 for (i = 0; i < BFI_MAX_UCMAC; i++) {
3222 bfa_q_qe_init(&ucam_mod->ucmac[i].qe);
3223 list_add_tail(&ucam_mod->ucmac[i].qe, &ucam_mod->free_q);
3224 }
3225
3226 ucam_mod->bna = bna;
3227}
3228
3229static void
3230bna_ucam_mod_uninit(struct bna_ucam_mod *ucam_mod)
3231{
3232 struct list_head *qe;
3233 int i = 0;
3234
3235 list_for_each(qe, &ucam_mod->free_q)
3236 i++;
3237
3238 ucam_mod->bna = NULL;
3239}
3240
3241static void
3242bna_mcam_mod_init(struct bna_mcam_mod *mcam_mod, struct bna *bna,
3243 struct bna_res_info *res_info)
3244{
3245 int i;
3246
3247 mcam_mod->mcmac = (struct bna_mac *)
3248 res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.mdl[0].kva;
3249
3250 INIT_LIST_HEAD(&mcam_mod->free_q);
3251 for (i = 0; i < BFI_MAX_MCMAC; i++) {
3252 bfa_q_qe_init(&mcam_mod->mcmac[i].qe);
3253 list_add_tail(&mcam_mod->mcmac[i].qe, &mcam_mod->free_q);
3254 }
3255
3256 mcam_mod->bna = bna;
3257}
3258
3259static void
3260bna_mcam_mod_uninit(struct bna_mcam_mod *mcam_mod)
3261{
3262 struct list_head *qe;
3263 int i = 0;
3264
3265 list_for_each(qe, &mcam_mod->free_q)
3266 i++;
3267
3268 mcam_mod->bna = NULL;
3269}
3270
3271static void
3272bna_rit_mod_init(struct bna_rit_mod *rit_mod,
3273 struct bna_res_info *res_info)
3274{
3275 int i;
3276 int j;
3277 int count;
3278 int offset;
3279
3280 rit_mod->rit = (struct bna_rit_entry *)
3281 res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.mdl[0].kva;
3282 rit_mod->rit_segment = (struct bna_rit_segment *)
3283 res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.mdl[0].kva;
3284
3285 count = 0;
3286 offset = 0;
3287 for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
3288 INIT_LIST_HEAD(&rit_mod->rit_seg_pool[i]);
3289 for (j = 0; j < ritseg_pool_cfg[i].pool_size; j++) {
3290 bfa_q_qe_init(&rit_mod->rit_segment[count].qe);
3291 rit_mod->rit_segment[count].max_rit_size =
3292 ritseg_pool_cfg[i].pool_entry_size;
3293 rit_mod->rit_segment[count].rit_offset = offset;
3294 rit_mod->rit_segment[count].rit =
3295 &rit_mod->rit[offset];
3296 list_add_tail(&rit_mod->rit_segment[count].qe,
3297 &rit_mod->rit_seg_pool[i]);
3298 count++;
3299 offset += ritseg_pool_cfg[i].pool_entry_size;
3300 }
3301 }
3302}
3303
3304static void
3305bna_rit_mod_uninit(struct bna_rit_mod *rit_mod)
3306{
3307 struct bna_rit_segment *rit_segment;
3308 struct list_head *qe;
3309 int i;
3310 int j;
3311
3312 for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
3313 j = 0;
3314 list_for_each(qe, &rit_mod->rit_seg_pool[i]) {
3315 rit_segment = (struct bna_rit_segment *)qe;
3316 j++;
3317 }
3318 }
3319}
3320
3321/*
3322 * Public functions
3323 */
3324
3325/* Called during probe(), before calling bna_init() */
3326void
3327bna_res_req(struct bna_res_info *res_info)
3328{
3329 bna_adv_res_req(res_info);
3330
3331 /* DMA memory for retrieving IOC attributes */
3332 res_info[BNA_RES_MEM_T_ATTR].res_type = BNA_RES_T_MEM;
3333 res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
3334 res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.num = 1;
3335 res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.len =
3336 ALIGN(bfa_ioc_meminfo(), PAGE_SIZE);
3337
3338 /* DMA memory for index segment of an IB */
3339 res_info[BNA_RES_MEM_T_IBIDX].res_type = BNA_RES_T_MEM;
3340 res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
3341 res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.len =
3342 BFI_IBIDX_SIZE * BFI_IBIDX_MAX_SEGSIZE;
3343 res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.num = BFI_MAX_IB;
3344
3345 /* Virtual memory for IB objects - stored by IB module */
3346 res_info[BNA_RES_MEM_T_IB_ARRAY].res_type = BNA_RES_T_MEM;
3347 res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.mem_type =
3348 BNA_MEM_T_KVA;
3349 res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.num = 1;
3350 res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.len =
3351 BFI_MAX_IB * sizeof(struct bna_ib);
3352
3353 /* Virtual memory for intr objects - stored by IB module */
3354 res_info[BNA_RES_MEM_T_INTR_ARRAY].res_type = BNA_RES_T_MEM;
3355 res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.mem_type =
3356 BNA_MEM_T_KVA;
3357 res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.num = 1;
3358 res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.len =
3359 BFI_MAX_IB * sizeof(struct bna_intr);
3360
3361 /* Virtual memory for idx_seg objects - stored by IB module */
3362 res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_type = BNA_RES_T_MEM;
3363 res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.mem_type =
3364 BNA_MEM_T_KVA;
3365 res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.num = 1;
3366 res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.len =
3367 BFI_IBIDX_TOTAL_SEGS * sizeof(struct bna_ibidx_seg);
3368
3369 /* Virtual memory for Tx objects - stored by Tx module */
3370 res_info[BNA_RES_MEM_T_TX_ARRAY].res_type = BNA_RES_T_MEM;
3371 res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.mem_type =
3372 BNA_MEM_T_KVA;
3373 res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.num = 1;
3374 res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.len =
3375 BFI_MAX_TXQ * sizeof(struct bna_tx);
3376
3377 /* Virtual memory for TxQ - stored by Tx module */
3378 res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_type = BNA_RES_T_MEM;
3379 res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.mem_type =
3380 BNA_MEM_T_KVA;
3381 res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.num = 1;
3382 res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.len =
3383 BFI_MAX_TXQ * sizeof(struct bna_txq);
3384
3385 /* Virtual memory for Rx objects - stored by Rx module */
3386 res_info[BNA_RES_MEM_T_RX_ARRAY].res_type = BNA_RES_T_MEM;
3387 res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.mem_type =
3388 BNA_MEM_T_KVA;
3389 res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.num = 1;
3390 res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.len =
3391 BFI_MAX_RXQ * sizeof(struct bna_rx);
3392
3393 /* Virtual memory for RxPath - stored by Rx module */
3394 res_info[BNA_RES_MEM_T_RXP_ARRAY].res_type = BNA_RES_T_MEM;
3395 res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.mem_type =
3396 BNA_MEM_T_KVA;
3397 res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.num = 1;
3398 res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.len =
3399 BFI_MAX_RXQ * sizeof(struct bna_rxp);
3400
3401 /* Virtual memory for RxQ - stored by Rx module */
3402 res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_type = BNA_RES_T_MEM;
3403 res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.mem_type =
3404 BNA_MEM_T_KVA;
3405 res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.num = 1;
3406 res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.len =
3407 BFI_MAX_RXQ * sizeof(struct bna_rxq);
3408
3409 /* Virtual memory for Unicast MAC address - stored by ucam module */
3410 res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_type = BNA_RES_T_MEM;
3411 res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.mem_type =
3412 BNA_MEM_T_KVA;
3413 res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.num = 1;
3414 res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.len =
3415 BFI_MAX_UCMAC * sizeof(struct bna_mac);
3416
3417 /* Virtual memory for Multicast MAC address - stored by mcam module */
3418 res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_type = BNA_RES_T_MEM;
3419 res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.mem_type =
3420 BNA_MEM_T_KVA;
3421 res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.num = 1;
3422 res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.len =
3423 BFI_MAX_MCMAC * sizeof(struct bna_mac);
3424
3425 /* Virtual memory for RIT entries */
3426 res_info[BNA_RES_MEM_T_RIT_ENTRY].res_type = BNA_RES_T_MEM;
3427 res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.mem_type =
3428 BNA_MEM_T_KVA;
3429 res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.num = 1;
3430 res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.len =
3431 BFI_MAX_RIT_SIZE * sizeof(struct bna_rit_entry);
3432
3433 /* Virtual memory for RIT segment table */
3434 res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_type = BNA_RES_T_MEM;
3435 res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.mem_type =
3436 BNA_MEM_T_KVA;
3437 res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.num = 1;
3438 res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.len =
3439 BFI_RIT_TOTAL_SEGS * sizeof(struct bna_rit_segment);
3440
3441 /* Interrupt resource for mailbox interrupt */
3442 res_info[BNA_RES_INTR_T_MBOX].res_type = BNA_RES_T_INTR;
3443 res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.intr_type =
3444 BNA_INTR_T_MSIX;
3445 res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.num = 1;
3446}
3447
3448/* Called during probe() */
3449void
3450bna_init(struct bna *bna, struct bnad *bnad, struct bfa_pcidev *pcidev,
3451 struct bna_res_info *res_info)
3452{
3453 bna->bnad = bnad;
3454 bna->pcidev = *pcidev;
3455
3456 bna->stats.hw_stats = (struct bfi_ll_stats *)
3457 res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mdl[0].kva;
3458 bna->hw_stats_dma.msb =
3459 res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mdl[0].dma.msb;
3460 bna->hw_stats_dma.lsb =
3461 res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mdl[0].dma.lsb;
3462 bna->stats.sw_stats = (struct bna_sw_stats *)
3463 res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.mdl[0].kva;
3464
3465 bna->regs.page_addr = bna->pcidev.pci_bar_kva +
3466 reg_offset[bna->pcidev.pci_func].page_addr;
3467 bna->regs.fn_int_status = bna->pcidev.pci_bar_kva +
3468 reg_offset[bna->pcidev.pci_func].fn_int_status;
3469 bna->regs.fn_int_mask = bna->pcidev.pci_bar_kva +
3470 reg_offset[bna->pcidev.pci_func].fn_int_mask;
3471
3472 if (bna->pcidev.pci_func < 3)
3473 bna->port_num = 0;
3474 else
3475 bna->port_num = 1;
3476
3477 /* Also initializes diag, cee, sfp, phy_port and mbox_mod */
3478 bna_device_init(&bna->device, bna, res_info);
3479
3480 bna_port_init(&bna->port, bna);
3481
3482 bna_tx_mod_init(&bna->tx_mod, bna, res_info);
3483
3484 bna_rx_mod_init(&bna->rx_mod, bna, res_info);
3485
3486 bna_ib_mod_init(&bna->ib_mod, bna, res_info);
3487
3488 bna_rit_mod_init(&bna->rit_mod, res_info);
3489
3490 bna_ucam_mod_init(&bna->ucam_mod, bna, res_info);
3491
3492 bna_mcam_mod_init(&bna->mcam_mod, bna, res_info);
3493
3494 bna->rxf_default_id = BFI_MAX_RXF;
3495 bna->rxf_promisc_id = BFI_MAX_RXF;
3496
3497 /* Mbox q element for posting stat request to f/w */
3498 bfa_q_qe_init(&bna->mbox_qe.qe);
3499}
3500
3501void
3502bna_uninit(struct bna *bna)
3503{
3504 bna_mcam_mod_uninit(&bna->mcam_mod);
3505
3506 bna_ucam_mod_uninit(&bna->ucam_mod);
3507
3508 bna_rit_mod_uninit(&bna->rit_mod);
3509
3510 bna_ib_mod_uninit(&bna->ib_mod);
3511
3512 bna_rx_mod_uninit(&bna->rx_mod);
3513
3514 bna_tx_mod_uninit(&bna->tx_mod);
3515
3516 bna_port_uninit(&bna->port);
3517
3518 bna_device_uninit(&bna->device);
3519
3520 bna->bnad = NULL;
3521}
3522
3523struct bna_mac *
3524bna_ucam_mod_mac_get(struct bna_ucam_mod *ucam_mod)
3525{
3526 struct list_head *qe;
3527
3528 if (list_empty(&ucam_mod->free_q))
3529 return NULL;
3530
3531 bfa_q_deq(&ucam_mod->free_q, &qe);
3532
3533 return (struct bna_mac *)qe;
3534}
3535
3536void
3537bna_ucam_mod_mac_put(struct bna_ucam_mod *ucam_mod, struct bna_mac *mac)
3538{
3539 list_add_tail(&mac->qe, &ucam_mod->free_q);
3540}
3541
3542struct bna_mac *
3543bna_mcam_mod_mac_get(struct bna_mcam_mod *mcam_mod)
3544{
3545 struct list_head *qe;
3546
3547 if (list_empty(&mcam_mod->free_q))
3548 return NULL;
3549
3550 bfa_q_deq(&mcam_mod->free_q, &qe);
3551
3552 return (struct bna_mac *)qe;
3553}
3554
3555void
3556bna_mcam_mod_mac_put(struct bna_mcam_mod *mcam_mod, struct bna_mac *mac)
3557{
3558 list_add_tail(&mac->qe, &mcam_mod->free_q);
3559}
3560
3561/**
3562 * Note: This should be called in the same locking context as the call to
3563 * bna_rit_mod_seg_get()
3564 */
3565int
3566bna_rit_mod_can_satisfy(struct bna_rit_mod *rit_mod, int seg_size)
3567{
3568 int i;
3569
3570 /* Select the pool for seg_size */
3571 for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
3572 if (seg_size <= ritseg_pool_cfg[i].pool_entry_size)
3573 break;
3574 }
3575
3576 if (i == BFI_RIT_SEG_TOTAL_POOLS)
3577 return 0;
3578
3579 if (list_empty(&rit_mod->rit_seg_pool[i]))
3580 return 0;
3581
3582 return 1;
3583}
3584
3585struct bna_rit_segment *
3586bna_rit_mod_seg_get(struct bna_rit_mod *rit_mod, int seg_size)
3587{
3588 struct bna_rit_segment *seg;
3589 struct list_head *qe;
3590 int i;
3591
3592 /* Select the pool for seg_size */
3593 for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
3594 if (seg_size <= ritseg_pool_cfg[i].pool_entry_size)
3595 break;
3596 }
3597
3598 if (i == BFI_RIT_SEG_TOTAL_POOLS)
3599 return NULL;
3600
3601 if (list_empty(&rit_mod->rit_seg_pool[i]))
3602 return NULL;
3603
3604 bfa_q_deq(&rit_mod->rit_seg_pool[i], &qe);
3605 seg = (struct bna_rit_segment *)qe;
3606 bfa_q_qe_init(&seg->qe);
3607 seg->rit_size = seg_size;
3608
3609 return seg;
3610}
3611
3612void
3613bna_rit_mod_seg_put(struct bna_rit_mod *rit_mod,
3614 struct bna_rit_segment *seg)
3615{
3616 int i;
3617
3618 /* Select the pool for seg->max_rit_size */
3619 for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
3620 if (seg->max_rit_size == ritseg_pool_cfg[i].pool_entry_size)
3621 break;
3622 }
3623
3624 seg->rit_size = 0;
3625 list_add_tail(&seg->qe, &rit_mod->rit_seg_pool[i]);
3626}
diff --git a/drivers/net/bna/bna_hw.h b/drivers/net/bna/bna_hw.h
new file mode 100644
index 000000000000..67eb376c5c7e
--- /dev/null
+++ b/drivers/net/bna/bna_hw.h
@@ -0,0 +1,1491 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 *
18 * File for interrupt macros and functions
19 */
20
21#ifndef __BNA_HW_H__
22#define __BNA_HW_H__
23
24#include "bfi_ctreg.h"
25
26/**
27 *
28 * SW imposed limits
29 *
30 */
31
32#ifndef BNA_BIOS_BUILD
33
34#define BFI_MAX_TXQ 64
35#define BFI_MAX_RXQ 64
36#define BFI_MAX_RXF 64
37#define BFI_MAX_IB 128
38#define BFI_MAX_RIT_SIZE 256
39#define BFI_RSS_RIT_SIZE 64
40#define BFI_NONRSS_RIT_SIZE 1
41#define BFI_MAX_UCMAC 256
42#define BFI_MAX_MCMAC 512
43#define BFI_IBIDX_SIZE 4
44#define BFI_MAX_VLAN 4095
45
46/**
47 * There are 2 free IB index pools:
48 * pool1: 120 segments of 1 index each
49 * pool8: 1 segment of 8 indexes
50 */
51#define BFI_IBIDX_POOL1_SIZE 116
52#define BFI_IBIDX_POOL1_ENTRY_SIZE 1
53#define BFI_IBIDX_POOL2_SIZE 2
54#define BFI_IBIDX_POOL2_ENTRY_SIZE 2
55#define BFI_IBIDX_POOL8_SIZE 1
56#define BFI_IBIDX_POOL8_ENTRY_SIZE 8
57#define BFI_IBIDX_TOTAL_POOLS 3
58#define BFI_IBIDX_TOTAL_SEGS 119 /* (POOL1 + POOL2 + POOL8)_SIZE */
59#define BFI_IBIDX_MAX_SEGSIZE 8
60#define init_ibidx_pool(name) \
61static struct bna_ibidx_pool name[BFI_IBIDX_TOTAL_POOLS] = \
62{ \
63 { BFI_IBIDX_POOL1_SIZE, BFI_IBIDX_POOL1_ENTRY_SIZE }, \
64 { BFI_IBIDX_POOL2_SIZE, BFI_IBIDX_POOL2_ENTRY_SIZE }, \
65 { BFI_IBIDX_POOL8_SIZE, BFI_IBIDX_POOL8_ENTRY_SIZE } \
66}
67
68/**
69 * There are 2 free RIT segment pools:
70 * Pool1: 192 segments of 1 RIT entry each
71 * Pool2: 1 segment of 64 RIT entry
72 */
73#define BFI_RIT_SEG_POOL1_SIZE 192
74#define BFI_RIT_SEG_POOL1_ENTRY_SIZE 1
75#define BFI_RIT_SEG_POOLRSS_SIZE 1
76#define BFI_RIT_SEG_POOLRSS_ENTRY_SIZE 64
77#define BFI_RIT_SEG_TOTAL_POOLS 2
78#define BFI_RIT_TOTAL_SEGS 193 /* POOL1_SIZE + POOLRSS_SIZE */
79#define init_ritseg_pool(name) \
80static struct bna_ritseg_pool_cfg name[BFI_RIT_SEG_TOTAL_POOLS] = \
81{ \
82 { BFI_RIT_SEG_POOL1_SIZE, BFI_RIT_SEG_POOL1_ENTRY_SIZE }, \
83 { BFI_RIT_SEG_POOLRSS_SIZE, BFI_RIT_SEG_POOLRSS_ENTRY_SIZE } \
84}
85
86#else /* BNA_BIOS_BUILD */
87
88#define BFI_MAX_TXQ 1
89#define BFI_MAX_RXQ 1
90#define BFI_MAX_RXF 1
91#define BFI_MAX_IB 2
92#define BFI_MAX_RIT_SIZE 2
93#define BFI_RSS_RIT_SIZE 64
94#define BFI_NONRSS_RIT_SIZE 1
95#define BFI_MAX_UCMAC 1
96#define BFI_MAX_MCMAC 8
97#define BFI_IBIDX_SIZE 4
98#define BFI_MAX_VLAN 4095
99/* There is one free pool: 2 segments of 1 index each */
100#define BFI_IBIDX_POOL1_SIZE 2
101#define BFI_IBIDX_POOL1_ENTRY_SIZE 1
102#define BFI_IBIDX_TOTAL_POOLS 1
103#define BFI_IBIDX_TOTAL_SEGS 2 /* POOL1_SIZE */
104#define BFI_IBIDX_MAX_SEGSIZE 1
105#define init_ibidx_pool(name) \
106static struct bna_ibidx_pool name[BFI_IBIDX_TOTAL_POOLS] = \
107{ \
108 { BFI_IBIDX_POOL1_SIZE, BFI_IBIDX_POOL1_ENTRY_SIZE } \
109}
110
111#define BFI_RIT_SEG_POOL1_SIZE 1
112#define BFI_RIT_SEG_POOL1_ENTRY_SIZE 1
113#define BFI_RIT_SEG_TOTAL_POOLS 1
114#define BFI_RIT_TOTAL_SEGS 1 /* POOL1_SIZE */
115#define init_ritseg_pool(name) \
116static struct bna_ritseg_pool_cfg name[BFI_RIT_SEG_TOTAL_POOLS] = \
117{ \
118 { BFI_RIT_SEG_POOL1_SIZE, BFI_RIT_SEG_POOL1_ENTRY_SIZE } \
119}
120
121#endif /* BNA_BIOS_BUILD */
122
123#define BFI_RSS_HASH_KEY_LEN 10
124
125#define BFI_COALESCING_TIMER_UNIT 5 /* 5us */
126#define BFI_MAX_COALESCING_TIMEO 0xFF /* in 5us units */
127#define BFI_MAX_INTERPKT_COUNT 0xFF
128#define BFI_MAX_INTERPKT_TIMEO 0xF /* in 0.5us units */
129#define BFI_TX_COALESCING_TIMEO 20 /* 20 * 5 = 100us */
130#define BFI_TX_INTERPKT_COUNT 32
131#define BFI_RX_COALESCING_TIMEO 12 /* 12 * 5 = 60us */
132#define BFI_RX_INTERPKT_COUNT 6 /* Pkt Cnt = 6 */
133#define BFI_RX_INTERPKT_TIMEO 3 /* 3 * 0.5 = 1.5us */
134
135#define BFI_TXQ_WI_SIZE 64 /* bytes */
136#define BFI_RXQ_WI_SIZE 8 /* bytes */
137#define BFI_CQ_WI_SIZE 16 /* bytes */
138#define BFI_TX_MAX_WRR_QUOTA 0xFFF
139
140#define BFI_TX_MAX_VECTORS_PER_WI 4
141#define BFI_TX_MAX_VECTORS_PER_PKT 0xFF
142#define BFI_TX_MAX_DATA_PER_VECTOR 0xFFFF
143#define BFI_TX_MAX_DATA_PER_PKT 0xFFFFFF
144
145/* Small Q buffer size */
146#define BFI_SMALL_RXBUF_SIZE 128
147
148/* Defined separately since BFA_FLASH_DMA_BUF_SZ is in bfa_flash.c */
149#define BFI_FLASH_DMA_BUF_SZ 0x010000 /* 64K DMA */
150#define BFI_HW_STATS_SIZE 0x4000 /* 16K DMA */
151
152/**
153 *
154 * HW register offsets, macros
155 *
156 */
157
158/* DMA Block Register Host Window Start Address */
159#define DMA_BLK_REG_ADDR 0x00013000
160
161/* DMA Block Internal Registers */
162#define DMA_CTRL_REG0 (DMA_BLK_REG_ADDR + 0x000)
163#define DMA_CTRL_REG1 (DMA_BLK_REG_ADDR + 0x004)
164#define DMA_ERR_INT_STATUS (DMA_BLK_REG_ADDR + 0x008)
165#define DMA_ERR_INT_ENABLE (DMA_BLK_REG_ADDR + 0x00c)
166#define DMA_ERR_INT_STATUS_SET (DMA_BLK_REG_ADDR + 0x010)
167
168/* APP Block Register Address Offset from BAR0 */
169#define APP_BLK_REG_ADDR 0x00014000
170
171/* Host Function Interrupt Mask Registers */
172#define HOSTFN0_INT_MASK (APP_BLK_REG_ADDR + 0x004)
173#define HOSTFN1_INT_MASK (APP_BLK_REG_ADDR + 0x104)
174#define HOSTFN2_INT_MASK (APP_BLK_REG_ADDR + 0x304)
175#define HOSTFN3_INT_MASK (APP_BLK_REG_ADDR + 0x404)
176
177/**
178 * Host Function PCIe Error Registers
179 * Duplicates "Correctable" & "Uncorrectable"
180 * registers in PCIe Config space.
181 */
182#define FN0_PCIE_ERR_REG (APP_BLK_REG_ADDR + 0x014)
183#define FN1_PCIE_ERR_REG (APP_BLK_REG_ADDR + 0x114)
184#define FN2_PCIE_ERR_REG (APP_BLK_REG_ADDR + 0x314)
185#define FN3_PCIE_ERR_REG (APP_BLK_REG_ADDR + 0x414)
186
187/* Host Function Error Type Status Registers */
188#define FN0_ERR_TYPE_STATUS_REG (APP_BLK_REG_ADDR + 0x018)
189#define FN1_ERR_TYPE_STATUS_REG (APP_BLK_REG_ADDR + 0x118)
190#define FN2_ERR_TYPE_STATUS_REG (APP_BLK_REG_ADDR + 0x318)
191#define FN3_ERR_TYPE_STATUS_REG (APP_BLK_REG_ADDR + 0x418)
192
193/* Host Function Error Type Mask Registers */
194#define FN0_ERR_TYPE_MSK_STATUS_REG (APP_BLK_REG_ADDR + 0x01c)
195#define FN1_ERR_TYPE_MSK_STATUS_REG (APP_BLK_REG_ADDR + 0x11c)
196#define FN2_ERR_TYPE_MSK_STATUS_REG (APP_BLK_REG_ADDR + 0x31c)
197#define FN3_ERR_TYPE_MSK_STATUS_REG (APP_BLK_REG_ADDR + 0x41c)
198
199/* Catapult Host Semaphore Status Registers (App block) */
200#define HOST_SEM_STS0_REG (APP_BLK_REG_ADDR + 0x630)
201#define HOST_SEM_STS1_REG (APP_BLK_REG_ADDR + 0x634)
202#define HOST_SEM_STS2_REG (APP_BLK_REG_ADDR + 0x638)
203#define HOST_SEM_STS3_REG (APP_BLK_REG_ADDR + 0x63c)
204#define HOST_SEM_STS4_REG (APP_BLK_REG_ADDR + 0x640)
205#define HOST_SEM_STS5_REG (APP_BLK_REG_ADDR + 0x644)
206#define HOST_SEM_STS6_REG (APP_BLK_REG_ADDR + 0x648)
207#define HOST_SEM_STS7_REG (APP_BLK_REG_ADDR + 0x64c)
208
209/* PCIe Misc Register */
210#define PCIE_MISC_REG (APP_BLK_REG_ADDR + 0x200)
211
212/* Temp Sensor Control Registers */
213#define TEMPSENSE_CNTL_REG (APP_BLK_REG_ADDR + 0x250)
214#define TEMPSENSE_STAT_REG (APP_BLK_REG_ADDR + 0x254)
215
216/* APP Block local error registers */
217#define APP_LOCAL_ERR_STAT (APP_BLK_REG_ADDR + 0x258)
218#define APP_LOCAL_ERR_MSK (APP_BLK_REG_ADDR + 0x25c)
219
220/* PCIe Link Error registers */
221#define PCIE_LNK_ERR_STAT (APP_BLK_REG_ADDR + 0x260)
222#define PCIE_LNK_ERR_MSK (APP_BLK_REG_ADDR + 0x264)
223
224/**
225 * FCoE/FIP Ethertype Register
226 * 31:16 -- Chip wide value for FIP type
227 * 15:0 -- Chip wide value for FCoE type
228 */
229#define FCOE_FIP_ETH_TYPE (APP_BLK_REG_ADDR + 0x280)
230
231/**
232 * Reserved Ethertype Register
233 * 31:16 -- Reserved
234 * 15:0 -- Other ethertype
235 */
236#define RESV_ETH_TYPE (APP_BLK_REG_ADDR + 0x284)
237
238/**
239 * Host Command Status Registers
240 * Each set consists of 3 registers :
241 * clear, set, cmd
242 * 16 such register sets in all
243 * See catapult_spec.pdf for detailed functionality
244 * Put each type in a single macro accessed by _num ?
245 */
246#define HOST_CMDSTS0_CLR_REG (APP_BLK_REG_ADDR + 0x500)
247#define HOST_CMDSTS0_SET_REG (APP_BLK_REG_ADDR + 0x504)
248#define HOST_CMDSTS0_REG (APP_BLK_REG_ADDR + 0x508)
249#define HOST_CMDSTS1_CLR_REG (APP_BLK_REG_ADDR + 0x510)
250#define HOST_CMDSTS1_SET_REG (APP_BLK_REG_ADDR + 0x514)
251#define HOST_CMDSTS1_REG (APP_BLK_REG_ADDR + 0x518)
252#define HOST_CMDSTS2_CLR_REG (APP_BLK_REG_ADDR + 0x520)
253#define HOST_CMDSTS2_SET_REG (APP_BLK_REG_ADDR + 0x524)
254#define HOST_CMDSTS2_REG (APP_BLK_REG_ADDR + 0x528)
255#define HOST_CMDSTS3_CLR_REG (APP_BLK_REG_ADDR + 0x530)
256#define HOST_CMDSTS3_SET_REG (APP_BLK_REG_ADDR + 0x534)
257#define HOST_CMDSTS3_REG (APP_BLK_REG_ADDR + 0x538)
258#define HOST_CMDSTS4_CLR_REG (APP_BLK_REG_ADDR + 0x540)
259#define HOST_CMDSTS4_SET_REG (APP_BLK_REG_ADDR + 0x544)
260#define HOST_CMDSTS4_REG (APP_BLK_REG_ADDR + 0x548)
261#define HOST_CMDSTS5_CLR_REG (APP_BLK_REG_ADDR + 0x550)
262#define HOST_CMDSTS5_SET_REG (APP_BLK_REG_ADDR + 0x554)
263#define HOST_CMDSTS5_REG (APP_BLK_REG_ADDR + 0x558)
264#define HOST_CMDSTS6_CLR_REG (APP_BLK_REG_ADDR + 0x560)
265#define HOST_CMDSTS6_SET_REG (APP_BLK_REG_ADDR + 0x564)
266#define HOST_CMDSTS6_REG (APP_BLK_REG_ADDR + 0x568)
267#define HOST_CMDSTS7_CLR_REG (APP_BLK_REG_ADDR + 0x570)
268#define HOST_CMDSTS7_SET_REG (APP_BLK_REG_ADDR + 0x574)
269#define HOST_CMDSTS7_REG (APP_BLK_REG_ADDR + 0x578)
270#define HOST_CMDSTS8_CLR_REG (APP_BLK_REG_ADDR + 0x580)
271#define HOST_CMDSTS8_SET_REG (APP_BLK_REG_ADDR + 0x584)
272#define HOST_CMDSTS8_REG (APP_BLK_REG_ADDR + 0x588)
273#define HOST_CMDSTS9_CLR_REG (APP_BLK_REG_ADDR + 0x590)
274#define HOST_CMDSTS9_SET_REG (APP_BLK_REG_ADDR + 0x594)
275#define HOST_CMDSTS9_REG (APP_BLK_REG_ADDR + 0x598)
276#define HOST_CMDSTS10_CLR_REG (APP_BLK_REG_ADDR + 0x5A0)
277#define HOST_CMDSTS10_SET_REG (APP_BLK_REG_ADDR + 0x5A4)
278#define HOST_CMDSTS10_REG (APP_BLK_REG_ADDR + 0x5A8)
279#define HOST_CMDSTS11_CLR_REG (APP_BLK_REG_ADDR + 0x5B0)
280#define HOST_CMDSTS11_SET_REG (APP_BLK_REG_ADDR + 0x5B4)
281#define HOST_CMDSTS11_REG (APP_BLK_REG_ADDR + 0x5B8)
282#define HOST_CMDSTS12_CLR_REG (APP_BLK_REG_ADDR + 0x5C0)
283#define HOST_CMDSTS12_SET_REG (APP_BLK_REG_ADDR + 0x5C4)
284#define HOST_CMDSTS12_REG (APP_BLK_REG_ADDR + 0x5C8)
285#define HOST_CMDSTS13_CLR_REG (APP_BLK_REG_ADDR + 0x5D0)
286#define HOST_CMDSTS13_SET_REG (APP_BLK_REG_ADDR + 0x5D4)
287#define HOST_CMDSTS13_REG (APP_BLK_REG_ADDR + 0x5D8)
288#define HOST_CMDSTS14_CLR_REG (APP_BLK_REG_ADDR + 0x5E0)
289#define HOST_CMDSTS14_SET_REG (APP_BLK_REG_ADDR + 0x5E4)
290#define HOST_CMDSTS14_REG (APP_BLK_REG_ADDR + 0x5E8)
291#define HOST_CMDSTS15_CLR_REG (APP_BLK_REG_ADDR + 0x5F0)
292#define HOST_CMDSTS15_SET_REG (APP_BLK_REG_ADDR + 0x5F4)
293#define HOST_CMDSTS15_REG (APP_BLK_REG_ADDR + 0x5F8)
294
295/**
296 * LPU0 Block Register Address Offset from BAR0
297 * Range 0x18000 - 0x18033
298 */
299#define LPU0_BLK_REG_ADDR 0x00018000
300
301/**
302 * LPU0 Registers
303 * Should they be directly used from host,
304 * except for diagnostics ?
305 * CTL_REG : Control register
306 * CMD_REG : Triggers exec. of cmd. in
307 * Mailbox memory
308 */
309#define LPU0_MBOX_CTL_REG (LPU0_BLK_REG_ADDR + 0x000)
310#define LPU0_MBOX_CMD_REG (LPU0_BLK_REG_ADDR + 0x004)
311#define LPU0_MBOX_LINK_0REG (LPU0_BLK_REG_ADDR + 0x008)
312#define LPU1_MBOX_LINK_0REG (LPU0_BLK_REG_ADDR + 0x00c)
313#define LPU0_MBOX_STATUS_0REG (LPU0_BLK_REG_ADDR + 0x010)
314#define LPU1_MBOX_STATUS_0REG (LPU0_BLK_REG_ADDR + 0x014)
315#define LPU0_ERR_STATUS_REG (LPU0_BLK_REG_ADDR + 0x018)
316#define LPU0_ERR_SET_REG (LPU0_BLK_REG_ADDR + 0x020)
317
318/**
319 * LPU1 Block Register Address Offset from BAR0
320 * Range 0x18400 - 0x18433
321 */
322#define LPU1_BLK_REG_ADDR 0x00018400
323
324/**
325 * LPU1 Registers
326 * Same as LPU0 registers above
327 */
328#define LPU1_MBOX_CTL_REG (LPU1_BLK_REG_ADDR + 0x000)
329#define LPU1_MBOX_CMD_REG (LPU1_BLK_REG_ADDR + 0x004)
330#define LPU0_MBOX_LINK_1REG (LPU1_BLK_REG_ADDR + 0x008)
331#define LPU1_MBOX_LINK_1REG (LPU1_BLK_REG_ADDR + 0x00c)
332#define LPU0_MBOX_STATUS_1REG (LPU1_BLK_REG_ADDR + 0x010)
333#define LPU1_MBOX_STATUS_1REG (LPU1_BLK_REG_ADDR + 0x014)
334#define LPU1_ERR_STATUS_REG (LPU1_BLK_REG_ADDR + 0x018)
335#define LPU1_ERR_SET_REG (LPU1_BLK_REG_ADDR + 0x020)
336
337/**
338 * PSS Block Register Address Offset from BAR0
339 * Range 0x18800 - 0x188DB
340 */
341#define PSS_BLK_REG_ADDR 0x00018800
342
343/**
344 * PSS Registers
345 * For details, see catapult_spec.pdf
346 * ERR_STATUS_REG : Indicates error in PSS module
347 * RAM_ERR_STATUS_REG : Indicates RAM module that detected error
348 */
349#define ERR_STATUS_SET (PSS_BLK_REG_ADDR + 0x018)
350#define PSS_RAM_ERR_STATUS_REG (PSS_BLK_REG_ADDR + 0x01C)
351
352/**
353 * PSS Semaphore Lock Registers, total 16
354 * First read when unlocked returns 0,
355 * and is set to 1, atomically.
356 * Subsequent reads returns 1.
357 * To clear set the value to 0.
358 * Range : 0x20 to 0x5c
359 */
360#define PSS_SEM_LOCK_REG(_num) \
361 (PSS_BLK_REG_ADDR + 0x020 + ((_num) << 2))
362
363/**
364 * PSS Semaphore Status Registers,
365 * corresponding to the lock registers above
366 */
367#define PSS_SEM_STATUS_REG(_num) \
368 (PSS_BLK_REG_ADDR + 0x060 + ((_num) << 2))
369
370/**
371 * Catapult CPQ Registers
372 * Defines for Mailbox Registers
373 * Used to send mailbox commands to firmware from
374 * host. The data part is written to the MBox
375 * memory, registers are used to indicate that
376 * a commnad is resident in memory.
377 *
378 * Note : LPU0<->LPU1 mailboxes are not listed here
379 */
380#define CPQ_BLK_REG_ADDR 0x00019000
381
382#define HOSTFN0_LPU0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x130)
383#define HOSTFN0_LPU1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x134)
384#define LPU0_HOSTFN0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x138)
385#define LPU1_HOSTFN0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x13C)
386
387#define HOSTFN1_LPU0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x140)
388#define HOSTFN1_LPU1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x144)
389#define LPU0_HOSTFN1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x148)
390#define LPU1_HOSTFN1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x14C)
391
392#define HOSTFN2_LPU0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x170)
393#define HOSTFN2_LPU1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x174)
394#define LPU0_HOSTFN2_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x178)
395#define LPU1_HOSTFN2_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x17C)
396
397#define HOSTFN3_LPU0_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x180)
398#define HOSTFN3_LPU1_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x184)
399#define LPU0_HOSTFN3_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x188)
400#define LPU1_HOSTFN3_MBOX1_CMD_STAT (CPQ_BLK_REG_ADDR + 0x18C)
401
402/* Host Function Force Parity Error Registers */
403#define HOSTFN0_LPU_FORCE_PERR (CPQ_BLK_REG_ADDR + 0x120)
404#define HOSTFN1_LPU_FORCE_PERR (CPQ_BLK_REG_ADDR + 0x124)
405#define HOSTFN2_LPU_FORCE_PERR (CPQ_BLK_REG_ADDR + 0x128)
406#define HOSTFN3_LPU_FORCE_PERR (CPQ_BLK_REG_ADDR + 0x12C)
407
408/* LL Port[0|1] Halt Mask Registers */
409#define LL_HALT_MSK_P0 (CPQ_BLK_REG_ADDR + 0x1A0)
410#define LL_HALT_MSK_P1 (CPQ_BLK_REG_ADDR + 0x1B0)
411
412/* LL Port[0|1] Error Mask Registers */
413#define LL_ERR_MSK_P0 (CPQ_BLK_REG_ADDR + 0x1D0)
414#define LL_ERR_MSK_P1 (CPQ_BLK_REG_ADDR + 0x1D4)
415
416/* EMC FLI (Flash Controller) Block Register Address Offset from BAR0 */
417#define FLI_BLK_REG_ADDR 0x0001D000
418
419/* EMC FLI Registers */
420#define FLI_CMD_REG (FLI_BLK_REG_ADDR + 0x000)
421#define FLI_ADDR_REG (FLI_BLK_REG_ADDR + 0x004)
422#define FLI_CTL_REG (FLI_BLK_REG_ADDR + 0x008)
423#define FLI_WRDATA_REG (FLI_BLK_REG_ADDR + 0x00C)
424#define FLI_RDDATA_REG (FLI_BLK_REG_ADDR + 0x010)
425#define FLI_DEV_STATUS_REG (FLI_BLK_REG_ADDR + 0x014)
426#define FLI_SIG_WD_REG (FLI_BLK_REG_ADDR + 0x018)
427
428/**
429 * RO register
430 * 31:16 -- Vendor Id
431 * 15:0 -- Device Id
432 */
433#define FLI_DEV_VENDOR_REG (FLI_BLK_REG_ADDR + 0x01C)
434#define FLI_ERR_STATUS_REG (FLI_BLK_REG_ADDR + 0x020)
435
436/**
437 * RAD (RxAdm) Block Register Address Offset from BAR0
438 * RAD0 Range : 0x20000 - 0x203FF
439 * RAD1 Range : 0x20400 - 0x207FF
440 */
441#define RAD0_BLK_REG_ADDR 0x00020000
442#define RAD1_BLK_REG_ADDR 0x00020400
443
444/* RAD0 Registers */
445#define RAD0_CTL_REG (RAD0_BLK_REG_ADDR + 0x000)
446#define RAD0_PE_PARM_REG (RAD0_BLK_REG_ADDR + 0x004)
447#define RAD0_BCN_REG (RAD0_BLK_REG_ADDR + 0x008)
448
449/* Default function ID register */
450#define RAD0_DEFAULT_REG (RAD0_BLK_REG_ADDR + 0x00C)
451
452/* Default promiscuous ID register */
453#define RAD0_PROMISC_REG (RAD0_BLK_REG_ADDR + 0x010)
454
455#define RAD0_BCNQ_REG (RAD0_BLK_REG_ADDR + 0x014)
456
457/*
458 * This register selects 1 of 8 PM Q's using
459 * VLAN pri, for non-BCN packets without a VLAN tag
460 */
461#define RAD0_DEFAULTQ_REG (RAD0_BLK_REG_ADDR + 0x018)
462
463#define RAD0_ERR_STS (RAD0_BLK_REG_ADDR + 0x01C)
464#define RAD0_SET_ERR_STS (RAD0_BLK_REG_ADDR + 0x020)
465#define RAD0_ERR_INT_EN (RAD0_BLK_REG_ADDR + 0x024)
466#define RAD0_FIRST_ERR (RAD0_BLK_REG_ADDR + 0x028)
467#define RAD0_FORCE_ERR (RAD0_BLK_REG_ADDR + 0x02C)
468
469#define RAD0_IF_RCVD (RAD0_BLK_REG_ADDR + 0x030)
470#define RAD0_IF_RCVD_OCTETS_HIGH (RAD0_BLK_REG_ADDR + 0x034)
471#define RAD0_IF_RCVD_OCTETS_LOW (RAD0_BLK_REG_ADDR + 0x038)
472#define RAD0_IF_RCVD_VLAN (RAD0_BLK_REG_ADDR + 0x03C)
473#define RAD0_IF_RCVD_UCAST (RAD0_BLK_REG_ADDR + 0x040)
474#define RAD0_IF_RCVD_UCAST_OCTETS_HIGH (RAD0_BLK_REG_ADDR + 0x044)
475#define RAD0_IF_RCVD_UCAST_OCTETS_LOW (RAD0_BLK_REG_ADDR + 0x048)
476#define RAD0_IF_RCVD_UCAST_VLAN (RAD0_BLK_REG_ADDR + 0x04C)
477#define RAD0_IF_RCVD_MCAST (RAD0_BLK_REG_ADDR + 0x050)
478#define RAD0_IF_RCVD_MCAST_OCTETS_HIGH (RAD0_BLK_REG_ADDR + 0x054)
479#define RAD0_IF_RCVD_MCAST_OCTETS_LOW (RAD0_BLK_REG_ADDR + 0x058)
480#define RAD0_IF_RCVD_MCAST_VLAN (RAD0_BLK_REG_ADDR + 0x05C)
481#define RAD0_IF_RCVD_BCAST (RAD0_BLK_REG_ADDR + 0x060)
482#define RAD0_IF_RCVD_BCAST_OCTETS_HIGH (RAD0_BLK_REG_ADDR + 0x064)
483#define RAD0_IF_RCVD_BCAST_OCTETS_LOW (RAD0_BLK_REG_ADDR + 0x068)
484#define RAD0_IF_RCVD_BCAST_VLAN (RAD0_BLK_REG_ADDR + 0x06C)
485#define RAD0_DROPPED_FRAMES (RAD0_BLK_REG_ADDR + 0x070)
486
487#define RAD0_MAC_MAN_1H (RAD0_BLK_REG_ADDR + 0x080)
488#define RAD0_MAC_MAN_1L (RAD0_BLK_REG_ADDR + 0x084)
489#define RAD0_MAC_MAN_2H (RAD0_BLK_REG_ADDR + 0x088)
490#define RAD0_MAC_MAN_2L (RAD0_BLK_REG_ADDR + 0x08C)
491#define RAD0_MAC_MAN_3H (RAD0_BLK_REG_ADDR + 0x090)
492#define RAD0_MAC_MAN_3L (RAD0_BLK_REG_ADDR + 0x094)
493#define RAD0_MAC_MAN_4H (RAD0_BLK_REG_ADDR + 0x098)
494#define RAD0_MAC_MAN_4L (RAD0_BLK_REG_ADDR + 0x09C)
495
496#define RAD0_LAST4_IP (RAD0_BLK_REG_ADDR + 0x100)
497
498/* RAD1 Registers */
499#define RAD1_CTL_REG (RAD1_BLK_REG_ADDR + 0x000)
500#define RAD1_PE_PARM_REG (RAD1_BLK_REG_ADDR + 0x004)
501#define RAD1_BCN_REG (RAD1_BLK_REG_ADDR + 0x008)
502
503/* Default function ID register */
504#define RAD1_DEFAULT_REG (RAD1_BLK_REG_ADDR + 0x00C)
505
506/* Promiscuous function ID register */
507#define RAD1_PROMISC_REG (RAD1_BLK_REG_ADDR + 0x010)
508
509#define RAD1_BCNQ_REG (RAD1_BLK_REG_ADDR + 0x014)
510
511/*
512 * This register selects 1 of 8 PM Q's using
513 * VLAN pri, for non-BCN packets without a VLAN tag
514 */
515#define RAD1_DEFAULTQ_REG (RAD1_BLK_REG_ADDR + 0x018)
516
517#define RAD1_ERR_STS (RAD1_BLK_REG_ADDR + 0x01C)
518#define RAD1_SET_ERR_STS (RAD1_BLK_REG_ADDR + 0x020)
519#define RAD1_ERR_INT_EN (RAD1_BLK_REG_ADDR + 0x024)
520
521/**
522 * TXA Block Register Address Offset from BAR0
523 * TXA0 Range : 0x21000 - 0x213FF
524 * TXA1 Range : 0x21400 - 0x217FF
525 */
526#define TXA0_BLK_REG_ADDR 0x00021000
527#define TXA1_BLK_REG_ADDR 0x00021400
528
529/* TXA Registers */
530#define TXA0_CTRL_REG (TXA0_BLK_REG_ADDR + 0x000)
531#define TXA1_CTRL_REG (TXA1_BLK_REG_ADDR + 0x000)
532
533/**
534 * TSO Sequence # Registers (RO)
535 * Total 8 (for 8 queues)
536 * Holds the last seq.# for TSO frames
537 * See catapult_spec.pdf for more details
538 */
539#define TXA0_TSO_TCP_SEQ_REG(_num) \
540 (TXA0_BLK_REG_ADDR + 0x020 + ((_num) << 2))
541
542#define TXA1_TSO_TCP_SEQ_REG(_num) \
543 (TXA1_BLK_REG_ADDR + 0x020 + ((_num) << 2))
544
545/**
546 * TSO IP ID # Registers (RO)
547 * Total 8 (for 8 queues)
548 * Holds the last IP ID for TSO frames
549 * See catapult_spec.pdf for more details
550 */
551#define TXA0_TSO_IP_INFO_REG(_num) \
552 (TXA0_BLK_REG_ADDR + 0x040 + ((_num) << 2))
553
554#define TXA1_TSO_IP_INFO_REG(_num) \
555 (TXA1_BLK_REG_ADDR + 0x040 + ((_num) << 2))
556
557/**
558 * RXA Block Register Address Offset from BAR0
559 * RXA0 Range : 0x21800 - 0x21BFF
560 * RXA1 Range : 0x21C00 - 0x21FFF
561 */
562#define RXA0_BLK_REG_ADDR 0x00021800
563#define RXA1_BLK_REG_ADDR 0x00021C00
564
565/* RXA Registers */
566#define RXA0_CTL_REG (RXA0_BLK_REG_ADDR + 0x040)
567#define RXA1_CTL_REG (RXA1_BLK_REG_ADDR + 0x040)
568
569/**
570 * PPLB Block Register Address Offset from BAR0
571 * PPLB0 Range : 0x22000 - 0x223FF
572 * PPLB1 Range : 0x22400 - 0x227FF
573 */
574#define PLB0_BLK_REG_ADDR 0x00022000
575#define PLB1_BLK_REG_ADDR 0x00022400
576
577/**
578 * PLB Registers
579 * Holds RL timer used time stamps in RLT tagged frames
580 */
581#define PLB0_ECM_TIMER_REG (PLB0_BLK_REG_ADDR + 0x05C)
582#define PLB1_ECM_TIMER_REG (PLB1_BLK_REG_ADDR + 0x05C)
583
584/* Controls the rate-limiter on each of the priority class */
585#define PLB0_RL_CTL (PLB0_BLK_REG_ADDR + 0x060)
586#define PLB1_RL_CTL (PLB1_BLK_REG_ADDR + 0x060)
587
588/**
589 * Max byte register, total 8, 0-7
590 * see catapult_spec.pdf for details
591 */
592#define PLB0_RL_MAX_BC(_num) \
593 (PLB0_BLK_REG_ADDR + 0x064 + ((_num) << 2))
594#define PLB1_RL_MAX_BC(_num) \
595 (PLB1_BLK_REG_ADDR + 0x064 + ((_num) << 2))
596
597/**
598 * RL Time Unit Register for priority 0-7
599 * 4 bits per priority
600 * (2^rl_unit)*1us is the actual time period
601 */
602#define PLB0_RL_TU_PRIO (PLB0_BLK_REG_ADDR + 0x084)
603#define PLB1_RL_TU_PRIO (PLB1_BLK_REG_ADDR + 0x084)
604
605/**
606 * RL byte count register,
607 * bytes transmitted in (rl_unit*1)us time period
608 * 1 per priority, 8 in all, 0-7.
609 */
610#define PLB0_RL_BYTE_CNT(_num) \
611 (PLB0_BLK_REG_ADDR + 0x088 + ((_num) << 2))
612#define PLB1_RL_BYTE_CNT(_num) \
613 (PLB1_BLK_REG_ADDR + 0x088 + ((_num) << 2))
614
615/**
616 * RL Min factor register
617 * 2 bits per priority,
618 * 4 factors possible: 1, 0.5, 0.25, 0
619 * 2'b00 - 0; 2'b01 - 0.25; 2'b10 - 0.5; 2'b11 - 1
620 */
621#define PLB0_RL_MIN_REG (PLB0_BLK_REG_ADDR + 0x0A8)
622#define PLB1_RL_MIN_REG (PLB1_BLK_REG_ADDR + 0x0A8)
623
624/**
625 * RL Max factor register
626 * 2 bits per priority,
627 * 4 factors possible: 1, 0.5, 0.25, 0
628 * 2'b00 - 0; 2'b01 - 0.25; 2'b10 - 0.5; 2'b11 - 1
629 */
630#define PLB0_RL_MAX_REG (PLB0_BLK_REG_ADDR + 0x0AC)
631#define PLB1_RL_MAX_REG (PLB1_BLK_REG_ADDR + 0x0AC)
632
633/* MAC SERDES Address Paging register */
634#define PLB0_EMS_ADD_REG (PLB0_BLK_REG_ADDR + 0xD0)
635#define PLB1_EMS_ADD_REG (PLB1_BLK_REG_ADDR + 0xD0)
636
637/* LL EMS Registers */
638#define LL_EMS0_BLK_REG_ADDR 0x00026800
639#define LL_EMS1_BLK_REG_ADDR 0x00026C00
640
641/**
642 * BPC Block Register Address Offset from BAR0
643 * BPC0 Range : 0x23000 - 0x233FF
644 * BPC1 Range : 0x23400 - 0x237FF
645 */
646#define BPC0_BLK_REG_ADDR 0x00023000
647#define BPC1_BLK_REG_ADDR 0x00023400
648
649/**
650 * PMM Block Register Address Offset from BAR0
651 * PMM0 Range : 0x23800 - 0x23BFF
652 * PMM1 Range : 0x23C00 - 0x23FFF
653 */
654#define PMM0_BLK_REG_ADDR 0x00023800
655#define PMM1_BLK_REG_ADDR 0x00023C00
656
657/**
658 * HQM Block Register Address Offset from BAR0
659 * HQM0 Range : 0x24000 - 0x243FF
660 * HQM1 Range : 0x24400 - 0x247FF
661 */
662#define HQM0_BLK_REG_ADDR 0x00024000
663#define HQM1_BLK_REG_ADDR 0x00024400
664
665/**
666 * HQM Control Register
667 * Controls some aspects of IB
668 * See catapult_spec.pdf for details
669 */
670#define HQM0_CTL_REG (HQM0_BLK_REG_ADDR + 0x000)
671#define HQM1_CTL_REG (HQM1_BLK_REG_ADDR + 0x000)
672
673/**
674 * HQM Stop Q Semaphore Registers.
675 * Only one Queue resource can be stopped at
676 * any given time. This register controls access
677 * to the single stop Q resource.
678 * See catapult_spec.pdf for details
679 */
680#define HQM0_RXQ_STOP_SEM (HQM0_BLK_REG_ADDR + 0x028)
681#define HQM0_TXQ_STOP_SEM (HQM0_BLK_REG_ADDR + 0x02C)
682#define HQM1_RXQ_STOP_SEM (HQM1_BLK_REG_ADDR + 0x028)
683#define HQM1_TXQ_STOP_SEM (HQM1_BLK_REG_ADDR + 0x02C)
684
685/**
686 * LUT Block Register Address Offset from BAR0
687 * LUT0 Range : 0x25800 - 0x25BFF
688 * LUT1 Range : 0x25C00 - 0x25FFF
689 */
690#define LUT0_BLK_REG_ADDR 0x00025800
691#define LUT1_BLK_REG_ADDR 0x00025C00
692
693/**
694 * LUT Registers
695 * See catapult_spec.pdf for details
696 */
697#define LUT0_ERR_STS (LUT0_BLK_REG_ADDR + 0x000)
698#define LUT1_ERR_STS (LUT1_BLK_REG_ADDR + 0x000)
699#define LUT0_SET_ERR_STS (LUT0_BLK_REG_ADDR + 0x004)
700#define LUT1_SET_ERR_STS (LUT1_BLK_REG_ADDR + 0x004)
701
702/**
703 * TRC (Debug/Trace) Register Offset from BAR0
704 * Range : 0x26000 -- 0x263FFF
705 */
706#define TRC_BLK_REG_ADDR 0x00026000
707
708/**
709 * TRC Registers
710 * See catapult_spec.pdf for details of each
711 */
712#define TRC_CTL_REG (TRC_BLK_REG_ADDR + 0x000)
713#define TRC_MODS_REG (TRC_BLK_REG_ADDR + 0x004)
714#define TRC_TRGC_REG (TRC_BLK_REG_ADDR + 0x008)
715#define TRC_CNT1_REG (TRC_BLK_REG_ADDR + 0x010)
716#define TRC_CNT2_REG (TRC_BLK_REG_ADDR + 0x014)
717#define TRC_NXTS_REG (TRC_BLK_REG_ADDR + 0x018)
718#define TRC_DIRR_REG (TRC_BLK_REG_ADDR + 0x01C)
719
720/**
721 * TRC Trigger match filters, total 10
722 * Determines the trigger condition
723 */
724#define TRC_TRGM_REG(_num) \
725 (TRC_BLK_REG_ADDR + 0x040 + ((_num) << 2))
726
727/**
728 * TRC Next State filters, total 10
729 * Determines the next state conditions
730 */
731#define TRC_NXTM_REG(_num) \
732 (TRC_BLK_REG_ADDR + 0x080 + ((_num) << 2))
733
734/**
735 * TRC Store Match filters, total 10
736 * Determines the store conditions
737 */
738#define TRC_STRM_REG(_num) \
739 (TRC_BLK_REG_ADDR + 0x0C0 + ((_num) << 2))
740
741/* DOORBELLS ACCESS */
742
743/**
744 * Catapult doorbells
745 * Each doorbell-queue set has
746 * 1 RxQ, 1 TxQ, 2 IBs in that order
747 * Size of each entry in 32 bytes, even though only 1 word
748 * is used. For Non-VM case each doorbell-q set is
749 * separated by 128 bytes, for VM case it is separated
750 * by 4K bytes
751 * Non VM case Range : 0x38000 - 0x39FFF
752 * VM case Range : 0x100000 - 0x11FFFF
753 * The range applies to both HQMs
754 */
755#define HQM_DOORBELL_BLK_BASE_ADDR 0x00038000
756#define HQM_DOORBELL_VM_BLK_BASE_ADDR 0x00100000
757
758/* MEMORY ACCESS */
759
760/**
761 * Catapult H/W Block Memory Access Address
762 * To the host a memory space of 32K (page) is visible
763 * at a time. The address range is from 0x08000 to 0x0FFFF
764 */
765#define HW_BLK_HOST_MEM_ADDR 0x08000
766
767/**
768 * Catapult LUT Memory Access Page Numbers
769 * Range : LUT0 0xa0-0xa1
770 * LUT1 0xa2-0xa3
771 */
772#define LUT0_MEM_BLK_BASE_PG_NUM 0x000000A0
773#define LUT1_MEM_BLK_BASE_PG_NUM 0x000000A2
774
775/**
776 * Catapult RxFn Database Memory Block Base Offset
777 *
778 * The Rx function database exists in LUT block.
779 * In PCIe space this is accessible as a 256x32
780 * bit block. Each entry in this database is 4
781 * (4 byte) words. Max. entries is 64.
782 * Address of an entry corresponding to a function
783 * = base_addr + (function_no. * 16)
784 */
785#define RX_FNDB_RAM_BASE_OFFSET 0x0000B400
786
787/**
788 * Catapult TxFn Database Memory Block Base Offset Address
789 *
790 * The Tx function database exists in LUT block.
791 * In PCIe space this is accessible as a 64x32
792 * bit block. Each entry in this database is 1
793 * (4 byte) word. Max. entries is 64.
794 * Address of an entry corresponding to a function
795 * = base_addr + (function_no. * 4)
796 */
797#define TX_FNDB_RAM_BASE_OFFSET 0x0000B800
798
799/**
800 * Catapult Unicast CAM Base Offset Address
801 *
802 * Exists in LUT memory space.
803 * Shared by both the LL & FCoE driver.
804 * Size is 256x48 bits; mapped to PCIe space
805 * 512x32 bit blocks. For each address, bits
806 * are written in the order : [47:32] and then
807 * [31:0].
808 */
809#define UCAST_CAM_BASE_OFFSET 0x0000A800
810
811/**
812 * Catapult Unicast RAM Base Offset Address
813 *
814 * Exists in LUT memory space.
815 * Shared by both the LL & FCoE driver.
816 * Size is 256x9 bits.
817 */
818#define UCAST_RAM_BASE_OFFSET 0x0000B000
819
820/**
821 * Catapult Mulicast CAM Base Offset Address
822 *
823 * Exists in LUT memory space.
824 * Shared by both the LL & FCoE driver.
825 * Size is 256x48 bits; mapped to PCIe space
826 * 512x32 bit blocks. For each address, bits
827 * are written in the order : [47:32] and then
828 * [31:0].
829 */
830#define MCAST_CAM_BASE_OFFSET 0x0000A000
831
832/**
833 * Catapult VLAN RAM Base Offset Address
834 *
835 * Exists in LUT memory space.
836 * Size is 4096x66 bits; mapped to PCIe space as
837 * 8192x32 bit blocks.
838 * All the 4K entries are within the address range
839 * 0x0000 to 0x8000, so in the first LUT page.
840 */
841#define VLAN_RAM_BASE_OFFSET 0x00000000
842
843/**
844 * Catapult Tx Stats RAM Base Offset Address
845 *
846 * Exists in LUT memory space.
847 * Size is 1024x33 bits;
848 * Each Tx function has 64 bytes of space
849 */
850#define TX_STATS_RAM_BASE_OFFSET 0x00009000
851
852/**
853 * Catapult Rx Stats RAM Base Offset Address
854 *
855 * Exists in LUT memory space.
856 * Size is 1024x33 bits;
857 * Each Rx function has 64 bytes of space
858 */
859#define RX_STATS_RAM_BASE_OFFSET 0x00008000
860
861/* Catapult RXA Memory Access Page Numbers */
862#define RXA0_MEM_BLK_BASE_PG_NUM 0x0000008C
863#define RXA1_MEM_BLK_BASE_PG_NUM 0x0000008D
864
865/**
866 * Catapult Multicast Vector Table Base Offset Address
867 *
868 * Exists in RxA memory space.
869 * Organized as 512x65 bit block.
870 * However for each entry 16 bytes allocated (power of 2)
871 * Total size 512*16 bytes.
872 * There are two logical divisions, 256 entries each :
873 * a) Entries 0x00 to 0xff (256) -- Approx. MVT
874 * Offset 0x000 to 0xFFF
875 * b) Entries 0x100 to 0x1ff (256) -- Exact MVT
876 * Offsets 0x1000 to 0x1FFF
877 */
878#define MCAST_APPROX_MVT_BASE_OFFSET 0x00000000
879#define MCAST_EXACT_MVT_BASE_OFFSET 0x00001000
880
881/**
882 * Catapult RxQ Translate Table (RIT) Base Offset Address
883 *
884 * Exists in RxA memory space
885 * Total no. of entries 64
886 * Each entry is 1 (4 byte) word.
887 * 31:12 -- Reserved
888 * 11:0 -- Two 6 bit RxQ Ids
889 */
890#define FUNCTION_TO_RXQ_TRANSLATE 0x00002000
891
892/* Catapult RxAdm (RAD) Memory Access Page Numbers */
893#define RAD0_MEM_BLK_BASE_PG_NUM 0x00000086
894#define RAD1_MEM_BLK_BASE_PG_NUM 0x00000087
895
896/**
897 * Catapult RSS Table Base Offset Address
898 *
899 * Exists in RAD memory space.
900 * Each entry is 352 bits, but alligned on
901 * 64 byte (512 bit) boundary. Accessed
902 * 4 byte words, the whole entry can be
903 * broken into 11 word accesses.
904 */
905#define RSS_TABLE_BASE_OFFSET 0x00000800
906
907/**
908 * Catapult CPQ Block Page Number
909 * This value is written to the page number registers
910 * to access the memory associated with the mailboxes.
911 */
912#define CPQ_BLK_PG_NUM 0x00000005
913
914/**
915 * Clarification :
916 * LL functions are 2 & 3; can HostFn0/HostFn1
917 * <-> LPU0/LPU1 memories be used ?
918 */
919/**
920 * Catapult HostFn0/HostFn1 to LPU0/LPU1 Mbox memory
921 * Per catapult_spec.pdf, the offset of the mbox
922 * memory is in the register space at an offset of 0x200
923 */
924#define CPQ_BLK_REG_MBOX_ADDR (CPQ_BLK_REG_ADDR + 0x200)
925
926#define HOSTFN_LPU_MBOX (CPQ_BLK_REG_MBOX_ADDR + 0x000)
927
928/* Catapult LPU0/LPU1 to HostFn0/HostFn1 Mbox memory */
929#define LPU_HOSTFN_MBOX (CPQ_BLK_REG_MBOX_ADDR + 0x080)
930
931/**
932 * Catapult HQM Block Page Number
933 * This is written to the page number register for
934 * the appropriate function to access the memory
935 * associated with HQM
936 */
937#define HQM0_BLK_PG_NUM 0x00000096
938#define HQM1_BLK_PG_NUM 0x00000097
939
940/**
941 * Note that TxQ and RxQ entries are interlaced
942 * the HQM memory, i.e RXQ0, TXQ0, RXQ1, TXQ1.. etc.
943 */
944
945#define HQM_RXTX_Q_RAM_BASE_OFFSET 0x00004000
946
947/**
948 * CQ Memory
949 * Exists in HQM Memory space
950 * Each entry is 16 (4 byte) words of which
951 * only 12 words are used for configuration
952 * Total 64 entries per HQM memory space
953 */
954#define HQM_CQ_RAM_BASE_OFFSET 0x00006000
955
956/**
957 * Interrupt Block (IB) Memory
958 * Exists in HQM Memory space
959 * Each entry is 8 (4 byte) words of which
960 * only 5 words are used for configuration
961 * Total 128 entries per HQM memory space
962 */
963#define HQM_IB_RAM_BASE_OFFSET 0x00001000
964
965/**
966 * Index Table (IT) Memory
967 * Exists in HQM Memory space
968 * Each entry is 1 (4 byte) word which
969 * is used for configuration
970 * Total 128 entries per HQM memory space
971 */
972#define HQM_INDX_TBL_RAM_BASE_OFFSET 0x00002000
973
974/**
975 * PSS Block Memory Page Number
976 * This is written to the appropriate page number
977 * register to access the CPU memory.
978 * Also known as the PSS secondary memory (SMEM).
979 * Range : 0x180 to 0x1CF
980 * See catapult_spec.pdf for details
981 */
982#define PSS_BLK_PG_NUM 0x00000180
983
984/**
985 * Offsets of different instances of PSS SMEM
986 * 2.5M of continuous 1T memory space : 2 blocks
987 * of 1M each (32 pages each, page=32KB) and 4 smaller
988 * blocks of 128K each (4 pages each, page=32KB)
989 * PSS_LMEM_INST0 is used for firmware download
990 */
991#define PSS_LMEM_INST0 0x00000000
992#define PSS_LMEM_INST1 0x00100000
993#define PSS_LMEM_INST2 0x00200000
994#define PSS_LMEM_INST3 0x00220000
995#define PSS_LMEM_INST4 0x00240000
996#define PSS_LMEM_INST5 0x00260000
997
998#define BNA_PCI_REG_CT_ADDRSZ (0x40000)
999
1000#define BNA_GET_PAGE_NUM(_base_page, _offset) \
1001 ((_base_page) + ((_offset) >> 15))
1002
1003#define BNA_GET_PAGE_OFFSET(_offset) \
1004 ((_offset) & 0x7fff)
1005
1006#define BNA_GET_MEM_BASE_ADDR(_bar0, _base_offset) \
1007 ((_bar0) + HW_BLK_HOST_MEM_ADDR \
1008 + BNA_GET_PAGE_OFFSET((_base_offset)))
1009
1010#define BNA_GET_VLAN_MEM_ENTRY_ADDR(_bar0, _fn_id, _vlan_id)\
1011 (_bar0 + (HW_BLK_HOST_MEM_ADDR) \
1012 + (BNA_GET_PAGE_OFFSET(VLAN_RAM_BASE_OFFSET)) \
1013 + (((_fn_id) & 0x3f) << 9) \
1014 + (((_vlan_id) & 0xfe0) >> 3))
1015
1016/**
1017 *
1018 * Interrupt related bits, flags and macros
1019 *
1020 */
1021
1022#define __LPU02HOST_MBOX0_STATUS_BITS 0x00100000
1023#define __LPU12HOST_MBOX0_STATUS_BITS 0x00200000
1024#define __LPU02HOST_MBOX1_STATUS_BITS 0x00400000
1025#define __LPU12HOST_MBOX1_STATUS_BITS 0x00800000
1026
1027#define __LPU02HOST_MBOX0_MASK_BITS 0x00100000
1028#define __LPU12HOST_MBOX0_MASK_BITS 0x00200000
1029#define __LPU02HOST_MBOX1_MASK_BITS 0x00400000
1030#define __LPU12HOST_MBOX1_MASK_BITS 0x00800000
1031
1032#define __LPU2HOST_MBOX_MASK_BITS \
1033 (__LPU02HOST_MBOX0_MASK_BITS | __LPU02HOST_MBOX1_MASK_BITS | \
1034 __LPU12HOST_MBOX0_MASK_BITS | __LPU12HOST_MBOX1_MASK_BITS)
1035
1036#define __LPU2HOST_IB_STATUS_BITS 0x0000ffff
1037
1038#define BNA_IS_LPU0_MBOX_INTR(_intr_status) \
1039 ((_intr_status) & (__LPU02HOST_MBOX0_STATUS_BITS | \
1040 __LPU02HOST_MBOX1_STATUS_BITS))
1041
1042#define BNA_IS_LPU1_MBOX_INTR(_intr_status) \
1043 ((_intr_status) & (__LPU12HOST_MBOX0_STATUS_BITS | \
1044 __LPU12HOST_MBOX1_STATUS_BITS))
1045
1046#define BNA_IS_MBOX_INTR(_intr_status) \
1047 ((_intr_status) & \
1048 (__LPU02HOST_MBOX0_STATUS_BITS | \
1049 __LPU02HOST_MBOX1_STATUS_BITS | \
1050 __LPU12HOST_MBOX0_STATUS_BITS | \
1051 __LPU12HOST_MBOX1_STATUS_BITS))
1052
1053#define __EMC_ERROR_STATUS_BITS 0x00010000
1054#define __LPU0_ERROR_STATUS_BITS 0x00020000
1055#define __LPU1_ERROR_STATUS_BITS 0x00040000
1056#define __PSS_ERROR_STATUS_BITS 0x00080000
1057
1058#define __HALT_STATUS_BITS 0x01000000
1059
1060#define __EMC_ERROR_MASK_BITS 0x00010000
1061#define __LPU0_ERROR_MASK_BITS 0x00020000
1062#define __LPU1_ERROR_MASK_BITS 0x00040000
1063#define __PSS_ERROR_MASK_BITS 0x00080000
1064
1065#define __HALT_MASK_BITS 0x01000000
1066
1067#define __ERROR_MASK_BITS \
1068 (__EMC_ERROR_MASK_BITS | __LPU0_ERROR_MASK_BITS | \
1069 __LPU1_ERROR_MASK_BITS | __PSS_ERROR_MASK_BITS | \
1070 __HALT_MASK_BITS)
1071
1072#define BNA_IS_ERR_INTR(_intr_status) \
1073 ((_intr_status) & \
1074 (__EMC_ERROR_STATUS_BITS | \
1075 __LPU0_ERROR_STATUS_BITS | \
1076 __LPU1_ERROR_STATUS_BITS | \
1077 __PSS_ERROR_STATUS_BITS | \
1078 __HALT_STATUS_BITS))
1079
1080#define BNA_IS_MBOX_ERR_INTR(_intr_status) \
1081 (BNA_IS_MBOX_INTR((_intr_status)) | \
1082 BNA_IS_ERR_INTR((_intr_status)))
1083
1084#define BNA_IS_INTX_DATA_INTR(_intr_status) \
1085 ((_intr_status) & __LPU2HOST_IB_STATUS_BITS)
1086
1087#define BNA_INTR_STATUS_MBOX_CLR(_intr_status) \
1088do { \
1089 (_intr_status) &= ~(__LPU02HOST_MBOX0_STATUS_BITS | \
1090 __LPU02HOST_MBOX1_STATUS_BITS | \
1091 __LPU12HOST_MBOX0_STATUS_BITS | \
1092 __LPU12HOST_MBOX1_STATUS_BITS); \
1093} while (0)
1094
1095#define BNA_INTR_STATUS_ERR_CLR(_intr_status) \
1096do { \
1097 (_intr_status) &= ~(__EMC_ERROR_STATUS_BITS | \
1098 __LPU0_ERROR_STATUS_BITS | \
1099 __LPU1_ERROR_STATUS_BITS | \
1100 __PSS_ERROR_STATUS_BITS | \
1101 __HALT_STATUS_BITS); \
1102} while (0)
1103
1104#define bna_intx_disable(_bna, _cur_mask) \
1105{ \
1106 (_cur_mask) = readl((_bna)->regs.fn_int_mask);\
1107 writel(0xffffffff, (_bna)->regs.fn_int_mask);\
1108}
1109
1110#define bna_intx_enable(bna, new_mask) \
1111 writel((new_mask), (bna)->regs.fn_int_mask)
1112
1113#define bna_mbox_intr_disable(bna) \
1114 writel((readl((bna)->regs.fn_int_mask) | \
1115 (__LPU2HOST_MBOX_MASK_BITS | __ERROR_MASK_BITS)), \
1116 (bna)->regs.fn_int_mask)
1117
1118#define bna_mbox_intr_enable(bna) \
1119 writel((readl((bna)->regs.fn_int_mask) & \
1120 ~(__LPU2HOST_MBOX_MASK_BITS | __ERROR_MASK_BITS)), \
1121 (bna)->regs.fn_int_mask)
1122
1123#define bna_intr_status_get(_bna, _status) \
1124{ \
1125 (_status) = readl((_bna)->regs.fn_int_status); \
1126 if ((_status)) { \
1127 writel((_status) & ~(__LPU02HOST_MBOX0_STATUS_BITS |\
1128 __LPU02HOST_MBOX1_STATUS_BITS |\
1129 __LPU12HOST_MBOX0_STATUS_BITS |\
1130 __LPU12HOST_MBOX1_STATUS_BITS), \
1131 (_bna)->regs.fn_int_status);\
1132 } \
1133}
1134
1135#define bna_intr_status_get_no_clr(_bna, _status) \
1136 (_status) = readl((_bna)->regs.fn_int_status)
1137
1138#define bna_intr_mask_get(bna, mask) \
1139 (*mask) = readl((bna)->regs.fn_int_mask)
1140
1141#define bna_intr_ack(bna, intr_bmap) \
1142 writel((intr_bmap), (bna)->regs.fn_int_status)
1143
1144#define bna_ib_intx_disable(bna, ib_id) \
1145 writel(readl((bna)->regs.fn_int_mask) | \
1146 (1 << (ib_id)), \
1147 (bna)->regs.fn_int_mask)
1148
1149#define bna_ib_intx_enable(bna, ib_id) \
1150 writel(readl((bna)->regs.fn_int_mask) & \
1151 ~(1 << (ib_id)), \
1152 (bna)->regs.fn_int_mask)
1153
1154#define bna_mbox_msix_idx_set(_device) \
1155do {\
1156 writel(((_device)->vector & 0x000001FF), \
1157 (_device)->bna->pcidev.pci_bar_kva + \
1158 reg_offset[(_device)->bna->pcidev.pci_func].msix_idx);\
1159} while (0)
1160
1161/**
1162 *
1163 * TxQ, RxQ, CQ related bits, offsets, macros
1164 *
1165 */
1166
1167#define BNA_Q_IDLE_STATE 0x00008001
1168
1169#define BNA_GET_DOORBELL_BASE_ADDR(_bar0) \
1170 ((_bar0) + HQM_DOORBELL_BLK_BASE_ADDR)
1171
1172#define BNA_GET_DOORBELL_ENTRY_OFFSET(_entry) \
1173 ((HQM_DOORBELL_BLK_BASE_ADDR) \
1174 + (_entry << 7))
1175
1176#define BNA_DOORBELL_IB_INT_ACK(_timeout, _events) \
1177 (0x80000000 | ((_timeout) << 16) | (_events))
1178
1179#define BNA_DOORBELL_IB_INT_DISABLE (0x40000000)
1180
1181/* TxQ Entry Opcodes */
1182#define BNA_TXQ_WI_SEND (0x402) /* Single Frame Transmission */
1183#define BNA_TXQ_WI_SEND_LSO (0x403) /* Multi-Frame Transmission */
1184#define BNA_TXQ_WI_EXTENSION (0x104) /* Extension WI */
1185
1186/* TxQ Entry Control Flags */
1187#define BNA_TXQ_WI_CF_FCOE_CRC (1 << 8)
1188#define BNA_TXQ_WI_CF_IPID_MODE (1 << 5)
1189#define BNA_TXQ_WI_CF_INS_PRIO (1 << 4)
1190#define BNA_TXQ_WI_CF_INS_VLAN (1 << 3)
1191#define BNA_TXQ_WI_CF_UDP_CKSUM (1 << 2)
1192#define BNA_TXQ_WI_CF_TCP_CKSUM (1 << 1)
1193#define BNA_TXQ_WI_CF_IP_CKSUM (1 << 0)
1194
1195#define BNA_TXQ_WI_L4_HDR_N_OFFSET(_hdr_size, _offset) \
1196 (((_hdr_size) << 10) | ((_offset) & 0x3FF))
1197
1198/*
1199 * Completion Q defines
1200 */
1201/* CQ Entry Flags */
1202#define BNA_CQ_EF_MAC_ERROR (1 << 0)
1203#define BNA_CQ_EF_FCS_ERROR (1 << 1)
1204#define BNA_CQ_EF_TOO_LONG (1 << 2)
1205#define BNA_CQ_EF_FC_CRC_OK (1 << 3)
1206
1207#define BNA_CQ_EF_RSVD1 (1 << 4)
1208#define BNA_CQ_EF_L4_CKSUM_OK (1 << 5)
1209#define BNA_CQ_EF_L3_CKSUM_OK (1 << 6)
1210#define BNA_CQ_EF_HDS_HEADER (1 << 7)
1211
1212#define BNA_CQ_EF_UDP (1 << 8)
1213#define BNA_CQ_EF_TCP (1 << 9)
1214#define BNA_CQ_EF_IP_OPTIONS (1 << 10)
1215#define BNA_CQ_EF_IPV6 (1 << 11)
1216
1217#define BNA_CQ_EF_IPV4 (1 << 12)
1218#define BNA_CQ_EF_VLAN (1 << 13)
1219#define BNA_CQ_EF_RSS (1 << 14)
1220#define BNA_CQ_EF_RSVD2 (1 << 15)
1221
1222#define BNA_CQ_EF_MCAST_MATCH (1 << 16)
1223#define BNA_CQ_EF_MCAST (1 << 17)
1224#define BNA_CQ_EF_BCAST (1 << 18)
1225#define BNA_CQ_EF_REMOTE (1 << 19)
1226
1227#define BNA_CQ_EF_LOCAL (1 << 20)
1228
1229/**
1230 *
1231 * Data structures
1232 *
1233 */
1234
1235enum txf_flags {
1236 BFI_TXF_CF_ENABLE = 1 << 0,
1237 BFI_TXF_CF_VLAN_FILTER = 1 << 8,
1238 BFI_TXF_CF_VLAN_ADMIT = 1 << 9,
1239 BFI_TXF_CF_VLAN_INSERT = 1 << 10,
1240 BFI_TXF_CF_RSVD1 = 1 << 11,
1241 BFI_TXF_CF_MAC_SA_CHECK = 1 << 12,
1242 BFI_TXF_CF_VLAN_WI_BASED = 1 << 13,
1243 BFI_TXF_CF_VSWITCH_MCAST = 1 << 14,
1244 BFI_TXF_CF_VSWITCH_UCAST = 1 << 15,
1245 BFI_TXF_CF_RSVD2 = 0x7F << 1
1246};
1247
1248enum ib_flags {
1249 BFI_IB_CF_MASTER_ENABLE = (1 << 0),
1250 BFI_IB_CF_MSIX_MODE = (1 << 1),
1251 BFI_IB_CF_COALESCING_MODE = (1 << 2),
1252 BFI_IB_CF_INTER_PKT_ENABLE = (1 << 3),
1253 BFI_IB_CF_INT_ENABLE = (1 << 4),
1254 BFI_IB_CF_INTER_PKT_DMA = (1 << 5),
1255 BFI_IB_CF_ACK_PENDING = (1 << 6),
1256 BFI_IB_CF_RESERVED1 = (1 << 7)
1257};
1258
1259enum rss_hash_type {
1260 BFI_RSS_T_V4_TCP = (1 << 11),
1261 BFI_RSS_T_V4_IP = (1 << 10),
1262 BFI_RSS_T_V6_TCP = (1 << 9),
1263 BFI_RSS_T_V6_IP = (1 << 8)
1264};
1265enum hds_header_type {
1266 BNA_HDS_T_V4_TCP = (1 << 11),
1267 BNA_HDS_T_V4_UDP = (1 << 10),
1268 BNA_HDS_T_V6_TCP = (1 << 9),
1269 BNA_HDS_T_V6_UDP = (1 << 8),
1270 BNA_HDS_FORCED = (1 << 7),
1271};
1272enum rxf_flags {
1273 BNA_RXF_CF_SM_LG_RXQ = (1 << 15),
1274 BNA_RXF_CF_DEFAULT_VLAN = (1 << 14),
1275 BNA_RXF_CF_DEFAULT_FUNCTION_ENABLE = (1 << 13),
1276 BNA_RXF_CF_VLAN_STRIP = (1 << 12),
1277 BNA_RXF_CF_RSS_ENABLE = (1 << 8)
1278};
1279struct bna_chip_regs_offset {
1280 u32 page_addr;
1281 u32 fn_int_status;
1282 u32 fn_int_mask;
1283 u32 msix_idx;
1284};
1285extern const struct bna_chip_regs_offset reg_offset[];
1286
1287struct bna_chip_regs {
1288 void __iomem *page_addr;
1289 void __iomem *fn_int_status;
1290 void __iomem *fn_int_mask;
1291};
1292
1293struct bna_txq_mem {
1294 u32 pg_tbl_addr_lo;
1295 u32 pg_tbl_addr_hi;
1296 u32 cur_q_entry_lo;
1297 u32 cur_q_entry_hi;
1298 u32 reserved1;
1299 u32 reserved2;
1300 u32 pg_cnt_n_prd_ptr; /* 31:16->total page count */
1301 /* 15:0 ->producer pointer (index?) */
1302 u32 entry_n_pg_size; /* 31:16->entry size */
1303 /* 15:0 ->page size */
1304 u32 int_blk_n_cns_ptr; /* 31:24->Int Blk Id; */
1305 /* 23:16->Int Blk Offset */
1306 /* 15:0 ->consumer pointer(index?) */
1307 u32 cns_ptr2_n_q_state; /* 31:16->cons. ptr 2; 15:0-> Q state */
1308 u32 nxt_qid_n_fid_n_pri; /* 17:10->next */
1309 /* QId;9:3->FID;2:0->Priority */
1310 u32 wvc_n_cquota_n_rquota; /* 31:24->WI Vector Count; */
1311 /* 23:12->Cfg Quota; */
1312 /* 11:0 ->Run Quota */
1313 u32 reserved3[4];
1314};
1315
1316struct bna_rxq_mem {
1317 u32 pg_tbl_addr_lo;
1318 u32 pg_tbl_addr_hi;
1319 u32 cur_q_entry_lo;
1320 u32 cur_q_entry_hi;
1321 u32 reserved1;
1322 u32 reserved2;
1323 u32 pg_cnt_n_prd_ptr; /* 31:16->total page count */
1324 /* 15:0 ->producer pointer (index?) */
1325 u32 entry_n_pg_size; /* 31:16->entry size */
1326 /* 15:0 ->page size */
1327 u32 sg_n_cq_n_cns_ptr; /* 31:28->reserved; 27:24->sg count */
1328 /* 23:16->CQ; */
1329 /* 15:0->consumer pointer(index?) */
1330 u32 buf_sz_n_q_state; /* 31:16->buffer size; 15:0-> Q state */
1331 u32 next_qid; /* 17:10->next QId */
1332 u32 reserved3;
1333 u32 reserved4[4];
1334};
1335
1336struct bna_rxtx_q_mem {
1337 struct bna_rxq_mem rxq;
1338 struct bna_txq_mem txq;
1339};
1340
1341struct bna_cq_mem {
1342 u32 pg_tbl_addr_lo;
1343 u32 pg_tbl_addr_hi;
1344 u32 cur_q_entry_lo;
1345 u32 cur_q_entry_hi;
1346
1347 u32 reserved1;
1348 u32 reserved2;
1349 u32 pg_cnt_n_prd_ptr; /* 31:16->total page count */
1350 /* 15:0 ->producer pointer (index?) */
1351 u32 entry_n_pg_size; /* 31:16->entry size */
1352 /* 15:0 ->page size */
1353 u32 int_blk_n_cns_ptr; /* 31:24->Int Blk Id; */
1354 /* 23:16->Int Blk Offset */
1355 /* 15:0 ->consumer pointer(index?) */
1356 u32 q_state; /* 31:16->reserved; 15:0-> Q state */
1357 u32 reserved3[2];
1358 u32 reserved4[4];
1359};
1360
1361struct bna_ib_blk_mem {
1362 u32 host_addr_lo;
1363 u32 host_addr_hi;
1364 u32 clsc_n_ctrl_n_msix; /* 31:24->coalescing; */
1365 /* 23:16->coalescing cfg; */
1366 /* 15:8 ->control; */
1367 /* 7:0 ->msix; */
1368 u32 ipkt_n_ent_n_idxof;
1369 u32 ipkt_cnt_cfg_n_unacked;
1370
1371 u32 reserved[3];
1372};
1373
1374struct bna_idx_tbl_mem {
1375 u32 idx; /* !< 31:16->res;15:0->idx; */
1376};
1377
1378struct bna_doorbell_qset {
1379 u32 rxq[0x20 >> 2];
1380 u32 txq[0x20 >> 2];
1381 u32 ib0[0x20 >> 2];
1382 u32 ib1[0x20 >> 2];
1383};
1384
1385struct bna_rx_fndb_ram {
1386 u32 rss_prop;
1387 u32 size_routing_props;
1388 u32 rit_hds_mcastq;
1389 u32 control_flags;
1390};
1391
1392struct bna_tx_fndb_ram {
1393 u32 vlan_n_ctrl_flags;
1394};
1395
1396/**
1397 * @brief
1398 * Structure which maps to RxFn Indirection Table (RIT)
1399 * Size : 1 word
1400 * See catapult_spec.pdf, RxA for details
1401 */
1402struct bna_rit_mem {
1403 u32 rxq_ids; /* !< 31:12->res;11:0->two 6 bit RxQ Ids */
1404};
1405
1406/**
1407 * @brief
1408 * Structure which maps to RSS Table entry
1409 * Size : 16 words
1410 * See catapult_spec.pdf, RAD for details
1411 */
1412struct bna_rss_mem {
1413 /*
1414 * 31:12-> res
1415 * 11:8 -> protocol type
1416 * 7:0 -> hash index
1417 */
1418 u32 type_n_hash;
1419 u32 hash_key[10]; /* !< 40 byte Toeplitz hash key */
1420 u32 reserved[5];
1421};
1422
1423/* TxQ Vector (a.k.a. Tx-Buffer Descriptor) */
1424struct bna_dma_addr {
1425 u32 msb;
1426 u32 lsb;
1427};
1428
1429struct bna_txq_wi_vector {
1430 u16 reserved;
1431 u16 length; /* Only 14 LSB are valid */
1432 struct bna_dma_addr host_addr; /* Tx-Buf DMA addr */
1433};
1434
1435typedef u16 bna_txq_wi_opcode_t;
1436
1437typedef u16 bna_txq_wi_ctrl_flag_t;
1438
1439/**
1440 * TxQ Entry Structure
1441 *
1442 * BEWARE: Load values into this structure with correct endianess.
1443 */
1444struct bna_txq_entry {
1445 union {
1446 struct {
1447 u8 reserved;
1448 u8 num_vectors; /* number of vectors present */
1449 bna_txq_wi_opcode_t opcode; /* Either */
1450 /* BNA_TXQ_WI_SEND or */
1451 /* BNA_TXQ_WI_SEND_LSO */
1452 bna_txq_wi_ctrl_flag_t flags; /* OR of all the flags */
1453 u16 l4_hdr_size_n_offset;
1454 u16 vlan_tag;
1455 u16 lso_mss; /* Only 14 LSB are valid */
1456 u32 frame_length; /* Only 24 LSB are valid */
1457 } wi;
1458
1459 struct {
1460 u16 reserved;
1461 bna_txq_wi_opcode_t opcode; /* Must be */
1462 /* BNA_TXQ_WI_EXTENSION */
1463 u32 reserved2[3]; /* Place holder for */
1464 /* removed vector (12 bytes) */
1465 } wi_ext;
1466 } hdr;
1467 struct bna_txq_wi_vector vector[4];
1468};
1469#define wi_hdr hdr.wi
1470#define wi_ext_hdr hdr.wi_ext
1471
1472/* RxQ Entry Structure */
1473struct bna_rxq_entry { /* Rx-Buffer */
1474 struct bna_dma_addr host_addr; /* Rx-Buffer DMA address */
1475};
1476
1477typedef u32 bna_cq_e_flag_t;
1478
1479/* CQ Entry Structure */
1480struct bna_cq_entry {
1481 bna_cq_e_flag_t flags;
1482 u16 vlan_tag;
1483 u16 length;
1484 u32 rss_hash;
1485 u8 valid;
1486 u8 reserved1;
1487 u8 reserved2;
1488 u8 rxq_id;
1489};
1490
1491#endif /* __BNA_HW_H__ */
diff --git a/drivers/net/bna/bna_txrx.c b/drivers/net/bna/bna_txrx.c
new file mode 100644
index 000000000000..890846d55502
--- /dev/null
+++ b/drivers/net/bna/bna_txrx.c
@@ -0,0 +1,4209 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18#include "bna.h"
19#include "bfa_sm.h"
20#include "bfi.h"
21
22/**
23 * IB
24 */
25#define bna_ib_find_free_ibidx(_mask, _pos)\
26do {\
27 (_pos) = 0;\
28 while (((_pos) < (BFI_IBIDX_MAX_SEGSIZE)) &&\
29 ((1 << (_pos)) & (_mask)))\
30 (_pos)++;\
31} while (0)
32
33#define bna_ib_count_ibidx(_mask, _count)\
34do {\
35 int pos = 0;\
36 (_count) = 0;\
37 while (pos < (BFI_IBIDX_MAX_SEGSIZE)) {\
38 if ((1 << pos) & (_mask))\
39 (_count) = pos + 1;\
40 pos++;\
41 } \
42} while (0)
43
44#define bna_ib_select_segpool(_count, _q_idx)\
45do {\
46 int i;\
47 (_q_idx) = -1;\
48 for (i = 0; i < BFI_IBIDX_TOTAL_POOLS; i++) {\
49 if ((_count <= ibidx_pool[i].pool_entry_size)) {\
50 (_q_idx) = i;\
51 break;\
52 } \
53 } \
54} while (0)
55
56struct bna_ibidx_pool {
57 int pool_size;
58 int pool_entry_size;
59};
60init_ibidx_pool(ibidx_pool);
61
62static struct bna_intr *
63bna_intr_get(struct bna_ib_mod *ib_mod, enum bna_intr_type intr_type,
64 int vector)
65{
66 struct bna_intr *intr;
67 struct list_head *qe;
68
69 list_for_each(qe, &ib_mod->intr_active_q) {
70 intr = (struct bna_intr *)qe;
71
72 if ((intr->intr_type == intr_type) &&
73 (intr->vector == vector)) {
74 intr->ref_count++;
75 return intr;
76 }
77 }
78
79 if (list_empty(&ib_mod->intr_free_q))
80 return NULL;
81
82 bfa_q_deq(&ib_mod->intr_free_q, &intr);
83 bfa_q_qe_init(&intr->qe);
84
85 intr->ref_count = 1;
86 intr->intr_type = intr_type;
87 intr->vector = vector;
88
89 list_add_tail(&intr->qe, &ib_mod->intr_active_q);
90
91 return intr;
92}
93
94static void
95bna_intr_put(struct bna_ib_mod *ib_mod,
96 struct bna_intr *intr)
97{
98 intr->ref_count--;
99
100 if (intr->ref_count == 0) {
101 intr->ib = NULL;
102 list_del(&intr->qe);
103 bfa_q_qe_init(&intr->qe);
104 list_add_tail(&intr->qe, &ib_mod->intr_free_q);
105 }
106}
107
108void
109bna_ib_mod_init(struct bna_ib_mod *ib_mod, struct bna *bna,
110 struct bna_res_info *res_info)
111{
112 int i;
113 int j;
114 int count;
115 u8 offset;
116 struct bna_doorbell_qset *qset;
117 unsigned long off;
118
119 ib_mod->bna = bna;
120
121 ib_mod->ib = (struct bna_ib *)
122 res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.mdl[0].kva;
123 ib_mod->intr = (struct bna_intr *)
124 res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.mdl[0].kva;
125 ib_mod->idx_seg = (struct bna_ibidx_seg *)
126 res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.mdl[0].kva;
127
128 INIT_LIST_HEAD(&ib_mod->ib_free_q);
129 INIT_LIST_HEAD(&ib_mod->intr_free_q);
130 INIT_LIST_HEAD(&ib_mod->intr_active_q);
131
132 for (i = 0; i < BFI_IBIDX_TOTAL_POOLS; i++)
133 INIT_LIST_HEAD(&ib_mod->ibidx_seg_pool[i]);
134
135 for (i = 0; i < BFI_MAX_IB; i++) {
136 ib_mod->ib[i].ib_id = i;
137
138 ib_mod->ib[i].ib_seg_host_addr_kva =
139 res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].kva;
140 ib_mod->ib[i].ib_seg_host_addr.lsb =
141 res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.lsb;
142 ib_mod->ib[i].ib_seg_host_addr.msb =
143 res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.msb;
144
145 qset = (struct bna_doorbell_qset *)0;
146 off = (unsigned long)(&qset[i >> 1].ib0[(i & 0x1)
147 * (0x20 >> 2)]);
148 ib_mod->ib[i].door_bell.doorbell_addr = off +
149 BNA_GET_DOORBELL_BASE_ADDR(bna->pcidev.pci_bar_kva);
150
151 bfa_q_qe_init(&ib_mod->ib[i].qe);
152 list_add_tail(&ib_mod->ib[i].qe, &ib_mod->ib_free_q);
153
154 bfa_q_qe_init(&ib_mod->intr[i].qe);
155 list_add_tail(&ib_mod->intr[i].qe, &ib_mod->intr_free_q);
156 }
157
158 count = 0;
159 offset = 0;
160 for (i = 0; i < BFI_IBIDX_TOTAL_POOLS; i++) {
161 for (j = 0; j < ibidx_pool[i].pool_size; j++) {
162 bfa_q_qe_init(&ib_mod->idx_seg[count]);
163 ib_mod->idx_seg[count].ib_seg_size =
164 ibidx_pool[i].pool_entry_size;
165 ib_mod->idx_seg[count].ib_idx_tbl_offset = offset;
166 list_add_tail(&ib_mod->idx_seg[count].qe,
167 &ib_mod->ibidx_seg_pool[i]);
168 count++;
169 offset += ibidx_pool[i].pool_entry_size;
170 }
171 }
172}
173
174void
175bna_ib_mod_uninit(struct bna_ib_mod *ib_mod)
176{
177 int i;
178 int j;
179 struct list_head *qe;
180
181 i = 0;
182 list_for_each(qe, &ib_mod->ib_free_q)
183 i++;
184
185 i = 0;
186 list_for_each(qe, &ib_mod->intr_free_q)
187 i++;
188
189 for (i = 0; i < BFI_IBIDX_TOTAL_POOLS; i++) {
190 j = 0;
191 list_for_each(qe, &ib_mod->ibidx_seg_pool[i])
192 j++;
193 }
194
195 ib_mod->bna = NULL;
196}
197
198struct bna_ib *
199bna_ib_get(struct bna_ib_mod *ib_mod,
200 enum bna_intr_type intr_type,
201 int vector)
202{
203 struct bna_ib *ib;
204 struct bna_intr *intr;
205
206 if (intr_type == BNA_INTR_T_INTX)
207 vector = (1 << vector);
208
209 intr = bna_intr_get(ib_mod, intr_type, vector);
210 if (intr == NULL)
211 return NULL;
212
213 if (intr->ib) {
214 if (intr->ib->ref_count == BFI_IBIDX_MAX_SEGSIZE) {
215 bna_intr_put(ib_mod, intr);
216 return NULL;
217 }
218 intr->ib->ref_count++;
219 return intr->ib;
220 }
221
222 if (list_empty(&ib_mod->ib_free_q)) {
223 bna_intr_put(ib_mod, intr);
224 return NULL;
225 }
226
227 bfa_q_deq(&ib_mod->ib_free_q, &ib);
228 bfa_q_qe_init(&ib->qe);
229
230 ib->ref_count = 1;
231 ib->start_count = 0;
232 ib->idx_mask = 0;
233
234 ib->intr = intr;
235 ib->idx_seg = NULL;
236 intr->ib = ib;
237
238 ib->bna = ib_mod->bna;
239
240 return ib;
241}
242
243void
244bna_ib_put(struct bna_ib_mod *ib_mod, struct bna_ib *ib)
245{
246 bna_intr_put(ib_mod, ib->intr);
247
248 ib->ref_count--;
249
250 if (ib->ref_count == 0) {
251 ib->intr = NULL;
252 ib->bna = NULL;
253 list_add_tail(&ib->qe, &ib_mod->ib_free_q);
254 }
255}
256
257/* Returns index offset - starting from 0 */
258int
259bna_ib_reserve_idx(struct bna_ib *ib)
260{
261 struct bna_ib_mod *ib_mod = &ib->bna->ib_mod;
262 struct bna_ibidx_seg *idx_seg;
263 int idx;
264 int num_idx;
265 int q_idx;
266
267 /* Find the first free index position */
268 bna_ib_find_free_ibidx(ib->idx_mask, idx);
269 if (idx == BFI_IBIDX_MAX_SEGSIZE)
270 return -1;
271
272 /*
273 * Calculate the total number of indexes held by this IB,
274 * including the index newly reserved above.
275 */
276 bna_ib_count_ibidx((ib->idx_mask | (1 << idx)), num_idx);
277
278 /* See if there is a free space in the index segment held by this IB */
279 if (ib->idx_seg && (num_idx <= ib->idx_seg->ib_seg_size)) {
280 ib->idx_mask |= (1 << idx);
281 return idx;
282 }
283
284 if (ib->start_count)
285 return -1;
286
287 /* Allocate a new segment */
288 bna_ib_select_segpool(num_idx, q_idx);
289 while (1) {
290 if (q_idx == BFI_IBIDX_TOTAL_POOLS)
291 return -1;
292 if (!list_empty(&ib_mod->ibidx_seg_pool[q_idx]))
293 break;
294 q_idx++;
295 }
296 bfa_q_deq(&ib_mod->ibidx_seg_pool[q_idx], &idx_seg);
297 bfa_q_qe_init(&idx_seg->qe);
298
299 /* Free the old segment */
300 if (ib->idx_seg) {
301 bna_ib_select_segpool(ib->idx_seg->ib_seg_size, q_idx);
302 list_add_tail(&ib->idx_seg->qe, &ib_mod->ibidx_seg_pool[q_idx]);
303 }
304
305 ib->idx_seg = idx_seg;
306
307 ib->idx_mask |= (1 << idx);
308
309 return idx;
310}
311
312void
313bna_ib_release_idx(struct bna_ib *ib, int idx)
314{
315 struct bna_ib_mod *ib_mod = &ib->bna->ib_mod;
316 struct bna_ibidx_seg *idx_seg;
317 int num_idx;
318 int cur_q_idx;
319 int new_q_idx;
320
321 ib->idx_mask &= ~(1 << idx);
322
323 if (ib->start_count)
324 return;
325
326 bna_ib_count_ibidx(ib->idx_mask, num_idx);
327
328 /*
329 * Free the segment, if there are no more indexes in the segment
330 * held by this IB
331 */
332 if (!num_idx) {
333 bna_ib_select_segpool(ib->idx_seg->ib_seg_size, cur_q_idx);
334 list_add_tail(&ib->idx_seg->qe,
335 &ib_mod->ibidx_seg_pool[cur_q_idx]);
336 ib->idx_seg = NULL;
337 return;
338 }
339
340 /* See if we can move to a smaller segment */
341 bna_ib_select_segpool(num_idx, new_q_idx);
342 bna_ib_select_segpool(ib->idx_seg->ib_seg_size, cur_q_idx);
343 while (new_q_idx < cur_q_idx) {
344 if (!list_empty(&ib_mod->ibidx_seg_pool[new_q_idx]))
345 break;
346 new_q_idx++;
347 }
348 if (new_q_idx < cur_q_idx) {
349 /* Select the new smaller segment */
350 bfa_q_deq(&ib_mod->ibidx_seg_pool[new_q_idx], &idx_seg);
351 bfa_q_qe_init(&idx_seg->qe);
352 /* Free the old segment */
353 list_add_tail(&ib->idx_seg->qe,
354 &ib_mod->ibidx_seg_pool[cur_q_idx]);
355 ib->idx_seg = idx_seg;
356 }
357}
358
359int
360bna_ib_config(struct bna_ib *ib, struct bna_ib_config *ib_config)
361{
362 if (ib->start_count)
363 return -1;
364
365 ib->ib_config.coalescing_timeo = ib_config->coalescing_timeo;
366 ib->ib_config.interpkt_timeo = ib_config->interpkt_timeo;
367 ib->ib_config.interpkt_count = ib_config->interpkt_count;
368 ib->ib_config.ctrl_flags = ib_config->ctrl_flags;
369
370 ib->ib_config.ctrl_flags |= BFI_IB_CF_MASTER_ENABLE;
371 if (ib->intr->intr_type == BNA_INTR_T_MSIX)
372 ib->ib_config.ctrl_flags |= BFI_IB_CF_MSIX_MODE;
373
374 return 0;
375}
376
377void
378bna_ib_start(struct bna_ib *ib)
379{
380 struct bna_ib_blk_mem ib_cfg;
381 struct bna_ib_blk_mem *ib_mem;
382 u32 pg_num;
383 u32 intx_mask;
384 int i;
385 void __iomem *base_addr;
386 unsigned long off;
387
388 ib->start_count++;
389
390 if (ib->start_count > 1)
391 return;
392
393 ib_cfg.host_addr_lo = (u32)(ib->ib_seg_host_addr.lsb);
394 ib_cfg.host_addr_hi = (u32)(ib->ib_seg_host_addr.msb);
395
396 ib_cfg.clsc_n_ctrl_n_msix = (((u32)
397 ib->ib_config.coalescing_timeo << 16) |
398 ((u32)ib->ib_config.ctrl_flags << 8) |
399 (ib->intr->vector));
400 ib_cfg.ipkt_n_ent_n_idxof =
401 ((u32)
402 (ib->ib_config.interpkt_timeo & 0xf) << 16) |
403 ((u32)ib->idx_seg->ib_seg_size << 8) |
404 (ib->idx_seg->ib_idx_tbl_offset);
405 ib_cfg.ipkt_cnt_cfg_n_unacked = ((u32)
406 ib->ib_config.interpkt_count << 24);
407
408 pg_num = BNA_GET_PAGE_NUM(HQM0_BLK_PG_NUM + ib->bna->port_num,
409 HQM_IB_RAM_BASE_OFFSET);
410 writel(pg_num, ib->bna->regs.page_addr);
411
412 base_addr = BNA_GET_MEM_BASE_ADDR(ib->bna->pcidev.pci_bar_kva,
413 HQM_IB_RAM_BASE_OFFSET);
414
415 ib_mem = (struct bna_ib_blk_mem *)0;
416 off = (unsigned long)&ib_mem[ib->ib_id].host_addr_lo;
417 writel(htonl(ib_cfg.host_addr_lo), base_addr + off);
418
419 off = (unsigned long)&ib_mem[ib->ib_id].host_addr_hi;
420 writel(htonl(ib_cfg.host_addr_hi), base_addr + off);
421
422 off = (unsigned long)&ib_mem[ib->ib_id].clsc_n_ctrl_n_msix;
423 writel(ib_cfg.clsc_n_ctrl_n_msix, base_addr + off);
424
425 off = (unsigned long)&ib_mem[ib->ib_id].ipkt_n_ent_n_idxof;
426 writel(ib_cfg.ipkt_n_ent_n_idxof, base_addr + off);
427
428 off = (unsigned long)&ib_mem[ib->ib_id].ipkt_cnt_cfg_n_unacked;
429 writel(ib_cfg.ipkt_cnt_cfg_n_unacked, base_addr + off);
430
431 ib->door_bell.doorbell_ack = BNA_DOORBELL_IB_INT_ACK(
432 (u32)ib->ib_config.coalescing_timeo, 0);
433
434 pg_num = BNA_GET_PAGE_NUM(HQM0_BLK_PG_NUM + ib->bna->port_num,
435 HQM_INDX_TBL_RAM_BASE_OFFSET);
436 writel(pg_num, ib->bna->regs.page_addr);
437
438 base_addr = BNA_GET_MEM_BASE_ADDR(ib->bna->pcidev.pci_bar_kva,
439 HQM_INDX_TBL_RAM_BASE_OFFSET);
440 for (i = 0; i < ib->idx_seg->ib_seg_size; i++) {
441 off = (unsigned long)
442 ((ib->idx_seg->ib_idx_tbl_offset + i) * BFI_IBIDX_SIZE);
443 writel(0, base_addr + off);
444 }
445
446 if (ib->intr->intr_type == BNA_INTR_T_INTX) {
447 bna_intx_disable(ib->bna, intx_mask);
448 intx_mask &= ~(ib->intr->vector);
449 bna_intx_enable(ib->bna, intx_mask);
450 }
451}
452
453void
454bna_ib_stop(struct bna_ib *ib)
455{
456 u32 intx_mask;
457
458 ib->start_count--;
459
460 if (ib->start_count == 0) {
461 writel(BNA_DOORBELL_IB_INT_DISABLE,
462 ib->door_bell.doorbell_addr);
463 if (ib->intr->intr_type == BNA_INTR_T_INTX) {
464 bna_intx_disable(ib->bna, intx_mask);
465 intx_mask |= (ib->intr->vector);
466 bna_intx_enable(ib->bna, intx_mask);
467 }
468 }
469}
470
471void
472bna_ib_fail(struct bna_ib *ib)
473{
474 ib->start_count = 0;
475}
476
477/**
478 * RXF
479 */
480static void rxf_enable(struct bna_rxf *rxf);
481static void rxf_disable(struct bna_rxf *rxf);
482static void __rxf_config_set(struct bna_rxf *rxf);
483static void __rxf_rit_set(struct bna_rxf *rxf);
484static void __bna_rxf_stat_clr(struct bna_rxf *rxf);
485static int rxf_process_packet_filter(struct bna_rxf *rxf);
486static int rxf_clear_packet_filter(struct bna_rxf *rxf);
487static void rxf_reset_packet_filter(struct bna_rxf *rxf);
488static void rxf_cb_enabled(void *arg, int status);
489static void rxf_cb_disabled(void *arg, int status);
490static void bna_rxf_cb_stats_cleared(void *arg, int status);
491static void __rxf_enable(struct bna_rxf *rxf);
492static void __rxf_disable(struct bna_rxf *rxf);
493
494bfa_fsm_state_decl(bna_rxf, stopped, struct bna_rxf,
495 enum bna_rxf_event);
496bfa_fsm_state_decl(bna_rxf, start_wait, struct bna_rxf,
497 enum bna_rxf_event);
498bfa_fsm_state_decl(bna_rxf, cam_fltr_mod_wait, struct bna_rxf,
499 enum bna_rxf_event);
500bfa_fsm_state_decl(bna_rxf, started, struct bna_rxf,
501 enum bna_rxf_event);
502bfa_fsm_state_decl(bna_rxf, cam_fltr_clr_wait, struct bna_rxf,
503 enum bna_rxf_event);
504bfa_fsm_state_decl(bna_rxf, stop_wait, struct bna_rxf,
505 enum bna_rxf_event);
506bfa_fsm_state_decl(bna_rxf, pause_wait, struct bna_rxf,
507 enum bna_rxf_event);
508bfa_fsm_state_decl(bna_rxf, resume_wait, struct bna_rxf,
509 enum bna_rxf_event);
510bfa_fsm_state_decl(bna_rxf, stat_clr_wait, struct bna_rxf,
511 enum bna_rxf_event);
512
513static struct bfa_sm_table rxf_sm_table[] = {
514 {BFA_SM(bna_rxf_sm_stopped), BNA_RXF_STOPPED},
515 {BFA_SM(bna_rxf_sm_start_wait), BNA_RXF_START_WAIT},
516 {BFA_SM(bna_rxf_sm_cam_fltr_mod_wait), BNA_RXF_CAM_FLTR_MOD_WAIT},
517 {BFA_SM(bna_rxf_sm_started), BNA_RXF_STARTED},
518 {BFA_SM(bna_rxf_sm_cam_fltr_clr_wait), BNA_RXF_CAM_FLTR_CLR_WAIT},
519 {BFA_SM(bna_rxf_sm_stop_wait), BNA_RXF_STOP_WAIT},
520 {BFA_SM(bna_rxf_sm_pause_wait), BNA_RXF_PAUSE_WAIT},
521 {BFA_SM(bna_rxf_sm_resume_wait), BNA_RXF_RESUME_WAIT},
522 {BFA_SM(bna_rxf_sm_stat_clr_wait), BNA_RXF_STAT_CLR_WAIT}
523};
524
525static void
526bna_rxf_sm_stopped_entry(struct bna_rxf *rxf)
527{
528 call_rxf_stop_cbfn(rxf, BNA_CB_SUCCESS);
529}
530
531static void
532bna_rxf_sm_stopped(struct bna_rxf *rxf, enum bna_rxf_event event)
533{
534 switch (event) {
535 case RXF_E_START:
536 bfa_fsm_set_state(rxf, bna_rxf_sm_start_wait);
537 break;
538
539 case RXF_E_STOP:
540 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
541 break;
542
543 case RXF_E_FAIL:
544 /* No-op */
545 break;
546
547 case RXF_E_CAM_FLTR_MOD:
548 call_rxf_cam_fltr_cbfn(rxf, BNA_CB_SUCCESS);
549 break;
550
551 case RXF_E_STARTED:
552 case RXF_E_STOPPED:
553 case RXF_E_CAM_FLTR_RESP:
554 /**
555 * These events are received due to flushing of mbox
556 * when device fails
557 */
558 /* No-op */
559 break;
560
561 case RXF_E_PAUSE:
562 rxf->rxf_oper_state = BNA_RXF_OPER_STATE_PAUSED;
563 call_rxf_pause_cbfn(rxf, BNA_CB_SUCCESS);
564 break;
565
566 case RXF_E_RESUME:
567 rxf->rxf_oper_state = BNA_RXF_OPER_STATE_RUNNING;
568 call_rxf_resume_cbfn(rxf, BNA_CB_SUCCESS);
569 break;
570
571 default:
572 bfa_sm_fault(rxf->rx->bna, event);
573 }
574}
575
576static void
577bna_rxf_sm_start_wait_entry(struct bna_rxf *rxf)
578{
579 __rxf_config_set(rxf);
580 __rxf_rit_set(rxf);
581 rxf_enable(rxf);
582}
583
584static void
585bna_rxf_sm_start_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
586{
587 switch (event) {
588 case RXF_E_STOP:
589 /**
590 * STOP is originated from bnad. When this happens,
591 * it can not be waiting for filter update
592 */
593 call_rxf_start_cbfn(rxf, BNA_CB_INTERRUPT);
594 bfa_fsm_set_state(rxf, bna_rxf_sm_stop_wait);
595 break;
596
597 case RXF_E_FAIL:
598 call_rxf_cam_fltr_cbfn(rxf, BNA_CB_SUCCESS);
599 call_rxf_start_cbfn(rxf, BNA_CB_FAIL);
600 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
601 break;
602
603 case RXF_E_CAM_FLTR_MOD:
604 /* No-op */
605 break;
606
607 case RXF_E_STARTED:
608 /**
609 * Force rxf_process_filter() to go through initial
610 * config
611 */
612 if ((rxf->ucast_active_mac != NULL) &&
613 (rxf->ucast_pending_set == 0))
614 rxf->ucast_pending_set = 1;
615
616 if (rxf->rss_status == BNA_STATUS_T_ENABLED)
617 rxf->rxf_flags |= BNA_RXF_FL_RSS_CONFIG_PENDING;
618
619 rxf->rxf_flags |= BNA_RXF_FL_VLAN_CONFIG_PENDING;
620
621 bfa_fsm_set_state(rxf, bna_rxf_sm_cam_fltr_mod_wait);
622 break;
623
624 case RXF_E_PAUSE:
625 case RXF_E_RESUME:
626 rxf->rxf_flags |= BNA_RXF_FL_OPERSTATE_CHANGED;
627 break;
628
629 default:
630 bfa_sm_fault(rxf->rx->bna, event);
631 }
632}
633
634static void
635bna_rxf_sm_cam_fltr_mod_wait_entry(struct bna_rxf *rxf)
636{
637 if (!rxf_process_packet_filter(rxf)) {
638 /* No more pending CAM entries to update */
639 bfa_fsm_set_state(rxf, bna_rxf_sm_started);
640 }
641}
642
643static void
644bna_rxf_sm_cam_fltr_mod_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
645{
646 switch (event) {
647 case RXF_E_STOP:
648 /**
649 * STOP is originated from bnad. When this happens,
650 * it can not be waiting for filter update
651 */
652 call_rxf_start_cbfn(rxf, BNA_CB_INTERRUPT);
653 bfa_fsm_set_state(rxf, bna_rxf_sm_cam_fltr_clr_wait);
654 break;
655
656 case RXF_E_FAIL:
657 rxf_reset_packet_filter(rxf);
658 call_rxf_cam_fltr_cbfn(rxf, BNA_CB_SUCCESS);
659 call_rxf_start_cbfn(rxf, BNA_CB_FAIL);
660 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
661 break;
662
663 case RXF_E_CAM_FLTR_MOD:
664 /* No-op */
665 break;
666
667 case RXF_E_CAM_FLTR_RESP:
668 if (!rxf_process_packet_filter(rxf)) {
669 /* No more pending CAM entries to update */
670 call_rxf_cam_fltr_cbfn(rxf, BNA_CB_SUCCESS);
671 bfa_fsm_set_state(rxf, bna_rxf_sm_started);
672 }
673 break;
674
675 case RXF_E_PAUSE:
676 case RXF_E_RESUME:
677 rxf->rxf_flags |= BNA_RXF_FL_OPERSTATE_CHANGED;
678 break;
679
680 default:
681 bfa_sm_fault(rxf->rx->bna, event);
682 }
683}
684
685static void
686bna_rxf_sm_started_entry(struct bna_rxf *rxf)
687{
688 call_rxf_start_cbfn(rxf, BNA_CB_SUCCESS);
689
690 if (rxf->rxf_flags & BNA_RXF_FL_OPERSTATE_CHANGED) {
691 if (rxf->rxf_oper_state == BNA_RXF_OPER_STATE_PAUSED)
692 bfa_fsm_send_event(rxf, RXF_E_PAUSE);
693 else
694 bfa_fsm_send_event(rxf, RXF_E_RESUME);
695 }
696
697}
698
699static void
700bna_rxf_sm_started(struct bna_rxf *rxf, enum bna_rxf_event event)
701{
702 switch (event) {
703 case RXF_E_STOP:
704 bfa_fsm_set_state(rxf, bna_rxf_sm_cam_fltr_clr_wait);
705 /* Hack to get FSM start clearing CAM entries */
706 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_RESP);
707 break;
708
709 case RXF_E_FAIL:
710 rxf_reset_packet_filter(rxf);
711 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
712 break;
713
714 case RXF_E_CAM_FLTR_MOD:
715 bfa_fsm_set_state(rxf, bna_rxf_sm_cam_fltr_mod_wait);
716 break;
717
718 case RXF_E_PAUSE:
719 bfa_fsm_set_state(rxf, bna_rxf_sm_pause_wait);
720 break;
721
722 case RXF_E_RESUME:
723 bfa_fsm_set_state(rxf, bna_rxf_sm_resume_wait);
724 break;
725
726 default:
727 bfa_sm_fault(rxf->rx->bna, event);
728 }
729}
730
731static void
732bna_rxf_sm_cam_fltr_clr_wait_entry(struct bna_rxf *rxf)
733{
734 /**
735 * Note: Do not add rxf_clear_packet_filter here.
736 * It will overstep mbox when this transition happens:
737 * cam_fltr_mod_wait -> cam_fltr_clr_wait on RXF_E_STOP event
738 */
739}
740
741static void
742bna_rxf_sm_cam_fltr_clr_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
743{
744 switch (event) {
745 case RXF_E_FAIL:
746 /**
747 * FSM was in the process of stopping, initiated by
748 * bnad. When this happens, no one can be waiting for
749 * start or filter update
750 */
751 rxf_reset_packet_filter(rxf);
752 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
753 break;
754
755 case RXF_E_CAM_FLTR_RESP:
756 if (!rxf_clear_packet_filter(rxf)) {
757 /* No more pending CAM entries to clear */
758 bfa_fsm_set_state(rxf, bna_rxf_sm_stop_wait);
759 rxf_disable(rxf);
760 }
761 break;
762
763 default:
764 bfa_sm_fault(rxf->rx->bna, event);
765 }
766}
767
768static void
769bna_rxf_sm_stop_wait_entry(struct bna_rxf *rxf)
770{
771 /**
772 * NOTE: Do not add rxf_disable here.
773 * It will overstep mbox when this transition happens:
774 * start_wait -> stop_wait on RXF_E_STOP event
775 */
776}
777
778static void
779bna_rxf_sm_stop_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
780{
781 switch (event) {
782 case RXF_E_FAIL:
783 /**
784 * FSM was in the process of stopping, initiated by
785 * bnad. When this happens, no one can be waiting for
786 * start or filter update
787 */
788 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
789 break;
790
791 case RXF_E_STARTED:
792 /**
793 * This event is received due to abrupt transition from
794 * bna_rxf_sm_start_wait state on receiving
795 * RXF_E_STOP event
796 */
797 rxf_disable(rxf);
798 break;
799
800 case RXF_E_STOPPED:
801 /**
802 * FSM was in the process of stopping, initiated by
803 * bnad. When this happens, no one can be waiting for
804 * start or filter update
805 */
806 bfa_fsm_set_state(rxf, bna_rxf_sm_stat_clr_wait);
807 break;
808
809 case RXF_E_PAUSE:
810 rxf->rxf_oper_state = BNA_RXF_OPER_STATE_PAUSED;
811 break;
812
813 case RXF_E_RESUME:
814 rxf->rxf_oper_state = BNA_RXF_OPER_STATE_RUNNING;
815 break;
816
817 default:
818 bfa_sm_fault(rxf->rx->bna, event);
819 }
820}
821
822static void
823bna_rxf_sm_pause_wait_entry(struct bna_rxf *rxf)
824{
825 rxf->rxf_flags &=
826 ~(BNA_RXF_FL_OPERSTATE_CHANGED | BNA_RXF_FL_RXF_ENABLED);
827 __rxf_disable(rxf);
828}
829
830static void
831bna_rxf_sm_pause_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
832{
833 switch (event) {
834 case RXF_E_FAIL:
835 /**
836 * FSM was in the process of disabling rxf, initiated by
837 * bnad.
838 */
839 call_rxf_pause_cbfn(rxf, BNA_CB_FAIL);
840 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
841 break;
842
843 case RXF_E_STOPPED:
844 rxf->rxf_oper_state = BNA_RXF_OPER_STATE_PAUSED;
845 call_rxf_pause_cbfn(rxf, BNA_CB_SUCCESS);
846 bfa_fsm_set_state(rxf, bna_rxf_sm_started);
847 break;
848
849 /*
850 * Since PAUSE/RESUME can only be sent by bnad, we don't expect
851 * any other event during these states
852 */
853 default:
854 bfa_sm_fault(rxf->rx->bna, event);
855 }
856}
857
858static void
859bna_rxf_sm_resume_wait_entry(struct bna_rxf *rxf)
860{
861 rxf->rxf_flags &= ~(BNA_RXF_FL_OPERSTATE_CHANGED);
862 rxf->rxf_flags |= BNA_RXF_FL_RXF_ENABLED;
863 __rxf_enable(rxf);
864}
865
866static void
867bna_rxf_sm_resume_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
868{
869 switch (event) {
870 case RXF_E_FAIL:
871 /**
872 * FSM was in the process of disabling rxf, initiated by
873 * bnad.
874 */
875 call_rxf_resume_cbfn(rxf, BNA_CB_FAIL);
876 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
877 break;
878
879 case RXF_E_STARTED:
880 rxf->rxf_oper_state = BNA_RXF_OPER_STATE_RUNNING;
881 call_rxf_resume_cbfn(rxf, BNA_CB_SUCCESS);
882 bfa_fsm_set_state(rxf, bna_rxf_sm_started);
883 break;
884
885 /*
886 * Since PAUSE/RESUME can only be sent by bnad, we don't expect
887 * any other event during these states
888 */
889 default:
890 bfa_sm_fault(rxf->rx->bna, event);
891 }
892}
893
894static void
895bna_rxf_sm_stat_clr_wait_entry(struct bna_rxf *rxf)
896{
897 __bna_rxf_stat_clr(rxf);
898}
899
900static void
901bna_rxf_sm_stat_clr_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
902{
903 switch (event) {
904 case RXF_E_FAIL:
905 case RXF_E_STAT_CLEARED:
906 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
907 break;
908
909 default:
910 bfa_sm_fault(rxf->rx->bna, event);
911 }
912}
913
914static void
915__rxf_enable(struct bna_rxf *rxf)
916{
917 struct bfi_ll_rxf_multi_req ll_req;
918 u32 bm[2] = {0, 0};
919
920 if (rxf->rxf_id < 32)
921 bm[0] = 1 << rxf->rxf_id;
922 else
923 bm[1] = 1 << (rxf->rxf_id - 32);
924
925 bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_RX_REQ, 0);
926 ll_req.rxf_id_mask[0] = htonl(bm[0]);
927 ll_req.rxf_id_mask[1] = htonl(bm[1]);
928 ll_req.enable = 1;
929
930 bna_mbox_qe_fill(&rxf->mbox_qe, &ll_req, sizeof(ll_req),
931 rxf_cb_enabled, rxf);
932
933 bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe);
934}
935
936static void
937__rxf_disable(struct bna_rxf *rxf)
938{
939 struct bfi_ll_rxf_multi_req ll_req;
940 u32 bm[2] = {0, 0};
941
942 if (rxf->rxf_id < 32)
943 bm[0] = 1 << rxf->rxf_id;
944 else
945 bm[1] = 1 << (rxf->rxf_id - 32);
946
947 bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_RX_REQ, 0);
948 ll_req.rxf_id_mask[0] = htonl(bm[0]);
949 ll_req.rxf_id_mask[1] = htonl(bm[1]);
950 ll_req.enable = 0;
951
952 bna_mbox_qe_fill(&rxf->mbox_qe, &ll_req, sizeof(ll_req),
953 rxf_cb_disabled, rxf);
954
955 bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe);
956}
957
958static void
959__rxf_config_set(struct bna_rxf *rxf)
960{
961 u32 i;
962 struct bna_rss_mem *rss_mem;
963 struct bna_rx_fndb_ram *rx_fndb_ram;
964 struct bna *bna = rxf->rx->bna;
965 void __iomem *base_addr;
966 unsigned long off;
967
968 base_addr = BNA_GET_MEM_BASE_ADDR(bna->pcidev.pci_bar_kva,
969 RSS_TABLE_BASE_OFFSET);
970
971 rss_mem = (struct bna_rss_mem *)0;
972
973 /* Configure RSS if required */
974 if (rxf->ctrl_flags & BNA_RXF_CF_RSS_ENABLE) {
975 /* configure RSS Table */
976 writel(BNA_GET_PAGE_NUM(RAD0_MEM_BLK_BASE_PG_NUM +
977 bna->port_num, RSS_TABLE_BASE_OFFSET),
978 bna->regs.page_addr);
979
980 /* temporarily disable RSS, while hash value is written */
981 off = (unsigned long)&rss_mem[0].type_n_hash;
982 writel(0, base_addr + off);
983
984 for (i = 0; i < BFI_RSS_HASH_KEY_LEN; i++) {
985 off = (unsigned long)
986 &rss_mem[0].hash_key[(BFI_RSS_HASH_KEY_LEN - 1) - i];
987 writel(htonl(rxf->rss_cfg.toeplitz_hash_key[i]),
988 base_addr + off);
989 }
990
991 off = (unsigned long)&rss_mem[0].type_n_hash;
992 writel(rxf->rss_cfg.hash_type | rxf->rss_cfg.hash_mask,
993 base_addr + off);
994 }
995
996 /* Configure RxF */
997 writel(BNA_GET_PAGE_NUM(
998 LUT0_MEM_BLK_BASE_PG_NUM + (bna->port_num * 2),
999 RX_FNDB_RAM_BASE_OFFSET),
1000 bna->regs.page_addr);
1001
1002 base_addr = BNA_GET_MEM_BASE_ADDR(bna->pcidev.pci_bar_kva,
1003 RX_FNDB_RAM_BASE_OFFSET);
1004
1005 rx_fndb_ram = (struct bna_rx_fndb_ram *)0;
1006
1007 /* We always use RSS table 0 */
1008 off = (unsigned long)&rx_fndb_ram[rxf->rxf_id].rss_prop;
1009 writel(rxf->ctrl_flags & BNA_RXF_CF_RSS_ENABLE,
1010 base_addr + off);
1011
1012 /* small large buffer enable/disable */
1013 off = (unsigned long)&rx_fndb_ram[rxf->rxf_id].size_routing_props;
1014 writel((rxf->ctrl_flags & BNA_RXF_CF_SM_LG_RXQ) | 0x80,
1015 base_addr + off);
1016
1017 /* RIT offset, HDS forced offset, multicast RxQ Id */
1018 off = (unsigned long)&rx_fndb_ram[rxf->rxf_id].rit_hds_mcastq;
1019 writel((rxf->rit_segment->rit_offset << 16) |
1020 (rxf->forced_offset << 8) |
1021 (rxf->hds_cfg.hdr_type & BNA_HDS_FORCED) | rxf->mcast_rxq_id,
1022 base_addr + off);
1023
1024 /*
1025 * default vlan tag, default function enable, strip vlan bytes,
1026 * HDS type, header size
1027 */
1028
1029 off = (unsigned long)&rx_fndb_ram[rxf->rxf_id].control_flags;
1030 writel(((u32)rxf->default_vlan_tag << 16) |
1031 (rxf->ctrl_flags &
1032 (BNA_RXF_CF_DEFAULT_VLAN |
1033 BNA_RXF_CF_DEFAULT_FUNCTION_ENABLE |
1034 BNA_RXF_CF_VLAN_STRIP)) |
1035 (rxf->hds_cfg.hdr_type & ~BNA_HDS_FORCED) |
1036 rxf->hds_cfg.header_size,
1037 base_addr + off);
1038}
1039
1040void
1041__rxf_vlan_filter_set(struct bna_rxf *rxf, enum bna_status status)
1042{
1043 struct bna *bna = rxf->rx->bna;
1044 int i;
1045
1046 writel(BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM +
1047 (bna->port_num * 2), VLAN_RAM_BASE_OFFSET),
1048 bna->regs.page_addr);
1049
1050 if (status == BNA_STATUS_T_ENABLED) {
1051 /* enable VLAN filtering on this function */
1052 for (i = 0; i <= BFI_MAX_VLAN / 32; i++) {
1053 writel(rxf->vlan_filter_table[i],
1054 BNA_GET_VLAN_MEM_ENTRY_ADDR
1055 (bna->pcidev.pci_bar_kva, rxf->rxf_id,
1056 i * 32));
1057 }
1058 } else {
1059 /* disable VLAN filtering on this function */
1060 for (i = 0; i <= BFI_MAX_VLAN / 32; i++) {
1061 writel(0xffffffff,
1062 BNA_GET_VLAN_MEM_ENTRY_ADDR
1063 (bna->pcidev.pci_bar_kva, rxf->rxf_id,
1064 i * 32));
1065 }
1066 }
1067}
1068
1069static void
1070__rxf_rit_set(struct bna_rxf *rxf)
1071{
1072 struct bna *bna = rxf->rx->bna;
1073 struct bna_rit_mem *rit_mem;
1074 int i;
1075 void __iomem *base_addr;
1076 unsigned long off;
1077
1078 base_addr = BNA_GET_MEM_BASE_ADDR(bna->pcidev.pci_bar_kva,
1079 FUNCTION_TO_RXQ_TRANSLATE);
1080
1081 rit_mem = (struct bna_rit_mem *)0;
1082
1083 writel(BNA_GET_PAGE_NUM(RXA0_MEM_BLK_BASE_PG_NUM + bna->port_num,
1084 FUNCTION_TO_RXQ_TRANSLATE),
1085 bna->regs.page_addr);
1086
1087 for (i = 0; i < rxf->rit_segment->rit_size; i++) {
1088 off = (unsigned long)&rit_mem[i + rxf->rit_segment->rit_offset];
1089 writel(rxf->rit_segment->rit[i].large_rxq_id << 6 |
1090 rxf->rit_segment->rit[i].small_rxq_id,
1091 base_addr + off);
1092 }
1093}
1094
1095static void
1096__bna_rxf_stat_clr(struct bna_rxf *rxf)
1097{
1098 struct bfi_ll_stats_req ll_req;
1099 u32 bm[2] = {0, 0};
1100
1101 if (rxf->rxf_id < 32)
1102 bm[0] = 1 << rxf->rxf_id;
1103 else
1104 bm[1] = 1 << (rxf->rxf_id - 32);
1105
1106 bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_STATS_CLEAR_REQ, 0);
1107 ll_req.stats_mask = 0;
1108 ll_req.txf_id_mask[0] = 0;
1109 ll_req.txf_id_mask[1] = 0;
1110
1111 ll_req.rxf_id_mask[0] = htonl(bm[0]);
1112 ll_req.rxf_id_mask[1] = htonl(bm[1]);
1113
1114 bna_mbox_qe_fill(&rxf->mbox_qe, &ll_req, sizeof(ll_req),
1115 bna_rxf_cb_stats_cleared, rxf);
1116 bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe);
1117}
1118
1119static void
1120rxf_enable(struct bna_rxf *rxf)
1121{
1122 if (rxf->rxf_oper_state == BNA_RXF_OPER_STATE_PAUSED)
1123 bfa_fsm_send_event(rxf, RXF_E_STARTED);
1124 else {
1125 rxf->rxf_flags |= BNA_RXF_FL_RXF_ENABLED;
1126 __rxf_enable(rxf);
1127 }
1128}
1129
1130static void
1131rxf_cb_enabled(void *arg, int status)
1132{
1133 struct bna_rxf *rxf = (struct bna_rxf *)arg;
1134
1135 bfa_q_qe_init(&rxf->mbox_qe.qe);
1136 bfa_fsm_send_event(rxf, RXF_E_STARTED);
1137}
1138
1139static void
1140rxf_disable(struct bna_rxf *rxf)
1141{
1142 if (rxf->rxf_oper_state == BNA_RXF_OPER_STATE_PAUSED)
1143 bfa_fsm_send_event(rxf, RXF_E_STOPPED);
1144 else
1145 rxf->rxf_flags &= ~BNA_RXF_FL_RXF_ENABLED;
1146 __rxf_disable(rxf);
1147}
1148
1149static void
1150rxf_cb_disabled(void *arg, int status)
1151{
1152 struct bna_rxf *rxf = (struct bna_rxf *)arg;
1153
1154 bfa_q_qe_init(&rxf->mbox_qe.qe);
1155 bfa_fsm_send_event(rxf, RXF_E_STOPPED);
1156}
1157
1158void
1159rxf_cb_cam_fltr_mbox_cmd(void *arg, int status)
1160{
1161 struct bna_rxf *rxf = (struct bna_rxf *)arg;
1162
1163 bfa_q_qe_init(&rxf->mbox_qe.qe);
1164
1165 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_RESP);
1166}
1167
1168static void
1169bna_rxf_cb_stats_cleared(void *arg, int status)
1170{
1171 struct bna_rxf *rxf = (struct bna_rxf *)arg;
1172
1173 bfa_q_qe_init(&rxf->mbox_qe.qe);
1174 bfa_fsm_send_event(rxf, RXF_E_STAT_CLEARED);
1175}
1176
1177void
1178rxf_cam_mbox_cmd(struct bna_rxf *rxf, u8 cmd,
1179 const struct bna_mac *mac_addr)
1180{
1181 struct bfi_ll_mac_addr_req req;
1182
1183 bfi_h2i_set(req.mh, BFI_MC_LL, cmd, 0);
1184
1185 req.rxf_id = rxf->rxf_id;
1186 memcpy(&req.mac_addr, (void *)&mac_addr->addr, ETH_ALEN);
1187
1188 bna_mbox_qe_fill(&rxf->mbox_qe, &req, sizeof(req),
1189 rxf_cb_cam_fltr_mbox_cmd, rxf);
1190
1191 bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe);
1192}
1193
1194static int
1195rxf_process_packet_filter_mcast(struct bna_rxf *rxf)
1196{
1197 struct bna_mac *mac = NULL;
1198 struct list_head *qe;
1199
1200 /* Add multicast entries */
1201 if (!list_empty(&rxf->mcast_pending_add_q)) {
1202 bfa_q_deq(&rxf->mcast_pending_add_q, &qe);
1203 bfa_q_qe_init(qe);
1204 mac = (struct bna_mac *)qe;
1205 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_ADD_REQ, mac);
1206 list_add_tail(&mac->qe, &rxf->mcast_active_q);
1207 return 1;
1208 }
1209
1210 /* Delete multicast entries previousely added */
1211 if (!list_empty(&rxf->mcast_pending_del_q)) {
1212 bfa_q_deq(&rxf->mcast_pending_del_q, &qe);
1213 bfa_q_qe_init(qe);
1214 mac = (struct bna_mac *)qe;
1215 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_DEL_REQ, mac);
1216 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
1217 return 1;
1218 }
1219
1220 return 0;
1221}
1222
1223static int
1224rxf_process_packet_filter_vlan(struct bna_rxf *rxf)
1225{
1226 /* Apply the VLAN filter */
1227 if (rxf->rxf_flags & BNA_RXF_FL_VLAN_CONFIG_PENDING) {
1228 rxf->rxf_flags &= ~BNA_RXF_FL_VLAN_CONFIG_PENDING;
1229 if (!(rxf->rxmode_active & BNA_RXMODE_PROMISC) &&
1230 !(rxf->rxmode_active & BNA_RXMODE_DEFAULT))
1231 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
1232 }
1233
1234 /* Apply RSS configuration */
1235 if (rxf->rxf_flags & BNA_RXF_FL_RSS_CONFIG_PENDING) {
1236 rxf->rxf_flags &= ~BNA_RXF_FL_RSS_CONFIG_PENDING;
1237 if (rxf->rss_status == BNA_STATUS_T_DISABLED) {
1238 /* RSS is being disabled */
1239 rxf->ctrl_flags &= ~BNA_RXF_CF_RSS_ENABLE;
1240 __rxf_rit_set(rxf);
1241 __rxf_config_set(rxf);
1242 } else {
1243 /* RSS is being enabled or reconfigured */
1244 rxf->ctrl_flags |= BNA_RXF_CF_RSS_ENABLE;
1245 __rxf_rit_set(rxf);
1246 __rxf_config_set(rxf);
1247 }
1248 }
1249
1250 return 0;
1251}
1252
1253/**
1254 * Processes pending ucast, mcast entry addition/deletion and issues mailbox
1255 * command. Also processes pending filter configuration - promiscuous mode,
1256 * default mode, allmutli mode and issues mailbox command or directly applies
1257 * to h/w
1258 */
1259static int
1260rxf_process_packet_filter(struct bna_rxf *rxf)
1261{
1262 /* Set the default MAC first */
1263 if (rxf->ucast_pending_set > 0) {
1264 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_SET_REQ,
1265 rxf->ucast_active_mac);
1266 rxf->ucast_pending_set--;
1267 return 1;
1268 }
1269
1270 if (rxf_process_packet_filter_ucast(rxf))
1271 return 1;
1272
1273 if (rxf_process_packet_filter_mcast(rxf))
1274 return 1;
1275
1276 if (rxf_process_packet_filter_promisc(rxf))
1277 return 1;
1278
1279 if (rxf_process_packet_filter_default(rxf))
1280 return 1;
1281
1282 if (rxf_process_packet_filter_allmulti(rxf))
1283 return 1;
1284
1285 if (rxf_process_packet_filter_vlan(rxf))
1286 return 1;
1287
1288 return 0;
1289}
1290
1291static int
1292rxf_clear_packet_filter_mcast(struct bna_rxf *rxf)
1293{
1294 struct bna_mac *mac = NULL;
1295 struct list_head *qe;
1296
1297 /* 3. delete pending mcast entries */
1298 if (!list_empty(&rxf->mcast_pending_del_q)) {
1299 bfa_q_deq(&rxf->mcast_pending_del_q, &qe);
1300 bfa_q_qe_init(qe);
1301 mac = (struct bna_mac *)qe;
1302 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_DEL_REQ, mac);
1303 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
1304 return 1;
1305 }
1306
1307 /* 4. clear active mcast entries; move them to pending_add_q */
1308 if (!list_empty(&rxf->mcast_active_q)) {
1309 bfa_q_deq(&rxf->mcast_active_q, &qe);
1310 bfa_q_qe_init(qe);
1311 mac = (struct bna_mac *)qe;
1312 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_DEL_REQ, mac);
1313 list_add_tail(&mac->qe, &rxf->mcast_pending_add_q);
1314 return 1;
1315 }
1316
1317 return 0;
1318}
1319
1320/**
1321 * In the rxf stop path, processes pending ucast/mcast delete queue and issues
1322 * the mailbox command. Moves the active ucast/mcast entries to pending add q,
1323 * so that they are added to CAM again in the rxf start path. Moves the current
1324 * filter settings - promiscuous, default, allmutli - to pending filter
1325 * configuration
1326 */
1327static int
1328rxf_clear_packet_filter(struct bna_rxf *rxf)
1329{
1330 if (rxf_clear_packet_filter_ucast(rxf))
1331 return 1;
1332
1333 if (rxf_clear_packet_filter_mcast(rxf))
1334 return 1;
1335
1336 /* 5. clear active default MAC in the CAM */
1337 if (rxf->ucast_pending_set > 0)
1338 rxf->ucast_pending_set = 0;
1339
1340 if (rxf_clear_packet_filter_promisc(rxf))
1341 return 1;
1342
1343 if (rxf_clear_packet_filter_default(rxf))
1344 return 1;
1345
1346 if (rxf_clear_packet_filter_allmulti(rxf))
1347 return 1;
1348
1349 return 0;
1350}
1351
1352static void
1353rxf_reset_packet_filter_mcast(struct bna_rxf *rxf)
1354{
1355 struct list_head *qe;
1356 struct bna_mac *mac;
1357
1358 /* 3. Move active mcast entries to pending_add_q */
1359 while (!list_empty(&rxf->mcast_active_q)) {
1360 bfa_q_deq(&rxf->mcast_active_q, &qe);
1361 bfa_q_qe_init(qe);
1362 list_add_tail(qe, &rxf->mcast_pending_add_q);
1363 }
1364
1365 /* 4. Throw away delete pending mcast entries */
1366 while (!list_empty(&rxf->mcast_pending_del_q)) {
1367 bfa_q_deq(&rxf->mcast_pending_del_q, &qe);
1368 bfa_q_qe_init(qe);
1369 mac = (struct bna_mac *)qe;
1370 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
1371 }
1372}
1373
1374/**
1375 * In the rxf fail path, throws away the ucast/mcast entries pending for
1376 * deletion, moves all active ucast/mcast entries to pending queue so that
1377 * they are added back to CAM in the rxf start path. Also moves the current
1378 * filter configuration to pending filter configuration.
1379 */
1380static void
1381rxf_reset_packet_filter(struct bna_rxf *rxf)
1382{
1383 rxf_reset_packet_filter_ucast(rxf);
1384
1385 rxf_reset_packet_filter_mcast(rxf);
1386
1387 /* 5. Turn off ucast set flag */
1388 rxf->ucast_pending_set = 0;
1389
1390 rxf_reset_packet_filter_promisc(rxf);
1391
1392 rxf_reset_packet_filter_default(rxf);
1393
1394 rxf_reset_packet_filter_allmulti(rxf);
1395}
1396
1397void
1398bna_rxf_init(struct bna_rxf *rxf,
1399 struct bna_rx *rx,
1400 struct bna_rx_config *q_config)
1401{
1402 struct list_head *qe;
1403 struct bna_rxp *rxp;
1404
1405 /* rxf_id is initialized during rx_mod init */
1406 rxf->rx = rx;
1407
1408 INIT_LIST_HEAD(&rxf->ucast_pending_add_q);
1409 INIT_LIST_HEAD(&rxf->ucast_pending_del_q);
1410 rxf->ucast_pending_set = 0;
1411 INIT_LIST_HEAD(&rxf->ucast_active_q);
1412 rxf->ucast_active_mac = NULL;
1413
1414 INIT_LIST_HEAD(&rxf->mcast_pending_add_q);
1415 INIT_LIST_HEAD(&rxf->mcast_pending_del_q);
1416 INIT_LIST_HEAD(&rxf->mcast_active_q);
1417
1418 bfa_q_qe_init(&rxf->mbox_qe.qe);
1419
1420 if (q_config->vlan_strip_status == BNA_STATUS_T_ENABLED)
1421 rxf->ctrl_flags |= BNA_RXF_CF_VLAN_STRIP;
1422
1423 rxf->rxf_oper_state = (q_config->paused) ?
1424 BNA_RXF_OPER_STATE_PAUSED : BNA_RXF_OPER_STATE_RUNNING;
1425
1426 bna_rxf_adv_init(rxf, rx, q_config);
1427
1428 rxf->rit_segment = bna_rit_mod_seg_get(&rxf->rx->bna->rit_mod,
1429 q_config->num_paths);
1430
1431 list_for_each(qe, &rx->rxp_q) {
1432 rxp = (struct bna_rxp *)qe;
1433 if (q_config->rxp_type == BNA_RXP_SINGLE)
1434 rxf->mcast_rxq_id = rxp->rxq.single.only->rxq_id;
1435 else
1436 rxf->mcast_rxq_id = rxp->rxq.slr.large->rxq_id;
1437 break;
1438 }
1439
1440 rxf->vlan_filter_status = BNA_STATUS_T_DISABLED;
1441 memset(rxf->vlan_filter_table, 0,
1442 (sizeof(u32) * ((BFI_MAX_VLAN + 1) / 32)));
1443
1444 bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
1445}
1446
1447void
1448bna_rxf_uninit(struct bna_rxf *rxf)
1449{
1450 struct bna_mac *mac;
1451
1452 bna_rit_mod_seg_put(&rxf->rx->bna->rit_mod, rxf->rit_segment);
1453 rxf->rit_segment = NULL;
1454
1455 rxf->ucast_pending_set = 0;
1456
1457 while (!list_empty(&rxf->ucast_pending_add_q)) {
1458 bfa_q_deq(&rxf->ucast_pending_add_q, &mac);
1459 bfa_q_qe_init(&mac->qe);
1460 bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
1461 }
1462
1463 if (rxf->ucast_active_mac) {
1464 bfa_q_qe_init(&rxf->ucast_active_mac->qe);
1465 bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod,
1466 rxf->ucast_active_mac);
1467 rxf->ucast_active_mac = NULL;
1468 }
1469
1470 while (!list_empty(&rxf->mcast_pending_add_q)) {
1471 bfa_q_deq(&rxf->mcast_pending_add_q, &mac);
1472 bfa_q_qe_init(&mac->qe);
1473 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
1474 }
1475
1476 rxf->rx = NULL;
1477}
1478
1479void
1480bna_rxf_start(struct bna_rxf *rxf)
1481{
1482 rxf->start_cbfn = bna_rx_cb_rxf_started;
1483 rxf->start_cbarg = rxf->rx;
1484 rxf->rxf_flags &= ~BNA_RXF_FL_FAILED;
1485 bfa_fsm_send_event(rxf, RXF_E_START);
1486}
1487
1488void
1489bna_rxf_stop(struct bna_rxf *rxf)
1490{
1491 rxf->stop_cbfn = bna_rx_cb_rxf_stopped;
1492 rxf->stop_cbarg = rxf->rx;
1493 bfa_fsm_send_event(rxf, RXF_E_STOP);
1494}
1495
1496void
1497bna_rxf_fail(struct bna_rxf *rxf)
1498{
1499 rxf->rxf_flags |= BNA_RXF_FL_FAILED;
1500 bfa_fsm_send_event(rxf, RXF_E_FAIL);
1501}
1502
1503int
1504bna_rxf_state_get(struct bna_rxf *rxf)
1505{
1506 return bfa_sm_to_state(rxf_sm_table, rxf->fsm);
1507}
1508
1509enum bna_cb_status
1510bna_rx_ucast_set(struct bna_rx *rx, u8 *ucmac,
1511 void (*cbfn)(struct bnad *, struct bna_rx *,
1512 enum bna_cb_status))
1513{
1514 struct bna_rxf *rxf = &rx->rxf;
1515
1516 if (rxf->ucast_active_mac == NULL) {
1517 rxf->ucast_active_mac =
1518 bna_ucam_mod_mac_get(&rxf->rx->bna->ucam_mod);
1519 if (rxf->ucast_active_mac == NULL)
1520 return BNA_CB_UCAST_CAM_FULL;
1521 bfa_q_qe_init(&rxf->ucast_active_mac->qe);
1522 }
1523
1524 memcpy(rxf->ucast_active_mac->addr, ucmac, ETH_ALEN);
1525 rxf->ucast_pending_set++;
1526 rxf->cam_fltr_cbfn = cbfn;
1527 rxf->cam_fltr_cbarg = rx->bna->bnad;
1528
1529 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
1530
1531 return BNA_CB_SUCCESS;
1532}
1533
1534enum bna_cb_status
1535bna_rx_mcast_add(struct bna_rx *rx, u8 *addr,
1536 void (*cbfn)(struct bnad *, struct bna_rx *,
1537 enum bna_cb_status))
1538{
1539 struct bna_rxf *rxf = &rx->rxf;
1540 struct list_head *qe;
1541 struct bna_mac *mac;
1542
1543 /* Check if already added */
1544 list_for_each(qe, &rxf->mcast_active_q) {
1545 mac = (struct bna_mac *)qe;
1546 if (BNA_MAC_IS_EQUAL(mac->addr, addr)) {
1547 if (cbfn)
1548 (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
1549 return BNA_CB_SUCCESS;
1550 }
1551 }
1552
1553 /* Check if pending addition */
1554 list_for_each(qe, &rxf->mcast_pending_add_q) {
1555 mac = (struct bna_mac *)qe;
1556 if (BNA_MAC_IS_EQUAL(mac->addr, addr)) {
1557 if (cbfn)
1558 (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
1559 return BNA_CB_SUCCESS;
1560 }
1561 }
1562
1563 mac = bna_mcam_mod_mac_get(&rxf->rx->bna->mcam_mod);
1564 if (mac == NULL)
1565 return BNA_CB_MCAST_LIST_FULL;
1566 bfa_q_qe_init(&mac->qe);
1567 memcpy(mac->addr, addr, ETH_ALEN);
1568 list_add_tail(&mac->qe, &rxf->mcast_pending_add_q);
1569
1570 rxf->cam_fltr_cbfn = cbfn;
1571 rxf->cam_fltr_cbarg = rx->bna->bnad;
1572
1573 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
1574
1575 return BNA_CB_SUCCESS;
1576}
1577
1578enum bna_cb_status
1579bna_rx_mcast_del(struct bna_rx *rx, u8 *addr,
1580 void (*cbfn)(struct bnad *, struct bna_rx *,
1581 enum bna_cb_status))
1582{
1583 struct bna_rxf *rxf = &rx->rxf;
1584 struct list_head *qe;
1585 struct bna_mac *mac;
1586
1587 list_for_each(qe, &rxf->mcast_pending_add_q) {
1588 mac = (struct bna_mac *)qe;
1589 if (BNA_MAC_IS_EQUAL(mac->addr, addr)) {
1590 list_del(qe);
1591 bfa_q_qe_init(qe);
1592 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
1593 if (cbfn)
1594 (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
1595 return BNA_CB_SUCCESS;
1596 }
1597 }
1598
1599 list_for_each(qe, &rxf->mcast_active_q) {
1600 mac = (struct bna_mac *)qe;
1601 if (BNA_MAC_IS_EQUAL(mac->addr, addr)) {
1602 list_del(qe);
1603 bfa_q_qe_init(qe);
1604 list_add_tail(qe, &rxf->mcast_pending_del_q);
1605 rxf->cam_fltr_cbfn = cbfn;
1606 rxf->cam_fltr_cbarg = rx->bna->bnad;
1607 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
1608 return BNA_CB_SUCCESS;
1609 }
1610 }
1611
1612 return BNA_CB_INVALID_MAC;
1613}
1614
1615enum bna_cb_status
1616bna_rx_mcast_listset(struct bna_rx *rx, int count, u8 *mclist,
1617 void (*cbfn)(struct bnad *, struct bna_rx *,
1618 enum bna_cb_status))
1619{
1620 struct bna_rxf *rxf = &rx->rxf;
1621 struct list_head list_head;
1622 struct list_head *qe;
1623 u8 *mcaddr;
1624 struct bna_mac *mac;
1625 struct bna_mac *mac1;
1626 int skip;
1627 int delete;
1628 int need_hw_config = 0;
1629 int i;
1630
1631 /* Allocate nodes */
1632 INIT_LIST_HEAD(&list_head);
1633 for (i = 0, mcaddr = mclist; i < count; i++) {
1634 mac = bna_mcam_mod_mac_get(&rxf->rx->bna->mcam_mod);
1635 if (mac == NULL)
1636 goto err_return;
1637 bfa_q_qe_init(&mac->qe);
1638 memcpy(mac->addr, mcaddr, ETH_ALEN);
1639 list_add_tail(&mac->qe, &list_head);
1640
1641 mcaddr += ETH_ALEN;
1642 }
1643
1644 /* Schedule for addition */
1645 while (!list_empty(&list_head)) {
1646 bfa_q_deq(&list_head, &qe);
1647 mac = (struct bna_mac *)qe;
1648 bfa_q_qe_init(&mac->qe);
1649
1650 skip = 0;
1651
1652 /* Skip if already added */
1653 list_for_each(qe, &rxf->mcast_active_q) {
1654 mac1 = (struct bna_mac *)qe;
1655 if (BNA_MAC_IS_EQUAL(mac1->addr, mac->addr)) {
1656 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod,
1657 mac);
1658 skip = 1;
1659 break;
1660 }
1661 }
1662
1663 if (skip)
1664 continue;
1665
1666 /* Skip if pending addition */
1667 list_for_each(qe, &rxf->mcast_pending_add_q) {
1668 mac1 = (struct bna_mac *)qe;
1669 if (BNA_MAC_IS_EQUAL(mac1->addr, mac->addr)) {
1670 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod,
1671 mac);
1672 skip = 1;
1673 break;
1674 }
1675 }
1676
1677 if (skip)
1678 continue;
1679
1680 need_hw_config = 1;
1681 list_add_tail(&mac->qe, &rxf->mcast_pending_add_q);
1682 }
1683
1684 /**
1685 * Delete the entries that are in the pending_add_q but not
1686 * in the new list
1687 */
1688 while (!list_empty(&rxf->mcast_pending_add_q)) {
1689 bfa_q_deq(&rxf->mcast_pending_add_q, &qe);
1690 mac = (struct bna_mac *)qe;
1691 bfa_q_qe_init(&mac->qe);
1692 for (i = 0, mcaddr = mclist, delete = 1; i < count; i++) {
1693 if (BNA_MAC_IS_EQUAL(mcaddr, mac->addr)) {
1694 delete = 0;
1695 break;
1696 }
1697 mcaddr += ETH_ALEN;
1698 }
1699 if (delete)
1700 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
1701 else
1702 list_add_tail(&mac->qe, &list_head);
1703 }
1704 while (!list_empty(&list_head)) {
1705 bfa_q_deq(&list_head, &qe);
1706 mac = (struct bna_mac *)qe;
1707 bfa_q_qe_init(&mac->qe);
1708 list_add_tail(&mac->qe, &rxf->mcast_pending_add_q);
1709 }
1710
1711 /**
1712 * Schedule entries for deletion that are in the active_q but not
1713 * in the new list
1714 */
1715 while (!list_empty(&rxf->mcast_active_q)) {
1716 bfa_q_deq(&rxf->mcast_active_q, &qe);
1717 mac = (struct bna_mac *)qe;
1718 bfa_q_qe_init(&mac->qe);
1719 for (i = 0, mcaddr = mclist, delete = 1; i < count; i++) {
1720 if (BNA_MAC_IS_EQUAL(mcaddr, mac->addr)) {
1721 delete = 0;
1722 break;
1723 }
1724 mcaddr += ETH_ALEN;
1725 }
1726 if (delete) {
1727 list_add_tail(&mac->qe, &rxf->mcast_pending_del_q);
1728 need_hw_config = 1;
1729 } else {
1730 list_add_tail(&mac->qe, &list_head);
1731 }
1732 }
1733 while (!list_empty(&list_head)) {
1734 bfa_q_deq(&list_head, &qe);
1735 mac = (struct bna_mac *)qe;
1736 bfa_q_qe_init(&mac->qe);
1737 list_add_tail(&mac->qe, &rxf->mcast_active_q);
1738 }
1739
1740 if (need_hw_config) {
1741 rxf->cam_fltr_cbfn = cbfn;
1742 rxf->cam_fltr_cbarg = rx->bna->bnad;
1743 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
1744 } else if (cbfn)
1745 (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
1746
1747 return BNA_CB_SUCCESS;
1748
1749err_return:
1750 while (!list_empty(&list_head)) {
1751 bfa_q_deq(&list_head, &qe);
1752 mac = (struct bna_mac *)qe;
1753 bfa_q_qe_init(&mac->qe);
1754 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
1755 }
1756
1757 return BNA_CB_MCAST_LIST_FULL;
1758}
1759
1760void
1761bna_rx_vlan_add(struct bna_rx *rx, int vlan_id)
1762{
1763 struct bna_rxf *rxf = &rx->rxf;
1764 int index = (vlan_id >> 5);
1765 int bit = (1 << (vlan_id & 0x1F));
1766
1767 rxf->vlan_filter_table[index] |= bit;
1768 if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED) {
1769 rxf->rxf_flags |= BNA_RXF_FL_VLAN_CONFIG_PENDING;
1770 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
1771 }
1772}
1773
1774void
1775bna_rx_vlan_del(struct bna_rx *rx, int vlan_id)
1776{
1777 struct bna_rxf *rxf = &rx->rxf;
1778 int index = (vlan_id >> 5);
1779 int bit = (1 << (vlan_id & 0x1F));
1780
1781 rxf->vlan_filter_table[index] &= ~bit;
1782 if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED) {
1783 rxf->rxf_flags |= BNA_RXF_FL_VLAN_CONFIG_PENDING;
1784 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
1785 }
1786}
1787
1788/**
1789 * RX
1790 */
1791#define RXQ_RCB_INIT(q, rxp, qdepth, bna, _id, unmapq_mem) do { \
1792 struct bna_doorbell_qset *_qset; \
1793 unsigned long off; \
1794 (q)->rcb->producer_index = (q)->rcb->consumer_index = 0; \
1795 (q)->rcb->q_depth = (qdepth); \
1796 (q)->rcb->unmap_q = unmapq_mem; \
1797 (q)->rcb->rxq = (q); \
1798 (q)->rcb->cq = &(rxp)->cq; \
1799 (q)->rcb->bnad = (bna)->bnad; \
1800 _qset = (struct bna_doorbell_qset *)0; \
1801 off = (unsigned long)&_qset[(q)->rxq_id].rxq[0]; \
1802 (q)->rcb->q_dbell = off + \
1803 BNA_GET_DOORBELL_BASE_ADDR((bna)->pcidev.pci_bar_kva); \
1804 (q)->rcb->id = _id; \
1805} while (0)
1806
1807#define BNA_GET_RXQS(qcfg) (((qcfg)->rxp_type == BNA_RXP_SINGLE) ? \
1808 (qcfg)->num_paths : ((qcfg)->num_paths * 2))
1809
1810#define SIZE_TO_PAGES(size) (((size) >> PAGE_SHIFT) + ((((size) &\
1811 (PAGE_SIZE - 1)) + (PAGE_SIZE - 1)) >> PAGE_SHIFT))
1812
1813#define call_rx_stop_callback(rx, status) \
1814 if ((rx)->stop_cbfn) { \
1815 (*(rx)->stop_cbfn)((rx)->stop_cbarg, rx, (status)); \
1816 (rx)->stop_cbfn = NULL; \
1817 (rx)->stop_cbarg = NULL; \
1818 }
1819
1820/*
1821 * Since rx_enable is synchronous callback, there is no start_cbfn required.
1822 * Instead, we'll call bnad_rx_post(rxp) so that bnad can post the buffers
1823 * for each rxpath.
1824 */
1825
1826#define call_rx_disable_cbfn(rx, status) \
1827 if ((rx)->disable_cbfn) { \
1828 (*(rx)->disable_cbfn)((rx)->disable_cbarg, \
1829 status); \
1830 (rx)->disable_cbfn = NULL; \
1831 (rx)->disable_cbarg = NULL; \
1832 } \
1833
1834#define rxqs_reqd(type, num_rxqs) \
1835 (((type) == BNA_RXP_SINGLE) ? (num_rxqs) : ((num_rxqs) * 2))
1836
1837#define rx_ib_fail(rx) \
1838do { \
1839 struct bna_rxp *rxp; \
1840 struct list_head *qe; \
1841 list_for_each(qe, &(rx)->rxp_q) { \
1842 rxp = (struct bna_rxp *)qe; \
1843 bna_ib_fail(rxp->cq.ib); \
1844 } \
1845} while (0)
1846
1847static void __bna_multi_rxq_stop(struct bna_rxp *, u32 *);
1848static void __bna_rxq_start(struct bna_rxq *rxq);
1849static void __bna_cq_start(struct bna_cq *cq);
1850static void bna_rit_create(struct bna_rx *rx);
1851static void bna_rx_cb_multi_rxq_stopped(void *arg, int status);
1852static void bna_rx_cb_rxq_stopped_all(void *arg);
1853
1854bfa_fsm_state_decl(bna_rx, stopped,
1855 struct bna_rx, enum bna_rx_event);
1856bfa_fsm_state_decl(bna_rx, rxf_start_wait,
1857 struct bna_rx, enum bna_rx_event);
1858bfa_fsm_state_decl(bna_rx, started,
1859 struct bna_rx, enum bna_rx_event);
1860bfa_fsm_state_decl(bna_rx, rxf_stop_wait,
1861 struct bna_rx, enum bna_rx_event);
1862bfa_fsm_state_decl(bna_rx, rxq_stop_wait,
1863 struct bna_rx, enum bna_rx_event);
1864
1865static struct bfa_sm_table rx_sm_table[] = {
1866 {BFA_SM(bna_rx_sm_stopped), BNA_RX_STOPPED},
1867 {BFA_SM(bna_rx_sm_rxf_start_wait), BNA_RX_RXF_START_WAIT},
1868 {BFA_SM(bna_rx_sm_started), BNA_RX_STARTED},
1869 {BFA_SM(bna_rx_sm_rxf_stop_wait), BNA_RX_RXF_STOP_WAIT},
1870 {BFA_SM(bna_rx_sm_rxq_stop_wait), BNA_RX_RXQ_STOP_WAIT},
1871};
1872
1873static void bna_rx_sm_stopped_entry(struct bna_rx *rx)
1874{
1875 struct bna_rxp *rxp;
1876 struct list_head *qe_rxp;
1877
1878 list_for_each(qe_rxp, &rx->rxp_q) {
1879 rxp = (struct bna_rxp *)qe_rxp;
1880 rx->rx_cleanup_cbfn(rx->bna->bnad, rxp->cq.ccb);
1881 }
1882
1883 call_rx_stop_callback(rx, BNA_CB_SUCCESS);
1884}
1885
1886static void bna_rx_sm_stopped(struct bna_rx *rx,
1887 enum bna_rx_event event)
1888{
1889 switch (event) {
1890 case RX_E_START:
1891 bfa_fsm_set_state(rx, bna_rx_sm_rxf_start_wait);
1892 break;
1893 case RX_E_STOP:
1894 call_rx_stop_callback(rx, BNA_CB_SUCCESS);
1895 break;
1896 case RX_E_FAIL:
1897 /* no-op */
1898 break;
1899 default:
1900 bfa_sm_fault(rx->bna, event);
1901 break;
1902 }
1903
1904}
1905
1906static void bna_rx_sm_rxf_start_wait_entry(struct bna_rx *rx)
1907{
1908 struct bna_rxp *rxp;
1909 struct list_head *qe_rxp;
1910 struct bna_rxq *q0 = NULL, *q1 = NULL;
1911
1912 /* Setup the RIT */
1913 bna_rit_create(rx);
1914
1915 list_for_each(qe_rxp, &rx->rxp_q) {
1916 rxp = (struct bna_rxp *)qe_rxp;
1917 bna_ib_start(rxp->cq.ib);
1918 GET_RXQS(rxp, q0, q1);
1919 q0->buffer_size = bna_port_mtu_get(&rx->bna->port);
1920 __bna_rxq_start(q0);
1921 rx->rx_post_cbfn(rx->bna->bnad, q0->rcb);
1922 if (q1) {
1923 __bna_rxq_start(q1);
1924 rx->rx_post_cbfn(rx->bna->bnad, q1->rcb);
1925 }
1926 __bna_cq_start(&rxp->cq);
1927 }
1928
1929 bna_rxf_start(&rx->rxf);
1930}
1931
1932static void bna_rx_sm_rxf_start_wait(struct bna_rx *rx,
1933 enum bna_rx_event event)
1934{
1935 switch (event) {
1936 case RX_E_STOP:
1937 bfa_fsm_set_state(rx, bna_rx_sm_rxf_stop_wait);
1938 break;
1939 case RX_E_FAIL:
1940 bfa_fsm_set_state(rx, bna_rx_sm_stopped);
1941 rx_ib_fail(rx);
1942 bna_rxf_fail(&rx->rxf);
1943 break;
1944 case RX_E_RXF_STARTED:
1945 bfa_fsm_set_state(rx, bna_rx_sm_started);
1946 break;
1947 default:
1948 bfa_sm_fault(rx->bna, event);
1949 break;
1950 }
1951}
1952
1953void
1954bna_rx_sm_started_entry(struct bna_rx *rx)
1955{
1956 struct bna_rxp *rxp;
1957 struct list_head *qe_rxp;
1958
1959 /* Start IB */
1960 list_for_each(qe_rxp, &rx->rxp_q) {
1961 rxp = (struct bna_rxp *)qe_rxp;
1962 bna_ib_ack(&rxp->cq.ib->door_bell, 0);
1963 }
1964
1965 bna_llport_admin_up(&rx->bna->port.llport);
1966}
1967
1968void
1969bna_rx_sm_started(struct bna_rx *rx, enum bna_rx_event event)
1970{
1971 switch (event) {
1972 case RX_E_FAIL:
1973 bna_llport_admin_down(&rx->bna->port.llport);
1974 bfa_fsm_set_state(rx, bna_rx_sm_stopped);
1975 rx_ib_fail(rx);
1976 bna_rxf_fail(&rx->rxf);
1977 break;
1978 case RX_E_STOP:
1979 bna_llport_admin_down(&rx->bna->port.llport);
1980 bfa_fsm_set_state(rx, bna_rx_sm_rxf_stop_wait);
1981 break;
1982 default:
1983 bfa_sm_fault(rx->bna, event);
1984 break;
1985 }
1986}
1987
1988void
1989bna_rx_sm_rxf_stop_wait_entry(struct bna_rx *rx)
1990{
1991 bna_rxf_stop(&rx->rxf);
1992}
1993
1994void
1995bna_rx_sm_rxf_stop_wait(struct bna_rx *rx, enum bna_rx_event event)
1996{
1997 switch (event) {
1998 case RX_E_RXF_STOPPED:
1999 bfa_fsm_set_state(rx, bna_rx_sm_rxq_stop_wait);
2000 break;
2001 case RX_E_RXF_STARTED:
2002 /**
2003 * RxF was in the process of starting up when
2004 * RXF_E_STOP was issued. Ignore this event
2005 */
2006 break;
2007 case RX_E_FAIL:
2008 bfa_fsm_set_state(rx, bna_rx_sm_stopped);
2009 rx_ib_fail(rx);
2010 bna_rxf_fail(&rx->rxf);
2011 break;
2012 default:
2013 bfa_sm_fault(rx->bna, event);
2014 break;
2015 }
2016
2017}
2018
2019void
2020bna_rx_sm_rxq_stop_wait_entry(struct bna_rx *rx)
2021{
2022 struct bna_rxp *rxp = NULL;
2023 struct bna_rxq *q0 = NULL;
2024 struct bna_rxq *q1 = NULL;
2025 struct list_head *qe;
2026 u32 rxq_mask[2] = {0, 0};
2027
2028 /* Only one call to multi-rxq-stop for all RXPs in this RX */
2029 bfa_wc_up(&rx->rxq_stop_wc);
2030 list_for_each(qe, &rx->rxp_q) {
2031 rxp = (struct bna_rxp *)qe;
2032 GET_RXQS(rxp, q0, q1);
2033 if (q0->rxq_id < 32)
2034 rxq_mask[0] |= ((u32)1 << q0->rxq_id);
2035 else
2036 rxq_mask[1] |= ((u32)1 << (q0->rxq_id - 32));
2037 if (q1) {
2038 if (q1->rxq_id < 32)
2039 rxq_mask[0] |= ((u32)1 << q1->rxq_id);
2040 else
2041 rxq_mask[1] |= ((u32)
2042 1 << (q1->rxq_id - 32));
2043 }
2044 }
2045
2046 __bna_multi_rxq_stop(rxp, rxq_mask);
2047}
2048
2049void
2050bna_rx_sm_rxq_stop_wait(struct bna_rx *rx, enum bna_rx_event event)
2051{
2052 struct bna_rxp *rxp = NULL;
2053 struct list_head *qe;
2054
2055 switch (event) {
2056 case RX_E_RXQ_STOPPED:
2057 list_for_each(qe, &rx->rxp_q) {
2058 rxp = (struct bna_rxp *)qe;
2059 bna_ib_stop(rxp->cq.ib);
2060 }
2061 /* Fall through */
2062 case RX_E_FAIL:
2063 bfa_fsm_set_state(rx, bna_rx_sm_stopped);
2064 break;
2065 default:
2066 bfa_sm_fault(rx->bna, event);
2067 break;
2068 }
2069}
2070
2071void
2072__bna_multi_rxq_stop(struct bna_rxp *rxp, u32 * rxq_id_mask)
2073{
2074 struct bfi_ll_q_stop_req ll_req;
2075
2076 bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_RXQ_STOP_REQ, 0);
2077 ll_req.q_id_mask[0] = htonl(rxq_id_mask[0]);
2078 ll_req.q_id_mask[1] = htonl(rxq_id_mask[1]);
2079 bna_mbox_qe_fill(&rxp->mbox_qe, &ll_req, sizeof(ll_req),
2080 bna_rx_cb_multi_rxq_stopped, rxp);
2081 bna_mbox_send(rxp->rx->bna, &rxp->mbox_qe);
2082}
2083
2084void
2085__bna_rxq_start(struct bna_rxq *rxq)
2086{
2087 struct bna_rxtx_q_mem *q_mem;
2088 struct bna_rxq_mem rxq_cfg, *rxq_mem;
2089 struct bna_dma_addr cur_q_addr;
2090 /* struct bna_doorbell_qset *qset; */
2091 struct bna_qpt *qpt;
2092 u32 pg_num;
2093 struct bna *bna = rxq->rx->bna;
2094 void __iomem *base_addr;
2095 unsigned long off;
2096
2097 qpt = &rxq->qpt;
2098 cur_q_addr = *((struct bna_dma_addr *)(qpt->kv_qpt_ptr));
2099
2100 rxq_cfg.pg_tbl_addr_lo = qpt->hw_qpt_ptr.lsb;
2101 rxq_cfg.pg_tbl_addr_hi = qpt->hw_qpt_ptr.msb;
2102 rxq_cfg.cur_q_entry_lo = cur_q_addr.lsb;
2103 rxq_cfg.cur_q_entry_hi = cur_q_addr.msb;
2104
2105 rxq_cfg.pg_cnt_n_prd_ptr = ((u32)qpt->page_count << 16) | 0x0;
2106 rxq_cfg.entry_n_pg_size = ((u32)(BFI_RXQ_WI_SIZE >> 2) << 16) |
2107 (qpt->page_size >> 2);
2108 rxq_cfg.sg_n_cq_n_cns_ptr =
2109 ((u32)(rxq->rxp->cq.cq_id & 0xff) << 16) | 0x0;
2110 rxq_cfg.buf_sz_n_q_state = ((u32)rxq->buffer_size << 16) |
2111 BNA_Q_IDLE_STATE;
2112 rxq_cfg.next_qid = 0x0 | (0x3 << 8);
2113
2114 /* Write the page number register */
2115 pg_num = BNA_GET_PAGE_NUM(HQM0_BLK_PG_NUM + bna->port_num,
2116 HQM_RXTX_Q_RAM_BASE_OFFSET);
2117 writel(pg_num, bna->regs.page_addr);
2118
2119 /* Write to h/w */
2120 base_addr = BNA_GET_MEM_BASE_ADDR(bna->pcidev.pci_bar_kva,
2121 HQM_RXTX_Q_RAM_BASE_OFFSET);
2122
2123 q_mem = (struct bna_rxtx_q_mem *)0;
2124 rxq_mem = &q_mem[rxq->rxq_id].rxq;
2125
2126 off = (unsigned long)&rxq_mem->pg_tbl_addr_lo;
2127 writel(htonl(rxq_cfg.pg_tbl_addr_lo), base_addr + off);
2128
2129 off = (unsigned long)&rxq_mem->pg_tbl_addr_hi;
2130 writel(htonl(rxq_cfg.pg_tbl_addr_hi), base_addr + off);
2131
2132 off = (unsigned long)&rxq_mem->cur_q_entry_lo;
2133 writel(htonl(rxq_cfg.cur_q_entry_lo), base_addr + off);
2134
2135 off = (unsigned long)&rxq_mem->cur_q_entry_hi;
2136 writel(htonl(rxq_cfg.cur_q_entry_hi), base_addr + off);
2137
2138 off = (unsigned long)&rxq_mem->pg_cnt_n_prd_ptr;
2139 writel(rxq_cfg.pg_cnt_n_prd_ptr, base_addr + off);
2140
2141 off = (unsigned long)&rxq_mem->entry_n_pg_size;
2142 writel(rxq_cfg.entry_n_pg_size, base_addr + off);
2143
2144 off = (unsigned long)&rxq_mem->sg_n_cq_n_cns_ptr;
2145 writel(rxq_cfg.sg_n_cq_n_cns_ptr, base_addr + off);
2146
2147 off = (unsigned long)&rxq_mem->buf_sz_n_q_state;
2148 writel(rxq_cfg.buf_sz_n_q_state, base_addr + off);
2149
2150 off = (unsigned long)&rxq_mem->next_qid;
2151 writel(rxq_cfg.next_qid, base_addr + off);
2152
2153 rxq->rcb->producer_index = 0;
2154 rxq->rcb->consumer_index = 0;
2155}
2156
2157void
2158__bna_cq_start(struct bna_cq *cq)
2159{
2160 struct bna_cq_mem cq_cfg, *cq_mem;
2161 const struct bna_qpt *qpt;
2162 struct bna_dma_addr cur_q_addr;
2163 u32 pg_num;
2164 struct bna *bna = cq->rx->bna;
2165 void __iomem *base_addr;
2166 unsigned long off;
2167
2168 qpt = &cq->qpt;
2169 cur_q_addr = *((struct bna_dma_addr *)(qpt->kv_qpt_ptr));
2170
2171 /*
2172 * Fill out structure, to be subsequently written
2173 * to hardware
2174 */
2175 cq_cfg.pg_tbl_addr_lo = qpt->hw_qpt_ptr.lsb;
2176 cq_cfg.pg_tbl_addr_hi = qpt->hw_qpt_ptr.msb;
2177 cq_cfg.cur_q_entry_lo = cur_q_addr.lsb;
2178 cq_cfg.cur_q_entry_hi = cur_q_addr.msb;
2179
2180 cq_cfg.pg_cnt_n_prd_ptr = (qpt->page_count << 16) | 0x0;
2181 cq_cfg.entry_n_pg_size =
2182 ((u32)(BFI_CQ_WI_SIZE >> 2) << 16) | (qpt->page_size >> 2);
2183 cq_cfg.int_blk_n_cns_ptr = ((((u32)cq->ib_seg_offset) << 24) |
2184 ((u32)(cq->ib->ib_id & 0xff) << 16) | 0x0);
2185 cq_cfg.q_state = BNA_Q_IDLE_STATE;
2186
2187 /* Write the page number register */
2188 pg_num = BNA_GET_PAGE_NUM(HQM0_BLK_PG_NUM + bna->port_num,
2189 HQM_CQ_RAM_BASE_OFFSET);
2190
2191 writel(pg_num, bna->regs.page_addr);
2192
2193 /* H/W write */
2194 base_addr = BNA_GET_MEM_BASE_ADDR(bna->pcidev.pci_bar_kva,
2195 HQM_CQ_RAM_BASE_OFFSET);
2196
2197 cq_mem = (struct bna_cq_mem *)0;
2198
2199 off = (unsigned long)&cq_mem[cq->cq_id].pg_tbl_addr_lo;
2200 writel(htonl(cq_cfg.pg_tbl_addr_lo), base_addr + off);
2201
2202 off = (unsigned long)&cq_mem[cq->cq_id].pg_tbl_addr_hi;
2203 writel(htonl(cq_cfg.pg_tbl_addr_hi), base_addr + off);
2204
2205 off = (unsigned long)&cq_mem[cq->cq_id].cur_q_entry_lo;
2206 writel(htonl(cq_cfg.cur_q_entry_lo), base_addr + off);
2207
2208 off = (unsigned long)&cq_mem[cq->cq_id].cur_q_entry_hi;
2209 writel(htonl(cq_cfg.cur_q_entry_hi), base_addr + off);
2210
2211 off = (unsigned long)&cq_mem[cq->cq_id].pg_cnt_n_prd_ptr;
2212 writel(cq_cfg.pg_cnt_n_prd_ptr, base_addr + off);
2213
2214 off = (unsigned long)&cq_mem[cq->cq_id].entry_n_pg_size;
2215 writel(cq_cfg.entry_n_pg_size, base_addr + off);
2216
2217 off = (unsigned long)&cq_mem[cq->cq_id].int_blk_n_cns_ptr;
2218 writel(cq_cfg.int_blk_n_cns_ptr, base_addr + off);
2219
2220 off = (unsigned long)&cq_mem[cq->cq_id].q_state;
2221 writel(cq_cfg.q_state, base_addr + off);
2222
2223 cq->ccb->producer_index = 0;
2224 *(cq->ccb->hw_producer_index) = 0;
2225}
2226
2227void
2228bna_rit_create(struct bna_rx *rx)
2229{
2230 struct list_head *qe_rxp;
2231 struct bna *bna;
2232 struct bna_rxp *rxp;
2233 struct bna_rxq *q0 = NULL;
2234 struct bna_rxq *q1 = NULL;
2235 int offset;
2236
2237 bna = rx->bna;
2238
2239 offset = 0;
2240 list_for_each(qe_rxp, &rx->rxp_q) {
2241 rxp = (struct bna_rxp *)qe_rxp;
2242 GET_RXQS(rxp, q0, q1);
2243 rx->rxf.rit_segment->rit[offset].large_rxq_id = q0->rxq_id;
2244 rx->rxf.rit_segment->rit[offset].small_rxq_id =
2245 (q1 ? q1->rxq_id : 0);
2246 offset++;
2247 }
2248}
2249
2250int
2251_rx_can_satisfy(struct bna_rx_mod *rx_mod,
2252 struct bna_rx_config *rx_cfg)
2253{
2254 if ((rx_mod->rx_free_count == 0) ||
2255 (rx_mod->rxp_free_count == 0) ||
2256 (rx_mod->rxq_free_count == 0))
2257 return 0;
2258
2259 if (rx_cfg->rxp_type == BNA_RXP_SINGLE) {
2260 if ((rx_mod->rxp_free_count < rx_cfg->num_paths) ||
2261 (rx_mod->rxq_free_count < rx_cfg->num_paths))
2262 return 0;
2263 } else {
2264 if ((rx_mod->rxp_free_count < rx_cfg->num_paths) ||
2265 (rx_mod->rxq_free_count < (2 * rx_cfg->num_paths)))
2266 return 0;
2267 }
2268
2269 if (!bna_rit_mod_can_satisfy(&rx_mod->bna->rit_mod, rx_cfg->num_paths))
2270 return 0;
2271
2272 return 1;
2273}
2274
2275struct bna_rxq *
2276_get_free_rxq(struct bna_rx_mod *rx_mod)
2277{
2278 struct bna_rxq *rxq = NULL;
2279 struct list_head *qe = NULL;
2280
2281 bfa_q_deq(&rx_mod->rxq_free_q, &qe);
2282 if (qe) {
2283 rx_mod->rxq_free_count--;
2284 rxq = (struct bna_rxq *)qe;
2285 }
2286 return rxq;
2287}
2288
2289void
2290_put_free_rxq(struct bna_rx_mod *rx_mod, struct bna_rxq *rxq)
2291{
2292 bfa_q_qe_init(&rxq->qe);
2293 list_add_tail(&rxq->qe, &rx_mod->rxq_free_q);
2294 rx_mod->rxq_free_count++;
2295}
2296
2297struct bna_rxp *
2298_get_free_rxp(struct bna_rx_mod *rx_mod)
2299{
2300 struct list_head *qe = NULL;
2301 struct bna_rxp *rxp = NULL;
2302
2303 bfa_q_deq(&rx_mod->rxp_free_q, &qe);
2304 if (qe) {
2305 rx_mod->rxp_free_count--;
2306
2307 rxp = (struct bna_rxp *)qe;
2308 }
2309
2310 return rxp;
2311}
2312
2313void
2314_put_free_rxp(struct bna_rx_mod *rx_mod, struct bna_rxp *rxp)
2315{
2316 bfa_q_qe_init(&rxp->qe);
2317 list_add_tail(&rxp->qe, &rx_mod->rxp_free_q);
2318 rx_mod->rxp_free_count++;
2319}
2320
2321struct bna_rx *
2322_get_free_rx(struct bna_rx_mod *rx_mod)
2323{
2324 struct list_head *qe = NULL;
2325 struct bna_rx *rx = NULL;
2326
2327 bfa_q_deq(&rx_mod->rx_free_q, &qe);
2328 if (qe) {
2329 rx_mod->rx_free_count--;
2330
2331 rx = (struct bna_rx *)qe;
2332 bfa_q_qe_init(qe);
2333 list_add_tail(&rx->qe, &rx_mod->rx_active_q);
2334 }
2335
2336 return rx;
2337}
2338
2339void
2340_put_free_rx(struct bna_rx_mod *rx_mod, struct bna_rx *rx)
2341{
2342 bfa_q_qe_init(&rx->qe);
2343 list_add_tail(&rx->qe, &rx_mod->rx_free_q);
2344 rx_mod->rx_free_count++;
2345}
2346
2347void
2348_rx_init(struct bna_rx *rx, struct bna *bna)
2349{
2350 rx->bna = bna;
2351 rx->rx_flags = 0;
2352
2353 INIT_LIST_HEAD(&rx->rxp_q);
2354
2355 rx->rxq_stop_wc.wc_resume = bna_rx_cb_rxq_stopped_all;
2356 rx->rxq_stop_wc.wc_cbarg = rx;
2357 rx->rxq_stop_wc.wc_count = 0;
2358
2359 rx->stop_cbfn = NULL;
2360 rx->stop_cbarg = NULL;
2361}
2362
2363void
2364_rxp_add_rxqs(struct bna_rxp *rxp,
2365 struct bna_rxq *q0,
2366 struct bna_rxq *q1)
2367{
2368 switch (rxp->type) {
2369 case BNA_RXP_SINGLE:
2370 rxp->rxq.single.only = q0;
2371 rxp->rxq.single.reserved = NULL;
2372 break;
2373 case BNA_RXP_SLR:
2374 rxp->rxq.slr.large = q0;
2375 rxp->rxq.slr.small = q1;
2376 break;
2377 case BNA_RXP_HDS:
2378 rxp->rxq.hds.data = q0;
2379 rxp->rxq.hds.hdr = q1;
2380 break;
2381 default:
2382 break;
2383 }
2384}
2385
2386void
2387_rxq_qpt_init(struct bna_rxq *rxq,
2388 struct bna_rxp *rxp,
2389 u32 page_count,
2390 u32 page_size,
2391 struct bna_mem_descr *qpt_mem,
2392 struct bna_mem_descr *swqpt_mem,
2393 struct bna_mem_descr *page_mem)
2394{
2395 int i;
2396
2397 rxq->qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb;
2398 rxq->qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb;
2399 rxq->qpt.kv_qpt_ptr = qpt_mem->kva;
2400 rxq->qpt.page_count = page_count;
2401 rxq->qpt.page_size = page_size;
2402
2403 rxq->rcb->sw_qpt = (void **) swqpt_mem->kva;
2404
2405 for (i = 0; i < rxq->qpt.page_count; i++) {
2406 rxq->rcb->sw_qpt[i] = page_mem[i].kva;
2407 ((struct bna_dma_addr *)rxq->qpt.kv_qpt_ptr)[i].lsb =
2408 page_mem[i].dma.lsb;
2409 ((struct bna_dma_addr *)rxq->qpt.kv_qpt_ptr)[i].msb =
2410 page_mem[i].dma.msb;
2411
2412 }
2413}
2414
2415void
2416_rxp_cqpt_setup(struct bna_rxp *rxp,
2417 u32 page_count,
2418 u32 page_size,
2419 struct bna_mem_descr *qpt_mem,
2420 struct bna_mem_descr *swqpt_mem,
2421 struct bna_mem_descr *page_mem)
2422{
2423 int i;
2424
2425 rxp->cq.qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb;
2426 rxp->cq.qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb;
2427 rxp->cq.qpt.kv_qpt_ptr = qpt_mem->kva;
2428 rxp->cq.qpt.page_count = page_count;
2429 rxp->cq.qpt.page_size = page_size;
2430
2431 rxp->cq.ccb->sw_qpt = (void **) swqpt_mem->kva;
2432
2433 for (i = 0; i < rxp->cq.qpt.page_count; i++) {
2434 rxp->cq.ccb->sw_qpt[i] = page_mem[i].kva;
2435
2436 ((struct bna_dma_addr *)rxp->cq.qpt.kv_qpt_ptr)[i].lsb =
2437 page_mem[i].dma.lsb;
2438 ((struct bna_dma_addr *)rxp->cq.qpt.kv_qpt_ptr)[i].msb =
2439 page_mem[i].dma.msb;
2440
2441 }
2442}
2443
2444void
2445_rx_add_rxp(struct bna_rx *rx, struct bna_rxp *rxp)
2446{
2447 list_add_tail(&rxp->qe, &rx->rxp_q);
2448}
2449
2450void
2451_init_rxmod_queues(struct bna_rx_mod *rx_mod)
2452{
2453 INIT_LIST_HEAD(&rx_mod->rx_free_q);
2454 INIT_LIST_HEAD(&rx_mod->rxq_free_q);
2455 INIT_LIST_HEAD(&rx_mod->rxp_free_q);
2456 INIT_LIST_HEAD(&rx_mod->rx_active_q);
2457
2458 rx_mod->rx_free_count = 0;
2459 rx_mod->rxq_free_count = 0;
2460 rx_mod->rxp_free_count = 0;
2461}
2462
2463void
2464_rx_ctor(struct bna_rx *rx, int id)
2465{
2466 bfa_q_qe_init(&rx->qe);
2467 INIT_LIST_HEAD(&rx->rxp_q);
2468 rx->bna = NULL;
2469
2470 rx->rxf.rxf_id = id;
2471
2472 /* FIXME: mbox_qe ctor()?? */
2473 bfa_q_qe_init(&rx->mbox_qe.qe);
2474
2475 rx->stop_cbfn = NULL;
2476 rx->stop_cbarg = NULL;
2477}
2478
2479void
2480bna_rx_cb_multi_rxq_stopped(void *arg, int status)
2481{
2482 struct bna_rxp *rxp = (struct bna_rxp *)arg;
2483
2484 bfa_wc_down(&rxp->rx->rxq_stop_wc);
2485}
2486
2487void
2488bna_rx_cb_rxq_stopped_all(void *arg)
2489{
2490 struct bna_rx *rx = (struct bna_rx *)arg;
2491
2492 bfa_fsm_send_event(rx, RX_E_RXQ_STOPPED);
2493}
2494
2495void
2496bna_rx_mod_cb_rx_stopped(void *arg, struct bna_rx *rx,
2497 enum bna_cb_status status)
2498{
2499 struct bna_rx_mod *rx_mod = (struct bna_rx_mod *)arg;
2500
2501 bfa_wc_down(&rx_mod->rx_stop_wc);
2502}
2503
2504void
2505bna_rx_mod_cb_rx_stopped_all(void *arg)
2506{
2507 struct bna_rx_mod *rx_mod = (struct bna_rx_mod *)arg;
2508
2509 if (rx_mod->stop_cbfn)
2510 rx_mod->stop_cbfn(&rx_mod->bna->port, BNA_CB_SUCCESS);
2511 rx_mod->stop_cbfn = NULL;
2512}
2513
2514void
2515bna_rx_start(struct bna_rx *rx)
2516{
2517 rx->rx_flags |= BNA_RX_F_PORT_ENABLED;
2518 if (rx->rx_flags & BNA_RX_F_ENABLE)
2519 bfa_fsm_send_event(rx, RX_E_START);
2520}
2521
2522void
2523bna_rx_stop(struct bna_rx *rx)
2524{
2525 rx->rx_flags &= ~BNA_RX_F_PORT_ENABLED;
2526 if (rx->fsm == (bfa_fsm_t) bna_rx_sm_stopped)
2527 bna_rx_mod_cb_rx_stopped(&rx->bna->rx_mod, rx, BNA_CB_SUCCESS);
2528 else {
2529 rx->stop_cbfn = bna_rx_mod_cb_rx_stopped;
2530 rx->stop_cbarg = &rx->bna->rx_mod;
2531 bfa_fsm_send_event(rx, RX_E_STOP);
2532 }
2533}
2534
2535void
2536bna_rx_fail(struct bna_rx *rx)
2537{
2538 /* Indicate port is not enabled, and failed */
2539 rx->rx_flags &= ~BNA_RX_F_PORT_ENABLED;
2540 rx->rx_flags |= BNA_RX_F_PORT_FAILED;
2541 bfa_fsm_send_event(rx, RX_E_FAIL);
2542}
2543
2544void
2545bna_rx_cb_rxf_started(struct bna_rx *rx, enum bna_cb_status status)
2546{
2547 bfa_fsm_send_event(rx, RX_E_RXF_STARTED);
2548 if (rx->rxf.rxf_id < 32)
2549 rx->bna->rx_mod.rxf_bmap[0] |= ((u32)1 << rx->rxf.rxf_id);
2550 else
2551 rx->bna->rx_mod.rxf_bmap[1] |= ((u32)
2552 1 << (rx->rxf.rxf_id - 32));
2553}
2554
2555void
2556bna_rx_cb_rxf_stopped(struct bna_rx *rx, enum bna_cb_status status)
2557{
2558 bfa_fsm_send_event(rx, RX_E_RXF_STOPPED);
2559 if (rx->rxf.rxf_id < 32)
2560 rx->bna->rx_mod.rxf_bmap[0] &= ~(u32)1 << rx->rxf.rxf_id;
2561 else
2562 rx->bna->rx_mod.rxf_bmap[1] &= ~(u32)
2563 1 << (rx->rxf.rxf_id - 32);
2564}
2565
2566void
2567bna_rx_mod_start(struct bna_rx_mod *rx_mod, enum bna_rx_type type)
2568{
2569 struct bna_rx *rx;
2570 struct list_head *qe;
2571
2572 rx_mod->flags |= BNA_RX_MOD_F_PORT_STARTED;
2573 if (type == BNA_RX_T_LOOPBACK)
2574 rx_mod->flags |= BNA_RX_MOD_F_PORT_LOOPBACK;
2575
2576 list_for_each(qe, &rx_mod->rx_active_q) {
2577 rx = (struct bna_rx *)qe;
2578 if (rx->type == type)
2579 bna_rx_start(rx);
2580 }
2581}
2582
2583void
2584bna_rx_mod_stop(struct bna_rx_mod *rx_mod, enum bna_rx_type type)
2585{
2586 struct bna_rx *rx;
2587 struct list_head *qe;
2588
2589 rx_mod->flags &= ~BNA_RX_MOD_F_PORT_STARTED;
2590 rx_mod->flags &= ~BNA_RX_MOD_F_PORT_LOOPBACK;
2591
2592 rx_mod->stop_cbfn = bna_port_cb_rx_stopped;
2593
2594 /**
2595 * Before calling bna_rx_stop(), increment rx_stop_wc as many times
2596 * as we are going to call bna_rx_stop
2597 */
2598 list_for_each(qe, &rx_mod->rx_active_q) {
2599 rx = (struct bna_rx *)qe;
2600 if (rx->type == type)
2601 bfa_wc_up(&rx_mod->rx_stop_wc);
2602 }
2603
2604 if (rx_mod->rx_stop_wc.wc_count == 0) {
2605 rx_mod->stop_cbfn(&rx_mod->bna->port, BNA_CB_SUCCESS);
2606 rx_mod->stop_cbfn = NULL;
2607 return;
2608 }
2609
2610 list_for_each(qe, &rx_mod->rx_active_q) {
2611 rx = (struct bna_rx *)qe;
2612 if (rx->type == type)
2613 bna_rx_stop(rx);
2614 }
2615}
2616
2617void
2618bna_rx_mod_fail(struct bna_rx_mod *rx_mod)
2619{
2620 struct bna_rx *rx;
2621 struct list_head *qe;
2622
2623 rx_mod->flags &= ~BNA_RX_MOD_F_PORT_STARTED;
2624 rx_mod->flags &= ~BNA_RX_MOD_F_PORT_LOOPBACK;
2625
2626 list_for_each(qe, &rx_mod->rx_active_q) {
2627 rx = (struct bna_rx *)qe;
2628 bna_rx_fail(rx);
2629 }
2630}
2631
2632void bna_rx_mod_init(struct bna_rx_mod *rx_mod, struct bna *bna,
2633 struct bna_res_info *res_info)
2634{
2635 int index;
2636 struct bna_rx *rx_ptr;
2637 struct bna_rxp *rxp_ptr;
2638 struct bna_rxq *rxq_ptr;
2639
2640 rx_mod->bna = bna;
2641 rx_mod->flags = 0;
2642
2643 rx_mod->rx = (struct bna_rx *)
2644 res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.mdl[0].kva;
2645 rx_mod->rxp = (struct bna_rxp *)
2646 res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.mdl[0].kva;
2647 rx_mod->rxq = (struct bna_rxq *)
2648 res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.mdl[0].kva;
2649
2650 /* Initialize the queues */
2651 _init_rxmod_queues(rx_mod);
2652
2653 /* Build RX queues */
2654 for (index = 0; index < BFI_MAX_RXQ; index++) {
2655 rx_ptr = &rx_mod->rx[index];
2656 _rx_ctor(rx_ptr, index);
2657 list_add_tail(&rx_ptr->qe, &rx_mod->rx_free_q);
2658 rx_mod->rx_free_count++;
2659 }
2660
2661 /* build RX-path queue */
2662 for (index = 0; index < BFI_MAX_RXQ; index++) {
2663 rxp_ptr = &rx_mod->rxp[index];
2664 rxp_ptr->cq.cq_id = index;
2665 bfa_q_qe_init(&rxp_ptr->qe);
2666 list_add_tail(&rxp_ptr->qe, &rx_mod->rxp_free_q);
2667 rx_mod->rxp_free_count++;
2668 }
2669
2670 /* build RXQ queue */
2671 for (index = 0; index < BFI_MAX_RXQ; index++) {
2672 rxq_ptr = &rx_mod->rxq[index];
2673 rxq_ptr->rxq_id = index;
2674
2675 bfa_q_qe_init(&rxq_ptr->qe);
2676 list_add_tail(&rxq_ptr->qe, &rx_mod->rxq_free_q);
2677 rx_mod->rxq_free_count++;
2678 }
2679
2680 rx_mod->rx_stop_wc.wc_resume = bna_rx_mod_cb_rx_stopped_all;
2681 rx_mod->rx_stop_wc.wc_cbarg = rx_mod;
2682 rx_mod->rx_stop_wc.wc_count = 0;
2683}
2684
2685void
2686bna_rx_mod_uninit(struct bna_rx_mod *rx_mod)
2687{
2688 struct list_head *qe;
2689 int i;
2690
2691 i = 0;
2692 list_for_each(qe, &rx_mod->rx_free_q)
2693 i++;
2694
2695 i = 0;
2696 list_for_each(qe, &rx_mod->rxp_free_q)
2697 i++;
2698
2699 i = 0;
2700 list_for_each(qe, &rx_mod->rxq_free_q)
2701 i++;
2702
2703 rx_mod->bna = NULL;
2704}
2705
2706int
2707bna_rx_state_get(struct bna_rx *rx)
2708{
2709 return bfa_sm_to_state(rx_sm_table, rx->fsm);
2710}
2711
2712void
2713bna_rx_res_req(struct bna_rx_config *q_cfg, struct bna_res_info *res_info)
2714{
2715 u32 cq_size, hq_size, dq_size;
2716 u32 cpage_count, hpage_count, dpage_count;
2717 struct bna_mem_info *mem_info;
2718 u32 cq_depth;
2719 u32 hq_depth;
2720 u32 dq_depth;
2721
2722 dq_depth = q_cfg->q_depth;
2723 hq_depth = ((q_cfg->rxp_type == BNA_RXP_SINGLE) ? 0 : q_cfg->q_depth);
2724 cq_depth = dq_depth + hq_depth;
2725
2726 BNA_TO_POWER_OF_2_HIGH(cq_depth);
2727 cq_size = cq_depth * BFI_CQ_WI_SIZE;
2728 cq_size = ALIGN(cq_size, PAGE_SIZE);
2729 cpage_count = SIZE_TO_PAGES(cq_size);
2730
2731 BNA_TO_POWER_OF_2_HIGH(dq_depth);
2732 dq_size = dq_depth * BFI_RXQ_WI_SIZE;
2733 dq_size = ALIGN(dq_size, PAGE_SIZE);
2734 dpage_count = SIZE_TO_PAGES(dq_size);
2735
2736 if (BNA_RXP_SINGLE != q_cfg->rxp_type) {
2737 BNA_TO_POWER_OF_2_HIGH(hq_depth);
2738 hq_size = hq_depth * BFI_RXQ_WI_SIZE;
2739 hq_size = ALIGN(hq_size, PAGE_SIZE);
2740 hpage_count = SIZE_TO_PAGES(hq_size);
2741 } else {
2742 hpage_count = 0;
2743 }
2744
2745 /* CCB structures */
2746 res_info[BNA_RX_RES_MEM_T_CCB].res_type = BNA_RES_T_MEM;
2747 mem_info = &res_info[BNA_RX_RES_MEM_T_CCB].res_u.mem_info;
2748 mem_info->mem_type = BNA_MEM_T_KVA;
2749 mem_info->len = sizeof(struct bna_ccb);
2750 mem_info->num = q_cfg->num_paths;
2751
2752 /* RCB structures */
2753 res_info[BNA_RX_RES_MEM_T_RCB].res_type = BNA_RES_T_MEM;
2754 mem_info = &res_info[BNA_RX_RES_MEM_T_RCB].res_u.mem_info;
2755 mem_info->mem_type = BNA_MEM_T_KVA;
2756 mem_info->len = sizeof(struct bna_rcb);
2757 mem_info->num = BNA_GET_RXQS(q_cfg);
2758
2759 /* Completion QPT */
2760 res_info[BNA_RX_RES_MEM_T_CQPT].res_type = BNA_RES_T_MEM;
2761 mem_info = &res_info[BNA_RX_RES_MEM_T_CQPT].res_u.mem_info;
2762 mem_info->mem_type = BNA_MEM_T_DMA;
2763 mem_info->len = cpage_count * sizeof(struct bna_dma_addr);
2764 mem_info->num = q_cfg->num_paths;
2765
2766 /* Completion s/w QPT */
2767 res_info[BNA_RX_RES_MEM_T_CSWQPT].res_type = BNA_RES_T_MEM;
2768 mem_info = &res_info[BNA_RX_RES_MEM_T_CSWQPT].res_u.mem_info;
2769 mem_info->mem_type = BNA_MEM_T_KVA;
2770 mem_info->len = cpage_count * sizeof(void *);
2771 mem_info->num = q_cfg->num_paths;
2772
2773 /* Completion QPT pages */
2774 res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_type = BNA_RES_T_MEM;
2775 mem_info = &res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info;
2776 mem_info->mem_type = BNA_MEM_T_DMA;
2777 mem_info->len = PAGE_SIZE;
2778 mem_info->num = cpage_count * q_cfg->num_paths;
2779
2780 /* Data QPTs */
2781 res_info[BNA_RX_RES_MEM_T_DQPT].res_type = BNA_RES_T_MEM;
2782 mem_info = &res_info[BNA_RX_RES_MEM_T_DQPT].res_u.mem_info;
2783 mem_info->mem_type = BNA_MEM_T_DMA;
2784 mem_info->len = dpage_count * sizeof(struct bna_dma_addr);
2785 mem_info->num = q_cfg->num_paths;
2786
2787 /* Data s/w QPTs */
2788 res_info[BNA_RX_RES_MEM_T_DSWQPT].res_type = BNA_RES_T_MEM;
2789 mem_info = &res_info[BNA_RX_RES_MEM_T_DSWQPT].res_u.mem_info;
2790 mem_info->mem_type = BNA_MEM_T_KVA;
2791 mem_info->len = dpage_count * sizeof(void *);
2792 mem_info->num = q_cfg->num_paths;
2793
2794 /* Data QPT pages */
2795 res_info[BNA_RX_RES_MEM_T_DPAGE].res_type = BNA_RES_T_MEM;
2796 mem_info = &res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info;
2797 mem_info->mem_type = BNA_MEM_T_DMA;
2798 mem_info->len = PAGE_SIZE;
2799 mem_info->num = dpage_count * q_cfg->num_paths;
2800
2801 /* Hdr QPTs */
2802 res_info[BNA_RX_RES_MEM_T_HQPT].res_type = BNA_RES_T_MEM;
2803 mem_info = &res_info[BNA_RX_RES_MEM_T_HQPT].res_u.mem_info;
2804 mem_info->mem_type = BNA_MEM_T_DMA;
2805 mem_info->len = hpage_count * sizeof(struct bna_dma_addr);
2806 mem_info->num = (hpage_count ? q_cfg->num_paths : 0);
2807
2808 /* Hdr s/w QPTs */
2809 res_info[BNA_RX_RES_MEM_T_HSWQPT].res_type = BNA_RES_T_MEM;
2810 mem_info = &res_info[BNA_RX_RES_MEM_T_HSWQPT].res_u.mem_info;
2811 mem_info->mem_type = BNA_MEM_T_KVA;
2812 mem_info->len = hpage_count * sizeof(void *);
2813 mem_info->num = (hpage_count ? q_cfg->num_paths : 0);
2814
2815 /* Hdr QPT pages */
2816 res_info[BNA_RX_RES_MEM_T_HPAGE].res_type = BNA_RES_T_MEM;
2817 mem_info = &res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info;
2818 mem_info->mem_type = BNA_MEM_T_DMA;
2819 mem_info->len = (hpage_count ? PAGE_SIZE : 0);
2820 mem_info->num = (hpage_count ? (hpage_count * q_cfg->num_paths) : 0);
2821
2822 /* RX Interrupts */
2823 res_info[BNA_RX_RES_T_INTR].res_type = BNA_RES_T_INTR;
2824 res_info[BNA_RX_RES_T_INTR].res_u.intr_info.intr_type = BNA_INTR_T_MSIX;
2825 res_info[BNA_RX_RES_T_INTR].res_u.intr_info.num = q_cfg->num_paths;
2826}
2827
2828struct bna_rx *
2829bna_rx_create(struct bna *bna, struct bnad *bnad,
2830 struct bna_rx_config *rx_cfg,
2831 struct bna_rx_event_cbfn *rx_cbfn,
2832 struct bna_res_info *res_info,
2833 void *priv)
2834{
2835 struct bna_rx_mod *rx_mod = &bna->rx_mod;
2836 struct bna_rx *rx;
2837 struct bna_rxp *rxp;
2838 struct bna_rxq *q0;
2839 struct bna_rxq *q1;
2840 struct bna_intr_info *intr_info;
2841 u32 page_count;
2842 struct bna_mem_descr *ccb_mem;
2843 struct bna_mem_descr *rcb_mem;
2844 struct bna_mem_descr *unmapq_mem;
2845 struct bna_mem_descr *cqpt_mem;
2846 struct bna_mem_descr *cswqpt_mem;
2847 struct bna_mem_descr *cpage_mem;
2848 struct bna_mem_descr *hqpt_mem; /* Header/Small Q qpt */
2849 struct bna_mem_descr *dqpt_mem; /* Data/Large Q qpt */
2850 struct bna_mem_descr *hsqpt_mem; /* s/w qpt for hdr */
2851 struct bna_mem_descr *dsqpt_mem; /* s/w qpt for data */
2852 struct bna_mem_descr *hpage_mem; /* hdr page mem */
2853 struct bna_mem_descr *dpage_mem; /* data page mem */
2854 int i, cpage_idx = 0, dpage_idx = 0, hpage_idx = 0, ret;
2855 int dpage_count, hpage_count, rcb_idx;
2856 struct bna_ib_config ibcfg;
2857 /* Fail if we don't have enough RXPs, RXQs */
2858 if (!_rx_can_satisfy(rx_mod, rx_cfg))
2859 return NULL;
2860
2861 /* Initialize resource pointers */
2862 intr_info = &res_info[BNA_RX_RES_T_INTR].res_u.intr_info;
2863 ccb_mem = &res_info[BNA_RX_RES_MEM_T_CCB].res_u.mem_info.mdl[0];
2864 rcb_mem = &res_info[BNA_RX_RES_MEM_T_RCB].res_u.mem_info.mdl[0];
2865 unmapq_mem = &res_info[BNA_RX_RES_MEM_T_UNMAPQ].res_u.mem_info.mdl[0];
2866 cqpt_mem = &res_info[BNA_RX_RES_MEM_T_CQPT].res_u.mem_info.mdl[0];
2867 cswqpt_mem = &res_info[BNA_RX_RES_MEM_T_CSWQPT].res_u.mem_info.mdl[0];
2868 cpage_mem = &res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info.mdl[0];
2869 hqpt_mem = &res_info[BNA_RX_RES_MEM_T_HQPT].res_u.mem_info.mdl[0];
2870 dqpt_mem = &res_info[BNA_RX_RES_MEM_T_DQPT].res_u.mem_info.mdl[0];
2871 hsqpt_mem = &res_info[BNA_RX_RES_MEM_T_HSWQPT].res_u.mem_info.mdl[0];
2872 dsqpt_mem = &res_info[BNA_RX_RES_MEM_T_DSWQPT].res_u.mem_info.mdl[0];
2873 hpage_mem = &res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info.mdl[0];
2874 dpage_mem = &res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info.mdl[0];
2875
2876 /* Compute q depth & page count */
2877 page_count = res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info.num /
2878 rx_cfg->num_paths;
2879
2880 dpage_count = res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info.num /
2881 rx_cfg->num_paths;
2882
2883 hpage_count = res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info.num /
2884 rx_cfg->num_paths;
2885 /* Get RX pointer */
2886 rx = _get_free_rx(rx_mod);
2887 _rx_init(rx, bna);
2888 rx->priv = priv;
2889 rx->type = rx_cfg->rx_type;
2890
2891 rx->rcb_setup_cbfn = rx_cbfn->rcb_setup_cbfn;
2892 rx->rcb_destroy_cbfn = rx_cbfn->rcb_destroy_cbfn;
2893 rx->ccb_setup_cbfn = rx_cbfn->ccb_setup_cbfn;
2894 rx->ccb_destroy_cbfn = rx_cbfn->ccb_destroy_cbfn;
2895 /* Following callbacks are mandatory */
2896 rx->rx_cleanup_cbfn = rx_cbfn->rx_cleanup_cbfn;
2897 rx->rx_post_cbfn = rx_cbfn->rx_post_cbfn;
2898
2899 if (rx->bna->rx_mod.flags & BNA_RX_MOD_F_PORT_STARTED) {
2900 switch (rx->type) {
2901 case BNA_RX_T_REGULAR:
2902 if (!(rx->bna->rx_mod.flags &
2903 BNA_RX_MOD_F_PORT_LOOPBACK))
2904 rx->rx_flags |= BNA_RX_F_PORT_ENABLED;
2905 break;
2906 case BNA_RX_T_LOOPBACK:
2907 if (rx->bna->rx_mod.flags & BNA_RX_MOD_F_PORT_LOOPBACK)
2908 rx->rx_flags |= BNA_RX_F_PORT_ENABLED;
2909 break;
2910 }
2911 }
2912
2913 for (i = 0, rcb_idx = 0; i < rx_cfg->num_paths; i++) {
2914 rxp = _get_free_rxp(rx_mod);
2915 rxp->type = rx_cfg->rxp_type;
2916 rxp->rx = rx;
2917 rxp->cq.rx = rx;
2918
2919 /* Get required RXQs, and queue them to rx-path */
2920 q0 = _get_free_rxq(rx_mod);
2921 if (BNA_RXP_SINGLE == rx_cfg->rxp_type)
2922 q1 = NULL;
2923 else
2924 q1 = _get_free_rxq(rx_mod);
2925
2926 /* Initialize IB */
2927 if (1 == intr_info->num) {
2928 rxp->cq.ib = bna_ib_get(&bna->ib_mod,
2929 intr_info->intr_type,
2930 intr_info->idl[0].vector);
2931 rxp->vector = intr_info->idl[0].vector;
2932 } else {
2933 rxp->cq.ib = bna_ib_get(&bna->ib_mod,
2934 intr_info->intr_type,
2935 intr_info->idl[i].vector);
2936
2937 /* Map the MSI-x vector used for this RXP */
2938 rxp->vector = intr_info->idl[i].vector;
2939 }
2940
2941 rxp->cq.ib_seg_offset = bna_ib_reserve_idx(rxp->cq.ib);
2942
2943 ibcfg.coalescing_timeo = BFI_RX_COALESCING_TIMEO;
2944 ibcfg.interpkt_count = BFI_RX_INTERPKT_COUNT;
2945 ibcfg.interpkt_timeo = BFI_RX_INTERPKT_TIMEO;
2946 ibcfg.ctrl_flags = BFI_IB_CF_INT_ENABLE;
2947
2948 ret = bna_ib_config(rxp->cq.ib, &ibcfg);
2949
2950 /* Link rxqs to rxp */
2951 _rxp_add_rxqs(rxp, q0, q1);
2952
2953 /* Link rxp to rx */
2954 _rx_add_rxp(rx, rxp);
2955
2956 q0->rx = rx;
2957 q0->rxp = rxp;
2958
2959 /* Initialize RCB for the large / data q */
2960 q0->rcb = (struct bna_rcb *) rcb_mem[rcb_idx].kva;
2961 RXQ_RCB_INIT(q0, rxp, rx_cfg->q_depth, bna, 0,
2962 (void *)unmapq_mem[rcb_idx].kva);
2963 rcb_idx++;
2964 (q0)->rx_packets = (q0)->rx_bytes = 0;
2965 (q0)->rx_packets_with_error = (q0)->rxbuf_alloc_failed = 0;
2966
2967 /* Initialize RXQs */
2968 _rxq_qpt_init(q0, rxp, dpage_count, PAGE_SIZE,
2969 &dqpt_mem[i], &dsqpt_mem[i], &dpage_mem[dpage_idx]);
2970 q0->rcb->page_idx = dpage_idx;
2971 q0->rcb->page_count = dpage_count;
2972 dpage_idx += dpage_count;
2973
2974 /* Call bnad to complete rcb setup */
2975 if (rx->rcb_setup_cbfn)
2976 rx->rcb_setup_cbfn(bnad, q0->rcb);
2977
2978 if (q1) {
2979 q1->rx = rx;
2980 q1->rxp = rxp;
2981
2982 q1->rcb = (struct bna_rcb *) rcb_mem[rcb_idx].kva;
2983 RXQ_RCB_INIT(q1, rxp, rx_cfg->q_depth, bna, 1,
2984 (void *)unmapq_mem[rcb_idx].kva);
2985 rcb_idx++;
2986 (q1)->buffer_size = (rx_cfg)->small_buff_size;
2987 (q1)->rx_packets = (q1)->rx_bytes = 0;
2988 (q1)->rx_packets_with_error =
2989 (q1)->rxbuf_alloc_failed = 0;
2990
2991 _rxq_qpt_init(q1, rxp, hpage_count, PAGE_SIZE,
2992 &hqpt_mem[i], &hsqpt_mem[i],
2993 &hpage_mem[hpage_idx]);
2994 q1->rcb->page_idx = hpage_idx;
2995 q1->rcb->page_count = hpage_count;
2996 hpage_idx += hpage_count;
2997
2998 /* Call bnad to complete rcb setup */
2999 if (rx->rcb_setup_cbfn)
3000 rx->rcb_setup_cbfn(bnad, q1->rcb);
3001 }
3002 /* Setup RXP::CQ */
3003 rxp->cq.ccb = (struct bna_ccb *) ccb_mem[i].kva;
3004 _rxp_cqpt_setup(rxp, page_count, PAGE_SIZE,
3005 &cqpt_mem[i], &cswqpt_mem[i], &cpage_mem[cpage_idx]);
3006 rxp->cq.ccb->page_idx = cpage_idx;
3007 rxp->cq.ccb->page_count = page_count;
3008 cpage_idx += page_count;
3009
3010 rxp->cq.ccb->pkt_rate.small_pkt_cnt = 0;
3011 rxp->cq.ccb->pkt_rate.large_pkt_cnt = 0;
3012
3013 rxp->cq.ccb->producer_index = 0;
3014 rxp->cq.ccb->q_depth = rx_cfg->q_depth +
3015 ((rx_cfg->rxp_type == BNA_RXP_SINGLE) ?
3016 0 : rx_cfg->q_depth);
3017 rxp->cq.ccb->i_dbell = &rxp->cq.ib->door_bell;
3018 rxp->cq.ccb->rcb[0] = q0->rcb;
3019 if (q1)
3020 rxp->cq.ccb->rcb[1] = q1->rcb;
3021 rxp->cq.ccb->cq = &rxp->cq;
3022 rxp->cq.ccb->bnad = bna->bnad;
3023 rxp->cq.ccb->hw_producer_index =
3024 ((volatile u32 *)rxp->cq.ib->ib_seg_host_addr_kva +
3025 (rxp->cq.ib_seg_offset * BFI_IBIDX_SIZE));
3026 *(rxp->cq.ccb->hw_producer_index) = 0;
3027 rxp->cq.ccb->intr_type = intr_info->intr_type;
3028 rxp->cq.ccb->intr_vector = (intr_info->num == 1) ?
3029 intr_info->idl[0].vector :
3030 intr_info->idl[i].vector;
3031 rxp->cq.ccb->rx_coalescing_timeo =
3032 rxp->cq.ib->ib_config.coalescing_timeo;
3033 rxp->cq.ccb->id = i;
3034
3035 /* Call bnad to complete CCB setup */
3036 if (rx->ccb_setup_cbfn)
3037 rx->ccb_setup_cbfn(bnad, rxp->cq.ccb);
3038
3039 } /* for each rx-path */
3040
3041 bna_rxf_init(&rx->rxf, rx, rx_cfg);
3042
3043 bfa_fsm_set_state(rx, bna_rx_sm_stopped);
3044
3045 return rx;
3046}
3047
3048void
3049bna_rx_destroy(struct bna_rx *rx)
3050{
3051 struct bna_rx_mod *rx_mod = &rx->bna->rx_mod;
3052 struct bna_ib_mod *ib_mod = &rx->bna->ib_mod;
3053 struct bna_rxq *q0 = NULL;
3054 struct bna_rxq *q1 = NULL;
3055 struct bna_rxp *rxp;
3056 struct list_head *qe;
3057
3058 bna_rxf_uninit(&rx->rxf);
3059
3060 while (!list_empty(&rx->rxp_q)) {
3061 bfa_q_deq(&rx->rxp_q, &rxp);
3062 GET_RXQS(rxp, q0, q1);
3063 /* Callback to bnad for destroying RCB */
3064 if (rx->rcb_destroy_cbfn)
3065 rx->rcb_destroy_cbfn(rx->bna->bnad, q0->rcb);
3066 q0->rcb = NULL;
3067 q0->rxp = NULL;
3068 q0->rx = NULL;
3069 _put_free_rxq(rx_mod, q0);
3070 if (q1) {
3071 /* Callback to bnad for destroying RCB */
3072 if (rx->rcb_destroy_cbfn)
3073 rx->rcb_destroy_cbfn(rx->bna->bnad, q1->rcb);
3074 q1->rcb = NULL;
3075 q1->rxp = NULL;
3076 q1->rx = NULL;
3077 _put_free_rxq(rx_mod, q1);
3078 }
3079 rxp->rxq.slr.large = NULL;
3080 rxp->rxq.slr.small = NULL;
3081 if (rxp->cq.ib) {
3082 if (rxp->cq.ib_seg_offset != 0xff)
3083 bna_ib_release_idx(rxp->cq.ib,
3084 rxp->cq.ib_seg_offset);
3085 bna_ib_put(ib_mod, rxp->cq.ib);
3086 rxp->cq.ib = NULL;
3087 }
3088 /* Callback to bnad for destroying CCB */
3089 if (rx->ccb_destroy_cbfn)
3090 rx->ccb_destroy_cbfn(rx->bna->bnad, rxp->cq.ccb);
3091 rxp->cq.ccb = NULL;
3092 rxp->rx = NULL;
3093 _put_free_rxp(rx_mod, rxp);
3094 }
3095
3096 list_for_each(qe, &rx_mod->rx_active_q) {
3097 if (qe == &rx->qe) {
3098 list_del(&rx->qe);
3099 bfa_q_qe_init(&rx->qe);
3100 break;
3101 }
3102 }
3103
3104 rx->bna = NULL;
3105 rx->priv = NULL;
3106 _put_free_rx(rx_mod, rx);
3107}
3108
3109void
3110bna_rx_enable(struct bna_rx *rx)
3111{
3112 if (rx->fsm != (bfa_sm_t)bna_rx_sm_stopped)
3113 return;
3114
3115 rx->rx_flags |= BNA_RX_F_ENABLE;
3116 if (rx->rx_flags & BNA_RX_F_PORT_ENABLED)
3117 bfa_fsm_send_event(rx, RX_E_START);
3118}
3119
3120void
3121bna_rx_disable(struct bna_rx *rx, enum bna_cleanup_type type,
3122 void (*cbfn)(void *, struct bna_rx *,
3123 enum bna_cb_status))
3124{
3125 if (type == BNA_SOFT_CLEANUP) {
3126 /* h/w should not be accessed. Treat we're stopped */
3127 (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
3128 } else {
3129 rx->stop_cbfn = cbfn;
3130 rx->stop_cbarg = rx->bna->bnad;
3131
3132 rx->rx_flags &= ~BNA_RX_F_ENABLE;
3133
3134 bfa_fsm_send_event(rx, RX_E_STOP);
3135 }
3136}
3137
3138/**
3139 * TX
3140 */
3141#define call_tx_stop_cbfn(tx, status)\
3142do {\
3143 if ((tx)->stop_cbfn)\
3144 (tx)->stop_cbfn((tx)->stop_cbarg, (tx), status);\
3145 (tx)->stop_cbfn = NULL;\
3146 (tx)->stop_cbarg = NULL;\
3147} while (0)
3148
3149#define call_tx_prio_change_cbfn(tx, status)\
3150do {\
3151 if ((tx)->prio_change_cbfn)\
3152 (tx)->prio_change_cbfn((tx)->bna->bnad, (tx), status);\
3153 (tx)->prio_change_cbfn = NULL;\
3154} while (0)
3155
3156static void bna_tx_mod_cb_tx_stopped(void *tx_mod, struct bna_tx *tx,
3157 enum bna_cb_status status);
3158static void bna_tx_cb_txq_stopped(void *arg, int status);
3159static void bna_tx_cb_stats_cleared(void *arg, int status);
3160static void __bna_tx_stop(struct bna_tx *tx);
3161static void __bna_tx_start(struct bna_tx *tx);
3162static void __bna_txf_stat_clr(struct bna_tx *tx);
3163
3164enum bna_tx_event {
3165 TX_E_START = 1,
3166 TX_E_STOP = 2,
3167 TX_E_FAIL = 3,
3168 TX_E_TXQ_STOPPED = 4,
3169 TX_E_PRIO_CHANGE = 5,
3170 TX_E_STAT_CLEARED = 6,
3171};
3172
3173enum bna_tx_state {
3174 BNA_TX_STOPPED = 1,
3175 BNA_TX_STARTED = 2,
3176 BNA_TX_TXQ_STOP_WAIT = 3,
3177 BNA_TX_PRIO_STOP_WAIT = 4,
3178 BNA_TX_STAT_CLR_WAIT = 5,
3179};
3180
3181bfa_fsm_state_decl(bna_tx, stopped, struct bna_tx,
3182 enum bna_tx_event);
3183bfa_fsm_state_decl(bna_tx, started, struct bna_tx,
3184 enum bna_tx_event);
3185bfa_fsm_state_decl(bna_tx, txq_stop_wait, struct bna_tx,
3186 enum bna_tx_event);
3187bfa_fsm_state_decl(bna_tx, prio_stop_wait, struct bna_tx,
3188 enum bna_tx_event);
3189bfa_fsm_state_decl(bna_tx, stat_clr_wait, struct bna_tx,
3190 enum bna_tx_event);
3191
3192static struct bfa_sm_table tx_sm_table[] = {
3193 {BFA_SM(bna_tx_sm_stopped), BNA_TX_STOPPED},
3194 {BFA_SM(bna_tx_sm_started), BNA_TX_STARTED},
3195 {BFA_SM(bna_tx_sm_txq_stop_wait), BNA_TX_TXQ_STOP_WAIT},
3196 {BFA_SM(bna_tx_sm_prio_stop_wait), BNA_TX_PRIO_STOP_WAIT},
3197 {BFA_SM(bna_tx_sm_stat_clr_wait), BNA_TX_STAT_CLR_WAIT},
3198};
3199
3200static void
3201bna_tx_sm_stopped_entry(struct bna_tx *tx)
3202{
3203 struct bna_txq *txq;
3204 struct list_head *qe;
3205
3206 list_for_each(qe, &tx->txq_q) {
3207 txq = (struct bna_txq *)qe;
3208 (tx->tx_cleanup_cbfn)(tx->bna->bnad, txq->tcb);
3209 }
3210
3211 call_tx_stop_cbfn(tx, BNA_CB_SUCCESS);
3212}
3213
3214static void
3215bna_tx_sm_stopped(struct bna_tx *tx, enum bna_tx_event event)
3216{
3217 switch (event) {
3218 case TX_E_START:
3219 bfa_fsm_set_state(tx, bna_tx_sm_started);
3220 break;
3221
3222 case TX_E_STOP:
3223 bfa_fsm_set_state(tx, bna_tx_sm_stopped);
3224 break;
3225
3226 case TX_E_FAIL:
3227 /* No-op */
3228 break;
3229
3230 case TX_E_PRIO_CHANGE:
3231 call_tx_prio_change_cbfn(tx, BNA_CB_SUCCESS);
3232 break;
3233
3234 case TX_E_TXQ_STOPPED:
3235 /**
3236 * This event is received due to flushing of mbox when
3237 * device fails
3238 */
3239 /* No-op */
3240 break;
3241
3242 default:
3243 bfa_sm_fault(tx->bna, event);
3244 }
3245}
3246
3247static void
3248bna_tx_sm_started_entry(struct bna_tx *tx)
3249{
3250 struct bna_txq *txq;
3251 struct list_head *qe;
3252
3253 __bna_tx_start(tx);
3254
3255 /* Start IB */
3256 list_for_each(qe, &tx->txq_q) {
3257 txq = (struct bna_txq *)qe;
3258 bna_ib_ack(&txq->ib->door_bell, 0);
3259 }
3260}
3261
3262static void
3263bna_tx_sm_started(struct bna_tx *tx, enum bna_tx_event event)
3264{
3265 struct bna_txq *txq;
3266 struct list_head *qe;
3267
3268 switch (event) {
3269 case TX_E_STOP:
3270 bfa_fsm_set_state(tx, bna_tx_sm_txq_stop_wait);
3271 __bna_tx_stop(tx);
3272 break;
3273
3274 case TX_E_FAIL:
3275 list_for_each(qe, &tx->txq_q) {
3276 txq = (struct bna_txq *)qe;
3277 bna_ib_fail(txq->ib);
3278 (tx->tx_stall_cbfn)(tx->bna->bnad, txq->tcb);
3279 }
3280 bfa_fsm_set_state(tx, bna_tx_sm_stopped);
3281 break;
3282
3283 case TX_E_PRIO_CHANGE:
3284 bfa_fsm_set_state(tx, bna_tx_sm_prio_stop_wait);
3285 break;
3286
3287 default:
3288 bfa_sm_fault(tx->bna, event);
3289 }
3290}
3291
3292static void
3293bna_tx_sm_txq_stop_wait_entry(struct bna_tx *tx)
3294{
3295}
3296
3297static void
3298bna_tx_sm_txq_stop_wait(struct bna_tx *tx, enum bna_tx_event event)
3299{
3300 struct bna_txq *txq;
3301 struct list_head *qe;
3302
3303 switch (event) {
3304 case TX_E_FAIL:
3305 bfa_fsm_set_state(tx, bna_tx_sm_stopped);
3306 break;
3307
3308 case TX_E_TXQ_STOPPED:
3309 list_for_each(qe, &tx->txq_q) {
3310 txq = (struct bna_txq *)qe;
3311 bna_ib_stop(txq->ib);
3312 }
3313 bfa_fsm_set_state(tx, bna_tx_sm_stat_clr_wait);
3314 break;
3315
3316 case TX_E_PRIO_CHANGE:
3317 /* No-op */
3318 break;
3319
3320 default:
3321 bfa_sm_fault(tx->bna, event);
3322 }
3323}
3324
3325static void
3326bna_tx_sm_prio_stop_wait_entry(struct bna_tx *tx)
3327{
3328 __bna_tx_stop(tx);
3329}
3330
3331static void
3332bna_tx_sm_prio_stop_wait(struct bna_tx *tx, enum bna_tx_event event)
3333{
3334 struct bna_txq *txq;
3335 struct list_head *qe;
3336
3337 switch (event) {
3338 case TX_E_STOP:
3339 bfa_fsm_set_state(tx, bna_tx_sm_txq_stop_wait);
3340 break;
3341
3342 case TX_E_FAIL:
3343 call_tx_prio_change_cbfn(tx, BNA_CB_FAIL);
3344 bfa_fsm_set_state(tx, bna_tx_sm_stopped);
3345 break;
3346
3347 case TX_E_TXQ_STOPPED:
3348 list_for_each(qe, &tx->txq_q) {
3349 txq = (struct bna_txq *)qe;
3350 bna_ib_stop(txq->ib);
3351 (tx->tx_cleanup_cbfn)(tx->bna->bnad, txq->tcb);
3352 }
3353 call_tx_prio_change_cbfn(tx, BNA_CB_SUCCESS);
3354 bfa_fsm_set_state(tx, bna_tx_sm_started);
3355 break;
3356
3357 case TX_E_PRIO_CHANGE:
3358 /* No-op */
3359 break;
3360
3361 default:
3362 bfa_sm_fault(tx->bna, event);
3363 }
3364}
3365
3366static void
3367bna_tx_sm_stat_clr_wait_entry(struct bna_tx *tx)
3368{
3369 __bna_txf_stat_clr(tx);
3370}
3371
3372static void
3373bna_tx_sm_stat_clr_wait(struct bna_tx *tx, enum bna_tx_event event)
3374{
3375 switch (event) {
3376 case TX_E_FAIL:
3377 case TX_E_STAT_CLEARED:
3378 bfa_fsm_set_state(tx, bna_tx_sm_stopped);
3379 break;
3380
3381 default:
3382 bfa_sm_fault(tx->bna, event);
3383 }
3384}
3385
3386static void
3387__bna_txq_start(struct bna_tx *tx, struct bna_txq *txq)
3388{
3389 struct bna_rxtx_q_mem *q_mem;
3390 struct bna_txq_mem txq_cfg;
3391 struct bna_txq_mem *txq_mem;
3392 struct bna_dma_addr cur_q_addr;
3393 u32 pg_num;
3394 void __iomem *base_addr;
3395 unsigned long off;
3396
3397 /* Fill out structure, to be subsequently written to hardware */
3398 txq_cfg.pg_tbl_addr_lo = txq->qpt.hw_qpt_ptr.lsb;
3399 txq_cfg.pg_tbl_addr_hi = txq->qpt.hw_qpt_ptr.msb;
3400 cur_q_addr = *((struct bna_dma_addr *)(txq->qpt.kv_qpt_ptr));
3401 txq_cfg.cur_q_entry_lo = cur_q_addr.lsb;
3402 txq_cfg.cur_q_entry_hi = cur_q_addr.msb;
3403
3404 txq_cfg.pg_cnt_n_prd_ptr = (txq->qpt.page_count << 16) | 0x0;
3405
3406 txq_cfg.entry_n_pg_size = ((u32)(BFI_TXQ_WI_SIZE >> 2) << 16) |
3407 (txq->qpt.page_size >> 2);
3408 txq_cfg.int_blk_n_cns_ptr = ((((u32)txq->ib_seg_offset) << 24) |
3409 ((u32)(txq->ib->ib_id & 0xff) << 16) | 0x0);
3410
3411 txq_cfg.cns_ptr2_n_q_state = BNA_Q_IDLE_STATE;
3412 txq_cfg.nxt_qid_n_fid_n_pri = (((tx->txf.txf_id & 0x3f) << 3) |
3413 (txq->priority & 0x3));
3414 txq_cfg.wvc_n_cquota_n_rquota =
3415 ((((u32)BFI_TX_MAX_WRR_QUOTA & 0xfff) << 12) |
3416 (BFI_TX_MAX_WRR_QUOTA & 0xfff));
3417
3418 /* Setup the page and write to H/W */
3419
3420 pg_num = BNA_GET_PAGE_NUM(HQM0_BLK_PG_NUM + tx->bna->port_num,
3421 HQM_RXTX_Q_RAM_BASE_OFFSET);
3422 writel(pg_num, tx->bna->regs.page_addr);
3423
3424 base_addr = BNA_GET_MEM_BASE_ADDR(tx->bna->pcidev.pci_bar_kva,
3425 HQM_RXTX_Q_RAM_BASE_OFFSET);
3426 q_mem = (struct bna_rxtx_q_mem *)0;
3427 txq_mem = &q_mem[txq->txq_id].txq;
3428
3429 /*
3430 * The following 4 lines, is a hack b'cos the H/W needs to read
3431 * these DMA addresses as little endian
3432 */
3433
3434 off = (unsigned long)&txq_mem->pg_tbl_addr_lo;
3435 writel(htonl(txq_cfg.pg_tbl_addr_lo), base_addr + off);
3436
3437 off = (unsigned long)&txq_mem->pg_tbl_addr_hi;
3438 writel(htonl(txq_cfg.pg_tbl_addr_hi), base_addr + off);
3439
3440 off = (unsigned long)&txq_mem->cur_q_entry_lo;
3441 writel(htonl(txq_cfg.cur_q_entry_lo), base_addr + off);
3442
3443 off = (unsigned long)&txq_mem->cur_q_entry_hi;
3444 writel(htonl(txq_cfg.cur_q_entry_hi), base_addr + off);
3445
3446 off = (unsigned long)&txq_mem->pg_cnt_n_prd_ptr;
3447 writel(txq_cfg.pg_cnt_n_prd_ptr, base_addr + off);
3448
3449 off = (unsigned long)&txq_mem->entry_n_pg_size;
3450 writel(txq_cfg.entry_n_pg_size, base_addr + off);
3451
3452 off = (unsigned long)&txq_mem->int_blk_n_cns_ptr;
3453 writel(txq_cfg.int_blk_n_cns_ptr, base_addr + off);
3454
3455 off = (unsigned long)&txq_mem->cns_ptr2_n_q_state;
3456 writel(txq_cfg.cns_ptr2_n_q_state, base_addr + off);
3457
3458 off = (unsigned long)&txq_mem->nxt_qid_n_fid_n_pri;
3459 writel(txq_cfg.nxt_qid_n_fid_n_pri, base_addr + off);
3460
3461 off = (unsigned long)&txq_mem->wvc_n_cquota_n_rquota;
3462 writel(txq_cfg.wvc_n_cquota_n_rquota, base_addr + off);
3463
3464 txq->tcb->producer_index = 0;
3465 txq->tcb->consumer_index = 0;
3466 *(txq->tcb->hw_consumer_index) = 0;
3467
3468}
3469
3470static void
3471__bna_txq_stop(struct bna_tx *tx, struct bna_txq *txq)
3472{
3473 struct bfi_ll_q_stop_req ll_req;
3474 u32 bit_mask[2] = {0, 0};
3475 if (txq->txq_id < 32)
3476 bit_mask[0] = (u32)1 << txq->txq_id;
3477 else
3478 bit_mask[1] = (u32)1 << (txq->txq_id - 32);
3479
3480 memset(&ll_req, 0, sizeof(ll_req));
3481 ll_req.mh.msg_class = BFI_MC_LL;
3482 ll_req.mh.msg_id = BFI_LL_H2I_TXQ_STOP_REQ;
3483 ll_req.mh.mtag.h2i.lpu_id = 0;
3484 ll_req.q_id_mask[0] = htonl(bit_mask[0]);
3485 ll_req.q_id_mask[1] = htonl(bit_mask[1]);
3486
3487 bna_mbox_qe_fill(&tx->mbox_qe, &ll_req, sizeof(ll_req),
3488 bna_tx_cb_txq_stopped, tx);
3489
3490 bna_mbox_send(tx->bna, &tx->mbox_qe);
3491}
3492
3493static void
3494__bna_txf_start(struct bna_tx *tx)
3495{
3496 struct bna_tx_fndb_ram *tx_fndb;
3497 struct bna_txf *txf = &tx->txf;
3498 void __iomem *base_addr;
3499 unsigned long off;
3500
3501 writel(BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM +
3502 (tx->bna->port_num * 2), TX_FNDB_RAM_BASE_OFFSET),
3503 tx->bna->regs.page_addr);
3504
3505 base_addr = BNA_GET_MEM_BASE_ADDR(tx->bna->pcidev.pci_bar_kva,
3506 TX_FNDB_RAM_BASE_OFFSET);
3507
3508 tx_fndb = (struct bna_tx_fndb_ram *)0;
3509 off = (unsigned long)&tx_fndb[txf->txf_id].vlan_n_ctrl_flags;
3510
3511 writel(((u32)txf->vlan << 16) | txf->ctrl_flags,
3512 base_addr + off);
3513
3514 if (tx->txf.txf_id < 32)
3515 tx->bna->tx_mod.txf_bmap[0] |= ((u32)1 << tx->txf.txf_id);
3516 else
3517 tx->bna->tx_mod.txf_bmap[1] |= ((u32)
3518 1 << (tx->txf.txf_id - 32));
3519}
3520
3521static void
3522__bna_txf_stop(struct bna_tx *tx)
3523{
3524 struct bna_tx_fndb_ram *tx_fndb;
3525 u32 page_num;
3526 u32 ctl_flags;
3527 struct bna_txf *txf = &tx->txf;
3528 void __iomem *base_addr;
3529 unsigned long off;
3530
3531 /* retrieve the running txf_flags & turn off enable bit */
3532 page_num = BNA_GET_PAGE_NUM(LUT0_MEM_BLK_BASE_PG_NUM +
3533 (tx->bna->port_num * 2), TX_FNDB_RAM_BASE_OFFSET);
3534 writel(page_num, tx->bna->regs.page_addr);
3535
3536 base_addr = BNA_GET_MEM_BASE_ADDR(tx->bna->pcidev.pci_bar_kva,
3537 TX_FNDB_RAM_BASE_OFFSET);
3538 tx_fndb = (struct bna_tx_fndb_ram *)0;
3539 off = (unsigned long)&tx_fndb[txf->txf_id].vlan_n_ctrl_flags;
3540
3541 ctl_flags = readl(base_addr + off);
3542 ctl_flags &= ~BFI_TXF_CF_ENABLE;
3543
3544 writel(ctl_flags, base_addr + off);
3545
3546 if (tx->txf.txf_id < 32)
3547 tx->bna->tx_mod.txf_bmap[0] &= ~((u32)1 << tx->txf.txf_id);
3548 else
3549 tx->bna->tx_mod.txf_bmap[0] &= ~((u32)
3550 1 << (tx->txf.txf_id - 32));
3551}
3552
3553static void
3554__bna_txf_stat_clr(struct bna_tx *tx)
3555{
3556 struct bfi_ll_stats_req ll_req;
3557 u32 txf_bmap[2] = {0, 0};
3558 if (tx->txf.txf_id < 32)
3559 txf_bmap[0] = ((u32)1 << tx->txf.txf_id);
3560 else
3561 txf_bmap[1] = ((u32)1 << (tx->txf.txf_id - 32));
3562 bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_STATS_CLEAR_REQ, 0);
3563 ll_req.stats_mask = 0;
3564 ll_req.rxf_id_mask[0] = 0;
3565 ll_req.rxf_id_mask[1] = 0;
3566 ll_req.txf_id_mask[0] = htonl(txf_bmap[0]);
3567 ll_req.txf_id_mask[1] = htonl(txf_bmap[1]);
3568
3569 bna_mbox_qe_fill(&tx->mbox_qe, &ll_req, sizeof(ll_req),
3570 bna_tx_cb_stats_cleared, tx);
3571 bna_mbox_send(tx->bna, &tx->mbox_qe);
3572}
3573
3574static void
3575__bna_tx_start(struct bna_tx *tx)
3576{
3577 struct bna_txq *txq;
3578 struct list_head *qe;
3579
3580 list_for_each(qe, &tx->txq_q) {
3581 txq = (struct bna_txq *)qe;
3582 bna_ib_start(txq->ib);
3583 __bna_txq_start(tx, txq);
3584 }
3585
3586 __bna_txf_start(tx);
3587
3588 list_for_each(qe, &tx->txq_q) {
3589 txq = (struct bna_txq *)qe;
3590 txq->tcb->priority = txq->priority;
3591 (tx->tx_resume_cbfn)(tx->bna->bnad, txq->tcb);
3592 }
3593}
3594
3595static void
3596__bna_tx_stop(struct bna_tx *tx)
3597{
3598 struct bna_txq *txq;
3599 struct list_head *qe;
3600
3601 list_for_each(qe, &tx->txq_q) {
3602 txq = (struct bna_txq *)qe;
3603 (tx->tx_stall_cbfn)(tx->bna->bnad, txq->tcb);
3604 }
3605
3606 __bna_txf_stop(tx);
3607
3608 list_for_each(qe, &tx->txq_q) {
3609 txq = (struct bna_txq *)qe;
3610 bfa_wc_up(&tx->txq_stop_wc);
3611 }
3612
3613 list_for_each(qe, &tx->txq_q) {
3614 txq = (struct bna_txq *)qe;
3615 __bna_txq_stop(tx, txq);
3616 }
3617}
3618
3619static void
3620bna_txq_qpt_setup(struct bna_txq *txq, int page_count, int page_size,
3621 struct bna_mem_descr *qpt_mem,
3622 struct bna_mem_descr *swqpt_mem,
3623 struct bna_mem_descr *page_mem)
3624{
3625 int i;
3626
3627 txq->qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb;
3628 txq->qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb;
3629 txq->qpt.kv_qpt_ptr = qpt_mem->kva;
3630 txq->qpt.page_count = page_count;
3631 txq->qpt.page_size = page_size;
3632
3633 txq->tcb->sw_qpt = (void **) swqpt_mem->kva;
3634
3635 for (i = 0; i < page_count; i++) {
3636 txq->tcb->sw_qpt[i] = page_mem[i].kva;
3637
3638 ((struct bna_dma_addr *)txq->qpt.kv_qpt_ptr)[i].lsb =
3639 page_mem[i].dma.lsb;
3640 ((struct bna_dma_addr *)txq->qpt.kv_qpt_ptr)[i].msb =
3641 page_mem[i].dma.msb;
3642
3643 }
3644}
3645
3646static void
3647bna_tx_free(struct bna_tx *tx)
3648{
3649 struct bna_tx_mod *tx_mod = &tx->bna->tx_mod;
3650 struct bna_txq *txq;
3651 struct bna_ib_mod *ib_mod = &tx->bna->ib_mod;
3652 struct list_head *qe;
3653
3654 while (!list_empty(&tx->txq_q)) {
3655 bfa_q_deq(&tx->txq_q, &txq);
3656 bfa_q_qe_init(&txq->qe);
3657 if (txq->ib) {
3658 if (txq->ib_seg_offset != -1)
3659 bna_ib_release_idx(txq->ib,
3660 txq->ib_seg_offset);
3661 bna_ib_put(ib_mod, txq->ib);
3662 txq->ib = NULL;
3663 }
3664 txq->tcb = NULL;
3665 txq->tx = NULL;
3666 list_add_tail(&txq->qe, &tx_mod->txq_free_q);
3667 }
3668
3669 list_for_each(qe, &tx_mod->tx_active_q) {
3670 if (qe == &tx->qe) {
3671 list_del(&tx->qe);
3672 bfa_q_qe_init(&tx->qe);
3673 break;
3674 }
3675 }
3676
3677 tx->bna = NULL;
3678 tx->priv = NULL;
3679 list_add_tail(&tx->qe, &tx_mod->tx_free_q);
3680}
3681
3682static void
3683bna_tx_cb_txq_stopped(void *arg, int status)
3684{
3685 struct bna_tx *tx = (struct bna_tx *)arg;
3686
3687 bfa_q_qe_init(&tx->mbox_qe.qe);
3688 bfa_wc_down(&tx->txq_stop_wc);
3689}
3690
3691static void
3692bna_tx_cb_txq_stopped_all(void *arg)
3693{
3694 struct bna_tx *tx = (struct bna_tx *)arg;
3695
3696 bfa_fsm_send_event(tx, TX_E_TXQ_STOPPED);
3697}
3698
3699static void
3700bna_tx_cb_stats_cleared(void *arg, int status)
3701{
3702 struct bna_tx *tx = (struct bna_tx *)arg;
3703
3704 bfa_q_qe_init(&tx->mbox_qe.qe);
3705
3706 bfa_fsm_send_event(tx, TX_E_STAT_CLEARED);
3707}
3708
3709static void
3710bna_tx_start(struct bna_tx *tx)
3711{
3712 tx->flags |= BNA_TX_F_PORT_STARTED;
3713 if (tx->flags & BNA_TX_F_ENABLED)
3714 bfa_fsm_send_event(tx, TX_E_START);
3715}
3716
3717static void
3718bna_tx_stop(struct bna_tx *tx)
3719{
3720 tx->stop_cbfn = bna_tx_mod_cb_tx_stopped;
3721 tx->stop_cbarg = &tx->bna->tx_mod;
3722
3723 tx->flags &= ~BNA_TX_F_PORT_STARTED;
3724 bfa_fsm_send_event(tx, TX_E_STOP);
3725}
3726
3727static void
3728bna_tx_fail(struct bna_tx *tx)
3729{
3730 tx->flags &= ~BNA_TX_F_PORT_STARTED;
3731 bfa_fsm_send_event(tx, TX_E_FAIL);
3732}
3733
3734void
3735bna_tx_prio_changed(struct bna_tx *tx, int prio)
3736{
3737 struct bna_txq *txq;
3738 struct list_head *qe;
3739
3740 list_for_each(qe, &tx->txq_q) {
3741 txq = (struct bna_txq *)qe;
3742 txq->priority = prio;
3743 }
3744
3745 bfa_fsm_send_event(tx, TX_E_PRIO_CHANGE);
3746}
3747
3748static void
3749bna_tx_cee_link_status(struct bna_tx *tx, int cee_link)
3750{
3751 if (cee_link)
3752 tx->flags |= BNA_TX_F_PRIO_LOCK;
3753 else
3754 tx->flags &= ~BNA_TX_F_PRIO_LOCK;
3755}
3756
3757static void
3758bna_tx_mod_cb_tx_stopped(void *arg, struct bna_tx *tx,
3759 enum bna_cb_status status)
3760{
3761 struct bna_tx_mod *tx_mod = (struct bna_tx_mod *)arg;
3762
3763 bfa_wc_down(&tx_mod->tx_stop_wc);
3764}
3765
3766static void
3767bna_tx_mod_cb_tx_stopped_all(void *arg)
3768{
3769 struct bna_tx_mod *tx_mod = (struct bna_tx_mod *)arg;
3770
3771 if (tx_mod->stop_cbfn)
3772 tx_mod->stop_cbfn(&tx_mod->bna->port, BNA_CB_SUCCESS);
3773 tx_mod->stop_cbfn = NULL;
3774}
3775
3776void
3777bna_tx_res_req(int num_txq, int txq_depth, struct bna_res_info *res_info)
3778{
3779 u32 q_size;
3780 u32 page_count;
3781 struct bna_mem_info *mem_info;
3782
3783 res_info[BNA_TX_RES_MEM_T_TCB].res_type = BNA_RES_T_MEM;
3784 mem_info = &res_info[BNA_TX_RES_MEM_T_TCB].res_u.mem_info;
3785 mem_info->mem_type = BNA_MEM_T_KVA;
3786 mem_info->len = sizeof(struct bna_tcb);
3787 mem_info->num = num_txq;
3788
3789 q_size = txq_depth * BFI_TXQ_WI_SIZE;
3790 q_size = ALIGN(q_size, PAGE_SIZE);
3791 page_count = q_size >> PAGE_SHIFT;
3792
3793 res_info[BNA_TX_RES_MEM_T_QPT].res_type = BNA_RES_T_MEM;
3794 mem_info = &res_info[BNA_TX_RES_MEM_T_QPT].res_u.mem_info;
3795 mem_info->mem_type = BNA_MEM_T_DMA;
3796 mem_info->len = page_count * sizeof(struct bna_dma_addr);
3797 mem_info->num = num_txq;
3798
3799 res_info[BNA_TX_RES_MEM_T_SWQPT].res_type = BNA_RES_T_MEM;
3800 mem_info = &res_info[BNA_TX_RES_MEM_T_SWQPT].res_u.mem_info;
3801 mem_info->mem_type = BNA_MEM_T_KVA;
3802 mem_info->len = page_count * sizeof(void *);
3803 mem_info->num = num_txq;
3804
3805 res_info[BNA_TX_RES_MEM_T_PAGE].res_type = BNA_RES_T_MEM;
3806 mem_info = &res_info[BNA_TX_RES_MEM_T_PAGE].res_u.mem_info;
3807 mem_info->mem_type = BNA_MEM_T_DMA;
3808 mem_info->len = PAGE_SIZE;
3809 mem_info->num = num_txq * page_count;
3810
3811 res_info[BNA_TX_RES_INTR_T_TXCMPL].res_type = BNA_RES_T_INTR;
3812 res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info.intr_type =
3813 BNA_INTR_T_MSIX;
3814 res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info.num = num_txq;
3815}
3816
3817struct bna_tx *
3818bna_tx_create(struct bna *bna, struct bnad *bnad,
3819 struct bna_tx_config *tx_cfg,
3820 struct bna_tx_event_cbfn *tx_cbfn,
3821 struct bna_res_info *res_info, void *priv)
3822{
3823 struct bna_intr_info *intr_info;
3824 struct bna_tx_mod *tx_mod = &bna->tx_mod;
3825 struct bna_tx *tx;
3826 struct bna_txq *txq;
3827 struct list_head *qe;
3828 struct bna_ib_mod *ib_mod = &bna->ib_mod;
3829 struct bna_doorbell_qset *qset;
3830 struct bna_ib_config ib_config;
3831 int page_count;
3832 int page_size;
3833 int page_idx;
3834 int i;
3835 unsigned long off;
3836
3837 intr_info = &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info;
3838 page_count = (res_info[BNA_TX_RES_MEM_T_PAGE].res_u.mem_info.num) /
3839 tx_cfg->num_txq;
3840 page_size = res_info[BNA_TX_RES_MEM_T_PAGE].res_u.mem_info.len;
3841
3842 /**
3843 * Get resources
3844 */
3845
3846 if ((intr_info->num != 1) && (intr_info->num != tx_cfg->num_txq))
3847 return NULL;
3848
3849 /* Tx */
3850
3851 if (list_empty(&tx_mod->tx_free_q))
3852 return NULL;
3853 bfa_q_deq(&tx_mod->tx_free_q, &tx);
3854 bfa_q_qe_init(&tx->qe);
3855
3856 /* TxQs */
3857
3858 INIT_LIST_HEAD(&tx->txq_q);
3859 for (i = 0; i < tx_cfg->num_txq; i++) {
3860 if (list_empty(&tx_mod->txq_free_q))
3861 goto err_return;
3862
3863 bfa_q_deq(&tx_mod->txq_free_q, &txq);
3864 bfa_q_qe_init(&txq->qe);
3865 list_add_tail(&txq->qe, &tx->txq_q);
3866 txq->ib = NULL;
3867 txq->ib_seg_offset = -1;
3868 txq->tx = tx;
3869 }
3870
3871 /* IBs */
3872 i = 0;
3873 list_for_each(qe, &tx->txq_q) {
3874 txq = (struct bna_txq *)qe;
3875
3876 if (intr_info->num == 1)
3877 txq->ib = bna_ib_get(ib_mod, intr_info->intr_type,
3878 intr_info->idl[0].vector);
3879 else
3880 txq->ib = bna_ib_get(ib_mod, intr_info->intr_type,
3881 intr_info->idl[i].vector);
3882
3883 if (txq->ib == NULL)
3884 goto err_return;
3885
3886 txq->ib_seg_offset = bna_ib_reserve_idx(txq->ib);
3887 if (txq->ib_seg_offset == -1)
3888 goto err_return;
3889
3890 i++;
3891 }
3892
3893 /*
3894 * Initialize
3895 */
3896
3897 /* Tx */
3898
3899 tx->tcb_setup_cbfn = tx_cbfn->tcb_setup_cbfn;
3900 tx->tcb_destroy_cbfn = tx_cbfn->tcb_destroy_cbfn;
3901 /* Following callbacks are mandatory */
3902 tx->tx_stall_cbfn = tx_cbfn->tx_stall_cbfn;
3903 tx->tx_resume_cbfn = tx_cbfn->tx_resume_cbfn;
3904 tx->tx_cleanup_cbfn = tx_cbfn->tx_cleanup_cbfn;
3905
3906 list_add_tail(&tx->qe, &tx_mod->tx_active_q);
3907 tx->bna = bna;
3908 tx->priv = priv;
3909 tx->txq_stop_wc.wc_resume = bna_tx_cb_txq_stopped_all;
3910 tx->txq_stop_wc.wc_cbarg = tx;
3911 tx->txq_stop_wc.wc_count = 0;
3912
3913 tx->type = tx_cfg->tx_type;
3914
3915 tx->flags = 0;
3916 if (tx->bna->tx_mod.flags & BNA_TX_MOD_F_PORT_STARTED) {
3917 switch (tx->type) {
3918 case BNA_TX_T_REGULAR:
3919 if (!(tx->bna->tx_mod.flags &
3920 BNA_TX_MOD_F_PORT_LOOPBACK))
3921 tx->flags |= BNA_TX_F_PORT_STARTED;
3922 break;
3923 case BNA_TX_T_LOOPBACK:
3924 if (tx->bna->tx_mod.flags & BNA_TX_MOD_F_PORT_LOOPBACK)
3925 tx->flags |= BNA_TX_F_PORT_STARTED;
3926 break;
3927 }
3928 }
3929 if (tx->bna->tx_mod.cee_link)
3930 tx->flags |= BNA_TX_F_PRIO_LOCK;
3931
3932 /* TxQ */
3933
3934 i = 0;
3935 page_idx = 0;
3936 list_for_each(qe, &tx->txq_q) {
3937 txq = (struct bna_txq *)qe;
3938 txq->priority = tx_mod->priority;
3939 txq->tcb = (struct bna_tcb *)
3940 res_info[BNA_TX_RES_MEM_T_TCB].res_u.mem_info.mdl[i].kva;
3941 txq->tx_packets = 0;
3942 txq->tx_bytes = 0;
3943
3944 /* IB */
3945
3946 ib_config.coalescing_timeo = BFI_TX_COALESCING_TIMEO;
3947 ib_config.interpkt_timeo = 0; /* Not used */
3948 ib_config.interpkt_count = BFI_TX_INTERPKT_COUNT;
3949 ib_config.ctrl_flags = (BFI_IB_CF_INTER_PKT_DMA |
3950 BFI_IB_CF_INT_ENABLE |
3951 BFI_IB_CF_COALESCING_MODE);
3952 bna_ib_config(txq->ib, &ib_config);
3953
3954 /* TCB */
3955
3956 txq->tcb->producer_index = 0;
3957 txq->tcb->consumer_index = 0;
3958 txq->tcb->hw_consumer_index = (volatile u32 *)
3959 ((volatile u8 *)txq->ib->ib_seg_host_addr_kva +
3960 (txq->ib_seg_offset * BFI_IBIDX_SIZE));
3961 *(txq->tcb->hw_consumer_index) = 0;
3962 txq->tcb->q_depth = tx_cfg->txq_depth;
3963 txq->tcb->unmap_q = (void *)
3964 res_info[BNA_TX_RES_MEM_T_UNMAPQ].res_u.mem_info.mdl[i].kva;
3965 qset = (struct bna_doorbell_qset *)0;
3966 off = (unsigned long)&qset[txq->txq_id].txq[0];
3967 txq->tcb->q_dbell = off +
3968 BNA_GET_DOORBELL_BASE_ADDR(bna->pcidev.pci_bar_kva);
3969 txq->tcb->i_dbell = &txq->ib->door_bell;
3970 txq->tcb->intr_type = intr_info->intr_type;
3971 txq->tcb->intr_vector = (intr_info->num == 1) ?
3972 intr_info->idl[0].vector :
3973 intr_info->idl[i].vector;
3974 txq->tcb->txq = txq;
3975 txq->tcb->bnad = bnad;
3976 txq->tcb->id = i;
3977
3978 /* QPT, SWQPT, Pages */
3979 bna_txq_qpt_setup(txq, page_count, page_size,
3980 &res_info[BNA_TX_RES_MEM_T_QPT].res_u.mem_info.mdl[i],
3981 &res_info[BNA_TX_RES_MEM_T_SWQPT].res_u.mem_info.mdl[i],
3982 &res_info[BNA_TX_RES_MEM_T_PAGE].
3983 res_u.mem_info.mdl[page_idx]);
3984 txq->tcb->page_idx = page_idx;
3985 txq->tcb->page_count = page_count;
3986 page_idx += page_count;
3987
3988 /* Callback to bnad for setting up TCB */
3989 if (tx->tcb_setup_cbfn)
3990 (tx->tcb_setup_cbfn)(bna->bnad, txq->tcb);
3991
3992 i++;
3993 }
3994
3995 /* TxF */
3996
3997 tx->txf.ctrl_flags = BFI_TXF_CF_ENABLE | BFI_TXF_CF_VLAN_WI_BASED;
3998 tx->txf.vlan = 0;
3999
4000 /* Mbox element */
4001 bfa_q_qe_init(&tx->mbox_qe.qe);
4002
4003 bfa_fsm_set_state(tx, bna_tx_sm_stopped);
4004
4005 return tx;
4006
4007err_return:
4008 bna_tx_free(tx);
4009 return NULL;
4010}
4011
4012void
4013bna_tx_destroy(struct bna_tx *tx)
4014{
4015 /* Callback to bnad for destroying TCB */
4016 if (tx->tcb_destroy_cbfn) {
4017 struct bna_txq *txq;
4018 struct list_head *qe;
4019
4020 list_for_each(qe, &tx->txq_q) {
4021 txq = (struct bna_txq *)qe;
4022 (tx->tcb_destroy_cbfn)(tx->bna->bnad, txq->tcb);
4023 }
4024 }
4025
4026 bna_tx_free(tx);
4027}
4028
4029void
4030bna_tx_enable(struct bna_tx *tx)
4031{
4032 if (tx->fsm != (bfa_sm_t)bna_tx_sm_stopped)
4033 return;
4034
4035 tx->flags |= BNA_TX_F_ENABLED;
4036
4037 if (tx->flags & BNA_TX_F_PORT_STARTED)
4038 bfa_fsm_send_event(tx, TX_E_START);
4039}
4040
4041void
4042bna_tx_disable(struct bna_tx *tx, enum bna_cleanup_type type,
4043 void (*cbfn)(void *, struct bna_tx *, enum bna_cb_status))
4044{
4045 if (type == BNA_SOFT_CLEANUP) {
4046 (*cbfn)(tx->bna->bnad, tx, BNA_CB_SUCCESS);
4047 return;
4048 }
4049
4050 tx->stop_cbfn = cbfn;
4051 tx->stop_cbarg = tx->bna->bnad;
4052
4053 tx->flags &= ~BNA_TX_F_ENABLED;
4054
4055 bfa_fsm_send_event(tx, TX_E_STOP);
4056}
4057
4058int
4059bna_tx_state_get(struct bna_tx *tx)
4060{
4061 return bfa_sm_to_state(tx_sm_table, tx->fsm);
4062}
4063
4064void
4065bna_tx_mod_init(struct bna_tx_mod *tx_mod, struct bna *bna,
4066 struct bna_res_info *res_info)
4067{
4068 int i;
4069
4070 tx_mod->bna = bna;
4071 tx_mod->flags = 0;
4072
4073 tx_mod->tx = (struct bna_tx *)
4074 res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.mdl[0].kva;
4075 tx_mod->txq = (struct bna_txq *)
4076 res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.mdl[0].kva;
4077
4078 INIT_LIST_HEAD(&tx_mod->tx_free_q);
4079 INIT_LIST_HEAD(&tx_mod->tx_active_q);
4080
4081 INIT_LIST_HEAD(&tx_mod->txq_free_q);
4082
4083 for (i = 0; i < BFI_MAX_TXQ; i++) {
4084 tx_mod->tx[i].txf.txf_id = i;
4085 bfa_q_qe_init(&tx_mod->tx[i].qe);
4086 list_add_tail(&tx_mod->tx[i].qe, &tx_mod->tx_free_q);
4087
4088 tx_mod->txq[i].txq_id = i;
4089 bfa_q_qe_init(&tx_mod->txq[i].qe);
4090 list_add_tail(&tx_mod->txq[i].qe, &tx_mod->txq_free_q);
4091 }
4092
4093 tx_mod->tx_stop_wc.wc_resume = bna_tx_mod_cb_tx_stopped_all;
4094 tx_mod->tx_stop_wc.wc_cbarg = tx_mod;
4095 tx_mod->tx_stop_wc.wc_count = 0;
4096}
4097
4098void
4099bna_tx_mod_uninit(struct bna_tx_mod *tx_mod)
4100{
4101 struct list_head *qe;
4102 int i;
4103
4104 i = 0;
4105 list_for_each(qe, &tx_mod->tx_free_q)
4106 i++;
4107
4108 i = 0;
4109 list_for_each(qe, &tx_mod->txq_free_q)
4110 i++;
4111
4112 tx_mod->bna = NULL;
4113}
4114
4115void
4116bna_tx_mod_start(struct bna_tx_mod *tx_mod, enum bna_tx_type type)
4117{
4118 struct bna_tx *tx;
4119 struct list_head *qe;
4120
4121 tx_mod->flags |= BNA_TX_MOD_F_PORT_STARTED;
4122 if (type == BNA_TX_T_LOOPBACK)
4123 tx_mod->flags |= BNA_TX_MOD_F_PORT_LOOPBACK;
4124
4125 list_for_each(qe, &tx_mod->tx_active_q) {
4126 tx = (struct bna_tx *)qe;
4127 if (tx->type == type)
4128 bna_tx_start(tx);
4129 }
4130}
4131
4132void
4133bna_tx_mod_stop(struct bna_tx_mod *tx_mod, enum bna_tx_type type)
4134{
4135 struct bna_tx *tx;
4136 struct list_head *qe;
4137
4138 tx_mod->flags &= ~BNA_TX_MOD_F_PORT_STARTED;
4139 tx_mod->flags &= ~BNA_TX_MOD_F_PORT_LOOPBACK;
4140
4141 tx_mod->stop_cbfn = bna_port_cb_tx_stopped;
4142
4143 /**
4144 * Before calling bna_tx_stop(), increment tx_stop_wc as many times
4145 * as we are going to call bna_tx_stop
4146 */
4147 list_for_each(qe, &tx_mod->tx_active_q) {
4148 tx = (struct bna_tx *)qe;
4149 if (tx->type == type)
4150 bfa_wc_up(&tx_mod->tx_stop_wc);
4151 }
4152
4153 if (tx_mod->tx_stop_wc.wc_count == 0) {
4154 tx_mod->stop_cbfn(&tx_mod->bna->port, BNA_CB_SUCCESS);
4155 tx_mod->stop_cbfn = NULL;
4156 return;
4157 }
4158
4159 list_for_each(qe, &tx_mod->tx_active_q) {
4160 tx = (struct bna_tx *)qe;
4161 if (tx->type == type)
4162 bna_tx_stop(tx);
4163 }
4164}
4165
4166void
4167bna_tx_mod_fail(struct bna_tx_mod *tx_mod)
4168{
4169 struct bna_tx *tx;
4170 struct list_head *qe;
4171
4172 tx_mod->flags &= ~BNA_TX_MOD_F_PORT_STARTED;
4173 tx_mod->flags &= ~BNA_TX_MOD_F_PORT_LOOPBACK;
4174
4175 list_for_each(qe, &tx_mod->tx_active_q) {
4176 tx = (struct bna_tx *)qe;
4177 bna_tx_fail(tx);
4178 }
4179}
4180
4181void
4182bna_tx_mod_prio_changed(struct bna_tx_mod *tx_mod, int prio)
4183{
4184 struct bna_tx *tx;
4185 struct list_head *qe;
4186
4187 if (prio != tx_mod->priority) {
4188 tx_mod->priority = prio;
4189
4190 list_for_each(qe, &tx_mod->tx_active_q) {
4191 tx = (struct bna_tx *)qe;
4192 bna_tx_prio_changed(tx, prio);
4193 }
4194 }
4195}
4196
4197void
4198bna_tx_mod_cee_link_status(struct bna_tx_mod *tx_mod, int cee_link)
4199{
4200 struct bna_tx *tx;
4201 struct list_head *qe;
4202
4203 tx_mod->cee_link = cee_link;
4204
4205 list_for_each(qe, &tx_mod->tx_active_q) {
4206 tx = (struct bna_tx *)qe;
4207 bna_tx_cee_link_status(tx, cee_link);
4208 }
4209}
diff --git a/drivers/net/bna/bna_types.h b/drivers/net/bna/bna_types.h
new file mode 100644
index 000000000000..6877310f6ef4
--- /dev/null
+++ b/drivers/net/bna/bna_types.h
@@ -0,0 +1,1128 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18#ifndef __BNA_TYPES_H__
19#define __BNA_TYPES_H__
20
21#include "cna.h"
22#include "bna_hw.h"
23#include "bfa_cee.h"
24
25/**
26 *
27 * Forward declarations
28 *
29 */
30
31struct bna_txq;
32struct bna_tx;
33struct bna_rxq;
34struct bna_cq;
35struct bna_rx;
36struct bna_rxf;
37struct bna_port;
38struct bna;
39struct bnad;
40
41/**
42 *
43 * Enums, primitive data types
44 *
45 */
46
47enum bna_status {
48 BNA_STATUS_T_DISABLED = 0,
49 BNA_STATUS_T_ENABLED = 1
50};
51
52enum bna_cleanup_type {
53 BNA_HARD_CLEANUP = 0,
54 BNA_SOFT_CLEANUP = 1
55};
56
57enum bna_cb_status {
58 BNA_CB_SUCCESS = 0,
59 BNA_CB_FAIL = 1,
60 BNA_CB_INTERRUPT = 2,
61 BNA_CB_BUSY = 3,
62 BNA_CB_INVALID_MAC = 4,
63 BNA_CB_MCAST_LIST_FULL = 5,
64 BNA_CB_UCAST_CAM_FULL = 6,
65 BNA_CB_WAITING = 7,
66 BNA_CB_NOT_EXEC = 8
67};
68
69enum bna_res_type {
70 BNA_RES_T_MEM = 1,
71 BNA_RES_T_INTR = 2
72};
73
74enum bna_mem_type {
75 BNA_MEM_T_KVA = 1,
76 BNA_MEM_T_DMA = 2
77};
78
79enum bna_intr_type {
80 BNA_INTR_T_INTX = 1,
81 BNA_INTR_T_MSIX = 2
82};
83
84enum bna_res_req_type {
85 BNA_RES_MEM_T_COM = 0,
86 BNA_RES_MEM_T_ATTR = 1,
87 BNA_RES_MEM_T_FWTRC = 2,
88 BNA_RES_MEM_T_STATS = 3,
89 BNA_RES_MEM_T_SWSTATS = 4,
90 BNA_RES_MEM_T_IBIDX = 5,
91 BNA_RES_MEM_T_IB_ARRAY = 6,
92 BNA_RES_MEM_T_INTR_ARRAY = 7,
93 BNA_RES_MEM_T_IDXSEG_ARRAY = 8,
94 BNA_RES_MEM_T_TX_ARRAY = 9,
95 BNA_RES_MEM_T_TXQ_ARRAY = 10,
96 BNA_RES_MEM_T_RX_ARRAY = 11,
97 BNA_RES_MEM_T_RXP_ARRAY = 12,
98 BNA_RES_MEM_T_RXQ_ARRAY = 13,
99 BNA_RES_MEM_T_UCMAC_ARRAY = 14,
100 BNA_RES_MEM_T_MCMAC_ARRAY = 15,
101 BNA_RES_MEM_T_RIT_ENTRY = 16,
102 BNA_RES_MEM_T_RIT_SEGMENT = 17,
103 BNA_RES_INTR_T_MBOX = 18,
104 BNA_RES_T_MAX
105};
106
107enum bna_tx_res_req_type {
108 BNA_TX_RES_MEM_T_TCB = 0,
109 BNA_TX_RES_MEM_T_UNMAPQ = 1,
110 BNA_TX_RES_MEM_T_QPT = 2,
111 BNA_TX_RES_MEM_T_SWQPT = 3,
112 BNA_TX_RES_MEM_T_PAGE = 4,
113 BNA_TX_RES_INTR_T_TXCMPL = 5,
114 BNA_TX_RES_T_MAX,
115};
116
117enum bna_rx_mem_type {
118 BNA_RX_RES_MEM_T_CCB = 0, /* CQ context */
119 BNA_RX_RES_MEM_T_RCB = 1, /* CQ context */
120 BNA_RX_RES_MEM_T_UNMAPQ = 2, /* UnmapQ for RxQs */
121 BNA_RX_RES_MEM_T_CQPT = 3, /* CQ QPT */
122 BNA_RX_RES_MEM_T_CSWQPT = 4, /* S/W QPT */
123 BNA_RX_RES_MEM_T_CQPT_PAGE = 5, /* CQPT page */
124 BNA_RX_RES_MEM_T_HQPT = 6, /* RX QPT */
125 BNA_RX_RES_MEM_T_DQPT = 7, /* RX QPT */
126 BNA_RX_RES_MEM_T_HSWQPT = 8, /* RX s/w QPT */
127 BNA_RX_RES_MEM_T_DSWQPT = 9, /* RX s/w QPT */
128 BNA_RX_RES_MEM_T_DPAGE = 10, /* RX s/w QPT */
129 BNA_RX_RES_MEM_T_HPAGE = 11, /* RX s/w QPT */
130 BNA_RX_RES_T_INTR = 12, /* Rx interrupts */
131 BNA_RX_RES_T_MAX = 13
132};
133
134enum bna_mbox_state {
135 BNA_MBOX_FREE = 0,
136 BNA_MBOX_POSTED = 1
137};
138
139enum bna_tx_type {
140 BNA_TX_T_REGULAR = 0,
141 BNA_TX_T_LOOPBACK = 1,
142};
143
144enum bna_tx_flags {
145 BNA_TX_F_PORT_STARTED = 1,
146 BNA_TX_F_ENABLED = 2,
147 BNA_TX_F_PRIO_LOCK = 4,
148};
149
150enum bna_tx_mod_flags {
151 BNA_TX_MOD_F_PORT_STARTED = 1,
152 BNA_TX_MOD_F_PORT_LOOPBACK = 2,
153};
154
155enum bna_rx_type {
156 BNA_RX_T_REGULAR = 0,
157 BNA_RX_T_LOOPBACK = 1,
158};
159
160enum bna_rxp_type {
161 BNA_RXP_SINGLE = 1,
162 BNA_RXP_SLR = 2,
163 BNA_RXP_HDS = 3
164};
165
166enum bna_rxmode {
167 BNA_RXMODE_PROMISC = 1,
168 BNA_RXMODE_DEFAULT = 2,
169 BNA_RXMODE_ALLMULTI = 4
170};
171
172enum bna_rx_event {
173 RX_E_START = 1,
174 RX_E_STOP = 2,
175 RX_E_FAIL = 3,
176 RX_E_RXF_STARTED = 4,
177 RX_E_RXF_STOPPED = 5,
178 RX_E_RXQ_STOPPED = 6,
179};
180
181enum bna_rx_state {
182 BNA_RX_STOPPED = 1,
183 BNA_RX_RXF_START_WAIT = 2,
184 BNA_RX_STARTED = 3,
185 BNA_RX_RXF_STOP_WAIT = 4,
186 BNA_RX_RXQ_STOP_WAIT = 5,
187};
188
189enum bna_rx_flags {
190 BNA_RX_F_ENABLE = 0x01, /* bnad enabled rxf */
191 BNA_RX_F_PORT_ENABLED = 0x02, /* Port object is enabled */
192 BNA_RX_F_PORT_FAILED = 0x04, /* Port in failed state */
193};
194
195enum bna_rx_mod_flags {
196 BNA_RX_MOD_F_PORT_STARTED = 1,
197 BNA_RX_MOD_F_PORT_LOOPBACK = 2,
198};
199
200enum bna_rxf_oper_state {
201 BNA_RXF_OPER_STATE_RUNNING = 0x01, /* rxf operational */
202 BNA_RXF_OPER_STATE_PAUSED = 0x02, /* rxf in PAUSED state */
203};
204
205enum bna_rxf_flags {
206 BNA_RXF_FL_STOP_PENDING = 0x01,
207 BNA_RXF_FL_FAILED = 0x02,
208 BNA_RXF_FL_RSS_CONFIG_PENDING = 0x04,
209 BNA_RXF_FL_OPERSTATE_CHANGED = 0x08,
210 BNA_RXF_FL_RXF_ENABLED = 0x10,
211 BNA_RXF_FL_VLAN_CONFIG_PENDING = 0x20,
212};
213
214enum bna_rxf_event {
215 RXF_E_START = 1,
216 RXF_E_STOP = 2,
217 RXF_E_FAIL = 3,
218 RXF_E_CAM_FLTR_MOD = 4,
219 RXF_E_STARTED = 5,
220 RXF_E_STOPPED = 6,
221 RXF_E_CAM_FLTR_RESP = 7,
222 RXF_E_PAUSE = 8,
223 RXF_E_RESUME = 9,
224 RXF_E_STAT_CLEARED = 10,
225};
226
227enum bna_rxf_state {
228 BNA_RXF_STOPPED = 1,
229 BNA_RXF_START_WAIT = 2,
230 BNA_RXF_CAM_FLTR_MOD_WAIT = 3,
231 BNA_RXF_STARTED = 4,
232 BNA_RXF_CAM_FLTR_CLR_WAIT = 5,
233 BNA_RXF_STOP_WAIT = 6,
234 BNA_RXF_PAUSE_WAIT = 7,
235 BNA_RXF_RESUME_WAIT = 8,
236 BNA_RXF_STAT_CLR_WAIT = 9,
237};
238
239enum bna_port_type {
240 BNA_PORT_T_REGULAR = 0,
241 BNA_PORT_T_LOOPBACK_INTERNAL = 1,
242 BNA_PORT_T_LOOPBACK_EXTERNAL = 2,
243};
244
245enum bna_link_status {
246 BNA_LINK_DOWN = 0,
247 BNA_LINK_UP = 1,
248 BNA_CEE_UP = 2
249};
250
251enum bna_llport_flags {
252 BNA_LLPORT_F_ENABLED = 1,
253 BNA_LLPORT_F_RX_ENABLED = 2
254};
255
256enum bna_port_flags {
257 BNA_PORT_F_DEVICE_READY = 1,
258 BNA_PORT_F_ENABLED = 2,
259 BNA_PORT_F_PAUSE_CHANGED = 4,
260 BNA_PORT_F_MTU_CHANGED = 8
261};
262
263enum bna_pkt_rates {
264 BNA_PKT_RATE_10K = 10000,
265 BNA_PKT_RATE_20K = 20000,
266 BNA_PKT_RATE_30K = 30000,
267 BNA_PKT_RATE_40K = 40000,
268 BNA_PKT_RATE_50K = 50000,
269 BNA_PKT_RATE_60K = 60000,
270 BNA_PKT_RATE_70K = 70000,
271 BNA_PKT_RATE_80K = 80000,
272};
273
274enum bna_dim_load_types {
275 BNA_LOAD_T_HIGH_4 = 0, /* 80K <= r */
276 BNA_LOAD_T_HIGH_3 = 1, /* 60K <= r < 80K */
277 BNA_LOAD_T_HIGH_2 = 2, /* 50K <= r < 60K */
278 BNA_LOAD_T_HIGH_1 = 3, /* 40K <= r < 50K */
279 BNA_LOAD_T_LOW_1 = 4, /* 30K <= r < 40K */
280 BNA_LOAD_T_LOW_2 = 5, /* 20K <= r < 30K */
281 BNA_LOAD_T_LOW_3 = 6, /* 10K <= r < 20K */
282 BNA_LOAD_T_LOW_4 = 7, /* r < 10K */
283 BNA_LOAD_T_MAX = 8
284};
285
286enum bna_dim_bias_types {
287 BNA_BIAS_T_SMALL = 0, /* small pkts > (large pkts * 2) */
288 BNA_BIAS_T_LARGE = 1, /* Not BNA_BIAS_T_SMALL */
289 BNA_BIAS_T_MAX = 2
290};
291
292struct bna_mac {
293 /* This should be the first one */
294 struct list_head qe;
295 u8 addr[ETH_ALEN];
296};
297
298struct bna_mem_descr {
299 u32 len;
300 void *kva;
301 struct bna_dma_addr dma;
302};
303
304struct bna_mem_info {
305 enum bna_mem_type mem_type;
306 u32 len;
307 u32 num;
308 u32 align_sz; /* 0/1 = no alignment */
309 struct bna_mem_descr *mdl;
310 void *cookie; /* For bnad to unmap dma later */
311};
312
313struct bna_intr_descr {
314 int vector;
315};
316
317struct bna_intr_info {
318 enum bna_intr_type intr_type;
319 int num;
320 struct bna_intr_descr *idl;
321};
322
323union bna_res_u {
324 struct bna_mem_info mem_info;
325 struct bna_intr_info intr_info;
326};
327
328struct bna_res_info {
329 enum bna_res_type res_type;
330 union bna_res_u res_u;
331};
332
333/* HW QPT */
334struct bna_qpt {
335 struct bna_dma_addr hw_qpt_ptr;
336 void *kv_qpt_ptr;
337 u32 page_count;
338 u32 page_size;
339};
340
341/**
342 *
343 * Device
344 *
345 */
346
347struct bna_device {
348 bfa_fsm_t fsm;
349 struct bfa_ioc ioc;
350
351 enum bna_intr_type intr_type;
352 int vector;
353
354 void (*ready_cbfn)(struct bnad *bnad, enum bna_cb_status status);
355 struct bnad *ready_cbarg;
356
357 void (*stop_cbfn)(struct bnad *bnad, enum bna_cb_status status);
358 struct bnad *stop_cbarg;
359
360 struct bna *bna;
361};
362
363/**
364 *
365 * Mail box
366 *
367 */
368
369struct bna_mbox_qe {
370 /* This should be the first one */
371 struct list_head qe;
372
373 struct bfa_mbox_cmd cmd;
374 u32 cmd_len;
375 /* Callback for port, tx, rx, rxf */
376 void (*cbfn)(void *arg, int status);
377 void *cbarg;
378};
379
380struct bna_mbox_mod {
381 enum bna_mbox_state state;
382 struct list_head posted_q;
383 u32 msg_pending;
384 u32 msg_ctr;
385 struct bna *bna;
386};
387
388/**
389 *
390 * Port
391 *
392 */
393
394/* Pause configuration */
395struct bna_pause_config {
396 enum bna_status tx_pause;
397 enum bna_status rx_pause;
398};
399
400struct bna_llport {
401 bfa_fsm_t fsm;
402 enum bna_llport_flags flags;
403
404 enum bna_port_type type;
405
406 enum bna_link_status link_status;
407
408 int admin_up_count;
409
410 void (*stop_cbfn)(struct bna_port *, enum bna_cb_status);
411
412 struct bna_mbox_qe mbox_qe;
413
414 struct bna *bna;
415};
416
417struct bna_port {
418 bfa_fsm_t fsm;
419 enum bna_port_flags flags;
420
421 enum bna_port_type type;
422
423 struct bna_llport llport;
424
425 struct bna_pause_config pause_config;
426 u8 priority;
427 int mtu;
428
429 /* Callback for bna_port_disable(), port_stop() */
430 void (*stop_cbfn)(void *, enum bna_cb_status);
431 void *stop_cbarg;
432
433 /* Callback for bna_port_pause_config() */
434 void (*pause_cbfn)(struct bnad *, enum bna_cb_status);
435
436 /* Callback for bna_port_mtu_set() */
437 void (*mtu_cbfn)(struct bnad *, enum bna_cb_status);
438
439 void (*link_cbfn)(struct bnad *, enum bna_link_status);
440
441 struct bfa_wc chld_stop_wc;
442
443 struct bna_mbox_qe mbox_qe;
444
445 struct bna *bna;
446};
447
448/**
449 *
450 * Interrupt Block
451 *
452 */
453
454/* IB index segment structure */
455struct bna_ibidx_seg {
456 /* This should be the first one */
457 struct list_head qe;
458
459 u8 ib_seg_size;
460 u8 ib_idx_tbl_offset;
461};
462
463/* Interrupt structure */
464struct bna_intr {
465 /* This should be the first one */
466 struct list_head qe;
467 int ref_count;
468
469 enum bna_intr_type intr_type;
470 int vector;
471
472 struct bna_ib *ib;
473};
474
475/* Doorbell structure */
476struct bna_ib_dbell {
477 void *__iomem doorbell_addr;
478 u32 doorbell_ack;
479};
480
481/* Interrupt timer configuration */
482struct bna_ib_config {
483 u8 coalescing_timeo; /* Unit is 5usec. */
484
485 int interpkt_count;
486 int interpkt_timeo;
487
488 enum ib_flags ctrl_flags;
489};
490
491/* IB structure */
492struct bna_ib {
493 /* This should be the first one */
494 struct list_head qe;
495
496 int ib_id;
497
498 int ref_count;
499 int start_count;
500
501 struct bna_dma_addr ib_seg_host_addr;
502 void *ib_seg_host_addr_kva;
503 u32 idx_mask; /* Size >= BNA_IBIDX_MAX_SEGSIZE */
504
505 struct bna_ibidx_seg *idx_seg;
506
507 struct bna_ib_dbell door_bell;
508
509 struct bna_intr *intr;
510
511 struct bna_ib_config ib_config;
512
513 struct bna *bna;
514};
515
516/* IB module - keeps track of IBs and interrupts */
517struct bna_ib_mod {
518 struct bna_ib *ib; /* BFI_MAX_IB entries */
519 struct bna_intr *intr; /* BFI_MAX_IB entries */
520 struct bna_ibidx_seg *idx_seg; /* BNA_IBIDX_TOTAL_SEGS */
521
522 struct list_head ib_free_q;
523
524 struct list_head ibidx_seg_pool[BFI_IBIDX_TOTAL_POOLS];
525
526 struct list_head intr_free_q;
527 struct list_head intr_active_q;
528
529 struct bna *bna;
530};
531
532/**
533 *
534 * Tx object
535 *
536 */
537
538/* Tx datapath control structure */
539#define BNA_Q_NAME_SIZE 16
540struct bna_tcb {
541 /* Fast path */
542 void **sw_qpt;
543 void *unmap_q;
544 u32 producer_index;
545 u32 consumer_index;
546 volatile u32 *hw_consumer_index;
547 u32 q_depth;
548 void *__iomem q_dbell;
549 struct bna_ib_dbell *i_dbell;
550 int page_idx;
551 int page_count;
552 /* Control path */
553 struct bna_txq *txq;
554 struct bnad *bnad;
555 enum bna_intr_type intr_type;
556 int intr_vector;
557 u8 priority; /* Current priority */
558 unsigned long flags; /* Used by bnad as required */
559 int id;
560 char name[BNA_Q_NAME_SIZE];
561};
562
563/* TxQ QPT and configuration */
564struct bna_txq {
565 /* This should be the first one */
566 struct list_head qe;
567
568 int txq_id;
569
570 u8 priority;
571
572 struct bna_qpt qpt;
573 struct bna_tcb *tcb;
574 struct bna_ib *ib;
575 int ib_seg_offset;
576
577 struct bna_tx *tx;
578
579 u64 tx_packets;
580 u64 tx_bytes;
581};
582
583/* TxF structure (hardware Tx Function) */
584struct bna_txf {
585 int txf_id;
586 enum txf_flags ctrl_flags;
587 u16 vlan;
588};
589
590/* Tx object */
591struct bna_tx {
592 /* This should be the first one */
593 struct list_head qe;
594
595 bfa_fsm_t fsm;
596 enum bna_tx_flags flags;
597
598 enum bna_tx_type type;
599
600 struct list_head txq_q;
601 struct bna_txf txf;
602
603 /* Tx event handlers */
604 void (*tcb_setup_cbfn)(struct bnad *, struct bna_tcb *);
605 void (*tcb_destroy_cbfn)(struct bnad *, struct bna_tcb *);
606 void (*tx_stall_cbfn)(struct bnad *, struct bna_tcb *);
607 void (*tx_resume_cbfn)(struct bnad *, struct bna_tcb *);
608 void (*tx_cleanup_cbfn)(struct bnad *, struct bna_tcb *);
609
610 /* callback for bna_tx_disable(), bna_tx_stop() */
611 void (*stop_cbfn)(void *arg, struct bna_tx *tx,
612 enum bna_cb_status status);
613 void *stop_cbarg;
614
615 /* callback for bna_tx_prio_set() */
616 void (*prio_change_cbfn)(struct bnad *bnad, struct bna_tx *tx,
617 enum bna_cb_status status);
618
619 struct bfa_wc txq_stop_wc;
620
621 struct bna_mbox_qe mbox_qe;
622
623 struct bna *bna;
624 void *priv; /* bnad's cookie */
625};
626
627struct bna_tx_config {
628 int num_txq;
629 int txq_depth;
630 enum bna_tx_type tx_type;
631};
632
633struct bna_tx_event_cbfn {
634 /* Optional */
635 void (*tcb_setup_cbfn)(struct bnad *, struct bna_tcb *);
636 void (*tcb_destroy_cbfn)(struct bnad *, struct bna_tcb *);
637 /* Mandatory */
638 void (*tx_stall_cbfn)(struct bnad *, struct bna_tcb *);
639 void (*tx_resume_cbfn)(struct bnad *, struct bna_tcb *);
640 void (*tx_cleanup_cbfn)(struct bnad *, struct bna_tcb *);
641};
642
643/* Tx module - keeps track of free, active tx objects */
644struct bna_tx_mod {
645 struct bna_tx *tx; /* BFI_MAX_TXQ entries */
646 struct bna_txq *txq; /* BFI_MAX_TXQ entries */
647
648 struct list_head tx_free_q;
649 struct list_head tx_active_q;
650
651 struct list_head txq_free_q;
652
653 /* callback for bna_tx_mod_stop() */
654 void (*stop_cbfn)(struct bna_port *port,
655 enum bna_cb_status status);
656
657 struct bfa_wc tx_stop_wc;
658
659 enum bna_tx_mod_flags flags;
660
661 int priority;
662 int cee_link;
663
664 u32 txf_bmap[2];
665
666 struct bna *bna;
667};
668
669/**
670 *
671 * Receive Indirection Table
672 *
673 */
674
675/* One row of RIT table */
676struct bna_rit_entry {
677 u8 large_rxq_id; /* used for either large or data buffers */
678 u8 small_rxq_id; /* used for either small or header buffers */
679};
680
681/* RIT segment */
682struct bna_rit_segment {
683 struct list_head qe;
684
685 u32 rit_offset;
686 u32 rit_size;
687 /**
688 * max_rit_size: Varies per RIT segment depending on how RIT is
689 * partitioned
690 */
691 u32 max_rit_size;
692
693 struct bna_rit_entry *rit;
694};
695
696struct bna_rit_mod {
697 struct bna_rit_entry *rit;
698 struct bna_rit_segment *rit_segment;
699
700 struct list_head rit_seg_pool[BFI_RIT_SEG_TOTAL_POOLS];
701};
702
703/**
704 *
705 * Rx object
706 *
707 */
708
709/* Rx datapath control structure */
710struct bna_rcb {
711 /* Fast path */
712 void **sw_qpt;
713 void *unmap_q;
714 u32 producer_index;
715 u32 consumer_index;
716 u32 q_depth;
717 void *__iomem q_dbell;
718 int page_idx;
719 int page_count;
720 /* Control path */
721 struct bna_rxq *rxq;
722 struct bna_cq *cq;
723 struct bnad *bnad;
724 unsigned long flags;
725 int id;
726};
727
728/* RxQ structure - QPT, configuration */
729struct bna_rxq {
730 struct list_head qe;
731 int rxq_id;
732
733 int buffer_size;
734 int q_depth;
735
736 struct bna_qpt qpt;
737 struct bna_rcb *rcb;
738
739 struct bna_rxp *rxp;
740 struct bna_rx *rx;
741
742 u64 rx_packets;
743 u64 rx_bytes;
744 u64 rx_packets_with_error;
745 u64 rxbuf_alloc_failed;
746};
747
748/* RxQ pair */
749union bna_rxq_u {
750 struct {
751 struct bna_rxq *hdr;
752 struct bna_rxq *data;
753 } hds;
754 struct {
755 struct bna_rxq *small;
756 struct bna_rxq *large;
757 } slr;
758 struct {
759 struct bna_rxq *only;
760 struct bna_rxq *reserved;
761 } single;
762};
763
764/* Packet rate for Dynamic Interrupt Moderation */
765struct bna_pkt_rate {
766 u32 small_pkt_cnt;
767 u32 large_pkt_cnt;
768};
769
770/* Completion control structure */
771struct bna_ccb {
772 /* Fast path */
773 void **sw_qpt;
774 u32 producer_index;
775 volatile u32 *hw_producer_index;
776 u32 q_depth;
777 struct bna_ib_dbell *i_dbell;
778 struct bna_rcb *rcb[2];
779 void *ctrl; /* For bnad */
780 struct bna_pkt_rate pkt_rate;
781 int page_idx;
782 int page_count;
783
784 /* Control path */
785 struct bna_cq *cq;
786 struct bnad *bnad;
787 enum bna_intr_type intr_type;
788 int intr_vector;
789 u8 rx_coalescing_timeo; /* For NAPI */
790 int id;
791 char name[BNA_Q_NAME_SIZE];
792};
793
794/* CQ QPT, configuration */
795struct bna_cq {
796 int cq_id;
797
798 struct bna_qpt qpt;
799 struct bna_ccb *ccb;
800
801 struct bna_ib *ib;
802 u8 ib_seg_offset;
803
804 struct bna_rx *rx;
805};
806
807struct bna_rss_config {
808 enum rss_hash_type hash_type;
809 u8 hash_mask;
810 u32 toeplitz_hash_key[BFI_RSS_HASH_KEY_LEN];
811};
812
813struct bna_hds_config {
814 enum hds_header_type hdr_type;
815 int header_size;
816};
817
818/* This structure is used during RX creation */
819struct bna_rx_config {
820 enum bna_rx_type rx_type;
821 int num_paths;
822 enum bna_rxp_type rxp_type;
823 int paused;
824 int q_depth;
825 /*
826 * Small/Large (or Header/Data) buffer size to be configured
827 * for SLR and HDS queue type. Large buffer size comes from
828 * port->mtu.
829 */
830 int small_buff_size;
831
832 enum bna_status rss_status;
833 struct bna_rss_config rss_config;
834
835 enum bna_status hds_status;
836 struct bna_hds_config hds_config;
837
838 enum bna_status vlan_strip_status;
839};
840
841/* Rx Path structure - one per MSIX vector/CPU */
842struct bna_rxp {
843 /* This should be the first one */
844 struct list_head qe;
845
846 enum bna_rxp_type type;
847 union bna_rxq_u rxq;
848 struct bna_cq cq;
849
850 struct bna_rx *rx;
851
852 /* MSI-x vector number for configuring RSS */
853 int vector;
854
855 struct bna_mbox_qe mbox_qe;
856};
857
858/* HDS configuration structure */
859struct bna_rxf_hds {
860 enum hds_header_type hdr_type;
861 int header_size;
862};
863
864/* RSS configuration structure */
865struct bna_rxf_rss {
866 enum rss_hash_type hash_type;
867 u8 hash_mask;
868 u32 toeplitz_hash_key[BFI_RSS_HASH_KEY_LEN];
869};
870
871/* RxF structure (hardware Rx Function) */
872struct bna_rxf {
873 bfa_fsm_t fsm;
874 int rxf_id;
875 enum rxf_flags ctrl_flags;
876 u16 default_vlan_tag;
877 enum bna_rxf_oper_state rxf_oper_state;
878 enum bna_status hds_status;
879 struct bna_rxf_hds hds_cfg;
880 enum bna_status rss_status;
881 struct bna_rxf_rss rss_cfg;
882 struct bna_rit_segment *rit_segment;
883 struct bna_rx *rx;
884 u32 forced_offset;
885 struct bna_mbox_qe mbox_qe;
886 int mcast_rxq_id;
887
888 /* callback for bna_rxf_start() */
889 void (*start_cbfn) (struct bna_rx *rx, enum bna_cb_status status);
890 struct bna_rx *start_cbarg;
891
892 /* callback for bna_rxf_stop() */
893 void (*stop_cbfn) (struct bna_rx *rx, enum bna_cb_status status);
894 struct bna_rx *stop_cbarg;
895
896 /* callback for bna_rxf_receive_enable() / bna_rxf_receive_disable() */
897 void (*oper_state_cbfn) (struct bnad *bnad, struct bna_rx *rx,
898 enum bna_cb_status status);
899 struct bnad *oper_state_cbarg;
900
901 /**
902 * callback for:
903 * bna_rxf_ucast_set()
904 * bna_rxf_{ucast/mcast}_add(),
905 * bna_rxf_{ucast/mcast}_del(),
906 * bna_rxf_mode_set()
907 */
908 void (*cam_fltr_cbfn)(struct bnad *bnad, struct bna_rx *rx,
909 enum bna_cb_status status);
910 struct bnad *cam_fltr_cbarg;
911
912 enum bna_rxf_flags rxf_flags;
913
914 /* List of unicast addresses yet to be applied to h/w */
915 struct list_head ucast_pending_add_q;
916 struct list_head ucast_pending_del_q;
917 int ucast_pending_set;
918 /* ucast addresses applied to the h/w */
919 struct list_head ucast_active_q;
920 struct bna_mac *ucast_active_mac;
921
922 /* List of multicast addresses yet to be applied to h/w */
923 struct list_head mcast_pending_add_q;
924 struct list_head mcast_pending_del_q;
925 /* multicast addresses applied to the h/w */
926 struct list_head mcast_active_q;
927
928 /* Rx modes yet to be applied to h/w */
929 enum bna_rxmode rxmode_pending;
930 enum bna_rxmode rxmode_pending_bitmask;
931 /* Rx modes applied to h/w */
932 enum bna_rxmode rxmode_active;
933
934 enum bna_status vlan_filter_status;
935 u32 vlan_filter_table[(BFI_MAX_VLAN + 1) / 32];
936};
937
938/* Rx object */
939struct bna_rx {
940 /* This should be the first one */
941 struct list_head qe;
942
943 bfa_fsm_t fsm;
944
945 enum bna_rx_type type;
946
947 /* list-head for RX path objects */
948 struct list_head rxp_q;
949
950 struct bna_rxf rxf;
951
952 enum bna_rx_flags rx_flags;
953
954 struct bna_mbox_qe mbox_qe;
955
956 struct bfa_wc rxq_stop_wc;
957
958 /* Rx event handlers */
959 void (*rcb_setup_cbfn)(struct bnad *, struct bna_rcb *);
960 void (*rcb_destroy_cbfn)(struct bnad *, struct bna_rcb *);
961 void (*ccb_setup_cbfn)(struct bnad *, struct bna_ccb *);
962 void (*ccb_destroy_cbfn)(struct bnad *, struct bna_ccb *);
963 void (*rx_cleanup_cbfn)(struct bnad *, struct bna_ccb *);
964 void (*rx_post_cbfn)(struct bnad *, struct bna_rcb *);
965
966 /* callback for bna_rx_disable(), bna_rx_stop() */
967 void (*stop_cbfn)(void *arg, struct bna_rx *rx,
968 enum bna_cb_status status);
969 void *stop_cbarg;
970
971 struct bna *bna;
972 void *priv; /* bnad's cookie */
973};
974
975struct bna_rx_event_cbfn {
976 /* Optional */
977 void (*rcb_setup_cbfn)(struct bnad *, struct bna_rcb *);
978 void (*rcb_destroy_cbfn)(struct bnad *, struct bna_rcb *);
979 void (*ccb_setup_cbfn)(struct bnad *, struct bna_ccb *);
980 void (*ccb_destroy_cbfn)(struct bnad *, struct bna_ccb *);
981 /* Mandatory */
982 void (*rx_cleanup_cbfn)(struct bnad *, struct bna_ccb *);
983 void (*rx_post_cbfn)(struct bnad *, struct bna_rcb *);
984};
985
986/* Rx module - keeps track of free, active rx objects */
987struct bna_rx_mod {
988 struct bna *bna; /* back pointer to parent */
989 struct bna_rx *rx; /* BFI_MAX_RXQ entries */
990 struct bna_rxp *rxp; /* BFI_MAX_RXQ entries */
991 struct bna_rxq *rxq; /* BFI_MAX_RXQ entries */
992
993 struct list_head rx_free_q;
994 struct list_head rx_active_q;
995 int rx_free_count;
996
997 struct list_head rxp_free_q;
998 int rxp_free_count;
999
1000 struct list_head rxq_free_q;
1001 int rxq_free_count;
1002
1003 enum bna_rx_mod_flags flags;
1004
1005 /* callback for bna_rx_mod_stop() */
1006 void (*stop_cbfn)(struct bna_port *port,
1007 enum bna_cb_status status);
1008
1009 struct bfa_wc rx_stop_wc;
1010 u32 dim_vector[BNA_LOAD_T_MAX][BNA_BIAS_T_MAX];
1011 u32 rxf_bmap[2];
1012};
1013
1014/**
1015 *
1016 * CAM
1017 *
1018 */
1019
1020struct bna_ucam_mod {
1021 struct bna_mac *ucmac; /* BFI_MAX_UCMAC entries */
1022 struct list_head free_q;
1023
1024 struct bna *bna;
1025};
1026
1027struct bna_mcam_mod {
1028 struct bna_mac *mcmac; /* BFI_MAX_MCMAC entries */
1029 struct list_head free_q;
1030
1031 struct bna *bna;
1032};
1033
1034/**
1035 *
1036 * Statistics
1037 *
1038 */
1039
1040struct bna_tx_stats {
1041 int tx_state;
1042 int tx_flags;
1043 int num_txqs;
1044 u32 txq_bmap[2];
1045 int txf_id;
1046};
1047
1048struct bna_rx_stats {
1049 int rx_state;
1050 int rx_flags;
1051 int num_rxps;
1052 int num_rxqs;
1053 u32 rxq_bmap[2];
1054 u32 cq_bmap[2];
1055 int rxf_id;
1056 int rxf_state;
1057 int rxf_oper_state;
1058 int num_active_ucast;
1059 int num_active_mcast;
1060 int rxmode_active;
1061 int vlan_filter_status;
1062 u32 vlan_filter_table[(BFI_MAX_VLAN + 1) / 32];
1063 int rss_status;
1064 int hds_status;
1065};
1066
1067struct bna_sw_stats {
1068 int device_state;
1069 int port_state;
1070 int port_flags;
1071 int llport_state;
1072 int priority;
1073 int num_active_tx;
1074 int num_active_rx;
1075 struct bna_tx_stats tx_stats[BFI_MAX_TXQ];
1076 struct bna_rx_stats rx_stats[BFI_MAX_RXQ];
1077};
1078
1079struct bna_stats {
1080 u32 txf_bmap[2];
1081 u32 rxf_bmap[2];
1082 struct bfi_ll_stats *hw_stats;
1083 struct bna_sw_stats *sw_stats;
1084};
1085
1086/**
1087 *
1088 * BNA
1089 *
1090 */
1091
1092struct bna {
1093 struct bfa_pcidev pcidev;
1094
1095 int port_num;
1096
1097 struct bna_chip_regs regs;
1098
1099 struct bna_dma_addr hw_stats_dma;
1100 struct bna_stats stats;
1101
1102 struct bna_device device;
1103 struct bfa_cee cee;
1104
1105 struct bna_mbox_mod mbox_mod;
1106
1107 struct bna_port port;
1108
1109 struct bna_tx_mod tx_mod;
1110
1111 struct bna_rx_mod rx_mod;
1112
1113 struct bna_ib_mod ib_mod;
1114
1115 struct bna_ucam_mod ucam_mod;
1116 struct bna_mcam_mod mcam_mod;
1117
1118 struct bna_rit_mod rit_mod;
1119
1120 int rxf_default_id;
1121 int rxf_promisc_id;
1122
1123 struct bna_mbox_qe mbox_qe;
1124
1125 struct bnad *bnad;
1126};
1127
1128#endif /* __BNA_TYPES_H__ */
diff --git a/drivers/net/bna/bnad.c b/drivers/net/bna/bnad.c
new file mode 100644
index 000000000000..491d148f88ae
--- /dev/null
+++ b/drivers/net/bna/bnad.c
@@ -0,0 +1,3270 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18#include <linux/netdevice.h>
19#include <linux/skbuff.h>
20#include <linux/etherdevice.h>
21#include <linux/in.h>
22#include <linux/ethtool.h>
23#include <linux/if_vlan.h>
24#include <linux/if_ether.h>
25#include <linux/ip.h>
26
27#include "bnad.h"
28#include "bna.h"
29#include "cna.h"
30
31DEFINE_MUTEX(bnad_fwimg_mutex);
32
33/*
34 * Module params
35 */
36static uint bnad_msix_disable;
37module_param(bnad_msix_disable, uint, 0444);
38MODULE_PARM_DESC(bnad_msix_disable, "Disable MSIX mode");
39
40static uint bnad_ioc_auto_recover = 1;
41module_param(bnad_ioc_auto_recover, uint, 0444);
42MODULE_PARM_DESC(bnad_ioc_auto_recover, "Enable / Disable auto recovery");
43
44/*
45 * Global variables
46 */
47u32 bnad_rxqs_per_cq = 2;
48
49const u8 bnad_bcast_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
50
51/*
52 * Local MACROS
53 */
54#define BNAD_TX_UNMAPQ_DEPTH (bnad->txq_depth * 2)
55
56#define BNAD_RX_UNMAPQ_DEPTH (bnad->rxq_depth)
57
58#define BNAD_GET_MBOX_IRQ(_bnad) \
59 (((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \
60 ((_bnad)->msix_table[(_bnad)->msix_num - 1].vector) : \
61 ((_bnad)->pcidev->irq))
62
63#define BNAD_FILL_UNMAPQ_MEM_REQ(_res_info, _num, _depth) \
64do { \
65 (_res_info)->res_type = BNA_RES_T_MEM; \
66 (_res_info)->res_u.mem_info.mem_type = BNA_MEM_T_KVA; \
67 (_res_info)->res_u.mem_info.num = (_num); \
68 (_res_info)->res_u.mem_info.len = \
69 sizeof(struct bnad_unmap_q) + \
70 (sizeof(struct bnad_skb_unmap) * ((_depth) - 1)); \
71} while (0)
72
73/*
74 * Reinitialize completions in CQ, once Rx is taken down
75 */
76static void
77bnad_cq_cmpl_init(struct bnad *bnad, struct bna_ccb *ccb)
78{
79 struct bna_cq_entry *cmpl, *next_cmpl;
80 unsigned int wi_range, wis = 0, ccb_prod = 0;
81 int i;
82
83 BNA_CQ_QPGE_PTR_GET(ccb_prod, ccb->sw_qpt, cmpl,
84 wi_range);
85
86 for (i = 0; i < ccb->q_depth; i++) {
87 wis++;
88 if (likely(--wi_range))
89 next_cmpl = cmpl + 1;
90 else {
91 BNA_QE_INDX_ADD(ccb_prod, wis, ccb->q_depth);
92 wis = 0;
93 BNA_CQ_QPGE_PTR_GET(ccb_prod, ccb->sw_qpt,
94 next_cmpl, wi_range);
95 }
96 cmpl->valid = 0;
97 cmpl = next_cmpl;
98 }
99}
100
101/*
102 * Frees all pending Tx Bufs
103 * At this point no activity is expected on the Q,
104 * so DMA unmap & freeing is fine.
105 */
106static void
107bnad_free_all_txbufs(struct bnad *bnad,
108 struct bna_tcb *tcb)
109{
110 u16 unmap_cons;
111 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
112 struct bnad_skb_unmap *unmap_array;
113 struct sk_buff *skb = NULL;
114 int i;
115
116 unmap_array = unmap_q->unmap_array;
117
118 unmap_cons = 0;
119 while (unmap_cons < unmap_q->q_depth) {
120 skb = unmap_array[unmap_cons].skb;
121 if (!skb) {
122 unmap_cons++;
123 continue;
124 }
125 unmap_array[unmap_cons].skb = NULL;
126
127 pci_unmap_single(bnad->pcidev,
128 pci_unmap_addr(&unmap_array[unmap_cons],
129 dma_addr), skb_headlen(skb),
130 PCI_DMA_TODEVICE);
131
132 pci_unmap_addr_set(&unmap_array[unmap_cons], dma_addr, 0);
133 unmap_cons++;
134 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
135 pci_unmap_page(bnad->pcidev,
136 pci_unmap_addr(&unmap_array[unmap_cons],
137 dma_addr),
138 skb_shinfo(skb)->frags[i].size,
139 PCI_DMA_TODEVICE);
140 pci_unmap_addr_set(&unmap_array[unmap_cons], dma_addr,
141 0);
142 unmap_cons++;
143 }
144 dev_kfree_skb_any(skb);
145 }
146}
147
148/* Data Path Handlers */
149
150/*
151 * bnad_free_txbufs : Frees the Tx bufs on Tx completion
152 * Can be called in a) Interrupt context
153 * b) Sending context
154 * c) Tasklet context
155 */
156static u32
157bnad_free_txbufs(struct bnad *bnad,
158 struct bna_tcb *tcb)
159{
160 u32 sent_packets = 0, sent_bytes = 0;
161 u16 wis, unmap_cons, updated_hw_cons;
162 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
163 struct bnad_skb_unmap *unmap_array;
164 struct sk_buff *skb;
165 int i;
166
167 /*
168 * Just return if TX is stopped. This check is useful
169 * when bnad_free_txbufs() runs out of a tasklet scheduled
170 * before bnad_cb_tx_cleanup() cleared BNAD_RF_TX_STARTED bit
171 * but this routine runs actually after the cleanup has been
172 * executed.
173 */
174 if (!test_bit(BNAD_RF_TX_STARTED, &bnad->run_flags))
175 return 0;
176
177 updated_hw_cons = *(tcb->hw_consumer_index);
178
179 wis = BNA_Q_INDEX_CHANGE(tcb->consumer_index,
180 updated_hw_cons, tcb->q_depth);
181
182 BUG_ON(!(wis <= BNA_QE_IN_USE_CNT(tcb, tcb->q_depth)));
183
184 unmap_array = unmap_q->unmap_array;
185 unmap_cons = unmap_q->consumer_index;
186
187 prefetch(&unmap_array[unmap_cons + 1]);
188 while (wis) {
189 skb = unmap_array[unmap_cons].skb;
190
191 unmap_array[unmap_cons].skb = NULL;
192
193 sent_packets++;
194 sent_bytes += skb->len;
195 wis -= BNA_TXQ_WI_NEEDED(1 + skb_shinfo(skb)->nr_frags);
196
197 pci_unmap_single(bnad->pcidev,
198 pci_unmap_addr(&unmap_array[unmap_cons],
199 dma_addr), skb_headlen(skb),
200 PCI_DMA_TODEVICE);
201 pci_unmap_addr_set(&unmap_array[unmap_cons], dma_addr, 0);
202 BNA_QE_INDX_ADD(unmap_cons, 1, unmap_q->q_depth);
203
204 prefetch(&unmap_array[unmap_cons + 1]);
205 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
206 prefetch(&unmap_array[unmap_cons + 1]);
207
208 pci_unmap_page(bnad->pcidev,
209 pci_unmap_addr(&unmap_array[unmap_cons],
210 dma_addr),
211 skb_shinfo(skb)->frags[i].size,
212 PCI_DMA_TODEVICE);
213 pci_unmap_addr_set(&unmap_array[unmap_cons], dma_addr,
214 0);
215 BNA_QE_INDX_ADD(unmap_cons, 1, unmap_q->q_depth);
216 }
217 dev_kfree_skb_any(skb);
218 }
219
220 /* Update consumer pointers. */
221 tcb->consumer_index = updated_hw_cons;
222 unmap_q->consumer_index = unmap_cons;
223
224 tcb->txq->tx_packets += sent_packets;
225 tcb->txq->tx_bytes += sent_bytes;
226
227 return sent_packets;
228}
229
230/* Tx Free Tasklet function */
231/* Frees for all the tcb's in all the Tx's */
232/*
233 * Scheduled from sending context, so that
234 * the fat Tx lock is not held for too long
235 * in the sending context.
236 */
237static void
238bnad_tx_free_tasklet(unsigned long bnad_ptr)
239{
240 struct bnad *bnad = (struct bnad *)bnad_ptr;
241 struct bna_tcb *tcb;
242 u32 acked;
243 int i, j;
244
245 for (i = 0; i < bnad->num_tx; i++) {
246 for (j = 0; j < bnad->num_txq_per_tx; j++) {
247 tcb = bnad->tx_info[i].tcb[j];
248 if (!tcb)
249 continue;
250 if (((u16) (*tcb->hw_consumer_index) !=
251 tcb->consumer_index) &&
252 (!test_and_set_bit(BNAD_TXQ_FREE_SENT,
253 &tcb->flags))) {
254 acked = bnad_free_txbufs(bnad, tcb);
255 bna_ib_ack(tcb->i_dbell, acked);
256 smp_mb__before_clear_bit();
257 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
258 }
259 }
260 }
261}
262
263static u32
264bnad_tx(struct bnad *bnad, struct bna_tcb *tcb)
265{
266 struct net_device *netdev = bnad->netdev;
267 u32 sent;
268
269 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
270 return 0;
271
272 sent = bnad_free_txbufs(bnad, tcb);
273 if (sent) {
274 if (netif_queue_stopped(netdev) &&
275 netif_carrier_ok(netdev) &&
276 BNA_QE_FREE_CNT(tcb, tcb->q_depth) >=
277 BNAD_NETIF_WAKE_THRESHOLD) {
278 netif_wake_queue(netdev);
279 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
280 }
281 bna_ib_ack(tcb->i_dbell, sent);
282 } else
283 bna_ib_ack(tcb->i_dbell, 0);
284
285 smp_mb__before_clear_bit();
286 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
287
288 return sent;
289}
290
291/* MSIX Tx Completion Handler */
292static irqreturn_t
293bnad_msix_tx(int irq, void *data)
294{
295 struct bna_tcb *tcb = (struct bna_tcb *)data;
296 struct bnad *bnad = tcb->bnad;
297
298 bnad_tx(bnad, tcb);
299
300 return IRQ_HANDLED;
301}
302
303static void
304bnad_reset_rcb(struct bnad *bnad, struct bna_rcb *rcb)
305{
306 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
307
308 rcb->producer_index = 0;
309 rcb->consumer_index = 0;
310
311 unmap_q->producer_index = 0;
312 unmap_q->consumer_index = 0;
313}
314
315static void
316bnad_free_rxbufs(struct bnad *bnad, struct bna_rcb *rcb)
317{
318 struct bnad_unmap_q *unmap_q;
319 struct sk_buff *skb;
320
321 unmap_q = rcb->unmap_q;
322 while (BNA_QE_IN_USE_CNT(unmap_q, unmap_q->q_depth)) {
323 skb = unmap_q->unmap_array[unmap_q->consumer_index].skb;
324 BUG_ON(!(skb));
325 unmap_q->unmap_array[unmap_q->consumer_index].skb = NULL;
326 pci_unmap_single(bnad->pcidev, pci_unmap_addr(&unmap_q->
327 unmap_array[unmap_q->consumer_index],
328 dma_addr), rcb->rxq->buffer_size +
329 NET_IP_ALIGN, PCI_DMA_FROMDEVICE);
330 dev_kfree_skb(skb);
331 BNA_QE_INDX_ADD(unmap_q->consumer_index, 1, unmap_q->q_depth);
332 BNA_QE_INDX_ADD(rcb->consumer_index, 1, rcb->q_depth);
333 }
334
335 bnad_reset_rcb(bnad, rcb);
336}
337
338static void
339bnad_alloc_n_post_rxbufs(struct bnad *bnad, struct bna_rcb *rcb)
340{
341 u16 to_alloc, alloced, unmap_prod, wi_range;
342 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
343 struct bnad_skb_unmap *unmap_array;
344 struct bna_rxq_entry *rxent;
345 struct sk_buff *skb;
346 dma_addr_t dma_addr;
347
348 alloced = 0;
349 to_alloc =
350 BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth);
351
352 unmap_array = unmap_q->unmap_array;
353 unmap_prod = unmap_q->producer_index;
354
355 BNA_RXQ_QPGE_PTR_GET(unmap_prod, rcb->sw_qpt, rxent, wi_range);
356
357 while (to_alloc--) {
358 if (!wi_range) {
359 BNA_RXQ_QPGE_PTR_GET(unmap_prod, rcb->sw_qpt, rxent,
360 wi_range);
361 }
362 skb = alloc_skb(rcb->rxq->buffer_size + NET_IP_ALIGN,
363 GFP_ATOMIC);
364 if (unlikely(!skb)) {
365 BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed);
366 goto finishing;
367 }
368 skb->dev = bnad->netdev;
369 skb_reserve(skb, NET_IP_ALIGN);
370 unmap_array[unmap_prod].skb = skb;
371 dma_addr = pci_map_single(bnad->pcidev, skb->data,
372 rcb->rxq->buffer_size, PCI_DMA_FROMDEVICE);
373 pci_unmap_addr_set(&unmap_array[unmap_prod], dma_addr,
374 dma_addr);
375 BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr);
376 BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
377
378 rxent++;
379 wi_range--;
380 alloced++;
381 }
382
383finishing:
384 if (likely(alloced)) {
385 unmap_q->producer_index = unmap_prod;
386 rcb->producer_index = unmap_prod;
387 smp_mb();
388 bna_rxq_prod_indx_doorbell(rcb);
389 }
390}
391
392/*
393 * Locking is required in the enable path
394 * because it is called from a napi poll
395 * context, where the bna_lock is not held
396 * unlike the IRQ context.
397 */
398static void
399bnad_enable_txrx_irqs(struct bnad *bnad)
400{
401 struct bna_tcb *tcb;
402 struct bna_ccb *ccb;
403 int i, j;
404 unsigned long flags;
405
406 spin_lock_irqsave(&bnad->bna_lock, flags);
407 for (i = 0; i < bnad->num_tx; i++) {
408 for (j = 0; j < bnad->num_txq_per_tx; j++) {
409 tcb = bnad->tx_info[i].tcb[j];
410 bna_ib_coalescing_timer_set(tcb->i_dbell,
411 tcb->txq->ib->ib_config.coalescing_timeo);
412 bna_ib_ack(tcb->i_dbell, 0);
413 }
414 }
415
416 for (i = 0; i < bnad->num_rx; i++) {
417 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
418 ccb = bnad->rx_info[i].rx_ctrl[j].ccb;
419 bnad_enable_rx_irq_unsafe(ccb);
420 }
421 }
422 spin_unlock_irqrestore(&bnad->bna_lock, flags);
423}
424
425static inline void
426bnad_refill_rxq(struct bnad *bnad, struct bna_rcb *rcb)
427{
428 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
429
430 if (!test_and_set_bit(BNAD_RXQ_REFILL, &rcb->flags)) {
431 if (BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth)
432 >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT)
433 bnad_alloc_n_post_rxbufs(bnad, rcb);
434 smp_mb__before_clear_bit();
435 clear_bit(BNAD_RXQ_REFILL, &rcb->flags);
436 }
437}
438
439static u32
440bnad_poll_cq(struct bnad *bnad, struct bna_ccb *ccb, int budget)
441{
442 struct bna_cq_entry *cmpl, *next_cmpl;
443 struct bna_rcb *rcb = NULL;
444 unsigned int wi_range, packets = 0, wis = 0;
445 struct bnad_unmap_q *unmap_q;
446 struct sk_buff *skb;
447 u32 flags;
448 u32 qid0 = ccb->rcb[0]->rxq->rxq_id;
449 struct bna_pkt_rate *pkt_rt = &ccb->pkt_rate;
450
451 prefetch(bnad->netdev);
452 BNA_CQ_QPGE_PTR_GET(ccb->producer_index, ccb->sw_qpt, cmpl,
453 wi_range);
454 BUG_ON(!(wi_range <= ccb->q_depth));
455 while (cmpl->valid && packets < budget) {
456 packets++;
457 BNA_UPDATE_PKT_CNT(pkt_rt, ntohs(cmpl->length));
458
459 if (qid0 == cmpl->rxq_id)
460 rcb = ccb->rcb[0];
461 else
462 rcb = ccb->rcb[1];
463
464 unmap_q = rcb->unmap_q;
465
466 skb = unmap_q->unmap_array[unmap_q->consumer_index].skb;
467 BUG_ON(!(skb));
468 unmap_q->unmap_array[unmap_q->consumer_index].skb = NULL;
469 pci_unmap_single(bnad->pcidev,
470 pci_unmap_addr(&unmap_q->
471 unmap_array[unmap_q->
472 consumer_index],
473 dma_addr),
474 rcb->rxq->buffer_size,
475 PCI_DMA_FROMDEVICE);
476 BNA_QE_INDX_ADD(unmap_q->consumer_index, 1, unmap_q->q_depth);
477
478 /* Should be more efficient ? Performance ? */
479 BNA_QE_INDX_ADD(rcb->consumer_index, 1, rcb->q_depth);
480
481 wis++;
482 if (likely(--wi_range))
483 next_cmpl = cmpl + 1;
484 else {
485 BNA_QE_INDX_ADD(ccb->producer_index, wis, ccb->q_depth);
486 wis = 0;
487 BNA_CQ_QPGE_PTR_GET(ccb->producer_index, ccb->sw_qpt,
488 next_cmpl, wi_range);
489 BUG_ON(!(wi_range <= ccb->q_depth));
490 }
491 prefetch(next_cmpl);
492
493 flags = ntohl(cmpl->flags);
494 if (unlikely
495 (flags &
496 (BNA_CQ_EF_MAC_ERROR | BNA_CQ_EF_FCS_ERROR |
497 BNA_CQ_EF_TOO_LONG))) {
498 dev_kfree_skb_any(skb);
499 rcb->rxq->rx_packets_with_error++;
500 goto next;
501 }
502
503 skb_put(skb, ntohs(cmpl->length));
504 if (likely
505 (bnad->rx_csum &&
506 (((flags & BNA_CQ_EF_IPV4) &&
507 (flags & BNA_CQ_EF_L3_CKSUM_OK)) ||
508 (flags & BNA_CQ_EF_IPV6)) &&
509 (flags & (BNA_CQ_EF_TCP | BNA_CQ_EF_UDP)) &&
510 (flags & BNA_CQ_EF_L4_CKSUM_OK)))
511 skb->ip_summed = CHECKSUM_UNNECESSARY;
512 else
513 skb->ip_summed = CHECKSUM_NONE;
514
515 rcb->rxq->rx_packets++;
516 rcb->rxq->rx_bytes += skb->len;
517 skb->protocol = eth_type_trans(skb, bnad->netdev);
518
519 if (bnad->vlan_grp && (flags & BNA_CQ_EF_VLAN)) {
520 struct bnad_rx_ctrl *rx_ctrl =
521 (struct bnad_rx_ctrl *)ccb->ctrl;
522 if (skb->ip_summed == CHECKSUM_UNNECESSARY)
523 vlan_gro_receive(&rx_ctrl->napi, bnad->vlan_grp,
524 ntohs(cmpl->vlan_tag), skb);
525 else
526 vlan_hwaccel_receive_skb(skb,
527 bnad->vlan_grp,
528 ntohs(cmpl->vlan_tag));
529
530 } else { /* Not VLAN tagged/stripped */
531 struct bnad_rx_ctrl *rx_ctrl =
532 (struct bnad_rx_ctrl *)ccb->ctrl;
533 if (skb->ip_summed == CHECKSUM_UNNECESSARY)
534 napi_gro_receive(&rx_ctrl->napi, skb);
535 else
536 netif_receive_skb(skb);
537 }
538
539next:
540 cmpl->valid = 0;
541 cmpl = next_cmpl;
542 }
543
544 BNA_QE_INDX_ADD(ccb->producer_index, wis, ccb->q_depth);
545
546 if (likely(ccb)) {
547 bna_ib_ack(ccb->i_dbell, packets);
548 bnad_refill_rxq(bnad, ccb->rcb[0]);
549 if (ccb->rcb[1])
550 bnad_refill_rxq(bnad, ccb->rcb[1]);
551 } else
552 bna_ib_ack(ccb->i_dbell, 0);
553
554 return packets;
555}
556
557static void
558bnad_disable_rx_irq(struct bnad *bnad, struct bna_ccb *ccb)
559{
560 bna_ib_coalescing_timer_set(ccb->i_dbell, 0);
561 bna_ib_ack(ccb->i_dbell, 0);
562}
563
564static void
565bnad_enable_rx_irq(struct bnad *bnad, struct bna_ccb *ccb)
566{
567 spin_lock_irq(&bnad->bna_lock); /* Because of polling context */
568 bnad_enable_rx_irq_unsafe(ccb);
569 spin_unlock_irq(&bnad->bna_lock);
570}
571
572static void
573bnad_netif_rx_schedule_poll(struct bnad *bnad, struct bna_ccb *ccb)
574{
575 struct bnad_rx_ctrl *rx_ctrl = (struct bnad_rx_ctrl *)(ccb->ctrl);
576 if (likely(napi_schedule_prep((&rx_ctrl->napi)))) {
577 bnad_disable_rx_irq(bnad, ccb);
578 __napi_schedule((&rx_ctrl->napi));
579 }
580 BNAD_UPDATE_CTR(bnad, netif_rx_schedule);
581}
582
583/* MSIX Rx Path Handler */
584static irqreturn_t
585bnad_msix_rx(int irq, void *data)
586{
587 struct bna_ccb *ccb = (struct bna_ccb *)data;
588 struct bnad *bnad = ccb->bnad;
589
590 bnad_netif_rx_schedule_poll(bnad, ccb);
591
592 return IRQ_HANDLED;
593}
594
595/* Interrupt handlers */
596
597/* Mbox Interrupt Handlers */
598static irqreturn_t
599bnad_msix_mbox_handler(int irq, void *data)
600{
601 u32 intr_status;
602 unsigned long flags;
603 struct net_device *netdev = data;
604 struct bnad *bnad;
605
606 bnad = netdev_priv(netdev);
607
608 /* BNA_ISR_GET(bnad); Inc Ref count */
609 spin_lock_irqsave(&bnad->bna_lock, flags);
610
611 bna_intr_status_get(&bnad->bna, intr_status);
612
613 if (BNA_IS_MBOX_ERR_INTR(intr_status))
614 bna_mbox_handler(&bnad->bna, intr_status);
615
616 spin_unlock_irqrestore(&bnad->bna_lock, flags);
617
618 /* BNAD_ISR_PUT(bnad); Dec Ref count */
619 return IRQ_HANDLED;
620}
621
622static irqreturn_t
623bnad_isr(int irq, void *data)
624{
625 int i, j;
626 u32 intr_status;
627 unsigned long flags;
628 struct net_device *netdev = data;
629 struct bnad *bnad = netdev_priv(netdev);
630 struct bnad_rx_info *rx_info;
631 struct bnad_rx_ctrl *rx_ctrl;
632
633 spin_lock_irqsave(&bnad->bna_lock, flags);
634
635 bna_intr_status_get(&bnad->bna, intr_status);
636 if (!intr_status) {
637 spin_unlock_irqrestore(&bnad->bna_lock, flags);
638 return IRQ_NONE;
639 }
640
641 if (BNA_IS_MBOX_ERR_INTR(intr_status)) {
642 bna_mbox_handler(&bnad->bna, intr_status);
643 if (!BNA_IS_INTX_DATA_INTR(intr_status)) {
644 spin_unlock_irqrestore(&bnad->bna_lock, flags);
645 goto done;
646 }
647 }
648 spin_unlock_irqrestore(&bnad->bna_lock, flags);
649
650 /* Process data interrupts */
651 for (i = 0; i < bnad->num_rx; i++) {
652 rx_info = &bnad->rx_info[i];
653 if (!rx_info->rx)
654 continue;
655 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
656 rx_ctrl = &rx_info->rx_ctrl[j];
657 if (rx_ctrl->ccb)
658 bnad_netif_rx_schedule_poll(bnad,
659 rx_ctrl->ccb);
660 }
661 }
662done:
663 return IRQ_HANDLED;
664}
665
666/*
667 * Called in interrupt / callback context
668 * with bna_lock held, so cfg_flags access is OK
669 */
670static void
671bnad_enable_mbox_irq(struct bnad *bnad)
672{
673 int irq = BNAD_GET_MBOX_IRQ(bnad);
674
675 if (!(bnad->cfg_flags & BNAD_CF_MSIX))
676 return;
677
678 if (test_and_clear_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))
679 enable_irq(irq);
680 BNAD_UPDATE_CTR(bnad, mbox_intr_enabled);
681}
682
683/*
684 * Called with bnad->bna_lock held b'cos of
685 * bnad->cfg_flags access.
686 */
687void
688bnad_disable_mbox_irq(struct bnad *bnad)
689{
690 int irq = BNAD_GET_MBOX_IRQ(bnad);
691
692 if (!(bnad->cfg_flags & BNAD_CF_MSIX))
693 return;
694
695 if (!test_and_set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))
696 disable_irq_nosync(irq);
697 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
698}
699
700/* Control Path Handlers */
701
702/* Callbacks */
703void
704bnad_cb_device_enable_mbox_intr(struct bnad *bnad)
705{
706 bnad_enable_mbox_irq(bnad);
707}
708
709void
710bnad_cb_device_disable_mbox_intr(struct bnad *bnad)
711{
712 bnad_disable_mbox_irq(bnad);
713}
714
715void
716bnad_cb_device_enabled(struct bnad *bnad, enum bna_cb_status status)
717{
718 complete(&bnad->bnad_completions.ioc_comp);
719 bnad->bnad_completions.ioc_comp_status = status;
720}
721
722void
723bnad_cb_device_disabled(struct bnad *bnad, enum bna_cb_status status)
724{
725 complete(&bnad->bnad_completions.ioc_comp);
726 bnad->bnad_completions.ioc_comp_status = status;
727}
728
729static void
730bnad_cb_port_disabled(void *arg, enum bna_cb_status status)
731{
732 struct bnad *bnad = (struct bnad *)arg;
733
734 complete(&bnad->bnad_completions.port_comp);
735
736 netif_carrier_off(bnad->netdev);
737}
738
739void
740bnad_cb_port_link_status(struct bnad *bnad,
741 enum bna_link_status link_status)
742{
743 bool link_up = 0;
744
745 link_up = (link_status == BNA_LINK_UP) || (link_status == BNA_CEE_UP);
746
747 if (link_status == BNA_CEE_UP) {
748 set_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
749 BNAD_UPDATE_CTR(bnad, cee_up);
750 } else
751 clear_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
752
753 if (link_up) {
754 if (!netif_carrier_ok(bnad->netdev)) {
755 pr_warn("bna: %s link up\n",
756 bnad->netdev->name);
757 netif_carrier_on(bnad->netdev);
758 BNAD_UPDATE_CTR(bnad, link_toggle);
759 if (test_bit(BNAD_RF_TX_STARTED, &bnad->run_flags)) {
760 /* Force an immediate Transmit Schedule */
761 pr_info("bna: %s TX_STARTED\n",
762 bnad->netdev->name);
763 netif_wake_queue(bnad->netdev);
764 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
765 } else {
766 netif_stop_queue(bnad->netdev);
767 BNAD_UPDATE_CTR(bnad, netif_queue_stop);
768 }
769 }
770 } else {
771 if (netif_carrier_ok(bnad->netdev)) {
772 pr_warn("bna: %s link down\n",
773 bnad->netdev->name);
774 netif_carrier_off(bnad->netdev);
775 BNAD_UPDATE_CTR(bnad, link_toggle);
776 }
777 }
778}
779
780static void
781bnad_cb_tx_disabled(void *arg, struct bna_tx *tx,
782 enum bna_cb_status status)
783{
784 struct bnad *bnad = (struct bnad *)arg;
785
786 complete(&bnad->bnad_completions.tx_comp);
787}
788
789static void
790bnad_cb_tcb_setup(struct bnad *bnad, struct bna_tcb *tcb)
791{
792 struct bnad_tx_info *tx_info =
793 (struct bnad_tx_info *)tcb->txq->tx->priv;
794 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
795
796 tx_info->tcb[tcb->id] = tcb;
797 unmap_q->producer_index = 0;
798 unmap_q->consumer_index = 0;
799 unmap_q->q_depth = BNAD_TX_UNMAPQ_DEPTH;
800}
801
802static void
803bnad_cb_tcb_destroy(struct bnad *bnad, struct bna_tcb *tcb)
804{
805 struct bnad_tx_info *tx_info =
806 (struct bnad_tx_info *)tcb->txq->tx->priv;
807
808 tx_info->tcb[tcb->id] = NULL;
809}
810
811static void
812bnad_cb_rcb_setup(struct bnad *bnad, struct bna_rcb *rcb)
813{
814 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
815
816 unmap_q->producer_index = 0;
817 unmap_q->consumer_index = 0;
818 unmap_q->q_depth = BNAD_RX_UNMAPQ_DEPTH;
819}
820
821static void
822bnad_cb_ccb_setup(struct bnad *bnad, struct bna_ccb *ccb)
823{
824 struct bnad_rx_info *rx_info =
825 (struct bnad_rx_info *)ccb->cq->rx->priv;
826
827 rx_info->rx_ctrl[ccb->id].ccb = ccb;
828 ccb->ctrl = &rx_info->rx_ctrl[ccb->id];
829}
830
831static void
832bnad_cb_ccb_destroy(struct bnad *bnad, struct bna_ccb *ccb)
833{
834 struct bnad_rx_info *rx_info =
835 (struct bnad_rx_info *)ccb->cq->rx->priv;
836
837 rx_info->rx_ctrl[ccb->id].ccb = NULL;
838}
839
840static void
841bnad_cb_tx_stall(struct bnad *bnad, struct bna_tcb *tcb)
842{
843 struct bnad_tx_info *tx_info =
844 (struct bnad_tx_info *)tcb->txq->tx->priv;
845
846 if (tx_info != &bnad->tx_info[0])
847 return;
848
849 clear_bit(BNAD_RF_TX_STARTED, &bnad->run_flags);
850 netif_stop_queue(bnad->netdev);
851 pr_info("bna: %s TX_STOPPED\n", bnad->netdev->name);
852}
853
854static void
855bnad_cb_tx_resume(struct bnad *bnad, struct bna_tcb *tcb)
856{
857 if (test_and_set_bit(BNAD_RF_TX_STARTED, &bnad->run_flags))
858 return;
859
860 if (netif_carrier_ok(bnad->netdev)) {
861 pr_info("bna: %s TX_STARTED\n", bnad->netdev->name);
862 netif_wake_queue(bnad->netdev);
863 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
864 }
865}
866
867static void
868bnad_cb_tx_cleanup(struct bnad *bnad, struct bna_tcb *tcb)
869{
870 struct bnad_unmap_q *unmap_q = tcb->unmap_q;
871
872 if (!tcb || (!tcb->unmap_q))
873 return;
874
875 if (!unmap_q->unmap_array)
876 return;
877
878 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
879 return;
880
881 bnad_free_all_txbufs(bnad, tcb);
882
883 unmap_q->producer_index = 0;
884 unmap_q->consumer_index = 0;
885
886 smp_mb__before_clear_bit();
887 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
888}
889
890static void
891bnad_cb_rx_cleanup(struct bnad *bnad,
892 struct bna_ccb *ccb)
893{
894 bnad_cq_cmpl_init(bnad, ccb);
895
896 bnad_free_rxbufs(bnad, ccb->rcb[0]);
897 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags);
898
899 if (ccb->rcb[1]) {
900 bnad_free_rxbufs(bnad, ccb->rcb[1]);
901 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[1]->flags);
902 }
903}
904
905static void
906bnad_cb_rx_post(struct bnad *bnad, struct bna_rcb *rcb)
907{
908 struct bnad_unmap_q *unmap_q = rcb->unmap_q;
909
910 set_bit(BNAD_RXQ_STARTED, &rcb->flags);
911
912 /* Now allocate & post buffers for this RCB */
913 /* !!Allocation in callback context */
914 if (!test_and_set_bit(BNAD_RXQ_REFILL, &rcb->flags)) {
915 if (BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth)
916 >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT)
917 bnad_alloc_n_post_rxbufs(bnad, rcb);
918 smp_mb__before_clear_bit();
919 clear_bit(BNAD_RXQ_REFILL, &rcb->flags);
920 }
921}
922
923static void
924bnad_cb_rx_disabled(void *arg, struct bna_rx *rx,
925 enum bna_cb_status status)
926{
927 struct bnad *bnad = (struct bnad *)arg;
928
929 complete(&bnad->bnad_completions.rx_comp);
930}
931
932static void
933bnad_cb_rx_mcast_add(struct bnad *bnad, struct bna_rx *rx,
934 enum bna_cb_status status)
935{
936 bnad->bnad_completions.mcast_comp_status = status;
937 complete(&bnad->bnad_completions.mcast_comp);
938}
939
940void
941bnad_cb_stats_get(struct bnad *bnad, enum bna_cb_status status,
942 struct bna_stats *stats)
943{
944 if (status == BNA_CB_SUCCESS)
945 BNAD_UPDATE_CTR(bnad, hw_stats_updates);
946
947 if (!netif_running(bnad->netdev) ||
948 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
949 return;
950
951 mod_timer(&bnad->stats_timer,
952 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
953}
954
955void
956bnad_cb_stats_clr(struct bnad *bnad)
957{
958}
959
960/* Resource allocation, free functions */
961
962static void
963bnad_mem_free(struct bnad *bnad,
964 struct bna_mem_info *mem_info)
965{
966 int i;
967 dma_addr_t dma_pa;
968
969 if (mem_info->mdl == NULL)
970 return;
971
972 for (i = 0; i < mem_info->num; i++) {
973 if (mem_info->mdl[i].kva != NULL) {
974 if (mem_info->mem_type == BNA_MEM_T_DMA) {
975 BNA_GET_DMA_ADDR(&(mem_info->mdl[i].dma),
976 dma_pa);
977 pci_free_consistent(bnad->pcidev,
978 mem_info->mdl[i].len,
979 mem_info->mdl[i].kva, dma_pa);
980 } else
981 kfree(mem_info->mdl[i].kva);
982 }
983 }
984 kfree(mem_info->mdl);
985 mem_info->mdl = NULL;
986}
987
988static int
989bnad_mem_alloc(struct bnad *bnad,
990 struct bna_mem_info *mem_info)
991{
992 int i;
993 dma_addr_t dma_pa;
994
995 if ((mem_info->num == 0) || (mem_info->len == 0)) {
996 mem_info->mdl = NULL;
997 return 0;
998 }
999
1000 mem_info->mdl = kcalloc(mem_info->num, sizeof(struct bna_mem_descr),
1001 GFP_KERNEL);
1002 if (mem_info->mdl == NULL)
1003 return -ENOMEM;
1004
1005 if (mem_info->mem_type == BNA_MEM_T_DMA) {
1006 for (i = 0; i < mem_info->num; i++) {
1007 mem_info->mdl[i].len = mem_info->len;
1008 mem_info->mdl[i].kva =
1009 pci_alloc_consistent(bnad->pcidev,
1010 mem_info->len, &dma_pa);
1011
1012 if (mem_info->mdl[i].kva == NULL)
1013 goto err_return;
1014
1015 BNA_SET_DMA_ADDR(dma_pa,
1016 &(mem_info->mdl[i].dma));
1017 }
1018 } else {
1019 for (i = 0; i < mem_info->num; i++) {
1020 mem_info->mdl[i].len = mem_info->len;
1021 mem_info->mdl[i].kva = kzalloc(mem_info->len,
1022 GFP_KERNEL);
1023 if (mem_info->mdl[i].kva == NULL)
1024 goto err_return;
1025 }
1026 }
1027
1028 return 0;
1029
1030err_return:
1031 bnad_mem_free(bnad, mem_info);
1032 return -ENOMEM;
1033}
1034
1035/* Free IRQ for Mailbox */
1036static void
1037bnad_mbox_irq_free(struct bnad *bnad,
1038 struct bna_intr_info *intr_info)
1039{
1040 int irq;
1041 unsigned long flags;
1042
1043 if (intr_info->idl == NULL)
1044 return;
1045
1046 spin_lock_irqsave(&bnad->bna_lock, flags);
1047
1048 bnad_disable_mbox_irq(bnad);
1049
1050 irq = BNAD_GET_MBOX_IRQ(bnad);
1051 free_irq(irq, bnad->netdev);
1052
1053 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1054
1055 kfree(intr_info->idl);
1056}
1057
1058/*
1059 * Allocates IRQ for Mailbox, but keep it disabled
1060 * This will be enabled once we get the mbox enable callback
1061 * from bna
1062 */
1063static int
1064bnad_mbox_irq_alloc(struct bnad *bnad,
1065 struct bna_intr_info *intr_info)
1066{
1067 int err;
1068 unsigned long flags;
1069 u32 irq;
1070 irq_handler_t irq_handler;
1071
1072 /* Mbox should use only 1 vector */
1073
1074 intr_info->idl = kzalloc(sizeof(*(intr_info->idl)), GFP_KERNEL);
1075 if (!intr_info->idl)
1076 return -ENOMEM;
1077
1078 spin_lock_irqsave(&bnad->bna_lock, flags);
1079 if (bnad->cfg_flags & BNAD_CF_MSIX) {
1080 irq_handler = (irq_handler_t)bnad_msix_mbox_handler;
1081 irq = bnad->msix_table[bnad->msix_num - 1].vector;
1082 flags = 0;
1083 intr_info->intr_type = BNA_INTR_T_MSIX;
1084 intr_info->idl[0].vector = bnad->msix_num - 1;
1085 } else {
1086 irq_handler = (irq_handler_t)bnad_isr;
1087 irq = bnad->pcidev->irq;
1088 flags = IRQF_SHARED;
1089 intr_info->intr_type = BNA_INTR_T_INTX;
1090 /* intr_info->idl.vector = 0 ? */
1091 }
1092 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1093
1094 sprintf(bnad->mbox_irq_name, "%s", BNAD_NAME);
1095
1096 err = request_irq(irq, irq_handler, flags,
1097 bnad->mbox_irq_name, bnad->netdev);
1098 if (err) {
1099 kfree(intr_info->idl);
1100 intr_info->idl = NULL;
1101 return err;
1102 }
1103
1104 spin_lock_irqsave(&bnad->bna_lock, flags);
1105 bnad_disable_mbox_irq(bnad);
1106 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1107 return 0;
1108}
1109
1110static void
1111bnad_txrx_irq_free(struct bnad *bnad, struct bna_intr_info *intr_info)
1112{
1113 kfree(intr_info->idl);
1114 intr_info->idl = NULL;
1115}
1116
1117/* Allocates Interrupt Descriptor List for MSIX/INT-X vectors */
1118static int
1119bnad_txrx_irq_alloc(struct bnad *bnad, enum bnad_intr_source src,
1120 uint txrx_id, struct bna_intr_info *intr_info)
1121{
1122 int i, vector_start = 0;
1123 u32 cfg_flags;
1124 unsigned long flags;
1125
1126 spin_lock_irqsave(&bnad->bna_lock, flags);
1127 cfg_flags = bnad->cfg_flags;
1128 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1129
1130 if (cfg_flags & BNAD_CF_MSIX) {
1131 intr_info->intr_type = BNA_INTR_T_MSIX;
1132 intr_info->idl = kcalloc(intr_info->num,
1133 sizeof(struct bna_intr_descr),
1134 GFP_KERNEL);
1135 if (!intr_info->idl)
1136 return -ENOMEM;
1137
1138 switch (src) {
1139 case BNAD_INTR_TX:
1140 vector_start = txrx_id;
1141 break;
1142
1143 case BNAD_INTR_RX:
1144 vector_start = bnad->num_tx * bnad->num_txq_per_tx +
1145 txrx_id;
1146 break;
1147
1148 default:
1149 BUG();
1150 }
1151
1152 for (i = 0; i < intr_info->num; i++)
1153 intr_info->idl[i].vector = vector_start + i;
1154 } else {
1155 intr_info->intr_type = BNA_INTR_T_INTX;
1156 intr_info->num = 1;
1157 intr_info->idl = kcalloc(intr_info->num,
1158 sizeof(struct bna_intr_descr),
1159 GFP_KERNEL);
1160 if (!intr_info->idl)
1161 return -ENOMEM;
1162
1163 switch (src) {
1164 case BNAD_INTR_TX:
1165 intr_info->idl[0].vector = 0x1; /* Bit mask : Tx IB */
1166 break;
1167
1168 case BNAD_INTR_RX:
1169 intr_info->idl[0].vector = 0x2; /* Bit mask : Rx IB */
1170 break;
1171 }
1172 }
1173 return 0;
1174}
1175
1176/**
1177 * NOTE: Should be called for MSIX only
1178 * Unregisters Tx MSIX vector(s) from the kernel
1179 */
1180static void
1181bnad_tx_msix_unregister(struct bnad *bnad, struct bnad_tx_info *tx_info,
1182 int num_txqs)
1183{
1184 int i;
1185 int vector_num;
1186
1187 for (i = 0; i < num_txqs; i++) {
1188 if (tx_info->tcb[i] == NULL)
1189 continue;
1190
1191 vector_num = tx_info->tcb[i]->intr_vector;
1192 free_irq(bnad->msix_table[vector_num].vector, tx_info->tcb[i]);
1193 }
1194}
1195
1196/**
1197 * NOTE: Should be called for MSIX only
1198 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1199 */
1200static int
1201bnad_tx_msix_register(struct bnad *bnad, struct bnad_tx_info *tx_info,
1202 uint tx_id, int num_txqs)
1203{
1204 int i;
1205 int err;
1206 int vector_num;
1207
1208 for (i = 0; i < num_txqs; i++) {
1209 vector_num = tx_info->tcb[i]->intr_vector;
1210 sprintf(tx_info->tcb[i]->name, "%s TXQ %d", bnad->netdev->name,
1211 tx_id + tx_info->tcb[i]->id);
1212 err = request_irq(bnad->msix_table[vector_num].vector,
1213 (irq_handler_t)bnad_msix_tx, 0,
1214 tx_info->tcb[i]->name,
1215 tx_info->tcb[i]);
1216 if (err)
1217 goto err_return;
1218 }
1219
1220 return 0;
1221
1222err_return:
1223 if (i > 0)
1224 bnad_tx_msix_unregister(bnad, tx_info, (i - 1));
1225 return -1;
1226}
1227
1228/**
1229 * NOTE: Should be called for MSIX only
1230 * Unregisters Rx MSIX vector(s) from the kernel
1231 */
1232static void
1233bnad_rx_msix_unregister(struct bnad *bnad, struct bnad_rx_info *rx_info,
1234 int num_rxps)
1235{
1236 int i;
1237 int vector_num;
1238
1239 for (i = 0; i < num_rxps; i++) {
1240 if (rx_info->rx_ctrl[i].ccb == NULL)
1241 continue;
1242
1243 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
1244 free_irq(bnad->msix_table[vector_num].vector,
1245 rx_info->rx_ctrl[i].ccb);
1246 }
1247}
1248
1249/**
1250 * NOTE: Should be called for MSIX only
1251 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1252 */
1253static int
1254bnad_rx_msix_register(struct bnad *bnad, struct bnad_rx_info *rx_info,
1255 uint rx_id, int num_rxps)
1256{
1257 int i;
1258 int err;
1259 int vector_num;
1260
1261 for (i = 0; i < num_rxps; i++) {
1262 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
1263 sprintf(rx_info->rx_ctrl[i].ccb->name, "%s CQ %d",
1264 bnad->netdev->name,
1265 rx_id + rx_info->rx_ctrl[i].ccb->id);
1266 err = request_irq(bnad->msix_table[vector_num].vector,
1267 (irq_handler_t)bnad_msix_rx, 0,
1268 rx_info->rx_ctrl[i].ccb->name,
1269 rx_info->rx_ctrl[i].ccb);
1270 if (err)
1271 goto err_return;
1272 }
1273
1274 return 0;
1275
1276err_return:
1277 if (i > 0)
1278 bnad_rx_msix_unregister(bnad, rx_info, (i - 1));
1279 return -1;
1280}
1281
1282/* Free Tx object Resources */
1283static void
1284bnad_tx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
1285{
1286 int i;
1287
1288 for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
1289 if (res_info[i].res_type == BNA_RES_T_MEM)
1290 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
1291 else if (res_info[i].res_type == BNA_RES_T_INTR)
1292 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
1293 }
1294}
1295
1296/* Allocates memory and interrupt resources for Tx object */
1297static int
1298bnad_tx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
1299 uint tx_id)
1300{
1301 int i, err = 0;
1302
1303 for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
1304 if (res_info[i].res_type == BNA_RES_T_MEM)
1305 err = bnad_mem_alloc(bnad,
1306 &res_info[i].res_u.mem_info);
1307 else if (res_info[i].res_type == BNA_RES_T_INTR)
1308 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_TX, tx_id,
1309 &res_info[i].res_u.intr_info);
1310 if (err)
1311 goto err_return;
1312 }
1313 return 0;
1314
1315err_return:
1316 bnad_tx_res_free(bnad, res_info);
1317 return err;
1318}
1319
1320/* Free Rx object Resources */
1321static void
1322bnad_rx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
1323{
1324 int i;
1325
1326 for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
1327 if (res_info[i].res_type == BNA_RES_T_MEM)
1328 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
1329 else if (res_info[i].res_type == BNA_RES_T_INTR)
1330 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
1331 }
1332}
1333
1334/* Allocates memory and interrupt resources for Rx object */
1335static int
1336bnad_rx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
1337 uint rx_id)
1338{
1339 int i, err = 0;
1340
1341 /* All memory needs to be allocated before setup_ccbs */
1342 for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
1343 if (res_info[i].res_type == BNA_RES_T_MEM)
1344 err = bnad_mem_alloc(bnad,
1345 &res_info[i].res_u.mem_info);
1346 else if (res_info[i].res_type == BNA_RES_T_INTR)
1347 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_RX, rx_id,
1348 &res_info[i].res_u.intr_info);
1349 if (err)
1350 goto err_return;
1351 }
1352 return 0;
1353
1354err_return:
1355 bnad_rx_res_free(bnad, res_info);
1356 return err;
1357}
1358
1359/* Timer callbacks */
1360/* a) IOC timer */
1361static void
1362bnad_ioc_timeout(unsigned long data)
1363{
1364 struct bnad *bnad = (struct bnad *)data;
1365 unsigned long flags;
1366
1367 spin_lock_irqsave(&bnad->bna_lock, flags);
1368 bfa_ioc_timeout((void *) &bnad->bna.device.ioc);
1369 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1370}
1371
1372static void
1373bnad_ioc_hb_check(unsigned long data)
1374{
1375 struct bnad *bnad = (struct bnad *)data;
1376 unsigned long flags;
1377
1378 spin_lock_irqsave(&bnad->bna_lock, flags);
1379 bfa_ioc_hb_check((void *) &bnad->bna.device.ioc);
1380 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1381}
1382
1383static void
1384bnad_ioc_sem_timeout(unsigned long data)
1385{
1386 struct bnad *bnad = (struct bnad *)data;
1387 unsigned long flags;
1388
1389 spin_lock_irqsave(&bnad->bna_lock, flags);
1390 bfa_ioc_sem_timeout((void *) &bnad->bna.device.ioc);
1391 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1392}
1393
1394/*
1395 * All timer routines use bnad->bna_lock to protect against
1396 * the following race, which may occur in case of no locking:
1397 * Time CPU m CPU n
1398 * 0 1 = test_bit
1399 * 1 clear_bit
1400 * 2 del_timer_sync
1401 * 3 mod_timer
1402 */
1403
1404/* b) Dynamic Interrupt Moderation Timer */
1405static void
1406bnad_dim_timeout(unsigned long data)
1407{
1408 struct bnad *bnad = (struct bnad *)data;
1409 struct bnad_rx_info *rx_info;
1410 struct bnad_rx_ctrl *rx_ctrl;
1411 int i, j;
1412 unsigned long flags;
1413
1414 if (!netif_carrier_ok(bnad->netdev))
1415 return;
1416
1417 spin_lock_irqsave(&bnad->bna_lock, flags);
1418 for (i = 0; i < bnad->num_rx; i++) {
1419 rx_info = &bnad->rx_info[i];
1420 if (!rx_info->rx)
1421 continue;
1422 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
1423 rx_ctrl = &rx_info->rx_ctrl[j];
1424 if (!rx_ctrl->ccb)
1425 continue;
1426 bna_rx_dim_update(rx_ctrl->ccb);
1427 }
1428 }
1429
1430 /* Check for BNAD_CF_DIM_ENABLED, does not eleminate a race */
1431 if (test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags))
1432 mod_timer(&bnad->dim_timer,
1433 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
1434 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1435}
1436
1437/* c) Statistics Timer */
1438static void
1439bnad_stats_timeout(unsigned long data)
1440{
1441 struct bnad *bnad = (struct bnad *)data;
1442 unsigned long flags;
1443
1444 if (!netif_running(bnad->netdev) ||
1445 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1446 return;
1447
1448 spin_lock_irqsave(&bnad->bna_lock, flags);
1449 bna_stats_get(&bnad->bna);
1450 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1451}
1452
1453/*
1454 * Set up timer for DIM
1455 * Called with bnad->bna_lock held
1456 */
1457void
1458bnad_dim_timer_start(struct bnad *bnad)
1459{
1460 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED &&
1461 !test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) {
1462 setup_timer(&bnad->dim_timer, bnad_dim_timeout,
1463 (unsigned long)bnad);
1464 set_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
1465 mod_timer(&bnad->dim_timer,
1466 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
1467 }
1468}
1469
1470/*
1471 * Set up timer for statistics
1472 * Called with mutex_lock(&bnad->conf_mutex) held
1473 */
1474static void
1475bnad_stats_timer_start(struct bnad *bnad)
1476{
1477 unsigned long flags;
1478
1479 spin_lock_irqsave(&bnad->bna_lock, flags);
1480 if (!test_and_set_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) {
1481 setup_timer(&bnad->stats_timer, bnad_stats_timeout,
1482 (unsigned long)bnad);
1483 mod_timer(&bnad->stats_timer,
1484 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
1485 }
1486 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1487
1488}
1489
1490/*
1491 * Stops the stats timer
1492 * Called with mutex_lock(&bnad->conf_mutex) held
1493 */
1494static void
1495bnad_stats_timer_stop(struct bnad *bnad)
1496{
1497 int to_del = 0;
1498 unsigned long flags;
1499
1500 spin_lock_irqsave(&bnad->bna_lock, flags);
1501 if (test_and_clear_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1502 to_del = 1;
1503 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1504 if (to_del)
1505 del_timer_sync(&bnad->stats_timer);
1506}
1507
1508/* Utilities */
1509
1510static void
1511bnad_netdev_mc_list_get(struct net_device *netdev, u8 *mc_list)
1512{
1513 int i = 1; /* Index 0 has broadcast address */
1514 struct netdev_hw_addr *mc_addr;
1515
1516 netdev_for_each_mc_addr(mc_addr, netdev) {
1517 memcpy(&mc_list[i * ETH_ALEN], &mc_addr->addr[0],
1518 ETH_ALEN);
1519 i++;
1520 }
1521}
1522
1523static int
1524bnad_napi_poll_rx(struct napi_struct *napi, int budget)
1525{
1526 struct bnad_rx_ctrl *rx_ctrl =
1527 container_of(napi, struct bnad_rx_ctrl, napi);
1528 struct bna_ccb *ccb;
1529 struct bnad *bnad;
1530 int rcvd = 0;
1531
1532 ccb = rx_ctrl->ccb;
1533
1534 bnad = ccb->bnad;
1535
1536 if (!netif_carrier_ok(bnad->netdev))
1537 goto poll_exit;
1538
1539 rcvd = bnad_poll_cq(bnad, ccb, budget);
1540 if (rcvd == budget)
1541 return rcvd;
1542
1543poll_exit:
1544 napi_complete((napi));
1545
1546 BNAD_UPDATE_CTR(bnad, netif_rx_complete);
1547
1548 bnad_enable_rx_irq(bnad, ccb);
1549 return rcvd;
1550}
1551
1552static int
1553bnad_napi_poll_txrx(struct napi_struct *napi, int budget)
1554{
1555 struct bnad_rx_ctrl *rx_ctrl =
1556 container_of(napi, struct bnad_rx_ctrl, napi);
1557 struct bna_ccb *ccb;
1558 struct bnad *bnad;
1559 int rcvd = 0;
1560 int i, j;
1561
1562 ccb = rx_ctrl->ccb;
1563
1564 bnad = ccb->bnad;
1565
1566 if (!netif_carrier_ok(bnad->netdev))
1567 goto poll_exit;
1568
1569 /* Handle Tx Completions, if any */
1570 for (i = 0; i < bnad->num_tx; i++) {
1571 for (j = 0; j < bnad->num_txq_per_tx; j++)
1572 bnad_tx(bnad, bnad->tx_info[i].tcb[j]);
1573 }
1574
1575 /* Handle Rx Completions */
1576 rcvd = bnad_poll_cq(bnad, ccb, budget);
1577 if (rcvd == budget)
1578 return rcvd;
1579poll_exit:
1580 napi_complete((napi));
1581
1582 BNAD_UPDATE_CTR(bnad, netif_rx_complete);
1583
1584 bnad_enable_txrx_irqs(bnad);
1585 return rcvd;
1586}
1587
1588static void
1589bnad_napi_enable(struct bnad *bnad, u32 rx_id)
1590{
1591 int (*napi_poll) (struct napi_struct *, int);
1592 struct bnad_rx_ctrl *rx_ctrl;
1593 int i;
1594 unsigned long flags;
1595
1596 spin_lock_irqsave(&bnad->bna_lock, flags);
1597 if (bnad->cfg_flags & BNAD_CF_MSIX)
1598 napi_poll = bnad_napi_poll_rx;
1599 else
1600 napi_poll = bnad_napi_poll_txrx;
1601 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1602
1603 /* Initialize & enable NAPI */
1604 for (i = 0; i < bnad->num_rxp_per_rx; i++) {
1605 rx_ctrl = &bnad->rx_info[rx_id].rx_ctrl[i];
1606 netif_napi_add(bnad->netdev, &rx_ctrl->napi,
1607 napi_poll, 64);
1608 napi_enable(&rx_ctrl->napi);
1609 }
1610}
1611
1612static void
1613bnad_napi_disable(struct bnad *bnad, u32 rx_id)
1614{
1615 int i;
1616
1617 /* First disable and then clean up */
1618 for (i = 0; i < bnad->num_rxp_per_rx; i++) {
1619 napi_disable(&bnad->rx_info[rx_id].rx_ctrl[i].napi);
1620 netif_napi_del(&bnad->rx_info[rx_id].rx_ctrl[i].napi);
1621 }
1622}
1623
1624/* Should be held with conf_lock held */
1625void
1626bnad_cleanup_tx(struct bnad *bnad, uint tx_id)
1627{
1628 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
1629 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
1630 unsigned long flags;
1631
1632 if (!tx_info->tx)
1633 return;
1634
1635 init_completion(&bnad->bnad_completions.tx_comp);
1636 spin_lock_irqsave(&bnad->bna_lock, flags);
1637 bna_tx_disable(tx_info->tx, BNA_HARD_CLEANUP, bnad_cb_tx_disabled);
1638 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1639 wait_for_completion(&bnad->bnad_completions.tx_comp);
1640
1641 if (tx_info->tcb[0]->intr_type == BNA_INTR_T_MSIX)
1642 bnad_tx_msix_unregister(bnad, tx_info,
1643 bnad->num_txq_per_tx);
1644
1645 spin_lock_irqsave(&bnad->bna_lock, flags);
1646 bna_tx_destroy(tx_info->tx);
1647 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1648
1649 tx_info->tx = NULL;
1650
1651 if (0 == tx_id)
1652 tasklet_kill(&bnad->tx_free_tasklet);
1653
1654 bnad_tx_res_free(bnad, res_info);
1655}
1656
1657/* Should be held with conf_lock held */
1658int
1659bnad_setup_tx(struct bnad *bnad, uint tx_id)
1660{
1661 int err;
1662 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
1663 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
1664 struct bna_intr_info *intr_info =
1665 &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info;
1666 struct bna_tx_config *tx_config = &bnad->tx_config[tx_id];
1667 struct bna_tx_event_cbfn tx_cbfn;
1668 struct bna_tx *tx;
1669 unsigned long flags;
1670
1671 /* Initialize the Tx object configuration */
1672 tx_config->num_txq = bnad->num_txq_per_tx;
1673 tx_config->txq_depth = bnad->txq_depth;
1674 tx_config->tx_type = BNA_TX_T_REGULAR;
1675
1676 /* Initialize the tx event handlers */
1677 tx_cbfn.tcb_setup_cbfn = bnad_cb_tcb_setup;
1678 tx_cbfn.tcb_destroy_cbfn = bnad_cb_tcb_destroy;
1679 tx_cbfn.tx_stall_cbfn = bnad_cb_tx_stall;
1680 tx_cbfn.tx_resume_cbfn = bnad_cb_tx_resume;
1681 tx_cbfn.tx_cleanup_cbfn = bnad_cb_tx_cleanup;
1682
1683 /* Get BNA's resource requirement for one tx object */
1684 spin_lock_irqsave(&bnad->bna_lock, flags);
1685 bna_tx_res_req(bnad->num_txq_per_tx,
1686 bnad->txq_depth, res_info);
1687 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1688
1689 /* Fill Unmap Q memory requirements */
1690 BNAD_FILL_UNMAPQ_MEM_REQ(
1691 &res_info[BNA_TX_RES_MEM_T_UNMAPQ],
1692 bnad->num_txq_per_tx,
1693 BNAD_TX_UNMAPQ_DEPTH);
1694
1695 /* Allocate resources */
1696 err = bnad_tx_res_alloc(bnad, res_info, tx_id);
1697 if (err)
1698 return err;
1699
1700 /* Ask BNA to create one Tx object, supplying required resources */
1701 spin_lock_irqsave(&bnad->bna_lock, flags);
1702 tx = bna_tx_create(&bnad->bna, bnad, tx_config, &tx_cbfn, res_info,
1703 tx_info);
1704 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1705 if (!tx)
1706 goto err_return;
1707 tx_info->tx = tx;
1708
1709 /* Register ISR for the Tx object */
1710 if (intr_info->intr_type == BNA_INTR_T_MSIX) {
1711 err = bnad_tx_msix_register(bnad, tx_info,
1712 tx_id, bnad->num_txq_per_tx);
1713 if (err)
1714 goto err_return;
1715 }
1716
1717 spin_lock_irqsave(&bnad->bna_lock, flags);
1718 bna_tx_enable(tx);
1719 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1720
1721 return 0;
1722
1723err_return:
1724 bnad_tx_res_free(bnad, res_info);
1725 return err;
1726}
1727
1728/* Setup the rx config for bna_rx_create */
1729/* bnad decides the configuration */
1730static void
1731bnad_init_rx_config(struct bnad *bnad, struct bna_rx_config *rx_config)
1732{
1733 rx_config->rx_type = BNA_RX_T_REGULAR;
1734 rx_config->num_paths = bnad->num_rxp_per_rx;
1735
1736 if (bnad->num_rxp_per_rx > 1) {
1737 rx_config->rss_status = BNA_STATUS_T_ENABLED;
1738 rx_config->rss_config.hash_type =
1739 (BFI_RSS_T_V4_TCP |
1740 BFI_RSS_T_V6_TCP |
1741 BFI_RSS_T_V4_IP |
1742 BFI_RSS_T_V6_IP);
1743 rx_config->rss_config.hash_mask =
1744 bnad->num_rxp_per_rx - 1;
1745 get_random_bytes(rx_config->rss_config.toeplitz_hash_key,
1746 sizeof(rx_config->rss_config.toeplitz_hash_key));
1747 } else {
1748 rx_config->rss_status = BNA_STATUS_T_DISABLED;
1749 memset(&rx_config->rss_config, 0,
1750 sizeof(rx_config->rss_config));
1751 }
1752 rx_config->rxp_type = BNA_RXP_SLR;
1753 rx_config->q_depth = bnad->rxq_depth;
1754
1755 rx_config->small_buff_size = BFI_SMALL_RXBUF_SIZE;
1756
1757 rx_config->vlan_strip_status = BNA_STATUS_T_ENABLED;
1758}
1759
1760/* Called with mutex_lock(&bnad->conf_mutex) held */
1761void
1762bnad_cleanup_rx(struct bnad *bnad, uint rx_id)
1763{
1764 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
1765 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
1766 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
1767 unsigned long flags;
1768 int dim_timer_del = 0;
1769
1770 if (!rx_info->rx)
1771 return;
1772
1773 if (0 == rx_id) {
1774 spin_lock_irqsave(&bnad->bna_lock, flags);
1775 dim_timer_del = bnad_dim_timer_running(bnad);
1776 if (dim_timer_del)
1777 clear_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
1778 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1779 if (dim_timer_del)
1780 del_timer_sync(&bnad->dim_timer);
1781 }
1782
1783 bnad_napi_disable(bnad, rx_id);
1784
1785 init_completion(&bnad->bnad_completions.rx_comp);
1786 spin_lock_irqsave(&bnad->bna_lock, flags);
1787 bna_rx_disable(rx_info->rx, BNA_HARD_CLEANUP, bnad_cb_rx_disabled);
1788 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1789 wait_for_completion(&bnad->bnad_completions.rx_comp);
1790
1791 if (rx_info->rx_ctrl[0].ccb->intr_type == BNA_INTR_T_MSIX)
1792 bnad_rx_msix_unregister(bnad, rx_info, rx_config->num_paths);
1793
1794 spin_lock_irqsave(&bnad->bna_lock, flags);
1795 bna_rx_destroy(rx_info->rx);
1796 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1797
1798 rx_info->rx = NULL;
1799
1800 bnad_rx_res_free(bnad, res_info);
1801}
1802
1803/* Called with mutex_lock(&bnad->conf_mutex) held */
1804int
1805bnad_setup_rx(struct bnad *bnad, uint rx_id)
1806{
1807 int err;
1808 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
1809 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
1810 struct bna_intr_info *intr_info =
1811 &res_info[BNA_RX_RES_T_INTR].res_u.intr_info;
1812 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
1813 struct bna_rx_event_cbfn rx_cbfn;
1814 struct bna_rx *rx;
1815 unsigned long flags;
1816
1817 /* Initialize the Rx object configuration */
1818 bnad_init_rx_config(bnad, rx_config);
1819
1820 /* Initialize the Rx event handlers */
1821 rx_cbfn.rcb_setup_cbfn = bnad_cb_rcb_setup;
1822 rx_cbfn.rcb_destroy_cbfn = NULL;
1823 rx_cbfn.ccb_setup_cbfn = bnad_cb_ccb_setup;
1824 rx_cbfn.ccb_destroy_cbfn = bnad_cb_ccb_destroy;
1825 rx_cbfn.rx_cleanup_cbfn = bnad_cb_rx_cleanup;
1826 rx_cbfn.rx_post_cbfn = bnad_cb_rx_post;
1827
1828 /* Get BNA's resource requirement for one Rx object */
1829 spin_lock_irqsave(&bnad->bna_lock, flags);
1830 bna_rx_res_req(rx_config, res_info);
1831 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1832
1833 /* Fill Unmap Q memory requirements */
1834 BNAD_FILL_UNMAPQ_MEM_REQ(
1835 &res_info[BNA_RX_RES_MEM_T_UNMAPQ],
1836 rx_config->num_paths +
1837 ((rx_config->rxp_type == BNA_RXP_SINGLE) ? 0 :
1838 rx_config->num_paths), BNAD_RX_UNMAPQ_DEPTH);
1839
1840 /* Allocate resource */
1841 err = bnad_rx_res_alloc(bnad, res_info, rx_id);
1842 if (err)
1843 return err;
1844
1845 /* Ask BNA to create one Rx object, supplying required resources */
1846 spin_lock_irqsave(&bnad->bna_lock, flags);
1847 rx = bna_rx_create(&bnad->bna, bnad, rx_config, &rx_cbfn, res_info,
1848 rx_info);
1849 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1850 if (!rx)
1851 goto err_return;
1852 rx_info->rx = rx;
1853
1854 /* Register ISR for the Rx object */
1855 if (intr_info->intr_type == BNA_INTR_T_MSIX) {
1856 err = bnad_rx_msix_register(bnad, rx_info, rx_id,
1857 rx_config->num_paths);
1858 if (err)
1859 goto err_return;
1860 }
1861
1862 /* Enable NAPI */
1863 bnad_napi_enable(bnad, rx_id);
1864
1865 spin_lock_irqsave(&bnad->bna_lock, flags);
1866 if (0 == rx_id) {
1867 /* Set up Dynamic Interrupt Moderation Vector */
1868 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED)
1869 bna_rx_dim_reconfig(&bnad->bna, bna_napi_dim_vector);
1870
1871 /* Enable VLAN filtering only on the default Rx */
1872 bna_rx_vlanfilter_enable(rx);
1873
1874 /* Start the DIM timer */
1875 bnad_dim_timer_start(bnad);
1876 }
1877
1878 bna_rx_enable(rx);
1879 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1880
1881 return 0;
1882
1883err_return:
1884 bnad_cleanup_rx(bnad, rx_id);
1885 return err;
1886}
1887
1888/* Called with conf_lock & bnad->bna_lock held */
1889void
1890bnad_tx_coalescing_timeo_set(struct bnad *bnad)
1891{
1892 struct bnad_tx_info *tx_info;
1893
1894 tx_info = &bnad->tx_info[0];
1895 if (!tx_info->tx)
1896 return;
1897
1898 bna_tx_coalescing_timeo_set(tx_info->tx, bnad->tx_coalescing_timeo);
1899}
1900
1901/* Called with conf_lock & bnad->bna_lock held */
1902void
1903bnad_rx_coalescing_timeo_set(struct bnad *bnad)
1904{
1905 struct bnad_rx_info *rx_info;
1906 int i;
1907
1908 for (i = 0; i < bnad->num_rx; i++) {
1909 rx_info = &bnad->rx_info[i];
1910 if (!rx_info->rx)
1911 continue;
1912 bna_rx_coalescing_timeo_set(rx_info->rx,
1913 bnad->rx_coalescing_timeo);
1914 }
1915}
1916
1917/*
1918 * Called with bnad->bna_lock held
1919 */
1920static int
1921bnad_mac_addr_set_locked(struct bnad *bnad, u8 *mac_addr)
1922{
1923 int ret;
1924
1925 if (!is_valid_ether_addr(mac_addr))
1926 return -EADDRNOTAVAIL;
1927
1928 /* If datapath is down, pretend everything went through */
1929 if (!bnad->rx_info[0].rx)
1930 return 0;
1931
1932 ret = bna_rx_ucast_set(bnad->rx_info[0].rx, mac_addr, NULL);
1933 if (ret != BNA_CB_SUCCESS)
1934 return -EADDRNOTAVAIL;
1935
1936 return 0;
1937}
1938
1939/* Should be called with conf_lock held */
1940static int
1941bnad_enable_default_bcast(struct bnad *bnad)
1942{
1943 struct bnad_rx_info *rx_info = &bnad->rx_info[0];
1944 int ret;
1945 unsigned long flags;
1946
1947 init_completion(&bnad->bnad_completions.mcast_comp);
1948
1949 spin_lock_irqsave(&bnad->bna_lock, flags);
1950 ret = bna_rx_mcast_add(rx_info->rx, (u8 *)bnad_bcast_addr,
1951 bnad_cb_rx_mcast_add);
1952 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1953
1954 if (ret == BNA_CB_SUCCESS)
1955 wait_for_completion(&bnad->bnad_completions.mcast_comp);
1956 else
1957 return -ENODEV;
1958
1959 if (bnad->bnad_completions.mcast_comp_status != BNA_CB_SUCCESS)
1960 return -ENODEV;
1961
1962 return 0;
1963}
1964
1965/* Statistics utilities */
1966void
1967bnad_netdev_qstats_fill(struct bnad *bnad)
1968{
1969 struct net_device_stats *net_stats = &bnad->net_stats;
1970 int i, j;
1971
1972 for (i = 0; i < bnad->num_rx; i++) {
1973 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
1974 if (bnad->rx_info[i].rx_ctrl[j].ccb) {
1975 net_stats->rx_packets += bnad->rx_info[i].
1976 rx_ctrl[j].ccb->rcb[0]->rxq->rx_packets;
1977 net_stats->rx_bytes += bnad->rx_info[i].
1978 rx_ctrl[j].ccb->rcb[0]->rxq->rx_bytes;
1979 if (bnad->rx_info[i].rx_ctrl[j].ccb->rcb[1] &&
1980 bnad->rx_info[i].rx_ctrl[j].ccb->
1981 rcb[1]->rxq) {
1982 net_stats->rx_packets +=
1983 bnad->rx_info[i].rx_ctrl[j].
1984 ccb->rcb[1]->rxq->rx_packets;
1985 net_stats->rx_bytes +=
1986 bnad->rx_info[i].rx_ctrl[j].
1987 ccb->rcb[1]->rxq->rx_bytes;
1988 }
1989 }
1990 }
1991 }
1992 for (i = 0; i < bnad->num_tx; i++) {
1993 for (j = 0; j < bnad->num_txq_per_tx; j++) {
1994 if (bnad->tx_info[i].tcb[j]) {
1995 net_stats->tx_packets +=
1996 bnad->tx_info[i].tcb[j]->txq->tx_packets;
1997 net_stats->tx_bytes +=
1998 bnad->tx_info[i].tcb[j]->txq->tx_bytes;
1999 }
2000 }
2001 }
2002}
2003
2004/*
2005 * Must be called with the bna_lock held.
2006 */
2007void
2008bnad_netdev_hwstats_fill(struct bnad *bnad)
2009{
2010 struct bfi_ll_stats_mac *mac_stats;
2011 struct net_device_stats *net_stats = &bnad->net_stats;
2012 u64 bmap;
2013 int i;
2014
2015 mac_stats = &bnad->stats.bna_stats->hw_stats->mac_stats;
2016 net_stats->rx_errors =
2017 mac_stats->rx_fcs_error + mac_stats->rx_alignment_error +
2018 mac_stats->rx_frame_length_error + mac_stats->rx_code_error +
2019 mac_stats->rx_undersize;
2020 net_stats->tx_errors = mac_stats->tx_fcs_error +
2021 mac_stats->tx_undersize;
2022 net_stats->rx_dropped = mac_stats->rx_drop;
2023 net_stats->tx_dropped = mac_stats->tx_drop;
2024 net_stats->multicast = mac_stats->rx_multicast;
2025 net_stats->collisions = mac_stats->tx_total_collision;
2026
2027 net_stats->rx_length_errors = mac_stats->rx_frame_length_error;
2028
2029 /* receive ring buffer overflow ?? */
2030
2031 net_stats->rx_crc_errors = mac_stats->rx_fcs_error;
2032 net_stats->rx_frame_errors = mac_stats->rx_alignment_error;
2033 /* recv'r fifo overrun */
2034 bmap = (u64)bnad->stats.bna_stats->rxf_bmap[0] |
2035 ((u64)bnad->stats.bna_stats->rxf_bmap[1] << 32);
2036 for (i = 0; bmap && (i < BFI_LL_RXF_ID_MAX); i++) {
2037 if (bmap & 1) {
2038 net_stats->rx_fifo_errors =
2039 bnad->stats.bna_stats->
2040 hw_stats->rxf_stats[i].frame_drops;
2041 break;
2042 }
2043 bmap >>= 1;
2044 }
2045}
2046
2047static void
2048bnad_mbox_irq_sync(struct bnad *bnad)
2049{
2050 u32 irq;
2051 unsigned long flags;
2052
2053 spin_lock_irqsave(&bnad->bna_lock, flags);
2054 if (bnad->cfg_flags & BNAD_CF_MSIX)
2055 irq = bnad->msix_table[bnad->msix_num - 1].vector;
2056 else
2057 irq = bnad->pcidev->irq;
2058 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2059
2060 synchronize_irq(irq);
2061}
2062
2063/* Utility used by bnad_start_xmit, for doing TSO */
2064static int
2065bnad_tso_prepare(struct bnad *bnad, struct sk_buff *skb)
2066{
2067 int err;
2068
2069 /* SKB_GSO_TCPV4 and SKB_GSO_TCPV6 is defined since 2.6.18. */
2070 BUG_ON(!(skb_shinfo(skb)->gso_type == SKB_GSO_TCPV4 ||
2071 skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6));
2072 if (skb_header_cloned(skb)) {
2073 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2074 if (err) {
2075 BNAD_UPDATE_CTR(bnad, tso_err);
2076 return err;
2077 }
2078 }
2079
2080 /*
2081 * For TSO, the TCP checksum field is seeded with pseudo-header sum
2082 * excluding the length field.
2083 */
2084 if (skb->protocol == htons(ETH_P_IP)) {
2085 struct iphdr *iph = ip_hdr(skb);
2086
2087 /* Do we really need these? */
2088 iph->tot_len = 0;
2089 iph->check = 0;
2090
2091 tcp_hdr(skb)->check =
2092 ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
2093 IPPROTO_TCP, 0);
2094 BNAD_UPDATE_CTR(bnad, tso4);
2095 } else {
2096 struct ipv6hdr *ipv6h = ipv6_hdr(skb);
2097
2098 BUG_ON(!(skb->protocol == htons(ETH_P_IPV6)));
2099 ipv6h->payload_len = 0;
2100 tcp_hdr(skb)->check =
2101 ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr, 0,
2102 IPPROTO_TCP, 0);
2103 BNAD_UPDATE_CTR(bnad, tso6);
2104 }
2105
2106 return 0;
2107}
2108
2109/*
2110 * Initialize Q numbers depending on Rx Paths
2111 * Called with bnad->bna_lock held, because of cfg_flags
2112 * access.
2113 */
2114static void
2115bnad_q_num_init(struct bnad *bnad)
2116{
2117 int rxps;
2118
2119 rxps = min((uint)num_online_cpus(),
2120 (uint)(BNAD_MAX_RXS * BNAD_MAX_RXPS_PER_RX));
2121
2122 if (!(bnad->cfg_flags & BNAD_CF_MSIX))
2123 rxps = 1; /* INTx */
2124
2125 bnad->num_rx = 1;
2126 bnad->num_tx = 1;
2127 bnad->num_rxp_per_rx = rxps;
2128 bnad->num_txq_per_tx = BNAD_TXQ_NUM;
2129}
2130
2131/*
2132 * Adjusts the Q numbers, given a number of msix vectors
2133 * Give preference to RSS as opposed to Tx priority Queues,
2134 * in such a case, just use 1 Tx Q
2135 * Called with bnad->bna_lock held b'cos of cfg_flags access
2136 */
2137static void
2138bnad_q_num_adjust(struct bnad *bnad, int msix_vectors)
2139{
2140 bnad->num_txq_per_tx = 1;
2141 if ((msix_vectors >= (bnad->num_tx * bnad->num_txq_per_tx) +
2142 bnad_rxqs_per_cq + BNAD_MAILBOX_MSIX_VECTORS) &&
2143 (bnad->cfg_flags & BNAD_CF_MSIX)) {
2144 bnad->num_rxp_per_rx = msix_vectors -
2145 (bnad->num_tx * bnad->num_txq_per_tx) -
2146 BNAD_MAILBOX_MSIX_VECTORS;
2147 } else
2148 bnad->num_rxp_per_rx = 1;
2149}
2150
2151static void
2152bnad_set_netdev_perm_addr(struct bnad *bnad)
2153{
2154 struct net_device *netdev = bnad->netdev;
2155
2156 memcpy(netdev->perm_addr, &bnad->perm_addr, netdev->addr_len);
2157 if (is_zero_ether_addr(netdev->dev_addr))
2158 memcpy(netdev->dev_addr, &bnad->perm_addr, netdev->addr_len);
2159}
2160
2161/* Enable / disable device */
2162static void
2163bnad_device_disable(struct bnad *bnad)
2164{
2165 unsigned long flags;
2166
2167 init_completion(&bnad->bnad_completions.ioc_comp);
2168
2169 spin_lock_irqsave(&bnad->bna_lock, flags);
2170 bna_device_disable(&bnad->bna.device, BNA_HARD_CLEANUP);
2171 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2172
2173 wait_for_completion(&bnad->bnad_completions.ioc_comp);
2174
2175}
2176
2177static int
2178bnad_device_enable(struct bnad *bnad)
2179{
2180 int err = 0;
2181 unsigned long flags;
2182
2183 init_completion(&bnad->bnad_completions.ioc_comp);
2184
2185 spin_lock_irqsave(&bnad->bna_lock, flags);
2186 bna_device_enable(&bnad->bna.device);
2187 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2188
2189 wait_for_completion(&bnad->bnad_completions.ioc_comp);
2190
2191 if (bnad->bnad_completions.ioc_comp_status)
2192 err = bnad->bnad_completions.ioc_comp_status;
2193
2194 return err;
2195}
2196
2197/* Free BNA resources */
2198static void
2199bnad_res_free(struct bnad *bnad)
2200{
2201 int i;
2202 struct bna_res_info *res_info = &bnad->res_info[0];
2203
2204 for (i = 0; i < BNA_RES_T_MAX; i++) {
2205 if (res_info[i].res_type == BNA_RES_T_MEM)
2206 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
2207 else
2208 bnad_mbox_irq_free(bnad, &res_info[i].res_u.intr_info);
2209 }
2210}
2211
2212/* Allocates memory and interrupt resources for BNA */
2213static int
2214bnad_res_alloc(struct bnad *bnad)
2215{
2216 int i, err;
2217 struct bna_res_info *res_info = &bnad->res_info[0];
2218
2219 for (i = 0; i < BNA_RES_T_MAX; i++) {
2220 if (res_info[i].res_type == BNA_RES_T_MEM)
2221 err = bnad_mem_alloc(bnad, &res_info[i].res_u.mem_info);
2222 else
2223 err = bnad_mbox_irq_alloc(bnad,
2224 &res_info[i].res_u.intr_info);
2225 if (err)
2226 goto err_return;
2227 }
2228 return 0;
2229
2230err_return:
2231 bnad_res_free(bnad);
2232 return err;
2233}
2234
2235/* Interrupt enable / disable */
2236static void
2237bnad_enable_msix(struct bnad *bnad)
2238{
2239 int i, ret;
2240 u32 tot_msix_num;
2241 unsigned long flags;
2242
2243 spin_lock_irqsave(&bnad->bna_lock, flags);
2244 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
2245 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2246 return;
2247 }
2248 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2249
2250 if (bnad->msix_table)
2251 return;
2252
2253 tot_msix_num = bnad->msix_num + bnad->msix_diag_num;
2254
2255 bnad->msix_table =
2256 kcalloc(tot_msix_num, sizeof(struct msix_entry), GFP_KERNEL);
2257
2258 if (!bnad->msix_table)
2259 goto intx_mode;
2260
2261 for (i = 0; i < tot_msix_num; i++)
2262 bnad->msix_table[i].entry = i;
2263
2264 ret = pci_enable_msix(bnad->pcidev, bnad->msix_table, tot_msix_num);
2265 if (ret > 0) {
2266 /* Not enough MSI-X vectors. */
2267
2268 spin_lock_irqsave(&bnad->bna_lock, flags);
2269 /* ret = #of vectors that we got */
2270 bnad_q_num_adjust(bnad, ret);
2271 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2272
2273 bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx)
2274 + (bnad->num_rx
2275 * bnad->num_rxp_per_rx) +
2276 BNAD_MAILBOX_MSIX_VECTORS;
2277 tot_msix_num = bnad->msix_num + bnad->msix_diag_num;
2278
2279 /* Try once more with adjusted numbers */
2280 /* If this fails, fall back to INTx */
2281 ret = pci_enable_msix(bnad->pcidev, bnad->msix_table,
2282 tot_msix_num);
2283 if (ret)
2284 goto intx_mode;
2285
2286 } else if (ret < 0)
2287 goto intx_mode;
2288 return;
2289
2290intx_mode:
2291
2292 kfree(bnad->msix_table);
2293 bnad->msix_table = NULL;
2294 bnad->msix_num = 0;
2295 bnad->msix_diag_num = 0;
2296 spin_lock_irqsave(&bnad->bna_lock, flags);
2297 bnad->cfg_flags &= ~BNAD_CF_MSIX;
2298 bnad_q_num_init(bnad);
2299 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2300}
2301
2302static void
2303bnad_disable_msix(struct bnad *bnad)
2304{
2305 u32 cfg_flags;
2306 unsigned long flags;
2307
2308 spin_lock_irqsave(&bnad->bna_lock, flags);
2309 cfg_flags = bnad->cfg_flags;
2310 if (bnad->cfg_flags & BNAD_CF_MSIX)
2311 bnad->cfg_flags &= ~BNAD_CF_MSIX;
2312 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2313
2314 if (cfg_flags & BNAD_CF_MSIX) {
2315 pci_disable_msix(bnad->pcidev);
2316 kfree(bnad->msix_table);
2317 bnad->msix_table = NULL;
2318 }
2319}
2320
2321/* Netdev entry points */
2322static int
2323bnad_open(struct net_device *netdev)
2324{
2325 int err;
2326 struct bnad *bnad = netdev_priv(netdev);
2327 struct bna_pause_config pause_config;
2328 int mtu;
2329 unsigned long flags;
2330
2331 mutex_lock(&bnad->conf_mutex);
2332
2333 /* Tx */
2334 err = bnad_setup_tx(bnad, 0);
2335 if (err)
2336 goto err_return;
2337
2338 /* Rx */
2339 err = bnad_setup_rx(bnad, 0);
2340 if (err)
2341 goto cleanup_tx;
2342
2343 /* Port */
2344 pause_config.tx_pause = 0;
2345 pause_config.rx_pause = 0;
2346
2347 mtu = ETH_HLEN + bnad->netdev->mtu + ETH_FCS_LEN;
2348
2349 spin_lock_irqsave(&bnad->bna_lock, flags);
2350 bna_port_mtu_set(&bnad->bna.port, mtu, NULL);
2351 bna_port_pause_config(&bnad->bna.port, &pause_config, NULL);
2352 bna_port_enable(&bnad->bna.port);
2353 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2354
2355 /* Enable broadcast */
2356 bnad_enable_default_bcast(bnad);
2357
2358 /* Set the UCAST address */
2359 spin_lock_irqsave(&bnad->bna_lock, flags);
2360 bnad_mac_addr_set_locked(bnad, netdev->dev_addr);
2361 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2362
2363 /* Start the stats timer */
2364 bnad_stats_timer_start(bnad);
2365
2366 mutex_unlock(&bnad->conf_mutex);
2367
2368 return 0;
2369
2370cleanup_tx:
2371 bnad_cleanup_tx(bnad, 0);
2372
2373err_return:
2374 mutex_unlock(&bnad->conf_mutex);
2375 return err;
2376}
2377
2378static int
2379bnad_stop(struct net_device *netdev)
2380{
2381 struct bnad *bnad = netdev_priv(netdev);
2382 unsigned long flags;
2383
2384 mutex_lock(&bnad->conf_mutex);
2385
2386 /* Stop the stats timer */
2387 bnad_stats_timer_stop(bnad);
2388
2389 init_completion(&bnad->bnad_completions.port_comp);
2390
2391 spin_lock_irqsave(&bnad->bna_lock, flags);
2392 bna_port_disable(&bnad->bna.port, BNA_HARD_CLEANUP,
2393 bnad_cb_port_disabled);
2394 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2395
2396 wait_for_completion(&bnad->bnad_completions.port_comp);
2397
2398 bnad_cleanup_tx(bnad, 0);
2399 bnad_cleanup_rx(bnad, 0);
2400
2401 /* Synchronize mailbox IRQ */
2402 bnad_mbox_irq_sync(bnad);
2403
2404 mutex_unlock(&bnad->conf_mutex);
2405
2406 return 0;
2407}
2408
2409/* TX */
2410/*
2411 * bnad_start_xmit : Netdev entry point for Transmit
2412 * Called under lock held by net_device
2413 */
2414static netdev_tx_t
2415bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2416{
2417 struct bnad *bnad = netdev_priv(netdev);
2418
2419 u16 txq_prod, vlan_tag = 0;
2420 u32 unmap_prod, wis, wis_used, wi_range;
2421 u32 vectors, vect_id, i, acked;
2422 u32 tx_id;
2423 int err;
2424
2425 struct bnad_tx_info *tx_info;
2426 struct bna_tcb *tcb;
2427 struct bnad_unmap_q *unmap_q;
2428 dma_addr_t dma_addr;
2429 struct bna_txq_entry *txqent;
2430 bna_txq_wi_ctrl_flag_t flags;
2431
2432 if (unlikely
2433 (skb->len <= ETH_HLEN || skb->len > BFI_TX_MAX_DATA_PER_PKT)) {
2434 dev_kfree_skb(skb);
2435 return NETDEV_TX_OK;
2436 }
2437
2438 /*
2439 * Takes care of the Tx that is scheduled between clearing the flag
2440 * and the netif_stop_queue() call.
2441 */
2442 if (unlikely(!test_bit(BNAD_RF_TX_STARTED, &bnad->run_flags))) {
2443 dev_kfree_skb(skb);
2444 return NETDEV_TX_OK;
2445 }
2446
2447 tx_id = 0;
2448
2449 tx_info = &bnad->tx_info[tx_id];
2450 tcb = tx_info->tcb[tx_id];
2451 unmap_q = tcb->unmap_q;
2452
2453 vectors = 1 + skb_shinfo(skb)->nr_frags;
2454 if (vectors > BFI_TX_MAX_VECTORS_PER_PKT) {
2455 dev_kfree_skb(skb);
2456 return NETDEV_TX_OK;
2457 }
2458 wis = BNA_TXQ_WI_NEEDED(vectors); /* 4 vectors per work item */
2459 acked = 0;
2460 if (unlikely
2461 (wis > BNA_QE_FREE_CNT(tcb, tcb->q_depth) ||
2462 vectors > BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth))) {
2463 if ((u16) (*tcb->hw_consumer_index) !=
2464 tcb->consumer_index &&
2465 !test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) {
2466 acked = bnad_free_txbufs(bnad, tcb);
2467 bna_ib_ack(tcb->i_dbell, acked);
2468 smp_mb__before_clear_bit();
2469 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
2470 } else {
2471 netif_stop_queue(netdev);
2472 BNAD_UPDATE_CTR(bnad, netif_queue_stop);
2473 }
2474
2475 smp_mb();
2476 /*
2477 * Check again to deal with race condition between
2478 * netif_stop_queue here, and netif_wake_queue in
2479 * interrupt handler which is not inside netif tx lock.
2480 */
2481 if (likely
2482 (wis > BNA_QE_FREE_CNT(tcb, tcb->q_depth) ||
2483 vectors > BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth))) {
2484 BNAD_UPDATE_CTR(bnad, netif_queue_stop);
2485 return NETDEV_TX_BUSY;
2486 } else {
2487 netif_wake_queue(netdev);
2488 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
2489 }
2490 }
2491
2492 unmap_prod = unmap_q->producer_index;
2493 wis_used = 1;
2494 vect_id = 0;
2495 flags = 0;
2496
2497 txq_prod = tcb->producer_index;
2498 BNA_TXQ_QPGE_PTR_GET(txq_prod, tcb->sw_qpt, txqent, wi_range);
2499 BUG_ON(!(wi_range <= tcb->q_depth));
2500 txqent->hdr.wi.reserved = 0;
2501 txqent->hdr.wi.num_vectors = vectors;
2502 txqent->hdr.wi.opcode =
2503 htons((skb_is_gso(skb) ? BNA_TXQ_WI_SEND_LSO :
2504 BNA_TXQ_WI_SEND));
2505
2506 if (bnad->vlan_grp && vlan_tx_tag_present(skb)) {
2507 vlan_tag = (u16) vlan_tx_tag_get(skb);
2508 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
2509 }
2510 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) {
2511 vlan_tag =
2512 (tcb->priority & 0x7) << 13 | (vlan_tag & 0x1fff);
2513 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
2514 }
2515
2516 txqent->hdr.wi.vlan_tag = htons(vlan_tag);
2517
2518 if (skb_is_gso(skb)) {
2519 err = bnad_tso_prepare(bnad, skb);
2520 if (err) {
2521 dev_kfree_skb(skb);
2522 return NETDEV_TX_OK;
2523 }
2524 txqent->hdr.wi.lso_mss = htons(skb_is_gso(skb));
2525 flags |= (BNA_TXQ_WI_CF_IP_CKSUM | BNA_TXQ_WI_CF_TCP_CKSUM);
2526 txqent->hdr.wi.l4_hdr_size_n_offset =
2527 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2528 (tcp_hdrlen(skb) >> 2,
2529 skb_transport_offset(skb)));
2530 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2531 u8 proto = 0;
2532
2533 txqent->hdr.wi.lso_mss = 0;
2534
2535 if (skb->protocol == htons(ETH_P_IP))
2536 proto = ip_hdr(skb)->protocol;
2537 else if (skb->protocol == htons(ETH_P_IPV6)) {
2538 /* nexthdr may not be TCP immediately. */
2539 proto = ipv6_hdr(skb)->nexthdr;
2540 }
2541 if (proto == IPPROTO_TCP) {
2542 flags |= BNA_TXQ_WI_CF_TCP_CKSUM;
2543 txqent->hdr.wi.l4_hdr_size_n_offset =
2544 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2545 (0, skb_transport_offset(skb)));
2546
2547 BNAD_UPDATE_CTR(bnad, tcpcsum_offload);
2548
2549 BUG_ON(!(skb_headlen(skb) >=
2550 skb_transport_offset(skb) + tcp_hdrlen(skb)));
2551
2552 } else if (proto == IPPROTO_UDP) {
2553 flags |= BNA_TXQ_WI_CF_UDP_CKSUM;
2554 txqent->hdr.wi.l4_hdr_size_n_offset =
2555 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2556 (0, skb_transport_offset(skb)));
2557
2558 BNAD_UPDATE_CTR(bnad, udpcsum_offload);
2559
2560 BUG_ON(!(skb_headlen(skb) >=
2561 skb_transport_offset(skb) +
2562 sizeof(struct udphdr)));
2563 } else {
2564 err = skb_checksum_help(skb);
2565 BNAD_UPDATE_CTR(bnad, csum_help);
2566 if (err) {
2567 dev_kfree_skb(skb);
2568 BNAD_UPDATE_CTR(bnad, csum_help_err);
2569 return NETDEV_TX_OK;
2570 }
2571 }
2572 } else {
2573 txqent->hdr.wi.lso_mss = 0;
2574 txqent->hdr.wi.l4_hdr_size_n_offset = 0;
2575 }
2576
2577 txqent->hdr.wi.flags = htons(flags);
2578
2579 txqent->hdr.wi.frame_length = htonl(skb->len);
2580
2581 unmap_q->unmap_array[unmap_prod].skb = skb;
2582 BUG_ON(!(skb_headlen(skb) <= BFI_TX_MAX_DATA_PER_VECTOR));
2583 txqent->vector[vect_id].length = htons(skb_headlen(skb));
2584 dma_addr = pci_map_single(bnad->pcidev, skb->data, skb_headlen(skb),
2585 PCI_DMA_TODEVICE);
2586 pci_unmap_addr_set(&unmap_q->unmap_array[unmap_prod], dma_addr,
2587 dma_addr);
2588
2589 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr);
2590 BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
2591
2592 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2593 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
2594 u32 size = frag->size;
2595
2596 if (++vect_id == BFI_TX_MAX_VECTORS_PER_WI) {
2597 vect_id = 0;
2598 if (--wi_range)
2599 txqent++;
2600 else {
2601 BNA_QE_INDX_ADD(txq_prod, wis_used,
2602 tcb->q_depth);
2603 wis_used = 0;
2604 BNA_TXQ_QPGE_PTR_GET(txq_prod, tcb->sw_qpt,
2605 txqent, wi_range);
2606 BUG_ON(!(wi_range <= tcb->q_depth));
2607 }
2608 wis_used++;
2609 txqent->hdr.wi_ext.opcode = htons(BNA_TXQ_WI_EXTENSION);
2610 }
2611
2612 BUG_ON(!(size <= BFI_TX_MAX_DATA_PER_VECTOR));
2613 txqent->vector[vect_id].length = htons(size);
2614 dma_addr =
2615 pci_map_page(bnad->pcidev, frag->page,
2616 frag->page_offset, size,
2617 PCI_DMA_TODEVICE);
2618 pci_unmap_addr_set(&unmap_q->unmap_array[unmap_prod], dma_addr,
2619 dma_addr);
2620 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr);
2621 BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
2622 }
2623
2624 unmap_q->producer_index = unmap_prod;
2625 BNA_QE_INDX_ADD(txq_prod, wis_used, tcb->q_depth);
2626 tcb->producer_index = txq_prod;
2627
2628 smp_mb();
2629 bna_txq_prod_indx_doorbell(tcb);
2630
2631 if ((u16) (*tcb->hw_consumer_index) != tcb->consumer_index)
2632 tasklet_schedule(&bnad->tx_free_tasklet);
2633
2634 return NETDEV_TX_OK;
2635}
2636
2637/*
2638 * Used spin_lock to synchronize reading of stats structures, which
2639 * is written by BNA under the same lock.
2640 */
2641static struct net_device_stats *
2642bnad_get_netdev_stats(struct net_device *netdev)
2643{
2644 struct bnad *bnad = netdev_priv(netdev);
2645 unsigned long flags;
2646
2647 spin_lock_irqsave(&bnad->bna_lock, flags);
2648
2649 memset(&bnad->net_stats, 0, sizeof(struct net_device_stats));
2650
2651 bnad_netdev_qstats_fill(bnad);
2652 bnad_netdev_hwstats_fill(bnad);
2653
2654 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2655
2656 return &bnad->net_stats;
2657}
2658
2659static void
2660bnad_set_rx_mode(struct net_device *netdev)
2661{
2662 struct bnad *bnad = netdev_priv(netdev);
2663 u32 new_mask, valid_mask;
2664 unsigned long flags;
2665
2666 spin_lock_irqsave(&bnad->bna_lock, flags);
2667
2668 new_mask = valid_mask = 0;
2669
2670 if (netdev->flags & IFF_PROMISC) {
2671 if (!(bnad->cfg_flags & BNAD_CF_PROMISC)) {
2672 new_mask = BNAD_RXMODE_PROMISC_DEFAULT;
2673 valid_mask = BNAD_RXMODE_PROMISC_DEFAULT;
2674 bnad->cfg_flags |= BNAD_CF_PROMISC;
2675 }
2676 } else {
2677 if (bnad->cfg_flags & BNAD_CF_PROMISC) {
2678 new_mask = ~BNAD_RXMODE_PROMISC_DEFAULT;
2679 valid_mask = BNAD_RXMODE_PROMISC_DEFAULT;
2680 bnad->cfg_flags &= ~BNAD_CF_PROMISC;
2681 }
2682 }
2683
2684 if (netdev->flags & IFF_ALLMULTI) {
2685 if (!(bnad->cfg_flags & BNAD_CF_ALLMULTI)) {
2686 new_mask |= BNA_RXMODE_ALLMULTI;
2687 valid_mask |= BNA_RXMODE_ALLMULTI;
2688 bnad->cfg_flags |= BNAD_CF_ALLMULTI;
2689 }
2690 } else {
2691 if (bnad->cfg_flags & BNAD_CF_ALLMULTI) {
2692 new_mask &= ~BNA_RXMODE_ALLMULTI;
2693 valid_mask |= BNA_RXMODE_ALLMULTI;
2694 bnad->cfg_flags &= ~BNAD_CF_ALLMULTI;
2695 }
2696 }
2697
2698 bna_rx_mode_set(bnad->rx_info[0].rx, new_mask, valid_mask, NULL);
2699
2700 if (!netdev_mc_empty(netdev)) {
2701 u8 *mcaddr_list;
2702 int mc_count = netdev_mc_count(netdev);
2703
2704 /* Index 0 holds the broadcast address */
2705 mcaddr_list =
2706 kzalloc((mc_count + 1) * ETH_ALEN,
2707 GFP_ATOMIC);
2708 if (!mcaddr_list)
2709 return;
2710
2711 memcpy(&mcaddr_list[0], &bnad_bcast_addr[0], ETH_ALEN);
2712
2713 /* Copy rest of the MC addresses */
2714 bnad_netdev_mc_list_get(netdev, mcaddr_list);
2715
2716 bna_rx_mcast_listset(bnad->rx_info[0].rx, mc_count + 1,
2717 mcaddr_list, NULL);
2718
2719 /* Should we enable BNAD_CF_ALLMULTI for err != 0 ? */
2720 kfree(mcaddr_list);
2721 }
2722 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2723}
2724
2725/*
2726 * bna_lock is used to sync writes to netdev->addr
2727 * conf_lock cannot be used since this call may be made
2728 * in a non-blocking context.
2729 */
2730static int
2731bnad_set_mac_address(struct net_device *netdev, void *mac_addr)
2732{
2733 int err;
2734 struct bnad *bnad = netdev_priv(netdev);
2735 struct sockaddr *sa = (struct sockaddr *)mac_addr;
2736 unsigned long flags;
2737
2738 spin_lock_irqsave(&bnad->bna_lock, flags);
2739
2740 err = bnad_mac_addr_set_locked(bnad, sa->sa_data);
2741
2742 if (!err)
2743 memcpy(netdev->dev_addr, sa->sa_data, netdev->addr_len);
2744
2745 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2746
2747 return err;
2748}
2749
2750static int
2751bnad_change_mtu(struct net_device *netdev, int new_mtu)
2752{
2753 int mtu, err = 0;
2754 unsigned long flags;
2755
2756 struct bnad *bnad = netdev_priv(netdev);
2757
2758 if (new_mtu + ETH_HLEN < ETH_ZLEN || new_mtu > BNAD_JUMBO_MTU)
2759 return -EINVAL;
2760
2761 mutex_lock(&bnad->conf_mutex);
2762
2763 netdev->mtu = new_mtu;
2764
2765 mtu = ETH_HLEN + new_mtu + ETH_FCS_LEN;
2766
2767 spin_lock_irqsave(&bnad->bna_lock, flags);
2768 bna_port_mtu_set(&bnad->bna.port, mtu, NULL);
2769 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2770
2771 mutex_unlock(&bnad->conf_mutex);
2772 return err;
2773}
2774
2775static void
2776bnad_vlan_rx_register(struct net_device *netdev,
2777 struct vlan_group *vlan_grp)
2778{
2779 struct bnad *bnad = netdev_priv(netdev);
2780
2781 mutex_lock(&bnad->conf_mutex);
2782 bnad->vlan_grp = vlan_grp;
2783 mutex_unlock(&bnad->conf_mutex);
2784}
2785
2786static void
2787bnad_vlan_rx_add_vid(struct net_device *netdev,
2788 unsigned short vid)
2789{
2790 struct bnad *bnad = netdev_priv(netdev);
2791 unsigned long flags;
2792
2793 if (!bnad->rx_info[0].rx)
2794 return;
2795
2796 mutex_lock(&bnad->conf_mutex);
2797
2798 spin_lock_irqsave(&bnad->bna_lock, flags);
2799 bna_rx_vlan_add(bnad->rx_info[0].rx, vid);
2800 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2801
2802 mutex_unlock(&bnad->conf_mutex);
2803}
2804
2805static void
2806bnad_vlan_rx_kill_vid(struct net_device *netdev,
2807 unsigned short vid)
2808{
2809 struct bnad *bnad = netdev_priv(netdev);
2810 unsigned long flags;
2811
2812 if (!bnad->rx_info[0].rx)
2813 return;
2814
2815 mutex_lock(&bnad->conf_mutex);
2816
2817 spin_lock_irqsave(&bnad->bna_lock, flags);
2818 bna_rx_vlan_del(bnad->rx_info[0].rx, vid);
2819 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2820
2821 mutex_unlock(&bnad->conf_mutex);
2822}
2823
2824#ifdef CONFIG_NET_POLL_CONTROLLER
2825static void
2826bnad_netpoll(struct net_device *netdev)
2827{
2828 struct bnad *bnad = netdev_priv(netdev);
2829 struct bnad_rx_info *rx_info;
2830 struct bnad_rx_ctrl *rx_ctrl;
2831 u32 curr_mask;
2832 int i, j;
2833
2834 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
2835 bna_intx_disable(&bnad->bna, curr_mask);
2836 bnad_isr(bnad->pcidev->irq, netdev);
2837 bna_intx_enable(&bnad->bna, curr_mask);
2838 } else {
2839 for (i = 0; i < bnad->num_rx; i++) {
2840 rx_info = &bnad->rx_info[i];
2841 if (!rx_info->rx)
2842 continue;
2843 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
2844 rx_ctrl = &rx_info->rx_ctrl[j];
2845 if (rx_ctrl->ccb) {
2846 bnad_disable_rx_irq(bnad,
2847 rx_ctrl->ccb);
2848 bnad_netif_rx_schedule_poll(bnad,
2849 rx_ctrl->ccb);
2850 }
2851 }
2852 }
2853 }
2854}
2855#endif
2856
2857static const struct net_device_ops bnad_netdev_ops = {
2858 .ndo_open = bnad_open,
2859 .ndo_stop = bnad_stop,
2860 .ndo_start_xmit = bnad_start_xmit,
2861 .ndo_get_stats = bnad_get_netdev_stats,
2862 .ndo_set_rx_mode = bnad_set_rx_mode,
2863 .ndo_set_multicast_list = bnad_set_rx_mode,
2864 .ndo_validate_addr = eth_validate_addr,
2865 .ndo_set_mac_address = bnad_set_mac_address,
2866 .ndo_change_mtu = bnad_change_mtu,
2867 .ndo_vlan_rx_register = bnad_vlan_rx_register,
2868 .ndo_vlan_rx_add_vid = bnad_vlan_rx_add_vid,
2869 .ndo_vlan_rx_kill_vid = bnad_vlan_rx_kill_vid,
2870#ifdef CONFIG_NET_POLL_CONTROLLER
2871 .ndo_poll_controller = bnad_netpoll
2872#endif
2873};
2874
2875static void
2876bnad_netdev_init(struct bnad *bnad, bool using_dac)
2877{
2878 struct net_device *netdev = bnad->netdev;
2879
2880 netdev->features |= NETIF_F_IPV6_CSUM;
2881 netdev->features |= NETIF_F_TSO;
2882 netdev->features |= NETIF_F_TSO6;
2883
2884 netdev->features |= NETIF_F_GRO;
2885 pr_warn("bna: GRO enabled, using kernel stack GRO\n");
2886
2887 netdev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
2888
2889 if (using_dac)
2890 netdev->features |= NETIF_F_HIGHDMA;
2891
2892 netdev->features |=
2893 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX |
2894 NETIF_F_HW_VLAN_FILTER;
2895
2896 netdev->vlan_features = netdev->features;
2897 netdev->mem_start = bnad->mmio_start;
2898 netdev->mem_end = bnad->mmio_start + bnad->mmio_len - 1;
2899
2900 netdev->netdev_ops = &bnad_netdev_ops;
2901 bnad_set_ethtool_ops(netdev);
2902}
2903
2904/*
2905 * 1. Initialize the bnad structure
2906 * 2. Setup netdev pointer in pci_dev
2907 * 3. Initialze Tx free tasklet
2908 * 4. Initialize no. of TxQ & CQs & MSIX vectors
2909 */
2910static int
2911bnad_init(struct bnad *bnad,
2912 struct pci_dev *pdev, struct net_device *netdev)
2913{
2914 unsigned long flags;
2915
2916 SET_NETDEV_DEV(netdev, &pdev->dev);
2917 pci_set_drvdata(pdev, netdev);
2918
2919 bnad->netdev = netdev;
2920 bnad->pcidev = pdev;
2921 bnad->mmio_start = pci_resource_start(pdev, 0);
2922 bnad->mmio_len = pci_resource_len(pdev, 0);
2923 bnad->bar0 = ioremap_nocache(bnad->mmio_start, bnad->mmio_len);
2924 if (!bnad->bar0) {
2925 dev_err(&pdev->dev, "ioremap for bar0 failed\n");
2926 pci_set_drvdata(pdev, NULL);
2927 return -ENOMEM;
2928 }
2929 pr_info("bar0 mapped to %p, len %llu\n", bnad->bar0,
2930 (unsigned long long) bnad->mmio_len);
2931
2932 spin_lock_irqsave(&bnad->bna_lock, flags);
2933 if (!bnad_msix_disable)
2934 bnad->cfg_flags = BNAD_CF_MSIX;
2935
2936 bnad->cfg_flags |= BNAD_CF_DIM_ENABLED;
2937
2938 bnad_q_num_init(bnad);
2939 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2940
2941 bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx) +
2942 (bnad->num_rx * bnad->num_rxp_per_rx) +
2943 BNAD_MAILBOX_MSIX_VECTORS;
2944 bnad->msix_diag_num = 2; /* 1 for Tx, 1 for Rx */
2945
2946 bnad->txq_depth = BNAD_TXQ_DEPTH;
2947 bnad->rxq_depth = BNAD_RXQ_DEPTH;
2948 bnad->rx_csum = true;
2949
2950 bnad->tx_coalescing_timeo = BFI_TX_COALESCING_TIMEO;
2951 bnad->rx_coalescing_timeo = BFI_RX_COALESCING_TIMEO;
2952
2953 tasklet_init(&bnad->tx_free_tasklet, bnad_tx_free_tasklet,
2954 (unsigned long)bnad);
2955
2956 return 0;
2957}
2958
2959/*
2960 * Must be called after bnad_pci_uninit()
2961 * so that iounmap() and pci_set_drvdata(NULL)
2962 * happens only after PCI uninitialization.
2963 */
2964static void
2965bnad_uninit(struct bnad *bnad)
2966{
2967 if (bnad->bar0)
2968 iounmap(bnad->bar0);
2969 pci_set_drvdata(bnad->pcidev, NULL);
2970}
2971
2972/*
2973 * Initialize locks
2974 a) Per device mutes used for serializing configuration
2975 changes from OS interface
2976 b) spin lock used to protect bna state machine
2977 */
2978static void
2979bnad_lock_init(struct bnad *bnad)
2980{
2981 spin_lock_init(&bnad->bna_lock);
2982 mutex_init(&bnad->conf_mutex);
2983}
2984
2985static void
2986bnad_lock_uninit(struct bnad *bnad)
2987{
2988 mutex_destroy(&bnad->conf_mutex);
2989}
2990
2991/* PCI Initialization */
2992static int
2993bnad_pci_init(struct bnad *bnad,
2994 struct pci_dev *pdev, bool *using_dac)
2995{
2996 int err;
2997
2998 err = pci_enable_device(pdev);
2999 if (err)
3000 return err;
3001 err = pci_request_regions(pdev, BNAD_NAME);
3002 if (err)
3003 goto disable_device;
3004 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
3005 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
3006 *using_dac = 1;
3007 } else {
3008 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3009 if (err) {
3010 err = pci_set_consistent_dma_mask(pdev,
3011 DMA_BIT_MASK(32));
3012 if (err)
3013 goto release_regions;
3014 }
3015 *using_dac = 0;
3016 }
3017 pci_set_master(pdev);
3018 return 0;
3019
3020release_regions:
3021 pci_release_regions(pdev);
3022disable_device:
3023 pci_disable_device(pdev);
3024
3025 return err;
3026}
3027
3028static void
3029bnad_pci_uninit(struct pci_dev *pdev)
3030{
3031 pci_release_regions(pdev);
3032 pci_disable_device(pdev);
3033}
3034
3035static int __devinit
3036bnad_pci_probe(struct pci_dev *pdev,
3037 const struct pci_device_id *pcidev_id)
3038{
3039 bool using_dac;
3040 int err;
3041 struct bnad *bnad;
3042 struct bna *bna;
3043 struct net_device *netdev;
3044 struct bfa_pcidev pcidev_info;
3045 unsigned long flags;
3046
3047 pr_info("bnad_pci_probe : (0x%p, 0x%p) PCI Func : (%d)\n",
3048 pdev, pcidev_id, PCI_FUNC(pdev->devfn));
3049
3050 mutex_lock(&bnad_fwimg_mutex);
3051 if (!cna_get_firmware_buf(pdev)) {
3052 mutex_unlock(&bnad_fwimg_mutex);
3053 pr_warn("Failed to load Firmware Image!\n");
3054 return -ENODEV;
3055 }
3056 mutex_unlock(&bnad_fwimg_mutex);
3057
3058 /*
3059 * Allocates sizeof(struct net_device + struct bnad)
3060 * bnad = netdev->priv
3061 */
3062 netdev = alloc_etherdev(sizeof(struct bnad));
3063 if (!netdev) {
3064 dev_err(&pdev->dev, "alloc_etherdev failed\n");
3065 err = -ENOMEM;
3066 return err;
3067 }
3068 bnad = netdev_priv(netdev);
3069
3070
3071 /*
3072 * PCI initialization
3073 * Output : using_dac = 1 for 64 bit DMA
3074 * = 0 for 32 bit DMA
3075 */
3076 err = bnad_pci_init(bnad, pdev, &using_dac);
3077 if (err)
3078 goto free_netdev;
3079
3080 bnad_lock_init(bnad);
3081 /*
3082 * Initialize bnad structure
3083 * Setup relation between pci_dev & netdev
3084 * Init Tx free tasklet
3085 */
3086 err = bnad_init(bnad, pdev, netdev);
3087 if (err)
3088 goto pci_uninit;
3089 /* Initialize netdev structure, set up ethtool ops */
3090 bnad_netdev_init(bnad, using_dac);
3091
3092 bnad_enable_msix(bnad);
3093
3094 /* Get resource requirement form bna */
3095 bna_res_req(&bnad->res_info[0]);
3096
3097 /* Allocate resources from bna */
3098 err = bnad_res_alloc(bnad);
3099 if (err)
3100 goto free_netdev;
3101
3102 bna = &bnad->bna;
3103
3104 /* Setup pcidev_info for bna_init() */
3105 pcidev_info.pci_slot = PCI_SLOT(bnad->pcidev->devfn);
3106 pcidev_info.pci_func = PCI_FUNC(bnad->pcidev->devfn);
3107 pcidev_info.device_id = bnad->pcidev->device;
3108 pcidev_info.pci_bar_kva = bnad->bar0;
3109
3110 mutex_lock(&bnad->conf_mutex);
3111
3112 spin_lock_irqsave(&bnad->bna_lock, flags);
3113 bna_init(bna, bnad, &pcidev_info, &bnad->res_info[0]);
3114
3115 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3116
3117 bnad->stats.bna_stats = &bna->stats;
3118
3119 /* Set up timers */
3120 setup_timer(&bnad->bna.device.ioc.ioc_timer, bnad_ioc_timeout,
3121 ((unsigned long)bnad));
3122 setup_timer(&bnad->bna.device.ioc.hb_timer, bnad_ioc_hb_check,
3123 ((unsigned long)bnad));
3124 setup_timer(&bnad->bna.device.ioc.sem_timer, bnad_ioc_sem_timeout,
3125 ((unsigned long)bnad));
3126
3127 /* Now start the timer before calling IOC */
3128 mod_timer(&bnad->bna.device.ioc.ioc_timer,
3129 jiffies + msecs_to_jiffies(BNA_IOC_TIMER_FREQ));
3130
3131 /*
3132 * Start the chip
3133 * Don't care even if err != 0, bna state machine will
3134 * deal with it
3135 */
3136 err = bnad_device_enable(bnad);
3137
3138 /* Get the burnt-in mac */
3139 spin_lock_irqsave(&bnad->bna_lock, flags);
3140 bna_port_mac_get(&bna->port, &bnad->perm_addr);
3141 bnad_set_netdev_perm_addr(bnad);
3142 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3143
3144 mutex_unlock(&bnad->conf_mutex);
3145
3146 /*
3147 * Make sure the link appears down to the stack
3148 */
3149 netif_carrier_off(netdev);
3150
3151 /* Finally, reguister with net_device layer */
3152 err = register_netdev(netdev);
3153 if (err) {
3154 pr_err("BNA : Registering with netdev failed\n");
3155 goto disable_device;
3156 }
3157
3158 return 0;
3159
3160disable_device:
3161 mutex_lock(&bnad->conf_mutex);
3162 bnad_device_disable(bnad);
3163 del_timer_sync(&bnad->bna.device.ioc.ioc_timer);
3164 del_timer_sync(&bnad->bna.device.ioc.sem_timer);
3165 del_timer_sync(&bnad->bna.device.ioc.hb_timer);
3166 spin_lock_irqsave(&bnad->bna_lock, flags);
3167 bna_uninit(bna);
3168 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3169 mutex_unlock(&bnad->conf_mutex);
3170
3171 bnad_res_free(bnad);
3172 bnad_disable_msix(bnad);
3173pci_uninit:
3174 bnad_pci_uninit(pdev);
3175 bnad_lock_uninit(bnad);
3176 bnad_uninit(bnad);
3177free_netdev:
3178 free_netdev(netdev);
3179 return err;
3180}
3181
3182static void __devexit
3183bnad_pci_remove(struct pci_dev *pdev)
3184{
3185 struct net_device *netdev = pci_get_drvdata(pdev);
3186 struct bnad *bnad;
3187 struct bna *bna;
3188 unsigned long flags;
3189
3190 if (!netdev)
3191 return;
3192
3193 pr_info("%s bnad_pci_remove\n", netdev->name);
3194 bnad = netdev_priv(netdev);
3195 bna = &bnad->bna;
3196
3197 unregister_netdev(netdev);
3198
3199 mutex_lock(&bnad->conf_mutex);
3200 bnad_device_disable(bnad);
3201 del_timer_sync(&bnad->bna.device.ioc.ioc_timer);
3202 del_timer_sync(&bnad->bna.device.ioc.sem_timer);
3203 del_timer_sync(&bnad->bna.device.ioc.hb_timer);
3204 spin_lock_irqsave(&bnad->bna_lock, flags);
3205 bna_uninit(bna);
3206 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3207 mutex_unlock(&bnad->conf_mutex);
3208
3209 bnad_res_free(bnad);
3210 bnad_disable_msix(bnad);
3211 bnad_pci_uninit(pdev);
3212 bnad_lock_uninit(bnad);
3213 bnad_uninit(bnad);
3214 free_netdev(netdev);
3215}
3216
3217const struct pci_device_id bnad_pci_id_table[] = {
3218 {
3219 PCI_DEVICE(PCI_VENDOR_ID_BROCADE,
3220 PCI_DEVICE_ID_BROCADE_CT),
3221 .class = PCI_CLASS_NETWORK_ETHERNET << 8,
3222 .class_mask = 0xffff00
3223 }, {0, }
3224};
3225
3226MODULE_DEVICE_TABLE(pci, bnad_pci_id_table);
3227
3228static struct pci_driver bnad_pci_driver = {
3229 .name = BNAD_NAME,
3230 .id_table = bnad_pci_id_table,
3231 .probe = bnad_pci_probe,
3232 .remove = __devexit_p(bnad_pci_remove),
3233};
3234
3235static int __init
3236bnad_module_init(void)
3237{
3238 int err;
3239
3240 pr_info("Brocade 10G Ethernet driver\n");
3241
3242 bfa_ioc_auto_recover(bnad_ioc_auto_recover);
3243
3244 err = pci_register_driver(&bnad_pci_driver);
3245 if (err < 0) {
3246 pr_err("bna : PCI registration failed in module init "
3247 "(%d)\n", err);
3248 return err;
3249 }
3250
3251 return 0;
3252}
3253
3254static void __exit
3255bnad_module_exit(void)
3256{
3257 pci_unregister_driver(&bnad_pci_driver);
3258
3259 if (bfi_fw)
3260 release_firmware(bfi_fw);
3261}
3262
3263module_init(bnad_module_init);
3264module_exit(bnad_module_exit);
3265
3266MODULE_AUTHOR("Brocade");
3267MODULE_LICENSE("GPL");
3268MODULE_DESCRIPTION("Brocade 10G PCIe Ethernet driver");
3269MODULE_VERSION(BNAD_VERSION);
3270MODULE_FIRMWARE(CNA_FW_FILE_CT);
diff --git a/drivers/net/bna/bnad.h b/drivers/net/bna/bnad.h
new file mode 100644
index 000000000000..3261401e35cb
--- /dev/null
+++ b/drivers/net/bna/bnad.h
@@ -0,0 +1,334 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18#ifndef __BNAD_H__
19#define __BNAD_H__
20
21#include <linux/rtnetlink.h>
22#include <linux/workqueue.h>
23#include <linux/ipv6.h>
24#include <linux/etherdevice.h>
25#include <linux/mutex.h>
26#include <linux/firmware.h>
27
28/* Fix for IA64 */
29#include <asm/checksum.h>
30#include <net/ip6_checksum.h>
31
32#include <net/ip.h>
33#include <net/tcp.h>
34
35#include "bna.h"
36
37#define BNAD_TXQ_DEPTH 2048
38#define BNAD_RXQ_DEPTH 2048
39
40#define BNAD_MAX_TXS 1
41#define BNAD_MAX_TXQ_PER_TX 8 /* 8 priority queues */
42#define BNAD_TXQ_NUM 1
43
44#define BNAD_MAX_RXS 1
45#define BNAD_MAX_RXPS_PER_RX 16
46
47/*
48 * Control structure pointed to ccb->ctrl, which
49 * determines the NAPI / LRO behavior CCB
50 * There is 1:1 corres. between ccb & ctrl
51 */
52struct bnad_rx_ctrl {
53 struct bna_ccb *ccb;
54 struct napi_struct napi;
55};
56
57#define BNAD_RXMODE_PROMISC_DEFAULT BNA_RXMODE_PROMISC
58
59#define BNAD_GET_TX_ID(_skb) (0)
60
61/*
62 * GLOBAL #defines (CONSTANTS)
63 */
64#define BNAD_NAME "bna"
65#define BNAD_NAME_LEN 64
66
67#define BNAD_VERSION "2.3.2.0"
68
69#define BNAD_MAILBOX_MSIX_VECTORS 1
70
71#define BNAD_STATS_TIMER_FREQ 1000 /* in msecs */
72#define BNAD_DIM_TIMER_FREQ 1000 /* in msecs */
73
74#define BNAD_MAX_Q_DEPTH 0x10000
75#define BNAD_MIN_Q_DEPTH 0x200
76
77#define BNAD_JUMBO_MTU 9000
78
79#define BNAD_NETIF_WAKE_THRESHOLD 8
80
81#define BNAD_RXQ_REFILL_THRESHOLD_SHIFT 3
82
83/* Bit positions for tcb->flags */
84#define BNAD_TXQ_FREE_SENT 0
85
86/* Bit positions for rcb->flags */
87#define BNAD_RXQ_REFILL 0
88#define BNAD_RXQ_STARTED 1
89
90/*
91 * DATA STRUCTURES
92 */
93
94/* enums */
95enum bnad_intr_source {
96 BNAD_INTR_TX = 1,
97 BNAD_INTR_RX = 2
98};
99
100enum bnad_link_state {
101 BNAD_LS_DOWN = 0,
102 BNAD_LS_UP = 1
103};
104
105struct bnad_completion {
106 struct completion ioc_comp;
107 struct completion ucast_comp;
108 struct completion mcast_comp;
109 struct completion tx_comp;
110 struct completion rx_comp;
111 struct completion stats_comp;
112 struct completion port_comp;
113
114 u8 ioc_comp_status;
115 u8 ucast_comp_status;
116 u8 mcast_comp_status;
117 u8 tx_comp_status;
118 u8 rx_comp_status;
119 u8 stats_comp_status;
120 u8 port_comp_status;
121};
122
123/* Tx Rx Control Stats */
124struct bnad_drv_stats {
125 u64 netif_queue_stop;
126 u64 netif_queue_wakeup;
127 u64 tso4;
128 u64 tso6;
129 u64 tso_err;
130 u64 tcpcsum_offload;
131 u64 udpcsum_offload;
132 u64 csum_help;
133 u64 csum_help_err;
134
135 u64 hw_stats_updates;
136 u64 netif_rx_schedule;
137 u64 netif_rx_complete;
138 u64 netif_rx_dropped;
139
140 u64 link_toggle;
141 u64 cee_up;
142
143 u64 rxp_info_alloc_failed;
144 u64 mbox_intr_disabled;
145 u64 mbox_intr_enabled;
146 u64 tx_unmap_q_alloc_failed;
147 u64 rx_unmap_q_alloc_failed;
148
149 u64 rxbuf_alloc_failed;
150};
151
152/* Complete driver stats */
153struct bnad_stats {
154 struct bnad_drv_stats drv_stats;
155 struct bna_stats *bna_stats;
156};
157
158/* Tx / Rx Resources */
159struct bnad_tx_res_info {
160 struct bna_res_info res_info[BNA_TX_RES_T_MAX];
161};
162
163struct bnad_rx_res_info {
164 struct bna_res_info res_info[BNA_RX_RES_T_MAX];
165};
166
167struct bnad_tx_info {
168 struct bna_tx *tx; /* 1:1 between tx_info & tx */
169 struct bna_tcb *tcb[BNAD_MAX_TXQ_PER_TX];
170} ____cacheline_aligned;
171
172struct bnad_rx_info {
173 struct bna_rx *rx; /* 1:1 between rx_info & rx */
174
175 struct bnad_rx_ctrl rx_ctrl[BNAD_MAX_RXPS_PER_RX];
176} ____cacheline_aligned;
177
178/* Unmap queues for Tx / Rx cleanup */
179struct bnad_skb_unmap {
180 struct sk_buff *skb;
181 DECLARE_PCI_UNMAP_ADDR(dma_addr)
182};
183
184struct bnad_unmap_q {
185 u32 producer_index;
186 u32 consumer_index;
187 u32 q_depth;
188 /* This should be the last one */
189 struct bnad_skb_unmap unmap_array[1];
190};
191
192/* Bit mask values for bnad->cfg_flags */
193#define BNAD_CF_DIM_ENABLED 0x01 /* DIM */
194#define BNAD_CF_PROMISC 0x02
195#define BNAD_CF_ALLMULTI 0x04
196#define BNAD_CF_MSIX 0x08 /* If in MSIx mode */
197
198/* Defines for run_flags bit-mask */
199/* Set, tested & cleared using xxx_bit() functions */
200/* Values indicated bit positions */
201#define BNAD_RF_CEE_RUNNING 1
202#define BNAD_RF_HW_ERROR 2
203#define BNAD_RF_MBOX_IRQ_DISABLED 3
204#define BNAD_RF_TX_STARTED 4
205#define BNAD_RF_RX_STARTED 5
206#define BNAD_RF_DIM_TIMER_RUNNING 6
207#define BNAD_RF_STATS_TIMER_RUNNING 7
208
209struct bnad {
210 struct net_device *netdev;
211
212 /* Data path */
213 struct bnad_tx_info tx_info[BNAD_MAX_TXS];
214 struct bnad_rx_info rx_info[BNAD_MAX_RXS];
215
216 struct vlan_group *vlan_grp;
217 /*
218 * These q numbers are global only because
219 * they are used to calculate MSIx vectors.
220 * Actually the exact # of queues are per Tx/Rx
221 * object.
222 */
223 u32 num_tx;
224 u32 num_rx;
225 u32 num_txq_per_tx;
226 u32 num_rxp_per_rx;
227
228 u32 txq_depth;
229 u32 rxq_depth;
230
231 u8 tx_coalescing_timeo;
232 u8 rx_coalescing_timeo;
233
234 struct bna_rx_config rx_config[BNAD_MAX_RXS];
235 struct bna_tx_config tx_config[BNAD_MAX_TXS];
236
237 u32 rx_csum;
238
239 void __iomem *bar0; /* BAR0 address */
240
241 struct bna bna;
242
243 u32 cfg_flags;
244 unsigned long run_flags;
245
246 struct pci_dev *pcidev;
247 u64 mmio_start;
248 u64 mmio_len;
249
250 u32 msix_num;
251 u32 msix_diag_num;
252 struct msix_entry *msix_table;
253
254 struct mutex conf_mutex;
255 spinlock_t bna_lock ____cacheline_aligned;
256
257 /* Timers */
258 struct timer_list ioc_timer;
259 struct timer_list dim_timer;
260 struct timer_list stats_timer;
261
262 /* Control path resources, memory & irq */
263 struct bna_res_info res_info[BNA_RES_T_MAX];
264 struct bnad_tx_res_info tx_res_info[BNAD_MAX_TXS];
265 struct bnad_rx_res_info rx_res_info[BNAD_MAX_RXS];
266
267 struct bnad_completion bnad_completions;
268
269 /* Burnt in MAC address */
270 mac_t perm_addr;
271
272 struct tasklet_struct tx_free_tasklet;
273
274 /* Statistics */
275 struct bnad_stats stats;
276 struct net_device_stats net_stats;
277
278 struct bnad_diag *diag;
279
280 char adapter_name[BNAD_NAME_LEN];
281 char port_name[BNAD_NAME_LEN];
282 char mbox_irq_name[BNAD_NAME_LEN];
283};
284
285/*
286 * EXTERN VARIABLES
287 */
288extern struct firmware *bfi_fw;
289extern u32 bnad_rxqs_per_cq;
290
291/*
292 * EXTERN PROTOTYPES
293 */
294extern u32 *cna_get_firmware_buf(struct pci_dev *pdev);
295/* Netdev entry point prototypes */
296extern void bnad_set_ethtool_ops(struct net_device *netdev);
297
298/* Configuration & setup */
299extern void bnad_tx_coalescing_timeo_set(struct bnad *bnad);
300extern void bnad_rx_coalescing_timeo_set(struct bnad *bnad);
301
302extern int bnad_setup_rx(struct bnad *bnad, uint rx_id);
303extern int bnad_setup_tx(struct bnad *bnad, uint tx_id);
304extern void bnad_cleanup_tx(struct bnad *bnad, uint tx_id);
305extern void bnad_cleanup_rx(struct bnad *bnad, uint rx_id);
306
307/* Timer start/stop protos */
308extern void bnad_dim_timer_start(struct bnad *bnad);
309
310/* Statistics */
311extern void bnad_netdev_qstats_fill(struct bnad *bnad);
312extern void bnad_netdev_hwstats_fill(struct bnad *bnad);
313
314/**
315 * MACROS
316 */
317/* To set & get the stats counters */
318#define BNAD_UPDATE_CTR(_bnad, _ctr) \
319 (((_bnad)->stats.drv_stats._ctr)++)
320
321#define BNAD_GET_CTR(_bnad, _ctr) ((_bnad)->stats.drv_stats._ctr)
322
323#define bnad_enable_rx_irq_unsafe(_ccb) \
324{ \
325 bna_ib_coalescing_timer_set((_ccb)->i_dbell, \
326 (_ccb)->rx_coalescing_timeo); \
327 bna_ib_ack((_ccb)->i_dbell, 0); \
328}
329
330#define bnad_dim_timer_running(_bnad) \
331 (((_bnad)->cfg_flags & BNAD_CF_DIM_ENABLED) && \
332 (test_bit(BNAD_RF_DIM_TIMER_RUNNING, &((_bnad)->run_flags))))
333
334#endif /* __BNAD_H__ */
diff --git a/drivers/net/bna/bnad_ethtool.c b/drivers/net/bna/bnad_ethtool.c
new file mode 100644
index 000000000000..e982785b6b25
--- /dev/null
+++ b/drivers/net/bna/bnad_ethtool.c
@@ -0,0 +1,1282 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18
19#include "cna.h"
20
21#include <linux/netdevice.h>
22#include <linux/skbuff.h>
23#include <linux/ethtool.h>
24#include <linux/rtnetlink.h>
25
26#include "bna.h"
27
28#include "bnad.h"
29
30#define BNAD_NUM_TXF_COUNTERS 12
31#define BNAD_NUM_RXF_COUNTERS 10
32#define BNAD_NUM_CQ_COUNTERS 3
33#define BNAD_NUM_RXQ_COUNTERS 6
34#define BNAD_NUM_TXQ_COUNTERS 5
35
36#define BNAD_ETHTOOL_STATS_NUM \
37 (sizeof(struct net_device_stats) / sizeof(unsigned long) + \
38 sizeof(struct bnad_drv_stats) / sizeof(u64) + \
39 offsetof(struct bfi_ll_stats, rxf_stats[0]) / sizeof(u64))
40
41static char *bnad_net_stats_strings[BNAD_ETHTOOL_STATS_NUM] = {
42 "rx_packets",
43 "tx_packets",
44 "rx_bytes",
45 "tx_bytes",
46 "rx_errors",
47 "tx_errors",
48 "rx_dropped",
49 "tx_dropped",
50 "multicast",
51 "collisions",
52
53 "rx_length_errors",
54 "rx_over_errors",
55 "rx_crc_errors",
56 "rx_frame_errors",
57 "rx_fifo_errors",
58 "rx_missed_errors",
59
60 "tx_aborted_errors",
61 "tx_carrier_errors",
62 "tx_fifo_errors",
63 "tx_heartbeat_errors",
64 "tx_window_errors",
65
66 "rx_compressed",
67 "tx_compressed",
68
69 "netif_queue_stop",
70 "netif_queue_wakeup",
71 "tso4",
72 "tso6",
73 "tso_err",
74 "tcpcsum_offload",
75 "udpcsum_offload",
76 "csum_help",
77 "csum_help_err",
78 "hw_stats_updates",
79 "netif_rx_schedule",
80 "netif_rx_complete",
81 "netif_rx_dropped",
82
83 "link_toggle",
84 "cee_up",
85
86 "rxp_info_alloc_failed",
87 "mbox_intr_disabled",
88 "mbox_intr_enabled",
89 "tx_unmap_q_alloc_failed",
90 "rx_unmap_q_alloc_failed",
91 "rxbuf_alloc_failed",
92
93 "mac_frame_64",
94 "mac_frame_65_127",
95 "mac_frame_128_255",
96 "mac_frame_256_511",
97 "mac_frame_512_1023",
98 "mac_frame_1024_1518",
99 "mac_frame_1518_1522",
100 "mac_rx_bytes",
101 "mac_rx_packets",
102 "mac_rx_fcs_error",
103 "mac_rx_multicast",
104 "mac_rx_broadcast",
105 "mac_rx_control_frames",
106 "mac_rx_pause",
107 "mac_rx_unknown_opcode",
108 "mac_rx_alignment_error",
109 "mac_rx_frame_length_error",
110 "mac_rx_code_error",
111 "mac_rx_carrier_sense_error",
112 "mac_rx_undersize",
113 "mac_rx_oversize",
114 "mac_rx_fragments",
115 "mac_rx_jabber",
116 "mac_rx_drop",
117
118 "mac_tx_bytes",
119 "mac_tx_packets",
120 "mac_tx_multicast",
121 "mac_tx_broadcast",
122 "mac_tx_pause",
123 "mac_tx_deferral",
124 "mac_tx_excessive_deferral",
125 "mac_tx_single_collision",
126 "mac_tx_muliple_collision",
127 "mac_tx_late_collision",
128 "mac_tx_excessive_collision",
129 "mac_tx_total_collision",
130 "mac_tx_pause_honored",
131 "mac_tx_drop",
132 "mac_tx_jabber",
133 "mac_tx_fcs_error",
134 "mac_tx_control_frame",
135 "mac_tx_oversize",
136 "mac_tx_undersize",
137 "mac_tx_fragments",
138
139 "bpc_tx_pause_0",
140 "bpc_tx_pause_1",
141 "bpc_tx_pause_2",
142 "bpc_tx_pause_3",
143 "bpc_tx_pause_4",
144 "bpc_tx_pause_5",
145 "bpc_tx_pause_6",
146 "bpc_tx_pause_7",
147 "bpc_tx_zero_pause_0",
148 "bpc_tx_zero_pause_1",
149 "bpc_tx_zero_pause_2",
150 "bpc_tx_zero_pause_3",
151 "bpc_tx_zero_pause_4",
152 "bpc_tx_zero_pause_5",
153 "bpc_tx_zero_pause_6",
154 "bpc_tx_zero_pause_7",
155 "bpc_tx_first_pause_0",
156 "bpc_tx_first_pause_1",
157 "bpc_tx_first_pause_2",
158 "bpc_tx_first_pause_3",
159 "bpc_tx_first_pause_4",
160 "bpc_tx_first_pause_5",
161 "bpc_tx_first_pause_6",
162 "bpc_tx_first_pause_7",
163
164 "bpc_rx_pause_0",
165 "bpc_rx_pause_1",
166 "bpc_rx_pause_2",
167 "bpc_rx_pause_3",
168 "bpc_rx_pause_4",
169 "bpc_rx_pause_5",
170 "bpc_rx_pause_6",
171 "bpc_rx_pause_7",
172 "bpc_rx_zero_pause_0",
173 "bpc_rx_zero_pause_1",
174 "bpc_rx_zero_pause_2",
175 "bpc_rx_zero_pause_3",
176 "bpc_rx_zero_pause_4",
177 "bpc_rx_zero_pause_5",
178 "bpc_rx_zero_pause_6",
179 "bpc_rx_zero_pause_7",
180 "bpc_rx_first_pause_0",
181 "bpc_rx_first_pause_1",
182 "bpc_rx_first_pause_2",
183 "bpc_rx_first_pause_3",
184 "bpc_rx_first_pause_4",
185 "bpc_rx_first_pause_5",
186 "bpc_rx_first_pause_6",
187 "bpc_rx_first_pause_7",
188
189 "rad_rx_frames",
190 "rad_rx_octets",
191 "rad_rx_vlan_frames",
192 "rad_rx_ucast",
193 "rad_rx_ucast_octets",
194 "rad_rx_ucast_vlan",
195 "rad_rx_mcast",
196 "rad_rx_mcast_octets",
197 "rad_rx_mcast_vlan",
198 "rad_rx_bcast",
199 "rad_rx_bcast_octets",
200 "rad_rx_bcast_vlan",
201 "rad_rx_drops",
202
203 "fc_rx_ucast_octets",
204 "fc_rx_ucast",
205 "fc_rx_ucast_vlan",
206 "fc_rx_mcast_octets",
207 "fc_rx_mcast",
208 "fc_rx_mcast_vlan",
209 "fc_rx_bcast_octets",
210 "fc_rx_bcast",
211 "fc_rx_bcast_vlan",
212
213 "fc_tx_ucast_octets",
214 "fc_tx_ucast",
215 "fc_tx_ucast_vlan",
216 "fc_tx_mcast_octets",
217 "fc_tx_mcast",
218 "fc_tx_mcast_vlan",
219 "fc_tx_bcast_octets",
220 "fc_tx_bcast",
221 "fc_tx_bcast_vlan",
222 "fc_tx_parity_errors",
223 "fc_tx_timeout",
224 "fc_tx_fid_parity_errors",
225};
226
227static int
228bnad_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
229{
230 cmd->supported = SUPPORTED_10000baseT_Full;
231 cmd->advertising = ADVERTISED_10000baseT_Full;
232 cmd->autoneg = AUTONEG_DISABLE;
233 cmd->supported |= SUPPORTED_FIBRE;
234 cmd->advertising |= ADVERTISED_FIBRE;
235 cmd->port = PORT_FIBRE;
236 cmd->phy_address = 0;
237
238 if (netif_carrier_ok(netdev)) {
239 cmd->speed = SPEED_10000;
240 cmd->duplex = DUPLEX_FULL;
241 } else {
242 cmd->speed = -1;
243 cmd->duplex = -1;
244 }
245 cmd->transceiver = XCVR_EXTERNAL;
246 cmd->maxtxpkt = 0;
247 cmd->maxrxpkt = 0;
248
249 return 0;
250}
251
252static int
253bnad_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
254{
255 /* 10G full duplex setting supported only */
256 if (cmd->autoneg == AUTONEG_ENABLE)
257 return -EOPNOTSUPP; else {
258 if ((cmd->speed == SPEED_10000) && (cmd->duplex == DUPLEX_FULL))
259 return 0;
260 }
261
262 return -EOPNOTSUPP;
263}
264
265static void
266bnad_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
267{
268 struct bnad *bnad = netdev_priv(netdev);
269 struct bfa_ioc_attr *ioc_attr;
270 unsigned long flags;
271
272 strcpy(drvinfo->driver, BNAD_NAME);
273 strcpy(drvinfo->version, BNAD_VERSION);
274
275 ioc_attr = kzalloc(sizeof(*ioc_attr), GFP_KERNEL);
276 if (ioc_attr) {
277 memset(ioc_attr, 0, sizeof(*ioc_attr));
278 spin_lock_irqsave(&bnad->bna_lock, flags);
279 bfa_ioc_get_attr(&bnad->bna.device.ioc, ioc_attr);
280 spin_unlock_irqrestore(&bnad->bna_lock, flags);
281
282 strncpy(drvinfo->fw_version, ioc_attr->adapter_attr.fw_ver,
283 sizeof(drvinfo->fw_version) - 1);
284 kfree(ioc_attr);
285 }
286
287 strncpy(drvinfo->bus_info, pci_name(bnad->pcidev), ETHTOOL_BUSINFO_LEN);
288}
289
290static int
291get_regs(struct bnad *bnad, u32 * regs)
292{
293 int num = 0, i;
294 u32 reg_addr;
295 unsigned long flags;
296
297#define BNAD_GET_REG(addr) \
298do { \
299 if (regs) \
300 regs[num++] = readl(bnad->bar0 + (addr)); \
301 else \
302 num++; \
303} while (0)
304
305 spin_lock_irqsave(&bnad->bna_lock, flags);
306
307 /* DMA Block Internal Registers */
308 BNAD_GET_REG(DMA_CTRL_REG0);
309 BNAD_GET_REG(DMA_CTRL_REG1);
310 BNAD_GET_REG(DMA_ERR_INT_STATUS);
311 BNAD_GET_REG(DMA_ERR_INT_ENABLE);
312 BNAD_GET_REG(DMA_ERR_INT_STATUS_SET);
313
314 /* APP Block Register Address Offset from BAR0 */
315 BNAD_GET_REG(HOSTFN0_INT_STATUS);
316 BNAD_GET_REG(HOSTFN0_INT_MASK);
317 BNAD_GET_REG(HOST_PAGE_NUM_FN0);
318 BNAD_GET_REG(HOST_MSIX_ERR_INDEX_FN0);
319 BNAD_GET_REG(FN0_PCIE_ERR_REG);
320 BNAD_GET_REG(FN0_ERR_TYPE_STATUS_REG);
321 BNAD_GET_REG(FN0_ERR_TYPE_MSK_STATUS_REG);
322
323 BNAD_GET_REG(HOSTFN1_INT_STATUS);
324 BNAD_GET_REG(HOSTFN1_INT_MASK);
325 BNAD_GET_REG(HOST_PAGE_NUM_FN1);
326 BNAD_GET_REG(HOST_MSIX_ERR_INDEX_FN1);
327 BNAD_GET_REG(FN1_PCIE_ERR_REG);
328 BNAD_GET_REG(FN1_ERR_TYPE_STATUS_REG);
329 BNAD_GET_REG(FN1_ERR_TYPE_MSK_STATUS_REG);
330
331 BNAD_GET_REG(PCIE_MISC_REG);
332
333 BNAD_GET_REG(HOST_SEM0_REG);
334 BNAD_GET_REG(HOST_SEM1_REG);
335 BNAD_GET_REG(HOST_SEM2_REG);
336 BNAD_GET_REG(HOST_SEM3_REG);
337 BNAD_GET_REG(HOST_SEM0_INFO_REG);
338 BNAD_GET_REG(HOST_SEM1_INFO_REG);
339 BNAD_GET_REG(HOST_SEM2_INFO_REG);
340 BNAD_GET_REG(HOST_SEM3_INFO_REG);
341
342 BNAD_GET_REG(TEMPSENSE_CNTL_REG);
343 BNAD_GET_REG(TEMPSENSE_STAT_REG);
344
345 BNAD_GET_REG(APP_LOCAL_ERR_STAT);
346 BNAD_GET_REG(APP_LOCAL_ERR_MSK);
347
348 BNAD_GET_REG(PCIE_LNK_ERR_STAT);
349 BNAD_GET_REG(PCIE_LNK_ERR_MSK);
350
351 BNAD_GET_REG(FCOE_FIP_ETH_TYPE);
352 BNAD_GET_REG(RESV_ETH_TYPE);
353
354 BNAD_GET_REG(HOSTFN2_INT_STATUS);
355 BNAD_GET_REG(HOSTFN2_INT_MASK);
356 BNAD_GET_REG(HOST_PAGE_NUM_FN2);
357 BNAD_GET_REG(HOST_MSIX_ERR_INDEX_FN2);
358 BNAD_GET_REG(FN2_PCIE_ERR_REG);
359 BNAD_GET_REG(FN2_ERR_TYPE_STATUS_REG);
360 BNAD_GET_REG(FN2_ERR_TYPE_MSK_STATUS_REG);
361
362 BNAD_GET_REG(HOSTFN3_INT_STATUS);
363 BNAD_GET_REG(HOSTFN3_INT_MASK);
364 BNAD_GET_REG(HOST_PAGE_NUM_FN3);
365 BNAD_GET_REG(HOST_MSIX_ERR_INDEX_FN3);
366 BNAD_GET_REG(FN3_PCIE_ERR_REG);
367 BNAD_GET_REG(FN3_ERR_TYPE_STATUS_REG);
368 BNAD_GET_REG(FN3_ERR_TYPE_MSK_STATUS_REG);
369
370 /* Host Command Status Registers */
371 reg_addr = HOST_CMDSTS0_CLR_REG;
372 for (i = 0; i < 16; i++) {
373 BNAD_GET_REG(reg_addr);
374 BNAD_GET_REG(reg_addr + 4);
375 BNAD_GET_REG(reg_addr + 8);
376 reg_addr += 0x10;
377 }
378
379 /* Function ID register */
380 BNAD_GET_REG(FNC_ID_REG);
381
382 /* Function personality register */
383 BNAD_GET_REG(FNC_PERS_REG);
384
385 /* Operation mode register */
386 BNAD_GET_REG(OP_MODE);
387
388 /* LPU0 Registers */
389 BNAD_GET_REG(LPU0_MBOX_CTL_REG);
390 BNAD_GET_REG(LPU0_MBOX_CMD_REG);
391 BNAD_GET_REG(LPU0_MBOX_LINK_0REG);
392 BNAD_GET_REG(LPU1_MBOX_LINK_0REG);
393 BNAD_GET_REG(LPU0_MBOX_STATUS_0REG);
394 BNAD_GET_REG(LPU1_MBOX_STATUS_0REG);
395 BNAD_GET_REG(LPU0_ERR_STATUS_REG);
396 BNAD_GET_REG(LPU0_ERR_SET_REG);
397
398 /* LPU1 Registers */
399 BNAD_GET_REG(LPU1_MBOX_CTL_REG);
400 BNAD_GET_REG(LPU1_MBOX_CMD_REG);
401 BNAD_GET_REG(LPU0_MBOX_LINK_1REG);
402 BNAD_GET_REG(LPU1_MBOX_LINK_1REG);
403 BNAD_GET_REG(LPU0_MBOX_STATUS_1REG);
404 BNAD_GET_REG(LPU1_MBOX_STATUS_1REG);
405 BNAD_GET_REG(LPU1_ERR_STATUS_REG);
406 BNAD_GET_REG(LPU1_ERR_SET_REG);
407
408 /* PSS Registers */
409 BNAD_GET_REG(PSS_CTL_REG);
410 BNAD_GET_REG(PSS_ERR_STATUS_REG);
411 BNAD_GET_REG(ERR_STATUS_SET);
412 BNAD_GET_REG(PSS_RAM_ERR_STATUS_REG);
413
414 /* Catapult CPQ Registers */
415 BNAD_GET_REG(HOSTFN0_LPU0_MBOX0_CMD_STAT);
416 BNAD_GET_REG(HOSTFN0_LPU1_MBOX0_CMD_STAT);
417 BNAD_GET_REG(LPU0_HOSTFN0_MBOX0_CMD_STAT);
418 BNAD_GET_REG(LPU1_HOSTFN0_MBOX0_CMD_STAT);
419
420 BNAD_GET_REG(HOSTFN0_LPU0_MBOX1_CMD_STAT);
421 BNAD_GET_REG(HOSTFN0_LPU1_MBOX1_CMD_STAT);
422 BNAD_GET_REG(LPU0_HOSTFN0_MBOX1_CMD_STAT);
423 BNAD_GET_REG(LPU1_HOSTFN0_MBOX1_CMD_STAT);
424
425 BNAD_GET_REG(HOSTFN1_LPU0_MBOX0_CMD_STAT);
426 BNAD_GET_REG(HOSTFN1_LPU1_MBOX0_CMD_STAT);
427 BNAD_GET_REG(LPU0_HOSTFN1_MBOX0_CMD_STAT);
428 BNAD_GET_REG(LPU1_HOSTFN1_MBOX0_CMD_STAT);
429
430 BNAD_GET_REG(HOSTFN1_LPU0_MBOX1_CMD_STAT);
431 BNAD_GET_REG(HOSTFN1_LPU1_MBOX1_CMD_STAT);
432 BNAD_GET_REG(LPU0_HOSTFN1_MBOX1_CMD_STAT);
433 BNAD_GET_REG(LPU1_HOSTFN1_MBOX1_CMD_STAT);
434
435 BNAD_GET_REG(HOSTFN2_LPU0_MBOX0_CMD_STAT);
436 BNAD_GET_REG(HOSTFN2_LPU1_MBOX0_CMD_STAT);
437 BNAD_GET_REG(LPU0_HOSTFN2_MBOX0_CMD_STAT);
438 BNAD_GET_REG(LPU1_HOSTFN2_MBOX0_CMD_STAT);
439
440 BNAD_GET_REG(HOSTFN2_LPU0_MBOX1_CMD_STAT);
441 BNAD_GET_REG(HOSTFN2_LPU1_MBOX1_CMD_STAT);
442 BNAD_GET_REG(LPU0_HOSTFN2_MBOX1_CMD_STAT);
443 BNAD_GET_REG(LPU1_HOSTFN2_MBOX1_CMD_STAT);
444
445 BNAD_GET_REG(HOSTFN3_LPU0_MBOX0_CMD_STAT);
446 BNAD_GET_REG(HOSTFN3_LPU1_MBOX0_CMD_STAT);
447 BNAD_GET_REG(LPU0_HOSTFN3_MBOX0_CMD_STAT);
448 BNAD_GET_REG(LPU1_HOSTFN3_MBOX0_CMD_STAT);
449
450 BNAD_GET_REG(HOSTFN3_LPU0_MBOX1_CMD_STAT);
451 BNAD_GET_REG(HOSTFN3_LPU1_MBOX1_CMD_STAT);
452 BNAD_GET_REG(LPU0_HOSTFN3_MBOX1_CMD_STAT);
453 BNAD_GET_REG(LPU1_HOSTFN3_MBOX1_CMD_STAT);
454
455 /* Host Function Force Parity Error Registers */
456 BNAD_GET_REG(HOSTFN0_LPU_FORCE_PERR);
457 BNAD_GET_REG(HOSTFN1_LPU_FORCE_PERR);
458 BNAD_GET_REG(HOSTFN2_LPU_FORCE_PERR);
459 BNAD_GET_REG(HOSTFN3_LPU_FORCE_PERR);
460
461 /* LL Port[0|1] Halt Mask Registers */
462 BNAD_GET_REG(LL_HALT_MSK_P0);
463 BNAD_GET_REG(LL_HALT_MSK_P1);
464
465 /* LL Port[0|1] Error Mask Registers */
466 BNAD_GET_REG(LL_ERR_MSK_P0);
467 BNAD_GET_REG(LL_ERR_MSK_P1);
468
469 /* EMC FLI Registers */
470 BNAD_GET_REG(FLI_CMD_REG);
471 BNAD_GET_REG(FLI_ADDR_REG);
472 BNAD_GET_REG(FLI_CTL_REG);
473 BNAD_GET_REG(FLI_WRDATA_REG);
474 BNAD_GET_REG(FLI_RDDATA_REG);
475 BNAD_GET_REG(FLI_DEV_STATUS_REG);
476 BNAD_GET_REG(FLI_SIG_WD_REG);
477
478 BNAD_GET_REG(FLI_DEV_VENDOR_REG);
479 BNAD_GET_REG(FLI_ERR_STATUS_REG);
480
481 /* RxAdm 0 Registers */
482 BNAD_GET_REG(RAD0_CTL_REG);
483 BNAD_GET_REG(RAD0_PE_PARM_REG);
484 BNAD_GET_REG(RAD0_BCN_REG);
485 BNAD_GET_REG(RAD0_DEFAULT_REG);
486 BNAD_GET_REG(RAD0_PROMISC_REG);
487 BNAD_GET_REG(RAD0_BCNQ_REG);
488 BNAD_GET_REG(RAD0_DEFAULTQ_REG);
489
490 BNAD_GET_REG(RAD0_ERR_STS);
491 BNAD_GET_REG(RAD0_SET_ERR_STS);
492 BNAD_GET_REG(RAD0_ERR_INT_EN);
493 BNAD_GET_REG(RAD0_FIRST_ERR);
494 BNAD_GET_REG(RAD0_FORCE_ERR);
495
496 BNAD_GET_REG(RAD0_MAC_MAN_1H);
497 BNAD_GET_REG(RAD0_MAC_MAN_1L);
498 BNAD_GET_REG(RAD0_MAC_MAN_2H);
499 BNAD_GET_REG(RAD0_MAC_MAN_2L);
500 BNAD_GET_REG(RAD0_MAC_MAN_3H);
501 BNAD_GET_REG(RAD0_MAC_MAN_3L);
502 BNAD_GET_REG(RAD0_MAC_MAN_4H);
503 BNAD_GET_REG(RAD0_MAC_MAN_4L);
504
505 BNAD_GET_REG(RAD0_LAST4_IP);
506
507 /* RxAdm 1 Registers */
508 BNAD_GET_REG(RAD1_CTL_REG);
509 BNAD_GET_REG(RAD1_PE_PARM_REG);
510 BNAD_GET_REG(RAD1_BCN_REG);
511 BNAD_GET_REG(RAD1_DEFAULT_REG);
512 BNAD_GET_REG(RAD1_PROMISC_REG);
513 BNAD_GET_REG(RAD1_BCNQ_REG);
514 BNAD_GET_REG(RAD1_DEFAULTQ_REG);
515
516 BNAD_GET_REG(RAD1_ERR_STS);
517 BNAD_GET_REG(RAD1_SET_ERR_STS);
518 BNAD_GET_REG(RAD1_ERR_INT_EN);
519
520 /* TxA0 Registers */
521 BNAD_GET_REG(TXA0_CTRL_REG);
522 /* TxA0 TSO Sequence # Registers (RO) */
523 for (i = 0; i < 8; i++) {
524 BNAD_GET_REG(TXA0_TSO_TCP_SEQ_REG(i));
525 BNAD_GET_REG(TXA0_TSO_IP_INFO_REG(i));
526 }
527
528 /* TxA1 Registers */
529 BNAD_GET_REG(TXA1_CTRL_REG);
530 /* TxA1 TSO Sequence # Registers (RO) */
531 for (i = 0; i < 8; i++) {
532 BNAD_GET_REG(TXA1_TSO_TCP_SEQ_REG(i));
533 BNAD_GET_REG(TXA1_TSO_IP_INFO_REG(i));
534 }
535
536 /* RxA Registers */
537 BNAD_GET_REG(RXA0_CTL_REG);
538 BNAD_GET_REG(RXA1_CTL_REG);
539
540 /* PLB0 Registers */
541 BNAD_GET_REG(PLB0_ECM_TIMER_REG);
542 BNAD_GET_REG(PLB0_RL_CTL);
543 for (i = 0; i < 8; i++)
544 BNAD_GET_REG(PLB0_RL_MAX_BC(i));
545 BNAD_GET_REG(PLB0_RL_TU_PRIO);
546 for (i = 0; i < 8; i++)
547 BNAD_GET_REG(PLB0_RL_BYTE_CNT(i));
548 BNAD_GET_REG(PLB0_RL_MIN_REG);
549 BNAD_GET_REG(PLB0_RL_MAX_REG);
550 BNAD_GET_REG(PLB0_EMS_ADD_REG);
551
552 /* PLB1 Registers */
553 BNAD_GET_REG(PLB1_ECM_TIMER_REG);
554 BNAD_GET_REG(PLB1_RL_CTL);
555 for (i = 0; i < 8; i++)
556 BNAD_GET_REG(PLB1_RL_MAX_BC(i));
557 BNAD_GET_REG(PLB1_RL_TU_PRIO);
558 for (i = 0; i < 8; i++)
559 BNAD_GET_REG(PLB1_RL_BYTE_CNT(i));
560 BNAD_GET_REG(PLB1_RL_MIN_REG);
561 BNAD_GET_REG(PLB1_RL_MAX_REG);
562 BNAD_GET_REG(PLB1_EMS_ADD_REG);
563
564 /* HQM Control Register */
565 BNAD_GET_REG(HQM0_CTL_REG);
566 BNAD_GET_REG(HQM0_RXQ_STOP_SEM);
567 BNAD_GET_REG(HQM0_TXQ_STOP_SEM);
568 BNAD_GET_REG(HQM1_CTL_REG);
569 BNAD_GET_REG(HQM1_RXQ_STOP_SEM);
570 BNAD_GET_REG(HQM1_TXQ_STOP_SEM);
571
572 /* LUT Registers */
573 BNAD_GET_REG(LUT0_ERR_STS);
574 BNAD_GET_REG(LUT0_SET_ERR_STS);
575 BNAD_GET_REG(LUT1_ERR_STS);
576 BNAD_GET_REG(LUT1_SET_ERR_STS);
577
578 /* TRC Registers */
579 BNAD_GET_REG(TRC_CTL_REG);
580 BNAD_GET_REG(TRC_MODS_REG);
581 BNAD_GET_REG(TRC_TRGC_REG);
582 BNAD_GET_REG(TRC_CNT1_REG);
583 BNAD_GET_REG(TRC_CNT2_REG);
584 BNAD_GET_REG(TRC_NXTS_REG);
585 BNAD_GET_REG(TRC_DIRR_REG);
586 for (i = 0; i < 10; i++)
587 BNAD_GET_REG(TRC_TRGM_REG(i));
588 for (i = 0; i < 10; i++)
589 BNAD_GET_REG(TRC_NXTM_REG(i));
590 for (i = 0; i < 10; i++)
591 BNAD_GET_REG(TRC_STRM_REG(i));
592
593 spin_unlock_irqrestore(&bnad->bna_lock, flags);
594#undef BNAD_GET_REG
595 return num;
596}
597static int
598bnad_get_regs_len(struct net_device *netdev)
599{
600 int ret = get_regs(netdev_priv(netdev), NULL) * sizeof(u32);
601 return ret;
602}
603
604static void
605bnad_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *buf)
606{
607 memset(buf, 0, bnad_get_regs_len(netdev));
608 get_regs(netdev_priv(netdev), buf);
609}
610
611static void
612bnad_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wolinfo)
613{
614 wolinfo->supported = 0;
615 wolinfo->wolopts = 0;
616}
617
618static int
619bnad_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coalesce)
620{
621 struct bnad *bnad = netdev_priv(netdev);
622 unsigned long flags;
623
624 /* Lock rqd. to access bnad->bna_lock */
625 spin_lock_irqsave(&bnad->bna_lock, flags);
626 coalesce->use_adaptive_rx_coalesce =
627 (bnad->cfg_flags & BNAD_CF_DIM_ENABLED) ? true : false;
628 spin_unlock_irqrestore(&bnad->bna_lock, flags);
629
630 coalesce->rx_coalesce_usecs = bnad->rx_coalescing_timeo *
631 BFI_COALESCING_TIMER_UNIT;
632 coalesce->tx_coalesce_usecs = bnad->tx_coalescing_timeo *
633 BFI_COALESCING_TIMER_UNIT;
634 coalesce->tx_max_coalesced_frames = BFI_TX_INTERPKT_COUNT;
635
636 return 0;
637}
638
639static int
640bnad_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coalesce)
641{
642 struct bnad *bnad = netdev_priv(netdev);
643 unsigned long flags;
644 int dim_timer_del = 0;
645
646 if (coalesce->rx_coalesce_usecs == 0 ||
647 coalesce->rx_coalesce_usecs >
648 BFI_MAX_COALESCING_TIMEO * BFI_COALESCING_TIMER_UNIT)
649 return -EINVAL;
650
651 if (coalesce->tx_coalesce_usecs == 0 ||
652 coalesce->tx_coalesce_usecs >
653 BFI_MAX_COALESCING_TIMEO * BFI_COALESCING_TIMER_UNIT)
654 return -EINVAL;
655
656 mutex_lock(&bnad->conf_mutex);
657 /*
658 * Do not need to store rx_coalesce_usecs here
659 * Every time DIM is disabled, we can get it from the
660 * stack.
661 */
662 spin_lock_irqsave(&bnad->bna_lock, flags);
663 if (coalesce->use_adaptive_rx_coalesce) {
664 if (!(bnad->cfg_flags & BNAD_CF_DIM_ENABLED)) {
665 bnad->cfg_flags |= BNAD_CF_DIM_ENABLED;
666 bnad_dim_timer_start(bnad);
667 }
668 } else {
669 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED) {
670 bnad->cfg_flags &= ~BNAD_CF_DIM_ENABLED;
671 dim_timer_del = bnad_dim_timer_running(bnad);
672 if (dim_timer_del) {
673 clear_bit(BNAD_RF_DIM_TIMER_RUNNING,
674 &bnad->run_flags);
675 spin_unlock_irqrestore(&bnad->bna_lock, flags);
676 del_timer_sync(&bnad->dim_timer);
677 spin_lock_irqsave(&bnad->bna_lock, flags);
678 }
679 bnad_rx_coalescing_timeo_set(bnad);
680 }
681 }
682 if (bnad->tx_coalescing_timeo != coalesce->tx_coalesce_usecs /
683 BFI_COALESCING_TIMER_UNIT) {
684 bnad->tx_coalescing_timeo = coalesce->tx_coalesce_usecs /
685 BFI_COALESCING_TIMER_UNIT;
686 bnad_tx_coalescing_timeo_set(bnad);
687 }
688
689 if (bnad->rx_coalescing_timeo != coalesce->rx_coalesce_usecs /
690 BFI_COALESCING_TIMER_UNIT) {
691 bnad->rx_coalescing_timeo = coalesce->rx_coalesce_usecs /
692 BFI_COALESCING_TIMER_UNIT;
693
694 if (!(bnad->cfg_flags & BNAD_CF_DIM_ENABLED))
695 bnad_rx_coalescing_timeo_set(bnad);
696
697 }
698
699 /* Add Tx Inter-pkt DMA count? */
700
701 spin_unlock_irqrestore(&bnad->bna_lock, flags);
702
703 mutex_unlock(&bnad->conf_mutex);
704 return 0;
705}
706
707static void
708bnad_get_ringparam(struct net_device *netdev,
709 struct ethtool_ringparam *ringparam)
710{
711 struct bnad *bnad = netdev_priv(netdev);
712
713 ringparam->rx_max_pending = BNAD_MAX_Q_DEPTH / bnad_rxqs_per_cq;
714 ringparam->rx_mini_max_pending = 0;
715 ringparam->rx_jumbo_max_pending = 0;
716 ringparam->tx_max_pending = BNAD_MAX_Q_DEPTH;
717
718 ringparam->rx_pending = bnad->rxq_depth;
719 ringparam->rx_mini_max_pending = 0;
720 ringparam->rx_jumbo_max_pending = 0;
721 ringparam->tx_pending = bnad->txq_depth;
722}
723
724static int
725bnad_set_ringparam(struct net_device *netdev,
726 struct ethtool_ringparam *ringparam)
727{
728 int i, current_err, err = 0;
729 struct bnad *bnad = netdev_priv(netdev);
730
731 mutex_lock(&bnad->conf_mutex);
732 if (ringparam->rx_pending == bnad->rxq_depth &&
733 ringparam->tx_pending == bnad->txq_depth) {
734 mutex_unlock(&bnad->conf_mutex);
735 return 0;
736 }
737
738 if (ringparam->rx_pending < BNAD_MIN_Q_DEPTH ||
739 ringparam->rx_pending > BNAD_MAX_Q_DEPTH / bnad_rxqs_per_cq ||
740 !BNA_POWER_OF_2(ringparam->rx_pending)) {
741 mutex_unlock(&bnad->conf_mutex);
742 return -EINVAL;
743 }
744 if (ringparam->tx_pending < BNAD_MIN_Q_DEPTH ||
745 ringparam->tx_pending > BNAD_MAX_Q_DEPTH ||
746 !BNA_POWER_OF_2(ringparam->tx_pending)) {
747 mutex_unlock(&bnad->conf_mutex);
748 return -EINVAL;
749 }
750
751 if (ringparam->rx_pending != bnad->rxq_depth) {
752 bnad->rxq_depth = ringparam->rx_pending;
753 for (i = 0; i < bnad->num_rx; i++) {
754 if (!bnad->rx_info[i].rx)
755 continue;
756 bnad_cleanup_rx(bnad, i);
757 current_err = bnad_setup_rx(bnad, i);
758 if (current_err && !err)
759 err = current_err;
760 }
761 }
762 if (ringparam->tx_pending != bnad->txq_depth) {
763 bnad->txq_depth = ringparam->tx_pending;
764 for (i = 0; i < bnad->num_tx; i++) {
765 if (!bnad->tx_info[i].tx)
766 continue;
767 bnad_cleanup_tx(bnad, i);
768 current_err = bnad_setup_tx(bnad, i);
769 if (current_err && !err)
770 err = current_err;
771 }
772 }
773
774 mutex_unlock(&bnad->conf_mutex);
775 return err;
776}
777
778static void
779bnad_get_pauseparam(struct net_device *netdev,
780 struct ethtool_pauseparam *pauseparam)
781{
782 struct bnad *bnad = netdev_priv(netdev);
783
784 pauseparam->autoneg = 0;
785 pauseparam->rx_pause = bnad->bna.port.pause_config.rx_pause;
786 pauseparam->tx_pause = bnad->bna.port.pause_config.tx_pause;
787}
788
789static int
790bnad_set_pauseparam(struct net_device *netdev,
791 struct ethtool_pauseparam *pauseparam)
792{
793 struct bnad *bnad = netdev_priv(netdev);
794 struct bna_pause_config pause_config;
795 unsigned long flags;
796
797 if (pauseparam->autoneg == AUTONEG_ENABLE)
798 return -EINVAL;
799
800 mutex_lock(&bnad->conf_mutex);
801 if (pauseparam->rx_pause != bnad->bna.port.pause_config.rx_pause ||
802 pauseparam->tx_pause != bnad->bna.port.pause_config.tx_pause) {
803 pause_config.rx_pause = pauseparam->rx_pause;
804 pause_config.tx_pause = pauseparam->tx_pause;
805 spin_lock_irqsave(&bnad->bna_lock, flags);
806 bna_port_pause_config(&bnad->bna.port, &pause_config, NULL);
807 spin_unlock_irqrestore(&bnad->bna_lock, flags);
808 }
809 mutex_unlock(&bnad->conf_mutex);
810 return 0;
811}
812
813static u32
814bnad_get_rx_csum(struct net_device *netdev)
815{
816 u32 rx_csum;
817 struct bnad *bnad = netdev_priv(netdev);
818
819 rx_csum = bnad->rx_csum;
820 return rx_csum;
821}
822
823static int
824bnad_set_rx_csum(struct net_device *netdev, u32 rx_csum)
825{
826 struct bnad *bnad = netdev_priv(netdev);
827
828 mutex_lock(&bnad->conf_mutex);
829 bnad->rx_csum = rx_csum;
830 mutex_unlock(&bnad->conf_mutex);
831 return 0;
832}
833
834static int
835bnad_set_tx_csum(struct net_device *netdev, u32 tx_csum)
836{
837 struct bnad *bnad = netdev_priv(netdev);
838
839 mutex_lock(&bnad->conf_mutex);
840 if (tx_csum) {
841 netdev->features |= NETIF_F_IP_CSUM;
842 netdev->features |= NETIF_F_IPV6_CSUM;
843 } else {
844 netdev->features &= ~NETIF_F_IP_CSUM;
845 netdev->features &= ~NETIF_F_IPV6_CSUM;
846 }
847 mutex_unlock(&bnad->conf_mutex);
848 return 0;
849}
850
851static int
852bnad_set_tso(struct net_device *netdev, u32 tso)
853{
854 struct bnad *bnad = netdev_priv(netdev);
855
856 mutex_lock(&bnad->conf_mutex);
857 if (tso) {
858 netdev->features |= NETIF_F_TSO;
859 netdev->features |= NETIF_F_TSO6;
860 } else {
861 netdev->features &= ~NETIF_F_TSO;
862 netdev->features &= ~NETIF_F_TSO6;
863 }
864 mutex_unlock(&bnad->conf_mutex);
865 return 0;
866}
867
868static void
869bnad_get_strings(struct net_device *netdev, u32 stringset, u8 * string)
870{
871 struct bnad *bnad = netdev_priv(netdev);
872 int i, j, q_num;
873 u64 bmap;
874
875 mutex_lock(&bnad->conf_mutex);
876
877 switch (stringset) {
878 case ETH_SS_STATS:
879 for (i = 0; i < BNAD_ETHTOOL_STATS_NUM; i++) {
880 BUG_ON(!(strlen(bnad_net_stats_strings[i]) <
881 ETH_GSTRING_LEN));
882 memcpy(string, bnad_net_stats_strings[i],
883 ETH_GSTRING_LEN);
884 string += ETH_GSTRING_LEN;
885 }
886 bmap = (u64)bnad->bna.tx_mod.txf_bmap[0] |
887 ((u64)bnad->bna.tx_mod.txf_bmap[1] << 32);
888 for (i = 0; bmap && (i < BFI_LL_TXF_ID_MAX); i++) {
889 if (bmap & 1) {
890 sprintf(string, "txf%d_ucast_octets", i);
891 string += ETH_GSTRING_LEN;
892 sprintf(string, "txf%d_ucast", i);
893 string += ETH_GSTRING_LEN;
894 sprintf(string, "txf%d_ucast_vlan", i);
895 string += ETH_GSTRING_LEN;
896 sprintf(string, "txf%d_mcast_octets", i);
897 string += ETH_GSTRING_LEN;
898 sprintf(string, "txf%d_mcast", i);
899 string += ETH_GSTRING_LEN;
900 sprintf(string, "txf%d_mcast_vlan", i);
901 string += ETH_GSTRING_LEN;
902 sprintf(string, "txf%d_bcast_octets", i);
903 string += ETH_GSTRING_LEN;
904 sprintf(string, "txf%d_bcast", i);
905 string += ETH_GSTRING_LEN;
906 sprintf(string, "txf%d_bcast_vlan", i);
907 string += ETH_GSTRING_LEN;
908 sprintf(string, "txf%d_errors", i);
909 string += ETH_GSTRING_LEN;
910 sprintf(string, "txf%d_filter_vlan", i);
911 string += ETH_GSTRING_LEN;
912 sprintf(string, "txf%d_filter_mac_sa", i);
913 string += ETH_GSTRING_LEN;
914 }
915 bmap >>= 1;
916 }
917
918 bmap = (u64)bnad->bna.rx_mod.rxf_bmap[0] |
919 ((u64)bnad->bna.rx_mod.rxf_bmap[1] << 32);
920 for (i = 0; bmap && (i < BFI_LL_RXF_ID_MAX); i++) {
921 if (bmap & 1) {
922 sprintf(string, "rxf%d_ucast_octets", i);
923 string += ETH_GSTRING_LEN;
924 sprintf(string, "rxf%d_ucast", i);
925 string += ETH_GSTRING_LEN;
926 sprintf(string, "rxf%d_ucast_vlan", i);
927 string += ETH_GSTRING_LEN;
928 sprintf(string, "rxf%d_mcast_octets", i);
929 string += ETH_GSTRING_LEN;
930 sprintf(string, "rxf%d_mcast", i);
931 string += ETH_GSTRING_LEN;
932 sprintf(string, "rxf%d_mcast_vlan", i);
933 string += ETH_GSTRING_LEN;
934 sprintf(string, "rxf%d_bcast_octets", i);
935 string += ETH_GSTRING_LEN;
936 sprintf(string, "rxf%d_bcast", i);
937 string += ETH_GSTRING_LEN;
938 sprintf(string, "rxf%d_bcast_vlan", i);
939 string += ETH_GSTRING_LEN;
940 sprintf(string, "rxf%d_frame_drops", i);
941 string += ETH_GSTRING_LEN;
942 }
943 bmap >>= 1;
944 }
945
946 q_num = 0;
947 for (i = 0; i < bnad->num_rx; i++) {
948 if (!bnad->rx_info[i].rx)
949 continue;
950 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
951 sprintf(string, "cq%d_producer_index", q_num);
952 string += ETH_GSTRING_LEN;
953 sprintf(string, "cq%d_consumer_index", q_num);
954 string += ETH_GSTRING_LEN;
955 sprintf(string, "cq%d_hw_producer_index",
956 q_num);
957 string += ETH_GSTRING_LEN;
958 q_num++;
959 }
960 }
961
962 q_num = 0;
963 for (i = 0; i < bnad->num_rx; i++) {
964 if (!bnad->rx_info[i].rx)
965 continue;
966 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
967 sprintf(string, "rxq%d_packets", q_num);
968 string += ETH_GSTRING_LEN;
969 sprintf(string, "rxq%d_bytes", q_num);
970 string += ETH_GSTRING_LEN;
971 sprintf(string, "rxq%d_packets_with_error",
972 q_num);
973 string += ETH_GSTRING_LEN;
974 sprintf(string, "rxq%d_allocbuf_failed", q_num);
975 string += ETH_GSTRING_LEN;
976 sprintf(string, "rxq%d_producer_index", q_num);
977 string += ETH_GSTRING_LEN;
978 sprintf(string, "rxq%d_consumer_index", q_num);
979 string += ETH_GSTRING_LEN;
980 q_num++;
981 if (bnad->rx_info[i].rx_ctrl[j].ccb &&
982 bnad->rx_info[i].rx_ctrl[j].ccb->
983 rcb[1] &&
984 bnad->rx_info[i].rx_ctrl[j].ccb->
985 rcb[1]->rxq) {
986 sprintf(string, "rxq%d_packets", q_num);
987 string += ETH_GSTRING_LEN;
988 sprintf(string, "rxq%d_bytes", q_num);
989 string += ETH_GSTRING_LEN;
990 sprintf(string,
991 "rxq%d_packets_with_error", q_num);
992 string += ETH_GSTRING_LEN;
993 sprintf(string, "rxq%d_allocbuf_failed",
994 q_num);
995 string += ETH_GSTRING_LEN;
996 sprintf(string, "rxq%d_producer_index",
997 q_num);
998 string += ETH_GSTRING_LEN;
999 sprintf(string, "rxq%d_consumer_index",
1000 q_num);
1001 string += ETH_GSTRING_LEN;
1002 q_num++;
1003 }
1004 }
1005 }
1006
1007 q_num = 0;
1008 for (i = 0; i < bnad->num_tx; i++) {
1009 if (!bnad->tx_info[i].tx)
1010 continue;
1011 for (j = 0; j < bnad->num_txq_per_tx; j++) {
1012 sprintf(string, "txq%d_packets", q_num);
1013 string += ETH_GSTRING_LEN;
1014 sprintf(string, "txq%d_bytes", q_num);
1015 string += ETH_GSTRING_LEN;
1016 sprintf(string, "txq%d_producer_index", q_num);
1017 string += ETH_GSTRING_LEN;
1018 sprintf(string, "txq%d_consumer_index", q_num);
1019 string += ETH_GSTRING_LEN;
1020 sprintf(string, "txq%d_hw_consumer_index",
1021 q_num);
1022 string += ETH_GSTRING_LEN;
1023 q_num++;
1024 }
1025 }
1026
1027 break;
1028
1029 default:
1030 break;
1031 }
1032
1033 mutex_unlock(&bnad->conf_mutex);
1034}
1035
1036static int
1037bnad_get_stats_count_locked(struct net_device *netdev)
1038{
1039 struct bnad *bnad = netdev_priv(netdev);
1040 int i, j, count, rxf_active_num = 0, txf_active_num = 0;
1041 u64 bmap;
1042
1043 bmap = (u64)bnad->bna.tx_mod.txf_bmap[0] |
1044 ((u64)bnad->bna.tx_mod.txf_bmap[1] << 32);
1045 for (i = 0; bmap && (i < BFI_LL_TXF_ID_MAX); i++) {
1046 if (bmap & 1)
1047 txf_active_num++;
1048 bmap >>= 1;
1049 }
1050 bmap = (u64)bnad->bna.rx_mod.rxf_bmap[0] |
1051 ((u64)bnad->bna.rx_mod.rxf_bmap[1] << 32);
1052 for (i = 0; bmap && (i < BFI_LL_RXF_ID_MAX); i++) {
1053 if (bmap & 1)
1054 rxf_active_num++;
1055 bmap >>= 1;
1056 }
1057 count = BNAD_ETHTOOL_STATS_NUM +
1058 txf_active_num * BNAD_NUM_TXF_COUNTERS +
1059 rxf_active_num * BNAD_NUM_RXF_COUNTERS;
1060
1061 for (i = 0; i < bnad->num_rx; i++) {
1062 if (!bnad->rx_info[i].rx)
1063 continue;
1064 count += bnad->num_rxp_per_rx * BNAD_NUM_CQ_COUNTERS;
1065 count += bnad->num_rxp_per_rx * BNAD_NUM_RXQ_COUNTERS;
1066 for (j = 0; j < bnad->num_rxp_per_rx; j++)
1067 if (bnad->rx_info[i].rx_ctrl[j].ccb &&
1068 bnad->rx_info[i].rx_ctrl[j].ccb->rcb[1] &&
1069 bnad->rx_info[i].rx_ctrl[j].ccb->rcb[1]->rxq)
1070 count += BNAD_NUM_RXQ_COUNTERS;
1071 }
1072
1073 for (i = 0; i < bnad->num_tx; i++) {
1074 if (!bnad->tx_info[i].tx)
1075 continue;
1076 count += bnad->num_txq_per_tx * BNAD_NUM_TXQ_COUNTERS;
1077 }
1078 return count;
1079}
1080
1081static int
1082bnad_per_q_stats_fill(struct bnad *bnad, u64 *buf, int bi)
1083{
1084 int i, j;
1085 struct bna_rcb *rcb = NULL;
1086 struct bna_tcb *tcb = NULL;
1087
1088 for (i = 0; i < bnad->num_rx; i++) {
1089 if (!bnad->rx_info[i].rx)
1090 continue;
1091 for (j = 0; j < bnad->num_rxp_per_rx; j++)
1092 if (bnad->rx_info[i].rx_ctrl[j].ccb &&
1093 bnad->rx_info[i].rx_ctrl[j].ccb->rcb[0] &&
1094 bnad->rx_info[i].rx_ctrl[j].ccb->rcb[0]->rxq) {
1095 buf[bi++] = bnad->rx_info[i].rx_ctrl[j].
1096 ccb->producer_index;
1097 buf[bi++] = 0; /* ccb->consumer_index */
1098 buf[bi++] = *(bnad->rx_info[i].rx_ctrl[j].
1099 ccb->hw_producer_index);
1100 }
1101 }
1102 for (i = 0; i < bnad->num_rx; i++) {
1103 if (!bnad->rx_info[i].rx)
1104 continue;
1105 for (j = 0; j < bnad->num_rxp_per_rx; j++)
1106 if (bnad->rx_info[i].rx_ctrl[j].ccb) {
1107 if (bnad->rx_info[i].rx_ctrl[j].ccb->rcb[0] &&
1108 bnad->rx_info[i].rx_ctrl[j].ccb->
1109 rcb[0]->rxq) {
1110 rcb = bnad->rx_info[i].rx_ctrl[j].
1111 ccb->rcb[0];
1112 buf[bi++] = rcb->rxq->rx_packets;
1113 buf[bi++] = rcb->rxq->rx_bytes;
1114 buf[bi++] = rcb->rxq->
1115 rx_packets_with_error;
1116 buf[bi++] = rcb->rxq->
1117 rxbuf_alloc_failed;
1118 buf[bi++] = rcb->producer_index;
1119 buf[bi++] = rcb->consumer_index;
1120 }
1121 if (bnad->rx_info[i].rx_ctrl[j].ccb->rcb[1] &&
1122 bnad->rx_info[i].rx_ctrl[j].ccb->
1123 rcb[1]->rxq) {
1124 rcb = bnad->rx_info[i].rx_ctrl[j].
1125 ccb->rcb[1];
1126 buf[bi++] = rcb->rxq->rx_packets;
1127 buf[bi++] = rcb->rxq->rx_bytes;
1128 buf[bi++] = rcb->rxq->
1129 rx_packets_with_error;
1130 buf[bi++] = rcb->rxq->
1131 rxbuf_alloc_failed;
1132 buf[bi++] = rcb->producer_index;
1133 buf[bi++] = rcb->consumer_index;
1134 }
1135 }
1136 }
1137
1138 for (i = 0; i < bnad->num_tx; i++) {
1139 if (!bnad->tx_info[i].tx)
1140 continue;
1141 for (j = 0; j < bnad->num_txq_per_tx; j++)
1142 if (bnad->tx_info[i].tcb[j] &&
1143 bnad->tx_info[i].tcb[j]->txq) {
1144 tcb = bnad->tx_info[i].tcb[j];
1145 buf[bi++] = tcb->txq->tx_packets;
1146 buf[bi++] = tcb->txq->tx_bytes;
1147 buf[bi++] = tcb->producer_index;
1148 buf[bi++] = tcb->consumer_index;
1149 buf[bi++] = *(tcb->hw_consumer_index);
1150 }
1151 }
1152
1153 return bi;
1154}
1155
1156static void
1157bnad_get_ethtool_stats(struct net_device *netdev, struct ethtool_stats *stats,
1158 u64 *buf)
1159{
1160 struct bnad *bnad = netdev_priv(netdev);
1161 int i, j, bi;
1162 unsigned long *net_stats, flags;
1163 u64 *stats64;
1164 u64 bmap;
1165
1166 mutex_lock(&bnad->conf_mutex);
1167 if (bnad_get_stats_count_locked(netdev) != stats->n_stats) {
1168 mutex_unlock(&bnad->conf_mutex);
1169 return;
1170 }
1171
1172 /*
1173 * Used bna_lock to sync reads from bna_stats, which is written
1174 * under the same lock
1175 */
1176 spin_lock_irqsave(&bnad->bna_lock, flags);
1177 bi = 0;
1178 memset(buf, 0, stats->n_stats * sizeof(u64));
1179 memset(&bnad->net_stats, 0, sizeof(struct net_device_stats));
1180
1181 bnad_netdev_qstats_fill(bnad);
1182 bnad_netdev_hwstats_fill(bnad);
1183
1184 /* Fill net_stats into ethtool buffers */
1185 net_stats = (unsigned long *)&bnad->net_stats;
1186 for (i = 0; i < sizeof(struct net_device_stats) / sizeof(unsigned long);
1187 i++)
1188 buf[bi++] = net_stats[i];
1189
1190 /* Fill driver stats into ethtool buffers */
1191 stats64 = (u64 *)&bnad->stats.drv_stats;
1192 for (i = 0; i < sizeof(struct bnad_drv_stats) / sizeof(u64); i++)
1193 buf[bi++] = stats64[i];
1194
1195 /* Fill hardware stats excluding the rxf/txf into ethtool bufs */
1196 stats64 = (u64 *) bnad->stats.bna_stats->hw_stats;
1197 for (i = 0;
1198 i < offsetof(struct bfi_ll_stats, rxf_stats[0]) / sizeof(u64);
1199 i++)
1200 buf[bi++] = stats64[i];
1201
1202 /* Fill txf stats into ethtool buffers */
1203 bmap = (u64)bnad->bna.tx_mod.txf_bmap[0] |
1204 ((u64)bnad->bna.tx_mod.txf_bmap[1] << 32);
1205 for (i = 0; bmap && (i < BFI_LL_TXF_ID_MAX); i++) {
1206 if (bmap & 1) {
1207 stats64 = (u64 *)&bnad->stats.bna_stats->
1208 hw_stats->txf_stats[i];
1209 for (j = 0; j < sizeof(struct bfi_ll_stats_txf) /
1210 sizeof(u64); j++)
1211 buf[bi++] = stats64[j];
1212 }
1213 bmap >>= 1;
1214 }
1215
1216 /* Fill rxf stats into ethtool buffers */
1217 bmap = (u64)bnad->bna.rx_mod.rxf_bmap[0] |
1218 ((u64)bnad->bna.rx_mod.rxf_bmap[1] << 32);
1219 for (i = 0; bmap && (i < BFI_LL_RXF_ID_MAX); i++) {
1220 if (bmap & 1) {
1221 stats64 = (u64 *)&bnad->stats.bna_stats->
1222 hw_stats->rxf_stats[i];
1223 for (j = 0; j < sizeof(struct bfi_ll_stats_rxf) /
1224 sizeof(u64); j++)
1225 buf[bi++] = stats64[j];
1226 }
1227 bmap >>= 1;
1228 }
1229
1230 /* Fill per Q stats into ethtool buffers */
1231 bi = bnad_per_q_stats_fill(bnad, buf, bi);
1232
1233 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1234
1235 mutex_unlock(&bnad->conf_mutex);
1236}
1237
1238static int
1239bnad_get_sset_count(struct net_device *netdev, int sset)
1240{
1241 switch (sset) {
1242 case ETH_SS_STATS:
1243 return bnad_get_stats_count_locked(netdev);
1244 default:
1245 return -EOPNOTSUPP;
1246 }
1247}
1248
1249static struct ethtool_ops bnad_ethtool_ops = {
1250 .get_settings = bnad_get_settings,
1251 .set_settings = bnad_set_settings,
1252 .get_drvinfo = bnad_get_drvinfo,
1253 .get_regs_len = bnad_get_regs_len,
1254 .get_regs = bnad_get_regs,
1255 .get_wol = bnad_get_wol,
1256 .get_link = ethtool_op_get_link,
1257 .get_coalesce = bnad_get_coalesce,
1258 .set_coalesce = bnad_set_coalesce,
1259 .get_ringparam = bnad_get_ringparam,
1260 .set_ringparam = bnad_set_ringparam,
1261 .get_pauseparam = bnad_get_pauseparam,
1262 .set_pauseparam = bnad_set_pauseparam,
1263 .get_rx_csum = bnad_get_rx_csum,
1264 .set_rx_csum = bnad_set_rx_csum,
1265 .get_tx_csum = ethtool_op_get_tx_csum,
1266 .set_tx_csum = bnad_set_tx_csum,
1267 .get_sg = ethtool_op_get_sg,
1268 .set_sg = ethtool_op_set_sg,
1269 .get_tso = ethtool_op_get_tso,
1270 .set_tso = bnad_set_tso,
1271 .get_flags = ethtool_op_get_flags,
1272 .set_flags = ethtool_op_set_flags,
1273 .get_strings = bnad_get_strings,
1274 .get_ethtool_stats = bnad_get_ethtool_stats,
1275 .get_sset_count = bnad_get_sset_count
1276};
1277
1278void
1279bnad_set_ethtool_ops(struct net_device *netdev)
1280{
1281 SET_ETHTOOL_OPS(netdev, &bnad_ethtool_ops);
1282}
diff --git a/drivers/net/bna/cna.h b/drivers/net/bna/cna.h
new file mode 100644
index 000000000000..bbd39dc65972
--- /dev/null
+++ b/drivers/net/bna/cna.h
@@ -0,0 +1,81 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2006-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18
19#ifndef __CNA_H__
20#define __CNA_H__
21
22#include <linux/version.h>
23#include <linux/kernel.h>
24#include <linux/types.h>
25#include <linux/pci.h>
26#include <linux/delay.h>
27#include <linux/bitops.h>
28#include <linux/timer.h>
29#include <linux/interrupt.h>
30#include <linux/if_ether.h>
31#include <asm/page.h>
32#include <asm/io.h>
33#include <asm/string.h>
34
35#include <linux/list.h>
36
37#define bfa_sm_fault(__mod, __event) do { \
38 pr_err("SM Assertion failure: %s: %d: event = %d", __FILE__, __LINE__, \
39 __event); \
40} while (0)
41
42extern char bfa_version[];
43
44#define CNA_FW_FILE_CT "ctfw_cna.bin"
45#define FC_SYMNAME_MAX 256 /*!< max name server symbolic name size */
46
47#pragma pack(1)
48
49#define MAC_ADDRLEN (6)
50typedef struct mac { u8 mac[MAC_ADDRLEN]; } mac_t;
51
52#pragma pack()
53
54#define bfa_q_first(_q) ((void *)(((struct list_head *) (_q))->next))
55#define bfa_q_next(_qe) (((struct list_head *) (_qe))->next)
56#define bfa_q_prev(_qe) (((struct list_head *) (_qe))->prev)
57
58/*
59 * bfa_q_qe_init - to initialize a queue element
60 */
61#define bfa_q_qe_init(_qe) { \
62 bfa_q_next(_qe) = (struct list_head *) NULL; \
63 bfa_q_prev(_qe) = (struct list_head *) NULL; \
64}
65
66/*
67 * bfa_q_deq - dequeue an element from head of the queue
68 */
69#define bfa_q_deq(_q, _qe) { \
70 if (!list_empty(_q)) { \
71 (*((struct list_head **) (_qe))) = bfa_q_next(_q); \
72 bfa_q_prev(bfa_q_next(*((struct list_head **) _qe))) = \
73 (struct list_head *) (_q); \
74 bfa_q_next(_q) = bfa_q_next(*((struct list_head **) _qe)); \
75 bfa_q_qe_init(*((struct list_head **) _qe)); \
76 } else { \
77 *((struct list_head **) (_qe)) = (struct list_head *) NULL; \
78 } \
79}
80
81#endif /* __CNA_H__ */
diff --git a/drivers/net/bna/cna_fwimg.c b/drivers/net/bna/cna_fwimg.c
new file mode 100644
index 000000000000..0bd1d3790a27
--- /dev/null
+++ b/drivers/net/bna/cna_fwimg.c
@@ -0,0 +1,64 @@
1/*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13/*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18#include <linux/firmware.h>
19#include "cna.h"
20
21const struct firmware *bfi_fw;
22static u32 *bfi_image_ct_cna;
23static u32 bfi_image_ct_cna_size;
24
25u32 *
26cna_read_firmware(struct pci_dev *pdev, u32 **bfi_image,
27 u32 *bfi_image_size, char *fw_name)
28{
29 const struct firmware *fw;
30
31 if (request_firmware(&fw, fw_name, &pdev->dev)) {
32 pr_alert("Can't locate firmware %s\n", fw_name);
33 goto error;
34 }
35
36 *bfi_image = (u32 *)fw->data;
37 *bfi_image_size = fw->size/sizeof(u32);
38 bfi_fw = fw;
39
40 return *bfi_image;
41error:
42 return NULL;
43}
44
45u32 *
46cna_get_firmware_buf(struct pci_dev *pdev)
47{
48 if (bfi_image_ct_cna_size == 0)
49 cna_read_firmware(pdev, &bfi_image_ct_cna,
50 &bfi_image_ct_cna_size, CNA_FW_FILE_CT);
51 return bfi_image_ct_cna;
52}
53
54u32 *
55bfa_cb_image_get_chunk(int type, u32 off)
56{
57 return (u32 *)(bfi_image_ct_cna + off);
58}
59
60u32
61bfa_cb_image_get_size(int type)
62{
63 return bfi_image_ct_cna_size;
64}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 09:11:09 -0500